Skip to content

Hotfix/pr comment permission 403#800

Closed
ADubeyAMD wants to merge 10 commits into
masterfrom
hotfix/pr-comment-permission-403
Closed

Hotfix/pr comment permission 403#800
ADubeyAMD wants to merge 10 commits into
masterfrom
hotfix/pr-comment-permission-403

Conversation

@ADubeyAMD

Copy link
Copy Markdown
Collaborator

No description provided.

@github-actions

github-actions Bot commented Jun 4, 2026

Copy link
Copy Markdown

🔍 Board Pre-Validation Report

❌ 32 board(s) failed pre-validation

Please fix the errors listed below before requesting a review.

1.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "ac701"
  • ✔️ board.xml: display_name = "Artix-7 AC701 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7a200tfbg676-2"
  • ✔️ part0_pins.xml: 197 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 16 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "ac701"
  • ✔️ xitem.json: infra.display = "Artix-7 AC701 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Artix-7 AC701 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — emc_preset
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "emb-plus-vpr-4616"
  • ✔️ board.xml: display_name = "Embedded+ Sapphire VPR-4616"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcve2302-sfva784-2MP-e-S"
  • ✔️ part0_pins.xml: 154 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 4 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "emb-plus-vpr-4616"
  • ✔️ xitem.json: infra.display = "Embedded+ Sapphire VPR-4616"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Embedded+ Sapphire VPR-4616"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "emb-plus-vpr-4616"
  • ✔️ board.xml: display_name = "Embedded+ Sapphire VPR-4616"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcve2302-sfva784-2MP-e-S"
  • ✔️ part0_pins.xml: 154 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 4 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "emb-plus-vpr-4616"
  • ✔️ xitem.json: infra.display = "Embedded+ Sapphire VPR-4616"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Embedded+ Sapphire VPR-4616"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "emb-plus-vpr-4616"
  • ✔️ board.xml: display_name = "Embedded+ Sapphire VPR-4616"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcve2302-sfva784-2MP-e-S"
  • ✔️ part0_pins.xml: 150 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 4 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "emb-plus-vpr-4616"
  • ✔️ xitem.json: infra.display = "Embedded+ Sapphire VPR-4616"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Embedded+ Sapphire VPR-4616"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k24c"
  • ✔️ board.xml: display_name = "Kria K24C SOM"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck24-ubva530-2LV-c"
  • ✔️ part0_pins.xml: 79 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k24c"
  • ✔️ xitem.json: infra.display = "Kria K24C SOM"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Kria K24C SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k24c"
  • ✔️ board.xml: display_name = "Kria K24C SOM"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck24-ubva530-2LV-c"
  • ✔️ part0_pins.xml: 79 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k24c"
  • ✔️ xitem.json: infra.display = "Kria K24C SOM"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Kria K24C SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ xitem.json: infra.revision "1.0" does not match board.xml <file_version> "1.1"
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k24c"
  • ✔️ board.xml: display_name = "Kria K24C SOM"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck24-ubva530-2LV-c"
  • ✔️ part0_pins.xml: 79 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k24c"
  • ✔️ xitem.json: infra.display = "Kria K24C SOM"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Kria K24C SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k24i"
  • ✔️ board.xml: display_name = "Kria K24I SOM"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck24-ubva530-2LVI-i"
  • ✔️ part0_pins.xml: 79 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k24i"
  • ✔️ xitem.json: infra.display = "Kria K24I SOM"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Kria K24I SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k24i"
  • ✔️ board.xml: display_name = "Kria K24I SOM"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck24-ubva530-2LVI-i"
  • ✔️ part0_pins.xml: 79 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k24i"
  • ✔️ xitem.json: infra.display = "Kria K24I SOM"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Kria K24I SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k26c"
  • ✔️ board.xml: display_name = "Kria K26C SOM"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k26c"
  • ✔️ xitem.json: infra.display = "Kria K26C SOM"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Kria K26C SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.3  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k26c"
  • ✔️ board.xml: display_name = "Kria K26C SOM"
  • ✔️ board.xml: <file_version> = 1.3
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k26c"
  • ✔️ xitem.json: infra.display = "Kria K26C SOM"
  • ✔️ xitem.json: infra.revision = "1.3"
  • ✔️ xitem.json: infra.description = "Kria K26C SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.3)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k26c"
  • ✔️ board.xml: display_name = "Kria K26C SOM"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k26c"
  • ✔️ xitem.json: infra.display = "Kria K26C SOM"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Kria K26C SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k26c"
  • ✔️ board.xml: display_name = "Kria K26C SOM"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k26c"
  • ✔️ xitem.json: infra.display = "Kria K26C SOM"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Kria K26C SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k26i"
  • ✔️ board.xml: display_name = "Kria K26I SOM"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck26-sfvc784-2LVI-i"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k26i"
  • ✔️ xitem.json: infra.display = "Kria K26i SOM"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Kria K26I SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.3  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k26i"
  • ✔️ board.xml: display_name = "Kria K26I SOM"
  • ✔️ board.xml: <file_version> = 1.3
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck26-sfvc784-2LVI-i"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k26i"
  • ✔️ xitem.json: infra.display = "Kria K26i SOM"
  • ✔️ xitem.json: infra.revision = "1.3"
  • ✔️ xitem.json: infra.description = "Kria K26I SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.3)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k26i"
  • ✔️ board.xml: display_name = "Kria K26I SOM"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck26-sfvc784-2LVI-i"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k26i"
  • ✔️ xitem.json: infra.display = "Kria K26i SOM"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Kria K26I SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "k26i"
  • ✔️ board.xml: display_name = "Kria K26I SOM"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck26-sfvc784-2LVI-i"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "k26i"
  • ✔️ xitem.json: infra.display = "Kria K26i SOM"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Kria K26I SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.6  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kc705"
  • ✔️ board.xml: display_name = "Kintex-7 KC705 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.6
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7k325tffg900-2"
  • ✔️ part0_pins.xml: 390 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 23 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kc705"
  • ✔️ xitem.json: infra.display = "Kintex-7 KC705 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.6"
  • ✔️ xitem.json: infra.description = "Kintex-7 KC705 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.6)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.7  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kc705"
  • ✔️ board.xml: display_name = "Kintex-7 KC705 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.7
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7k325tffg900-2"
  • ✔️ part0_pins.xml: 390 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 24 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kc705"
  • ✔️ xitem.json: infra.display = "Kintex-7 KC705 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.7"
  • ✔️ xitem.json: infra.description = "Kintex-7 KC705 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.7)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.6  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kcu105"
  • ✔️ board.xml: display_name = "Kintex-UltraScale KCU105 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.6
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcku040ffva1156e-2"
  • ✔️ part0_pins.xml: 458 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 21 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kcu105"
  • ✔️ xitem.json: infra.display = "Kintex-UltraScale KCU105 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.6"
  • ✔️ xitem.json: infra.description = "Kintex-UltraScale KCU105 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.6)

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — default_sysclk_300_preset, sysclk_125_preset, user_prog_clock_preset
1.7  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kcu105"
  • ✔️ board.xml: display_name = "Kintex-UltraScale KCU105 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.7
  • ✔️ board.xml: 2 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcku040ffva1156e-2"
  • ✔️ part0_pins.xml: 463 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 23 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kcu105"
  • ✔️ xitem.json: infra.display = "Kintex-UltraScale KCU105 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.7"
  • ✔️ xitem.json: infra.description = "Kintex-UltraScale KCU105 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.7)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kcu116"
  • ✔️ board.xml: display_name = "Kintex UltraScale+ KCU116 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcku5p-ffvb676-2-e"
  • ✔️ part0_pins.xml: 212 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 15 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kcu116"
  • ✔️ xitem.json: infra.display = "Kintex UltraScale+ KCU116 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Kintex UltraScale+ KCU116 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — default_250mhz_clk1_preset, default_250mhz_clk2_preset
1.5  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kcu116"
  • ✔️ board.xml: display_name = "Kintex UltraScale+ KCU116 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.5
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcku5p-ffvb676-2-e"
  • ✔️ part0_pins.xml: 212 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 16 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kcu116"
  • ✔️ xitem.json: infra.display = "Kintex UltraScale+ KCU116 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.5"
  • ✔️ xitem.json: infra.description = "Kintex UltraScale+ KCU116 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.5)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — default_250mhz_clk1_preset, default_250mhz_clk2_preset
1.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "KCU1500"
  • ✔️ board.xml: display_name = "Kintex UltraScale KCU1500 Acceleration Development Board"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcku115flvb2104e-2"
  • ✔️ part0_pins.xml: 566 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 15 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kcu1500"
  • ✔️ xitem.json: infra.display = "Kintex UltraScale KCU1500 Acceleration Development Board"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Kintex UltraScale KCU1500 Acceleration Development Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "KCU1500"
  • ✔️ board.xml: display_name = "Kintex UltraScale KCU1500 Acceleration Development Board"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcku115-flvb2104-2-e"
  • ✔️ part0_pins.xml: 563 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 15 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kcu1500"
  • ✔️ xitem.json: infra.display = "Kintex UltraScale KCU1500 Acceleration Development Board"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Kintex UltraScale KCU1500 Acceleration Development Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kd240_carrier"
  • ✔️ board.xml: display_name = "Drives Starter Kit Carrier"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 10 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kd240_carrier"
  • ✔️ xitem.json: infra.display = "Drives Starter Kit carrier card"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Drives Starter Kit carrier card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — clk_preset

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ board.xml: No found inside
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kd240_som"
  • ✔️ board.xml: display_name = "Kria KD240 Drives Starter Kit SOM"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck24-ubva530-2LV-c"
  • ✔️ part0_pins.xml: 79 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kd240_som"
  • ✔️ xitem.json: infra.display = "Kria KD240 Drives Starter Kit SOM"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Kria KD240 Drives Starter Kit SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kd240_som"
  • ✔️ board.xml: display_name = "Kria KD240 Drives Starter Kit SOM"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xck24-ubva530-2LV-c"
  • ✔️ part0_pins.xml: 79 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kd240_som"
  • ✔️ xitem.json: infra.display = "Kria KD240 Drives Starter Kit SOM"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Kria KD240 Drives Starter Kit SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ xitem.json: infra.revision "1.0" does not match board.xml <file_version> "1.1"
1.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kr260_carrier"
  • ✔️ board.xml: display_name = "Robotics Starter Kit Carrier"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 6 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kr260"
  • ✔️ xitem.json: infra.display = "Robotics Starter Kit carrier card"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Robotics Starter Kit carrier card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ board.xml: No found inside
1.1  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kr260_carrier"
  • ✔️ board.xml: display_name = "Robotics Starter Kit Carrier"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kr260"
  • ✔️ xitem.json: infra.display = "Robotics Starter Kit carrier card"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Robotics Starter Kit carrier card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ board.xml: No found inside
2.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kr260_carrier"
  • ✔️ board.xml: display_name = "Robotics Starter Kit Carrier"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kr260"
  • ✔️ xitem.json: infra.display = "Robotics Starter Kit carrier card"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Robotics Starter Kit carrier card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ board.xml: No found inside
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kr260_som"
  • ✔️ board.xml: display_name = "Kria KR260 Robotics Starter Kit SOM"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kr260_som"
  • ✔️ xitem.json: infra.display = "Kria KR260 Robotics Starter Kit SOM"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Kria KR260 Robotics Starter Kit SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kr260_som"
  • ✔️ board.xml: display_name = "Kria KR260 Robotics Starter Kit SOM"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kr260_som"
  • ✔️ xitem.json: infra.display = "Kria KR260 Robotics Starter Kit SOM"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Kria KR260 Robotics Starter Kit SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kr260_som"
  • ✔️ board.xml: display_name = "Kria KR260 Robotics Starter Kit SOM"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 205 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 1 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kr260_som"
  • ✔️ xitem.json: infra.display = "Kria KR260 Robotics Starter Kit SOM"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Kria KR260 Robotics Starter Kit SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.2  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kv260_carrier"
  • ✔️ board.xml: display_name = "Vision AI Starter Kit carrier card"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kv260_carrier"
  • ✔️ xitem.json: infra.display = "Vision AI Starter Kit carrier card"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Vision AI Starter Kit carrier card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — push_buttons_preset

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ board.xml: No found inside
1.3  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kv260_carrier"
  • ✔️ board.xml: display_name = "Vision AI Starter Kit carrier card"
  • ✔️ board.xml: <file_version> = 1.3
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kv260_carrier"
  • ✔️ xitem.json: infra.display = "Vision AI Starter Kit carrier card"
  • ✔️ xitem.json: infra.revision = "1.3"
  • ✔️ xitem.json: infra.description = "Vision AI Starter Kit carrier card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.3)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — push_buttons_preset

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ board.xml: No found inside
2.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kv260_carrier"
  • ✔️ board.xml: display_name = "Vision AI Starter Kit carrier card"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kv260_carrier"
  • ✔️ xitem.json: infra.display = "Vision AI Starter Kit carrier card"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Vision AI Starter Kit carrier card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — push_buttons_preset

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ board.xml: No found inside
1.2  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kv260_som"
  • ✔️ board.xml: display_name = "Kria KV260 Vision AI Starter Kit"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 39 pin(s) defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kv260_som"
  • ✔️ xitem.json: infra.display = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)

Errors — must be fixed before merge:

  • ❌ Missing required file: preset.xml
1.3  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kv260_som"
  • ✔️ board.xml: display_name = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ board.xml: <file_version> = 1.3
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 39 pin(s) defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kv260_som"
  • ✔️ xitem.json: infra.display = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ xitem.json: infra.revision = "1.3"
  • ✔️ xitem.json: infra.description = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.3)

Errors — must be fixed before merge:

  • ❌ Missing required file: preset.xml
1.4  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kv260_som"
  • ✔️ board.xml: display_name = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 39 pin(s) defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kv260_som"
  • ✔️ xitem.json: infra.display = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)

Errors — must be fixed before merge:

  • ❌ Missing required file: preset.xml
2.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "kv260_som"
  • ✔️ board.xml: display_name = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "XCK26-SFVC784-2LV-C"
  • ✔️ part0_pins.xml: 39 pin(s) defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "kv260_som"
  • ✔️ xitem.json: infra.display = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Kria KV260 Vision AI Starter Kit SOM"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)

Errors — must be fixed before merge:

  • ❌ Missing required file: preset.xml
1.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "leopardimaging"
  • ✔️ board.xml: name = "LI-IMX274MIPI-FMC"
  • ✔️ board.xml: display_name = "LI-IMX274MIPI-FMC V1.0"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 6 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "LI-IMX274MIPI-FMC"
  • ✔️ xitem.json: infra.display = "LI-IMX274MIPI-FMC V1.0"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "LI-IMX274MIPI-FMC V1.0"
  • ✔️ xitem.json: infra.company = "Leopardimaging"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ board.xml: No found inside
1.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "leopardimaging"
  • ✔️ board.xml: name = "LI-IMX274MIPI-FMC-Versal"
  • ✔️ board.xml: display_name = "LI-IMX274MIPI-FMC Versal"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 6 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "LI-IMX274MIPI-FMC-Versal"
  • ✔️ xitem.json: infra.display = "LI-IMX274MIPI-FMC Versal"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "LI-IMX274MIPI-FMC Versal"
  • ✔️ xitem.json: infra.company = "Leopardimaging"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ board.xml: No found inside
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "scu200"
  • ✔️ board.xml: display_name = "Spartan Ultrascale+ SCU200 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcsu200p-sbva1024-2-e"
  • ✔️ part0_pins.xml: 197 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "scu200"
  • ✔️ xitem.json: infra.display = "Spartan Ultrascale+ SCU200 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Spartan Ultrascale+ SCU200 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "scu35"
  • ✔️ board.xml: display_name = "Spartan UltraScale+ SCU35 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 3 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcsu35p-sbvb625-2-e"
  • ✔️ part0_pins.xml: 64 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "scu35"
  • ✔️ xitem.json: infra.display = "Spartan UltraScale+ SCU35 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Spartan UltraScale+ SCU35 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "scu35"
  • ✔️ board.xml: display_name = "Spartan UltraScale+ SCU35 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 3 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcsu35p-sbvb625-2-e"
  • ✔️ part0_pins.xml: 64 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "scu35"
  • ✔️ xitem.json: infra.display = "Spartan UltraScale+ SCU35 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Spartan UltraScale+ SCU35 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "SP701"
  • ✔️ board.xml: display_name = "Spartan-7 SP701 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7s100fgga676-2"
  • ✔️ part0_pins.xml: 71 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "sp701"
  • ✔️ xitem.json: infra.display = "Spartan-7 SP701 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Spartan-7 SP701 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — led_4bits_preset
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "SP701"
  • ✔️ board.xml: display_name = "Spartan-7 SP701 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7s100fgga676-2"
  • ✔️ part0_pins.xml: 119 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "sp701"
  • ✔️ xitem.json: infra.display = "Spartan-7 SP701 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Spartan-7 SP701 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — led_4bits_preset
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "v80"
  • ✔️ board.xml: display_name = "Alveo V80 Compute Accelerator Card"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcv80-lsva4737-2MHP-e-S"
  • ✔️ part0_pins.xml: 269 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 4 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "v80"
  • ✔️ xitem.json: infra.display = "Alveo V80 Compute Accelerator Card"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Alveo V80 Compute Accelerator Card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "v80"
  • ✔️ board.xml: display_name = "Alveo V80 Compute Accelerator Card"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcv80-lsva4737-2MHP-e-S"
  • ✔️ part0_pins.xml: 269 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 4 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "v80"
  • ✔️ xitem.json: infra.display = "Alveo V80 Compute Accelerator Card"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Alveo V80 Compute Accelerator Card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vc707"
  • ✔️ board.xml: display_name = "Virtex-7 VC707 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7vx485tffg1761-2"
  • ✔️ part0_pins.xml: 107 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 15 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vc707"
  • ✔️ xitem.json: infra.display = "Virtex-7 VC707 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Virtex-7 VC707 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.5  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vc707"
  • ✔️ board.xml: display_name = "Virtex-7 VC707 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.5
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7vx485tffg1761-2"
  • ✔️ part0_pins.xml: 107 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 16 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vc707"
  • ✔️ xitem.json: infra.display = "Virtex-7 VC707 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.5"
  • ✔️ xitem.json: infra.description = "Virtex-7 VC707 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.5)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.8  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vc709"
  • ✔️ board.xml: display_name = "Virtex-7 VC709 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.8
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7vx690tffg1761-2"
  • ✔️ part0_pins.xml: 133 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vc709"
  • ✔️ xitem.json: infra.display = "Virtex-7 VC709 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.8"
  • ✔️ xitem.json: infra.description = "Virtex-7 VC709 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.8)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.2  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 470 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.2"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.2)

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — dc_pl_gpio_preset, rs232_uart_preset, sysctlr_gpio_preset
3.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 472 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.0"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 474 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.1"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 474 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.2"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.3  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.3
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 474 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.3"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.3)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.4  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 474 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.3"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ xitem.json: infra.revision "3.3" does not match board.xml <file_version> "3.4"
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190_newl"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 472 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190_newl"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190_newl"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 472 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190_newl"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190_newl"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 474 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190_newl"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.3  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vck190_newl"
  • ✔️ board.xml: display_name = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ board.xml: <file_version> = 1.3
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvc1902-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 474 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vck190_newl"
  • ✔️ xitem.json: infra.display = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Versal VCK190 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ xitem.json: infra.revision "1.2" does not match board.xml <file_version> "1.3"
1.6  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu108"
  • ✔️ board.xml: display_name = "Virtex-UltraScale VCU108 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.6
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu095ffva2104e-2"
  • ✔️ part0_pins.xml: 591 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 36 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu108"
  • ✔️ xitem.json: infra.display = "Virtex-UltraScale VCU108 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.6"
  • ✔️ xitem.json: infra.description = "Virtex-UltraScale VCU108 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.6)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.7  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu108"
  • ✔️ board.xml: display_name = "Virtex-UltraScale VCU108 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.7
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu095ffva2104e-2"
  • ✔️ part0_pins.xml: 591 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 37 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu108"
  • ✔️ xitem.json: infra.display = "Virtex-UltraScale VCU108 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.7"
  • ✔️ xitem.json: infra.description = "Virtex-UltraScale VCU108 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.7)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu110"
  • ✔️ board.xml: display_name = "Virtex-UltraScale VCU110 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu190-flgc2104-2-e-es2"
  • ✔️ part0_pins.xml: 168 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu110"
  • ✔️ xitem.json: infra.display = "Virtex-UltraScale VCU110 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Virtex-UltraScale VCU110 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu118"
  • ✔️ board.xml: display_name = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu9p-flga2104-2L-e"
  • ✔️ part0_pins.xml: 381 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 25 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu118"
  • ✔️ xitem.json: infra.display = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.3  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu118"
  • ✔️ board.xml: display_name = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.3
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu9p-flga2104-2L-e"
  • ✔️ part0_pins.xml: 386 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 26 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu118"
  • ✔️ xitem.json: infra.display = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.3"
  • ✔️ xitem.json: infra.description = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.3)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu118"
  • ✔️ board.xml: display_name = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu9p-flga2104-2L-e"
  • ✔️ part0_pins.xml: 386 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 28 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu118"
  • ✔️ xitem.json: infra.display = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.4"
  • ✔️ xitem.json: infra.description = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.4)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu118"
  • ✔️ board.xml: display_name = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu9p-flga2104-2L-e"
  • ✔️ part0_pins.xml: 382 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 28 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu118"
  • ✔️ xitem.json: infra.display = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.0"
  • ✔️ xitem.json: infra.description = "Virtex UltraScale+ VCU118 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu128"
  • ✔️ board.xml: display_name = "Virtex Ultrascale+ HBM VCU128 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu37p-fsvh2892-2L-e"
  • ✔️ part0_pins.xml: 305 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 27 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu128"
  • ✔️ xitem.json: infra.display = "Virtex Ultrascale+ HBM VCU128 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Virtex Ultrascale+ HBM VCU128 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu128"
  • ✔️ board.xml: display_name = "Virtex Ultrascale+ HBM VCU128 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu37p-fsvh2892-2L-e"
  • ✔️ part0_pins.xml: 301 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 27 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu128"
  • ✔️ xitem.json: infra.display = "Virtex Ultrascale+ HBM VCU128 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Virtex Ultrascale+ HBM VCU128 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu129"
  • ✔️ board.xml: display_name = "Virtex Ultrascale+ 56G VCU129 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu29p-fsga2577-2L-e"
  • ✔️ part0_pins.xml: 191 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu129"
  • ✔️ xitem.json: infra.display = "Virtex Ultrascale+ 56G VCU129 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Virtex Ultrascale+ 56G VCU129 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vcu129"
  • ✔️ board.xml: display_name = "Virtex Ultrascale+ 56G VCU129 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu29p-fsga2577-2L-e"
  • ✔️ part0_pins.xml: 183 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu129"
  • ✔️ xitem.json: infra.display = "Virtex Ultrascale+ 56G VCU129 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Virtex Ultrascale+ 56G VCU129 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.3  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "VCU1525"
  • ✔️ board.xml: display_name = "Virtex UltraScale+ VCU1525 Acceleration Development Board"
  • ✔️ board.xml: <file_version> = 1.3
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvu9p-fsgd2104-2L-e"
  • ✔️ part0_pins.xml: 664 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vcu1525"
  • ✔️ xitem.json: infra.display = "Virtex UltraScale+ VCU1525 Acceleration Development Board"
  • ✔️ xitem.json: infra.revision = "1.3"
  • ✔️ xitem.json: infra.description = "Virtex UltraScale+ VCU1525 Acceleration Development Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.3)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vek280"
  • ✔️ board.xml: display_name = "Versal VEK280 Evaluation Platform with FMC Connector"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcve2802-vsvh1760-2MP-e-S"
  • ✔️ part0_pins.xml: 546 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vek280"
  • ✔️ xitem.json: infra.display = "Versal VEK280 Evaluation Platform with FMC Connector"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VEK280 Evaluation Platform with FMC Connector"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vek280"
  • ✔️ board.xml: display_name = "Versal VEK280 Evaluation Platform with FMC Connector"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcve2802-vsvh1760-2MP-e-S"
  • ✔️ part0_pins.xml: 546 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vek280"
  • ✔️ xitem.json: infra.display = "Versal VEK280 Evaluation Platform with FMC Connector"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Versal VEK280 Evaluation Platform with FMC Connector"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vek280"
  • ✔️ board.xml: display_name = "Versal VEK280 Evaluation Platform with FMC Connector"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcve2802-vsvh1760-2MP-e-S"
  • ✔️ part0_pins.xml: 546 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vek280"
  • ✔️ xitem.json: infra.display = "Versal VEK280 Evaluation Platform with FMC Connector"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Versal VEK280 Evaluation Platform with FMC Connector"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vek385"
  • ✔️ board.xml: display_name = "VEK385 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc2ve3858-ssva2112-2MP-e-S"
  • ✔️ part0_pins.xml: 338 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vek385"
  • ✔️ xitem.json: infra.display = "Versal VEK385 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VEK385 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vek385"
  • ✔️ board.xml: display_name = "VEK385 Evaluation Platform (Rev A)"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc2ve3858-ssva2112-2MP-e-S"
  • ✔️ part0_pins.xml: 338 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 15 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vek385"
  • ✔️ xitem.json: infra.display = "Versal VEK385 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Versal VEK385 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vek385_1"
  • ✔️ board.xml: display_name = "VEK385 Evaluation Platform (Rev B)"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc2ve3858-ssva2112-2MP-e-S"
  • ✔️ part0_pins.xml: 338 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 15 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vek385_1"
  • ✔️ xitem.json: infra.display = "Versal VEK385 Evaluation Platform (Rev B)"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VEK385 Evaluation Platform (Rev B)"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vermeo_t1_mpsoc"
  • ✔️ board.xml: display_name = "Vermeo T1 MPSoC Board"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu19eg-ffvd1760-2L-e"
  • ✔️ part0_pins.xml: 197 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vermeo_t1_mpsoc"
  • ✔️ xitem.json: infra.display = "Zynq Ultrascale+ MPSoC T1 Development Board"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Zynq Ultrascale+ MPSoC T1 Development Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vermeo_t1_mpsoc"
  • ✔️ board.xml: display_name = "Vermeo T1 MPSoC Board"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu19eg-ffvd1760-2L-e"
  • ✔️ part0_pins.xml: 197 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vermeo_t1_mpsoc"
  • ✔️ xitem.json: infra.display = "Zynq Ultrascale+ MPSoC T1 Development Board"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Zynq Ultrascale+ MPSoC T1 Development Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vermeo_t1_rfsoc"
  • ✔️ board.xml: display_name = "Vermeo T1 RFSoC Board"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu21dr-ffvd1156-2L-e"
  • ✔️ part0_pins.xml: 185 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vermeo_t1_rfsoc"
  • ✔️ xitem.json: infra.display = "Zynq Ultrascale+ RFSoC T1 Development Board"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Zynq Ultrascale+ RFSoC T1 Development Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vermeo_t1_rfsoc"
  • ✔️ board.xml: display_name = "Vermeo T1 RFSoC Board"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu21dr-ffvd1156-2L-e"
  • ✔️ part0_pins.xml: 185 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vermeo_t1_rfsoc"
  • ✔️ xitem.json: infra.display = "Zynq Ultrascale+ RFSoC T1 Development Board"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Zynq Ultrascale+ RFSoC T1 Development Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vhk158"
  • ✔️ board.xml: display_name = "Versal VHK158 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvh1582-vsva3697-2MP-e-S"
  • ✔️ part0_pins.xml: 350 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vhk158"
  • ✔️ xitem.json: infra.display = "Versal VHK158 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VHK158 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vhk158"
  • ✔️ board.xml: display_name = "Versal VHK158 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvh1582-vsva3697-2MP-e-S"
  • ✔️ part0_pins.xml: 350 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vhk158"
  • ✔️ xitem.json: infra.display = "Versal VHK158 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Versal VHK158 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.2  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vhk158"
  • ✔️ board.xml: display_name = "Versal VHK158 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvh1582-vsva3697-2MP-e-S"
  • ✔️ part0_pins.xml: 352 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vhk158"
  • ✔️ xitem.json: infra.display = "Versal VHK158 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Versal VHK158 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Errors — must be fixed before merge:

  • ❌ xitem.json: infra.revision "1.1" does not match board.xml <file_version> "1.2"
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vhk158"
  • ✔️ board.xml: display_name = "Versal VHK158 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvh1582-vsva3697-2MP-e-S"
  • ✔️ part0_pins.xml: 274 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vhk158"
  • ✔️ xitem.json: infra.display = "Versal VHK158 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Versal VHK158 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.2  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vmk180"
  • ✔️ board.xml: display_name = "Versal VMK180 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvm1802-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 470 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vmk180"
  • ✔️ xitem.json: infra.display = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.2"
  • ✔️ xitem.json: infra.description = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.2)

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — dc_pl_gpio_preset, rs232_uart_preset, sysctlr_gpio_preset
3.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vmk180"
  • ✔️ board.xml: display_name = "Versal VMK180 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvm1802-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 472 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vmk180"
  • ✔️ xitem.json: infra.display = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.0"
  • ✔️ xitem.json: infra.description = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.0)

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — dc_pl_gpio_preset, rs232_uart_preset, sysctlr_gpio_preset
3.1  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vmk180"
  • ✔️ board.xml: display_name = "Versal VMK180 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvm1802-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 474 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vmk180"
  • ✔️ xitem.json: infra.display = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.1"
  • ✔️ xitem.json: infra.description = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.1)

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — dc_pl_gpio_preset, rs232_uart_preset, sysctlr_gpio_preset
3.2  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vmk180"
  • ✔️ board.xml: display_name = "Versal VMK180 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvm1802-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 474 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vmk180"
  • ✔️ xitem.json: infra.display = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.2"
  • ✔️ xitem.json: infra.description = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.2)

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — dc_pl_gpio_preset, rs232_uart_preset, sysctlr_gpio_preset
3.3  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vmk180"
  • ✔️ board.xml: display_name = "Versal VMK180 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.3
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvm1802-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 474 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 17 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vmk180"
  • ✔️ xitem.json: infra.display = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.2"
  • ✔️ xitem.json: infra.description = "Versal VMK180 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"

Errors — must be fixed before merge:

  • ❌ xitem.json: infra.revision "3.2" does not match board.xml <file_version> "3.3"
  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — dc_pl_gpio_preset, rs232_uart_preset, sysctlr_gpio_preset
1.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vmk180_newl"
  • ✔️ board.xml: display_name = "Versal VMK180 Evaluation Platform with New SD Level Shifter"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvm1802-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 472 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vmk180_newl"
  • ✔️ xitem.json: infra.display = "Versal VMK180 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VMK180 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — dc_pl_gpio_preset, rs232_uart_preset, sysctlr_gpio_preset
1.1  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vmk180_newl"
  • ✔️ board.xml: display_name = "Versal VMK180 Evaluation Platform with New SD Level Shifter"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvm1802-vsva2197-2MP-e-S"
  • ✔️ part0_pins.xml: 472 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vmk180_newl"
  • ✔️ xitem.json: infra.display = "Versal VMK180 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Versal VMK180 Evaluation Platform with New SD Level Shifter"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — dc_pl_gpio_preset, rs232_uart_preset, sysctlr_gpio_preset
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vpk120"
  • ✔️ board.xml: display_name = "Versal VPK120 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvp1202-vsva2785-2MP-e-S"
  • ✔️ part0_pins.xml: 478 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vpk120"
  • ✔️ xitem.json: infra.display = "Versal VPK120 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VPK120 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vpk120"
  • ✔️ board.xml: display_name = "Versal VPK120 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvp1202-vsva2785-2MP-e-S"
  • ✔️ part0_pins.xml: 478 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vpk120"
  • ✔️ xitem.json: infra.display = "Versal VPK120 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Versal VPK120 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vpk120"
  • ✔️ board.xml: display_name = "Versal VPK120 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvp1202-vsva2785-2MP-e-S"
  • ✔️ part0_pins.xml: 478 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vpk120"
  • ✔️ xitem.json: infra.display = "Versal VPK120 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Versal VPK120 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vpk120"
  • ✔️ board.xml: display_name = "Versal VPK120 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvp1202-vsva2785-2MP-e-S"
  • ✔️ part0_pins.xml: 426 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vpk120"
  • ✔️ xitem.json: infra.display = "Versal VPK120 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Versal VPK120 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vpk180"
  • ✔️ board.xml: display_name = "Versal VPK180 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvp1802-lsvc4072-2MP-e-S"
  • ✔️ part0_pins.xml: 450 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vpk180"
  • ✔️ xitem.json: infra.display = "Versal VPK180 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VPK180 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vpk180"
  • ✔️ board.xml: display_name = "Versal VPK180 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvp1802-lsvc4072-2MP-e-S"
  • ✔️ part0_pins.xml: 450 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vpk180"
  • ✔️ xitem.json: infra.display = "Versal VPK180 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Versal VPK180 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vpk180"
  • ✔️ board.xml: display_name = "Versal VPK180 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvp1802-lsvc4072-2MP-e-S"
  • ✔️ part0_pins.xml: 450 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vpk180"
  • ✔️ xitem.json: infra.display = "Versal VPK180 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Versal VPK180 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vpk180"
  • ✔️ board.xml: display_name = "Versal VPK180 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvp1802-lsvc4072-2MP-e-S"
  • ✔️ part0_pins.xml: 426 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 8 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vpk180"
  • ✔️ xitem.json: infra.display = "Versal VPK180 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Versal VPK180 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vpk360"
  • ✔️ board.xml: display_name = "VPK360 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc2vp3602-vsvc3340-2MP-e-S"
  • ✔️ part0_pins.xml: 345 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 15 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vpk360"
  • ✔️ xitem.json: infra.display = "Versal VPK360 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VPK360 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vrk160"
  • ✔️ board.xml: display_name = "VRK160 ES1 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvr1602-vsva2488-2MP-e-S-es1"
  • ✔️ part0_pins.xml: 290 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vrk160"
  • ✔️ xitem.json: infra.display = "Versal VRK160 ES1 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VRK160 ES1 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vrk160"
  • ✔️ board.xml: display_name = "VRK160 ES1 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvr1602-vsva2488-2MP-e-S-es1"
  • ✔️ part0_pins.xml: 290 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vrk160"
  • ✔️ xitem.json: infra.display = "Versal VRK160 ES1 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Versal VRK160 ES1 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vrk160"
  • ✔️ board.xml: display_name = "VRK160 ES1 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvr1602-vsva2488-2MP-e-S-es1"
  • ✔️ part0_pins.xml: 290 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vrk160"
  • ✔️ xitem.json: infra.display = "Versal VRK160 ES1 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Versal VRK160 ES1 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "vrk165_es"
  • ✔️ board.xml: display_name = "VRK165 ES1 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xcvr1652-vsva2488-2MP-e-S-es1"
  • ✔️ part0_pins.xml: 290 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "vrk165"
  • ✔️ xitem.json: infra.display = "Versal VRK165 ES1 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Versal VRK165 ES1 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx"
  • ✔️ board.xml: name = "xm105"
  • ✔️ board.xml: display_name = "FMC XM105 Debug Card"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "xm105"
  • ✔️ xitem.json: infra.display = "FMC XM105 Debug Card"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "FMC XM105 Debug Card"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)

Errors — must be fixed before merge:

  • ❌ Missing required file: part0_pins.xml
  • ❌ Missing required file: preset.xml
  • ❌ board.xml: Missing <compatible_board_revisions> element
  • ❌ board.xml: No found inside
1.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zc702"
  • ✔️ board.xml: display_name = "Zynq 7000 ZC702 Evaluation Board"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7z020clg484-1"
  • ✔️ part0_pins.xml: 156 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 4 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zc702"
  • ✔️ xitem.json: infra.display = "Zynq 7000 ZC702 Evaluation Board"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Zynq 7000 ZC702 Evaluation Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zc706"
  • ✔️ board.xml: display_name = "Zynq 7000 ZC706 Evaluation Board"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7z045ffg900-2"
  • ✔️ part0_pins.xml: 212 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "ZC706"
  • ✔️ xitem.json: infra.display = "Zynq 7000 ZC706 Evaluation Board"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Zynq 7000 ZC706 Evaluation Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — sfp_preset, sfp_sgmii_preset, sma_sfp_preset, sma_sgmii_preset, sys_diff_clk_preset
1.5  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zc706"
  • ✔️ board.xml: display_name = "Zynq 7000 ZC706 Evaluation Board"
  • ✔️ board.xml: <file_version> = 1.5
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xc7z045ffg900-2"
  • ✔️ part0_pins.xml: 212 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 12 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "ZC706"
  • ✔️ xitem.json: infra.display = "Zynq 7000 ZC706 Evaluation Board"
  • ✔️ xitem.json: infra.revision = "1.5"
  • ✔️ xitem.json: infra.description = "Zynq 7000 ZC706 Evaluation Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.5)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — sfp_preset, sfp_sgmii_preset, sma_sfp_preset, sma_sgmii_preset, sys_diff_clk_preset
3.3  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu102"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU102 Evaluation Board"
  • ✔️ board.xml: <file_version> = 3.3
  • ✔️ board.xml: 2 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu9eg-ffvb1156-2-e"
  • ✔️ part0_pins.xml: 291 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 6 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu102"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU102 Evaluation Board"
  • ✔️ xitem.json: infra.revision = "3.3"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU102 Evaluation Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.3)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu102"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU102 Evaluation Board"
  • ✔️ board.xml: <file_version> = 3.4
  • ✔️ board.xml: 2 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu9eg-ffvb1156-2-e"
  • ✔️ part0_pins.xml: 291 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu102"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU102 Evaluation Board"
  • ✔️ xitem.json: infra.revision = "3.4"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU102 Evaluation Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.4)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.1  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu104"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU104 Evaluation Board"
  • ✔️ board.xml: <file_version> = 1.1
  • ✔️ board.xml: 3 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu7ev-ffvc1156-2-e"
  • ✔️ part0_pins.xml: 210 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 6 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu104"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU104 Evaluation Board"
  • ✔️ xitem.json: infra.revision = "1.1"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU104 Evaluation Board"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.1)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu106"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU106 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.4
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu7ev-ffvc1156-2-e"
  • ✔️ part0_pins.xml: 314 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu106"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU106 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.4"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU106 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.4)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — pciex8_preset
2.5  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu106"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU106 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.5
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu7ev-ffvc1156-2-e"
  • ✔️ part0_pins.xml: 324 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu106"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU106 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.5"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU106 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.5)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — pciex8_preset
2.6  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu106"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU106 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.6
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu7ev-ffvc1156-2-e"
  • ✔️ part0_pins.xml: 324 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 14 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu106"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU106 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.6"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU106 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.6)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — pciex8_preset
1.2  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu111"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.2
  • ✔️ board.xml: 3 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu28dr-ffvg1517-2-e"
  • ✔️ part0_pins.xml: 152 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 6 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu111"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.2"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.2)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.3  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu111"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.3
  • ✔️ board.xml: 3 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu28dr-ffvg1517-2-e"
  • ✔️ part0_pins.xml: 152 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 7 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu111"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.3"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.3)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.4  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu111"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 1.4
  • ✔️ board.xml: 3 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu28dr-ffvg1517-2-e"
  • ✔️ part0_pins.xml: 168 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu111"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.4"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.4)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu111"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 3 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu28dr-ffvg1517-2-e"
  • ✔️ part0_pins.xml: 168 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu111"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU111 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu1275"
  • ✔️ board.xml: display_name = "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu29dr-ffvf1760-2-e"
  • ✔️ part0_pins.xml: 18 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 5 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu1275"
  • ✔️ xitem.json: infra.display = "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — push_buttons_5bits_preset, uart2_PL_preset

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — uart2_pl_preset
2.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu1275"
  • ✔️ board.xml: display_name = "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu29dr-ffvf1760-2-e"
  • ✔️ part0_pins.xml: 18 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 4 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu1275"
  • ✔️ xitem.json: infra.display = "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — uart2_PL_preset

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — uart2_pl_preset
1.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu1285"
  • ✔️ board.xml: display_name = "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu39dr-ffvf1760-2-i"
  • ✔️ part0_pins.xml: 18 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 5 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu1285"
  • ✔️ xitem.json: infra.display = "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — push_buttons_5bits_preset, uart2_PL_preset

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — uart2_pl_preset
2.0  —  ❌ Failed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu1285"
  • ✔️ board.xml: display_name = "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu39dr-ffvf1760-2-i"
  • ✔️ part0_pins.xml: 18 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 4 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu1285"
  • ✔️ xitem.json: infra.display = "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)

Warnings:

  • ⚠️ preset.xml: Preset(s) not referenced by any board.xml interface — uart2_PL_preset

Errors — must be fixed before merge:

  • ❌ board.xml: Interface preset_proc reference(s) not defined in preset.xml — uart2_pl_preset
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu208"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu48dr-fsvg1517-2-e"
  • ✔️ part0_pins.xml: 198 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu208"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU208 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU208 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu208"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit"
  • ✔️ board.xml: <file_version> = 3.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu48dr-fsvg1517-2-e"
  • ✔️ part0_pins.xml: 190 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu208"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU208 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU208 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu208ld"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ RFSoC ZCU208-LD Evaluation Kit"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu58dr-fsvg1517-2-i-"
  • ✔️ part0_pins.xml: 198 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu208ld"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU208-LD Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU208-LD Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu208ld"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ RFSoC ZCU208-LD Evaluation Kit"
  • ✔️ board.xml: <file_version> = 3.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu58dr-fsvg1517-2-i"
  • ✔️ part0_pins.xml: 190 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu208ld"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU208-LD Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU208-LD Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu216"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU216 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu49dr-ffvf1760-2-e"
  • ✔️ part0_pins.xml: 214 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu216"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU216 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU216 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu216"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU216 Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu49dr-ffvf1760-2-e"
  • ✔️ part0_pins.xml: 206 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 13 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu216"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU216 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU216 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu216ld"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU216-LD Evaluation Platform"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu59dr-ffvf1760-2-i"
  • ✔️ part0_pins.xml: 214 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu216ld"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU216-LD Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU216-LD Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu216ld"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ ZCU216-LD Evaluation Platform"
  • ✔️ board.xml: <file_version> = 3.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu59dr-ffvf1760-2-i"
  • ✔️ part0_pins.xml: 206 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 11 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu216ld"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU216-LD Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU216-LD Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu670"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ RFSoC ZCU670 Evaluation Kit"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu67dr-fsve1156-2-i"
  • ✔️ part0_pins.xml: 109 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu670"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU670 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU670 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
3.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu670"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ RFSoC ZCU670 Evaluation Kit"
  • ✔️ board.xml: <file_version> = 3.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu67dr-fsve1156-2-i"
  • ✔️ part0_pins.xml: 109 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu670"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU670 Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "3.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU670 Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (3.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
1.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu670ld"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ RFSoC ZCU670-LD Evaluation Kit"
  • ✔️ board.xml: <file_version> = 1.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu57dr-fsve1156-2-i"
  • ✔️ part0_pins.xml: 109 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu670ld"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU670-LD Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "1.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU670-LD Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (1.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml
2.0  —  ✅ Passed

Passed checks:

  • ✔️ Required file present: board.xml
  • ✔️ Required file present: part0_pins.xml
  • ✔️ Required file present: preset.xml
  • ✔️ board.xml: Well-formed XML
  • ✔️ board.xml: Root element is
  • ✔️ board.xml: vendor = "xilinx.com"
  • ✔️ board.xml: name = "zcu670ld"
  • ✔️ board.xml: display_name = "Zynq UltraScale+ RFSoC ZCU670-LD Evaluation Kit"
  • ✔️ board.xml: <file_version> = 2.0
  • ✔️ board.xml: 1 compatible board revision(s) declared
  • ✔️ board.xml: 1 FPGA component(s) declared
  • ✔️ part0_pins.xml: Well-formed XML
  • ✔️ part0_pins.xml: Root element is <part_info>
  • ✔️ part0_pins.xml: part_name = "xczu57dr-fsve1156-2-i"
  • ✔️ part0_pins.xml: 109 pin(s) defined
  • ✔️ preset.xml: Well-formed XML
  • ✔️ preset.xml: Root element is <ip_presets>
  • ✔️ preset.xml: 9 preset entry/entries defined
  • ✔️ xitem.json: Valid JSON
  • ✔️ xitem.json: '_major' = 1
  • ✔️ xitem.json: '_minor' = 0
  • ✔️ xitem.json: infra.name = "zcu670ld"
  • ✔️ xitem.json: infra.display = "Zynq UltraScale+ ZCU670-LD Evaluation Platform"
  • ✔️ xitem.json: infra.revision = "2.0"
  • ✔️ xitem.json: infra.description = "Zynq UltraScale+ ZCU670-LD Evaluation Platform"
  • ✔️ xitem.json: infra.company = "xilinx.com"
  • ✔️ xitem.json: infra.revision matches board.xml <file_version> (2.0)
  • ✔️ Cross-check: preset_proc references are consistent between board.xml and preset.xml

Generated by board_validator_basic.py — AMD/Xilinx Board Store CI

@ADubeyAMD ADubeyAMD closed this Jun 8, 2026
@ADubeyAMD ADubeyAMD deleted the hotfix/pr-comment-permission-403 branch June 9, 2026 09:25
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants