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Pull requests: Xilinx/RapidWright

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Pull requests list

[Params] Adds parameters to control how readable EDIF is extracted when DCP is loaded
#1374 opened Jun 2, 2026 by clavin-xlnx Member Loading…
Enumerate Versal Delay Paths [No timing information]
#1371 opened May 21, 2026 by clavin-xlnx Member • Draft
WIP - enable {dis,}connectNet() to operate on macro port insts
#1367 opened May 5, 2026 by clavin-xlnx Member • Draft
2025.2.2
#1366 opened Apr 28, 2026 by clavin-xlnx Member • Draft
Add backward routing for RapidWright.
#1346 opened Jan 7, 2026 by kylepham-amd Contributor • Draft
9
Initial method to resolve hold time violations on ArrayBuilder designs
#1334 opened Dec 5, 2025 by abutt-amd Collaborator • Draft
Fix DesignTools.getConnectionPips for sinks driven by lut constant generators
#1231 opened Jun 20, 2025 by reillymck Contributor Loading…
5
Example Clock Signal Tracer
#1216 opened Jun 12, 2025 by clavin-xlnx Member • Draft
[TestExamples] Test PipelineGenerator with Vivado
#1193 opened May 20, 2025 by eddieh-xlnx Collaborator • Draft
Array Builder Tool - Replicate Optimized Kernels in an Array
#1163 opened Apr 10, 2025 by clavin-xlnx Member • Draft
2
[EDIFNetlist] exportEDIF() to use getLibrariesInExportOrder()
#1148 opened Feb 14, 2025 by eddieh-xlnx Collaborator • Draft
1
[DREAMPlaceFPGA] Add placeDesign() wrapper for DREAMPlaceFPGA
#1137 opened Jan 13, 2025 by eddieh-xlnx Collaborator • Draft
1
[RWRoute] Adjust wire base costs + cross SLR estimates
#1030 opened Jul 12, 2024 by eddieh-xlnx Collaborator • Draft
1
[Interchange] Exports DeviceResources Routing (Wires and Nodes) Info in Multiple Messages
#1017 opened Jun 25, 2024 by clavin-xlnx Member Loading…
Adding shape support for DREAMPlaceFPGA inputs and Interchange Netlist
#1011 opened Jun 21, 2024 by clavin-xlnx Member Loading…
3
[TestDeviceResources] Test/verify xcau10p
#1004 opened Jun 13, 2024 by eddieh-xlnx Collaborator • Draft
Node.getAllWiresInNode() returns empty list when Vivado doesn't bug
#1002 opened Jun 12, 2024 by eddieh-xlnx Collaborator • Draft
@clavin-xlnx
2
[DeviceResourcesWriter] Output resource timings for US+
#1001 opened Jun 12, 2024 by eddieh-xlnx Collaborator • Draft
5
Adds a tieoff method for module instances with unconnected inputs
#811 opened Sep 7, 2023 by clavin-xlnx Member Loading…
6
Draft approach for running tutorials in JUnit tests
#773 opened Jul 27, 2023 by clavin-xlnx Member • Draft
Add flag to filter static sources
#771 opened Jul 27, 2023 by clavin-xlnx Member Loading…
Create phys nets from logical
#770 opened Jul 26, 2023 by haydenc-amd Contributor Loading…
19
Inconsistent behaviour for Cell.getSitePinFromLogicalPin() bug
#473 opened Jul 14, 2022 by eddieh-xlnx Collaborator • Draft
6
ProTip! Exclude everything labeled bug with -label:bug.