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Design Space Exploration Methods - Max's Blog

/2022/12/31/DSE/

Gitalk

Status: Open.

#13 In VVViy/VVViy.github.io;

· VVViy opened on Mar 2, 2023

All-In-One Platform for Chip Design - Max's Blog

/2022/07/26/IC-platform/

Gitalk

Status: Open.

#12 In VVViy/VVViy.github.io;

· VVViy opened on Jul 29, 2022

致歉 - Max's Blog

/2022/07/22/Apology/

Gitalk

Status: Open.

#11 In VVViy/VVViy.github.io;

· VVViy opened on Jul 28, 2022

博客复更 - Max's Blog

/2020/04/06/recover/

Gitalk

Status: Open.

#10 In VVViy/VVViy.github.io;

· VVViy opened on Apr 6, 2020

create the NVDLA IP for the nv_small with Vivado and manage the connections with the Zynq UltraScale

Status: Open.

#9 In VVViy/VVViy.github.io;

· ghost opened on Jan 15, 2019

NVDLA HW Source Code Analysis - Max's Blog

/2019/01/11/NVDLA-Source-Code-Analysis/

Gitalk

Status: Open.

#8 In VVViy/VVViy.github.io;

· VVViy opened on Jan 14, 2019

Learning Chisel and Scala - Max's Blog

/2018/12/12/Learning-Chisel-and-Scala-Part-II/

Gitalk

Status: Open.

#7 In VVViy/VVViy.github.io;

· VVViy opened on Dec 13, 2018

Learning Chisel and Scala - Max's Blog

/2018/12/01/Learning-Chisel-and-Scala-Part-I/

Gitalk

Status: Open.

#6 In VVViy/VVViy.github.io;

· VVViy opened on Dec 1, 2018

Git - Max's Blog

/2017/02/15/Git-CMD/

Gitalk

Status: Open.

#5 In VVViy/VVViy.github.io;

· VVViy opened on Oct 18, 2018

nv_small FPGA Mapping Workflow - Max's Blog

/2018/09/12/nv_small-FPGA-Mapping-Workflow-I/

Gitalk

Status: Open.

#4 In VVViy/VVViy.github.io;

· VVViy opened on Oct 18, 2018

nv_small FPGA Mapping Workflow - Max's Blog

/2018/09/17/nv_small-FPGA-Mapping-Workflow-II/

Gitalk

Status: Open.

#3 In VVViy/VVViy.github.io;

· VVViy opened on Oct 18, 2018

Device Tree Survey and Summary - Max's Blog

/2018/10/02/Device-Tree-Survey-and-Summary/

Gitalk

Status: Open.

#2 In VVViy/VVViy.github.io;

· VVViy opened on Oct 18, 2018