docs(research): record the CUDA Tile additive-reduction gap - #1391
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The CUDA Tile audit recommended not adopting Tile C++. This timeboxed spike tests that against the kernel family where Tile looked most plausible -- float_vif_compute, whose inner loop is a windowed statistics pass. The result is sharper than "not worth it". The Tile API in CUDA 13.3 provides no additive reduction at all: reduce_max, reduce_min and the three bitwise reductions are builtins, reduce_add is absent. Every hot kernel in this fork is built from additive reductions. Measured on an RTX 4090 (sm_89), same 32x32 tile, only the operator differs: tile_max_native (reduce_max) REG:24 SHARED:0 tile_sum_via_scan (two partial_sums) REG:47 SHARED:4096 ~2x the registers and a 4 KB shared-memory staging buffer to produce one scalar that the current SIMT path gets from a register-only warp shuffle. Two further findings, both build-system rather than capability: a __global__ function cannot call __tile__ code, so a Tile port is a second parallel entry point (__tile_global__) rather than an incremental edit; and a plain -cubin build with --enable-tile emits no SASS for tile kernels at all -- codegen lands only under --tilefatbin, in a separate fatbin section. Revisit if a future CUDA adds reduce_add. Co-Authored-By: Claude Opus 5 <noreply@anthropic.com>
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Summary
Timeboxed spike closing out the CUDA Tile adoption question, run against the
kernel family where Tile looked most plausible —
float_vif_compute.The result is sharper than "not worth it": the Tile API in CUDA 13.3 has no
additive reduction primitive at all.
reduce_max,reduce_min,reduce_bitand,reduce_bitorandreduce_bitxorare builtins;reduce_adddoes not exist. Every hot kernel in this fork —
float_vif_compute, theinteger_admaccumulators,float_moment, the SpEED covariance pass — is builtfrom additive reductions.
Measured on an RTX 4090 (sm_89), same 32×32 tile, only the operator differs:
tile_max_nativereduce_max(builtin)tile_sum_via_scanpartial_sumscans~2× the registers plus a 4 KB shared-memory staging buffer, to produce one
scalar the current SIMT path gets from a register-only warp shuffle.
Two further findings, both build-system rather than capability:
__global__function cannot call__tile__code (calling a __tile__ function ... from a __global__ function is not allowed). Tile kernels needthe separate
__tile_global__entry point, so a Tile port is a secondparallel entry point plus host-side dispatch, not an incremental kernel edit.
-cubinbuild with--enable-tileemits no SASS for tile kernels— only
.note.nv.tkinfoandGLOBAL:0. Codegen lands only under--tilefatbin, in a separate fatbin section: a second build artifact forcore/src/meson.buildand the CUDA loader to manage.Recommendation unchanged (do not adopt), now resting on a mechanism rather than
a judgement call. Revisit if a future CUDA release adds
reduce_add.Reproducer / smoke-test command
The digest carries the full
tile_spike.cusource.Deep-dive deliverables (ADR-0108)
docs/research/2040-cuda-tile-additive-reduction-gap.md.AGENTS.mdinvariant note — no rebase-sensitive invariants; no code changes.changelog.d/added/2040-cuda-tile-spike.md,CHANGELOG.mdregenerated.Docs (rule 10)
Docs-only PR; no user-discoverable surface changes.
State (rule 13)
no state delta: a research measurement, no bug opened or closed.
🤖 Generated with Claude Code