Skip to content
View Tinotenda-K's full-sized avatar

Highlights

  • Pro

Block or report Tinotenda-K

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Tinotenda-K/README.md

Hi there 👋

Electrical Engineering, University of Twente. Enschede, Netherlands.

Building Seneca Aldwyn — financial and operational intelligence for Dutch deep-tech SMBs. Backend, ML and infrastructure, solo.

Interested in computer architecture, ML systems, and the boundary between them.

asip-neural-processor — custom ISA, Verilog datapath and an assembler written from scratch. 450 MHz on Spartan-7.

digital-modulation-ber — QPSK and 16-QAM chains from first principles, Monte Carlo BER validated against closed-form bounds.

transaction-classifier — three-tier routing: rules → FinBERT → LLM. (COMING SOON)

Pinned Loading

  1. asip-neural-processor asip-neural-processor Public

    Custom application-specific processor for neural-network inference: MIPS-like ISA, Verilog datapath, assembler written from scratch, 50 MHz on Spartan-7.

    Jupyter Notebook

  2. digital-modulation-ber digital-modulation-ber Public

    QPSK, 16-QAM and π/4-DQPSK modulation chains built from first principles, with Monte Carlo bit-error-rate estimation validated against closed-form bounds.

    MATLAB