A CMOS inverter designed and simulated in LTspice, characterized through DC (VTC), transient, and power/delay analysis.
This project implements a basic CMOS inverter using a PMOS pull-up and NMOS pull-down transistor, and evaluates its static and dynamic behavior — voltage transfer characteristics, switching noise margins, propagation delay, and power dissipation — as a foundational digital/mixed-signal building block.
- M1 (PMOS): Source tied to +Vcc, Drain tied to Vout, Gate tied to Vin
- M2 (NMOS): Source tied to ground, Drain tied to Vout, Gate tied to Vin
- Supply: +Vcc = 5V
- Input: Vin swept 0V–5V (DC analysis) or driven as a pulse (transient analysis)
Swept Vin from 0V to 5V using .dc Vin 0 5 0.01 to characterize the static input-output relationship.
Extracted parameters:
| Parameter | Value |
|---|---|
| VOH (output high) | 5.00 V |
| VOL (output low) | ~0 V |
| VIL (input low threshold) | 1.78 V |
| VIH (input high threshold) | 2.75 V |
| Noise Margin Low (NML = VIL − VOL) | 1.78 V |
| Noise Margin High (NMH = VOH − VIH) | 2.25 V |
| Switching threshold (Vin = Vout) | 2.32 V |
The VTC shows a full rail-to-rail swing (0V to 5V) with a sharp transition region, indicating good noise immunity and a well-defined logic threshold close to Vcc/2.
Driven Vin with a pulse source (PULSE(0 5 10n 1n 1n 20n 40n)) to observe dynamic switching behavior.
Extracted parameters:
| Parameter | Value |
|---|---|
| Propagation delay, High-to-Low (tpHL) | ~20 ns |
| Propagation delay, Low-to-High (tpLH) | ~20 ns |
| Average propagation delay (tp) | ~20 ns |
| Average power dissipation | ~20.4 µW |
The VTC's sharp transition and roughly Vcc/2-centered switching threshold indicate a reasonably balanced PMOS/NMOS drive strength. Propagation delay is dominated by the RC charge/discharge behavior at the output node under the given transistor sizing; power dissipation stays low since this is a purely combinational (non-switching-heavy) test scenario with a single output transition per input edge.
CMOS_Inverter.asc— LTspice schematicimages/— schematic, VTC, and transient plot screenshots
LTspice 24.1.9
Subrat Panda LinkedIn | GitHub | 24je0177@iitism.ac.in