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new experiments folder CI #275: Commit 1efe51c pushed by RCoeurjoly
1m 33s task6-crisp
task6-crisp
1m 33s
Checkpoint Task 6 M2 submilestones CI #274: Commit 6d821c9 pushed by RCoeurjoly
1m 23s task6-crisp
task6-crisp
1m 23s
Record M2.4 BAR boundary probe CI #273: Commit 8b2d2e6 pushed by RCoeurjoly
1m 28s task6-crisp
task6-crisp
1m 28s
just works, the milestone does not though CI #272: Commit 23d5a23 pushed by RCoeurjoly
1m 41s task6-crisp
task6-crisp
1m 41s
Exclude artifacts from shell checks CI #271: Commit 64b0dee pushed by RCoeurjoly
1m 31s task6
task6
1m 31s
task6: update gating, replay, and zero-to-one workflows CI #270: Commit 7a40ce6 pushed by RCoeurjoly
1m 31s task6
task6
1m 31s
task6: record M2 status route pass CI #269: Commit a642672 pushed by RCoeurjoly
1m 18s task6
task6
1m 18s
task6: add M2 layernorm attention sublane selftest CI #268: Commit 7b1a261 pushed by RCoeurjoly
3h 13m 2s task6
task6
3h 13m 2s
task6: add PWL MLP lane and autonomous PCIe bringup CI #267: Commit 52a3135 pushed by RCoeurjoly
2h 28m 39s task6
task6
2h 28m 39s
task6: record PCIe DDR3 board evidence CI #266: Commit b70b549 pushed by RCoeurjoly
6m 38s task6
task6
6m 38s
Record Task 6 full rowstream seed20 flash CI #265: Commit 9f6ec13 pushed by RCoeurjoly
2h 57m 48s task6
task6
2h 57m 48s
Add Task 6 rowstream top1 host gate CI #264: Commit feb4799 pushed by RCoeurjoly
2h 7m 58s task6
task6
2h 7m 58s
Add OpenXC7 PCIe debug instrumentation CI #263: Commit 579258c pushed by RCoeurjoly
3h 18m 25s task6
task6
3h 18m 25s
Checkpoint Task 6 PCIe recovery artifacts CI #262: Commit 65d08c1 pushed by RCoeurjoly
3h 6m 19s task6
task6
3h 6m 19s
task6: use mem-backed PCIe command bridge CI #261: Commit a0aebbb pushed by RCoeurjoly
3h 17m 27s task6
task6
3h 17m 27s
Add DDR3 packet slot acknowledgement CI #260: Commit e46088d pushed by RCoeurjoly
2h 58m 47s task6
task6
2h 58m 47s
Restore DDR3 loader executable bit CI #259: Commit 5e06409 pushed by RCoeurjoly
3h 17m 49s task6
task6
3h 17m 49s
Add DDR3 RTL burst diagnostic and write retries CI #258: Commit 2ece9ec pushed by RCoeurjoly
3h 16m 53s task6
task6
3h 16m 53s
Support prefix-scoped Task 6 BEL locks CI #257: Commit 7d604be pushed by RCoeurjoly
2h 58m 27s task6
task6
2h 58m 27s
default = task6Int8V9984L2ResidualAddOutputHeadSelftestJtagDebug5MHzB… CI #256: Commit ede513d pushed by RCoeurjoly
3h 1m 5s task6
task6
3h 1m 5s
WIP CI #255: Commit e35796c pushed by RCoeurjoly
6h 0m 27s scaling
scaling
6h 0m 27s
task6: set default package to latest pre-DDR3 task6 target CI #254: Commit 85f7b67 pushed by RCoeurjoly
3h 5m 15s task6
task6
3h 5m 15s
task6: add inferred ypcb gate run artifacts and uberddr3 seed16-vaini… CI #253: Commit 3bd7cef pushed by RCoeurjoly
3h 28m 8s task6-ddr3
task6-ddr3
3h 28m 8s
task6: add DDR3 clock and signature gates CI #252: Commit 27bc106 pushed by RCoeurjoly
3h 15m 52s task6-ddr3
task6-ddr3
3h 15m 52s
task6: simulate UberDDR3 stage2 timing CI #251: Commit f0ebc66 pushed by RCoeurjoly
3h 7m 11s task6-ddr3
task6-ddr3
3h 7m 11s