6T SRAM Cell Design and Verification in Cadence Virtuoso

📌 Project Overview

This repository contains the transistor-level design, schematic capture, and functional verification of a standard 6T Static Random-Access Memory (SRAM) cell. The project was developed using Cadence Virtuoso and simulates both static stability (Static Noise Margin) and dynamic functionality (Transient Read, Write, and Hold operations).

Author: Vemana Venkata Pujithram

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🛠️ Tools & Technology

• EDA Tool: Cadence Virtuoso (Schematic Editor L, ADE L, Visualization & Analysis XL / ViVA)
• Simulator: Spectre
• Supply Voltage (VDD): 1.8V

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🏗️ Design Architecture

The 6T SRAM cell consists of two primary components:

1. The Storage Loop: Two cross-coupled CMOS inverters (2 PMOS Pull-Up, 2 NMOS Pull-Down) responsible for holding the 1-bit logic state (Q and QB).
2. The Access Logic: Two NMOS Pass-Gate transistors controlled by the Wordline (WL) that connect the storage nodes to the Bitlines (BL and BLB) for read and write operations.

Transistor Sizing Strategy (Ratioed Logic)

To ensure read stability and write-ability, the cell utilizes standard ratioed logic:

• Pull-Down NMOS: Strongest (W ≈ 240nm - 300nm)
• Pass-Gate NMOS: Medium (W ≈ 120nm - 150nm)
• Pull-Up PMOS: Weakest (W ≈ 120nm)

(Note: Channel length L is kept at the minimum technology node size).

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⚙️ Environment Setup & Key Commands

The following Virtuoso hotkeys and commands were utilized throughout the schematic capture and debugging process:

Terminal

# Sourcing the Cadence environment and launching the tool
source <path_to_cadence_env_script>
virtuoso &

Virtuoso Schematic Editor Shortcuts

• i : Add Instance (e.g., analogLib -> vpulse, vdc, gnd)
• w : Add Wire
• q : Edit Object Properties (Used for setting vpulse timing parameters)
• m : Move object
• Shift + X : Check and Save (Crucial before any netlist generation)

🧪 Simulation Phase 1: Static Analysis (SNM)

Objective: Measure the Static Noise Margin (SNM) to ensure the cell can withstand voltage fluctuations without losing data.

• Setup: Performed a DC Sweep of the internal storage nodes.
• Output: Generated a Butterfly Curve (Voltage Transfer Characteristics) using the waveVsWave calculator function in ViVA.
• Result: The largest inscribed square within the curve yields an SNM of ~529 mV, indicating robust cell stability.

---(Insert butterfly_curve.png here)---

📊 Simulation Phase 2: Transient Analysis (Read & Write)

Objective: Verify the dynamic time-domain functionality of the SRAM cell.

1. Write Operation Test

• Stimuli Setup (sram_6t_tb): ** BL and BLB set as complementary signals (e.g., BL=0V, BLB=1.8V). ** WL configured as a vpulse (0V to 1.8V) with a delay to ensure bitlines settle before access.

• Result: When WL goes HIGH, the access transistors turn on, and the internal nodes (Q and QB) successfully flip to match the driven Bitline states.

---(Insert write_transient.png here)---

2. Read Operation Test

• Stimuli Setup: ** BL and BLB both pre-charged to VDD (1.8V) using vpulse or vdc. ** WL pulsed HIGH (1.8V) for 10ns.

• Result: When WL goes HIGH, the Bitline corresponding to the 0 state inside the cell discharges slightly through the access and pull-down transistors. This creates a distinct voltage "dip" on the graph, confirming a successful Read operation.

---(Insert read_transient.png here)---

3. Hold State Test

• Stimuli Setup: WL forced to 0V.
• Result: The cell is completely isolated from the bitlines. Q and QB maintain their latched states indefinitely without degradation, proving successful data retention.

🚀 Next Steps

• This verified schematic serves as the "Golden Netlist" for the physical design phase. Future implementations will include:
• Custom Layout Design in Virtuoso Layout Suite.
• Physical Verification via Design Rule Check (DRC) and Layout vs. Schematic (LVS).
• Post-Layout Simulation incorporating Parasitic Extraction (PEX) delays.

Developed as part of MUJ Summer School in VLSI Design - Advanced Digital VLSI & Custom IC Design coursework