[Frontend] MLIR codegen on Python bindings: port C++ passes + affine-only DMA#259

Merged

YWHyuk merged 20 commits into

feature/tog-python-binding

Jun 19, 2026

Commits on Jun 17, 2026

[Frontend] MLIR Python bindings: in-process passes and lowering
YWHyuk
committed
[Frontend] decompose togsim.transfer to <=4D dma_start
YWHyuk
committed
[Frontend] axis-split: remove aligned floor/mod at the scheduling layer
YWHyuk
committed
[Frontend] graph-copy: relayout operands on incompatible / cross-axis floor/mod
YWHyuk
committed
[Frontend] build_tog: port test-tile-operation-graph to Python
YWHyuk
committed
[Test] floor/mod axis-split + graph-copy coverage; deterministic deepseek seed
YWHyuk
committed
[Frontend] decompose-transfer: affine.for peel with lane-banked physical SRAM offset
YWHyuk
committed
[Frontend] Unify all DMA codegen on togsim.transfer

YWHyuk
and
claude
committed
[Docs] axis-split: rank guard removed, >4D peel via affine.for

YWHyuk
and
claude
committed
[Frontend] dma-fine-grained: port the C++ pass to Python (MLIR bindings)
YWHyuk
committed
[Frontend] pytorchsim-to-vcix: port the C++ pass to Python (MLIR bindings)
YWHyuk
committed
[Docs] lower_to_llvm: only test-loop-padding remains in mlir-opt
YWHyuk
committed

Commits on Jun 18, 2026