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wip: Float support and rv64f.vadl #1040

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56ce498
wip: Float support and rv64f.vadl
BadGraphixD Jul 11, 2026
8c5a1b2
wip: Add float-type definition
BadGraphixD Jul 19, 2026
83babe1
wip: Add float config annotations
BadGraphixD Jul 20, 2026
e04f10d
wip: Fix float flag annotation
BadGraphixD Jul 21, 2026
451ad2f
wip: Add risc-v float to/from int convert instructions
BadGraphixD Jul 23, 2026
c175a26
wip: Add remaining risc-v float built-ins + qemu impl
BadGraphixD Jul 24, 2026
73da252
wip: Finish RISC-V D extension
BadGraphixD Jul 25, 2026
b3e41cd
wip: Add risc-v cosim scripts and config
BadGraphixD Jul 27, 2026
d23227e
wip: Add built-in constant parameters
BadGraphixD Jul 28, 2026
2d85f3d
wip: Add IEEE rounding modes to ISS
BadGraphixD Jul 31, 2026
ccc069a
wip: Change builtin constant param syntax
BadGraphixD Aug 2, 2026
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12 changes: 8 additions & 4 deletions sys/risc-v/rv64csr.vadl
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,8 @@ import rv3264im::{RV3264Base, RV3264M} with ("ArchSize=Arch64")
instruction set architecture RV64IZicsr extending RV3264Base = {

enumeration CsrDef : Bits<12> = // defined control and status register indices
{ mstatus = 0x300 // 768 Machine STATUS
{ fcsr = 0x003 // 003 Floating-Point Control and Status Register (frm + fflags)
, mstatus = 0x300 // 768 Machine STATUS
, misa = 0x301 // 769 Machine ISA
, mie = 0x304 // 772 Machine Interrupt Enable register
, mtvec = 0x305 // 773 Machine Trap VECtor base address
Expand All @@ -20,7 +21,8 @@ instruction set architecture RV64IZicsr extending RV3264Base = {
using CsrImplIndex = Bits<CsrIndexSize> // index type for implemented CSR registers

enumeration CsrImpl : CsrImplIndex = // implemented control and status register indices
{ mstatus // 0x300 Machine STATUS
{ fcsr // 0x003 003 Floating-Point Control and Status Register (frm + fflags)
, mstatus // 0x300 Machine STATUS
, misa // 0x301 Machine ISA
, mie // 0x304 Machine Interrupt Enable
, mtvec // 0x305 Machine Trap VECtor base address
Expand All @@ -35,7 +37,8 @@ instruction set architecture RV64IZicsr extending RV3264Base = {

function CsrDefToImpl (csr : Bits<12>) -> CsrImplIndex = // map defined CSR index to implemented CSR index
match csr with
{ CsrDef::mstatus => CsrImpl::mstatus // 0x300 Machine STATUS
{ CsrDef::fcsr => CsrImpl::fcsr // 0x003 Floating-Point Control and Status Register (frm + fflags)
, CsrDef::mstatus => CsrImpl::mstatus // 0x300 Machine STATUS
, CsrDef::misa => CsrImpl::misa // 0x301 Machine ISA
, CsrDef::mie => CsrImpl::mie // 0x304 Machine Interrupt Enable
, CsrDef::mtvec => CsrImpl::mtvec // 0x305 Machine Trap VECtor base address
Expand All @@ -50,7 +53,8 @@ instruction set architecture RV64IZicsr extending RV3264Base = {

function CsrName(index : Bits<12>) -> String =
match index with
{ CsrDef::mstatus => "mstatus" // Machine STATUS
{ CsrDef::fcsr => "fcsr" // Floating-Point Control and Status Register (frm + fflags)
, CsrDef::mstatus => "mstatus" // Machine STATUS
, CsrDef::misa => "misa" // Machine ISA
, CsrDef::mie => "mie" // Machine Interrupt Enable
, CsrDef::mtvec => "mtvec" // Machine Trap VECtor base address
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35 changes: 35 additions & 0 deletions sys/risc-v/rv64d.vadl
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@@ -0,0 +1,35 @@

import rv64fd::{RV64IFD} with ("ExtensionFD=D")

instruction set architecture RV64ID extending RV64IFD = {}

[ htif ]
processor Spike implements RV64ID = {
constant reset_vec_addr = 0x1000

reset = {
PC := reset_vec_addr
}

[ firmware ]
[ base: 0x80000000 ]
memory region [RAM] DRAM in MEM

memory region [ROM] MROM in MEM = {
MEM<4>(0x1000) := 0x00000297 // auipc t0, 0x0
MEM<4>(0x1004) := 0x02828613 // addi a2, t0, 40
// TODO: this is not quite right:
// this processor has no zicsr extension
MEM<4>(0x1008) := 0x00000013 // addi x0, x0, 0
MEM<4>(0x100c) := 0x0202b583 // ld a1, 32(t0)
MEM<4>(0x1010) := 0x0182b283 // ld t0, 24(t0)
MEM<4>(0x1014) := 0x00028067 // jr t0
// store start_addr in memory (0x80000000)
MEM<4>(0x1018) := 0x80000000 // lo32(start_addr)
MEM<4>(0x101c) := 0x00000000 // hi32(start_addr)
// we do not yet support a fdt, but we set the address,
// to keep the registers consistent with upstream
MEM<4>(0x1020) := 0x87e00000 // lo32(fdt_addr)
MEM<4>(0x1024) := 0x00000000 // hi32(fdt_addr)
}
}
35 changes: 35 additions & 0 deletions sys/risc-v/rv64f.vadl
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@@ -0,0 +1,35 @@

import rv64fd::{RV64IFD}

instruction set architecture RV64IF extending RV64IFD = {}

[ htif ]
processor Spike implements RV64IF = {
constant reset_vec_addr = 0x1000

reset = {
PC := reset_vec_addr
}

[ firmware ]
[ base: 0x80000000 ]
memory region [RAM] DRAM in MEM

memory region [ROM] MROM in MEM = {
MEM<4>(0x1000) := 0x00000297 // auipc t0, 0x0
MEM<4>(0x1004) := 0x02828613 // addi a2, t0, 40
// TODO: this is not quite right:
// this processor has no zicsr extension
MEM<4>(0x1008) := 0x00000013 // addi x0, x0, 0
MEM<4>(0x100c) := 0x0202b583 // ld a1, 32(t0)
MEM<4>(0x1010) := 0x0182b283 // ld t0, 24(t0)
MEM<4>(0x1014) := 0x00028067 // jr t0
// store start_addr in memory (0x80000000)
MEM<4>(0x1018) := 0x80000000 // lo32(start_addr)
MEM<4>(0x101c) := 0x00000000 // hi32(start_addr)
// we do not yet support a fdt, but we set the address,
// to keep the registers consistent with upstream
MEM<4>(0x1020) := 0x87e00000 // lo32(fdt_addr)
MEM<4>(0x1024) := 0x00000000 // hi32(fdt_addr)
}
}
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