Skip to content

linx: support clean qemu-user glibc execution #32

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
touzicongbupianren wants to merge 3 commits into
base: qemu-my-patch-v7.0.0
Choose a base branch
from
Open

linx: support clean qemu-user glibc execution #32

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
0fcd07d
linx: remove temporary qemu-user TB diagnostics
touzicongbupianren Jun 3, 2026
d3abfe4
linx: align linux-user syscall and signal ABI
touzicongbupianren Jun 3, 2026
74acbcc
linx: complete qemu-user block translation fixes
touzicongbupianren Jun 3, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 0 additions & 5 deletions accel/tcg/cpu-exec.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -52,9 +52,6 @@
#include "sysemu/runstate-action.h"
#include "qemu/timer.h"

uint64_t kenny_tb_exec = 0;
uint64_t kenny_tb_trans = 0;

bool enable_delay_block_intr = false;

/* -icount align implementation. */
Expand Down Expand Up @@ -214,8 +211,6 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
static inline void log_cpu_exec(target_ulong pc, CPUState *cpu,
const TranslationBlock *tb)
{
kenny_tb_exec++;

if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC))
&& qemu_log_in_addr_range(pc)) {

Expand Down
3 changes: 0 additions & 3 deletions accel/tcg/translate-all.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1378,8 +1378,6 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
return tb;
}

extern uint64_t kenny_tb_trans;

/* Called with mmap_lock held for user mode emulation. */
TranslationBlock *tb_gen_code(CPUState *cpu,
target_ulong pc, target_ulong cs_base,
Expand All @@ -1396,7 +1394,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
int64_t ti;
#endif

kenny_tb_trans++;
assert_memory_lock();
qemu_thread_jit_write();

Expand Down
2 changes: 1 addition & 1 deletion include/elf.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,7 @@ typedef struct mips_elf_abiflags_v0 {

#define EM_LOONGARCH 258 /* LoongArch */

#define EM_LINX 261 /* Let's use same value with RISCV currently */
#define EM_LINX 233 /* LinxISA */

/*
* This is an interim value that we will use until the committee comes
Expand Down
13 changes: 4 additions & 9 deletions linux-user/linx/cpu_loop.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -27,9 +27,6 @@
#include "elf.h"
#include "semihosting/common-semi.h"

extern uint64_t kenny_tb_exec;
extern uint64_t kenny_tb_trans;

void cpu_loop(CPULINXState *env)
{
CPUState *cs = env_cpu(env);
Expand Down Expand Up @@ -60,14 +57,12 @@ void cpu_loop(CPULINXState *env)
case LINX_EXCP_SCALL:
env->pc = env->next_bpc;

linx_reset_bstate(env);

if (env->gpr[xX1] == TARGET_NR_linx_flush_icache) {
if (env->gpr[xA7] == TARGET_NR_linx_flush_icache) {
/* linx_flush_icache_syscall is a no-op in QEMU as
self-modifying code is automatically detected */
ret = 0;
} else {
ret = do_syscall(env, env->gpr[xX1],
ret = do_syscall(env, env->gpr[xA7],
env->gpr[xA0],
env->gpr[xA1],
env->gpr[xA2],
Expand All @@ -76,14 +71,14 @@ void cpu_loop(CPULINXState *env)
env->gpr[xA5],
0, 0);
}
if (ret == -TARGET_ERESTARTSYS) {
if (ret == -QEMU_ERESTARTSYS) {
/*
* Regenerate the exception so that cpu_exec can exit before
* executing the instruction.
*/
cs->exception_index = LINX_EXCP_SCALL;
} else {
if (ret != -TARGET_QEMU_ESIGRETURN)
if (ret != -QEMU_ESIGRETURN)
env->gpr[xA0] = ret;
}
Comment on lines +74 to 83

@gemini-code-assist gemini-code-assist Bot Jun 3, 2026

Copy link
Copy Markdown

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

critical

Regenerating the exception on -QEMU_ERESTARTSYS without rewinding env->pc is incorrect and leads to severe bugs. When a signal is pending, cpu_exec will exit immediately and process_pending_signals will set up the signal frame and modify env->pc to point to the signal handler. However, because cs->exception_index is still set to LINX_EXCP_SCALL, the loop will immediately execute case LINX_EXCP_SCALL again, overwriting env->pc with env->next_bpc. This completely bypasses the signal handler and corrupts the execution state.

Instead, we should rewind env->pc to the original syscall instruction (which is 4 bytes before env->next_bpc) and let the normal QEMU signal delivery mechanism handle the restart without regenerating the exception, matching the standard behavior of other QEMU targets like RISC-V.

            if (ret == -QEMU_ERESTARTSYS) {
                env->pc -= 4;
            } else {
                if (ret != -QEMU_ESIGRETURN)
                    env->gpr[xA0] = ret;
            }


Expand Down
2 changes: 1 addition & 1 deletion linux-user/linx/signal.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -187,7 +187,7 @@ long do_rt_sigreturn(CPULINXState *env)
target_restore_altstack(&frame->uc.uc_stack, env);

unlock_user_struct(frame, frame_addr, 0);
return -TARGET_QEMU_ESIGRETURN;
return -QEMU_ESIGRETURN;

badframe:
unlock_user_struct(frame, frame_addr, 0);
Expand Down
1 change: 1 addition & 0 deletions linux-user/linx/target_prctl.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
/* No special prctl support required. */
1 change: 1 addition & 0 deletions linux-user/linx/target_resource.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
#include "../generic/target_resource.h"
12 changes: 0 additions & 12 deletions linux-user/linx/target_signal.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,18 +1,6 @@
#ifndef LINX_TARGET_SIGNAL_H
#define LINX_TARGET_SIGNAL_H

typedef struct target_sigaltstack {
abi_ulong ss_sp;
abi_int ss_flags;
abi_ulong ss_size;
} target_stack_t;

#define TARGET_SS_ONSTACK 1
#define TARGET_SS_DISABLE 2

#define TARGET_MINSIGSTKSZ 2048
#define TARGET_SIGSTKSZ 8192

#include "../generic/signal.h"

#define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1
Expand Down
6 changes: 0 additions & 6 deletions linux-user/syscall.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13153,9 +13153,6 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1,
return ret;
}

extern uint64_t kenny_tb_exec;
extern uint64_t kenny_tb_trans;

abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
abi_long arg2, abi_long arg3, abi_long arg4,
abi_long arg5, abi_long arg6, abi_long arg7,
Expand All @@ -13178,9 +13175,6 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
#endif

if(num==TARGET_NR_exit || num == TARGET_NR_exit_group)
printf("kenny: TB exec = %lu, trans = %lu\n", kenny_tb_exec, kenny_tb_trans);

record_syscall_start(cpu, num, arg1,
arg2, arg3, arg4, arg5, arg6, arg7, arg8);

Expand Down
5 changes: 3 additions & 2 deletions target/linx/block32.decode
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -207,7 +207,8 @@ blk_bdim ............ ..... ... ..... 100 0011 @bdim
%s_imm_12_1 7:s5 25:7
%s_imm_17 15:s17
%s_imm_17_1 7:s5 20:12
%s_imm_20 12:s20 !function=ex_shift_12
%s_imm_20 12:s20
%s_imm_20_12 12:s20 !function=ex_shift_12
%s_imm_20_1 12:s20 !function=ex_shift_1
%imms 26:6
%imml 20:6
Expand Down Expand Up @@ -280,7 +281,7 @@ blk_bdim ............ ..... ... ..... 100 0011 @bdim
@arg_setc_ui ............ ..... ... ..... ... .... &arg_setc_i imm=%u_imm_12 %SrcL shamt=%RegDst
@arg_addtpc .................... ..... ... .... &arg_pc imm=%s_imm_20 %RegDst
@arg_setret .................... ..... ... .... &arg_pc imm=%s_imm_20_1 RegDst=10
@arg_lui .................... ..... ... .... &arg_pc imm=%s_imm_20 %RegDst
@arg_lui .................... ..... ... .... &arg_pc imm=%s_imm_20_12 %RegDst

@arg_branch ....... ..... ..... ... ..... .... . . . &arg_branch imm=%imm_12_1 %SrcR %SrcL
@arg_jr ....... ..... ..... ... ..... .... . . . &arg_branch imm=%imm_12_1 SrcR=0 %SrcL
Expand Down
67 changes: 44 additions & 23 deletions target/linx/block48.decode
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,10 @@ blk_start_call ---------------- ................. 100 ..... 000 000 1 ........
%s_imm_17 6:s5 36:12
%s_imm_12 36:s12
%s_imm_12_1 23:s5 41:7 !function=ex_shift_1
%s_imm_17_sdi 6:s5 23:5 41:7
%s_imm_17_sdip 11:s5 23:5 41:7
%s_imm_24 4:s12 36:12
%u_imm_24 4:12 36:12
%s_imm_28 4:s12 31:17
%s_imm_28_1 4:s12 23:5 36:12

Expand Down Expand Up @@ -81,6 +85,7 @@ blk_start_call ---------------- ................. 100 ..... 000 000 1 ........
&arg_sdi imm SrcR SrcD RegDst
&arg_sdp SrcD SrcRType SrcR SrcL RegDst SrcD1
&arg_sdip imm SrcR SrcD RegDst SrcD1
&arg_hl_arith_i imm SrcL RegDst

&arg_ld_pcr imm RegDst
&arg_sd_pcr imm SrcL
Expand Down Expand Up @@ -111,9 +116,12 @@ blk_start_call ---------------- ................. 100 ..... 000 000 1 ........
@arg_ldp ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_ld shamt=%shamt_5 %SrcRType %SrcR %SrcL %RegDst0 %RegDst1 %RegDst2
@arg_ldip ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_ldi imm=%s_imm_12 %SrcL %RegDst0 %RegDst1 %RegDst2
@arg_sd ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_sd %SrcD %SrcRType %SrcR %SrcL RegDst=%RegDst1
@arg_sdi ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_sdi imm=%s_imm_12_1 %SrcR SrcD=%SrcL RegDst=%RegDst1
@arg_sdi ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_sdi imm=%s_imm_17_sdi %SrcR SrcD=%SrcL RegDst=%RegDst1
@arg_sdp ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_sdp %SrcD %SrcRType %SrcR %SrcL RegDst=%RegDst1 SrcD1=%RegDst2
@arg_sdip ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_sdip imm=%s_imm_12_1 %SrcR SrcD=%SrcL RegDst=%RegDst1 SrcD1=%RegDst2
@arg_sdip_cur ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_sdip imm=%s_imm_17_sdip %SrcR SrcD=%SrcL RegDst=0 SrcD1=%RegDst2
@arg_arith_si ................ ............ ..... ... ..... ... ... . ............ ... . &arg_hl_arith_i imm=%s_imm_24 %SrcL RegDst=%RegDst0
@arg_arith_ui ................ ............ ..... ... ..... ... ... . ............ ... . &arg_hl_arith_i imm=%u_imm_24 %SrcL RegDst=%RegDst0
@arg_ld_pcr ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_ld_pcr imm=%s_imm_28 RegDst=%RegDst0
@arg_sd_pcr ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_sd_pcr imm=%s_imm_28_1 %SrcL
@arg_prf ................ ..... .. ..... ..... ... ..... ... ... . ..... ..... .. ... . &arg_prf shamt=%shamt_5 %SrcRType %SrcR %SrcL RegDst=0 %model
Expand Down Expand Up @@ -244,13 +252,13 @@ blk_sh_upr_48 ---------------- ..... .. ..... ..... 101 00000 100 100 1 .....
blk_sw_upr_48 ---------------- ..... .. ..... ..... 110 00000 100 100 1 ..... 00000 00 111 0 @arg_sd
blk_sd_upr_48 ---------------- ..... .. ..... ..... 111 00000 100 100 1 ..... 00000 00 111 0 @arg_sd

blk_sbi_pr_48 ---------------- ............ ..... 000 ..... 101 100 1 ..... 00000 00 111 0 @arg_sdi
blk_shi_pr_48 ---------------- ............ ..... 001 ..... 101 100 1 ..... 00000 00 111 0 @arg_sdi
blk_swi_pr_48 ---------------- ............ ..... 010 ..... 101 100 1 ..... 00000 00 111 0 @arg_sdi
blk_sdi_pr_48 ---------------- ............ ..... 011 ..... 101 100 1 ..... 00000 00 111 0 @arg_sdi
blk_shi_upr_48 ---------------- ............ ..... 101 ..... 101 100 1 ..... 00000 00 111 0 @arg_sdi
blk_swi_upr_48 ---------------- ............ ..... 110 ..... 101 100 1 ..... 00000 00 111 0 @arg_sdi
blk_sdi_upr_48 ---------------- ............ ..... 111 ..... 101 100 1 ..... 00000 00 111 0 @arg_sdi
blk_sbi_pr_48 ---------------- ....... ..... ..... 000 ..... 101 100 1 ..... ..... 00 111 0 @arg_sdi
blk_shi_pr_48 ---------------- ....... ..... ..... 001 ..... 101 100 1 ..... ..... 00 111 0 @arg_sdi
blk_swi_pr_48 ---------------- ....... ..... ..... 010 ..... 101 100 1 ..... ..... 00 111 0 @arg_sdi
blk_sdi_pr_48 ---------------- ....... ..... ..... 011 ..... 101 100 1 ..... ..... 00 111 0 @arg_sdi
blk_shi_upr_48 ---------------- ....... ..... ..... 101 ..... 101 100 1 ..... ..... 00 111 0 @arg_sdi
blk_swi_upr_48 ---------------- ....... ..... ..... 110 ..... 101 100 1 ..... ..... 00 111 0 @arg_sdi
blk_sdi_upr_48 ---------------- ....... ..... ..... 111 ..... 101 100 1 ..... ..... 00 111 0 @arg_sdi

# Store Post-Index
blk_sb_po_48 ---------------- ..... .. ..... ..... 000 00000 100 100 1 ..... 00000 01 111 0 @arg_sd
Expand All @@ -261,13 +269,22 @@ blk_sh_upo_48 ---------------- ..... .. ..... ..... 101 00000 100 100 1 .....
blk_sw_upo_48 ---------------- ..... .. ..... ..... 110 00000 100 100 1 ..... 00000 01 111 0 @arg_sd
blk_sd_upo_48 ---------------- ..... .. ..... ..... 111 00000 100 100 1 ..... 00000 01 111 0 @arg_sd

blk_sbi_po_48 ---------------- ............ ..... 000 ..... 101 100 1 ..... 00000 01 111 0 @arg_sdi
blk_shi_po_48 ---------------- ............ ..... 001 ..... 101 100 1 ..... 00000 01 111 0 @arg_sdi
blk_swi_po_48 ---------------- ............ ..... 010 ..... 101 100 1 ..... 00000 01 111 0 @arg_sdi
blk_sdi_po_48 ---------------- ............ ..... 011 ..... 101 100 1 ..... 00000 01 111 0 @arg_sdi
blk_shi_upo_48 ---------------- ............ ..... 101 ..... 101 100 1 ..... 00000 01 111 0 @arg_sdi
blk_swi_upo_48 ---------------- ............ ..... 110 ..... 101 100 1 ..... 00000 01 111 0 @arg_sdi
blk_sdi_upo_48 ---------------- ............ ..... 111 ..... 101 100 1 ..... 00000 01 111 0 @arg_sdi
# Store Pair Immediate (current v0.56 bits[5:4] = 01)
blk_sbip_48 ---------------- ....... ..... ..... 000 ..... 101 100 1 ..... ..... 01 111 0 @arg_sdip_cur
blk_ship_48 ---------------- ....... ..... ..... 001 ..... 101 100 1 ..... ..... 01 111 0 @arg_sdip_cur
blk_swip_48 ---------------- ....... ..... ..... 010 ..... 101 100 1 ..... ..... 01 111 0 @arg_sdip_cur
blk_sdip_48 ---------------- ....... ..... ..... 011 ..... 101 100 1 ..... ..... 01 111 0 @arg_sdip_cur
blk_ship_u_48 ---------------- ....... ..... ..... 101 ..... 101 100 1 ..... ..... 01 111 0 @arg_sdip_cur
blk_swip_u_48 ---------------- ....... ..... ..... 110 ..... 101 100 1 ..... ..... 01 111 0 @arg_sdip_cur
blk_sdip_u_48 ---------------- ....... ..... ..... 111 ..... 101 100 1 ..... ..... 01 111 0 @arg_sdip_cur

blk_sbi_po_48 ---------------- ....... ..... ..... 000 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdi
blk_shi_po_48 ---------------- ....... ..... ..... 001 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdi
blk_swi_po_48 ---------------- ....... ..... ..... 010 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdi
blk_sdi_po_48 ---------------- ....... ..... ..... 011 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdi
blk_shi_upo_48 ---------------- ....... ..... ..... 101 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdi
blk_swi_upo_48 ---------------- ....... ..... ..... 110 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdi
blk_sdi_upo_48 ---------------- ....... ..... ..... 111 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdi

# Srore Pair Pre-Index
blk_sbp_pr_48 ---------------- ..... .. ..... ..... 000 00000 100 100 1 ..... ..... 10 111 0 @arg_sdp
Expand Down Expand Up @@ -295,14 +312,6 @@ blk_shp_upo_48 ---------------- ..... .. ..... ..... 101 00000 100 100 1 .....
blk_swp_upo_48 ---------------- ..... .. ..... ..... 110 00000 100 100 1 ..... ..... 11 111 0 @arg_sdp
blk_sdp_upo_48 ---------------- ..... .. ..... ..... 111 00000 100 100 1 ..... ..... 11 111 0 @arg_sdp

blk_sbip_po_48 ---------------- ....... ..... ..... 000 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdip
blk_ship_po_48 ---------------- ....... ..... ..... 001 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdip
blk_swip_po_48 ---------------- ....... ..... ..... 010 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdip
blk_sdip_po_48 ---------------- ....... ..... ..... 011 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdip
blk_ship_upo_48 ---------------- ....... ..... ..... 101 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdip
blk_swip_upo_48 ---------------- ....... ..... ..... 110 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdip
blk_sdip_upo_48 ---------------- ....... ..... ..... 111 ..... 101 100 1 ..... ..... 11 111 0 @arg_sdip

# Load PC-Relative
blk_lb_pcr_48 ---------------- ................. 000 ..... 011 100 1 ............ 111 0 @arg_ld_pcr
blk_lh_pcr_48 ---------------- ................. 001 ..... 011 100 1 ............ 111 0 @arg_ld_pcr
Expand Down Expand Up @@ -339,6 +348,18 @@ blk_casw_48 ---------------- 0010 . . . ..... ..... 110 ..... 000 101 1 00000
blk_casd_48 ---------------- 0011 . . . ..... ..... 110 ..... 000 101 1 00000 ..... 00 111 0 @arg_cas

# Long Immediate
blk_addi_48 ---------------- ............ ..... 000 ..... 001 010 1 ............ 111 0 @arg_arith_ui
blk_subi_48 ---------------- ............ ..... 001 ..... 001 010 1 ............ 111 0 @arg_arith_ui
blk_andi_48 ---------------- ............ ..... 010 ..... 001 010 1 ............ 111 0 @arg_arith_si
blk_ori_48 ---------------- ............ ..... 011 ..... 001 010 1 ............ 111 0 @arg_arith_si
blk_xori_48 ---------------- ............ ..... 100 ..... 001 010 1 ............ 111 0 @arg_arith_si

blk_addiw_48 ---------------- ............ ..... 000 ..... 011 010 1 ............ 111 0 @arg_arith_ui
blk_subiw_48 ---------------- ............ ..... 001 ..... 011 010 1 ............ 111 0 @arg_arith_ui
blk_andiw_48 ---------------- ............ ..... 010 ..... 011 010 1 ............ 111 0 @arg_arith_si
blk_oriw_48 ---------------- ............ ..... 011 ..... 011 010 1 ............ 111 0 @arg_arith_si
blk_xoriw_48 ---------------- ............ ..... 100 ..... 011 010 1 ............ 111 0 @arg_arith_si

blk_lis_48 ---------------- .................... ..... 000 110 1 ............ 111 0 @arg_lis
blk_liu_48 ---------------- .................... ..... 001 110 1 ............ 111 0 @arg_liu

Expand Down
24 changes: 13 additions & 11 deletions target/linx/cpu_bits.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -363,27 +363,29 @@ typedef struct {
#define INSTR_TYPE_FP 3
/* Load/Store support only EXT_NONE, EXT_SW, EXT_UW, except AU_NEG */
#define INSTR_TYPE_CMP_SETC_LD_ST 4
/* CMP/SETC syntax only exposes .sw/.uw; SrcRType=3 is treated as none. */
#define INSTR_TYPE_CMP_SETC_SWUW 5

/* register ext operation type*/
#define REG_EXT_NONE 0
#define REG_EXT_SW 1
#define REG_EXT_UW 2
#define REG_EXT_NOT 3
#define REG_EXT_SW 0
#define REG_EXT_UW 1
#define REG_EXT_NOT 2
#define REG_EXT_NONE 3


#define AU_NONE 0
#define AU_SW 1
#define AU_UW 2
#define AU_NEG 3
#define AU_SW 0
#define AU_UW 1
#define AU_NEG 2
#define AU_NONE 3

#define ATOMIC_B 0
#define ATOMIC_H 1
#define ATOMIC_S 2
#define ATOMIC_D 3

#define SETC_NONE 0
#define SETC_SW 1
#define SETC_UW 2
#define SETC_SW 0
#define SETC_UW 1
#define SETC_NONE 3

#define SRC_FVEC_VT_1 0b0000000
#define SRC_FVEC_VT_4 0b0000011
Expand Down
1 change: 1 addition & 0 deletions target/linx/cpu_user.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@
#define xA4 6
#define xA5 7
#define xA6 8
#define xA7 9
#define xX1 21 /* syscall number */

#endif
Loading