avs: validate PTO ISA v0.2 QEMU Tile profiles

[jiale-wangOwO]

Summary

• add exact-value AVS coverage for the PTO ISA v0.2 Tile target on the LinxISA v0.57 encoding profile
• retain the PTO ISA v0.1 baseline for operations unchanged by v0.2
• organize the suite by broad TMA, CUBE, TEPL, and cross-family groups
• consolidate low-level execution carriers into one CUBE assembly file and one TEPL assembly file
• cover packed predicates and selection, signed narrow and FP16/BF16 arithmetic, reductions, expand/layout/partial operations, dequantization, TGEMV variants, TMATMUL_BIAS, interleave/de-interleave, and partial arg selection
• publish the QEMU support matrix and cross-model handoff for LinxISA/SuperScalarModel#31
• update the QEMU submodule to the implementation in target/linx: execute PTO ISA v0.2 Tile profiles qemu#39

Depends on LinxISA/qemu#39. This PR should remain draft until that QEMU PR merges; after merge, the submodule gitlink must be advanced to the upstream QEMU merge commit before this PR is marked ready.

Version scope

• previous semantic baseline: PTO ISA v0.1
• current semantic target: PTO ISA v0.2
• encoding profile: LinxISA v0.57

The 111-operation count is the complete v0.2 target set, not the number of operations newly introduced in v0.2. Earlier commit subjects that mention v0.57 refer to the LinxISA encoding profile; history is preserved to avoid force-pushing an open PR.

Current support evidence

• TMA: 6/6 operations have execution paths
• CUBE: 5/8 operations have execution paths
• TEPL: 86/97 selectors have explicit execution paths
• total: 97/111 operations
• remaining fail-closed: 14

An execution path means at least one defined profile changes Tile, ACC, or memory state. It does not imply complete dtype, layout, shape, rounding, exception, or target-profile coverage. TQUANT, MX profiles, unresolved implicit-destination or variable-operand forms, and Pipe/control operations remain fail-closed.

Validation

• QEMU=$PWD/emulator/qemu/build/qemu-system-linx64 LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite tile --timeout 40
• QEMU incremental ninja qemu-system-linx64
• call/ret contract
• QEMU opcode metadata sync
• ISA/QEMU L1 coverage report generation
• repository layout policy
• git diff --check in the superproject and QEMU submodule
• python3 docs/check_documentation.py --root .

The documentation gate passes generated SVG and instruction/group-page checks, but the repository baseline reports stale docs/zh/translation-manifest.json source/translation hashes. This PR does not rewrite unrelated translation freshness metadata.

The full AVS --all run has an existing unrelated liveness blocker at DeepSeek test 0x00001702; focused Tile PASS is not presented as a full-suite PASS.

Submodules

• The QEMU SHA is intentional and limited to target/linx: execute PTO ISA v0.2 Tile profiles qemu#39
• .gitmodules URLs are unchanged
• Update the gitlink to the upstream merge commit after target/linx: execute PTO ISA v0.2 Tile profiles qemu#39 merges

[gemini-code-assist]

Caution

The consumer version of Gemini Code Assist on GitHub has been sunset. All code review activity has officially ceased.

[zhoubot]

This should remain draft and unmerged until LinxISA/qemu#39 is corrected and merged, then the gitlink is advanced to its upstream merge commit as the PR body requires. Also, the focused Tile gate skips the TMA descriptor/layout/padding tests: avs/qemu/tests/10_tile_tma.cpp:9-10 defaults LINX_TEST_ENABLE_TMA_DESC to 0, while run_tests.py:1281-1287 only emits macros registered in SUITES and never enables this one. Please enable it for --suite tile or narrow the L3 claims. The machine-readable coverage report still marks L2/L3 unavailable for this QEMU head, no CI checks are reported, and docs/bringup/qemu_pto_tile_support.md:167 says 18 fail-closed operations while the same page reports 14.

[jiale-wangOwO]

Review fixes are pushed in commit 80d3b064; this PR remains draft and the QEMU gitlink has not been advanced.

Changes:

• --suite tile now emits -DLINX_TEST_ENABLE_TMA_DESC=1, so the normal focused gate executes NORM, ND/NZ, padding, non-power-of-two, and ordering coverage;
• corrected the padding oracle to compare the 8x8 source against the 16x64 destination view using its 64-element row stride;
• added same-ACR negative TEPL AVS cases for FP16 TEXP and BF16 TLOG; trap return stores the surviving queue head and verifies all 1024 lanes, proving no rejected output publication;
• updated the support document, corrected 18 fail-closed operations to 14, and explicitly kept machine-readable L2/L3 as unavailable.

Local gates:

• python3 -m unittest avs.qemu.test_run_tests: 17 PASS
• python3 tools/isa/check_pto_v057_manifest.py --root .: PASS
• focused verbose Tile suite with QEMU commit 983afe0b42: PASS, including IDs 0x000A000E through 0x000A0011, 0x000A000B, 0x000A0029, and 0x000A002A.
• python3 docs/check_documentation.py --root .: remaining failure is the pre-existing stale docs/zh/translation-manifest.json freshness metadata; generated SVG and instruction-page checks pass.

Per the review requirement, the gitlink will only be advanced after LinxISA/qemu#39 is merged, using its upstream merge commit.

[gemini-code-assist]

Caution

The consumer version of Gemini Code Assist on GitHub has been sunset. All code review activity has officially ceased.

[zhoubot]

Validated against merged QEMU commit 50e3e9a74a3e8d315b87944d21858392a0dcfb72. The Tile suite enables the descriptor lane, verifies corrected ND/NZ padding indexing, exercises exact FP32/FP16/BF16 TCVT encodings, and retains same-ACR negative rejection checks 0xA0029/0xA002A. Required descriptor IDs 0xA000E-0xA0011, manifest, opcode/meta sync, repository layout, and call/ret audit pass. Full AVS still reaches the documented unrelated DeepSeek 0x1702 liveness blocker; strict L1 coverage remains an unchanged baseline gap.

[zhoubot]

Final re-review after refreshing translation-manifest hashes. All protected CI jobs now pass (guards, docs, lint, model, avs-contract). The exact merged-QEMU Tile AVS and local cross-stack gates remain green.