feat(isa): Add 32-bit CAS and DMA instructions to v0.56

[fengzhazha]

Summary

This PR adds 5 new 32-bit instructions to LinxISA v0.56:

• CASB/CASH/CASW/CASD: Atomic compare-and-swap operations (byte/halfword/word/doubleword)
• DMA: DMA transfer operation

New Instructions

Atomic Compare-And-Swap (CAS)

Instruction	Encoding	Description
CASB	6..4=001, 3..1=101, 14..12=000	Compare-and-swap byte
CASH	6..4=001, 3..1=101, 14..12=001	Compare-and-swap halfword
CASW	6..4=001, 3..1=101, 14..12=010	Compare-and-swap word
CASD	6..4=001, 3..1=101, 14..12=011	Compare-and-swap doubleword

Assembly format: casb<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd}

Semantics:

old = [SrcL]
if (old == SrcR) [SrcL] = SrcD
RegDst = old

Features:

• 4 independent 5-bit register operands
• Supports aq (acquire) and rl (release) memory ordering
• Does NOT support far flag (use 48-bit HL.CAS* for remote cache operations)

DMA Operation

Instruction	Encoding	Description
DMA	6..4=000, 3..1=101, 14..12=111	DMA transfer operation

Assembly format: dma [SrcL], SrcR

Encoding Space Allocation

The new instructions use previously unused encoding slots:

• CAS group: 6..4=3'b001, 3..1=3'b101 (new allocation, separate from existing atomics)
• DMA: 6..4=3'b000, 3..1=3'b101, 14..12=3'b111 (fills gap in atomic group)

No conflicts with existing instructions:

• LR.*: 14..12=000
• SC.*: 14..12=001
• LW.*: 14..12=010
• LD.*: 14..12=100
• SD.*: 14..12=101
• SWAP*: 14..12=110

Changes

Core Definition Files

• isa/v0.56/opcodes/lx_32.opc - Added instruction definitions
• isa/v0.56/meta.json - Updated version notes
• isa/v0.56/linxisa-v0.56.json - Recompiled instruction catalog

Tools

• tools/isa/gen_instruction_fragments.py - Fixed 32-bit CAS description generation

Documentation

• docs/isa/blockIntro/sys_block/atomic.md - Uncommented and updated CAS section
• docs/isa/blockIntro/sys_block/instlist.md - Added instruction list entries
• docs/change_log/update_v0.56_cas_dma.md - Comprehensive changelog
• docs/architecture/isa-manual/src/generated/instructions/*.adoc - Auto-generated reference docs

Validation

✅ Encoding conflict check passed (validate_spec.py)
✅ JSON spec compiled successfully with all 5 new instructions
✅ Auto-generated documentation complete
✅ All register operands use full 5-bit encoding (r0-r31 accessible)

Comparison with 48-bit HL.CAS*

Feature	32-bit CAS	48-bit HL.CAS*
Length	32 bits	48 bits
Registers	4 independent	4 independent
Memory ordering	aq, rl, aqrl	aq, rl, f, aqrl, aqf, rlf, aqrlf
Far flag	❌	✅
Code density	Higher	Lower
Use case	Local cache	Remote cache / distributed

Recommendation: Use 32-bit CAS for typical single-node synchronization; use 48-bit HL.CAS* when far flag is required.

Testing

Please verify:

• Assembler recognizes new mnemonics
• Disassembler decodes correctly
• Simulator implements CAS and DMA semantics
• Hardware decode logic handles new encoding groups

---

📋 Detailed changelog: update_v0.56_cas_dma.md

[gemini-code-assist]

Code Review

This pull request introduces 32-bit atomic Compare-And-Swap (CAS) instructions (CASB, CASH, CASW, CASD) and a DMA operation instruction to LinxISA v0.56, updating core opcode definitions, metadata, and documentation. The review feedback highlights a logic bug in the reference counting assembly example where the retry label is placed after the load instruction, as well as minor formatting and syntax inconsistencies in the documentation tables.

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[gemini-code-assist]

The reference counting CAS loop example contains a logic bug. The retry label is placed after the ld instruction, which means if the CAS operation fails (due to another thread modifying the refcount), the loop will retry without reloading the updated refcount value from memory into x10. This will result in an infinite loop or incorrect behavior under contention. Moving the retry label before the ld instruction resolves this issue.

Suggested change

	incr_refcount:
	ld [refcount], ->x10
	retry:
	addi x10, 1, ->x11 # Increment
	casd.aq [refcount], x10, x11, ->x12
	b.ne x10, x12, retry # Retry if value changed
	incr_refcount:
	retry:
	ld [refcount], ->x10
	addi x10, 1, ->x11 # Increment
	casd.aq [refcount], x10, x11, ->x12
	b.ne x10, x12, retry # Retry if value changed

[gemini-code-assist]

The newly added instructions CASB, CASH, CASW, CASD and DMA are listed as plain text, which is inconsistent with the other instructions in the table that link to their respective reference markdown files. They should be formatted as links to maintain consistency and completeness.

Suggested change

	| **Atomic Compare-And-Swap** | CASB, CASH, CASW, CASD |
	| **DMA Operation** | DMA |
	| **Atomic Compare-And-Swap** | [CASB](../../inst/misa_s/CASB.md), [CASH](../../inst/misa_s/CASH.md), [CASW](../../inst/misa_s/CASW.md), [CASD](../../inst/misa_s/CASD.md) |
	| **DMA Operation** | [DMA](../../inst/misa_s/DMA.md) |

[gemini-code-assist]

The assembly format for the new CAS instructions in the table uses <{.aq,.rl,.aqrl}> instead of the official syntax <.{aq, rl, aqrl}> defined in lx_32.opc and the generated .adoc reference files. Updating this will ensure consistency across the documentation and the ISA specification.

Suggested change

	| CASB | casb<{.aq,.rl,.aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | Memory-register compare-and-swap **byte** |
	| CASH | cash<{.aq,.rl,.aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | Memory-register compare-and-swap **halfword** |
	| CASW | casw<{.aq,.rl,.aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | Memory-register compare-and-swap **word** |
	| CASD | casd<{.aq,.rl,.aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | Memory-register compare-and-swap **doubleword** |
	| CASB | casb<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | Memory-register compare-and-swap **byte** |
	| CASH | cash<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | Memory-register compare-and-swap **halfword** |
	| CASW | casw<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | Memory-register compare-and-swap **word** |
	| CASD | casd<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | Memory-register compare-and-swap **doubleword** |