Feat/dstorage transport

[khalilswdp]

Summary

On Windows, big expert-miss reads go through pread and are CPU/copy-bound
well below what the SSD can deliver. This PR adds a DirectStorage transport:
COLI_DSTORAGE=1 serves the coalesced expert-slab disk reads via DirectStorage
instead of pread (primary replica only; the dual-SSD mirror keeps its stock
path), and the VRAM-side arena API ships alongside for the VRAM-depot PR's
startup fill.

Opt-in twice over, so the smallest change that engages it is zero: the DLL only
gains the code when built with DSTORAGE_HOME (the entry points are optional
exports; dstorage.dll is loaded dynamically at runtime), and the engine only
uses it when COLI_DSTORAGE=1. Any failure falls back cleanly to pread.

Hard-won notes live in the backend_dstorage.cpp header: never take the
default D3D12 adapter (it's the display adapter — on hybrid boxes an iGPU
whose resources CUDA cannot import; enumerate DXGI for the NVIDIA one); the
arena splits into ≤2 GiB chunks (destination offsets past 4 GiB wrap on this
stack); every chunk gets D3D12_RESIDENCY_PRIORITY_MAXIMUM (a demoted page
means a torn DMA write); reads chunk at 16 MB against a 128 MB staging buffer.

Stacked on the Windows-suite PR (its commits ride along until it merges;
feat(win): DirectStorage expert-load transport is the only new content).

Possible next step on Linux: the engine already batches expert reads via
io_uring (uring.h); routing this same coalesced slab read through io_uring
(O_DIRECT + registered buffers) would be the natural counterpart there.

Validation

• make -C c check — full pass at this tip (Windows, mingw-w64 gcc 16.1);
  warning set identical to dev's own baseline on the same toolchain.
  Token-exact oracle: 32/32 TF, 20/20 greedy with the flag unset, and a
  pread-vs-DS A/B on a tiny int4 container produced byte-identical output
  (the transport delivers the same raw file bytes into the same slab).
• make -C c cuda-test — n/a for the transport (backend_dstorage.cpp is
  _WIN32-only and compiles only with DSTORAGE_HOME); backend_cuda.cu
  kernel code is untouched, and the loader-side symbols are optional.
• Performance (i5-13400 · 32 GB DDR4 · RTX 5080 16 GB · NVMe; GLM-5.2
  358 GB int4):
  - Transport microbench (dsbench harness, 64 GB cold file, random
  4K-aligned offsets, interleaved arms): 19 MB slabs 2.25 GB/s pread →
  3.7–4.2 GB/s DS (+65–85%); 38 MB slabs 2.24 → 5.05 GB/s (+125%). On an
  HDD both arms are seek-bound at parity (~220 MB/s) — the win is
  NVMe-class only.
  - Engine A/B in a deliberately miss-heavy config (RAM_GB=13 CTX=2048,
  ~2% hit rate, 3 interleaved rounds, frozen .coli_usage, 48-token
  generations): decode 0.13/0.13/0.13 → 0.18/0.18/0.18 tok/s (+38%),
  prefill −23%, ~630 GB/run served via DS at ~1.9 GB/s sustained. In
  tuned configs (20%+ hit rate) the gap compresses — this is a
  disk-bound-regime win, which is exactly when the flag matters.

Compatibility

• The default CPU build remains dependency-free — nothing new compiles
  without DSTORAGE_HOME, and no default dependency is added anywhere.
• No model files, generated binaries, or benchmark artifacts are included
  (the DirectStorage redistributable DLLs are gitignored, not vendored).

Engine defaults changed: none (COLI_DSTORAGE unset = stock pread path).