GitHub - Juliofat/Lab_Monociclo: Implementação do processador riscv mononociclo ADD, SUB, AND, OR, SLT, LW, SW E BEQ

Implementação em SystemVerilog de um processador RISC-V de ciclo único, baseada no Capítulo 4 de Patterson & Hennessy — Computer Organization and Design (RISC-V Edition).

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
sc_alu.sv		sc_alu.sv
sc_alu_ctrl.sv		sc_alu_ctrl.sv
sc_control.sv		sc_control.sv
sc_cpu.sv		sc_cpu.sv
sc_cpu_tb.sv		sc_cpu_tb.sv
sc_datapath.sv		sc_datapath.sv
sc_dmem.sv		sc_dmem.sv
sc_imem.sv		sc_imem.sv
sc_regfile.sv		sc_regfile.sv
sc_sign_ext.sv		sc_sign_ext.sv
sc_top.sv		sc_top.sv

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