VHDL--Advanced-Digital-Design

Mostly VHDL, Lab 6 is Verilog

Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
Lab_1.sim/sim_1/behav/xsim		Lab_1.sim/sim_1/behav/xsim
Lab_1_1.srcs		Lab_1_1.srcs
Lab_2_noErrors.sim/sim_1/behav/xsim		Lab_2_noErrors.sim/sim_1/behav/xsim
Lab_2_noErrors.srcs		Lab_2_noErrors.srcs
imports		imports
lab6		lab6
new		new
sources_1		sources_1
Lab_2_noErrors.xpr		Lab_2_noErrors.xpr
MULT_TOP_tb.tcl		MULT_TOP_tb.tcl
README.md		README.md
flipflop.vhd		flipflop.vhd
mult.c		mult.c

Provide feedback