🛠️
Building
Just a curious soul interested low-level computer architecture and systems design in hardware and software of custom workloads.
Popular repositories Loading
-
-
RISCV-32I
RISCV-32I PublicRTL implementation of RISCV-32I 5-stage pipelined core with hazard handling and data forwarding
Verilog
-
-
-
-
RISC-VxNVDLA
RISC-VxNVDLA PublicSoC architecture verification consisting NVDLA and RISC-V targeted for computer vision workloads
C++
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.