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Added digital IC subcircuits and simulation files #537

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51 changes: 51 additions & 0 deletions library/SubcircuitLibrary/74ALS640/74ALS640.cir
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.title KiCad schematic
U29 unconnected-_U29-Pad1_ Net-_U1-Pad9_ Net-_U29-Pad3_ d_nand
U7 unconnected-_U7-Pad1_ Net-_U28-Pad1_ d_inverter
U28 Net-_U28-Pad1_ Net-_U1-Pad9_ Net-_U28-Pad3_ d_and
U14 Net-_U1-Pad10_ Net-_U14-Pad2_ d_inverter
U40 Net-_U24-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad18_ d_and
U24 Net-_U24-Pad1_ Net-_U1-Pad9_ Net-_U24-Pad3_ d_and
U23 Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_U23-Pad3_ d_nand
U25 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U25-Pad3_ d_nand
U12 Net-_U1-Pad10_ Net-_U12-Pad2_ d_inverter
U39 Net-_U23-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad13_ d_and
U41 Net-_U25-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad14_ d_and
U6 unconnected-_U6-Pad1_ Net-_U26-Pad1_ d_inverter
U5 Net-_U1-Pad4_ Net-_U24-Pad1_ d_inverter
U26 Net-_U26-Pad1_ Net-_U1-Pad9_ Net-_U26-Pad3_ d_and
U27 unconnected-_U27-Pad1_ Net-_U1-Pad9_ Net-_U27-Pad3_ d_nand
U13 Net-_U1-Pad10_ Net-_U13-Pad2_ d_inverter
U42 Net-_U26-Pad3_ Net-_U14-Pad2_ unconnected-_U42-Pad3_ d_and
U43 Net-_U27-Pad3_ Net-_U14-Pad2_ unconnected-_U43-Pad3_ d_and
U45 Net-_U29-Pad3_ Net-_U15-Pad2_ unconnected-_U45-Pad3_ d_and
U44 Net-_U28-Pad3_ Net-_U15-Pad2_ unconnected-_U44-Pad3_ d_and
U48 Net-_U32-Pad3_ Net-_U17-Pad2_ unconnected-_U48-Pad3_ d_and
U49 Net-_U33-Pad3_ Net-_U17-Pad2_ unconnected-_U49-Pad3_ d_and
U47 Net-_U31-Pad3_ Net-_U16-Pad2_ unconnected-_U47-Pad3_ d_and
U46 Net-_U30-Pad3_ Net-_U16-Pad2_ unconnected-_U46-Pad3_ d_and
U9 unconnected-_U9-Pad1_ Net-_U32-Pad1_ d_inverter
U16 Net-_U1-Pad10_ Net-_U16-Pad2_ d_inverter
U32 Net-_U32-Pad1_ Net-_U1-Pad9_ Net-_U32-Pad3_ d_and
U17 Net-_U1-Pad10_ Net-_U17-Pad2_ d_inverter
U33 unconnected-_U33-Pad1_ Net-_U1-Pad9_ Net-_U33-Pad3_ d_nand
U8 unconnected-_U8-Pad1_ Net-_U30-Pad1_ d_inverter
U31 unconnected-_U31-Pad1_ Net-_U1-Pad9_ Net-_U31-Pad3_ d_nand
U30 Net-_U30-Pad1_ Net-_U1-Pad9_ Net-_U30-Pad3_ d_and
U15 Net-_U1-Pad10_ Net-_U15-Pad2_ d_inverter
U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT
U4 Net-_U1-Pad3_ Net-_U22-Pad1_ d_inverter
U3 Net-_U1-Pad2_ Net-_U20-Pad1_ d_inverter
U22 Net-_U22-Pad1_ Net-_U1-Pad9_ Net-_U22-Pad3_ d_and
U11 Net-_U1-Pad10_ Net-_U11-Pad2_ d_inverter
U20 Net-_U20-Pad1_ Net-_U1-Pad9_ Net-_U20-Pad3_ d_and
U21 Net-_U1-Pad6_ Net-_U1-Pad9_ Net-_U21-Pad3_ d_nand
U34 Net-_U18-Pad3_ Net-_U10-Pad2_ Net-_U1-Pad15_ d_and
U35 Net-_U19-Pad3_ Net-_U10-Pad2_ Net-_U1-Pad11_ d_and
U36 Net-_U20-Pad3_ Net-_U11-Pad2_ Net-_U1-Pad16_ d_and
U37 Net-_U21-Pad3_ Net-_U11-Pad2_ Net-_U1-Pad12_ d_and
U38 Net-_U22-Pad3_ Net-_U12-Pad2_ Net-_U1-Pad17_ d_and
U10 Net-_U1-Pad10_ Net-_U10-Pad2_ d_inverter
U2 Net-_U1-Pad1_ Net-_U18-Pad1_ d_inverter
U18 Net-_U18-Pad1_ Net-_U1-Pad9_ Net-_U18-Pad3_ d_and
U19 Net-_U1-Pad5_ Net-_U1-Pad9_ Net-_U19-Pad3_ d_nand
.end
204 changes: 204 additions & 0 deletions library/SubcircuitLibrary/74ALS640/74ALS640.cir.out
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.title kicad schematic

* u29 unconnected-_u29-pad1_ net-_u1-pad9_ net-_u29-pad3_ d_nand
* u7 unconnected-_u7-pad1_ net-_u28-pad1_ d_inverter
* u28 net-_u28-pad1_ net-_u1-pad9_ net-_u28-pad3_ d_and
* u14 net-_u1-pad10_ net-_u14-pad2_ d_inverter
* u40 net-_u24-pad3_ net-_u13-pad2_ net-_u1-pad18_ d_and
* u24 net-_u24-pad1_ net-_u1-pad9_ net-_u24-pad3_ d_and
* u23 net-_u1-pad7_ net-_u1-pad9_ net-_u23-pad3_ d_nand
* u25 net-_u1-pad8_ net-_u1-pad9_ net-_u25-pad3_ d_nand
* u12 net-_u1-pad10_ net-_u12-pad2_ d_inverter
* u39 net-_u23-pad3_ net-_u12-pad2_ net-_u1-pad13_ d_and
* u41 net-_u25-pad3_ net-_u13-pad2_ net-_u1-pad14_ d_and
* u6 unconnected-_u6-pad1_ net-_u26-pad1_ d_inverter
* u5 net-_u1-pad4_ net-_u24-pad1_ d_inverter
* u26 net-_u26-pad1_ net-_u1-pad9_ net-_u26-pad3_ d_and
* u27 unconnected-_u27-pad1_ net-_u1-pad9_ net-_u27-pad3_ d_nand
* u13 net-_u1-pad10_ net-_u13-pad2_ d_inverter
* u42 net-_u26-pad3_ net-_u14-pad2_ unconnected-_u42-pad3_ d_and
* u43 net-_u27-pad3_ net-_u14-pad2_ unconnected-_u43-pad3_ d_and
* u45 net-_u29-pad3_ net-_u15-pad2_ unconnected-_u45-pad3_ d_and
* u44 net-_u28-pad3_ net-_u15-pad2_ unconnected-_u44-pad3_ d_and
* u48 net-_u32-pad3_ net-_u17-pad2_ unconnected-_u48-pad3_ d_and
* u49 net-_u33-pad3_ net-_u17-pad2_ unconnected-_u49-pad3_ d_and
* u47 net-_u31-pad3_ net-_u16-pad2_ unconnected-_u47-pad3_ d_and
* u46 net-_u30-pad3_ net-_u16-pad2_ unconnected-_u46-pad3_ d_and
* u9 unconnected-_u9-pad1_ net-_u32-pad1_ d_inverter
* u16 net-_u1-pad10_ net-_u16-pad2_ d_inverter
* u32 net-_u32-pad1_ net-_u1-pad9_ net-_u32-pad3_ d_and
* u17 net-_u1-pad10_ net-_u17-pad2_ d_inverter
* u33 unconnected-_u33-pad1_ net-_u1-pad9_ net-_u33-pad3_ d_nand
* u8 unconnected-_u8-pad1_ net-_u30-pad1_ d_inverter
* u31 unconnected-_u31-pad1_ net-_u1-pad9_ net-_u31-pad3_ d_nand
* u30 net-_u30-pad1_ net-_u1-pad9_ net-_u30-pad3_ d_and
* u15 net-_u1-pad10_ net-_u15-pad2_ d_inverter
* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port
* u4 net-_u1-pad3_ net-_u22-pad1_ d_inverter
* u3 net-_u1-pad2_ net-_u20-pad1_ d_inverter
* u22 net-_u22-pad1_ net-_u1-pad9_ net-_u22-pad3_ d_and
* u11 net-_u1-pad10_ net-_u11-pad2_ d_inverter
* u20 net-_u20-pad1_ net-_u1-pad9_ net-_u20-pad3_ d_and
* u21 net-_u1-pad6_ net-_u1-pad9_ net-_u21-pad3_ d_nand
* u34 net-_u18-pad3_ net-_u10-pad2_ net-_u1-pad15_ d_and
* u35 net-_u19-pad3_ net-_u10-pad2_ net-_u1-pad11_ d_and
* u36 net-_u20-pad3_ net-_u11-pad2_ net-_u1-pad16_ d_and
* u37 net-_u21-pad3_ net-_u11-pad2_ net-_u1-pad12_ d_and
* u38 net-_u22-pad3_ net-_u12-pad2_ net-_u1-pad17_ d_and
* u10 net-_u1-pad10_ net-_u10-pad2_ d_inverter
* u2 net-_u1-pad1_ net-_u18-pad1_ d_inverter
* u18 net-_u18-pad1_ net-_u1-pad9_ net-_u18-pad3_ d_and
* u19 net-_u1-pad5_ net-_u1-pad9_ net-_u19-pad3_ d_nand
a1 [unconnected-_u29-pad1_ net-_u1-pad9_ ] net-_u29-pad3_ u29
a2 unconnected-_u7-pad1_ net-_u28-pad1_ u7
a3 [net-_u28-pad1_ net-_u1-pad9_ ] net-_u28-pad3_ u28
a4 net-_u1-pad10_ net-_u14-pad2_ u14
a5 [net-_u24-pad3_ net-_u13-pad2_ ] net-_u1-pad18_ u40
a6 [net-_u24-pad1_ net-_u1-pad9_ ] net-_u24-pad3_ u24
a7 [net-_u1-pad7_ net-_u1-pad9_ ] net-_u23-pad3_ u23
a8 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u25-pad3_ u25
a9 net-_u1-pad10_ net-_u12-pad2_ u12
a10 [net-_u23-pad3_ net-_u12-pad2_ ] net-_u1-pad13_ u39
a11 [net-_u25-pad3_ net-_u13-pad2_ ] net-_u1-pad14_ u41
a12 unconnected-_u6-pad1_ net-_u26-pad1_ u6
a13 net-_u1-pad4_ net-_u24-pad1_ u5
a14 [net-_u26-pad1_ net-_u1-pad9_ ] net-_u26-pad3_ u26
a15 [unconnected-_u27-pad1_ net-_u1-pad9_ ] net-_u27-pad3_ u27
a16 net-_u1-pad10_ net-_u13-pad2_ u13
a17 [net-_u26-pad3_ net-_u14-pad2_ ] unconnected-_u42-pad3_ u42
a18 [net-_u27-pad3_ net-_u14-pad2_ ] unconnected-_u43-pad3_ u43
a19 [net-_u29-pad3_ net-_u15-pad2_ ] unconnected-_u45-pad3_ u45
a20 [net-_u28-pad3_ net-_u15-pad2_ ] unconnected-_u44-pad3_ u44
a21 [net-_u32-pad3_ net-_u17-pad2_ ] unconnected-_u48-pad3_ u48
a22 [net-_u33-pad3_ net-_u17-pad2_ ] unconnected-_u49-pad3_ u49
a23 [net-_u31-pad3_ net-_u16-pad2_ ] unconnected-_u47-pad3_ u47
a24 [net-_u30-pad3_ net-_u16-pad2_ ] unconnected-_u46-pad3_ u46
a25 unconnected-_u9-pad1_ net-_u32-pad1_ u9
a26 net-_u1-pad10_ net-_u16-pad2_ u16
a27 [net-_u32-pad1_ net-_u1-pad9_ ] net-_u32-pad3_ u32
a28 net-_u1-pad10_ net-_u17-pad2_ u17
a29 [unconnected-_u33-pad1_ net-_u1-pad9_ ] net-_u33-pad3_ u33
a30 unconnected-_u8-pad1_ net-_u30-pad1_ u8
a31 [unconnected-_u31-pad1_ net-_u1-pad9_ ] net-_u31-pad3_ u31
a32 [net-_u30-pad1_ net-_u1-pad9_ ] net-_u30-pad3_ u30
a33 net-_u1-pad10_ net-_u15-pad2_ u15
a34 net-_u1-pad3_ net-_u22-pad1_ u4
a35 net-_u1-pad2_ net-_u20-pad1_ u3
a36 [net-_u22-pad1_ net-_u1-pad9_ ] net-_u22-pad3_ u22
a37 net-_u1-pad10_ net-_u11-pad2_ u11
a38 [net-_u20-pad1_ net-_u1-pad9_ ] net-_u20-pad3_ u20
a39 [net-_u1-pad6_ net-_u1-pad9_ ] net-_u21-pad3_ u21
a40 [net-_u18-pad3_ net-_u10-pad2_ ] net-_u1-pad15_ u34
a41 [net-_u19-pad3_ net-_u10-pad2_ ] net-_u1-pad11_ u35
a42 [net-_u20-pad3_ net-_u11-pad2_ ] net-_u1-pad16_ u36
a43 [net-_u21-pad3_ net-_u11-pad2_ ] net-_u1-pad12_ u37
a44 [net-_u22-pad3_ net-_u12-pad2_ ] net-_u1-pad17_ u38
a45 net-_u1-pad10_ net-_u10-pad2_ u10
a46 net-_u1-pad1_ net-_u18-pad1_ u2
a47 [net-_u18-pad1_ net-_u1-pad9_ ] net-_u18-pad3_ u18
a48 [net-_u1-pad5_ net-_u1-pad9_ ] net-_u19-pad3_ u19
* Schematic Name: d_nand, Ngspice Name: d_nand
.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, Ngspice Name: d_nand
.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, Ngspice Name: d_nand
.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u41 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, Ngspice Name: d_nand
.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u43 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u45 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u44 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u46 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, Ngspice Name: d_nand
.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, Ngspice Name: d_nand
.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, Ngspice Name: d_nand
.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_inverter, Ngspice Name: d_inverter
.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_and, Ngspice Name: d_and
.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
* Schematic Name: d_nand, Ngspice Name: d_nand
.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
.tran 0e-00 0e-00 0e-00

* Control Statements
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
.endc
.end
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