feat: add VLSI Global Placement benchmark (Frontier-Eng)

[y-ji24]

Summary

This PR adds a new Frontier-Eng benchmark for VLSI Global Placement, based on the ISPD 2005 placement benchmark suite.

The task requires an agent to generate legal placements for movable components while minimizing Half-Perimeter Wirelength (HPWL) under placement constraints.

The benchmark includes two representative datasets with different difficulty levels:

• adaptec1 (Easy)
• adaptec3 (Medium)

Highlights

Benchmark

• Based on the ISPD 2005 placement benchmarks
• Deterministic evaluation
• Independent HPWL and legality computation
• Pure Python implementation using only the standard library

Agent Interface

The agent can modify only the place_components() function in scripts/init.py, which is enclosed by an EVOLVE-BLOCK. All evaluation logic, data loading, and output interfaces remain read-only.

Evaluation

The evaluator independently verifies:

• Half-Perimeter Wirelength (HPWL)
• Cell overlap
• Out-of-bound placement
• Fixed-cell movement
• Missing cells

A candidate is considered valid only if all legality constraints are satisfied.

Baseline

A deterministic row-based placement baseline is provided.

The baseline:

• produces legal placements,
• is fully deterministic,
• serves as a simple optimization starting point for Frontier-Eng agents.

Repository Structure

This benchmark follows the standard Frontier-Eng layout, including:

• scripts/
• verification/
• baseline/
• references/
• frontier_eval/

with scripts/init.py as the only editable source file.

Verification

Verified on both benchmarks.

Benchmark	Difficulty	Valid	HPWL	Overlaps	OOB	Fixed Moved
adaptec1	Easy	✅	1.32e9	0	0	0
adaptec3	Medium	✅	4.98e9	0	0	0

Runtime:

• adaptec1: ~5.5 s
• adaptec3: ~12.2 s

Docker Support

Containerized evaluation is supported through verification/docker/Dockerfile.

Notes

To reduce repository size, the benchmark stores netlists in a compact index-based representation. During loading, the representation is deterministically expanded into the original in-memory format. This compression is lossless and does not affect placement, legality checking, or HPWL computation.

Only two datasets (adaptec1 and adaptec3) are included in this benchmark. Frontier-Eng benchmarks are not required to include every instance from the original ISPD 2005 benchmark suite; representative instances covering different difficulty levels are sufficient.

[github-actions]

🤖 AI Code Review (gemini-3-flash-preview)

🇬🇧 English Analysis

1. Executive Summary

• Core Purpose: This PR introduces a new benchmark task for VLSI Global Placement, a critical stage in the Electronic Design Automation (EDA) physical design flow. It leverages industry-standard ISPD 2005 contest benchmarks (adaptec1, adaptec3) to evaluate an agent's ability to minimize Half-Perimeter Wirelength (HPWL) while adhering to strict physical constraints (no overlaps, boundary limits, and fixed cell preservation).
• Modified File Structure & Modifications:
  • .gitattributes: Configures JSON reference files to be treated as binary/non-diffable to handle large datasets.
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/README.md (and _zh-CN.md): Provides comprehensive navigation, quick start guides, and dataset descriptions.
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/Task.md (and _zh-CN.md): Detailed engineering background on the ASIC flow and formal problem definition.
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/baseline/solution.py: Implements a deterministic row-based placement algorithm as a reference.
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/frontier_eval/: Contains metadata files (agent_files.txt, constraints.txt, run_eval.py, etc.) required for integration with the frontier_eval framework.
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/references/: Contains preprocessed JSON versions of the ISPD 2005 benchmarks.

2. AI Content Analysis

• Estimated AI Component: 65%
• Reasoning & Evidence:
  • Documentation Structure: The README and Task files follow a highly structured, "template-like" format common in AI-generated technical documentation (e.g., the "Engineering Background" and "Why HPWL?" sections).
  • Boilerplate Code: The run_eval.py and the file-loading logic in solution.py (using Path(__file__).resolve()) exhibit standard patterns often produced by LLMs for scaffolding.
  • Domain Specificity: While the logic in place_components (row-based greedy placement) is domain-specific, it is a textbook implementation of a basic placement algorithm, which AI can generate accurately given the prompt context.

3. Engineering & Economic Assessment

• Engineering Reality Check: High. This is not a "toy example." The task involves handling hundreds of thousands of cells (210k to 450k), which reflects real-world ASIC design complexity. The inclusion of hard constraints (overlap and boundary checks) and the use of the HPWL metric align perfectly with industrial EDA standards.
• Economic Value: High. Global placement is a foundational problem in chip design. Improvements in placement algorithms directly translate to reduced chip area, lower power consumption, and better timing closure, which are multi-million dollar concerns in semiconductor manufacturing.

4. Quality Assurance

• Verification & Testing:
  • frontier_eval Integration: Yes.
  • task_name: ElectronicDesignAutomation/VLSIGlobalPlacement
  • Execution & Dependencies: The README.md clearly documents the pip install command for verification/requirements.txt and provides specific CLI commands for running the baseline and the evaluator.
• Documentation Quality: Excellent. The PR provides bilingual documentation (English/Chinese). It includes a clear file tree, task summaries, and technical references. No significant grammatical errors or formatting inconsistencies were detected in the provided diff.
• Organizational Structure: Logical and Scalable. The separation of baseline, references, scripts, and verification follows best practices for benchmark repositories.

5. Security & Privacy Check

• Sensitive Files: Clean. The .gitignore correctly excludes temp/, artifacts.json, and debug scripts (_debug_*.py). No .env or API keys were found.
• Absolute Paths: None detected. The code uses relative path resolution via the pathlib library (e.g., Path(__file__).resolve().parent.parent).

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🇨🇳 中文分析

1. 摘要

• 核心目的: 此 PR 引入了一个针对 VLSI 全局布局 (Global Placement) 的新基准测试任务，这是电子设计自动化 (EDA) 物理设计流程中的关键阶段。它利用行业标准的 ISPD 2005 竞赛基准（adaptec1, adaptec3）来评估智能体在遵守严格物理约束（无重叠、边界限制、固定单元不移动）的同时，最小化半周长线长 (HPWL) 的能力。
• 修改的文件结构与变更摘要:
  • .gitattributes: 配置 JSON 参考文件为二进制/不可差异化处理，以应对大数据集。
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/README.md (及 _zh-CN.md): 提供全面的导航、快速入门指南和数据集说明。
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/Task.md (及 _zh-CN.md): 详细介绍了 ASIC 流程的工程背景和正式的问题定义。
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/baseline/solution.py: 实现了一个确定性的行式布局算法作为基准参考。
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/frontier_eval/: 包含集成到 frontier_eval 框架所需的元数据文件（agent_files.txt, constraints.txt, run_eval.py 等）。
  • benchmarks/ElectronicDesignAutomation/VLSIGlobalPlacement/references/: 包含预处理后的 ISPD 2005 基准测试 JSON 文件。

2. AI 成分分析

• 预估 AI 含量: 65%
• 判断依据与证据:
  • 文档结构: README 和 Task 文件遵循高度结构化、模板化的格式，这在 AI 生成的技术文档中非常常见（例如“工程背景”和“为什么选择 HPWL？”章节）。
  • 样板代码: run_eval.py 以及 solution.py 中的文件加载逻辑（使用 Path(__file__).resolve()）表现出 LLM 在构建脚手架时常用的标准模式。
  • 领域专业性: 虽然 place_components 中的逻辑（贪心行式布局）具有领域专业性，但它是基础布局算法的教科书式实现，AI 在给定上下文的情况下可以准确生成。

3. 工程与经济评估

• 工程现实检验: 高。这并非“玩具示例”。该任务涉及处理数十万个单元（21万到45万），反映了真实的 ASIC 设计复杂度。硬约束（重叠和边界检查）的加入以及 HPWL 指标的使用完全符合工业级 EDA 标准。
• 经济价值: 高。全局布局是芯片设计的核心问题。布局算法的改进直接转化为芯片面积的减少、功耗的降低和时序收敛的优化，这些都是半导体制造中涉及数百万美元成本的关键因素。

4. 质量保证

• 验证与测试:
  • frontier_eval 集成: 是。
  • task_name: ElectronicDesignAutomation/VLSIGlobalPlacement
  • 运行与依赖: README.md 清晰地记录了 verification/requirements.txt 的安装命令，并提供了运行基线和评估器的具体 CLI 命令。
• 文档质量: 优秀。PR 提供了中英双语文档。包含清晰的文件树、任务摘要和技术参考文献。在提供的 diff 中未检测到明显的语法错误或格式不一致。
• 组织结构: 逻辑清晰且具备可扩展性。将 baseline、references、scripts 和 verification 分开存放符合基准测试仓库的最佳实践。

5. 安全与隐私检查

• 敏感文件: 未发现异常。.gitignore 正确排除了 temp/、artifacts.json 和调试脚本 (_debug_*.py)。未发现 .env 或 API 密钥。
• 绝对路径: 未检测到。代码通过 pathlib 库使用相对路径解析（例如 Path(__file__).resolve().parent.parent）。