GitHub - 7smd7/MIPS-Single-Cycle: A Verilog implementation of a single-cycle MIPS processor, designed for educational and experimental purposes in digital and computer architecture.

Name		Name	Last commit message	Last commit date
Latest commit History 46 Commits
.gitattributes		.gitattributes
ALU.v		ALU.v
ALUController.v		ALUController.v
And gate.v		And gate.v
DataMem.v		DataMem.v
InstMem.v		InstMem.v
LShift.v		LShift.v
MIPS(Main).v		MIPS(Main).v
Mux 2-1.v		Mux 2-1.v
PC.v		PC.v
RegFile.v		RegFile.v
SCPv0+++ADDI+Inst+Reg-Dst+ALU-Src+Reg-Write+Mem-Read+Mem-Write+Branch.jpg		SCPv0+++ADDI+Inst+Reg-Dst+ALU-Src+Reg-Write+Mem-Read+Mem-Write+Branch.jpg
adder.v		adder.v
controller.v		controller.v
photo_2019-05-17_19-11-19.jpg		photo_2019-05-17_19-11-19.jpg
signext.v		signext.v
testBench.v		testBench.v