Implement VHDL Hardware Concurrency Signatures

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Epic: #75
Target: gitgalaxy/standards/language_standards.py

Context & Strategic Value

Aerospace engineering relies heavily on FPGAs for hard-real-time execution (e.g., radar signal processing and engine control units). Unlike sequential software, VHDL executes concurrently. GitGalaxy must parse these hardware description files to map physical logic gate complexity and real-time hardware I/O.

Implementation Tasks

• Add vhdl to LANGUAGE_DEFINITIONS.
• Define Extensions: .vhd, .vhdl.
• Set lexical_family to line_exclusive (Uses -- for line comments).
• Implement class_start signature: Target entity, architecture.
• Implement concurrency signature: Target process, port map. (This is critical: high density here maps directly to hardware complexity).
• Implement io signature: Target in, out, inout port definitions.

Validation

Scan a standard FPGA radar or arithmetic logic unit (ALU) implementation to ensure concurrency and I/O boundaries are cleanly separated.