Problem Statement
While rhdl materially simplifies FPGA development, developers still need a significant amount of FPGA domain specific knoweldge and productivity is constrained by low-level details.
Proposed Solution: Wingfoil as a Composition Layer
I am exploring using Wingfoil (a graph based stream processing framework) to act as an abstraction layer over rhdl. The idea is to use wingfoil to wire up a graph of calculations that can be emitted as rhdl code and from there used to generate Verilog to run on FPGA. Additionally, wingfoil could be used in the software layer to receive from, process and publish to FPGA.
Any feedback on this or any interest in getting involved would be much appreciated.
Thanks!
Problem Statement
While rhdl materially simplifies FPGA development, developers still need a significant amount of FPGA domain specific knoweldge and productivity is constrained by low-level details.
Proposed Solution: Wingfoil as a Composition Layer
I am exploring using Wingfoil (a graph based stream processing framework) to act as an abstraction layer over rhdl. The idea is to use wingfoil to wire up a graph of calculations that can be emitted as rhdl code and from there used to generate Verilog to run on FPGA. Additionally, wingfoil could be used in the software layer to receive from, process and publish to FPGA.
Any feedback on this or any interest in getting involved would be much appreciated.
Thanks!