Feature gate: #![feature(stdarch_x86_avx512_vl_u32_to_f32_conversions)]
This is a tracking issue for the AVX-512VL intrinsics that convert packed unsigned 32-bit integers to single-precision floating-point values.
These intrinsics correspond to the VCVTUDQ2PS instruction. They are documented in the Intel Software Developer’s Manual, but are not listed in the Intel Intrinsics Guide.
Public API
#[target_feature(enable = "avx512f,avx512vl")]
pub const fn _mm_cvtepu32_ps(a: __m128i) -> __m128 { /* ... */ }
#[target_feature(enable = "avx512f,avx512vl")]
pub const fn _mm_mask_cvtepu32_ps(
src: __m128,
k: __mmask8,
a: __m128i,
) -> __m128 { /* ... */ }
#[target_feature(enable = "avx512f,avx512vl")]
pub const fn _mm_maskz_cvtepu32_ps(
k: __mmask8,
a: __m128i,
) -> __m128 { /* ... */ }
#[target_feature(enable = "avx512f,avx512vl")]
pub const fn _mm256_cvtepu32_ps(a: __m256i) -> __m256 { /* ... */ }
#[target_feature(enable = "avx512f,avx512vl")]
pub const fn _mm256_mask_cvtepu32_ps(
src: __m256,
k: __mmask8,
a: __m256i,
) -> __m256 { /* ... */ }
#[target_feature(enable = "avx512f,avx512vl")]
pub const fn _mm256_maskz_cvtepu32_ps(
k: __mmask8,
a: __m256i,
) -> __m256 { /* ... */ }
Steps / History
(Remember to update the S-tracking-* label when checking boxes.)
Unresolved Questions
None at this time.
Feature gate:
#![feature(stdarch_x86_avx512_vl_u32_to_f32_conversions)]This is a tracking issue for the AVX-512VL intrinsics that convert packed unsigned 32-bit integers to single-precision floating-point values.
These intrinsics correspond to the
VCVTUDQ2PSinstruction. They are documented in the Intel Software Developer’s Manual, but are not listed in the Intel Intrinsics Guide.Public API
Steps / History
(Remember to update the
S-tracking-*label when checking boxes.)Unresolved Questions
None at this time.
Footnotes
https://std-dev-guide.rust-lang.org/feature-lifecycle/stabilization.html ↩