From 129f64df8d140e7170792bb10a9b3319bfbcb57c Mon Sep 17 00:00:00 2001 From: Chao Wang <26245345+ChaoWao@users.noreply.github.com> Date: Wed, 22 Jul 2026 02:32:13 -0700 Subject: [PATCH] Fix: use task_attrs.has_predicate() in the L2 swimlane predicated-skip path #1410 consolidated the per-task dispatch predicates into the TaskAttrs byte, moving has_predicate() from ActiveMask to TaskAttrs and updating the scheduler call sites. It missed the two dummy-drain swimlane-skip calls that #1419 added: a2a3 and a5 tensormap_and_ringbuffer scheduler_dispatch.cpp still call dummy_slot.active_mask.has_predicate(). ActiveMask no longer has that member, so the default build (the calls sit under SIMPLER_DFX, which is on by default) fails to compile a2a3sim / a5sim. The two PRs were each green against their own base; the break only appears once both are on main. Point both call sites at dummy_slot.task_attrs.has_predicate(), matching every other has_predicate() caller in the scheduler. a2a3sim and a5sim build clean. Co-Authored-By: Claude Opus 4.8 (1M context) Co-Authored-By: Sergio Martin --- .../runtime/scheduler/scheduler_dispatch.cpp | 2 +- .../runtime/scheduler/scheduler_dispatch.cpp | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp b/src/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp index ab5a0b34f..c090f94cc 100644 --- a/src/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp +++ b/src/a2a3/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp @@ -1219,7 +1219,7 @@ int32_t SchedulerContext::resolve_and_dispatch(Runtime *runtime, int32_t thread_ sched_l2_swimlane_[thread_idx].sched_loop_count, dummy_consumers ); } - if (dummy_slot.active_mask.has_predicate()) { + if (dummy_slot.task_attrs.has_predicate()) { l2_swimlane_aicpu_record_predicated_skip( thread_idx, dummy_resolve_t0, sched_l2_swimlane_[thread_idx].sched_loop_count, dummy_slot.task->task_id.raw diff --git a/src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp b/src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp index 2651d1532..ca23c9cb1 100644 --- a/src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp +++ b/src/a5/runtime/tensormap_and_ringbuffer/runtime/scheduler/scheduler_dispatch.cpp @@ -1028,7 +1028,7 @@ int32_t SchedulerContext::resolve_and_dispatch(Runtime *runtime, int32_t thread_ #endif #if SIMPLER_DFX if (dummy_resolve_t0 != 0) { - if (dummy_slot.active_mask.has_predicate()) { + if (dummy_slot.task_attrs.has_predicate()) { l2_swimlane_aicpu_record_predicated_skip( thread_idx, dummy_resolve_t0, sched_l2_swimlane_[thread_idx].sched_loop_count, dummy_slot.task->task_id.raw