Component
Passes / Transforms (lib/PTO/Transforms)
Description
TileLang needs scalar GM accesses with data-cache bypass outside a SIMD/SIMT
region. It currently lowers those accesses to:
pto.ldg ... l1cache(uncache)
pto.stg ... l1cache(uncache)
inside the enclosing pto.aicore function.
PTOAS accepts and verifies this IR, even though PTOLdgOp and PTOStgOp
derive from PTO_SimtOp. The VPTO backend then lowers them to
llvm.hivm.ldg.* and llvm.hivm.stg.* calls in the ordinary AICore function.
Bisheng crashes while compiling the generated device LLVM IR.
The same pto.ldg/pto.stg operations work when placed inside a function with
the pto.simt_entry attribute. PTOAS's existing
simt-ldst-policy-core/kernel.pto test compiles successfully.
Reproduction (minimal)
module attributes {
pto.target_arch = "a5",
pto.kernel_kind = #pto.kernel_kind<vector>
} {
func.func @repro_aicore_scalar_ldg(
%src: !pto.ptr<f32, gm>,
%dst: !pto.ptr<f32, gm>
) attributes {pto.aicore} {
%c0 = arith.constant 0 : index
%value = pto.ldg %src[%c0]
l1cache(uncache) l2cache(nmfv)
: !pto.ptr<f32, gm> -> f32
pto.stg %value, %dst[%c0]
l1cache(uncache) l2cache(nmfv)
: !pto.ptr<f32, gm>, f32
return
}
}
Compile with:
ptoas --pto-arch=a5 --pto-backend=vpto \
repro_aicore_scalar_ldg.pto \
-o repro_aicore_scalar_ldg.fatobj.o
Expected behavior
- Support scalar GM cache-bypass load/store in a
pto.aicore function and
lower them to instructions valid in that execution context; or
- If
pto.ldg/pto.stg are only legal inside pto.simt_entry, reject their
use in other functions during PTO verification and provide a clear
diagnostic.
For TileLang integration, a dedicated AICore scalar GM bypass operation would
be useful. Replacing these accesses with ordinary pto.load/pto.store would
lose the required data-cache bypass semantics.
Actual behavior / error logs
Error: device LLVM compilation failed
Command: bisheng --cce-aicore-arch=dav-c310-vec ...
*** stack smashing detected ***: terminated
bisheng: error: clang frontend command failed with exit code 134
clang version 15.0.5
Git commit
a742263
Host platform
None
Target Ascend arch (if relevant)
None
PTOAS build level (if relevant)
None
Component
Passes / Transforms (lib/PTO/Transforms)
Description
TileLang needs scalar GM accesses with data-cache bypass outside a SIMD/SIMT
region. It currently lowers those accesses to:
inside the enclosing
pto.aicorefunction.PTOAS accepts and verifies this IR, even though
PTOLdgOpandPTOStgOpderive from
PTO_SimtOp. The VPTO backend then lowers them tollvm.hivm.ldg.*andllvm.hivm.stg.*calls in the ordinary AICore function.Bisheng crashes while compiling the generated device LLVM IR.
The same
pto.ldg/pto.stgoperations work when placed inside a function withthe
pto.simt_entryattribute. PTOAS's existingsimt-ldst-policy-core/kernel.ptotest compiles successfully.Reproduction (minimal)
module attributes { pto.target_arch = "a5", pto.kernel_kind = #pto.kernel_kind<vector> } { func.func @repro_aicore_scalar_ldg( %src: !pto.ptr<f32, gm>, %dst: !pto.ptr<f32, gm> ) attributes {pto.aicore} { %c0 = arith.constant 0 : index %value = pto.ldg %src[%c0] l1cache(uncache) l2cache(nmfv) : !pto.ptr<f32, gm> -> f32 pto.stg %value, %dst[%c0] l1cache(uncache) l2cache(nmfv) : !pto.ptr<f32, gm>, f32 return } } Compile with: ptoas --pto-arch=a5 --pto-backend=vpto \ repro_aicore_scalar_ldg.pto \ -o repro_aicore_scalar_ldg.fatobj.oExpected behavior
pto.aicorefunction andlower them to instructions valid in that execution context; or
pto.ldg/pto.stgare only legal insidepto.simt_entry, reject theiruse in other functions during PTO verification and provide a clear
diagnostic.
For TileLang integration, a dedicated AICore scalar GM bypass operation would
be useful. Replacing these accesses with ordinary
pto.load/pto.storewouldlose the required data-cache bypass semantics.
Actual behavior / error logs
Git commit
a742263
Host platform
None
Target Ascend arch (if relevant)
None
PTOAS build level (if relevant)
None