From 951646d29020ec5db2b95e31e232ce9cbe37715a Mon Sep 17 00:00:00 2001 From: asanaull Date: Mon, 17 Feb 2020 15:37:13 -0500 Subject: [PATCH 1/3] added digilent genesys2 (kintex7) example --- xilinx/examples/genesys2/Genesys2.xdc | 30 ++++++++++++++++++++++ xilinx/examples/genesys2/kintex7patch.py | 22 ++++++++++++++++ xilinx/examples/genesys2/simpleCircuit.sh | 7 +++++ xilinx/examples/genesys2/simpleCircuit.tcl | 4 +++ xilinx/examples/genesys2/simpleCircuit.v | 5 ++++ 5 files changed, 68 insertions(+) create mode 100644 xilinx/examples/genesys2/Genesys2.xdc create mode 100644 xilinx/examples/genesys2/kintex7patch.py create mode 100755 xilinx/examples/genesys2/simpleCircuit.sh create mode 100644 xilinx/examples/genesys2/simpleCircuit.tcl create mode 100644 xilinx/examples/genesys2/simpleCircuit.v diff --git a/xilinx/examples/genesys2/Genesys2.xdc b/xilinx/examples/genesys2/Genesys2.xdc new file mode 100644 index 000000000..ba30eb857 --- /dev/null +++ b/xilinx/examples/genesys2/Genesys2.xdc @@ -0,0 +1,30 @@ +set_property IOSTANDARD LVCMOS33 [get_ports led[0]] +set_property IOSTANDARD LVCMOS33 [get_ports led[1]] +set_property IOSTANDARD LVCMOS33 [get_ports led[2]] +set_property IOSTANDARD LVCMOS33 [get_ports led[3]] +set_property IOSTANDARD LVCMOS33 [get_ports led[4]] + +set_property LOC T28 [get_ports led[0]] +set_property LOC V19 [get_ports led[1]] +set_property LOC U30 [get_ports led[2]] +set_property LOC U29 [get_ports led[3]] +set_property LOC V20 [get_ports led[4]] + + +set_property IOSTANDARD LVCMOS33 [get_ports sw[0]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[1]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[2]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[3]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[4]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[5]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[6]] +set_property IOSTANDARD LVCMOS33 [get_ports sw[7]] + +set_property LOC G19 [get_ports sw[0]] +set_property LOC G25 [get_ports sw[1]] +set_property LOC H24 [get_ports sw[2]] +set_property LOC K19 [get_ports sw[3]] +set_property LOC N19 [get_ports sw[4]] +set_property LOC P19 [get_ports sw[5]] +set_property LOC P26 [get_ports sw[6]] +set_property LOC P27 [get_ports sw[7]] diff --git a/xilinx/examples/genesys2/kintex7patch.py b/xilinx/examples/genesys2/kintex7patch.py new file mode 100644 index 000000000..1f80ce83a --- /dev/null +++ b/xilinx/examples/genesys2/kintex7patch.py @@ -0,0 +1,22 @@ +import json +import sys +NextPnrFile = sys.argv[1] +input_file = open(NextPnrFile, 'r') +data = json.loads(input_file.read()) +input_file.close(); + +for cells in data['modules']['top']['cells']: + if (data['modules']['top']['cells'][cells]['type'] == 'PAD'): + data['modules']['top']['cells'][cells]['type'] = 'IOB_PAD' + + if (data['modules']['top']['cells'][cells]['type'] == 'IOB33_INBUF_EN' or data['modules']['top']['cells'][cells]['type'] == 'IOB33_OUTBUF'): + first_inst = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']).find('/') + second_inst = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']).find('/' ,1+first_inst) + if (first_inst >= 0): + if (second_inst >= 0): + data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'] = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'])[:first_inst] + (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'])[second_inst:]; + + +output_file = open(NextPnrFile, 'w') +output_file.write(json.dumps(data,indent = 5, sort_keys=True)) +output_file.close() diff --git a/xilinx/examples/genesys2/simpleCircuit.sh b/xilinx/examples/genesys2/simpleCircuit.sh new file mode 100755 index 000000000..495665d63 --- /dev/null +++ b/xilinx/examples/genesys2/simpleCircuit.sh @@ -0,0 +1,7 @@ +#!/usr/bin/env bash +set -ex +yosys -p "synth_xilinx -flatten -arch xcup -nobram -nowidelut -top top; write_json simpleCircuit.json" simpleCircuit.v +../../../nextpnr-xilinx --chipdb ../../xc7k325t.bin --json simpleCircuit.json --xdc Genesys2.xdc --write simpleCircuit_routed.json +python kintex7patch.py simpleCircuit_routed.json +java -jar ../../../rapidwright_json2dcp.jar xc7k325tffg900-2 simpleCircuit_routed.json simpleCircuit.dcp +vivado -mode batch -nojournal -nolog -source simpleCircuit.tcl diff --git a/xilinx/examples/genesys2/simpleCircuit.tcl b/xilinx/examples/genesys2/simpleCircuit.tcl new file mode 100644 index 000000000..4683cb02d --- /dev/null +++ b/xilinx/examples/genesys2/simpleCircuit.tcl @@ -0,0 +1,4 @@ +open_checkpoint simpleCircuit.dcp +write_verilog -force simpleCircuit_out.v +set_property IS_LOC_FIXED true [get_ports] +write_bitstream -force simpleCircuit.bit diff --git a/xilinx/examples/genesys2/simpleCircuit.v b/xilinx/examples/genesys2/simpleCircuit.v new file mode 100644 index 000000000..641143171 --- /dev/null +++ b/xilinx/examples/genesys2/simpleCircuit.v @@ -0,0 +1,5 @@ +module top (input [7:0] sw, output [4:0] led); + +assign led = {1'b0,sw[3:0]} + {1'b0,sw[7:4]}; + +endmodule From a06740dbe76cdfdcd97f3b4943d5cc873d5f4608 Mon Sep 17 00:00:00 2001 From: asanaull Date: Mon, 17 Feb 2020 16:26:43 -0500 Subject: [PATCH 2/3] code update --- xilinx/examples/genesys2/kintex7patch.py | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/xilinx/examples/genesys2/kintex7patch.py b/xilinx/examples/genesys2/kintex7patch.py index 1f80ce83a..c49dd9903 100644 --- a/xilinx/examples/genesys2/kintex7patch.py +++ b/xilinx/examples/genesys2/kintex7patch.py @@ -10,13 +10,12 @@ data['modules']['top']['cells'][cells]['type'] = 'IOB_PAD' if (data['modules']['top']['cells'][cells]['type'] == 'IOB33_INBUF_EN' or data['modules']['top']['cells'][cells]['type'] == 'IOB33_OUTBUF'): - first_inst = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']).find('/') - second_inst = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']).find('/' ,1+first_inst) - if (first_inst >= 0): - if (second_inst >= 0): - data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'] = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'])[:first_inst] + (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'])[second_inst:]; + first_inst = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']).find('/') + if (first_inst >= 0): + second_inst = (data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']).find('/',1+first_inst) + if (second_inst >= 0): + data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL']=data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'][:first_inst]+data['modules']['top']['cells'][cells]['attributes']['NEXTPNR_BEL'][second_inst:]; - output_file = open(NextPnrFile, 'w') output_file.write(json.dumps(data,indent = 5, sort_keys=True)) output_file.close() From d211422a5a57a1b9454af3cc791695426e5693e7 Mon Sep 17 00:00:00 2001 From: asanaullah <58180328+asanaullah@users.noreply.github.com> Date: Wed, 19 Feb 2020 11:36:36 -0500 Subject: [PATCH 3/3] Update simpleCircuit.sh --- xilinx/examples/genesys2/simpleCircuit.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xilinx/examples/genesys2/simpleCircuit.sh b/xilinx/examples/genesys2/simpleCircuit.sh index 495665d63..8371d8c5d 100755 --- a/xilinx/examples/genesys2/simpleCircuit.sh +++ b/xilinx/examples/genesys2/simpleCircuit.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash set -ex -yosys -p "synth_xilinx -flatten -arch xcup -nobram -nowidelut -top top; write_json simpleCircuit.json" simpleCircuit.v +yosys -p "synth_xilinx -flatten -arch xc7 -nobram -nowidelut -top top; write_json simpleCircuit.json" simpleCircuit.v ../../../nextpnr-xilinx --chipdb ../../xc7k325t.bin --json simpleCircuit.json --xdc Genesys2.xdc --write simpleCircuit_routed.json python kintex7patch.py simpleCircuit_routed.json java -jar ../../../rapidwright_json2dcp.jar xc7k325tffg900-2 simpleCircuit_routed.json simpleCircuit.dcp