ACPI and Device Tree expose incomplete CPU topology information on CIX Sky1 / CD8180

[coffnix]

This issue is reproducible on both kernel 6.19.14 and 7.0.14. Reported also on Sky1-Linux/linux-sky1#33

Summary

There are two different issues depending on the boot method:

1. ACPI boot
   • CPU topology is detected correctly.
   • CPU frequencies are reported correctly.
   • L1, L2, and L3 cache information is missing from both lscpu and hwloc.
2. Device Tree (DTB) boot
   • L1, L2, and L3 cache information is exposed correctly.
   • CPU frequency information becomes incorrect and shows bogus values.

It seems that neither boot method currently exposes all CPU topology information correctly.

Hardware

• Board: Orange Pi 6 Plus
• SoC: CIX Sky1 / CD8180 (CD8160 compatible branding)
• CPU: 8x Cortex-A720 + 4x Cortex-A520
• Firmware: SystemReady ACPI firmware
• Kernel: 6.19.14

Expected CPU frequencies

According to the board specifications, the CPU frequencies should be approximately:

• Cortex-A720 cluster: up to 2.6 GHz
• Cortex-A520 cluster: up to 1.8 GHz

These frequencies are reported correctly when booting with ACPI

Problem 1: ACPI mode

lscpu and hwloc do not report cache hierarchy information.

Expected:

• L1d cache
• L1i cache
• L2 cache
• L3 cache

Actual:

Cache information is missing entirely.

This also affects tools such as hwloc-ls and lstopo, which cannot build the proper cache topology.

Problem 2: Device Tree mode

When booting using a DTB file, cache information becomes available and is reported correctly.

However, CPU frequencies become incorrect and show unrealistic values.

Example:

Expected:

• Cortex-A720: 2.6 GHz
• Cortex-A520: 1.8 GHz

Actual:

• Cortex-A720: 1.5 GHz
• Cortex-A520: 1.8 GHz

Reproduction

ACPI boot

lscpu
lstopo
hwloc-info

Device Tree boot

lscpu
lstopo
hwloc-info

Question

It looks like the cache hierarchy information exists in the Device Tree but is not exposed properly through ACPI, while the CPU frequency information behaves in the opposite way.

Could this be caused by:

• incomplete PPTT (Processor Properties Topology Table) information in ACPI?
• missing cache nodes in the ACPI tables?
• incorrect OPP or cpufreq information in the Device Tree?
• missing cache descriptors in firmware?

In short, the cache topology information exposed by the kernel appears to be broken. The /sys/devices/system/cpu/cpu*/cache/ hierarchy does not provide any size values, which causes tools such as hwloc to report all caches as 0KB. Additionally, the reported sharing information is incorrect, as L1 data, L1 instruction and L2 caches are shown as being shared by all 12 CPUs (0-11), which is architecturally impossible for this SoC. This strongly suggests a problem in the ACPI PPTT tables or in the kernel’s cache topology parsing for the CIX platform, rather than an issue in hwloc itself. Same issue on kernel 7.0.14. Look:

The issue is reproducible on both 6.19.14 and 7.0.14 and does not appear to be a regression in a specific kernel version.

opi6plus ~ # for c in /sys/devices/system/cpu/cpu0/cache/index*; do
    echo "===== $c ====="
    cat "$c/level" "$c/type" "$c/size" "$c/shared_cpu_list" 2>/dev/null
done
===== /sys/devices/system/cpu/cpu0/cache/index0 =====
1
Data
0-11
===== /sys/devices/system/cpu/cpu0/cache/index1 =====
1
Instruction
0-11
===== /sys/devices/system/cpu/cpu0/cache/index2 =====
2
Unified
0-11
===== /sys/devices/system/cpu/cpu0/cache/index3 =====
3
Unified
0-1,6-11
opi6plus ~ # for cpu in /sys/devices/system/cpu/cpu*/cache/index*; do
    printf '%s: ' "$cpu"
    cat "$cpu/level" "$cpu/type" "$cpu/size" "$cpu/shared_cpu_list" 2>/dev/null | paste -sd ' '
done
/sys/devices/system/cpu/cpu0/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu0/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu0/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu0/cache/index3: 3 Unified 0-1,6-11
/sys/devices/system/cpu/cpu10/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu10/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu10/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu10/cache/index3: 3 Unified 0-1,6-11
/sys/devices/system/cpu/cpu11/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu11/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu11/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu11/cache/index3: 3 Unified 0-1,6-11
/sys/devices/system/cpu/cpu1/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu1/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu1/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu1/cache/index3: 3 Unified 0-1,6-11
/sys/devices/system/cpu/cpu2/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu2/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu2/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu3/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu3/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu3/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu4/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu4/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu4/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu5/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu5/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu5/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu6/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu6/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu6/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu6/cache/index3: 3 Unified 0-1,6-11
/sys/devices/system/cpu/cpu7/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu7/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu7/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu7/cache/index3: 3 Unified 0-1,6-11
/sys/devices/system/cpu/cpu8/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu8/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu8/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu8/cache/index3: 3 Unified 0-1,6-11
/sys/devices/system/cpu/cpu9/cache/index0: 1 Data 0-11
/sys/devices/system/cpu/cpu9/cache/index1: 1 Instruction 0-11
/sys/devices/system/cpu/cpu9/cache/index2: 2 Unified 0-11
/sys/devices/system/cpu/cpu9/cache/index3: 3 Unified 0-1,6-11

Kernel built from vanilla-sources using the latest cix-linux-main patchset plus PR #27 and PR #37.

opi6plus ~ # cat compile-kernel-cix-patches.sh
#!/bin/bash

### opi 6 plus

cd /usr/src ; rm -rf /usr/src/cix-linux-main ;  git clone https://github.com/cixtech/cix-linux-main.git

cd /usr/src/linux

# bug on 7.0.14 and new patch - after commit 759efc0 - https://github.com/cixtech/cix-linux-main/pull/37
cd /usr/src/cix-linux-main/patches-7.0/
sed -i 's/if (IS_ERR(n_phandles))/if (n_phandles < 0)/' /usr/src/cix-linux-main/patches-7.0/0033-regulator-add-acpi-support.patch

rm 0061-DPTSW-24991-usb-fix-SError-during-poweroff-by-releas.patch
rm 0062-DPTSW-25423-usb-cdns3-sky1-disabled-IRQ-before-disab.patch
wget https://raw.githubusercontent.com/npmccallum/cix-linux-main/9ace918767af39e90d42d00e6ce22a2d770bfbd0/patches-7.0/0061-usb-cdns3-cdnsp-sky1-tear-down-host-on-shutdown.patch

# new patch on 7.0.14 - after commit 759efc0 - https://github.com/cixtech/cix-linux-main/pull/27
wget https://raw.githubusercontent.com/perlowja/cix-linux-main/ebf4c22a950cdc3e21f05cbf657e1b3309945360/patches-7.0/2005-uapi-armchina_aipu-update-structs-to-sdk-26q1-r2p1.patch

cd /usr/src/linux
for p in ../cix-linux-main/patches-7.0/*.patch; do patch -p1 < "$p"; done
cp /usr/src/cix-linux-main/config/config-7.0.defconfig .config

scripts/config --disable DRM_NOUVEAU
scripts/config --disable OCTEONTX2_PF
scripts/config --disable OCTEONTX2_VF
scripts/config --disable OCTEONTX2_AF
make olddefconfig

make -j"$(nproc)" Image
if [ "$?" -ne 0 ];then echo 'ERRO' ;exit 1 ;fi

make -j"$(nproc)" modules
if [ "$?" -ne 0 ];then echo 'ERRO' ;exit 1 ;fi

make -j"$(nproc)" dtbs
if [ "$?" -ne 0 ];then echo 'ERRO' ;exit 1 ;fi

cd /usr/src/linux
export NEW="$(make kernelrelease)"
cp /usr/src/linux/arch/arm64/boot/dts/cix/sky1-xcp.dtb /boot/efi/sky1-orangepi-6-plus-${NEW}.dtb
cp arch/arm64/boot/Image /boot/vmlinuz-${NEW}
cp arch/arm64/boot/Image /boot/efi/vmlinuz-${NEW}
cp System.map /boot/System.map-${NEW}
cp .config /boot/config-${NEW}
make modules_install
depmod -a "${NEW}"
ls /lib/modules/"${NEW}" >/dev/null || exit 1
dracut /boot/initramfs-${NEW}.img ${NEW}
cp /boot/initramfs-${NEW}.img /boot/efi/initramfs-${NEW}.img
cd

The problem appears to be split between firmware interfaces:

• ACPI mode provides correct CPU frequencies but exposes an incomplete or broken cache topology.
• Device Tree mode provides correct cache topology but exposes incorrect CPU frequency information.

At the moment there is no boot method that provides both pieces of information correctly.

[coffnix]

another info:

The ACPI PPTT table is present, but it appears to be incomplete or malformed:

ACPI: PPTT 0x00000007F98DF118 00018C

The table is only 396 bytes long. Under ACPI boot, Linux creates cache index entries under /sys/devices/system/cpu/cpu*/cache/, but the cache size attributes are missing entirely. For example, /sys/devices/system/cpu/cpu0/cache/index*/size does not exist, and lscpu reports no cache information at all.

This suggests that the firmware exposes a PPTT table, but it does not provide enough valid cache descriptor information for the kernel cacheinfo code to populate cache sizes and sharing topology. The resulting topology is also clearly wrong, because L1 data, L1 instruction and L2 caches are reported as shared by all CPUs 0-11, which is not architecturally possible on this SoC.

opi6plus ~ # acpidump -n PPTT -b
opi6plus ~ # iasl -d pptt.dat

Intel ACPI Component Architecture
ASL+ Optimizing Compiler/Disassembler version 20240927
Copyright (c) 2000 - 2023 Intel Corporation

File appears to be binary: found 357 non-ASCII characters, disassembling
Binary file appears to be a valid ACPI table, disassembling
Input file pptt.dat, Length 0x18C (396) bytes
ACPI: PPTT 0x0000000000000000 00018C (v02 CIXTEK SKY1EDK2 01000101 CIX  00000001)
Acpi Data Table [PPTT] decoded
Formatted output:  pptt.dsl - 14517 bytes

After dumping and disassembling the ACPI PPTT table, it looks like the table only contains Processor Hierarchy Node entries and no cache descriptor entries at all.

The grep output from pptt.dsl shows no Cache Type, Size, NumberOfSets, Associativity or NextLevel cache information. This explains why Linux creates cache index entries but cannot expose any cache size values under /sys/devices/system/cpu/cpu*/cache/index*/size, and why lscpu and hwloc report missing or 0KB cache information.

So the issue does not appear to be caused by hwloc or lscpu. The ACPI PPTT table provided by firmware is missing the cache topology descriptors needed by Linux.

opi6plus ~ # grep -nEi 'Cache|Processor|Size|NumberOfSets|Associativity|Attributes|NextLevel|PPTT' pptt.dsl
6: * Disassembly of pptt.dat
8: * ACPI Data Table [PPTT]
13:[000h 0000 004h]                   Signature : "PPTT"    [Processor Properties Topology Table]
24:[024h 0036 001h]               Subtable Type : 00 [Processor Hierarchy Node]
29:                     ACPI Processor ID valid : 1
30:                       Processor is a thread : 0
34:[030h 0048 004h]           ACPI Processor ID : 00000000
37:[038h 0056 001h]               Subtable Type : 00 [Processor Hierarchy Node]
42:                     ACPI Processor ID valid : 1
43:                       Processor is a thread : 0
47:[044h 0068 004h]           ACPI Processor ID : 00000001
50:[04Ch 0076 001h]               Subtable Type : 00 [Processor Hierarchy Node]
55:                     ACPI Processor ID valid : 1
56:                       Processor is a thread : 0
60:[058h 0088 004h]           ACPI Processor ID : 00000000
63:[060h 0096 001h]               Subtable Type : 00 [Processor Hierarchy Node]
68:                     ACPI Processor ID valid : 1
69:                       Processor is a thread : 0
73:[06Ch 0108 004h]           ACPI Processor ID : 00000001
76:[074h 0116 001h]               Subtable Type : 00 [Processor Hierarchy Node]
81:                     ACPI Processor ID valid : 1
82:                       Processor is a thread : 0
86:[080h 0128 004h]           ACPI Processor ID : 00000002
89:[088h 0136 001h]               Subtable Type : 00 [Processor Hierarchy Node]
94:                     ACPI Processor ID valid : 1
95:                       Processor is a thread : 0
99:[094h 0148 004h]           ACPI Processor ID : 00000002
102:[09Ch 0156 001h]               Subtable Type : 00 [Processor Hierarchy Node]
107:                     ACPI Processor ID valid : 1
108:                       Processor is a thread : 0
112:[0A8h 0168 004h]           ACPI Processor ID : 00000003
115:[0B0h 0176 001h]               Subtable Type : 00 [Processor Hierarchy Node]
120:                     ACPI Processor ID valid : 1
121:                       Processor is a thread : 0
125:[0BCh 0188 004h]           ACPI Processor ID : 00000004
128:[0C4h 0196 001h]               Subtable Type : 00 [Processor Hierarchy Node]
133:                     ACPI Processor ID valid : 1
134:                       Processor is a thread : 0
138:[0D0h 0208 004h]           ACPI Processor ID : 00000005
141:[0D8h 0216 001h]               Subtable Type : 00 [Processor Hierarchy Node]
146:                     ACPI Processor ID valid : 1
147:                       Processor is a thread : 0
151:[0E4h 0228 004h]           ACPI Processor ID : 00000003
154:[0ECh 0236 001h]               Subtable Type : 00 [Processor Hierarchy Node]
159:                     ACPI Processor ID valid : 1
160:                       Processor is a thread : 0
164:[0F8h 0248 004h]           ACPI Processor ID : 00000006
167:[100h 0256 001h]               Subtable Type : 00 [Processor Hierarchy Node]
172:                     ACPI Processor ID valid : 1
173:                       Processor is a thread : 0
177:[10Ch 0268 004h]           ACPI Processor ID : 00000007
180:[114h 0276 001h]               Subtable Type : 00 [Processor Hierarchy Node]
185:                     ACPI Processor ID valid : 1
186:                       Processor is a thread : 0
190:[120h 0288 004h]           ACPI Processor ID : 00000004
193:[128h 0296 001h]               Subtable Type : 00 [Processor Hierarchy Node]
198:                     ACPI Processor ID valid : 1
199:                       Processor is a thread : 0
203:[134h 0308 004h]           ACPI Processor ID : 00000008
206:[13Ch 0316 001h]               Subtable Type : 00 [Processor Hierarchy Node]
211:                     ACPI Processor ID valid : 1
212:                       Processor is a thread : 0
216:[148h 0328 004h]           ACPI Processor ID : 00000009
219:[150h 0336 001h]               Subtable Type : 00 [Processor Hierarchy Node]
224:                     ACPI Processor ID valid : 1
225:                       Processor is a thread : 0
229:[15Ch 0348 004h]           ACPI Processor ID : 00000005
232:[164h 0356 001h]               Subtable Type : 00 [Processor Hierarchy Node]
237:                     ACPI Processor ID valid : 1
238:                       Processor is a thread : 0
242:[170h 0368 004h]           ACPI Processor ID : 0000000A
245:[178h 0376 001h]               Subtable Type : 00 [Processor Hierarchy Node]
250:                     ACPI Processor ID valid : 1
251:                       Processor is a thread : 0
255:[184h 0388 004h]           ACPI Processor ID : 0000000B
260:    0000: 50 50 54 54 8C 01 00 00 02 6D 43 49 58 54 45 4B  // PPTT.....mCIXTEK
opi6plus ~ #

Further confirmation:

The cache sysfs hierarchy is incomplete. No cache size files are exported at all:

opi6plus ~ # find /sys/devices/system/cpu/cpu*/cache -name size -exec ls -l {} \;
opi6plus ~ #

For cpu0, the cache directories only contain:

opi6plus ~ # for i in /sys/devices/system/cpu/cpu0/cache/index*; do
    echo "== $i =="
    ls "$i"
done
== /sys/devices/system/cpu/cpu0/cache/index0 ==
level  shared_cpu_list  shared_cpu_map  type  uevent
== /sys/devices/system/cpu/cpu0/cache/index1 ==
level  shared_cpu_list  shared_cpu_map  type  uevent
== /sys/devices/system/cpu/cpu0/cache/index2 ==
level  shared_cpu_list  shared_cpu_map  type  uevent
== /sys/devices/system/cpu/cpu0/cache/index3 ==
level  shared_cpu_list  shared_cpu_map  type  uevent

There are also no cache IDs:

opi6plus ~ # grep . /sys/devices/system/cpu/cpu0/cache/index*/id 2>/dev/null
opi6plus ~ #

The sharing masks are clearly incorrect:

opi6plus ~ # grep . /sys/devices/system/cpu/cpu0/cache/index*/shared_cpu_list
/sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_list:0-11
/sys/devices/system/cpu/cpu0/cache/index1/shared_cpu_list:0-11
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_list:0-11
/sys/devices/system/cpu/cpu0/cache/index3/shared_cpu_list:0-1,6-11
opi6plus ~ # grep . /sys/devices/system/cpu/cpu0/cache/index*/shared_cpu_map
/sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_map:fff
/sys/devices/system/cpu/cpu0/cache/index1/shared_cpu_map:fff
/sys/devices/system/cpu/cpu0/cache/index2/shared_cpu_map:fff
/sys/devices/system/cpu/cpu0/cache/index3/shared_cpu_map:fc3

This means Linux is reporting L1 data, L1 instruction and L2 as shared by all 12 CPUs, which is architecturally impossible for this SoC.

Therefore, the ACPI PPTT table appears to be incomplete or malformed. It is not only missing cache descriptors and cache sizes, but it is also causing incorrect cache sharing information to be exposed through sysfs.

[coffnix]

complete dmesg

dmesg.log

[coffnix]

This issue still persists with Linux kernel 7.1.3 and the 7.1 patches.

[coffnix]

I have opened a pull request containing a ready-to-use acpi_override.cpio for testing: #44

The pull request intentionally contains only the final acpi_override.cpio file so it can be tested immediately without rebuilding the ACPI tables.

The override has been successfully tested on an Orange Pi 6 Plus running a vanilla Linux 7.1.3 kernel with the CIX patches from this repository applied.

Below are the complete steps I used to reproduce the result from scratch.

1. Compile a vanilla Linux 7.1.3 kernel and apply the CIX patches from this repository. Then boot the board and extract the original ACPI tables.

mkdir -p /root/latest-acpi/sysfs/
find /sys/firmware/acpi/tables -maxdepth 1 -type f -exec cp {} /root/latest-acpi/sysfs/ \;
ls -lh /root/latest-acpi/sysfs

cd /root/latest-acpi/sysfs
iasl -e SSDT1 SSDT2 -d DSDT

iasl -d SSDT1
iasl -d SSDT2

mkdir -p /root/latest-acpi/build

cp /root/latest-acpi/sysfs/SSDT1.dsl \
   /root/latest-acpi/build/ssdt-main.dsl

cp /root/latest-acpi/sysfs/SSDT2.dsl \
   /root/latest-acpi/build/ssdt-cpu.dsl


   sed -i \
's/DefinitionBlock ("", "SSDT", 2, "CIXTEK", "SKY1EDK2", 0x00000001)/DefinitionBlock ("", "SSDT", 2, "CIXTEK", "SKY1EDK2", 0xFFFFFFFF)/' \
/root/latest-acpi/build/ssdt-main.dsl

sed -i \
's/DefinitionBlock ("", "SSDT", 2, "CIXTEK", "SKY1EDK2", 0x01000101)/DefinitionBlock ("", "SSDT", 2, "CIXTEK", "SKY1EDK2", 0x01000102)/' \
/root/latest-acpi/build/ssdt-cpu.dsl

sed -i '65s/0x2000/0x2276/;66s/0x2000/0x2276/' \
/root/latest-acpi/build/ssdt-cpu.dsl

sed -i '217s/0x2000/0x2276/;218s/0x2000/0x2276/' \
/root/latest-acpi/build/ssdt-cpu.dsl

sed -i '987s/0x1C4E/0x1D89/;988s/0x1C4E/0x1D89/' \
/root/latest-acpi/build/ssdt-cpu.dsl

sed -i '1139s/0x1C4E/0x1D89/;1140s/0x1C4E/0x1D89/' \
/root/latest-acpi/build/ssdt-cpu.dsl

sed -i '1296s/0x1B13/0x1D89/;1297s/0x1B13/0x1D89/' \
/root/latest-acpi/build/ssdt-cpu.dsl

sed -i '1448s/0x1B13/0x1D89/;1449s/0x1B13/0x1D89/' \
/root/latest-acpi/build/ssdt-cpu.dsl

sed -i '1605s/0x1EC4/0x2276/;1606s/0x1EC4/0x2276/' \
/root/latest-acpi/build/ssdt-cpu.dsl

sed -i '1757s/0x1EC4/0x2276/;1758s/0x1EC4/0x2276/' \
/root/latest-acpi/build/ssdt-cpu.dsl

cd /root/latest-acpi/build

iasl -tc ssdt-main.dsl
iasl -tc ssdt-cpu.dsl

# check
ls -lh /root/latest-acpi/build/*.aml

iasl -d /root/latest-acpi/build/ssdt-main.aml
iasl -d /root/latest-acpi/build/ssdt-cpu.aml

grep -n 'DefinitionBlock' \
/root/latest-acpi/build/ssdt-main.dsl \
/root/latest-acpi/build/ssdt-cpu.dsl

2. Generate the corrected PPTT table using the Python script below.

#!/usr/bin/env python3

import struct
from pathlib import Path


OUTPUT = Path("/root/latest-acpi/build/pptt.aml")

HEADER_SIZE = 36

PPTT_PROCESSOR = 0
PPTT_CACHE = 1

PROCESSOR_PHYSICAL_PACKAGE = 1 << 0
PROCESSOR_ID_VALID = 1 << 1
PROCESSOR_LEAF = 1 << 3
PROCESSOR_IDENTICAL = 1 << 4

CACHE_SIZE_VALID = 1 << 0
CACHE_TYPE_VALID = 1 << 4
CACHE_LINE_SIZE_VALID = 1 << 6
CACHE_ID_VALID = 1 << 7

CACHE_FLAGS = (
    CACHE_SIZE_VALID
    | CACHE_TYPE_VALID
    | CACHE_LINE_SIZE_VALID
    | CACHE_ID_VALID
)

CACHE_TYPE_DATA = 0x00
CACHE_TYPE_INSTRUCTION = 0x04
CACHE_TYPE_UNIFIED = 0x08

CACHE_LINE_SIZE = 64

L1_A720_SIZE = 64 * 1024
L1_A520_SIZE = 32 * 1024

L2_A720_SIZE = 512 * 1024
L2_A520_SHARED_SIZE = 2 * 1024 * 1024

L3_SIZE = 12 * 1024 * 1024


class TableBuilder:
    def __init__(self):
        self.entries = []
        self.offset = HEADER_SIZE

    def reserve_processor(self, resource_count):
        length = 20 + resource_count * 4
        offset = self.offset

        self.entries.append(
            {
                "kind": "processor",
                "offset": offset,
                "length": length,
                "data": None,
            }
        )

        self.offset += length
        return offset

    def reserve_cache(self):
        length = 28
        offset = self.offset

        self.entries.append(
            {
                "kind": "cache",
                "offset": offset,
                "length": length,
                "data": None,
            }
        )

        self.offset += length
        return offset

    def set_processor(
        self,
        offset,
        flags,
        parent,
        processor_id,
        resources,
    ):
        entry = self.find(offset)

        length = 20 + len(resources) * 4

        if length != entry["length"]:
            raise ValueError(
                f"Tamanho incorreto para processor em 0x{offset:x}"
            )

        data = struct.pack(
            "<BBHIIII",
            PPTT_PROCESSOR,
            length,
            0,
            flags,
            parent,
            processor_id,
            len(resources),
        )

        for resource in resources:
            data += struct.pack("<I", resource)

        entry["data"] = data

    def set_cache(
        self,
        offset,
        next_level,
        size,
        cache_type,
        cache_id,
    ):
        entry = self.find(offset)

        data = struct.pack(
            "<BBHIIIIBBHI",
            PPTT_CACHE,
            28,
            0,
            CACHE_FLAGS,
            next_level,
            size,
            0,
            0,
            cache_type,
            CACHE_LINE_SIZE,
            cache_id,
        )

        if len(data) != 28:
            raise ValueError(
                f"Tamanho incorreto para cache em 0x{offset:x}"
            )

        entry["data"] = data

    def find(self, offset):
        for entry in self.entries:
            if entry["offset"] == offset:
                return entry

        raise KeyError(
            f"Entrada não encontrada em 0x{offset:x}"
        )

    def payload(self):
        result = bytearray()

        for entry in self.entries:
            if entry["data"] is None:
                raise ValueError(
                    f"Entrada sem dados em 0x{entry['offset']:x}"
                )

            if len(entry["data"]) != entry["length"]:
                raise ValueError(
                    f"Tamanho divergente em 0x{entry['offset']:x}"
                )

            result.extend(entry["data"])

        return bytes(result)


builder = TableBuilder()

package = builder.reserve_processor(0)

cluster1 = builder.reserve_processor(0)
cpu0 = builder.reserve_processor(2)
cpu1 = builder.reserve_processor(2)

cluster2 = builder.reserve_processor(0)
cpu2 = builder.reserve_processor(2)
cpu3 = builder.reserve_processor(2)
cpu4 = builder.reserve_processor(2)
cpu5 = builder.reserve_processor(2)

cluster3 = builder.reserve_processor(0)
cpu6 = builder.reserve_processor(2)
cpu7 = builder.reserve_processor(2)

cluster4 = builder.reserve_processor(0)
cpu8 = builder.reserve_processor(2)
cpu9 = builder.reserve_processor(2)

cluster5 = builder.reserve_processor(0)
cpu10 = builder.reserve_processor(2)
cpu11 = builder.reserve_processor(2)

cpu_offsets = [
    cpu0,
    cpu1,
    cpu2,
    cpu3,
    cpu4,
    cpu5,
    cpu6,
    cpu7,
    cpu8,
    cpu9,
    cpu10,
    cpu11,
]

a520_cpus = {2, 3, 4, 5}

l3 = builder.reserve_cache()
l2_a520_shared = builder.reserve_cache()

cache_offsets = {}

for cpu_id in range(12):
    l1d = builder.reserve_cache()
    l1i = builder.reserve_cache()

    if cpu_id in a520_cpus:
        l2 = l2_a520_shared
    else:
        l2 = builder.reserve_cache()

    cache_offsets[cpu_id] = {
        "l1d": l1d,
        "l1i": l1i,
        "l2": l2,
    }

builder.set_processor(
    package,
    PROCESSOR_PHYSICAL_PACKAGE | PROCESSOR_ID_VALID,
    0,
    0,
    [],
)

cluster_flags = (
    PROCESSOR_ID_VALID
    | PROCESSOR_IDENTICAL
)

builder.set_processor(
    cluster1,
    cluster_flags,
    package,
    1,
    [],
)

builder.set_processor(
    cluster2,
    cluster_flags,
    package,
    2,
    [],
)

builder.set_processor(
    cluster3,
    cluster_flags,
    package,
    3,
    [],
)

builder.set_processor(
    cluster4,
    cluster_flags,
    package,
    4,
    [],
)

builder.set_processor(
    cluster5,
    cluster_flags,
    package,
    5,
    [],
)

cpu_parents = {
    0: cluster1,
    1: cluster1,
    2: cluster2,
    3: cluster2,
    4: cluster2,
    5: cluster2,
    6: cluster3,
    7: cluster3,
    8: cluster4,
    9: cluster4,
    10: cluster5,
    11: cluster5,
}

leaf_flags = (
    PROCESSOR_ID_VALID
    | PROCESSOR_LEAF
    | PROCESSOR_IDENTICAL
)

for cpu_id, cpu_offset in enumerate(cpu_offsets):
    caches = cache_offsets[cpu_id]

    builder.set_processor(
        cpu_offset,
        leaf_flags,
        cpu_parents[cpu_id],
        cpu_id,
        [
            caches["l1d"],
            caches["l1i"],
        ],
    )

builder.set_cache(
    l3,
    0,
    L3_SIZE,
    CACHE_TYPE_UNIFIED,
    0x300,
)

builder.set_cache(
    l2_a520_shared,
    l3,
    L2_A520_SHARED_SIZE,
    CACHE_TYPE_UNIFIED,
    0x200,
)

for cpu_id in range(12):
    caches = cache_offsets[cpu_id]

    if cpu_id in a520_cpus:
        l1_size = L1_A520_SIZE
    else:
        l1_size = L1_A720_SIZE

        builder.set_cache(
            caches["l2"],
            l3,
            L2_A720_SIZE,
            CACHE_TYPE_UNIFIED,
            0x210 + cpu_id,
        )

    builder.set_cache(
        caches["l1d"],
        caches["l2"],
        l1_size,
        CACHE_TYPE_DATA,
        0x100 + cpu_id,
    )

    builder.set_cache(
        caches["l1i"],
        caches["l2"],
        l1_size,
        CACHE_TYPE_INSTRUCTION,
        0x180 + cpu_id,
    )

payload = builder.payload()
table_length = HEADER_SIZE + len(payload)

header = struct.pack(
    "<4sIBB6s8sI4sI",
    b"PPTT",
    table_length,
    3,
    0,
    b"CIXTEK",
    b"SKY1EDK2",
    0x01000103,
    b"CIX ",
    1,
)

table = bytearray(header + payload)

checksum = (-sum(table)) & 0xFF
table[9] = checksum

if sum(table) & 0xFF:
    raise RuntimeError(
        "Checksum ACPI inválido"
    )

OUTPUT.write_bytes(table)

print(f"Arquivo criado: {OUTPUT}")
print(f"Tamanho: {len(table)} bytes")
print(f"Checksum: 0x{checksum:02X}")
print(f"Entradas: {len(builder.entries)}")
print("PPTT revisão 3")
print("L2 A520 compartilhado: 2 MiB")
print("L3 compartilhado: 12 MiB")

3. Build the ACPI override CPIO archive.

chmod 700 /root/latest-acpi/build/build-pptt.py
python3 /root/latest-acpi/build/build-pptt.py

# check
iasl -d /root/latest-acpi/build/pptt.aml
grep -nE 'Table Length|Oem Revision|Cache Type Structure|Processor Hierarchy Node|Size Property|Line Size|Attributes|Parent|ACPI Processor ID|Private Resource' \
/root/latest-acpi/build/pptt.dsl
grep -cE 'Subtable Type[[:space:]]*: 01' \
/root/latest-acpi/build/pptt.dsl

grep -nE 'Size Property|Next Level of Cache|Attributes|Line Size' \
/root/latest-acpi/build/pptt.dsl

for size in 00008000 00010000 00080000 00C00000; do
    printf '%s: ' "$size"
    grep -c "Size Property.*$size" /root/latest-acpi/build/pptt.dsl
done


grep -nE 'Subtable Type[[:space:]]*: 01|Next Level of Cache|Size Property|Attributes' \
/root/latest-acpi/build/pptt.dsl
sed -n '282,304p' /root/latest-acpi/build/pptt.dsl

ls -lh /root/latest-acpi/build/pptt.aml

cd 

rm -rf /root/latest-acpi/override

mkdir -p /root/latest-acpi/override/kernel/firmware/acpi


cp /root/latest-acpi/build/ssdt-main.aml \
/root/latest-acpi/override/kernel/firmware/acpi/ssdt1.aml

cp /root/latest-acpi/build/ssdt-cpu.aml \
/root/latest-acpi/override/kernel/firmware/acpi/ssdt2.aml

cp /root/latest-acpi/build/pptt.aml \
/root/latest-acpi/override/kernel/firmware/acpi/pptt.aml

4. Install the generated acpi_override.cpio and configure GRUB to load it during boot.

cd /root/latest-acpi/override

printf '%s\n' \
. \
kernel \
kernel/firmware \
kernel/firmware/acpi \
kernel/firmware/acpi/ssdt1.aml \
kernel/firmware/acpi/ssdt2.aml \
kernel/firmware/acpi/pptt.aml |
cpio -H newc -o > /boot/efi/acpi_override.cpio

5. GRUB configuration used for testing.

set debug=loader,mm
set term=vt100
set default=0
set timeout=5


menuentry '1 OrangePi 6 Plus (7.1.3) ACPI new' {
    linux /vmlinuz-7.1.3 \
        loglevel=8 ignore_loglevel printk.devkmsg=on drm.debug=0 \
		audit_backlog_limit=8192 \
        console=ttyAMA2,115200 console=tty0 \
        efi=noruntime \
        earlycon=pl011,0x040d0000 \
        acpi=on \
        clk_ignore_unused cpufreq.default_governor=performance \
		mitigations=off oops=panic panic=10 \
        root=PARTUUID=8112a51c-af33-4033-9676-c142ea88d79d rootwait ro
    initrd /acpi_override.cpio /initramfs-7.1.3.img
}

Check cpio content:

cpio -it < /boot/efi/acpi_override.cpio

rm -rf /root/latest-acpi/verify

mkdir -p /root/latest-acpi/verify

cd /root/latest-acpi/verify

cpio -idmv < /boot/efi/acpi_override.cpio

cmp \
/root/latest-acpi/build/ssdt-main.aml \
/root/latest-acpi/verify/kernel/firmware/acpi/ssdt1.aml \
&& echo "SSDT1 FIXED"

cmp \
/root/latest-acpi/build/ssdt-cpu.aml \
/root/latest-acpi/verify/kernel/firmware/acpi/ssdt2.aml \
&& echo "SSDT2 FIXED"

cmp \
/root/latest-acpi/build/pptt.aml \
/root/latest-acpi/verify/kernel/firmware/acpi/pptt.aml \
&& echo "PPTT FIXED"

6. Reboot and verify that the new PPTT has been loaded correctly.

dmesg | grep -iE 'ACPI.*(PPTT|Table Upgrade|Physical table override)'

lscpu

lscpu -C

hwloc-ls

for c in /sys/devices/system/cpu/cpu[0-9]*; do
    echo "===== $(basename "$c") ====="
    for i in "$c"/cache/index*; do
        [ -d "$i" ] || continue
        printf '%s level=%s type=%s size=%s id=%s shared=%s\n' \
            "$(basename "$i")" \
            "$(cat "$i/level" 2>/dev/null)" \
            "$(cat "$i/type" 2>/dev/null)" \
            "$(cat "$i/size" 2>/dev/null)" \
            "$(cat "$i/id" 2>/dev/null)" \
            "$(cat "$i/shared_cpu_list" 2>/dev/null)"
    done
done

I would really appreciate it if anyone with compatible CIX hardware could help validate this fix. Since GitHub does not allow attaching .cpio files directly to issue comments, I created a separate pull request containing only the ready-to-use acpi_override.cpio file:

#44

This allows anyone to simply download the archive, configure the bootloader to load it, boot the system, and verify whether the corrected PPTT works properly on their hardware. You can also extract the acpi_override.cpio archive to inspect its contents before using it, or, if you prefer, follow the complete procedure described above to build your own acpi_override.cpio from scratch and compare the results. Any feedback, successful tests, or reports from different boards and firmware versions would be greatly appreciated and will help confirm that this solution is correct before it is integrated into the firmware or ACPI sources. Finally, I would like to thank all of the CIX developers for their continuous work on improving Linux 7.1.x support and for fixing the issues reported by the community.

Below are the results I obtained after booting with the modified acpi_override.cpio.

# hwloc-ls
Machine (31GB total)
  Package L#0
    NUMANode L#0 (P#0 31GB)
    L3 L#0 (12MB)
      Group0(Cluster) L#0
        L2 L#0 (512KB) + L1d L#0 (64KB) + L1i L#0 (64KB) + Core L#0 + PU L#0 (P#0)
        L2 L#1 (512KB) + L1d L#1 (64KB) + L1i L#1 (64KB) + Core L#1 + PU L#1 (P#1)
      L2 L#2 (2048KB)
        L1d L#2 (32KB) + L1i L#2 (32KB) + Core L#2 + PU L#2 (P#2)
        L1d L#3 (32KB) + L1i L#3 (32KB) + Core L#3 + PU L#3 (P#3)
        L1d L#4 (32KB) + L1i L#4 (32KB) + Core L#4 + PU L#4 (P#4)
        L1d L#5 (32KB) + L1i L#5 (32KB) + Core L#5 + PU L#5 (P#5)
      Group0(Cluster) L#1
        L2 L#3 (512KB) + L1d L#6 (64KB) + L1i L#6 (64KB) + Core L#6 + PU L#6 (P#6)
        L2 L#4 (512KB) + L1d L#7 (64KB) + L1i L#7 (64KB) + Core L#7 + PU L#7 (P#7)
      Group0(Cluster) L#2
        L2 L#5 (512KB) + L1d L#8 (64KB) + L1i L#8 (64KB) + Core L#8 + PU L#8 (P#8)
        L2 L#6 (512KB) + L1d L#9 (64KB) + L1i L#9 (64KB) + Core L#9 + PU L#9 (P#9)
      Group0(Cluster) L#3
        L2 L#7 (512KB) + L1d L#10 (64KB) + L1i L#10 (64KB) + Core L#10 + PU L#10 (P#10)
        L2 L#8 (512KB) + L1d L#11 (64KB) + L1i L#11 (64KB) + Core L#11 + PU L#11 (P#11)
  HostBridge
    PCIBridge
      PCI 31:00.0 (Ethernet)
        Net "eth1"
  HostBridge
    PCIBridge
      PCI 61:00.0 (Ethernet)
        Net "eth0"
  HostBridge
    PCIBridge
      PCI 91:00.0 (NVMExp)
        Block(Disk) "nvme0n1"

# lscpu
Architecture:                aarch64
  CPU op-mode(s):            64-bit
  Byte Order:                Little Endian
CPU(s):                      12
  On-line CPU(s) list:       0-11
Vendor ID:                   ARM
  BIOS Vendor ID:            Cix Technology Group Co., Ltd.
  Model name:                Cortex-A520
    BIOS Model name:         CIX P1 CD8160   CPU @ 1.5GHz
    BIOS CPU family:         258
    Model:                   1
    Thread(s) per core:      1
    Core(s) per socket:      4
    Socket(s):               1
    Stepping:                r0p1
    Frequency boost:         disabled
    CPU(s) scaling MHz:      100%
    CPU max MHz:             1800.0000
    CPU min MHz:             800.0000
    BogoMIPS:                2000.00
    Flags:                   fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 s
                             m4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm sb paca pacg dcpodp sve2 sveaes svepmull svebitperm svesha
                             3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti mte ecv afp mte3 wfxt
  Model name:                Cortex-A720
    BIOS Model name:         CIX P1 CD8160   CPU @ 1.5GHz
    BIOS CPU family:         258
    Model:                   1
    Thread(s) per core:      1
    Core(s) per socket:      8
    Socket(s):               1
    Stepping:                r0p1
    CPU(s) scaling MHz:      100%
    CPU max MHz:             2600.0000
    CPU min MHz:             800.0000
    BogoMIPS:                2000.00
    Flags:                   fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 sm3 s
                             m4 asimddp sha512 sve asimdfhm dit uscat ilrcpc flagm sb paca pacg dcpodp sve2 sveaes svepmull svebitperm svesha
                             3 svesm4 flagm2 frint svei8mm svebf16 i8mm bf16 dgh bti mte ecv afp mte3 wfxt
Caches (sum of all):
  L1d:                       640 KiB (12 instances)
  L1i:                       640 KiB (12 instances)
  L2:                        6 MiB (9 instances)
  L3:                        12 MiB (1 instance)
NUMA:
  NUMA node(s):              1
  NUMA node0 CPU(s):         0-11
Vulnerabilities:
  Gather data sampling:      Not affected
  Ghostwrite:                Not affected
  Indirect target selection: Not affected
  Itlb multihit:             Not affected
  L1tf:                      Not affected
  Mds:                       Not affected
  Meltdown:                  Not affected
  Mmio stale data:           Not affected
  Old microcode:             Not affected
  Reg file data sampling:    Not affected
  Retbleed:                  Not affected
  Spec rstack overflow:      Not affected
  Spec store bypass:         Not affected
  Spectre v1:                Mitigation; __user pointer sanitization
  Spectre v2:                Mitigation; CSV2, BHB
  Srbds:                     Not affected
  Tsa:                       Not affected
  Tsx async abort:           Not affected
  Vmscape:                   Not affected

# lscpu -C
NAME ONE-SIZE ALL-SIZE WAYS TYPE        LEVEL SETS PHY-LINE COHERENCY-SIZE
L1d       64K     640K      Data            1                           64
L1i       64K     640K      Instruction     1                           64
L2       512K       6M      Unified         2                           64
L3        12M      12M      Unified         3                           64

# for c in /sys/devices/system/cpu/cpu[0-9]*; do
    echo "===== $(basename "$c") ====="
    for i in "$c"/cache/index*; do
        [ -d "$i" ] || continue
        printf '%s level=%s type=%s size=%s id=%s shared=%s\n' \
            "$(basename "$i")" \
            "$(cat "$i/level" 2>/dev/null)" \
            "$(cat "$i/type" 2>/dev/null)" \
            "$(cat "$i/size" 2>/dev/null)" \
            "$(cat "$i/id" 2>/dev/null)" \
            "$(cat "$i/shared_cpu_list" 2>/dev/null)"
    done
done
===== cpu0 =====
index0 level=1 type=Data size=64K id=256 shared=0
index1 level=1 type=Instruction size=64K id=384 shared=0
index2 level=2 type=Unified size=512K id=528 shared=0
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu1 =====
index0 level=1 type=Data size=64K id=257 shared=1
index1 level=1 type=Instruction size=64K id=385 shared=1
index2 level=2 type=Unified size=512K id=529 shared=1
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu10 =====
index0 level=1 type=Data size=64K id=266 shared=10
index1 level=1 type=Instruction size=64K id=394 shared=10
index2 level=2 type=Unified size=512K id=538 shared=10
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu11 =====
index0 level=1 type=Data size=64K id=267 shared=11
index1 level=1 type=Instruction size=64K id=395 shared=11
index2 level=2 type=Unified size=512K id=539 shared=11
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu2 =====
index0 level=1 type=Data size=32K id=258 shared=2
index1 level=1 type=Instruction size=32K id=386 shared=2
index2 level=2 type=Unified size=2048K id=512 shared=2-5
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu3 =====
index0 level=1 type=Data size=32K id=259 shared=3
index1 level=1 type=Instruction size=32K id=387 shared=3
index2 level=2 type=Unified size=2048K id=512 shared=2-5
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu4 =====
index0 level=1 type=Data size=32K id=260 shared=4
index1 level=1 type=Instruction size=32K id=388 shared=4
index2 level=2 type=Unified size=2048K id=512 shared=2-5
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu5 =====
index0 level=1 type=Data size=32K id=261 shared=5
index1 level=1 type=Instruction size=32K id=389 shared=5
index2 level=2 type=Unified size=2048K id=512 shared=2-5
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu6 =====
index0 level=1 type=Data size=64K id=262 shared=6
index1 level=1 type=Instruction size=64K id=390 shared=6
index2 level=2 type=Unified size=512K id=534 shared=6
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu7 =====
index0 level=1 type=Data size=64K id=263 shared=7
index1 level=1 type=Instruction size=64K id=391 shared=7
index2 level=2 type=Unified size=512K id=535 shared=7
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu8 =====
index0 level=1 type=Data size=64K id=264 shared=8
index1 level=1 type=Instruction size=64K id=392 shared=8
index2 level=2 type=Unified size=512K id=536 shared=8
index3 level=3 type=Unified size=12288K id=768 shared=0-11
===== cpu9 =====
index0 level=1 type=Data size=64K id=265 shared=9
index1 level=1 type=Instruction size=64K id=393 shared=9
index2 level=2 type=Unified size=512K id=537 shared=9
index3 level=3 type=Unified size=12288K id=768 shared=0-11

The cache hierarchy described in the updated PPTT was reconstructed by reading the available CIX documentation and matching it with the Linux cache topology exposed by the hardware. According to the CIX P1 block diagram, the correct cache hierarchy is:

• One shared 12 MiB L3 cache for the entire CPU complex.
• Two Cortex-A720 clusters, each containing four cores with private 64 KiB L1 Data, 64 KiB L1 Instruction and 512 KiB L2 caches per core.
• One Cortex-A520 cluster containing four cores with private 32 KiB L1 Data, 32 KiB L1 Instruction caches and one shared 2 MiB L2 cache for the entire cluster.

At this point, the remaining ACPI issue appears to be the CPU frequency information, since the cache topology is now correctly exposed to the operating system. Correcting the cache hierarchy alone already provides a much more accurate hardware description for Linux, hwloc and applications such as XMRig, and should serve as a solid foundation for completing the remaining ACPI fixes.

[MartJohnson]

@coffnix I ran your test(s) on MS-R1, this is with the manufacturer supplied ACPI and has not any modifications done:

echo "===== $(basename "$c") ====="
for i in "$c"/cache/index*; do
[ -d "$i" ] || continue
printf '%s level=%s type=%s size=%s id=%s shared=%s\n'
"$(basename "$i")"
"$(cat "$i/level" 2>/dev/null)"
"$(cat "$i/type" 2>/dev/null)"
"$(cat "$i/size" 2>/dev/null)"
"$(cat "$i/id" 2>/dev/null)"
"$(cat "$i/shared_cpu_list" 2>/dev/null)"
done
done

output.txt

Hope this info is helpful.

[coffnix]

@coffnix I ran your test(s) on MS-R1, this is with the manufacturer supplied ACPI and has not any modifications done:

echo "===== $(basename "$c") =====" for i in "$c"/cache/index*; do [ -d "$i" ] || continue printf '%s level=%s type=%s size=%s id=%s shared=%s\n' "$(basename "$i")" "$(cat "$i/level" 2>/dev/null)" "$(cat "$i/type" 2>/dev/null)" "$(cat "$i/size" 2>/dev/null)" "$(cat "$i/id" 2>/dev/null)" "$(cat "$i/shared_cpu_list" 2>/dev/null)" done done

output.txt

Hope this info is helpful.

New script python:

#!/usr/bin/env python3

import struct
from pathlib import Path


OUTPUT = Path("/root/latest-acpi/build/pptt.aml")

HEADER_SIZE = 36

PPTT_PROCESSOR = 0
PPTT_CACHE = 1

PROCESSOR_PHYSICAL_PACKAGE = 1 << 0
PROCESSOR_ID_VALID = 1 << 1
PROCESSOR_LEAF = 1 << 3
PROCESSOR_IDENTICAL = 1 << 4

CACHE_SIZE_VALID = 1 << 0
CACHE_TYPE_VALID = 1 << 4
CACHE_LINE_SIZE_VALID = 1 << 6
CACHE_ID_VALID = 1 << 7

CACHE_FLAGS = (
    CACHE_SIZE_VALID
    | CACHE_TYPE_VALID
    | CACHE_LINE_SIZE_VALID
    | CACHE_ID_VALID
)

CACHE_TYPE_DATA = 0x00
CACHE_TYPE_INSTRUCTION = 0x04
CACHE_TYPE_UNIFIED = 0x08

CACHE_LINE_SIZE = 64

L1_A720_SIZE = 64 * 1024
L1_A520_SIZE = 32 * 1024

L2_PRIVATE_SIZE = 512 * 1024

L3_DSU_SIZE = 12 * 1024 * 1024


class TableBuilder:
    def __init__(self):
        self.entries = []
        self.offset = HEADER_SIZE

    def reserve_processor(self, resource_count):
        length = 20 + resource_count * 4
        offset = self.offset

        self.entries.append(
            {
                "kind": "processor",
                "offset": offset,
                "length": length,
                "data": None,
            }
        )

        self.offset += length
        return offset

    def reserve_cache(self):
        length = 28
        offset = self.offset

        self.entries.append(
            {
                "kind": "cache",
                "offset": offset,
                "length": length,
                "data": None,
            }
        )

        self.offset += length
        return offset

    def set_processor(
        self,
        offset,
        flags,
        parent,
        processor_id,
        resources,
    ):
        entry = self.find(offset)

        length = 20 + len(resources) * 4

        if length != entry["length"]:
            raise ValueError(
                f"Tamanho incorreto para processor em 0x{offset:x}"
            )

        data = struct.pack(
            "<BBHIIII",
            PPTT_PROCESSOR,
            length,
            0,
            flags,
            parent,
            processor_id,
            len(resources),
        )

        for resource in resources:
            data += struct.pack("<I", resource)

        entry["data"] = data

    def set_cache(
        self,
        offset,
        next_level,
        size,
        cache_type,
        cache_id,
    ):
        entry = self.find(offset)

        data = struct.pack(
            "<BBHIIIIBBHI",
            PPTT_CACHE,
            28,
            0,
            CACHE_FLAGS,
            next_level,
            size,
            0,
            0,
            cache_type,
            CACHE_LINE_SIZE,
            cache_id,
        )

        if len(data) != 28:
            raise ValueError(
                f"Tamanho incorreto para cache em 0x{offset:x}"
            )

        entry["data"] = data

    def find(self, offset):
        for entry in self.entries:
            if entry["offset"] == offset:
                return entry

        raise KeyError(
            f"Entrada não encontrada em 0x{offset:x}"
        )

    def payload(self):
        result = bytearray()

        for entry in self.entries:
            if entry["data"] is None:
                raise ValueError(
                    f"Entrada sem dados em 0x{entry['offset']:x}"
                )

            if len(entry["data"]) != entry["length"]:
                raise ValueError(
                    f"Tamanho divergente em 0x{entry['offset']:x}"
                )

            result.extend(entry["data"])

        return bytes(result)


builder = TableBuilder()

package = builder.reserve_processor(0)

cluster1 = builder.reserve_processor(0)
cpu0 = builder.reserve_processor(2)
cpu1 = builder.reserve_processor(2)

cluster2 = builder.reserve_processor(0)
cpu2 = builder.reserve_processor(2)
cpu3 = builder.reserve_processor(2)
cpu4 = builder.reserve_processor(2)
cpu5 = builder.reserve_processor(2)

cluster3 = builder.reserve_processor(0)
cpu6 = builder.reserve_processor(2)
cpu7 = builder.reserve_processor(2)

cluster4 = builder.reserve_processor(0)
cpu8 = builder.reserve_processor(2)
cpu9 = builder.reserve_processor(2)

cluster5 = builder.reserve_processor(0)
cpu10 = builder.reserve_processor(2)
cpu11 = builder.reserve_processor(2)

cpu_offsets = [
    cpu0,
    cpu1,
    cpu2,
    cpu3,
    cpu4,
    cpu5,
    cpu6,
    cpu7,
    cpu8,
    cpu9,
    cpu10,
    cpu11,
]

a520_cpus = {2, 3, 4, 5}

l3_dsu = builder.reserve_cache()

cache_offsets = {}

for cpu_id in range(12):
    l1d = builder.reserve_cache()
    l1i = builder.reserve_cache()
    l2 = builder.reserve_cache()

    cache_offsets[cpu_id] = {
        "l1d": l1d,
        "l1i": l1i,
        "l2": l2,
    }

builder.set_processor(
    package,
    PROCESSOR_PHYSICAL_PACKAGE | PROCESSOR_ID_VALID,
    0,
    0,
    [],
)

cluster_flags = (
    PROCESSOR_ID_VALID
    | PROCESSOR_IDENTICAL
)

builder.set_processor(
    cluster1,
    cluster_flags,
    package,
    1,
    [],
)

builder.set_processor(
    cluster2,
    cluster_flags,
    package,
    2,
    [],
)

builder.set_processor(
    cluster3,
    cluster_flags,
    package,
    3,
    [],
)

builder.set_processor(
    cluster4,
    cluster_flags,
    package,
    4,
    [],
)

builder.set_processor(
    cluster5,
    cluster_flags,
    package,
    5,
    [],
)

cpu_parents = {
    0: cluster1,
    1: cluster1,
    2: cluster2,
    3: cluster2,
    4: cluster2,
    5: cluster2,
    6: cluster3,
    7: cluster3,
    8: cluster4,
    9: cluster4,
    10: cluster5,
    11: cluster5,
}

leaf_flags = (
    PROCESSOR_ID_VALID
    | PROCESSOR_LEAF
    | PROCESSOR_IDENTICAL
)

for cpu_id, cpu_offset in enumerate(cpu_offsets):
    caches = cache_offsets[cpu_id]

    builder.set_processor(
        cpu_offset,
        leaf_flags,
        cpu_parents[cpu_id],
        cpu_id,
        [
            caches["l1d"],
            caches["l1i"],
        ],
    )

builder.set_cache(
    l3_dsu,
    0,
    L3_DSU_SIZE,
    CACHE_TYPE_UNIFIED,
    0x300,
)

for cpu_id in range(12):
    caches = cache_offsets[cpu_id]

    if cpu_id in a520_cpus:
        l1_size = L1_A520_SIZE
    else:
        l1_size = L1_A720_SIZE

    l2_size = L2_PRIVATE_SIZE

    builder.set_cache(
        caches["l2"],
        l3_dsu,
        l2_size,
        CACHE_TYPE_UNIFIED,
        0x200 + cpu_id,
    )

    builder.set_cache(
        caches["l1d"],
        caches["l2"],
        l1_size,
        CACHE_TYPE_DATA,
        0x100 + cpu_id,
    )

    builder.set_cache(
        caches["l1i"],
        caches["l2"],
        l1_size,
        CACHE_TYPE_INSTRUCTION,
        0x180 + cpu_id,
    )

payload = builder.payload()
table_length = HEADER_SIZE + len(payload)

header = struct.pack(
    "<4sIBB6s8sI4sI",
    b"PPTT",
    table_length,
    3,
    0,
    b"CIXTEK",
    b"SKY1EDK2",
    0x01000107,
    b"CIX ",
    1,
)

table = bytearray(header + payload)

checksum = (-sum(table)) & 0xFF
table[9] = checksum

if sum(table) & 0xFF:
    raise RuntimeError(
        "Checksum ACPI inválido"
    )

OUTPUT.write_bytes(table)

processor_entries = sum(
    1
    for entry in builder.entries
    if entry["kind"] == "processor"
)

cache_entries = sum(
    1
    for entry in builder.entries
    if entry["kind"] == "cache"
)

print(f"Output file: {OUTPUT}")
print(f"Table size: {len(table)} bytes")
print(f"Checksum: 0x{checksum:02X}")
print(f"Total entries: {len(builder.entries)}")
print(f"Processor entries: {processor_entries}")
print(f"Cache entries: {cache_entries}")
print("PPTT revision: 3")
print("Cortex-A720: private 64 KiB L1D + 64 KiB L1I + private 512 KiB L2")
print("Cortex-A520: private 32 KiB L1D + 32 KiB L1I + private 512 KiB L2")
print("Shared DSU L3: 12 MiB shared across CPUs 0-11")
print("Expected total private L2: 6144 KiB (6 MiB)")
print("Expected shared L3: 12288 KiB (12 MiB)")
print("Topology follows the intended CIX P1 cache layout")

[coffnix]

command to check:

echo "=== Check: ACPI PPTT override loaded ==="
dmesg | grep -iE 'ACPI.*(PPTT|Table Upgrade|Physical table override)'

echo
echo "=== Check: CPU and cache summary ==="
lscpu

echo
echo "=== Check: Cache summary only ==="
lscpu -C

echo
echo "=== Check: hwloc topology ==="
hwloc-ls

echo
echo "=== Check: sysfs cache topology ==="
for c in /sys/devices/system/cpu/cpu[0-9]*; do
    echo "===== $(basename "$c") ====="
    for i in "$c"/cache/index*; do
        [ -d "$i" ] || continue
        printf '%s level=%s type=%s size=%s id=%s shared=%s\n' \
            "$(basename "$i")" \
            "$(cat "$i/level")" \
            "$(cat "$i/type")" \
            "$(cat "$i/size")" \
            "$(cat "$i/id")" \
            "$(cat "$i/shared_cpu_list")"
    done
done

echo
echo "=== Check: PMU groups ==="
for p in /sys/bus/event_source/devices/armv8_pmuv3_*; do
    echo "===== $(basename "$p") ====="
    cat "$p/cpus"
done

echo
echo "=== Check: Cache register dump ==="
dmesg | grep 'cache_regs:'

echo
echo "=== Check: PPTT disassembly ==="
iasl -d /root/latest-acpi/build/pptt.aml >/dev/null 2>&1
grep -nE 'Processor ID|Cache ID|Size|Next Level of Cache|Flags|Type|Number of Private Resources' \
    /root/latest-acpi/build/pptt.dsl

[amazingfate]

ACPI PPTT table and devicetree lack cpu cache info. Please check if the attached edk2 patch works for acpi.

9ef122e.diff.zip

[srcshelton]

ACPI PPTT table and devicetree lack cpu cache info. Please check if the attached edk2 patch works for acpi.

9ef122e.diff.zip

If I'm reading this correctly, this patch creates a stated-valid zero-sized A520 L2 cache and then links the A520 L1 cache to this. This forces the 12MB shared cache to appear as L3 on all nodes.

My understanding is that this is not correct (and it doesn't reflect CLIDR_EL1 register contents): for the A520 cores the 12MB cache is legitimately their L2.

If would also be beneficial to migrate to revision 3/ACPI 6.4 PPTT cache structures (from current revision 2/ACPI6.3) in order to give the shared 12 MiB cache a valid common Cache ID, so that Linux can then recognise the same physical last-level cache across A520 L2 and A720 L3 using that Cache ID - otherwise the hardware cache configuration cannot be correctly represented in PPTT.

(Support for ACPI 6.4 PPTT Cache structures has been in Linux since kernel 5.14, so should present no issue with the CIX BSP 6.1.x or 6.6.x kernels)

[amazingfate]

ACPI PPTT table and devicetree lack cpu cache info. Please check if the attached edk2 patch works for acpi.
9ef122e.diff.zip

If I'm reading this correctly, this patch creates a stated-valid zero-sized A520 L2 cache and then links the A520 L1 cache to this. This forces the 12MB shared cache to appear as L3 on all nodes.

My understanding is that this is not correct (and it doesn't reflect CLIDR_EL1 register contents): for the A520 cores the 12MB cache is legitimately their L2.

If would also be beneficial to migrate to revision 3/ACPI 6.4 PPTT cache structures (from current revision 2/ACPI6.3) in order to give the shared 12 MiB cache a valid common Cache ID, so that Linux can then recognise the same physical last-level cache across A520 L2 and A720 L3 using that Cache ID - otherwise the hardware cache configuration cannot be correctly represented in PPTT.

(Support for ACPI 6.4 PPTT Cache structures has been in Linux since kernel 5.14, so should present no issue with the CIX BSP 6.1.x or 6.6.x kernels)

After the patch, cache info should look like: