Stuck at sim = Simulator()

[mayank-kabra2001]

from typing import List

from nmigen import *
from nmigen.back.pysim import Simulator, Delay, Settle
from nmigen import Elaboratable,Module,Signal
from nmigen.build import Platform
from nmigen.cli import main_parser,main_runner

class Adder(Elaboratable):
def init(self):
self.x = Signal(8)
self.y = Signal(8)
self.out = Signal(8)

def elaborate(self,platform:Platform)->Module:
    m = Module()
    mydomain = ClockDomain("clk")
    m.domains += mydomain

    m.d.sync += self.out.eq(self.x+self.y)

    return m

def ports(self)->List[Signal]:
    return [self.x,self.y,self.out]

if name == "main":
parser = main_parser()
args = parser.parse_args()

m = Module()
m.submodules.adder = adder = Adder()

x = Signal(8)
y = Signal(8)
m.d.mydomain += adder.x.eq(x)
m.d.mydomain += adder.y.eq(y)

sim = Simulator(m)
sim.add_clock(1e-9, domain="clk")


def process():
    yield x.eq(0x00)
    yield y.eq(0x00)
    #yield Delay(1e-6)
    yield x.eq(0xFF)
    yield y.eq(0xFF)
    #yield Delay(1e-6)
    yield x.eq(0x00)
    yield y.eq(0xFF)
    #yield Delay(1e-6)

sim.add_sync_process(process,domain = "clk")
with sim.write_vcd("test.vcd","test.gtkw",traces=[x,y]+adder.ports()):
sim.run_until(1e-6, run_passive=True)

I am compiling this code and when i see the test.vcd file there is no clk being generated. Can someone help me out