PoolController/PoolController.vhd at main · Riizv/PoolController · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
library ieee;

use ieee.std_logic_1164.all;

entity PoolController is

    port (
        clk : in std_logic;
        reset : in std_logic;
        level_sensor : in std_logic_vector(1 downto 0);
        pump : out std_logic
    );

end entity PoolController;

architecture arch of PoolController is
    type state is (idle, pumping);
    signal current_state, next_state : state;
    signal level_sensor_counter: std_logic_vector(1 downto 0);

begin

    process(clk, reset)
    begin
        if reset = '1' then
            current_state <= idle;
            level_sensor_counter <= "00";
        elsif rising_edge(clk) then
            current_state <= next_state;
            level_sensor_counter <= level_sensor_counter + '1';
        end if;
    end process;


    process(current_state, level_sensor_counter)
    begin
        case current_state is
            when idle =>
                if level_sensor_counter = "00" then
                    next_state <= idle;
                    pump <= '0';
                elsif level_sensor_counter = "01" then
                    next_state <= pumping;
                    pump <= '1';
                elsif level_sensor_counter = "10" then
                    next_state <= idle;
                    pump <= '0';
                else
                    next_state <= idle;
                    pump <= '0';
                end if;
            when pumping =>
                if level_sensor_counter = "00" then
                    next_state <= idle;
                    pump <= '0';
                elsif level_sensor_counter = "01" then
                    next_state <= pumping;
                    pump <= '1';
                elsif level_sensor_counter = "10" then
                    next_state <= idle;
                    pump <= '0';
                else
                    next_state <= idle;
                    pump <= '0';
                end if;
        end case;
    end process;

end architecture arch;