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Software Mitigations for "A Security RISC" by Gerlach, Weber, Zhang and Schwarz

This repository contains the software mitigations for the novel attack primitives presented in the IEEE S&P 2023 paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs".

This repository is part of a project in "CS4702-Computer Security" at University of Lübeck.

Testing Device:

Mitigations

The proposed mitigations are:

  • Disable+Emulate: Disable the RISC-V performance counters and emulate the values to make all attacks less reliable
  • Catch+Wait: Wait on context switch to make Flush+Fault attacks less reliable
  • Switch+Clear: Clear the I-Cache on every context switch to make Flush+Fault attacks infeasible

The mitigations require custom Linux kernel patches that can be found under custom-kernel.

Benchmarks

All benchmarks can be run automatically by using the run-all.sh script:

cd ./kernel_modules/benchmarks && sudo ./run-all.sh

Simple Testing Programs for Hardware Performance Counters

To test the availability of the performance counters and their output, we added simple testing programs that simply print the value of each counter. They can be found under printers.