aarch32: Missing and superfluous instructions for version 6

[BadGraphixD]

I oriented myself on the ARM Architecture Reference Manual. I did not investigate whether the currently present instructions are implemented correctly or whether all variants are present.

Two general points:

• Our stm instruction mnemonics put the addressing mode before the condition, but it should come after the condition. So e.g. stmdaeq should be stmeqda.
• The instruction svc, which was called swi in version 6.

Superflous instructions (for version 6)

1. SDIV
2. UDIV

Missing instructions (for complete version 6 base instruction set)

1. BKPT
2. BLX (1)
3. BXJ
4. CDP
5. CDP2
6. CLZ
7. CPS
8. CPY
9. LDC
10. LDC2
11. LDRD
12. LDRBT
13. LDREX
14. LDRT
15. MCR
16. MCR2
17. MCRR
18. MCRR2
19. MRC
20. MRC2
21. MRRC
22. MRRC2
23. MSR
24. MVN
25. PKH (both forms)
26. PLD
27. QADD
28. QADD16
29. QADD8
30. QADDSUBX
31. QDADD
32. QDSUB
33. QSUB
34. QSUB16
35. QSUB8
36. QSUBADDX
37. REV (all forms)
38. RFE
39. RSC
40. SADD (all forms)
41. SEL
42. SETEND
43. SHADD (all forms)
44. SHSUB (all forms)
45. SMLAD
46. SMLALD
47. SMLA<x><y> (BB, TT, BT, TB)
48. SMLAL<x><y (BB, TT, BT, TB)
49. SMLAW<y> (B, T)
50. SMLSD
51. SMLSLD
52. SMMLA
53. SMMLS
54. SMMUL
55. SMUAD
56. SMUL<x><y> (BB, TT, BT, TB)
57. SMULW<y> (B, T)
58. SMUSD
59. SRS
60. SSAT (both forms)
61. SSUB (all forms)
62. STC
63. STC2
64. STM (2)
65. STRBT
66. STRD
67. STREX
68. STRH
69. STRT
70. SWI
71. SWP (depricated)
72. SWPB (depricated)
73. SXT (all forms)
74. UADD (all forms)
75. UHADD (all forms)
76. UHSUB (all forms)
77. UMAAL
78. UQADD (all forms)
79. UQSUB (all forms)
80. USAD (both forms)
81. USAT (both forms)
82. USUB (all forms)
83. UXT (all forms)

Missing instructions (for non-fp benchmarks)

These I have generated from the combined dump of all benchmark text sections. Pseudo instructions can be ignored.

1. clz
2. clzeq
3. ldmgt // all conditional ldm are implemented
4. ldrd
5. lslcc (pseudo for mov)
6. lsleq (pseudo for mov)
7. lslne (pseudo for mov)
8. lsrcs (pseudo for mov)
9. lsreq (pseudo for mov)
10. lsrhi (pseudo for mov)
11. lsrne (pseudo for mov)
12. lsrs (pseudo for mov)
13. lsrsne (pseudo for mov)
14. mvn
15. mvneq
16. mvnhi
17. mvnne
18. nop (pseudo for mov)
19. pop (pseudo for ldr/ldm)
20. popeq (pseudo for ldr/ldm)
21. popge (pseudo for ldr/ldm)
22. pople (pseudo for ldr/ldm)
23. popls (pseudo for ldr/ldm)
24. popne (pseudo for ldr/ldm)
25. push (pseudo for str/stm)
26. rev
27. smlabb
28. smulbb
29. strd
30. sxth
31. sxthhi
32. uxtab
33. uxtah
34. uxtb
35. uxtbeq
36. uxtbls
37. uxtbne
38. uxth
39. uxthhi
40. uxthne

[BadGraphixD]

@AndreasKrall @Jozott00 these are the missing instructions for aarch32. The last list is the minimum set of instructions needed to get the aarch32 non-fp benchmarks to run.