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frontend/vdt/iss: select ISA dynamically on register values, specify exception for undefined/illegal instructions #1029

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@AndreasKrall

A processor can execute different instruction sets depending on the processor state. Common examples are that certain instructions are only allowed if the processor executes in a higher privilege level or if vector ISAs are dynamically enabled and disabled.

Currently it is only possible to check this register state or privilege level in every restricted instruction and raise an exception if the restrictions apply, e.g.:

      if CurrentEL = 0
        then raise $UndefinedException ()
        else match sysreg with
          { SysRegEncode::CurrentEL => X(rt) := CurrentEL as BitsX << 2
          , SysRegEncode::SPSel     => X(rt) := SPSel as BitsX
          ...
          , _                       => raise $UndefinedException ()
          }

This is cumbersome and should be improved by adding an annotation either to a single instruction or to a whole ISA.
I will first start a discussion how this annotation should look like. There are different options like putting everything in a single annotation or a pair of annotations separating the specification the condition and the selection of the exception.
Furthermore, currently it is not possible to define the exception/behavior what happens when an illegal instruction is encountered, it is handled implicitly by the decoder.
Eventually the same annotation (syntax) also could be used when attaching exceptions to the memory.
Here some ideas:

[raise IllegalInstruction when : CurrentEL = 0]       // IllegalInstruction is the name of an exception
[raise IllegalInstruction when : CPACR_EL1.smen = 0]  // IllegalInstruction when SME is not enabled

Please add further ideas.
There will be problems like adding arguments. In the old specification example the exception is raised by a model invocation.
Probably these fields should also go into the QEMU translation block state.

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