From ede9f2ddfb133fb6a29e68835a15de39808c0711 Mon Sep 17 00:00:00 2001 From: Shane Caldwell Date: Sat, 6 Jun 2026 07:16:48 -0500 Subject: [PATCH 1/3] [docs] Clarify HSB RFSoC artifact locations Signed-off-by: Shane Caldwell --- docs/sphinx/using/realtime/host.md | 4 ++-- docs/sphinx/using/realtime/installation.rst | 11 ++++++--- realtime/docs/building.md | 14 ++++++++++-- realtime/docs/cudaq_realtime_host_api.md | 4 ++-- realtime/docs/nvqlink_latency_demo.md | 17 +++++++++++++- realtime/docs/user_guide.md | 25 ++++++++++++++++----- 6 files changed, 59 insertions(+), 16 deletions(-) diff --git a/docs/sphinx/using/realtime/host.md b/docs/sphinx/using/realtime/host.md index ab5ea40871a..8495e900cd7 100644 --- a/docs/sphinx/using/realtime/host.md +++ b/docs/sphinx/using/realtime/host.md @@ -18,7 +18,7 @@ using RDMA (Remote Direct Memory Access) via ConnectX NIC's. In the context of quantum error correction, HSB is one example of a transport mechanism that connects the quantum control system (typically an FPGA) to GPU-based decoders. -**Repository**: [`nvidia-holoscan`/`holoscan-sensor-bridge` (`nvqlink` branch)](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/nvqlink) +**Repository**: [`nvidia-holoscan`/`holoscan-sensor-bridge` (`2.6.0-EA2` tag)](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/2.6.0-EA2) HSB handles: @@ -392,7 +392,7 @@ struct RPCResponse { }; ``` -Both structs are 24 bytes, packed with no padding. See `cudaq_realtime_message_protocol.bs` +Both structs are 24 bytes, packed with no padding. See `cudaq_realtime_message_protocol.md` for `request_id` and `ptp_timestamp` semantics. Payload conventions: diff --git a/docs/sphinx/using/realtime/installation.rst b/docs/sphinx/using/realtime/installation.rst index 1a3319462ee..f71f0524227 100644 --- a/docs/sphinx/using/realtime/installation.rst +++ b/docs/sphinx/using/realtime/installation.rst @@ -39,8 +39,13 @@ Setup - Follow the instructions given by the installer for post-installation steps to set environment variables. - - Load HSB IP bit-file to the FPGA. - The bit-file for supported FPGA vendors can be found `here `__. + - Load the HSB IP bit-file to the FPGA. + The HSB 2.6.0-EA RFSoC artifacts are split across two locations. The `HSB-2.6.0-EA URM directory `__ contains the prebuilt ``nvqlink_rfsoc_v2603.bit`` bit-file and the ``pynq_rfsoc_2603_EA_release.zip`` RFSoC PYNQ reference-design archive. + The matching ``nv_hsb_ip`` source directory is in the `Holoscan Sensor Bridge release-2.6.0-EA branch `__. + + When building the RFSoC project from the PYNQ archive, place the ``nv_hsb_ip`` directory from that release branch at the same level as the archive's ``pynq`` directory. + Do not mix ``nv_hsb_ip`` from an older HSB release with the HSB 2.6.0-EA RFSoC collateral. + The included RFSoC PYNQ build project targets ``xczu48dr-ffvg1517-2-e``; for another RFSoC part, update the Vivado part and constraints in ``pynq/rfsoc-pynq/build/build.tcl`` and rebuild the bit-file. .. note:: @@ -114,7 +119,7 @@ The validation includes checking the data correctness and measuring the round-tr .. tab:: Using Custom Networking Layer - To measure the latency with a custom networking implementation, a stimulus (data generation) tool must the implemented that sends data to CUDA-Q realtime according to the custom networking protocol. + To measure latency with a custom networking implementation, implement a stimulus (data generation) tool that sends data to CUDA-Q Realtime according to the custom networking protocol. For example, in the HSB-based implementation, we use the `ptp_timestamp` field in the `RPCHeader` / `RPCResponse` (see the message protocol documentation) to capture the timestamp for latency analysis. Specifically, the stimulus tool (FPGA) stores the 'send' timestamp in the `RPCHeader` (incoming message), which will be echoed by the GPU in the outgoing `RPCResponse` after processing it (e.g., with the RPC handler). Using the Integrated Logic Analyzer timestamp when the FPGA receives the response from the GPU, we can compute the round-trip latency. `This file `__ contains an example of such a data generation tool. diff --git a/realtime/docs/building.md b/realtime/docs/building.md index 4d97eb0171d..7901b4cf661 100644 --- a/realtime/docs/building.md +++ b/realtime/docs/building.md @@ -111,8 +111,18 @@ sub-directory in CUDA-Q source tree. To run the end-to-end RPC dispatch testing between FPGA and GPU using CUDA-Q Realtime and Holoscan Sensor Bridge, -- Load the `HSB` bit-file into the FPGA. -The bit-file can be obtained from [here](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA). +- Load the `HSB` bit-file into the FPGA. The + [HSB-2.6.0-EA URM directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) + contains the prebuilt `nvqlink_rfsoc_v2603.bit` bit-file and + `pynq_rfsoc_2603_EA_release.zip` RFSoC PYNQ reference-design archive. + The matching `nv_hsb_ip` source directory for rebuilding that project is in + the [Holoscan Sensor Bridge `release-2.6.0-EA` branch](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA/fpga/nv_hsb_ip). + When building the RFSoC project from the PYNQ archive, place `nv_hsb_ip` as a + sibling of the archive's `pynq` directory. Do not mix `nv_hsb_ip` from an + older HSB release with the HSB 2.6.0-EA RFSoC collateral. The included RFSoC + PYNQ build project targets `xczu48dr-ffvg1517-2-e`; for another RFSoC part, + update the Vivado part and constraints in `pynq/rfsoc-pynq/build/build.tcl` + and rebuild the bit-file. - Run the test script (at `cuda-quantum/realtime/unittests/utils/hololink_test.sh`). For example, diff --git a/realtime/docs/cudaq_realtime_host_api.md b/realtime/docs/cudaq_realtime_host_api.md index b249ed7ef9f..46fa5e2d723 100644 --- a/realtime/docs/cudaq_realtime_host_api.md +++ b/realtime/docs/cudaq_realtime_host_api.md @@ -355,7 +355,7 @@ TX Slot: | RPCResponse | response payload bytes | ``` Payload encoding details (type system, multi-argument encoding, bit-packing, -and QEC-specific examples) are defined in `cudaq_realtime_message_protocol.bs`. +and QEC-specific examples) are defined in `cudaq_realtime_message_protocol.md`. Magic values (little-endian 32-bit): @@ -381,7 +381,7 @@ struct RPCResponse { }; ``` -Both structs are 24 bytes, packed with no padding. See `cudaq_realtime_message_protocol.bs` +Both structs are 24 bytes, packed with no padding. See `cudaq_realtime_message_protocol.md` for `request_id` and `ptp_timestamp` semantics. Payload conventions: diff --git a/realtime/docs/nvqlink_latency_demo.md b/realtime/docs/nvqlink_latency_demo.md index 2637241cb61..7711aa06604 100644 --- a/realtime/docs/nvqlink_latency_demo.md +++ b/realtime/docs/nvqlink_latency_demo.md @@ -1,6 +1,21 @@ # Steps to execute the NVQLink latency demo -The source Verilog code can be found [here](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/). +The HSB 2.6.0-EA RFSoC collateral is split across two locations. The +[HSB-2.6.0-EA URM directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) +contains the prebuilt `nvqlink_rfsoc_v2603.bit` bit-file and the +`pynq_rfsoc_2603_EA_release.zip` RFSoC PYNQ reference-design archive. +The zip archive contains the RFSoC top-level RTL, Vivado build scripts, +Integrated Logic Analyzer (`ILA`) and latency scripts, and a prebuilt +`pynq_rfsoc_v2603.bit`, but it does not contain the `nv_hsb_ip` source +directory required by its README. + +Download the matching `nv_hsb_ip` source directory from the +[Holoscan Sensor Bridge `release-2.6.0-EA` branch](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA/fpga/nv_hsb_ip). +When building the RFSoC project from the PYNQ archive, place `nv_hsb_ip` +as a sibling of the archive's `pynq` directory. Do not mix `nv_hsb_ip` +from an older HSB release with the HSB 2.6.0-EA RFSoC collateral. +The included RFSoC PYNQ build project targets `xczu48dr-ffvg1517-2-e`; +for another RFSoC part, update `pynq/rfsoc-pynq/build/build.tcl` and constraints. More details about how the `Holoscan Sensor Bridge` (`HSB`) IP can be incorporated can be found [here](https://docs.nvidia.com/holoscan/sensor-bridge/latest/fpga_index.html) diff --git a/realtime/docs/user_guide.md b/realtime/docs/user_guide.md index 98dd1abf1e4..9e7eedf1503 100644 --- a/realtime/docs/user_guide.md +++ b/realtime/docs/user_guide.md @@ -11,9 +11,9 @@ CUDA-Q Realtime, including connectivity to a - A host system with NVIDIA GPU and ConnectX-7/BlueField NIC. -- A FPGA, programmed with `HSB` IP and connected to the NIC. +- An FPGA, programmed with `HSB` IP and connected to the NIC. -> **_NOTE:_** We recommended using NVIDIA ConnectX-7 as prior generations +> **_NOTE:_** We recommend using NVIDIA ConnectX-7 as prior generations may not have all the required capabilities. ### Software Components @@ -26,7 +26,7 @@ may not have all the required capabilities. with `gpunetio` support. > **_NOTE:_** `DOCA` is required to run the end-to-end validation with FPGA -using the builtin `HSB` support of CUDA-Q realtime. +using the built-in `HSB` support of CUDA-Q Realtime. @@ -61,10 +61,23 @@ Please refer to this [section](#using-docker) for instructions. 2. Load `HSB` IP bit-file to the FPGA - The bit-file for supported FPGA vendors - can be found [here](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/). + The HSB 2.6.0-EA RFSoC artifacts are split across two locations: - > **_NOTE:_** Please make sure set up the [host system](https://docs.nvidia.com/holoscan/sensor-bridge/latest/setup.html) + - The [HSB-2.6.0-EA URM directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) + contains the prebuilt `nvqlink_rfsoc_v2603.bit` bit-file and the + `pynq_rfsoc_2603_EA_release.zip` RFSoC PYNQ reference-design archive. + - The matching `nv_hsb_ip` source directory is in the + [Holoscan Sensor Bridge `release-2.6.0-EA` branch](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA/fpga/nv_hsb_ip). + + When building the RFSoC project from the PYNQ archive, place the + `nv_hsb_ip` directory from that release branch at the same level as + the archive's `pynq` directory. Do not mix `nv_hsb_ip` from an older + HSB release with the HSB 2.6.0-EA RFSoC collateral. The included RFSoC + PYNQ build project targets `xczu48dr-ffvg1517-2-e`; for another RFSoC + part, update the Vivado part and constraints in + `pynq/rfsoc-pynq/build/build.tcl` and rebuild the bit-file. + + > **_NOTE:_** Please make sure to set up the [host system](https://docs.nvidia.com/holoscan/sensor-bridge/latest/setup.html) and the `HSB` FPGA device [IP address](https://docs.nvidia.com/holoscan/sensor-bridge/latest/architecture.html#datachannel-enumeration-and-ip-address-configuration) (if not already done so). From d9e5c724f41c85c48677deb74ed4d6fdb0dd6260 Mon Sep 17 00:00:00 2001 From: Shane Caldwell Date: Sun, 7 Jun 2026 11:59:50 -0500 Subject: [PATCH 2/3] docs: pass spellcheck Signed-off-by: Shane Caldwell --- .github/pre-commit/spelling_allowlist.txt | 4 ++++ docs/sphinx/using/realtime/installation.rst | 5 +++-- realtime/docs/building.md | 6 +++--- realtime/docs/nvqlink_latency_demo.md | 12 ++++++------ realtime/docs/user_guide.md | 6 +++--- 5 files changed, 19 insertions(+), 14 deletions(-) diff --git a/.github/pre-commit/spelling_allowlist.txt b/.github/pre-commit/spelling_allowlist.txt index a8c671271a1..4ab50dbf21a 100644 --- a/.github/pre-commit/spelling_allowlist.txt +++ b/.github/pre-commit/spelling_allowlist.txt @@ -100,6 +100,7 @@ Ou POSIX PSIRT PTSBE +PYNQ Pasqal Pauli Paulis @@ -131,10 +132,12 @@ Quake Quantinuum RDMA REPL +RFSoC RHEL RPC RSA RSH +RTL Realtime RoCE SDK @@ -157,6 +160,7 @@ UCCSD VQE Vazirani Verilog +Vivado WSL Xcode Zener diff --git a/docs/sphinx/using/realtime/installation.rst b/docs/sphinx/using/realtime/installation.rst index f71f0524227..b4ae05b9372 100644 --- a/docs/sphinx/using/realtime/installation.rst +++ b/docs/sphinx/using/realtime/installation.rst @@ -40,11 +40,12 @@ Setup - Follow the instructions given by the installer for post-installation steps to set environment variables. - Load the HSB IP bit-file to the FPGA. - The HSB 2.6.0-EA RFSoC artifacts are split across two locations. The `HSB-2.6.0-EA URM directory `__ contains the prebuilt ``nvqlink_rfsoc_v2603.bit`` bit-file and the ``pynq_rfsoc_2603_EA_release.zip`` RFSoC PYNQ reference-design archive. + The HSB 2.6.0-EA RFSoC artifacts are split across two locations. + The `HSB 2.6.0-EA artifact directory `__ contains the pre-built ``nvqlink_rfsoc_v2603.bit`` bit-file and the ``pynq_rfsoc_2603_EA_release.zip`` RFSoC PYNQ reference-design archive. The matching ``nv_hsb_ip`` source directory is in the `Holoscan Sensor Bridge release-2.6.0-EA branch `__. When building the RFSoC project from the PYNQ archive, place the ``nv_hsb_ip`` directory from that release branch at the same level as the archive's ``pynq`` directory. - Do not mix ``nv_hsb_ip`` from an older HSB release with the HSB 2.6.0-EA RFSoC collateral. + Do not mix ``nv_hsb_ip`` from an older HSB release with the HSB 2.6.0-EA RFSoC files. The included RFSoC PYNQ build project targets ``xczu48dr-ffvg1517-2-e``; for another RFSoC part, update the Vivado part and constraints in ``pynq/rfsoc-pynq/build/build.tcl`` and rebuild the bit-file. .. note:: diff --git a/realtime/docs/building.md b/realtime/docs/building.md index 7901b4cf661..a7b3c801c59 100644 --- a/realtime/docs/building.md +++ b/realtime/docs/building.md @@ -112,14 +112,14 @@ To run the end-to-end RPC dispatch testing between FPGA and GPU using CUDA-Q Realtime and Holoscan Sensor Bridge, - Load the `HSB` bit-file into the FPGA. The - [HSB-2.6.0-EA URM directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) - contains the prebuilt `nvqlink_rfsoc_v2603.bit` bit-file and + [HSB 2.6.0-EA artifact directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) + contains the pre-built `nvqlink_rfsoc_v2603.bit` bit-file and `pynq_rfsoc_2603_EA_release.zip` RFSoC PYNQ reference-design archive. The matching `nv_hsb_ip` source directory for rebuilding that project is in the [Holoscan Sensor Bridge `release-2.6.0-EA` branch](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA/fpga/nv_hsb_ip). When building the RFSoC project from the PYNQ archive, place `nv_hsb_ip` as a sibling of the archive's `pynq` directory. Do not mix `nv_hsb_ip` from an - older HSB release with the HSB 2.6.0-EA RFSoC collateral. The included RFSoC + older HSB release with the HSB 2.6.0-EA RFSoC files. The included RFSoC PYNQ build project targets `xczu48dr-ffvg1517-2-e`; for another RFSoC part, update the Vivado part and constraints in `pynq/rfsoc-pynq/build/build.tcl` and rebuild the bit-file. diff --git a/realtime/docs/nvqlink_latency_demo.md b/realtime/docs/nvqlink_latency_demo.md index 7711aa06604..f9417f3d451 100644 --- a/realtime/docs/nvqlink_latency_demo.md +++ b/realtime/docs/nvqlink_latency_demo.md @@ -1,19 +1,19 @@ # Steps to execute the NVQLink latency demo -The HSB 2.6.0-EA RFSoC collateral is split across two locations. The -[HSB-2.6.0-EA URM directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) -contains the prebuilt `nvqlink_rfsoc_v2603.bit` bit-file and the +The HSB 2.6.0-EA RFSoC files are split across two locations. The +[HSB 2.6.0-EA artifact directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) +contains the pre-built `nvqlink_rfsoc_v2603.bit` bit-file and the `pynq_rfsoc_2603_EA_release.zip` RFSoC PYNQ reference-design archive. The zip archive contains the RFSoC top-level RTL, Vivado build scripts, -Integrated Logic Analyzer (`ILA`) and latency scripts, and a prebuilt +Integrated Logic Analyzer (`ILA`) and latency scripts, and a pre-built `pynq_rfsoc_v2603.bit`, but it does not contain the `nv_hsb_ip` source -directory required by its README. +directory required by the archive's build instructions. Download the matching `nv_hsb_ip` source directory from the [Holoscan Sensor Bridge `release-2.6.0-EA` branch](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA/fpga/nv_hsb_ip). When building the RFSoC project from the PYNQ archive, place `nv_hsb_ip` as a sibling of the archive's `pynq` directory. Do not mix `nv_hsb_ip` -from an older HSB release with the HSB 2.6.0-EA RFSoC collateral. +from an older HSB release with the HSB 2.6.0-EA RFSoC files. The included RFSoC PYNQ build project targets `xczu48dr-ffvg1517-2-e`; for another RFSoC part, update `pynq/rfsoc-pynq/build/build.tcl` and constraints. diff --git a/realtime/docs/user_guide.md b/realtime/docs/user_guide.md index 9e7eedf1503..93911ef6349 100644 --- a/realtime/docs/user_guide.md +++ b/realtime/docs/user_guide.md @@ -63,8 +63,8 @@ Please refer to this [section](#using-docker) for instructions. The HSB 2.6.0-EA RFSoC artifacts are split across two locations: - - The [HSB-2.6.0-EA URM directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) - contains the prebuilt `nvqlink_rfsoc_v2603.bit` bit-file and the + - The [HSB 2.6.0-EA artifact directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) + contains the pre-built `nvqlink_rfsoc_v2603.bit` bit-file and the `pynq_rfsoc_2603_EA_release.zip` RFSoC PYNQ reference-design archive. - The matching `nv_hsb_ip` source directory is in the [Holoscan Sensor Bridge `release-2.6.0-EA` branch](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA/fpga/nv_hsb_ip). @@ -72,7 +72,7 @@ Please refer to this [section](#using-docker) for instructions. When building the RFSoC project from the PYNQ archive, place the `nv_hsb_ip` directory from that release branch at the same level as the archive's `pynq` directory. Do not mix `nv_hsb_ip` from an older - HSB release with the HSB 2.6.0-EA RFSoC collateral. The included RFSoC + HSB release with the HSB 2.6.0-EA RFSoC files. The included RFSoC PYNQ build project targets `xczu48dr-ffvg1517-2-e`; for another RFSoC part, update the Vivado part and constraints in `pynq/rfsoc-pynq/build/build.tcl` and rebuild the bit-file. From 7b63602a5cfa84c409ebe844695b4eb48610a450 Mon Sep 17 00:00:00 2001 From: Shane Caldwell Date: Mon, 8 Jun 2026 07:01:04 -0500 Subject: [PATCH 3/3] docs: clarify RTL core vs bitfile, and dedupe Signed-off-by: Shane Caldwell --- docs/sphinx/using/realtime/installation.rst | 26 ++++++++++++++------- realtime/docs/building.md | 15 +++--------- realtime/docs/nvqlink_latency_demo.md | 26 +++++++-------------- realtime/docs/user_guide.md | 21 ++++------------- 4 files changed, 34 insertions(+), 54 deletions(-) diff --git a/docs/sphinx/using/realtime/installation.rst b/docs/sphinx/using/realtime/installation.rst index b4ae05b9372..c8beec5d2d6 100644 --- a/docs/sphinx/using/realtime/installation.rst +++ b/docs/sphinx/using/realtime/installation.rst @@ -26,6 +26,22 @@ Prerequisites - CUDA Runtime with version 12.6+ or 13.x +.. _realtime-hsb-fpga-artifacts: + +HSB FPGA IP core and RFSoC bit-file +----------------------------------- + +The primary FPGA deliverable is the open-source HSB FPGA IP core, ``nv_hsb_ip``. +Integrate this RTL source into your FPGA design when you want to use HSB with your FPGA target. + +The HSB 2.6.0-EA release also provides a fully packaged RFSoC example for the Real Digital RFSoC 4x2 evaluation board, using Vivado part ``xczu48dr-ffvg1517-2-e``. +The `HSB 2.6.0-EA artifact directory `__ contains the pre-built ``nvqlink_rfsoc_v2603.bit`` bit-file and the ``pynq_rfsoc_2603_EA_release.zip`` RFSoC PYNQ reference-design archive. +The matching ``nv_hsb_ip`` source directory is in the `Holoscan Sensor Bridge release-2.6.0-EA branch `__. + +When building the RFSoC project from the PYNQ archive, place the ``nv_hsb_ip`` directory from that release branch at the same level as the archive's ``pynq`` directory. +Do not mix ``nv_hsb_ip`` from an older HSB release with the HSB 2.6.0-EA RFSoC files. +For another RFSoC part or board, update the Vivado part and constraints in ``pynq/rfsoc-pynq/build/build.tcl`` and rebuild the bit-file. + Setup --------------------- @@ -39,14 +55,8 @@ Setup - Follow the instructions given by the installer for post-installation steps to set environment variables. - - Load the HSB IP bit-file to the FPGA. - The HSB 2.6.0-EA RFSoC artifacts are split across two locations. - The `HSB 2.6.0-EA artifact directory `__ contains the pre-built ``nvqlink_rfsoc_v2603.bit`` bit-file and the ``pynq_rfsoc_2603_EA_release.zip`` RFSoC PYNQ reference-design archive. - The matching ``nv_hsb_ip`` source directory is in the `Holoscan Sensor Bridge release-2.6.0-EA branch `__. - - When building the RFSoC project from the PYNQ archive, place the ``nv_hsb_ip`` directory from that release branch at the same level as the archive's ``pynq`` directory. - Do not mix ``nv_hsb_ip`` from an older HSB release with the HSB 2.6.0-EA RFSoC files. - The included RFSoC PYNQ build project targets ``xczu48dr-ffvg1517-2-e``; for another RFSoC part, update the Vivado part and constraints in ``pynq/rfsoc-pynq/build/build.tcl`` and rebuild the bit-file. + - Program the FPGA with HSB. + See :ref:`realtime-hsb-fpga-artifacts` for the reusable ``nv_hsb_ip`` RTL source and the packaged RFSoC example bit-file. .. note:: diff --git a/realtime/docs/building.md b/realtime/docs/building.md index a7b3c801c59..c7b10e1de84 100644 --- a/realtime/docs/building.md +++ b/realtime/docs/building.md @@ -111,18 +111,9 @@ sub-directory in CUDA-Q source tree. To run the end-to-end RPC dispatch testing between FPGA and GPU using CUDA-Q Realtime and Holoscan Sensor Bridge, -- Load the `HSB` bit-file into the FPGA. The - [HSB 2.6.0-EA artifact directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) - contains the pre-built `nvqlink_rfsoc_v2603.bit` bit-file and - `pynq_rfsoc_2603_EA_release.zip` RFSoC PYNQ reference-design archive. - The matching `nv_hsb_ip` source directory for rebuilding that project is in - the [Holoscan Sensor Bridge `release-2.6.0-EA` branch](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA/fpga/nv_hsb_ip). - When building the RFSoC project from the PYNQ archive, place `nv_hsb_ip` as a - sibling of the archive's `pynq` directory. Do not mix `nv_hsb_ip` from an - older HSB release with the HSB 2.6.0-EA RFSoC files. The included RFSoC - PYNQ build project targets `xczu48dr-ffvg1517-2-e`; for another RFSoC part, - update the Vivado part and constraints in `pynq/rfsoc-pynq/build/build.tcl` - and rebuild the bit-file. +- Program the FPGA with `HSB`. + See the [CUDA-Q Realtime installation docs](https://nvidia.github.io/cuda-quantum/latest/using/realtime/installation.html#realtime-hsb-fpga-artifacts) + for the reusable `nv_hsb_ip` RTL source and the packaged RFSoC example bit-file. - Run the test script (at `cuda-quantum/realtime/unittests/utils/hololink_test.sh`). For example, diff --git a/realtime/docs/nvqlink_latency_demo.md b/realtime/docs/nvqlink_latency_demo.md index f9417f3d451..249d2912519 100644 --- a/realtime/docs/nvqlink_latency_demo.md +++ b/realtime/docs/nvqlink_latency_demo.md @@ -1,21 +1,13 @@ # Steps to execute the NVQLink latency demo -The HSB 2.6.0-EA RFSoC files are split across two locations. The -[HSB 2.6.0-EA artifact directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) -contains the pre-built `nvqlink_rfsoc_v2603.bit` bit-file and the -`pynq_rfsoc_2603_EA_release.zip` RFSoC PYNQ reference-design archive. -The zip archive contains the RFSoC top-level RTL, Vivado build scripts, -Integrated Logic Analyzer (`ILA`) and latency scripts, and a pre-built -`pynq_rfsoc_v2603.bit`, but it does not contain the `nv_hsb_ip` source -directory required by the archive's build instructions. - -Download the matching `nv_hsb_ip` source directory from the -[Holoscan Sensor Bridge `release-2.6.0-EA` branch](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA/fpga/nv_hsb_ip). -When building the RFSoC project from the PYNQ archive, place `nv_hsb_ip` -as a sibling of the archive's `pynq` directory. Do not mix `nv_hsb_ip` -from an older HSB release with the HSB 2.6.0-EA RFSoC files. -The included RFSoC PYNQ build project targets `xczu48dr-ffvg1517-2-e`; -for another RFSoC part, update `pynq/rfsoc-pynq/build/build.tcl` and constraints. +Start from the HSB FPGA artifacts described in the +[CUDA-Q Realtime installation docs](https://nvidia.github.io/cuda-quantum/latest/using/realtime/installation.html#realtime-hsb-fpga-artifacts). +For this demo, use the packaged RFSoC PYNQ reference design and place the +matching `nv_hsb_ip` RTL source as described there. + +The RFSoC PYNQ archive contains the top-level RTL, Vivado build scripts, +Integrated Logic Analyzer (`ILA`) and latency scripts, and the pre-built +bit-file for the packaged RFSoC example. More details about how the `Holoscan Sensor Bridge` (`HSB`) IP can be incorporated can be found [here](https://docs.nvidia.com/holoscan/sensor-bridge/latest/fpga_index.html) @@ -30,7 +22,7 @@ the capabilities required. ## Steps to do the experiment -1. Load the bit-file into the FPGA. +1. Load the packaged RFSoC example bit-file into the FPGA. 2. Setup the host to run the experiment. Mainly the IP address of the NIC needs to be set to `192.168.0.101`. More details can be found at the diff --git a/realtime/docs/user_guide.md b/realtime/docs/user_guide.md index 93911ef6349..cfc91acd322 100644 --- a/realtime/docs/user_guide.md +++ b/realtime/docs/user_guide.md @@ -59,23 +59,10 @@ Please refer to this [section](#using-docker) for instructions. > export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/opt/nvidia/cudaq/realtime/lib > ``` -2. Load `HSB` IP bit-file to the FPGA - - The HSB 2.6.0-EA RFSoC artifacts are split across two locations: - - - The [HSB 2.6.0-EA artifact directory](https://edge.urm.nvidia.com/artifactory/sw-holoscan-thirdparty-generic-local/QEC/HSB-2.6.0-EA/) - contains the pre-built `nvqlink_rfsoc_v2603.bit` bit-file and the - `pynq_rfsoc_2603_EA_release.zip` RFSoC PYNQ reference-design archive. - - The matching `nv_hsb_ip` source directory is in the - [Holoscan Sensor Bridge `release-2.6.0-EA` branch](https://github.com/nvidia-holoscan/holoscan-sensor-bridge/tree/release-2.6.0-EA/fpga/nv_hsb_ip). - - When building the RFSoC project from the PYNQ archive, place the - `nv_hsb_ip` directory from that release branch at the same level as - the archive's `pynq` directory. Do not mix `nv_hsb_ip` from an older - HSB release with the HSB 2.6.0-EA RFSoC files. The included RFSoC - PYNQ build project targets `xczu48dr-ffvg1517-2-e`; for another RFSoC - part, update the Vivado part and constraints in - `pynq/rfsoc-pynq/build/build.tcl` and rebuild the bit-file. +2. Program the FPGA with `HSB` + + See the [CUDA-Q Realtime installation docs](https://nvidia.github.io/cuda-quantum/latest/using/realtime/installation.html#realtime-hsb-fpga-artifacts) + for the reusable `nv_hsb_ip` RTL source and the packaged RFSoC example bit-file. > **_NOTE:_** Please make sure to set up the [host system](https://docs.nvidia.com/holoscan/sensor-bridge/latest/setup.html) and the `HSB` FPGA device [IP address](https://docs.nvidia.com/holoscan/sensor-bridge/latest/architecture.html#datachannel-enumeration-and-ip-address-configuration)