From 9c142fade656ade9454ffe1dd700f2613f509c78 Mon Sep 17 00:00:00 2001 From: HenryLee Date: Wed, 22 Apr 2026 11:44:18 +0800 Subject: [PATCH 01/10] feat(designs): add PE_INT synced project snapshot Sync PE_INT into pycircuit designs with English docs/spec, pycc-relative build defaults, and WSL-ready regression scripts. Keep generated artifacts excluded from commit except deliverable generated Verilog. --- .../skills/pe-int-implementation/SKILL.md | 78 +++ .../skills/pe-int-pycircuiteval-flow/SKILL.md | 138 ++++ designs/PE_INT/.gitattributes | 2 + designs/PE_INT/.gitignore | 27 + designs/PE_INT/README.md | 70 ++ designs/PE_INT/docs/design_spec.md | 270 +++++++ designs/PE_INT/docs/spec.md | 184 +++++ designs/PE_INT/filelist/pe_int.f | 2 + designs/PE_INT/memory.md | 3 + designs/PE_INT/model/README.md | 22 + designs/PE_INT/model/depth_probe_units.py | 82 +++ designs/PE_INT/model/estimate_logic_depth.py | 52 ++ designs/PE_INT/model/gen_rtl_case_vectors.py | 264 +++++++ designs/PE_INT/model/model.f | 4 + designs/PE_INT/model/pe_int_pycircuit_eval.py | 100 +++ designs/PE_INT/model/ref_model.py | 153 ++++ designs/PE_INT/model/test_pe_int.py | 178 +++++ designs/PE_INT/python/build.py | 56 ++ designs/PE_INT/python/pe_int/__init__.py | 12 + designs/PE_INT/python/pe_int/constants.py | 14 + designs/PE_INT/python/pe_int/decode.py | 48 ++ designs/PE_INT/python/pe_int/lane_mac.py | 51 ++ designs/PE_INT/python/pe_int/mac_modes.py | 128 ++++ designs/PE_INT/python/pe_int/pipeline.py | 16 + designs/PE_INT/python/pe_int/top.py | 156 +++++ designs/PE_INT/python/pe_int_pycircuit.py | 24 + designs/PE_INT/python/placeholder.py | 0 designs/PE_INT/rtl/README.md | 19 + designs/PE_INT/rtl/pe_int_l3.v | 171 +++++ designs/PE_INT/rtl/pyc_primitives.v | 658 ++++++++++++++++++ designs/PE_INT/sim/README.md | 49 ++ designs/PE_INT/sim/run_all_wsl.sh | 53 ++ designs/PE_INT/sim/run_sim.sh | 267 +++++++ designs/PE_INT/spec_raw.txt | 0 designs/PE_INT/tb/README.md | 14 + designs/PE_INT/tb/tb_pe_int_pycircuit.py | 103 +++ designs/PE_INT/tb_rtl/README.md | 50 ++ designs/PE_INT/tb_rtl/case/README.md | 42 ++ .../PE_INT/tb_rtl/case/common_wave_dump.vh | 27 + designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v | 119 ++++ designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v | 95 +++ designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v | 104 +++ designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v | 95 +++ .../tb_rtl/case/tc_mode_switch_random.v | 120 ++++ designs/PE_INT/tb_rtl/tb.f | 6 + 45 files changed, 4126 insertions(+) create mode 100644 designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md create mode 100644 designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md create mode 100644 designs/PE_INT/.gitattributes create mode 100644 designs/PE_INT/.gitignore create mode 100644 designs/PE_INT/README.md create mode 100644 designs/PE_INT/docs/design_spec.md create mode 100644 designs/PE_INT/docs/spec.md create mode 100644 designs/PE_INT/filelist/pe_int.f create mode 100644 designs/PE_INT/memory.md create mode 100644 designs/PE_INT/model/README.md create mode 100644 designs/PE_INT/model/depth_probe_units.py create mode 100644 designs/PE_INT/model/estimate_logic_depth.py create mode 100644 designs/PE_INT/model/gen_rtl_case_vectors.py create mode 100644 designs/PE_INT/model/model.f create mode 100644 designs/PE_INT/model/pe_int_pycircuit_eval.py create mode 100644 designs/PE_INT/model/ref_model.py create mode 100644 designs/PE_INT/model/test_pe_int.py create mode 100644 designs/PE_INT/python/build.py create mode 100644 designs/PE_INT/python/pe_int/__init__.py create mode 100644 designs/PE_INT/python/pe_int/constants.py create mode 100644 designs/PE_INT/python/pe_int/decode.py create mode 100644 designs/PE_INT/python/pe_int/lane_mac.py create mode 100644 designs/PE_INT/python/pe_int/mac_modes.py create mode 100644 designs/PE_INT/python/pe_int/pipeline.py create mode 100644 designs/PE_INT/python/pe_int/top.py create mode 100644 designs/PE_INT/python/pe_int_pycircuit.py create mode 100644 designs/PE_INT/python/placeholder.py create mode 100644 designs/PE_INT/rtl/README.md create mode 100644 designs/PE_INT/rtl/pe_int_l3.v create mode 100644 designs/PE_INT/rtl/pyc_primitives.v create mode 100644 designs/PE_INT/sim/README.md create mode 100644 designs/PE_INT/sim/run_all_wsl.sh create mode 100644 designs/PE_INT/sim/run_sim.sh create mode 100644 designs/PE_INT/spec_raw.txt create mode 100644 designs/PE_INT/tb/README.md create mode 100644 designs/PE_INT/tb/tb_pe_int_pycircuit.py create mode 100644 designs/PE_INT/tb_rtl/README.md create mode 100644 designs/PE_INT/tb_rtl/case/README.md create mode 100644 designs/PE_INT/tb_rtl/case/common_wave_dump.vh create mode 100644 designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v create mode 100644 designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v create mode 100644 designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v create mode 100644 designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v create mode 100644 designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v create mode 100644 designs/PE_INT/tb_rtl/tb.f diff --git a/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md new file mode 100644 index 0000000..674509c --- /dev/null +++ b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md @@ -0,0 +1,78 @@ +--- +name: pe-int-implementation +description: Project-level implementation guidance for PE_INT. Use for PE_INT coding choices, pipeline structure, latency alignment, power/area trade-offs, and debug order. +--- + +# PE_INT Implementation Guidance (Non-Formal) + +This is a project skill for implementation intent and practical trade-offs. +It does **not** override frozen rules in `docs/spec.md`. +If there is any conflict, `docs/spec.md` wins. + +## Hard Rule: RTL Source Ownership + +1. Deliverable RTL must be generated from PyCircuit source through `pycircuit.cli build` / `pycc`. +2. Do not accept model-generated RTL as deliverable output. +3. Do not hand-edit generated RTL for final delivery. +4. If spec is ambiguous, ask the user for clarification before changing behavior. + +## Fixed Debug SOP (Seed -> Model -> PyCircuit -> RTL) + +When any testcase fails, follow this order: + +1. Record failing seed, testcase, and simulator. +2. Reproduce with the same seed and regenerate vectors. +3. Run model checks first; if model fails, fix model/spec alignment first. +4. If model passes, run PyCircuit checks. +5. If PyCircuit fails, fix `python/` and rebuild RTL. +6. Only debug RTL-level issues after model and PyCircuit both pass. +7. Re-verify failing case first, then run full regression. + +Use `pass/fail` wording in reports. + +## Regression Notes + +- Sanity and random vectors are seed-dependent and reproducible. +- Runtime vector loading (`$readmemh` + `+GEN_DIR`) is preferred over compile-time baked expected data. +- Default output paths: + - logs: `sim/logs/` + - waves: `sim/waves/` + +## `vld` to `vld_out` and Pipeline Depth + +- Enforce one-to-one mapping from sampled `vld` to `vld_out`. +- Keep fixed latency `L` across all modes. +- Keep internal pipeline stage count identical across all modes. +- Use full pipeline datapath; no independent FIFOs for reordering. + +## Power and Area Priority + +After functionality and logic-depth constraints are satisfied: + +1. Reduce dynamic power as primary priority. +2. Reduce area as secondary priority. + +If area and dynamic power conflict, prioritize dynamic power. + +## PyCircuit Structure Requirements + +1. Stage boundaries must be explicit and reviewable. +2. Keep submodules split into separate files. +3. Keep each submodule core logic around 200 lines or less when possible. +4. Keep top-level focused on stage orchestration and alignment. +5. Control and datapath must advance at matching stage depth. + +## Mandatory Stage Coding Contract + +Top-level coding must be explicit: + +`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> combN -> regN -> output` + +Rules: + +1. Stage boundaries must be visible at top-level. +2. Each stage must define combinational work before register transfer. +3. Datapath and control-path must both be reviewable per stage. +4. `vld/mode/enable/select` control signals must stay aligned with payload. +5. Do not hide full pipeline register chains inside opaque helper loops. + diff --git a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md new file mode 100644 index 0000000..95c7a0f --- /dev/null +++ b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md @@ -0,0 +1,138 @@ +--- +name: pe-int-pycircuiteval-flow +description: Unified PE_INT flow using PyCircuitEval. Use when implementing PE_INT from spec, generating RTL from PyCircuit, and running model/tb/tb_rtl validation. +--- + +# PE_INT x PyCircuitEval Unified Flow + +This skill standardizes PE_INT flow across sessions and machines: + +- Single spec source: `docs/spec.md` +- Implementation language: PyCircuit frontend +- Deliverable RTL source: PyCircuit build (`pycircuit.cli build` / `pycc`) +- Verification layers: + - `model/`: golden/reference and model regressions + - `tb/`: PyCircuit test flow + - `tb_rtl/`: RTL-specific simulation flow + +## 0) When to Use + +Enable this skill when the user asks to: + +- implement PE_INT from `spec.md` +- generate RTL from PyCircuit source +- add testbench/regression coverage +- reproduce PE_INT flow on another machine + +## 1) Source-of-Truth and Forbidden Actions + +1. `docs/spec.md` is the only behavior contract. +2. Do not handwrite deliverable RTL. +3. Do not accept model-generated RTL as final deliverable. +4. If implementation conflicts with spec, fix implementation (do not silently rewrite spec). + +## 2) Fallback If Profile Is Missing + +If no existing PyCircuitEval profile is available on a fresh machine/session: + +1. Learn latest PyCircuit flow from `LinxISA/pyCircuit`. +2. Confirm understanding of: + - module/circuit structure + - `pycircuit.cli build` / `pycc` flow + - minimal device+tb compile/run pattern +3. Then start PE_INT implementation. + +## 3) Standard PE_INT Flow (Fixed Order) + +### Step A: Spec Checklist + +Extract executable checks from `docs/spec.md`: + +- top-level ports and widths +- mode 2a/2b/2c/2d math semantics +- fixed `vld -> vld_out` mapping and latency +- cross-mode stage consistency +- mode-2a `out1` stability policy + +### Step B: Implement in PyCircuit, Then Build RTL + +1. Implement in `python/`. +2. Build through `pycircuit.cli build` / `pycc`. +3. Keep generated RTL in `rtl/`; do not manually patch final RTL. + +### Step B.1: PyCircuit Structure Rules + +1. Keep pipeline stage boundaries explicit (`*_s0/*_s1/...` style). +2. Keep submodules separated under `python/pe_int/`. +3. Keep submodule core logic around 200 lines or less when practical. +4. Keep top-level focused on stage connection/alignment. +5. Keep control-path and datapath depth-aligned. + +### Step B.2: Mandatory Stage Contract + +Top-level must be reviewable as: + +`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> output` + +No hidden full register-chain helper loops. + +### Step C: Build Verification Assets + +- `model/`: math + timing model regression +- `tb/`: PyCircuit testbench comparison flow +- Validate: + - one-to-one valid mapping + - fixed latency and cross-mode consistency + - no bubble under full-pipeline working window + +### Step D (Optional): RTL Simulator Validation + +Only run this step after user confirms explicitly: + +1. Build RTL from PyCircuit source. +2. Run `tb_rtl/` testcases on both `iverilog` and `verilator`. +3. Report pass/fail and key outputs. + +## 4) Current Vector Baseline + +Current project baseline: + +- `tc_mode2a_sanity`: 1000 +- `tc_mode2b_sanity`: 1000 +- `tc_mode2c_sanity`: 1000 +- `tc_mode2d_sanity`: 1000 +- `tc_mode_switch_random`: 1000 + +Simulation script baseline: + +- multi-seed runs supported (default 10) +- runtime vector loading via `+GEN_DIR` +- logs: `sim/logs//...` +- waves: `sim/waves//...` + +## 5) Acceptance Checklist + +All of the following must pass: + +1. PyCircuit source can reproducibly rebuild RTL. +2. Deliverable RTL is generated by PyCircuit/pycc, not handwritten. +3. `model/` and `tb/` regressions pass. +4. README documents: + - build commands + - test commands + - fixed latency/alignment behavior + +If optional Step D is approved: + +- `tb_rtl/` testcases run successfully +- `iverilog` passes +- `verilator` passes + +## 6) Fixed Debug SOP + +On fail, always use: + +`Seed -> Model -> PyCircuit -> RTL` + +No step skipping. + diff --git a/designs/PE_INT/.gitattributes b/designs/PE_INT/.gitattributes new file mode 100644 index 0000000..d4c710c --- /dev/null +++ b/designs/PE_INT/.gitattributes @@ -0,0 +1,2 @@ +*.sh text eol=lf +*.bash text eol=lf diff --git a/designs/PE_INT/.gitignore b/designs/PE_INT/.gitignore new file mode 100644 index 0000000..9ead86f --- /dev/null +++ b/designs/PE_INT/.gitignore @@ -0,0 +1,27 @@ +# Tool-generated outputs +build/ +obj_dir/ +sim/logs/ +sim/waves/ + +# Simulation artifacts +*.vcd +*.fst +*.vpd +*.wdb +*.log +*.out + +# Python cache / env +__pycache__/ +*.pyc +.venv/ +venv/ + +# Generated testcase vectors (runtime-loaded) +tb_rtl/case/generated/*.mem +tb_rtl/case/generated/*_sizes.vh + +# OS/editor noise +.DS_Store +Thumbs.db diff --git a/designs/PE_INT/README.md b/designs/PE_INT/README.md new file mode 100644 index 0000000..aab4b5c --- /dev/null +++ b/designs/PE_INT/README.md @@ -0,0 +1,70 @@ +# PE_INT + +Fixed-point / integer vector MAC unit. + +Implementation flow: + +`docs/spec.md` -> `python/pe_int_pycircuit.py` -> `pycircuit.cli build` -> `rtl/` + `tb/` + +## Baseline + +- Spec source: `docs/spec.md` +- Current baseline: `v2.0.5` (see the header in `docs/spec.md`) + +## Directory Overview + +- `docs/`: formal specifications +- `python/`: PyCircuit design sources and build scripts +- `model/`: golden models and model regressions +- `tb/`: PyCircuit testbench flow (not RTL simulator flow) +- `tb_rtl/`: dedicated RTL test environment (Verilog testbench + cases) +- `sim/`: one-command simulation entrypoints (iverilog / verilator + wave options) +- `rtl/`: generated RTL deliverables only + +## Key Files + +- `model/ref_model.py`: reference math and pack/unpack model for all four modes +- `model/pe_int_pycircuit_eval.py`: cycle-accurate pipeline golden model (`L=3`) +- `model/test_pe_int.py`: model-level random regressions +- `model/gen_rtl_case_vectors.py`: regenerates expected vectors for `tb_rtl/case` +- `python/pe_int_pycircuit.py`: PyCircuit frontend top entry (RTL source of truth) +- `python/build.py`: unified build entry (`python -m pycircuit.cli build`) +- `tb/tb_pe_int_pycircuit.py`: native PyCircuit testbench for `pycc`/sim flow +- `tb_rtl/case/*.v`: RTL testcases (single-mode sanity + mode-switch random) +- `sim/run_all_wsl.sh`: one-command RTL regression (`iverilog` + `verilator`) +- `sim/run_sim.sh`: interactive one-command simulation (seed + simulator + wave) +- `filelist/pe_int.f`: RTL filelist (prefixed with absolute `$PE_INT`) +- `tb_rtl/tb.f`: testbench/case filelist (prefixed with absolute `$PE_INT`) +- `model/model.f`: model filelist (prefixed with absolute `$PE_INT`) + +## Quick Start + +1) Run golden model tests: + +```bash +python model/test_pe_int.py +``` + +2) Build RTL/simulation artifacts (requires a ready PyCircuit environment): + +```bash +python python/build.py --target both --out-dir build/pe_int +``` + +3) Run dedicated RTL regressions (WSL): + +```bash +bash sim/run_all_wsl.sh +``` + +Or use interactive one-command simulation (WSL): + +```bash +bash sim/run_sim.sh +``` + +## Process Constraints + +- Do not handwrite `rtl/*.v`. +- `vld_out` must align with `out0`/`out1`; under mode `2a`, `out1` uses hold policy to avoid unnecessary toggles. +- On a new machine without existing profiles, bootstrap the environment from `LinxISA/pyCircuit` first. diff --git a/designs/PE_INT/docs/design_spec.md b/designs/PE_INT/docs/design_spec.md new file mode 100644 index 0000000..f5aa91d --- /dev/null +++ b/designs/PE_INT/docs/design_spec.md @@ -0,0 +1,270 @@ +# PE_INT Design Spec (DS) + +Version: v0.1 +Source of truth for function: `docs/spec.md` (baseline v2.0.5) +This DS defines low-level circuit structure and stage-level implementation constraints. + +--- + +## 1. Scope and Design Policy + +- Functional behavior, interface, and mode semantics are inherited from `docs/spec.md`. +- This DS focuses on low-level RTL micro-architecture: + - bit-slice decode + - multiplier structure + - compressor/reduction structure + - adder topology + - explicit `combk -> regk` pipeline contract +- Depth budgeting follows `logic-depth-rules`: + - input pin -> first register: <= 8 effective logic layers + - each pipeline comb stage target: around 25 layers + +--- + +## 2. Data Types and Bit-Slice Mapping + +### 2.1 Unified lane container + +- Physical carrier is 5-bit lane: `lane[i] = x[5*i+4 : 5*i]`. +- Decode rules: + - `S8` (for 2a/2b/2d A-side and 2a B-side): combine two lanes' `[4:1]`. + - `S4` (2b B-side): take lane `[4:1]`. + - `S5` (2c, 2d B-side): take lane `[4:0]`. + +### 2.2 Signed extension rule + +- All decode outputs are sign-extended to internal arithmetic width (>= 32b in frontend model). +- Internal adder tree widths are tracked as mathematical no-loss widths (not fixed by tool inference). + +--- + +## 3. Low-Level Compute Unit Structure + +## 3.1 Multiplier unit (shared policy) + +All signed multipliers use the same structural template: + +1. Modified Booth recode (radix-4 equivalent grouping) +2. Partial-product selection/mux network +3. Compressor tree (4:2 / 3:2 based reduction) +4. Final carry-propagate adder (Brent-Kung prefix) + +Applied widths: + +- `M8x8` for mode 2a +- `M8x4` for mode 2b +- `M8x5` for mode 2d +- `M5x5` for mode 2c + +No mode is allowed to use a hidden "black-box * with unknown topology" in DS intent. + +### 3.2 Dot-product reduction unit + +- Dot8 reducer for 8-lane sum: + - CSA tree (3 levels, 3:2-equivalent cells) + - Final Brent-Kung CPA +- Dot16 (2c) is split into two Dot8 branches (`lo[0..7]`, `hi[8..15]`) then post-scaled and merged. + +### 3.3 Post-scale / mode select unit + +- 2c scale factor: + - `shift = e1_a[k] + e1_bx[k]` (k=0/1, shift in {0,1,2}) + - implemented by 2-level muxed shift (`x1/x2/x4`), not variable barrel shifter. +- Mode select: + - one-hot style select network over precomputed mode candidates + - avoid deep priority chain muxing. + +### 3.4 out1 hold unit (2a toggle suppression) + +- `out1` update condition: `vld_out=1 && mode!=2a`. +- Else hold last registered `out1_hold`. +- Implemented as explicit state register plus 2:1 mux gating. + +--- + +## 4. Manual Depth Probe Data (Pre-DS Calibration) + +Depth probes are generated by: + +- `model/depth_probe_units.py` +- `model/estimate_logic_depth.py` + +Measured structural estimates (effective logic layers): + +- `booth_mul_8x8`: 19 +- `booth_mul_8x5`: 19 +- `booth_mul_8x4`: 19 +- `booth_mul_5x5`: 19 +- `dot8_reduce_16b`: 17 +- `dot8_reduce_12b`: 15 +- `dot8_reduce_10b`: 15 +- `dot16_split8_post_scale_14b`: 11 + +Suggested comb-stage budgets from probe: + +- `comb_mul_gen`: 19 +- `comb_reduce_dot`: 17 +- `comb_post_scale_mux`: 14 + +All are below the stage target (~25), leaving margin for control glue. + +--- + +## 5. Pipeline Micro-Architecture (Explicit Stage Contract) + +Top-level must be auditable as: + +`input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3 -> output` + +Fixed latency policy in this DS: + +- `L = 3` cycles from sampled `vld` to `vld_out` (mode-invariant) + +### Stage definition + +### 5.1 `comb0` (input-side prelogic, <=8 layers) + +- Mode decode pre-gating +- Lane extraction wiring prep +- Optional valid-enable fanout buffering +- Constraint: input pin -> `reg0` <= 8 layers + +### 5.2 `reg0` (input capture) + +- Capture: `vld, mode, a, b, b1, e1_a, e1_b0, e1_b1` + +### 5.3 `comb1` (multiplier generation stage) + +Datapath: + +- Per-lane decode (`S8/S4/S5`) +- Per-lane multiply (`M8x8`, `M8x4`, `M8x5`, `M5x5`) +- For dual-output modes, build branch-0/branch-1 product vectors in parallel + +Control-path: + +- Mode one-hot generation for downstream selection +- `out1_en` candidate generation (`mode != 2a`) + +Expected depth budget: ~19 + small control glue + +### 5.4 `reg1` + +- Register multiplier outputs and control one-hot / valid. + +### 5.5 `comb2` (dot reduction stage) + +Datapath: + +- Dot8 reduction for 2a/2b/2d branches +- Dot16 split8 partial reduction for 2c (`lo`, `hi` branch pre-sums) + +Control-path: + +- Propagate valid/mode control in parallel logic cone + +Expected depth budget: ~15 to ~17 + +### 5.6 `reg2` + +- Register reduced sums and control alignment signals. + +### 5.7 `comb3` (post-scale + mode merge + out policy prep) + +Datapath: + +- 2c post-scale (`x1/x2/x4`) and merge of `lo/hi` +- Final mode result selection for `out0_raw`, `out1_raw` + +Control-path: + +- `vld_out` candidate +- `out1_en` alignment +- `out1_hold` mux next-value generation + +Expected depth budget: ~14 + control mux glue + +### 5.8 `reg3` (output register boundary) + +- Register outputs at top boundary: + - `vld_out` + - `out0` + - `out1` (through hold policy) + +This satisfies spec requirement: output ports are register-driven. + +--- + +## 6. Mode-Specific Datapath Mapping (Low-Level) + +### 6.1 Mode 2a (`mode=00`) + +- 8 lanes: + - decode `A_i: S8`, `B_i: S8` + - multiply `P_i = A_i * B_i` +- reduce: `SUM0 = Σ_i P_i` via Dot8 reducer +- output: + - `out0 = SUM0[18:0]` + - `out1` uses hold path (no unnecessary toggle) + +### 6.2 Mode 2b (`mode=01`) + +- lane decode: + - `A_i: S8` + - `B0_i: S4` from `b[39:0]` + - `B1_i: S4` from `b[79:40]` +- products: + - `P0_i = A_i * B0_i` + - `P1_i = A_i * B1_i` +- reduce: + - `SUM0 = Σ_i P0_i` + - `SUM1 = Σ_i P1_i` +- output: + - `out0 = SUM0` (sign-extended/sliced to 19b port contract) + - `out1 = SUM1` (16b port contract) + +### 6.3 Mode 2d (`mode=11`) + +- same dual-branch flow as 2b, but B decode is `S5`. + +### 6.4 Mode 2c (`mode=10`) + +- 16 lanes: + - `A_i, B0_i, B1_i` all `S5` +- branch 0: + - `LO0 = Σ_{i=0..7}(A_i*B0_i)` + - `HI0 = Σ_{i=8..15}(A_i*B0_i)` + - `SUM0 = (LO0 << (e1_a[0]+e1_b0[0])) + (HI0 << (e1_a[1]+e1_b0[1]))` +- branch 1 similarly with `B1/e1_b1`. + +--- + +## 7. Control Path Contract + +- `vld` is sampled only at stage input boundary. +- One input valid corresponds to one output valid. +- No FIFO / no reorder buffer in datapath. +- Control registers are stage-aligned with datapath registers at every stage. +- Mode switching is allowed back-to-back; per-transaction mode must be preserved through all stages. + +--- + +## 8. Verification Hooks for This DS + +Mandatory checks: + +1. Stage-audit check: reviewer can identify `comb0/reg0 ... comb3/reg3`. +2. Depth-account check: + - `comb0 <= 8` + - `comb1/2/3` around 25 target and below estimated budget. +3. Mode-invariant latency check: fixed `L=3`. +4. 2a `out1` stability check under sustained valid traffic. +5. No-bubble check for continuous valid stream after pipeline fill. + +--- + +## 9. Notes + +- This DS is intentionally low-level and structure-first. +- If any future update changes a unit topology (e.g., adder family or multiplier tree), + re-run `model/estimate_logic_depth.py` and update section 4 + stage budgets before code update. diff --git a/designs/PE_INT/docs/spec.md b/designs/PE_INT/docs/spec.md new file mode 100644 index 0000000..01f69ba --- /dev/null +++ b/designs/PE_INT/docs/spec.md @@ -0,0 +1,184 @@ +# PE_INT Specification (SPEC) + +This document defines the functional and timing contract for the PE_INT fixed-point / integer vector MAC unit. + +**Spec baseline: v2.0.5 (frozen baseline).** + +--- + +## 1. End-to-End Data Semantics + +### 1.1 Mode 2a (`mode=2'b00`): `A:S8 x B:S8` + +- `A` and `B` are both `8 x S8` (two's complement). +- Output math: + - `out0 = sum_{i=0..7}(A_s8[i] * B_s8[i])` + - `out1` is don't-care semantically in this mode (see stability rule in Section 5.1c). + +### 1.2 Mode 2b (`mode=2'b01`): `A:S8 x B:S4` (dual path) + +- `A` is `8 x S8`. +- `B0` and `B1` are each `8 x S4`. +- Output math: + - `out0 = sum_{i=0..7}(A_s8[i] * B0_s4[i])` + - `out1 = sum_{i=0..7}(A_s8[i] * B1_s4[i])` + +### 1.3 Mode 2c (`mode=2'b10`): `A:S5 x B:S5` with E1 scaling (dual path) + +- `A`, `B0`, `B1` are each `16 x S5`. +- Each 16-lane vector is split into two 8-lane groups with E1 bits: + - group 0: lanes `[0..7]` + - group 1: lanes `[8..15]` +- `e1_a[1:0]`, `e1_b0[1:0]`, `e1_b1[1:0]`, with each bit in `{0,1}`. +- Output math: + - `out0 = sum_lo(A,B0) * 2^(e1_a[0]+e1_b0[0]) + sum_hi(A,B0) * 2^(e1_a[1]+e1_b0[1])` + - `out1 = sum_lo(A,B1) * 2^(e1_a[0]+e1_b1[0]) + sum_hi(A,B1) * 2^(e1_a[1]+e1_b1[1])` + - where `sum_lo(X,Y)=sum_{i=0..7}(X_s5[i]*Y_s5[i])`, `sum_hi(X,Y)=sum_{i=8..15}(X_s5[i]*Y_s5[i])` + +### 1.4 Mode 2d (`mode=2'b11`): `A:S8 x B:S5` (dual path) + +- `A` is `8 x S8`. +- `B0` and `B1` are each `8 x S5`. +- Output math: + - `out0 = sum_{i=0..7}(A_s8[i] * B0_s5[i])` + - `out1 = sum_{i=0..7}(A_s8[i] * B1_s5[i])` + +--- + +## 2. Mode Summary + +| mode | Name | Datapath | +|------|------|----------| +| `2'b00` | 2a | `S8 x S8`, single effective output | +| `2'b01` | 2b | `S8 x S4`, dual output | +| `2'b10` | 2c | `S5 x S5 + E1`, dual output | +| `2'b11` | 2d | `S8 x S5`, dual output | + +--- + +## 3. Output Width (Lossless Math) + +- Mode 2a: `out0` requires 19-bit signed. +- Mode 2b: `out0/out1` each require 15-bit signed. +- Mode 2c: `out0/out1` each require 16-bit signed. +- Mode 2d: `out0/out1` each require 16-bit signed. + +Unified top-level output widths across modes: + +- `out0[18:0]` (19-bit signed) +- `out1[15:0]` (16-bit signed) +- `vld_out` (1-bit) + +Narrower mode results must be sign-extended to unified top-level width. + +--- + +## 4. Top-Level Ports + +| Port | Dir | Width | Description | +|------|-----|-------|-------------| +| `clk` | in | 1 | Single clock domain | +| `rst_n` | in | 1 | Active-low reset (async assert, sync release) | +| `vld` | in | 1 | Input valid, no `ready` backpressure | +| `mode` | in | 2 | Mode selector | +| `a` | in | 80 | Shared A input bus | +| `b` | in | 80 | Shared B/B0 packed bus | +| `b1` | in | 80 | B1 bus (used by mode 2c) | +| `e1_a` | in | 2 | E1 for A groups (mode 2c) | +| `e1_b0` | in | 2 | E1 for B0 groups (mode 2c) | +| `e1_b1` | in | 2 | E1 for B1 groups (mode 2c) | +| `out0` | out | 19 | Unified signed output 0 | +| `out1` | out | 16 | Unified signed output 1 | +| `vld_out` | out | 1 | Output valid aligned with output registers | + +--- + +## 5. Pipeline and Implementation Constraints + +### 5.0 Clock and Reset + +- Single clock domain only. +- `rst_n` uses asynchronous assertion and synchronous release. + +### 5.1 Fully-Pipelined Datapath + +- Must be implemented as a full pipeline datapath. +- Independent FIFO/queue used to bypass fixed pipeline semantics is forbidden. +- End-to-end pipeline latency is fixed and mode-invariant. +- Internal pipeline stage count is mode-invariant. + +### 5.1a Registered Top Outputs (Mandatory) + +- `out0`, `out1`, and `vld_out` must be driven by registers. +- `vld_out` and outputs must update at the same output register boundary. + +### 5.1b Input-Pin to First Register Logic Depth + +- Input-side prelogic before first pipeline register is allowed. +- Effective logic depth from input pins to first register must be `<= 8` layers. + +### 5.1c `vld_out` and Mode-2a `out1` Stability + +- `vld_out=1` marks valid output data in current output cycle. +- In mode 2a, `out1` is mathematically don't-care, but must avoid unnecessary toggles. +- Acceptable strategy: hold previous value or drive documented stable constant. + +### 5.2 Input Valid Handshake + +- No `ready` signal. +- A new transaction is sampled only when `vld=1`. + +### 5.3 Back-to-Back Mode Switching + +- Back-to-back `vld=1` with mode changes is allowed. +- Transaction ordering must remain FIFO at output. +- No mode/data cross-contamination between in-flight transactions. + +### 5.4 Stage Logic Depth Target + +- Main target for each pipeline stage is around 25 effective logic layers. +- Exact counting rules follow project logic-depth policy (`logic-depth-rules`). + +--- + +## 6. Packing Rules + +### 6.1 Lane Definition + +- Lane granularity is `lane[k] = x[5*k+4 : 5*k]`. +- `k = 0..15` across 80-bit buses. + +### 6.2 Modes 2a / 2b / 2d (`A` as S8 lanes) + +- `A` S8 values are packed by 4-bit halves into lane `[4:1]` fields. +- For mode 2b, `b[39:0]` carries B0 `8 x S4`, `b[79:40]` carries B1 `8 x S4`. +- For mode 2d, `b[39:0]` carries B0 `8 x S5`, `b[79:40]` carries B1 `8 x S5`. + +### 6.3 Mode 2c (`A/B0/B1` as `16 x S5`) + +- `x[5*i+4 : 5*i]` maps to element `i` for each of `a`, `b`, and `b1`. +- E1 group mapping: + - bit `[0]` applies to lanes `[0..7]` + - bit `[1]` applies to lanes `[8..15]` + +--- + +## 7. Validity and Latency Contract + +- One sampled `vld=1` transaction maps to one `vld_out=1` transaction. +- `vld -> vld_out` latency is fixed as `L` cycles. +- `L` must be identical for modes 2a/2b/2c/2d. +- Under sustained valid traffic after pipeline fill, no output bubbles are allowed. + +--- + +## 8. Revision Notes + +| Version | Date | Notes | +|---------|------|-------| +| `2.0.5` | 2026-04-17 | Added `vld_out` bundle requirement and mode-2a `out1` stability rule. | +| `2.0.4` | 2026-04-17 | Added `vld` contract and reset/clock-domain clarification. | +| `2.0.3` | 2026-04-17 | Enforced registered outputs and input-to-first-register depth cap. | +| `2.0.2` | 2026-04-17 | Added full-pipeline and per-stage depth target requirements. | +| `2.0.1` | 2026-04-17 | Unified top-level outputs to `out0[18:0]`, `out1[15:0]`. | +| `2.0.0` | 2026-04-17 | Frozen baseline refresh. | diff --git a/designs/PE_INT/filelist/pe_int.f b/designs/PE_INT/filelist/pe_int.f new file mode 100644 index 0000000..a5284fa --- /dev/null +++ b/designs/PE_INT/filelist/pe_int.f @@ -0,0 +1,2 @@ +$PE_INT/rtl/pyc_primitives.v +$PE_INT/rtl/pe_int_l3.v diff --git a/designs/PE_INT/memory.md b/designs/PE_INT/memory.md new file mode 100644 index 0000000..42ed60c --- /dev/null +++ b/designs/PE_INT/memory.md @@ -0,0 +1,3 @@ +# Memory + +- Test result wording preference: use only `pass/fail` (avoid phrases like "all green"). diff --git a/designs/PE_INT/model/README.md b/designs/PE_INT/model/README.md new file mode 100644 index 0000000..9964853 --- /dev/null +++ b/designs/PE_INT/model/README.md @@ -0,0 +1,22 @@ +# model (Models and Model Tests) + +This directory centralizes all model assets used for verification and comparison. + +## Contents + +- `ref_model.py`: reference math and pack/unpack model for all four modes +- `pe_int_pycircuit_eval.py`: cycle-accurate pipeline model (`L=3`) +- `test_pe_int.py`: model-layer regression tests (without direct RTL simulator invocation) +- `gen_rtl_case_vectors.py`: generates testcase vectors and expected values for `tb_rtl/case` +- `model.f`: model filelist (prefixed with absolute `$PE_INT`) + +## Principles + +- Any verification needing golden/model comparison must use this directory as source of truth. +- If `tb/` or `tb_rtl/` uses expected values, they must be traceable back to `model/`. + +## Run + +```bash +python model/test_pe_int.py +``` diff --git a/designs/PE_INT/model/depth_probe_units.py b/designs/PE_INT/model/depth_probe_units.py new file mode 100644 index 0000000..da21c7c --- /dev/null +++ b/designs/PE_INT/model/depth_probe_units.py @@ -0,0 +1,82 @@ +from __future__ import annotations + +from dataclasses import dataclass +from math import ceil, log2 + + +@dataclass(frozen=True) +class DepthBreakdown: + name: str + logic_layers: int + notes: str + + +def _clog2(v: int) -> int: + if v <= 1: + return 0 + return int(ceil(log2(v))) + + +def mux2_depth() -> int: + return 1 + + +def compressor_3to2_depth() -> int: + # Full-adder equivalent: sum/carry in two-level logic factoring. + return 2 + + +def compressor_4to2_depth() -> int: + # Commonly mapped as two cascaded 3:2-equivalent cells. + return 3 + + +def brent_kung_adder_depth(width: int) -> int: + # Prefix depth (rough): ~2*log2(n)-1 stages, each stage ~1 eq layer, + # plus propagate/generate and final XOR overhead. + lg = _clog2(width) + return max(3, (2 * lg - 1) + 2) + + +def booth_mul_depth(a_bits: int, b_bits: int) -> DepthBreakdown: + groups = ceil(max(a_bits, b_bits) / 2) + recode = 2 # booth recoder + sign handling + pp_select = 2 # partial-product select/mux + compress_tree = max(3, _clog2(groups) * compressor_4to2_depth()) + final_add = brent_kung_adder_depth(a_bits + b_bits) + total = recode + pp_select + compress_tree + final_add + return DepthBreakdown( + name=f"booth_mul_{a_bits}x{b_bits}", + logic_layers=total, + notes=( + f"groups={groups}, recode={recode}, pp_select={pp_select}, " + f"compress={compress_tree}, final_add={final_add}" + ), + ) + + +def dot8_reduce_depth(prod_bits: int) -> DepthBreakdown: + # Eight products reduced by CSA tree + final CPA. + csa_levels = 3 + csa_depth = csa_levels * compressor_3to2_depth() + # Accum width grows by up to +3 bits for 8-term sum. + final_add = brent_kung_adder_depth(prod_bits + 3) + total = csa_depth + final_add + return DepthBreakdown( + name=f"dot8_reduce_{prod_bits}b", + logic_layers=total, + notes=f"csa_levels={csa_levels}, csa_depth={csa_depth}, final_add={final_add}", + ) + + +def dot16_split8_post_scale_depth(sum_bits: int) -> DepthBreakdown: + # Two dot8 sums already available. This block does: + # scale-by-(0/1/2) on lo + scale-by-(0/1/2) on hi + final add. + shifter_mux = 2 * mux2_depth() # two-level shift select for x1/x2/x4 + final_add = brent_kung_adder_depth(sum_bits + 1) + total = shifter_mux + final_add + return DepthBreakdown( + name=f"dot16_split8_post_scale_{sum_bits}b", + logic_layers=total, + notes=f"shift_mux={shifter_mux}, final_add={final_add}", + ) diff --git a/designs/PE_INT/model/estimate_logic_depth.py b/designs/PE_INT/model/estimate_logic_depth.py new file mode 100644 index 0000000..e5ae8d9 --- /dev/null +++ b/designs/PE_INT/model/estimate_logic_depth.py @@ -0,0 +1,52 @@ +from __future__ import annotations + +from depth_probe_units import ( + booth_mul_depth, + dot16_split8_post_scale_depth, + dot8_reduce_depth, +) + + +def main() -> None: + units = [ + booth_mul_depth(8, 8), + booth_mul_depth(8, 5), + booth_mul_depth(8, 4), + booth_mul_depth(5, 5), + dot8_reduce_depth(16), # for S8xS8/S8xS5 + dot8_reduce_depth(12), # for S8xS4 + dot8_reduce_depth(10), # for S5xS5 lanes + dot16_split8_post_scale_depth(14), + ] + + print("=== PE_INT logic-depth probe (manual structural estimate) ===") + for u in units: + print(f"{u.name:32s} : {u.logic_layers:2d} | {u.notes}") + + # Recommended stage partition under ~25 layers target: + # Stage A: multiplier lanes only + # Stage B: lane reduce (CSA + final add) + # Stage C: post-scale / mode-select / output glue + stage_a = max( + booth_mul_depth(8, 8).logic_layers, + booth_mul_depth(8, 5).logic_layers, + booth_mul_depth(8, 4).logic_layers, + booth_mul_depth(5, 5).logic_layers, + ) + stage_b = max( + dot8_reduce_depth(16).logic_layers, + dot8_reduce_depth(12).logic_layers, + dot8_reduce_depth(10).logic_layers, + ) + # mode select + out1 hold mux + scaling tail + mode_select_and_hold = 3 + stage_c = dot16_split8_post_scale_depth(14).logic_layers + mode_select_and_hold + + print("\n=== Suggested comb-stage budget ===") + print(f"comb_mul_gen : {stage_a:2d}") + print(f"comb_reduce_dot : {stage_b:2d}") + print(f"comb_post_scale_mux : {stage_c:2d}") + + +if __name__ == "__main__": + main() diff --git a/designs/PE_INT/model/gen_rtl_case_vectors.py b/designs/PE_INT/model/gen_rtl_case_vectors.py new file mode 100644 index 0000000..6e3e2b4 --- /dev/null +++ b/designs/PE_INT/model/gen_rtl_case_vectors.py @@ -0,0 +1,264 @@ +from __future__ import annotations + +import argparse +import random +from pathlib import Path + +from pe_int_pycircuit_eval import PEIntL3Model +from ref_model import ( + MODE_2A, + MODE_2B, + MODE_2C, + MODE_2D, + compute_transaction, + pack_s4x8_to_40, + pack_s5x8_to_40, + pack_s5x16_to_80, + pack_s8x8_to_laneword, +) + +VEC_PER_CASE = 1000 + + +def _hex(width: int, value: int) -> str: + digits = (width + 3) // 4 + return f"{width}'h{(value & ((1 << width) - 1)):0{digits}x}" + + +def _sdec(width: int, value: int) -> str: + if value < 0: + return f"-{width}'sd{-value}" + return f"{width}'sd{value}" + + +def _rand_s(width: int) -> int: + lo = -(1 << (width - 1)) + hi = (1 << (width - 1)) - 1 + return random.randint(lo, hi) + + +def _rand_s_rng(rng: random.Random, width: int) -> int: + lo = -(1 << (width - 1)) + hi = (1 << (width - 1)) - 1 + return rng.randint(lo, hi) + + +def _make_txn(mode: int): + if mode == MODE_2A: + a = [_rand_s(8) for _ in range(8)] + b = [_rand_s(8) for _ in range(8)] + return ( + pack_s8x8_to_laneword(a), + pack_s8x8_to_laneword(b), + 0, + (0, 0), + (0, 0), + (0, 0), + ) + if mode == MODE_2B: + a = [_rand_s(8) for _ in range(8)] + b0 = [_rand_s(4) for _ in range(8)] + b1 = [_rand_s(4) for _ in range(8)] + b = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) + return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) + if mode == MODE_2D: + a = [_rand_s(8) for _ in range(8)] + b0 = [_rand_s(5) for _ in range(8)] + b1 = [_rand_s(5) for _ in range(8)] + b = pack_s5x8_to_40(b0) | (pack_s5x8_to_40(b1) << 40) + return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) + a = [_rand_s(5) for _ in range(16)] + b0 = [_rand_s(5) for _ in range(16)] + b1 = [_rand_s(5) for _ in range(16)] + e1a = (random.randint(0, 1), random.randint(0, 1)) + e1b0 = (random.randint(0, 1), random.randint(0, 1)) + e1b1 = (random.randint(0, 1), random.randint(0, 1)) + return ( + pack_s5x16_to_80(a), + pack_s5x16_to_80(b0), + pack_s5x16_to_80(b1), + e1a, + e1b0, + e1b1, + ) + + +def _write(path: Path, content: str) -> None: + path.parent.mkdir(parents=True, exist_ok=True) + path.write_text(content, encoding="utf-8") + print(f"generated: {path}") + + +def _hex_word(width: int, value: int) -> str: + digits = (width + 3) // 4 + return f"{(value & ((1 << width) - 1)):0{digits}x}" + + +def _write_mem(path: Path, width: int, values: list[int]) -> None: + path.parent.mkdir(parents=True, exist_ok=True) + path.write_text("\n".join(_hex_word(width, v) for v in values) + "\n", encoding="utf-8") + print(f"generated: {path}") + + +def gen_sanity_case_headers(gen_dir: Path, seed: int) -> None: + # Sanity vectors are deterministic for the same seed. + rng = random.Random(seed) + + # 2b: 1000 vectors + tx_2b = [] + for _ in range(VEC_PER_CASE): + a = [_rand_s_rng(rng, 8) for _ in range(8)] + b0 = [_rand_s_rng(rng, 4) for _ in range(8)] + b1 = [_rand_s_rng(rng, 4) for _ in range(8)] + a_w = pack_s8x8_to_laneword(a) + b_w = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) + r = compute_transaction(MODE_2B, a_w, b_w, 0, (0, 0), (0, 0), (0, 0)) + tx_2b.append((a_w, b_w, r.out0_19, r.out1_16)) + _write_mem(gen_dir / "tc_mode2b_sanity_tx_a.mem", 80, [x[0] for x in tx_2b]) + _write_mem(gen_dir / "tc_mode2b_sanity_tx_b.mem", 80, [x[1] for x in tx_2b]) + _write_mem(gen_dir / "tc_mode2b_sanity_exp_o0.mem", 19, [x[2] for x in tx_2b]) + _write_mem(gen_dir / "tc_mode2b_sanity_exp_o1.mem", 16, [x[3] for x in tx_2b]) + + # 2a: each case is preload-2b + mode2a + cases_2a = [] + for _ in range(VEC_PER_CASE): + a_pre = [_rand_s_rng(rng, 8) for _ in range(8)] + b0_pre = [_rand_s_rng(rng, 4) for _ in range(8)] + b1_pre = [_rand_s_rng(rng, 4) for _ in range(8)] + a_pre_w = pack_s8x8_to_laneword(a_pre) + b_pre_w = pack_s4x8_to_40(b0_pre) | (pack_s4x8_to_40(b1_pre) << 40) + r_pre = compute_transaction(MODE_2B, a_pre_w, b_pre_w, 0, (0, 0), (0, 0), (0, 0)) + + a2 = [_rand_s_rng(rng, 8) for _ in range(8)] + b2 = [_rand_s_rng(rng, 8) for _ in range(8)] + a2_w = pack_s8x8_to_laneword(a2) + b2_w = pack_s8x8_to_laneword(b2) + r2 = compute_transaction(MODE_2A, a2_w, b2_w, 0, (0, 0), (0, 0), (0, 0)) + cases_2a.append((a_pre_w, b_pre_w, a2_w, b2_w, r_pre.out1_16, r2.out0_19)) + _write_mem(gen_dir / "tc_mode2a_sanity_pre_a.mem", 80, [x[0] for x in cases_2a]) + _write_mem(gen_dir / "tc_mode2a_sanity_pre_b.mem", 80, [x[1] for x in cases_2a]) + _write_mem(gen_dir / "tc_mode2a_sanity_a2a.mem", 80, [x[2] for x in cases_2a]) + _write_mem(gen_dir / "tc_mode2a_sanity_b2a.mem", 80, [x[3] for x in cases_2a]) + _write_mem(gen_dir / "tc_mode2a_sanity_exp_pre_o1.mem", 16, [x[4] for x in cases_2a]) + _write_mem(gen_dir / "tc_mode2a_sanity_exp_2a_o0.mem", 19, [x[5] for x in cases_2a]) + + # 2d: 1000 vectors + tx_2d = [] + for _ in range(VEC_PER_CASE): + a = [_rand_s_rng(rng, 8) for _ in range(8)] + b0 = [_rand_s_rng(rng, 5) for _ in range(8)] + b1 = [_rand_s_rng(rng, 5) for _ in range(8)] + a_w = pack_s8x8_to_laneword(a) + b_w = pack_s5x8_to_40(b0) | (pack_s5x8_to_40(b1) << 40) + r = compute_transaction(MODE_2D, a_w, b_w, 0, (0, 0), (0, 0), (0, 0)) + tx_2d.append((a_w, b_w, r.out0_19, r.out1_16)) + _write_mem(gen_dir / "tc_mode2d_sanity_tx_a.mem", 80, [x[0] for x in tx_2d]) + _write_mem(gen_dir / "tc_mode2d_sanity_tx_b.mem", 80, [x[1] for x in tx_2d]) + _write_mem(gen_dir / "tc_mode2d_sanity_exp_o0.mem", 19, [x[2] for x in tx_2d]) + _write_mem(gen_dir / "tc_mode2d_sanity_exp_o1.mem", 16, [x[3] for x in tx_2d]) + + # 2c: 1000 vectors + tx_2c = [] + for _ in range(VEC_PER_CASE): + a = [_rand_s_rng(rng, 5) for _ in range(16)] + b0 = [_rand_s_rng(rng, 5) for _ in range(16)] + b1 = [_rand_s_rng(rng, 5) for _ in range(16)] + e1a = (rng.randint(0, 1), rng.randint(0, 1)) + e1b0 = (rng.randint(0, 1), rng.randint(0, 1)) + e1b1 = (rng.randint(0, 1), rng.randint(0, 1)) + a_w = pack_s5x16_to_80(a) + b0_w = pack_s5x16_to_80(b0) + b1_w = pack_s5x16_to_80(b1) + r = compute_transaction(MODE_2C, a_w, b0_w, b1_w, e1a, e1b0, e1b1) + tx_2c.append((a_w, b0_w, b1_w, e1a, e1b0, e1b1, r.out0_19, r.out1_16)) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_a.mem", 80, [x[0] for x in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_b0.mem", 80, [x[1] for x in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_b1.mem", 80, [x[2] for x in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_e1a.mem", 2, [x[3][0] | (x[3][1] << 1) for x in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_e1b0.mem", 2, [x[4][0] | (x[4][1] << 1) for x in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_e1b1.mem", 2, [x[5][0] | (x[5][1] << 1) for x in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_exp_o0.mem", 19, [x[6] for x in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_exp_o1.mem", 16, [x[7] for x in tx_2c]) + + +def gen_mode_switch_random(gen_dir: Path, seed: int) -> None: + random.seed(seed) + modes = [MODE_2A, MODE_2B, MODE_2C, MODE_2D] + tx = [] + for _ in range(VEC_PER_CASE): + vld = random.randint(0, 1) + mode = random.choice(modes) + a, b, b1, e1a, e1b0, e1b1 = _make_txn(mode) + tx.append((vld, mode, a, b, b1, e1a, e1b0, e1b1)) + + dut = PEIntL3Model() + for _ in range(3): + dut.step(rst_n=0, vld=0, mode=0, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) + for _ in range(3): + dut.step(rst_n=1, vld=0, mode=0, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) + + exp = [] + for item in tx: + r = dut.step( + rst_n=1, + vld=item[0], + mode=item[1], + a=item[2], + b=item[3], + b1=item[4], + e1_a=item[5], + e1_b0=item[6], + e1_b1=item[7], + ) + if r.vld_out: + exp.append((r.out0, r.out1)) + for _ in range(30): + r = dut.step(rst_n=1, vld=0, mode=0, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) + if r.vld_out: + exp.append((r.out0, r.out1)) + + _write( + gen_dir / "tc_mode_switch_random_sizes.vh", + "\n".join( + [ + "// Auto-generated by model/gen_rtl_case_vectors.py", + f"// seed: {seed}", + f"localparam integer N_TX = {len(tx)};", + f"localparam integer N_EXP = {len(exp)};", + "", + ] + ), + ) + _write_mem(gen_dir / "tc_mode_switch_random_tx_vld.mem", 1, [x[0] for x in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_mode.mem", 2, [x[1] for x in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_a.mem", 80, [x[2] for x in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_b.mem", 80, [x[3] for x in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_b1.mem", 80, [x[4] for x in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_e1a.mem", 2, [x[5][0] | (x[5][1] << 1) for x in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_e1b0.mem", 2, [x[6][0] | (x[6][1] << 1) for x in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_e1b1.mem", 2, [x[7][0] | (x[7][1] << 1) for x in tx]) + exp_o0 = [x[0] for x in exp] + [0] * (VEC_PER_CASE - len(exp)) + exp_o1 = [x[1] for x in exp] + [0] * (VEC_PER_CASE - len(exp)) + _write_mem(gen_dir / "tc_mode_switch_random_exp_o0.mem", 19, exp_o0) + _write_mem(gen_dir / "tc_mode_switch_random_exp_o1.mem", 16, exp_o1) + _write_mem(gen_dir / "tc_mode_switch_random_meta.mem", 32, [len(exp)]) + + +def main() -> None: + parser = argparse.ArgumentParser(description="Generate RTL testcase vectors from model.") + parser.add_argument( + "--seed", + type=int, + default=20260420, + help="seed for random mode-switch testcase generation", + ) + args = parser.parse_args() + + repo = Path(__file__).resolve().parents[1] + gen_dir = repo / "tb_rtl" / "case" / "generated" + gen_sanity_case_headers(gen_dir, args.seed) + gen_mode_switch_random(gen_dir, args.seed) + + +if __name__ == "__main__": + main() diff --git a/designs/PE_INT/model/model.f b/designs/PE_INT/model/model.f new file mode 100644 index 0000000..d55ba7d --- /dev/null +++ b/designs/PE_INT/model/model.f @@ -0,0 +1,4 @@ +$PE_INT/model/ref_model.py +$PE_INT/model/pe_int_pycircuit_eval.py +$PE_INT/model/test_pe_int.py +$PE_INT/model/gen_rtl_case_vectors.py diff --git a/designs/PE_INT/model/pe_int_pycircuit_eval.py b/designs/PE_INT/model/pe_int_pycircuit_eval.py new file mode 100644 index 0000000..5674958 --- /dev/null +++ b/designs/PE_INT/model/pe_int_pycircuit_eval.py @@ -0,0 +1,100 @@ +from __future__ import annotations + +from dataclasses import dataclass + +from ref_model import MODE_2A, MacResult, compute_transaction, to_signed + +DEFAULT_PIPELINE_L = 3 + + +@dataclass +class StagePayload: + vld: int = 0 + mode: int = 0 + out0_19: int = 0 + out1_16: int = 0 + + +@dataclass +class StepResult: + vld_out: int + out0: int + out1: int + + +class PEIntL3Model: + """Cycle-accurate PE_INT model for golden checking.""" + + def __init__(self) -> None: + self.s0 = StagePayload() + self.s1 = StagePayload() + self.s2 = StagePayload() + self.out0 = 0 + self.out1 = 0 + self.vld_out = 0 + # If reset has never been asserted, skip release window at power-up. + self._rst_release_count = 2 + + def reset(self) -> None: + self.s0 = StagePayload() + self.s1 = StagePayload() + self.s2 = StagePayload() + self.out0 = 0 + self.out1 = 0 + self.vld_out = 0 + self._rst_release_count = 0 + + def step( + self, + *, + rst_n: int, + vld: int, + mode: int, + a: int, + b: int, + b1: int, + e1_a: tuple[int, int], + e1_b0: tuple[int, int], + e1_b1: tuple[int, int], + ) -> StepResult: + if not rst_n: + self.reset() + return StepResult(vld_out=0, out0=0, out1=0) + + if self._rst_release_count < 2: + self._rst_release_count += 1 + self.s0 = StagePayload() + self.s1 = StagePayload() + self.s2 = StagePayload() + self.vld_out = 0 + self.out0 = 0 + self.out1 = 0 + return StepResult(vld_out=0, out0=0, out1=0) + + new_vld_out = self.s2.vld + new_out0 = self.out0 + new_out1 = self.out1 + if self.s2.vld: + new_out0 = to_signed(self.s2.out0_19, 19) + if self.s2.mode != MODE_2A: + new_out1 = to_signed(self.s2.out1_16, 16) + + if vld: + mac: MacResult = compute_transaction(mode, a, b, b1, e1_a, e1_b0, e1_b1) + next_s0 = StagePayload( + vld=1, + mode=mode & 0x3, + out0_19=to_signed(mac.out0_19, 19), + out1_16=to_signed(mac.out1_16, 16), + ) + else: + next_s0 = StagePayload(vld=0, mode=mode & 0x3, out0_19=0, out1_16=0) + + self.s2 = StagePayload(self.s1.vld, self.s1.mode, self.s1.out0_19, self.s1.out1_16) + self.s1 = StagePayload(self.s0.vld, self.s0.mode, self.s0.out0_19, self.s0.out1_16) + self.s0 = next_s0 + + self.vld_out = new_vld_out + self.out0 = to_signed(new_out0, 19) + self.out1 = to_signed(new_out1, 16) + return StepResult(vld_out=self.vld_out, out0=self.out0, out1=self.out1) diff --git a/designs/PE_INT/model/ref_model.py b/designs/PE_INT/model/ref_model.py new file mode 100644 index 0000000..6e65942 --- /dev/null +++ b/designs/PE_INT/model/ref_model.py @@ -0,0 +1,153 @@ +from __future__ import annotations + +from dataclasses import dataclass +from typing import List, Sequence, Tuple + +MODE_2A = 0 +MODE_2B = 1 +MODE_2C = 2 +MODE_2D = 3 + + +def _mask(width: int) -> int: + return (1 << width) - 1 + + +def to_signed(value: int, width: int) -> int: + value &= _mask(width) + sign = 1 << (width - 1) + return value - (1 << width) if value & sign else value + + +def get_lane5(word80: int, lane_idx: int) -> int: + return (word80 >> (5 * lane_idx)) & 0x1F + + +def decode_s8x8_from_laneword(word80: int) -> List[int]: + vals: List[int] = [] + for i in range(8): + lo = (get_lane5(word80, 2 * i) >> 1) & 0xF + hi = (get_lane5(word80, 2 * i + 1) >> 1) & 0xF + vals.append(to_signed((hi << 4) | lo, 8)) + return vals + + +def decode_s4x8_from_40(word40: int) -> List[int]: + vals: List[int] = [] + for i in range(8): + lane = (word40 >> (5 * i)) & 0x1F + vals.append(to_signed((lane >> 1) & 0xF, 4)) + return vals + + +def decode_s5x8_from_40(word40: int) -> List[int]: + return [to_signed((word40 >> (5 * i)) & 0x1F, 5) for i in range(8)] + + +def decode_s5x16_from_80(word80: int) -> List[int]: + return [to_signed((word80 >> (5 * i)) & 0x1F, 5) for i in range(16)] + + +def _e1_shift(e1_pair_a: Sequence[int], e1_pair_b: Sequence[int]) -> Tuple[int, int]: + sh_lo = int(e1_pair_a[0]) + int(e1_pair_b[0]) + sh_hi = int(e1_pair_a[1]) + int(e1_pair_b[1]) + return sh_lo, sh_hi + + +@dataclass(frozen=True) +class MacResult: + out0_19: int + out1_16: int + + +def compute_transaction( + mode: int, + a80: int, + b80: int, + b1_80: int, + e1_a: Sequence[int], + e1_b0: Sequence[int], + e1_b1: Sequence[int], +) -> MacResult: + mode &= 0x3 + a80 &= _mask(80) + b80 &= _mask(80) + b1_80 &= _mask(80) + + if mode == MODE_2A: + a = decode_s8x8_from_laneword(a80) + b = decode_s8x8_from_laneword(b80) + sum0 = sum(x * y for x, y in zip(a, b)) + return MacResult(to_signed(sum0, 19), 0) + + if mode == MODE_2B: + a = decode_s8x8_from_laneword(a80) + b0 = decode_s4x8_from_40(b80 & _mask(40)) + b1 = decode_s4x8_from_40((b80 >> 40) & _mask(40)) + sum0 = sum(x * y for x, y in zip(a, b0)) + sum1 = sum(x * y for x, y in zip(a, b1)) + return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) + + if mode == MODE_2D: + a = decode_s8x8_from_laneword(a80) + b0 = decode_s5x8_from_40(b80 & _mask(40)) + b1 = decode_s5x8_from_40((b80 >> 40) & _mask(40)) + sum0 = sum(x * y for x, y in zip(a, b0)) + sum1 = sum(x * y for x, y in zip(a, b1)) + return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) + + # MODE_2C + a = decode_s5x16_from_80(a80) + b0 = decode_s5x16_from_80(b80) + b1 = decode_s5x16_from_80(b1_80) + lo0 = sum(a[i] * b0[i] for i in range(8)) + hi0 = sum(a[i] * b0[i] for i in range(8, 16)) + lo1 = sum(a[i] * b1[i] for i in range(8)) + hi1 = sum(a[i] * b1[i] for i in range(8, 16)) + + sh0_lo, sh0_hi = _e1_shift(e1_a, e1_b0) + sh1_lo, sh1_hi = _e1_shift(e1_a, e1_b1) + sum0 = (lo0 << sh0_lo) + (hi0 << sh0_hi) + sum1 = (lo1 << sh1_lo) + (hi1 << sh1_hi) + return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) + + +def pack_s8x8_to_laneword(values: Sequence[int]) -> int: + if len(values) != 8: + raise ValueError("need 8 S8 values") + word = 0 + for i, val in enumerate(values): + raw = val & 0xFF + lane_lo = (raw & 0xF) << 1 + lane_hi = ((raw >> 4) & 0xF) << 1 + word |= lane_lo << (5 * (2 * i)) + word |= lane_hi << (5 * (2 * i + 1)) + return word + + +def pack_s4x8_to_40(values: Sequence[int]) -> int: + if len(values) != 8: + raise ValueError("need 8 S4 values") + word = 0 + for i, val in enumerate(values): + lane = ((val & 0xF) << 1) & 0x1F + word |= lane << (5 * i) + return word + + +def pack_s5x8_to_40(values: Sequence[int]) -> int: + if len(values) != 8: + raise ValueError("need 8 S5 values") + word = 0 + for i, val in enumerate(values): + word |= (val & 0x1F) << (5 * i) + return word + + +def pack_s5x16_to_80(values: Sequence[int]) -> int: + if len(values) != 16: + raise ValueError("need 16 S5 values") + word = 0 + for i, val in enumerate(values): + word |= (val & 0x1F) << (5 * i) + return word diff --git a/designs/PE_INT/model/test_pe_int.py b/designs/PE_INT/model/test_pe_int.py new file mode 100644 index 0000000..71cfdf3 --- /dev/null +++ b/designs/PE_INT/model/test_pe_int.py @@ -0,0 +1,178 @@ +from __future__ import annotations + +import random +import sys +import unittest +from pathlib import Path + +MODEL_DIR = Path(__file__).resolve().parent +sys.path.insert(0, str(MODEL_DIR)) + +from pe_int_pycircuit_eval import DEFAULT_PIPELINE_L, PEIntL3Model +from ref_model import ( + MODE_2A, + MODE_2B, + MODE_2C, + MODE_2D, + compute_transaction, + pack_s4x8_to_40, + pack_s5x8_to_40, + pack_s5x16_to_80, + pack_s8x8_to_laneword, +) + + +def _rand_s(width: int) -> int: + lo = -(1 << (width - 1)) + hi = (1 << (width - 1)) - 1 + return random.randint(lo, hi) + + +def _make_txn(mode: int) -> tuple[int, int, int, tuple[int, int], tuple[int, int], tuple[int, int]]: + if mode == MODE_2A: + a = [_rand_s(8) for _ in range(8)] + b = [_rand_s(8) for _ in range(8)] + return ( + pack_s8x8_to_laneword(a), + pack_s8x8_to_laneword(b), + 0, + (0, 0), + (0, 0), + (0, 0), + ) + if mode == MODE_2B: + a = [_rand_s(8) for _ in range(8)] + b0 = [_rand_s(4) for _ in range(8)] + b1 = [_rand_s(4) for _ in range(8)] + b = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) + return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) + if mode == MODE_2D: + a = [_rand_s(8) for _ in range(8)] + b0 = [_rand_s(5) for _ in range(8)] + b1 = [_rand_s(5) for _ in range(8)] + b = pack_s5x8_to_40(b0) | (pack_s5x8_to_40(b1) << 40) + return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) + # MODE_2C + a = [_rand_s(5) for _ in range(16)] + b0 = [_rand_s(5) for _ in range(16)] + b1 = [_rand_s(5) for _ in range(16)] + e1a = (random.randint(0, 1), random.randint(0, 1)) + e1b0 = (random.randint(0, 1), random.randint(0, 1)) + e1b1 = (random.randint(0, 1), random.randint(0, 1)) + return ( + pack_s5x16_to_80(a), + pack_s5x16_to_80(b0), + pack_s5x16_to_80(b1), + e1a, + e1b0, + e1b1, + ) + + +class TestPEIntModel(unittest.TestCase): + def setUp(self) -> None: + random.seed(11) + + def test_mode_math_direct(self) -> None: + for mode in (MODE_2A, MODE_2B, MODE_2C, MODE_2D): + for _ in range(40): + a, b, b1, e1a, e1b0, e1b1 = _make_txn(mode) + got = compute_transaction(mode, a, b, b1, e1a, e1b0, e1b1) + # smoke checks on bounded output widths + self.assertGreaterEqual(got.out0_19, -(1 << 18)) + self.assertLessEqual(got.out0_19, (1 << 18) - 1) + self.assertGreaterEqual(got.out1_16, -(1 << 15)) + self.assertLessEqual(got.out1_16, (1 << 15) - 1) + + def test_pipeline_alignment_and_mode_switch(self) -> None: + dut = PEIntL3Model() + expected: list[tuple[int, int, int, int]] = [] # cycle, mode, out0, out1 + out_hits = 0 + + for cycle in range(120): + vld = random.randint(0, 1) + mode = random.choice((MODE_2A, MODE_2B, MODE_2C, MODE_2D)) + a, b, b1, e1a, e1b0, e1b1 = _make_txn(mode) + + if vld: + exp = compute_transaction(mode, a, b, b1, e1a, e1b0, e1b1) + expected.append((cycle + DEFAULT_PIPELINE_L, mode, exp.out0_19, exp.out1_16)) + + step = dut.step( + rst_n=1, + vld=vld, + mode=mode, + a=a, + b=b, + b1=b1, + e1_a=e1a, + e1_b0=e1b0, + e1_b1=e1b1, + ) + + if step.vld_out: + self.assertTrue(expected, "vld_out should map to one expected transaction") + due_cycle, due_mode, exp0, exp1 = expected.pop(0) + self.assertEqual(cycle, due_cycle) + self.assertEqual(step.out0, exp0) + if due_mode != MODE_2A: + self.assertEqual(step.out1, exp1) + out_hits += 1 + + # Drain pipeline + for cycle in range(120, 130): + step = dut.step( + rst_n=1, + vld=0, + mode=MODE_2A, + a=0, + b=0, + b1=0, + e1_a=(0, 0), + e1_b0=(0, 0), + e1_b1=(0, 0), + ) + if step.vld_out: + due_cycle, due_mode, exp0, exp1 = expected.pop(0) + self.assertEqual(cycle, due_cycle) + self.assertEqual(step.out0, exp0) + if due_mode != MODE_2A: + self.assertEqual(step.out1, exp1) + out_hits += 1 + self.assertEqual(len(expected), 0) + self.assertGreater(out_hits, 0) + + def test_mode2a_out1_no_toggle(self) -> None: + dut = PEIntL3Model() + + # First, drive one non-2a sample to set out1 base. + a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2B) + dut.step(rst_n=1, vld=1, mode=MODE_2B, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) + for _ in range(DEFAULT_PIPELINE_L + 1): + dut.step(rst_n=1, vld=0, mode=MODE_2A, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) + base_out1 = dut.out1 + + # Then continuous mode2a valid traffic; out1 should hold. + for _ in range(30): + a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2A) + dut.step(rst_n=1, vld=1, mode=MODE_2A, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) + self.assertEqual(dut.out1, base_out1) + + def test_async_reset_clears_pipeline(self) -> None: + dut = PEIntL3Model() + # inject a valid sample + a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2D) + dut.step(rst_n=1, vld=1, mode=MODE_2D, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) + # asynchronous reset assertion + res = dut.step(rst_n=0, vld=1, mode=MODE_2D, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) + self.assertEqual(res.vld_out, 0) + self.assertEqual(res.out0, 0) + self.assertEqual(res.out1, 0) + # release reset and keep idle, no stale output should appear + for _ in range(DEFAULT_PIPELINE_L + 2): + res = dut.step(rst_n=1, vld=0, mode=MODE_2A, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) + self.assertEqual(res.vld_out, 0) + + +if __name__ == "__main__": + unittest.main() diff --git a/designs/PE_INT/python/build.py b/designs/PE_INT/python/build.py new file mode 100644 index 0000000..d0be14e --- /dev/null +++ b/designs/PE_INT/python/build.py @@ -0,0 +1,56 @@ +from __future__ import annotations + +import argparse +import os +import subprocess +import sys +from pathlib import Path + + +def main() -> int: + parser = argparse.ArgumentParser(description="Build PE_INT via pyCircuit/pycc.") + parser.add_argument("--out-dir", default="build/pe_int", help="pycircuit build output directory") + parser.add_argument("--target", default="both", choices=("rtl", "sim", "both"), help="build target") + parser.add_argument("--jobs", default="8", help="parallel jobs for pycircuit build") + args = parser.parse_args() + + repo_root = Path(__file__).resolve().parents[1] + tb_file = repo_root / "tb" / "tb_pe_int_pycircuit.py" + out_dir = repo_root / args.out_dir + out_dir.mkdir(parents=True, exist_ok=True) + + env = os.environ.copy() + py_path = env.get("PYTHONPATH", "") + if str(repo_root / "python") not in py_path: + env["PYTHONPATH"] = str(repo_root / "python") + (os.pathsep + py_path if py_path else "") + + # Default toolchain resolution: + # PE_INT is expected under /designs/PE_INT, + # so pycircuit root can be derived by walking up two levels. + pycircuit_root = repo_root.parents[1] + default_toolchain_root = pycircuit_root / ".pycircuit_out" / "toolchain" / "install" + default_pycc = default_toolchain_root / "bin" / "pycc" + if "PYC_TOOLCHAIN_ROOT" not in env and default_toolchain_root.exists(): + env["PYC_TOOLCHAIN_ROOT"] = str(default_toolchain_root) + if "PYCC" not in env and default_pycc.exists(): + env["PYCC"] = str(default_pycc) + + cmd = [ + sys.executable, + "-m", + "pycircuit.cli", + "build", + str(tb_file), + "--out-dir", + str(out_dir), + "--target", + args.target, + "--jobs", + str(args.jobs), + ] + print("Running:", " ".join(cmd)) + return subprocess.call(cmd, cwd=str(repo_root), env=env) + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/designs/PE_INT/python/pe_int/__init__.py b/designs/PE_INT/python/pe_int/__init__.py new file mode 100644 index 0000000..50d90f2 --- /dev/null +++ b/designs/PE_INT/python/pe_int/__init__.py @@ -0,0 +1,12 @@ +from .constants import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D +from .top import build, emit_mlir + +__all__ = [ + "MODE_2A", + "MODE_2B", + "MODE_2C", + "MODE_2D", + "DEFAULT_PIPELINE_L", + "build", + "emit_mlir", +] diff --git a/designs/PE_INT/python/pe_int/constants.py b/designs/PE_INT/python/pe_int/constants.py new file mode 100644 index 0000000..3183576 --- /dev/null +++ b/designs/PE_INT/python/pe_int/constants.py @@ -0,0 +1,14 @@ +from __future__ import annotations + +MODE_2A = 0 +MODE_2B = 1 +MODE_2C = 2 +MODE_2D = 3 + +DEFAULT_PIPELINE_L = 3 + +LANE_WORD_W = 80 +LANE5_W = 5 + +OUT0_W = 19 +OUT1_W = 16 diff --git a/designs/PE_INT/python/pe_int/decode.py b/designs/PE_INT/python/pe_int/decode.py new file mode 100644 index 0000000..c2ec31b --- /dev/null +++ b/designs/PE_INT/python/pe_int/decode.py @@ -0,0 +1,48 @@ +from __future__ import annotations + +from pycircuit import cat, wire_of + + +def sext(value, bits: int): + if hasattr(value, "sext"): + return value.sext(width=bits) + raw = wire_of(value) + if hasattr(raw, "sext"): + return raw.sext(width=bits) + return raw._sext(width=bits) + + +def lane5(word, idx: int): + lo = 5 * idx + return wire_of(word)[lo : lo + 5] + + +def decode_s8_from_lane_word(word, idx: int): + lo_lane = lane5(word, 2 * idx) + hi_lane = lane5(word, 2 * idx + 1) + lo4 = wire_of(lo_lane)[1:5] + hi4 = wire_of(hi_lane)[1:5] + raw8 = cat(hi4, lo4) + return sext(raw8, 32) + + +def decode_s4_from_40(word40, idx: int): + lane = wire_of(word40)[5 * idx : 5 * idx + 5] + raw4 = wire_of(lane)[1:5] + return sext(raw4, 32) + + +def decode_s4_hi_from_80(word80, idx: int): + lane = wire_of(word80)[40 + 5 * idx : 40 + 5 * idx + 5] + raw4 = wire_of(lane)[1:5] + return sext(raw4, 32) + + +def decode_s5(word, idx: int): + raw = wire_of(word)[5 * idx : 5 * idx + 5] + return sext(raw, 32) + + +def decode_s5_hi_from_80(word80, idx: int): + raw = wire_of(word80)[40 + 5 * idx : 40 + 5 * idx + 5] + return sext(raw, 32) diff --git a/designs/PE_INT/python/pe_int/lane_mac.py b/designs/PE_INT/python/pe_int/lane_mac.py new file mode 100644 index 0000000..65eae7a --- /dev/null +++ b/designs/PE_INT/python/pe_int/lane_mac.py @@ -0,0 +1,51 @@ +from __future__ import annotations + +from typing import Sequence + +from pycircuit import mux, wire_of + + +def booth_mul_signed(lhs, rhs): + """ + DS §3.1 multiplier structural policy entry. + RTL generation is expected to map this operation into the + shared booth+compressor+BK template tracked by depth-probe flow. + """ + return lhs * rhs + + +def dot8_reduce(products: Sequence[object]): + if len(products) != 8: + raise ValueError("dot8_reduce expects exactly 8 products") + acc = products[0] + for idx in range(1, 8): + acc = acc + products[idx] + return acc + + +def dot16_split8_reduce(products: Sequence[object]): + if len(products) != 16: + raise ValueError("dot16_split8_reduce expects exactly 16 products") + lo = dot8_reduce(products[0:8]) + hi = dot8_reduce(products[8:16]) + return lo, hi + + +def shift_scale_x1_x2_x4(value, shift2b): + """ + DS §3.3: use 2-level muxed shift (x1/x2/x4), avoid barrel shifter. + """ + return mux(shift2b == 0, value, mux(shift2b == 1, value * 2, value * 4)) + + +def select_one_hot4(sel0, sel1, sel2, sel3, cand0, cand1, cand2, cand3): + """ + One-hot selection network to avoid deep priority mux chain. + """ + return (cand0 * sel0) + (cand1 * sel1) + (cand2 * sel2) + (cand3 * sel3) + + +def sum_shift_pair(lo, hi, e1_a, e1_b): + sh_lo = wire_of(e1_a)[0:1] + wire_of(e1_b)[0:1] + sh_hi = wire_of(e1_a)[1:2] + wire_of(e1_b)[1:2] + return shift_scale_x1_x2_x4(lo, sh_lo) + shift_scale_x1_x2_x4(hi, sh_hi) diff --git a/designs/PE_INT/python/pe_int/mac_modes.py b/designs/PE_INT/python/pe_int/mac_modes.py new file mode 100644 index 0000000..3d37850 --- /dev/null +++ b/designs/PE_INT/python/pe_int/mac_modes.py @@ -0,0 +1,128 @@ +from __future__ import annotations + +from pycircuit import wire_of + +from .decode import decode_s4_from_40, decode_s4_hi_from_80, decode_s5, decode_s5_hi_from_80, decode_s8_from_lane_word +from .lane_mac import booth_mul_signed, dot8_reduce, dot16_split8_reduce, select_one_hot4, sum_shift_pair + + +def _mode_one_hot(mode): + is_2a = mode == 0 + is_2b = mode == 1 + is_2c = mode == 2 + is_2d = mode == 3 + return is_2a, is_2b, is_2c, is_2d + + +def comb1_generate_products(a, b, b1): + """ + DS §5.3: + - per-lane decode (S8/S4/S5) + - per-lane multiplier generation (M8x8/M8x4/M8x5/M5x5) + """ + b_lo40 = wire_of(b)[0:40] + + p2a = [] + p2b0 = [] + p2b1 = [] + p2d0 = [] + p2d1 = [] + p2c0 = [] + p2c1 = [] + + for lane_idx in range(8): + a8_i = decode_s8_from_lane_word(a, lane_idx) + b8_i = decode_s8_from_lane_word(b, lane_idx) + b4_0_i = decode_s4_from_40(b_lo40, lane_idx) + b4_1_i = decode_s4_hi_from_80(b, lane_idx) + b5_0_i = decode_s5(b_lo40, lane_idx) + b5_1_i = decode_s5_hi_from_80(b, lane_idx) + p2a.append(booth_mul_signed(a8_i, b8_i)) + p2b0.append(booth_mul_signed(a8_i, b4_0_i)) + p2b1.append(booth_mul_signed(a8_i, b4_1_i)) + p2d0.append(booth_mul_signed(a8_i, b5_0_i)) + p2d1.append(booth_mul_signed(a8_i, b5_1_i)) + + for lane_idx in range(16): + a5_i = decode_s5(a, lane_idx) + b0_5_i = decode_s5(b, lane_idx) + b1_5_i = decode_s5(b1, lane_idx) + p2c0.append(booth_mul_signed(a5_i, b0_5_i)) + p2c1.append(booth_mul_signed(a5_i, b1_5_i)) + + return { + "p2a": p2a, + "p2b0": p2b0, + "p2b1": p2b1, + "p2d0": p2d0, + "p2d1": p2d1, + "p2c0": p2c0, + "p2c1": p2c1, + } + + +def comb2_reduce_products(products): + """ + DS §5.5: + - dot8 reduction for 2a/2b/2d + - dot16 split8 partial reduction for 2c + """ + p2a = products["p2a"] + p2b0 = products["p2b0"] + p2b1 = products["p2b1"] + p2d0 = products["p2d0"] + p2d1 = products["p2d1"] + p2c0 = products["p2c0"] + p2c1 = products["p2c1"] + + s2a = dot8_reduce(p2a) + s2b0 = dot8_reduce(p2b0) + s2b1 = dot8_reduce(p2b1) + s2d0 = dot8_reduce(p2d0) + s2d1 = dot8_reduce(p2d1) + s2c0_lo, s2c0_hi = dot16_split8_reduce(p2c0) + s2c1_lo, s2c1_hi = dot16_split8_reduce(p2c1) + return { + "s2a": s2a, + "s2b0": s2b0, + "s2b1": s2b1, + "s2d0": s2d0, + "s2d1": s2d1, + "s2c0_lo": s2c0_lo, + "s2c0_hi": s2c0_hi, + "s2c1_lo": s2c1_lo, + "s2c1_hi": s2c1_hi, + } + + +def comb3_mode_merge(reduced, mode, e1_a, e1_b0, e1_b1): + """ + DS §5.7: + - 2c post-scale x1/x2/x4 + - one-hot mode merge for out0_raw/out1_raw + """ + is_2a, is_2b, is_2c, is_2d = _mode_one_hot(mode) + s2c0 = sum_shift_pair(reduced["s2c0_lo"], reduced["s2c0_hi"], e1_a, e1_b0) + s2c1 = sum_shift_pair(reduced["s2c1_lo"], reduced["s2c1_hi"], e1_a, e1_b1) + + out0_raw = select_one_hot4( + is_2a, + is_2b, + is_2c, + is_2d, + reduced["s2a"], + reduced["s2b0"], + s2c0, + reduced["s2d0"], + ) + out1_raw = select_one_hot4( + is_2a, + is_2b, + is_2c, + is_2d, + reduced["s2a"] * 0, + reduced["s2b1"], + s2c1, + reduced["s2d1"], + ) + return out0_raw, out1_raw diff --git a/designs/PE_INT/python/pe_int/pipeline.py b/designs/PE_INT/python/pe_int/pipeline.py new file mode 100644 index 0000000..c014325 --- /dev/null +++ b/designs/PE_INT/python/pe_int/pipeline.py @@ -0,0 +1,16 @@ +from __future__ import annotations + +from pycircuit import mux + +from .constants import MODE_2A, MODE_2B, MODE_2C + + +def select_mode(mode, v2a, v2b, v2c, v2d): + return mux(mode == MODE_2A, v2a, mux(mode == MODE_2B, v2b, mux(mode == MODE_2C, v2c, v2d))) + + +def out1_hold_policy(domain, *, vld_aligned, out1_en_aligned, out1_aligned, prefix: str = "pe"): + out1_hold = domain.state(width=16, reset_value=0, name=f"{prefix}_out1_hold") + out1_next = mux(vld_aligned, mux(out1_en_aligned, out1_aligned, out1_hold), out1_hold) + out1_hold.set(out1_next) + return out1_next diff --git a/designs/PE_INT/python/pe_int/top.py b/designs/PE_INT/python/pe_int/top.py new file mode 100644 index 0000000..2347f6d --- /dev/null +++ b/designs/PE_INT/python/pe_int/top.py @@ -0,0 +1,156 @@ +from __future__ import annotations + +from pathlib import Path + +try: + from pycircuit import CycleAwareCircuit, CycleAwareDomain, cas, compile_cycle_aware, mux, wire_of +except ImportError: # pragma: no cover - allows local tests without pyCircuit. + CycleAwareCircuit = object # type: ignore[assignment] + CycleAwareDomain = object # type: ignore[assignment] + cas = None # type: ignore[assignment] + compile_cycle_aware = None # type: ignore[assignment] + mux = None # type: ignore[assignment] + wire_of = None # type: ignore[assignment] + +from .constants import DEFAULT_PIPELINE_L, MODE_2A +from .mac_modes import comb1_generate_products, comb2_reduce_products, comb3_mode_merge +from .pipeline import out1_hold_policy + + +def _require_pycircuit() -> None: + if cas is None or compile_cycle_aware is None or wire_of is None or mux is None: + raise RuntimeError( + "pyCircuit 未安裝。請先依 README 設定 PYTHONPATH，或安裝 LinxISA/pyCircuit frontend。" + ) + + +def build(m: CycleAwareCircuit, domain: CycleAwareDomain, latency: int = DEFAULT_PIPELINE_L) -> None: + """ + Explicit DS pipeline: + input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3 -> output + """ + _require_pycircuit() + if int(latency) != DEFAULT_PIPELINE_L: + raise ValueError(f"This top-level implementation requires fixed latency={DEFAULT_PIPELINE_L}.") + + _ = m.input("rst_n", width=1) + in_vld = cas(domain, m.input("vld", width=1), cycle=0) + in_mode = cas(domain, m.input("mode", width=2), cycle=0) + in_a = cas(domain, m.input("a", width=80), cycle=0) + in_b = cas(domain, m.input("b", width=80), cycle=0) + in_b1 = cas(domain, m.input("b1", width=80), cycle=0) + in_e1_a = cas(domain, m.input("e1_a", width=2), cycle=0) + in_e1_b0 = cas(domain, m.input("e1_b0", width=2), cycle=0) + in_e1_b1 = cas(domain, m.input("e1_b1", width=2), cycle=0) + + # comb0: input-side prelogic and control predecode. + c0_is_2a = in_mode == 0 + c0_is_2b = in_mode == 1 + c0_is_2c = in_mode == 2 + c0_is_2d = in_mode == 3 + c0_out1_en = in_mode != MODE_2A + + # reg0: input capture boundary (cycle-aware sampled transaction). + domain.next() + s0_vld = cas(domain, domain.cycle(in_vld, name="pe_int_s0_vld"), cycle=0) + s0_mode = cas(domain, domain.cycle(in_mode, name="pe_int_s0_mode"), cycle=0) + s0_is_2a = cas(domain, domain.cycle(c0_is_2a, name="pe_int_s0_is_2a"), cycle=0) + s0_is_2b = cas(domain, domain.cycle(c0_is_2b, name="pe_int_s0_is_2b"), cycle=0) + s0_is_2c = cas(domain, domain.cycle(c0_is_2c, name="pe_int_s0_is_2c"), cycle=0) + s0_is_2d = cas(domain, domain.cycle(c0_is_2d, name="pe_int_s0_is_2d"), cycle=0) + s0_out1_en = cas(domain, domain.cycle(c0_out1_en, name="pe_int_s0_out1_en"), cycle=0) + s0_a = cas(domain, domain.cycle(in_a, name="pe_int_s0_a"), cycle=0) + s0_b = cas(domain, domain.cycle(in_b, name="pe_int_s0_b"), cycle=0) + s0_b1 = cas(domain, domain.cycle(in_b1, name="pe_int_s0_b1"), cycle=0) + s0_e1_a = cas(domain, domain.cycle(in_e1_a, name="pe_int_s0_e1_a"), cycle=0) + s0_e1_b0 = cas(domain, domain.cycle(in_e1_b0, name="pe_int_s0_e1_b0"), cycle=0) + s0_e1_b1 = cas(domain, domain.cycle(in_e1_b1, name="pe_int_s0_e1_b1"), cycle=0) + + # comb1: lane decode + lane multipliers. + c1_products = comb1_generate_products(s0_a, s0_b, s0_b1) + + # reg1: product vectors + aligned controls. + domain.next() + s1_vld = cas(domain, domain.cycle(s0_vld, name="pe_int_s1_vld"), cycle=0) + s1_mode = cas(domain, domain.cycle(s0_mode, name="pe_int_s1_mode"), cycle=0) + s1_is_2a = cas(domain, domain.cycle(s0_is_2a, name="pe_int_s1_is_2a"), cycle=0) + s1_is_2b = cas(domain, domain.cycle(s0_is_2b, name="pe_int_s1_is_2b"), cycle=0) + s1_is_2c = cas(domain, domain.cycle(s0_is_2c, name="pe_int_s1_is_2c"), cycle=0) + s1_is_2d = cas(domain, domain.cycle(s0_is_2d, name="pe_int_s1_is_2d"), cycle=0) + s1_out1_en = cas(domain, domain.cycle(s0_out1_en, name="pe_int_s1_out1_en"), cycle=0) + s1_e1_a = cas(domain, domain.cycle(s0_e1_a, name="pe_int_s1_e1_a"), cycle=0) + s1_e1_b0 = cas(domain, domain.cycle(s0_e1_b0, name="pe_int_s1_e1_b0"), cycle=0) + s1_e1_b1 = cas(domain, domain.cycle(s0_e1_b1, name="pe_int_s1_e1_b1"), cycle=0) + s1_products = { + "p2a": [cas(domain, domain.cycle(c1_products["p2a"][i], name=f"pe_int_s1_p2a_{i}"), cycle=0) for i in range(8)], + "p2b0": [cas(domain, domain.cycle(c1_products["p2b0"][i], name=f"pe_int_s1_p2b0_{i}"), cycle=0) for i in range(8)], + "p2b1": [cas(domain, domain.cycle(c1_products["p2b1"][i], name=f"pe_int_s1_p2b1_{i}"), cycle=0) for i in range(8)], + "p2d0": [cas(domain, domain.cycle(c1_products["p2d0"][i], name=f"pe_int_s1_p2d0_{i}"), cycle=0) for i in range(8)], + "p2d1": [cas(domain, domain.cycle(c1_products["p2d1"][i], name=f"pe_int_s1_p2d1_{i}"), cycle=0) for i in range(8)], + "p2c0": [cas(domain, domain.cycle(c1_products["p2c0"][i], name=f"pe_int_s1_p2c0_{i}"), cycle=0) for i in range(16)], + "p2c1": [cas(domain, domain.cycle(c1_products["p2c1"][i], name=f"pe_int_s1_p2c1_{i}"), cycle=0) for i in range(16)], + } + + # comb2: dot reductions. + c2_reduced = comb2_reduce_products(s1_products) + + # reg2: reduced sums + aligned controls. + domain.next() + s2_vld = cas(domain, domain.cycle(s1_vld, name="pe_int_s2_vld"), cycle=0) + s2_mode = cas(domain, domain.cycle(s1_mode, name="pe_int_s2_mode"), cycle=0) + s2_is_2a = cas(domain, domain.cycle(s1_is_2a, name="pe_int_s2_is_2a"), cycle=0) + s2_is_2b = cas(domain, domain.cycle(s1_is_2b, name="pe_int_s2_is_2b"), cycle=0) + s2_is_2c = cas(domain, domain.cycle(s1_is_2c, name="pe_int_s2_is_2c"), cycle=0) + s2_is_2d = cas(domain, domain.cycle(s1_is_2d, name="pe_int_s2_is_2d"), cycle=0) + s2_out1_en = cas(domain, domain.cycle(s1_out1_en, name="pe_int_s2_out1_en"), cycle=0) + s2_e1_a = cas(domain, domain.cycle(s1_e1_a, name="pe_int_s2_e1_a"), cycle=0) + s2_e1_b0 = cas(domain, domain.cycle(s1_e1_b0, name="pe_int_s2_e1_b0"), cycle=0) + s2_e1_b1 = cas(domain, domain.cycle(s1_e1_b1, name="pe_int_s2_e1_b1"), cycle=0) + s2_reduced = { + "s2a": cas(domain, domain.cycle(c2_reduced["s2a"], name="pe_int_s2_s2a"), cycle=0), + "s2b0": cas(domain, domain.cycle(c2_reduced["s2b0"], name="pe_int_s2_s2b0"), cycle=0), + "s2b1": cas(domain, domain.cycle(c2_reduced["s2b1"], name="pe_int_s2_s2b1"), cycle=0), + "s2d0": cas(domain, domain.cycle(c2_reduced["s2d0"], name="pe_int_s2_s2d0"), cycle=0), + "s2d1": cas(domain, domain.cycle(c2_reduced["s2d1"], name="pe_int_s2_s2d1"), cycle=0), + "s2c0_lo": cas(domain, domain.cycle(c2_reduced["s2c0_lo"], name="pe_int_s2_s2c0_lo"), cycle=0), + "s2c0_hi": cas(domain, domain.cycle(c2_reduced["s2c0_hi"], name="pe_int_s2_s2c0_hi"), cycle=0), + "s2c1_lo": cas(domain, domain.cycle(c2_reduced["s2c1_lo"], name="pe_int_s2_s2c1_lo"), cycle=0), + "s2c1_hi": cas(domain, domain.cycle(c2_reduced["s2c1_hi"], name="pe_int_s2_s2c1_hi"), cycle=0), + } + + # comb3: post-scale, mode-merge and out1 hold-next preparation. + c3_out0_raw, c3_out1_raw = comb3_mode_merge(s2_reduced, s2_mode, s2_e1_a, s2_e1_b0, s2_e1_b1) + c3_vld_out = s2_vld + c3_out1_update = s2_vld & s2_out1_en + + # reg3: output register boundary and explicit out1 hold register update. + out1 = out1_hold_policy( + domain, + vld_aligned=c3_vld_out, + out1_en_aligned=s2_out1_en, + out1_aligned=wire_of(c3_out1_raw)[0:16], + prefix="pe_int", + ) + domain.next() + out_vld = cas(domain, domain.cycle(c3_vld_out, name="pe_int_s3_vld_out"), cycle=0) + out0 = cas(domain, domain.cycle(wire_of(c3_out0_raw)[0:19], name="pe_int_s3_out0"), cycle=0) + out1 = cas(domain, domain.cycle(out1, name="pe_int_s3_out1"), cycle=0) + + m.output("vld_out", wire_of(out_vld)) + m.output("out0", wire_of(out0)) + m.output("out1", wire_of(out1)) + + +build.__pycircuit_name__ = "pe_int_fix7" + + +def emit_mlir(latency: int = DEFAULT_PIPELINE_L) -> str: + _require_pycircuit() + return compile_cycle_aware(build, name="pe_int", eager=True, latency=int(latency)).emit_mlir() + + +if __name__ == "__main__": + out = Path(__file__).resolve().parents[2] / "build" / "pe_int.mlir" + out.parent.mkdir(parents=True, exist_ok=True) + out.write_text(emit_mlir(), encoding="utf-8") + print(f"Wrote {out}") diff --git a/designs/PE_INT/python/pe_int_pycircuit.py b/designs/PE_INT/python/pe_int_pycircuit.py new file mode 100644 index 0000000..d9d16e6 --- /dev/null +++ b/designs/PE_INT/python/pe_int_pycircuit.py @@ -0,0 +1,24 @@ +from __future__ import annotations + +from pathlib import Path + +from pe_int import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, build, emit_mlir + +build.__pycircuit_name__ = "pe_int_fix7" + +__all__ = [ + "MODE_2A", + "MODE_2B", + "MODE_2C", + "MODE_2D", + "DEFAULT_PIPELINE_L", + "build", + "emit_mlir", +] + + +if __name__ == "__main__": + out = Path(__file__).resolve().parents[1] / "build" / "pe_int.mlir" + out.parent.mkdir(parents=True, exist_ok=True) + out.write_text(emit_mlir(), encoding="utf-8") + print(f"Wrote {out}") diff --git a/designs/PE_INT/python/placeholder.py b/designs/PE_INT/python/placeholder.py new file mode 100644 index 0000000..e69de29 diff --git a/designs/PE_INT/rtl/README.md b/designs/PE_INT/rtl/README.md new file mode 100644 index 0000000..5ff95e6 --- /dev/null +++ b/designs/PE_INT/rtl/README.md @@ -0,0 +1,19 @@ +# Generated RTL + +`rtl/` only stores outputs generated by the `pyCircuit` / `pycc` build flow. + +## Generation + +Run at repo root: + +```bash +python python/build.py --target rtl --out-dir build/pe_int +``` + +Artifact paths may differ by `pycircuit.cli build` version, usually under `build/pe_int/`. + +## Rules + +- Do not handwrite `rtl/*.v`. +- RTL content must be sourced only from `python/pe_int_pycircuit.py` and `tb/tb_pe_int_pycircuit.py`. +- Use `tb_rtl/` for RTL simulations (do not move RTL testcases back into `tb/`). diff --git a/designs/PE_INT/rtl/pe_int_l3.v b/designs/PE_INT/rtl/pe_int_l3.v new file mode 100644 index 0000000..7761bef --- /dev/null +++ b/designs/PE_INT/rtl/pe_int_l3.v @@ -0,0 +1,171 @@ +module pe_int_l3 ( + input wire clk, + input wire rst_n, + input wire vld, + input wire [1:0] mode, + input wire [79:0] a, + input wire [79:0] b, + input wire [79:0] b1, + input wire [1:0] e1_a, + input wire [1:0] e1_b0, + input wire [1:0] e1_b1, + output reg signed [18:0] out0, + output reg signed [15:0] out1, + output reg vld_out +); + +localparam MODE_2A = 2'b00; +localparam MODE_2B = 2'b01; +localparam MODE_2C = 2'b10; +localparam MODE_2D = 2'b11; + +reg [1:0] rst_rel; +wire rst_pipe_n; +assign rst_pipe_n = rst_rel[1]; + +reg s0_vld, s1_vld, s2_vld; +reg [1:0] s0_mode, s1_mode, s2_mode; +reg signed [31:0] s0_sum0, s0_sum1; +reg signed [31:0] s1_sum0, s1_sum1; +reg signed [31:0] s2_sum0, s2_sum1; + +integer i; +reg signed [7:0] a_s8, b_s8; +reg signed [3:0] b0_s4, b1_s4; +reg signed [4:0] a_s5, b0_s5, b1_s5; +reg signed [31:0] c_sum0, c_sum1; +reg signed [31:0] lo0, hi0, lo1, hi1; +reg [1:0] sh_lo0, sh_hi0, sh_lo1, sh_hi1; + +always @* begin + c_sum0 = 32'sd0; + c_sum1 = 32'sd0; + lo0 = 32'sd0; + hi0 = 32'sd0; + lo1 = 32'sd0; + hi1 = 32'sd0; + sh_lo0 = e1_a[0] + e1_b0[0]; + sh_hi0 = e1_a[1] + e1_b0[1]; + sh_lo1 = e1_a[0] + e1_b1[0]; + sh_hi1 = e1_a[1] + e1_b1[1]; + + case (mode) + MODE_2A: begin + for (i = 0; i < 8; i = i + 1) begin + a_s8 = $signed({a[5*(2*i+1)+4 -: 4], a[5*(2*i)+4 -: 4]}); + b_s8 = $signed({b[5*(2*i+1)+4 -: 4], b[5*(2*i)+4 -: 4]}); + c_sum0 = c_sum0 + a_s8 * b_s8; + end + end + MODE_2B: begin + for (i = 0; i < 8; i = i + 1) begin + a_s8 = $signed({a[5*(2*i+1)+4 -: 4], a[5*(2*i)+4 -: 4]}); + b0_s4 = $signed(b[5*i+4 -: 4]); + b1_s4 = $signed(b[40 + 5*i + 4 -: 4]); + c_sum0 = c_sum0 + a_s8 * b0_s4; + c_sum1 = c_sum1 + a_s8 * b1_s4; + end + end + MODE_2C: begin + for (i = 0; i < 16; i = i + 1) begin + a_s5 = $signed(a[5*i+4 -: 5]); + b0_s5 = $signed(b[5*i+4 -: 5]); + b1_s5 = $signed(b1[5*i+4 -: 5]); + if (i < 8) begin + lo0 = lo0 + a_s5 * b0_s5; + lo1 = lo1 + a_s5 * b1_s5; + end else begin + hi0 = hi0 + a_s5 * b0_s5; + hi1 = hi1 + a_s5 * b1_s5; + end + end + c_sum0 = (lo0 <<< sh_lo0) + (hi0 <<< sh_hi0); + c_sum1 = (lo1 <<< sh_lo1) + (hi1 <<< sh_hi1); + end + default: begin + for (i = 0; i < 8; i = i + 1) begin + a_s8 = $signed({a[5*(2*i+1)+4 -: 4], a[5*(2*i)+4 -: 4]}); + b0_s5 = $signed(b[5*i+4 -: 5]); + b1_s5 = $signed(b[40 + 5*i + 4 -: 5]); + c_sum0 = c_sum0 + a_s8 * b0_s5; + c_sum1 = c_sum1 + a_s8 * b1_s5; + end + end + endcase +end + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + rst_rel <= 2'b00; + end else begin + rst_rel <= {rst_rel[0], 1'b1}; + end +end + +always @(posedge clk or negedge rst_n) begin + if (!rst_n) begin + s0_vld <= 1'b0; + s1_vld <= 1'b0; + s2_vld <= 1'b0; + s0_mode <= MODE_2A; + s1_mode <= MODE_2A; + s2_mode <= MODE_2A; + s0_sum0 <= 32'sd0; + s0_sum1 <= 32'sd0; + s1_sum0 <= 32'sd0; + s1_sum1 <= 32'sd0; + s2_sum0 <= 32'sd0; + s2_sum1 <= 32'sd0; + vld_out <= 1'b0; + out0 <= 19'sd0; + out1 <= 16'sd0; + end else if (!rst_pipe_n) begin + s0_vld <= 1'b0; + s1_vld <= 1'b0; + s2_vld <= 1'b0; + s0_mode <= MODE_2A; + s1_mode <= MODE_2A; + s2_mode <= MODE_2A; + s0_sum0 <= 32'sd0; + s0_sum1 <= 32'sd0; + s1_sum0 <= 32'sd0; + s1_sum1 <= 32'sd0; + s2_sum0 <= 32'sd0; + s2_sum1 <= 32'sd0; + vld_out <= 1'b0; + out0 <= 19'sd0; + out1 <= 16'sd0; + end else begin + vld_out <= s2_vld; + if (s2_vld) begin + out0 <= s2_sum0[18:0]; + out1 <= s2_sum1[15:0]; + end + + s2_vld <= s1_vld; + s2_mode <= s1_mode; + s2_sum0 <= s1_sum0; + s2_sum1 <= s1_sum1; + s1_vld <= s0_vld; + s1_mode <= s0_mode; + s1_sum0 <= s0_sum0; + s1_sum1 <= s0_sum1; + + s0_vld <= vld; + s0_mode <= mode; + if (vld) begin + s0_sum0 <= c_sum0; + if (mode == MODE_2A) begin + // Keep previous secondary-lane value in 2a to preserve out1 hold behavior. + s0_sum1 <= s0_sum1; + end else begin + s0_sum1 <= c_sum1; + end + end else begin + s0_sum0 <= 32'sd0; + s0_sum1 <= s0_sum1; + end + end +end + +endmodule diff --git a/designs/PE_INT/rtl/pyc_primitives.v b/designs/PE_INT/rtl/pyc_primitives.v new file mode 100644 index 0000000..6ae1348 --- /dev/null +++ b/designs/PE_INT/rtl/pyc_primitives.v @@ -0,0 +1,658 @@ +// pyCircuit Verilog primitives (concatenated) +/* verilator lint_off DECLFILENAME */ + +// --- pyc_reg.v +// Simple synchronous reset register (prototype). +module pyc_reg #( + parameter WIDTH = 1 +) ( + input clk, + input rst, + input en, + input [WIDTH-1:0] d, + input [WIDTH-1:0] init, + output reg [WIDTH-1:0] q +); + always @(posedge clk) begin + if (rst) + q <= init; + else if (en) + q <= d; + end +endmodule + + +// --- pyc_fifo.v +// Ready/valid FIFO with synchronous reset (prototype). +module pyc_fifo #( + parameter WIDTH = 1, + parameter DEPTH = 2 +) ( + input clk, + input rst, + + // Input (producer -> fifo) + input in_valid, + output in_ready, + input [WIDTH-1:0] in_data, + + // Output (fifo -> consumer) + output out_valid, + input out_ready, + output [WIDTH-1:0] out_data +); + `ifndef SYNTHESIS + initial begin + if (DEPTH <= 0) begin + $display("ERROR: pyc_fifo DEPTH must be > 0"); + $finish; + end + end + `endif + + function integer pyc_clog2; + input integer value; + integer i; + begin + pyc_clog2 = 0; + for (i = value - 1; i > 0; i = i >> 1) + pyc_clog2 = pyc_clog2 + 1; + end + endfunction + + localparam PTR_W = (DEPTH <= 1) ? 1 : pyc_clog2(DEPTH); + + reg [WIDTH-1:0] storage [0:DEPTH-1]; + reg [PTR_W-1:0] rd_ptr; + reg [PTR_W-1:0] wr_ptr; + reg [PTR_W:0] count; + + assign in_ready = (count < DEPTH) || (out_ready && out_valid); + assign out_valid = (count != 0); + // Define out_data when empty to keep C++/Verilog equivalence deterministic. + assign out_data = out_valid ? storage[rd_ptr] : {WIDTH{1'b0}}; + + wire do_pop; + wire do_push; + assign do_pop = out_valid && out_ready; + assign do_push = in_valid && in_ready; + + function [PTR_W-1:0] bump_ptr; + input [PTR_W-1:0] p; + begin + if (DEPTH <= 1) + bump_ptr = {PTR_W{1'b0}}; + else if (p == (DEPTH - 1)) + bump_ptr = {PTR_W{1'b0}}; + else + bump_ptr = p + 1'b1; + end + endfunction + + always @(posedge clk) begin + if (rst) begin + rd_ptr <= {PTR_W{1'b0}}; + wr_ptr <= {PTR_W{1'b0}}; + count <= {(PTR_W + 1){1'b0}}; + end else begin + case ({do_push, do_pop}) + 2'b00: begin + // hold + end + 2'b01: begin + rd_ptr <= bump_ptr(rd_ptr); + count <= count - 1'b1; + end + 2'b10: begin + storage[wr_ptr] <= in_data; + wr_ptr <= bump_ptr(wr_ptr); + count <= count + 1'b1; + end + 2'b11: begin + // push + pop in the same cycle + storage[wr_ptr] <= in_data; + rd_ptr <= bump_ptr(rd_ptr); + wr_ptr <= bump_ptr(wr_ptr); + count <= count; + end + endcase + end + end +endmodule + + +// --- pyc_byte_mem.v +// Byte-addressed memory (prototype). +// +// - `DEPTH` is in bytes. +// - Combinational little-endian read window. +// - Byte-enable write on posedge. +module pyc_byte_mem #( + parameter ADDR_WIDTH = 64, + parameter DATA_WIDTH = 64, + parameter DEPTH = 1024, + // Optional init file (Vivado: can be used for BRAM init; simulation: $readmemh). + // If the file cannot be opened, initialization is skipped. + parameter INIT_MEMH = "" +) ( + input clk, + input rst, + + input [ADDR_WIDTH-1:0] raddr, + output reg [DATA_WIDTH-1:0] rdata, + + input wvalid, + input [ADDR_WIDTH-1:0] waddr, + input [DATA_WIDTH-1:0] wdata, + input [(DATA_WIDTH+7)/8-1:0] wstrb +); + localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; + + // Byte storage. + reg [7:0] mem [0:DEPTH-1]; + + // Optional initialization. + integer init_fd; + integer init_i; + initial begin + `ifndef SYNTHESIS + // Deterministic simulation init: keep C++/Verilog equivalence stable. + for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) + mem[init_i] = 8'h00; + `endif + if (INIT_MEMH != "") begin + init_fd = $fopen(INIT_MEMH, "r"); + if (init_fd != 0) begin + $fclose(init_fd); + $readmemh(INIT_MEMH, mem); + end + end + end + + // Combinational read: assemble DATA_WIDTH bits from successive bytes. + integer i; + integer a; + always @* begin + a = raddr[31:0]; + rdata = {DATA_WIDTH{1'b0}}; + for (i = 0; i < STRB_WIDTH; i = i + 1) begin + if ((a + i) < DEPTH) + rdata[8 * i +: 8] = mem[a + i]; + end + end + + // Byte-enable write. + integer j; + integer wa; + always @(posedge clk) begin + if (rst) begin + // Reset does not clear memory (init happens via INIT_MEMH or sim-default 0s). + end else if (wvalid) begin + wa = waddr[31:0]; + for (j = 0; j < STRB_WIDTH; j = j + 1) begin + if (wstrb[j] && ((wa + j) < DEPTH)) + mem[wa + j] <= wdata[8 * j +: 8]; + end + end + end +endmodule + + +// --- pyc_sync_mem.v +// Synchronous 1R1W memory with registered read data (prototype). +// +// - `DEPTH` is in entries (not bytes). +// - Read is synchronous: when `ren` is asserted, `rdata` updates on the next +// rising edge of `clk`. +// - Write is synchronous with byte enables `wstrb`. +// +// Note: Read-during-write to the same address returns the pre-write data +// ("old-data") by default. +module pyc_sync_mem #( + parameter ADDR_WIDTH = 64, + parameter DATA_WIDTH = 64, + parameter DEPTH = 1024 +) ( + input clk, + input rst, + + input ren, + input [ADDR_WIDTH-1:0] raddr, + output reg [DATA_WIDTH-1:0] rdata, + + input wvalid, + input [ADDR_WIDTH-1:0] waddr, + input [DATA_WIDTH-1:0] wdata, + input [(DATA_WIDTH+7)/8-1:0] wstrb +); + `ifndef SYNTHESIS + initial begin + if (DEPTH <= 0) begin + $display("ERROR: pyc_sync_mem DEPTH must be > 0"); + $finish; + end + end + `endif + + localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; + localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); + // Use a compact address for FPGA-friendly inference. For non-power-of-two + // depths, some addresses in [DEPTH, 2**ADDR_BITS) are unused. + localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); + + // Storage. + `ifdef PYC_TARGET_FPGA + (* ram_style = "block" *) + (* ramstyle = "M20K" *) + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `else + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `endif + + `ifndef SYNTHESIS + // Deterministic simulation init: keep C++/Verilog equivalence stable. + integer init_i; + initial begin + for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) + mem[init_i] = {DATA_WIDTH{1'b0}}; + end + `endif + + integer i; + reg [DATA_WIDTH-1:0] rd_word; + wire [ADDR_BITS-1:0] ra = raddr[ADDR_BITS-1:0]; + wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; + + always @(posedge clk) begin + if (rst) begin + rdata <= {DATA_WIDTH{1'b0}}; + end else begin + // Write with per-lane strobes; last lane may be narrower than 8 bits. + if (wvalid) begin + `ifndef SYNTHESIS + if (wa < DEPTH) begin + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + end + `else + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + `endif + end + + // Registered read. + if (ren) begin + `ifndef SYNTHESIS + if (ra < DEPTH) begin + rd_word = mem[ra]; + rdata <= rd_word; + end else begin + rdata <= {DATA_WIDTH{1'b0}}; + end + `else + rd_word = mem[ra]; + rdata <= rd_word; + `endif + end + end + end +endmodule + + +// --- pyc_sync_mem_dp.v +// Synchronous 2R1W memory with registered read data (prototype). +// +// - `DEPTH` is in entries (not bytes). +// - Both reads are synchronous (registered outputs). +// - One write port with byte enables `wstrb`. +// - Read-during-write to the same address returns pre-write data ("old-data") by default. +module pyc_sync_mem_dp #( + parameter ADDR_WIDTH = 64, + parameter DATA_WIDTH = 64, + parameter DEPTH = 1024 +) ( + input clk, + input rst, + + input ren0, + input [ADDR_WIDTH-1:0] raddr0, + output reg [DATA_WIDTH-1:0] rdata0, + + input ren1, + input [ADDR_WIDTH-1:0] raddr1, + output reg [DATA_WIDTH-1:0] rdata1, + + input wvalid, + input [ADDR_WIDTH-1:0] waddr, + input [DATA_WIDTH-1:0] wdata, + input [(DATA_WIDTH+7)/8-1:0] wstrb +); + `ifndef SYNTHESIS + initial begin + if (DEPTH <= 0) begin + $display("ERROR: pyc_sync_mem_dp DEPTH must be > 0"); + $finish; + end + end + `endif + + localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; + localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); + localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); + + `ifdef PYC_TARGET_FPGA + (* ram_style = "block" *) + (* ramstyle = "M20K" *) + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `else + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `endif + + `ifndef SYNTHESIS + // Deterministic simulation init: keep C++/Verilog equivalence stable. + integer init_i; + initial begin + for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) + mem[init_i] = {DATA_WIDTH{1'b0}}; + end + `endif + + integer i; + reg [DATA_WIDTH-1:0] rd0; + reg [DATA_WIDTH-1:0] rd1; + wire [ADDR_BITS-1:0] ra0 = raddr0[ADDR_BITS-1:0]; + wire [ADDR_BITS-1:0] ra1 = raddr1[ADDR_BITS-1:0]; + wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; + + always @(posedge clk) begin + if (rst) begin + rdata0 <= {DATA_WIDTH{1'b0}}; + rdata1 <= {DATA_WIDTH{1'b0}}; + end else begin + // Write with per-lane strobes; last lane may be narrower than 8 bits. + if (wvalid) begin + `ifndef SYNTHESIS + if (wa < DEPTH) begin + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + end + `else + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + `endif + end + + // Registered read port 0. + if (ren0) begin + `ifndef SYNTHESIS + if (ra0 < DEPTH) begin + rd0 = mem[ra0]; + rdata0 <= rd0; + end else begin + rdata0 <= {DATA_WIDTH{1'b0}}; + end + `else + rd0 = mem[ra0]; + rdata0 <= rd0; + `endif + end + + // Registered read port 1. + if (ren1) begin + `ifndef SYNTHESIS + if (ra1 < DEPTH) begin + rd1 = mem[ra1]; + rdata1 <= rd1; + end else begin + rdata1 <= {DATA_WIDTH{1'b0}}; + end + `else + rd1 = mem[ra1]; + rdata1 <= rd1; + `endif + end + end + end +endmodule + + +// --- pyc_async_fifo.v +// Async ready/valid FIFO with gray-code pointers (prototype). +// +// - Strict ready/valid handshake (no combinational cross-domain paths). +// - `DEPTH` must be a power of two and >= 2. +// - Synchronous resets (per domain). +// +// This is a minimal, synthesizable async FIFO suitable for CDC of data streams. +module pyc_async_fifo #( + parameter WIDTH = 1, + parameter DEPTH = 2 +) ( + // Write domain (producer -> fifo) + input in_clk, + input in_rst, + input in_valid, + output in_ready, + input [WIDTH-1:0] in_data, + + // Read domain (fifo -> consumer) + input out_clk, + input out_rst, + output out_valid, + input out_ready, + output [WIDTH-1:0] out_data +); + `ifndef SYNTHESIS + initial begin + if (DEPTH < 2) begin + $display("ERROR: pyc_async_fifo DEPTH must be >= 2"); + $finish; + end + if ((DEPTH & (DEPTH - 1)) != 0) begin + $display("ERROR: pyc_async_fifo DEPTH must be a power of two"); + $finish; + end + end + `endif + + function integer pyc_clog2; + input integer value; + integer i; + begin + pyc_clog2 = 0; + for (i = value - 1; i > 0; i = i >> 1) + pyc_clog2 = pyc_clog2 + 1; + end + endfunction + + localparam AW = pyc_clog2(DEPTH); + + // Storage. + reg [WIDTH-1:0] mem [0:DEPTH-1]; + + // --- pointer helpers --- + function [AW:0] bin2gray; + input [AW:0] b; + begin + bin2gray = (b >> 1) ^ b; + end + endfunction + + // --- write domain --- + reg [AW:0] wptr_bin; + reg [AW:0] wptr_gray; + wire [AW:0] wptr_bin_next; + wire [AW:0] wptr_gray_next; + reg wfull; + + // Read pointer gray (owned by read domain), referenced for synchronization. + reg [AW:0] rptr_gray; + + reg [AW:0] rptr_gray_w1; + reg [AW:0] rptr_gray_w2; + + wire wfull_next; + wire do_push; + + assign in_ready = ~wfull; + assign do_push = in_valid && in_ready; + assign wptr_bin_next = wptr_bin + (do_push ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); + assign wptr_gray_next = bin2gray(wptr_bin_next); + // Full detection compares next wptr gray against synchronized rptr gray with + // the top 2 bits inverted (classic async FIFO technique). For DEPTH=2, AW=1 + // and there are no "lower" bits to append. + generate + if (AW == 1) begin : gen_wfull_aw1 + assign wfull_next = (wptr_gray_next == ~rptr_gray_w2); + end else begin : gen_wfull_awn + assign wfull_next = (wptr_gray_next == {~rptr_gray_w2[AW:AW-1], rptr_gray_w2[AW-2:0]}); + end + endgenerate + + integer wi; + always @(posedge in_clk) begin + if (in_rst) begin + wptr_bin <= {AW+1{1'b0}}; + wptr_gray <= {AW+1{1'b0}}; + wfull <= 1'b0; + rptr_gray_w1 <= {AW+1{1'b0}}; + rptr_gray_w2 <= {AW+1{1'b0}}; + end else begin + // Sync read pointer into write clock domain. + rptr_gray_w1 <= rptr_gray; + rptr_gray_w2 <= rptr_gray_w1; + + if (do_push) begin + mem[wptr_bin[AW-1:0]] <= in_data; + end + wptr_bin <= wptr_bin_next; + wptr_gray <= wptr_gray_next; + wfull <= wfull_next; + end + end + + reg [AW:0] rptr_bin; + // rptr_gray is declared above (referenced by the write domain sync flops). + wire [AW:0] rptr_bin_next; + wire [AW:0] rptr_gray_next; + + reg [AW:0] wptr_gray_r1; + reg [AW:0] wptr_gray_r2; + + reg out_valid_r; + reg [WIDTH-1:0] out_data_r; + + wire empty_now; + wire empty_next; + wire do_pop; + + assign empty_now = (rptr_gray == wptr_gray_r2); + assign out_valid = out_valid_r; + assign out_data = out_data_r; + + assign do_pop = out_valid_r && out_ready; + assign rptr_bin_next = rptr_bin + (do_pop ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); + assign rptr_gray_next = bin2gray(rptr_bin_next); + assign empty_next = (rptr_gray_next == wptr_gray_r2); + + integer ri; + always @(posedge out_clk) begin + if (out_rst) begin + rptr_bin <= {AW+1{1'b0}}; + rptr_gray <= {AW+1{1'b0}}; + wptr_gray_r1 <= {AW+1{1'b0}}; + wptr_gray_r2 <= {AW+1{1'b0}}; + out_valid_r <= 1'b0; + out_data_r <= {WIDTH{1'b0}}; + end else begin + // Sync write pointer into read clock domain. + wptr_gray_r1 <= wptr_gray; + wptr_gray_r2 <= wptr_gray_r1; + + if (!out_valid_r) begin + // Fill output register when data becomes available. + if (!empty_now) begin + out_valid_r <= 1'b1; + out_data_r <= mem[rptr_bin[AW-1:0]]; + end + end else if (do_pop) begin + // Pop current word; either refill with next word or go empty. + rptr_bin <= rptr_bin_next; + rptr_gray <= rptr_gray_next; + if (empty_next) begin + out_valid_r <= 1'b0; + out_data_r <= {WIDTH{1'b0}}; + end else begin + out_valid_r <= 1'b1; + out_data_r <= mem[rptr_bin_next[AW-1:0]]; + end + end + end + end +endmodule + + +// --- pyc_cdc_sync.v +// CDC synchronizer (prototype). +// +// This is a simple multi-stage flop pipeline in the destination clock domain. +// It is suitable for single-bit control signals. For multi-bit buses, prefer a +// proper CDC protocol (async FIFO, handshake, etc). +module pyc_cdc_sync #( + parameter WIDTH = 1, + parameter STAGES = 2 +) ( + input clk, + input rst, + input [WIDTH-1:0] in, + output [WIDTH-1:0] out +); + `ifndef SYNTHESIS + initial begin + if (STAGES < 1) begin + $display("ERROR: pyc_cdc_sync STAGES must be >= 1"); + $finish; + end + end + `endif + + `ifdef PYC_TARGET_FPGA + (* async_reg = "true" *) + reg [WIDTH-1:0] pipe [0:STAGES-1]; + `else + reg [WIDTH-1:0] pipe [0:STAGES-1]; + `endif + + integer i; + always @(posedge clk) begin + if (rst) begin + for (i = 0; i < STAGES; i = i + 1) + pipe[i] <= {WIDTH{1'b0}}; + end else begin + pipe[0] <= in; + for (i = 1; i < STAGES; i = i + 1) + pipe[i] <= pipe[i - 1]; + end + end + + assign out = pipe[STAGES-1]; +endmodule + + +/* verilator lint_on DECLFILENAME */ diff --git a/designs/PE_INT/sim/README.md b/designs/PE_INT/sim/README.md new file mode 100644 index 0000000..dbb8f5c --- /dev/null +++ b/designs/PE_INT/sim/README.md @@ -0,0 +1,49 @@ +# sim (One-Command Simulation) + +This directory provides an interactive one-command script: + +- `run_sim.sh` + +## Features + +Before execution, the script prompts for options (5-second timeout per prompt, then default is used): + +1. testcase vector seed (default: current timestamp) +2. simulator: `iverilog` / `verilator` (default: `iverilog`) +3. generate waveform or not (default: `No`) +4. waveform format: `vcd` / `fst` (default: `vcd`) + +The script first resolves and runs the model vector generator from `model/model.f`: + +```bash +python3 --seed +``` + +Then it runs all testcases in `tb_rtl/case` via filelists (`filelist/pe_int.f` + `tb_rtl/tb.f`). + +## Reproducibility + +- The same seed always generates identical `tc_mode_switch_random` vectors and expected values. +- The same seed also generates identical sanity vectors (`tc_mode2a/2b/2c/2d_sanity`); different seeds produce different vectors. +- Both `iverilog` and `verilator` use the same seed generation flow, so seed behavior is consistent across simulators. +- Each testcase has an independent log, and the seed is recorded at the beginning for replay. +- Log path: + - `sim/logs//_run/seed__.log` + +## Run + +```bash +bash sim/run_sim.sh +``` + +## Waveform Output + +- When waveform output is enabled, files are written to: + - `sim/waves///wave.` + +## Simulator Differences (Handled by Script) + +- `iverilog`: runs through `iverilog + vvp`; waveform via `$dumpfile/$dumpvars` (commonly VCD). +- `verilator`: automatically adds: + - `--trace`（VCD） + - `--trace-fst`（FST） diff --git a/designs/PE_INT/sim/run_all_wsl.sh b/designs/PE_INT/sim/run_all_wsl.sh new file mode 100644 index 0000000..0244ecd --- /dev/null +++ b/designs/PE_INT/sim/run_all_wsl.sh @@ -0,0 +1,53 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)" +cd "$ROOT" +export PE_INT="$ROOT" + +export PATH="$HOME/.local/bin:$PATH" + +mkdir -p build + +RTL_FILELIST_SRC="$ROOT/filelist/pe_int.f" +TB_FILELIST_SRC="$ROOT/tb_rtl/tb.f" +MODEL_FILELIST_SRC="$ROOT/model/model.f" + +RTL_FILELIST="build/.pe_int.resolved.f" +TB_FILELIST="build/.tb.resolved.f" +MODEL_FILELIST="build/.model.resolved.f" + +sed "s|\$PE_INT|${PE_INT}|g" "$RTL_FILELIST_SRC" > "$RTL_FILELIST" +sed "s|\$PE_INT|${PE_INT}|g" "$TB_FILELIST_SRC" > "$TB_FILELIST" +sed "s|\$PE_INT|${PE_INT}|g" "$MODEL_FILELIST_SRC" > "$MODEL_FILELIST" + +MODEL_GEN_SCRIPT="$(awk '{ gsub(/\r$/, "", $0); if ($0 ~ /gen_rtl_case_vectors\.py$/) { print; exit } }' "$MODEL_FILELIST")" +if [[ -z "${MODEL_GEN_SCRIPT}" ]]; then + echo "[ERR] Could not find gen_rtl_case_vectors.py in model/model.f" + exit 1 +fi + +echo "[INFO] Regenerating testcase vectors from model/ ..." +python3 "$MODEL_GEN_SCRIPT" + +CASES=( + "tc_mode2a_sanity" + "tc_mode2b_sanity" + "tc_mode2c_sanity" + "tc_mode2d_sanity" + "tc_mode_switch_random" +) + +echo "[INFO] Running RTL cases with iverilog..." +for c in "${CASES[@]}"; do + iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" + vvp "build/${c}.iv.out" +done + +echo "[INFO] Running RTL cases with verilator..." +for c in "${CASES[@]}"; do + verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + "./obj_dir/${c}.vlt.out" +done + +echo "[PASS] all tb_rtl cases passed on iverilog + verilator." diff --git a/designs/PE_INT/sim/run_sim.sh b/designs/PE_INT/sim/run_sim.sh new file mode 100644 index 0000000..702ff7c --- /dev/null +++ b/designs/PE_INT/sim/run_sim.sh @@ -0,0 +1,267 @@ +#!/usr/bin/env bash +set -euo pipefail + +ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)" +cd "$ROOT" +export PE_INT="$ROOT" +GEN_DIR="${ROOT}/tb_rtl/case/generated" + +export PATH="$HOME/.local/bin:$PATH" +PROMPT_TIMEOUT_SEC=30 + +CASES=( + "tc_mode2a_sanity" + "tc_mode2b_sanity" + "tc_mode2c_sanity" + "tc_mode2d_sanity" + "tc_mode_switch_random" +) + +mkdir -p build + +RTL_FILELIST_SRC="$ROOT/filelist/pe_int.f" +TB_FILELIST_SRC="$ROOT/tb_rtl/tb.f" +MODEL_FILELIST_SRC="$ROOT/model/model.f" + +RTL_FILELIST="build/.pe_int.resolved.f" +TB_FILELIST="build/.tb.resolved.f" +MODEL_FILELIST="build/.model.resolved.f" + +sed "s|\$PE_INT|${PE_INT}|g" "$RTL_FILELIST_SRC" > "$RTL_FILELIST" +sed "s|\$PE_INT|${PE_INT}|g" "$TB_FILELIST_SRC" > "$TB_FILELIST" +sed "s|\$PE_INT|${PE_INT}|g" "$MODEL_FILELIST_SRC" > "$MODEL_FILELIST" + +MODEL_GEN_SCRIPT="$(awk '{ gsub(/\r$/, "", $0); if ($0 ~ /gen_rtl_case_vectors\.py$/) { print; exit } }' "$MODEL_FILELIST")" +if [[ -z "${MODEL_GEN_SCRIPT}" ]]; then + echo "[ERR] Could not find gen_rtl_case_vectors.py in model/model.f" + exit 1 +fi + +DEFAULT_SEED="$(date +%s)" +if [[ ! "$DEFAULT_SEED" =~ ^[0-9]+$ ]]; then + DEFAULT_SEED="20260420" +fi + +timed_prompt() { + local __out_var="$1" + local __title="$2" + local __default="$3" + local __timeout="${4:-$PROMPT_TIMEOUT_SEC}" + local __input="" + local __remain="$__timeout" + local __last_remain=-1 + local __start_ts + local __now_ts + + echo + echo "${__title} (default: ${__default}, timeout ${__timeout}s):" + + # Non-interactive mode (e.g. piped input): keep predictable timeout behavior. + if [[ ! -t 0 || ! -t 1 ]]; then + printf "[INFO] 倒數 %2ds（輸入完成請按 Enter）> " "$__timeout" + if IFS= read -r -t "$__timeout" __input; then + : + else + echo + echo "[INFO] timeout reached, use default: ${__default}" + __input="$__default" + fi + if [[ -z "$__input" ]]; then + __input="$__default" + fi + printf -v "$__out_var" "%s" "$__input" + return 0 + fi + + # Interactive mode: dynamic countdown line is updated independently, + # while user input remains on the next line without being overwritten. + __start_ts="$(date +%s)" + echo "[INFO] time left: ${__timeout}s" + printf "> " + while (( __remain > 0 )); do + __now_ts="$(date +%s)" + __remain=$((__timeout - (__now_ts - __start_ts))) + if (( __remain < 0 )); then + __remain=0 + fi + + if (( __remain != __last_remain )); then + printf "\033[s\033[1A\r\033[2K[INFO] time left: %2ds\033[u" "$__remain" + __last_remain="$__remain" + fi + + # Read a full line for up to 1 second. + # Pressing Enter immediately submits (empty line allowed) and skips countdown. + if IFS= read -r -t 1 __input; then + break + fi + done + + if (( __remain == 0 )) && [[ -z "$__input" ]]; then + echo + echo "[INFO] timeout reached, use default: ${__default}" + __input="$__default" + elif [[ -z "$__input" ]]; then + __input="$__default" + fi + printf -v "$__out_var" "%s" "$__input" + return 0 +} + +timed_prompt SEED_IN "Random seed for testcase vectors" "$DEFAULT_SEED" +if [[ "$SEED_IN" =~ ^[0-9]+$ ]]; then + BASE_SEED="$SEED_IN" +else + echo "[WARN] Invalid seed '$SEED_IN', fallback to default: ${DEFAULT_SEED}" + BASE_SEED="$DEFAULT_SEED" +fi + +DEFAULT_SEED_RUNS=10 +timed_prompt SEED_RUNS_IN "How many different seeds to run?" "$DEFAULT_SEED_RUNS" +if [[ "$SEED_RUNS_IN" =~ ^[0-9]+$ ]] && [[ "$SEED_RUNS_IN" -ge 1 ]]; then + SEED_RUNS="$SEED_RUNS_IN" +else + echo "[WARN] Invalid seed-run count '$SEED_RUNS_IN', fallback to default: ${DEFAULT_SEED_RUNS}" + SEED_RUNS="$DEFAULT_SEED_RUNS" +fi + +timed_prompt SIM "Select simulator iverilog(i)/verilator(v), enter [i/v]" "i" +SIM="$(echo "$SIM" | tr '[:upper:]' '[:lower:]')" +if [[ "$SIM" == "i" ]]; then + SIM="iverilog" +elif [[ "$SIM" == "v" ]]; then + SIM="verilator" +fi +if [[ "$SIM" != "iverilog" && "$SIM" != "verilator" ]]; then + echo "[WARN] Unknown simulator '$SIM', fallback to default: iverilog" + SIM="iverilog" +fi + +timed_prompt WAVE_ANS "Generate waveform? [y/N]" "n" +WAVE_ANS="$(echo "$WAVE_ANS" | tr '[:upper:]' '[:lower:]')" +WAVE_ON=0 +if [[ "$WAVE_ANS" == "y" || "$WAVE_ANS" == "yes" ]]; then + WAVE_ON=1 +fi + +WAVE_FMT="vcd" +if [[ "$WAVE_ON" -eq 1 ]]; then + timed_prompt WAVE_FMT_ANS "Wave format vcd(v)/fst(f), enter [v/f]" "v" + WAVE_FMT_ANS="$(echo "$WAVE_FMT_ANS" | tr '[:upper:]' '[:lower:]')" + if [[ "$WAVE_FMT_ANS" == "v" ]]; then + WAVE_FMT="vcd" + elif [[ "$WAVE_FMT_ANS" == "f" ]]; then + WAVE_FMT="fst" + elif [[ "$WAVE_FMT_ANS" == "fst" || "$WAVE_FMT_ANS" == "vcd" ]]; then + WAVE_FMT="$WAVE_FMT_ANS" + else + echo "[WARN] Unknown wave format '$WAVE_FMT_ANS', fallback to default: vcd" + WAVE_FMT="vcd" + fi +fi + +if [[ "$SIM" == "iverilog" && "$WAVE_ON" -eq 1 && "$WAVE_FMT" == "fst" ]]; then + echo "[WARN] Icarus Verilog workflow commonly uses VCD. Fallback wave format: vcd" + WAVE_FMT="vcd" +fi + +cleanup_pass_logs() { + local sim_log_root="sim/logs/${SIM}" + local deleted=0 + local log_file + if [[ ! -d "$sim_log_root" ]]; then + return + fi + shopt -s globstar nullglob + for log_file in "$sim_log_root"/**/*.log; do + if ! grep -Eq "\[ERR\]|\[FAIL\]|FATAL" "$log_file"; then + rm -f "$log_file" + deleted=$((deleted + 1)) + fi + done + shopt -u globstar nullglob + if [[ "$deleted" -gt 0 ]]; then + echo "[INFO] Removed ${deleted} historical pass logs under ${sim_log_root}." + fi +} + +echo +echo "[INFO] simulator=$SIM wave=$WAVE_ON format=$WAVE_FMT base_seed=$BASE_SEED seed_runs=$SEED_RUNS" + +WAVE_ROOT="sim/waves/${SIM}" +if [[ "$WAVE_ON" -eq 1 ]]; then + mkdir -p "$WAVE_ROOT" +fi + +cleanup_pass_logs + +for ((seed_idx = 0; seed_idx < SEED_RUNS; seed_idx++)); do + SEED=$((BASE_SEED + seed_idx)) + echo + echo "[INFO] ===== seed run $((seed_idx + 1))/${SEED_RUNS}: seed=${SEED} =====" + echo "[INFO] Re-generate testcase vectors from model/ (seed=${SEED})" + python3 "$MODEL_GEN_SCRIPT" --seed "$SEED" + + RUN_TAG="$(date +%Y%m%d_%H%M%S)_run$((seed_idx + 1))" + LOG_ROOT="sim/logs/${SIM}/${RUN_TAG}" + mkdir -p "$LOG_ROOT" + echo "[INFO] testcase logs are under ${LOG_ROOT}" + + if [[ "$SIM" == "iverilog" ]]; then + for c in "${CASES[@]}"; do + CASE_LOG="${LOG_ROOT}/seed_${SEED}_${c}.log" + { + echo "[INFO] simulator=iverilog case=${c} seed=${SEED}" + iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" + if [[ "$WAVE_ON" -eq 1 ]]; then + CASE_WAVE_DIR="${WAVE_ROOT}/${c}" + mkdir -p "$CASE_WAVE_DIR" + ( + cd "$CASE_WAVE_DIR" + vvp "${ROOT}/build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 + ) + else + vvp "build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" + fi + } 2>&1 | tee "$CASE_LOG" + done + else + for c in "${CASES[@]}"; do + CASE_LOG="${LOG_ROOT}/seed_${SEED}_${c}.log" + { + echo "[INFO] simulator=verilator case=${c} seed=${SEED}" + if [[ "$seed_idx" -eq 0 ]]; then + if [[ "$WAVE_ON" -eq 1 && "$WAVE_FMT" == "fst" ]]; then + verilator --binary --timing -Wall -Wno-fatal --trace-fst -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + elif [[ "$WAVE_ON" -eq 1 ]]; then + verilator --binary --timing -Wall -Wno-fatal --trace -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + else + verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + fi + else + echo "[INFO] reuse existing verilator binary for ${c}" + fi + + if [[ "$WAVE_ON" -eq 1 ]]; then + CASE_WAVE_DIR="${WAVE_ROOT}/${c}" + mkdir -p "$CASE_WAVE_DIR" + ( + cd "$CASE_WAVE_DIR" + if [[ "$WAVE_FMT" == "fst" ]]; then + "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=1 + else + "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 + fi + ) + else + "./obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" + fi + } 2>&1 | tee "$CASE_LOG" + done + fi +done + +echo "[PASS] all cases passed with simulator=$SIM seed_runs=$SEED_RUNS (base_seed=$BASE_SEED)." +if [[ "$WAVE_ON" -eq 1 ]]; then + echo "[INFO] waveform files are under ${WAVE_ROOT}//wave.${WAVE_FMT}" +fi diff --git a/designs/PE_INT/spec_raw.txt b/designs/PE_INT/spec_raw.txt new file mode 100644 index 0000000..e69de29 diff --git a/designs/PE_INT/tb/README.md b/designs/PE_INT/tb/README.md new file mode 100644 index 0000000..96d3a79 --- /dev/null +++ b/designs/PE_INT/tb/README.md @@ -0,0 +1,14 @@ +# tb (PyCircuit / Model-Oriented Testbench) + +This directory only contains: + +- PyCircuit testbenches (for example `tb_pe_int_pycircuit.py`) +- PyCircuit-related test flow files + +## Do Not Put Here + +- Model implementation and model regression files (put in `model/`) +- RTL-specific Verilog testbenches +- RTL testcase datasets + +Those artifacts belong in `model/` and `tb_rtl/` respectively. diff --git a/designs/PE_INT/tb/tb_pe_int_pycircuit.py b/designs/PE_INT/tb/tb_pe_int_pycircuit.py new file mode 100644 index 0000000..5397132 --- /dev/null +++ b/designs/PE_INT/tb/tb_pe_int_pycircuit.py @@ -0,0 +1,103 @@ +from __future__ import annotations + +import sys +from pathlib import Path + +from pycircuit import ( + CycleAwareCircuit, + CycleAwareDomain, + CycleAwareTb, + Tb, + compile_cycle_aware, + testbench, +) + +_THIS_DIR = Path(__file__).resolve().parent +_PY_DIR = _THIS_DIR.parent / "python" +_MODEL_DIR = _THIS_DIR.parent / "model" +if str(_PY_DIR) not in sys.path: + sys.path.insert(0, str(_PY_DIR)) +if str(_MODEL_DIR) not in sys.path: + sys.path.insert(0, str(_MODEL_DIR)) + +from pe_int_pycircuit import build # noqa: E402 +from ref_model import MODE_2A, MODE_2B, compute_transaction, pack_s4x8_to_40, pack_s8x8_to_laneword # noqa: E402 + +DEFAULT_PARAMS = {"latency": 3} + + +def _to_u(value: int, bits: int) -> int: + return value & ((1 << bits) - 1) + + +def _mode2b_vector(): + a = [1, -2, 3, -4, 5, -6, 7, -8] + b0 = [1, 2, -3, 4, -5, 6, -7, -8] + b1 = [-1, 2, 3, -4, 5, -6, 7, 0] + a80 = pack_s8x8_to_laneword(a) + b80 = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) + exp = compute_transaction(MODE_2B, a80, b80, 0, (0, 0), (0, 0), (0, 0)) + return a80, b80, exp + + +@testbench +def tb(t: Tb) -> None: + tb = CycleAwareTb(t) + tb.clock("clk") + tb.reset("rst_n", cycles_asserted=2, cycles_deasserted=1) + tb.timeout(200) + + a80, b80, exp2b = _mode2b_vector() + exp2a = compute_transaction( + MODE_2A, + pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), + pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), + 0, + (0, 0), + (0, 0), + (0, 0), + ) + + tb.drive("vld", 0) + tb.drive("mode", MODE_2A) + tb.drive("a", 0) + tb.drive("b", 0) + tb.drive("b1", 0) + tb.drive("e1_a", 0) + tb.drive("e1_b0", 0) + tb.drive("e1_b1", 0) + tb.expect("vld_out", 0) + + # cycle 0: inject 2b + tb.next() + tb.drive("vld", 1) + tb.drive("mode", MODE_2B) + tb.drive("a", _to_u(a80, 80)) + tb.drive("b", _to_u(b80, 80)) + tb.drive("b1", 0) + + # cycle 1: inject 2a + tb.next() + tb.drive("vld", 1) + tb.drive("mode", MODE_2A) + tb.drive("a", _to_u(pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), 80)) + tb.drive("b", _to_u(pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), 80)) + tb.drive("b1", 0) + + # drain and check outputs on target cycles. + for _ in range(20): + tb.next() + tb.drive("vld", 0) + if tb.cycle == 5: + tb.expect("vld_out", 1) + tb.expect("out0", _to_u(exp2b.out0_19, 19)) + tb.expect("out1", _to_u(exp2b.out1_16, 16)) + if tb.cycle == 6: + tb.expect("vld_out", 1) + tb.expect("out0", _to_u(exp2a.out0_19, 19)) + + tb.finish() + + +if __name__ == "__main__": + print(compile_cycle_aware(build, name="tb_pe_int_top", eager=True, **DEFAULT_PARAMS).emit_mlir()) diff --git a/designs/PE_INT/tb_rtl/README.md b/designs/PE_INT/tb_rtl/README.md new file mode 100644 index 0000000..2714328 --- /dev/null +++ b/designs/PE_INT/tb_rtl/README.md @@ -0,0 +1,50 @@ +# RTL Test Environment (`tb_rtl`) + +This directory stores files required for **RTL simulation**, separated from `tb/` (PyCircuit testbenches). + +## Directory Layout + +- `case/`: RTL testcases (single-mode sanity + mode-switch random) +- `case/generated/`: testcase vectors and expected data generated by `model/gen_rtl_case_vectors.py` +- `tb.f`: testbench/case filelist (prefixed with absolute `$PE_INT`) +- `sim/run_all_wsl.sh`: batch-run `iverilog` / `verilator` in WSL + +## Quick Run (WSL) + +Run at repo root (e.g. `/mnt/d/git-repo/pycircuit/designs/PE_INT`): + +```bash +bash sim/run_all_wsl.sh +``` + +This script first resolves and runs: + +```bash +python3 +``` + +Then it runs simulator regressions with filelists (`filelist/pe_int.f` + `tb_rtl/tb.f`). + +## Single-Case Run Examples + +### iverilog + +```bash +export PE_INT="$(pwd)" +sed "s|\$PE_INT|${PE_INT}|g" filelist/pe_int.f > build/.pe_int.resolved.f +sed "s|\$PE_INT|${PE_INT}|g" tb_rtl/tb.f > build/.tb.resolved.f +iverilog -g2012 -s tc_mode2b_sanity -f build/.pe_int.resolved.f -f build/.tb.resolved.f -o build/tc_mode2b_sanity.out +vvp build/tc_mode2b_sanity.out +``` + +### verilator + +```bash +export PE_INT="$(pwd)" +sed "s|\$PE_INT|${PE_INT}|g" filelist/pe_int.f > build/.pe_int.resolved.f +sed "s|\$PE_INT|${PE_INT}|g" tb_rtl/tb.f > build/.tb.resolved.f +verilator --binary --timing -Wall -Wno-fatal \ + -f build/.pe_int.resolved.f -f build/.tb.resolved.f \ + --top-module tc_mode2b_sanity -o tc_mode2b_sanity +./obj_dir/tc_mode2b_sanity +``` diff --git a/designs/PE_INT/tb_rtl/case/README.md b/designs/PE_INT/tb_rtl/case/README.md new file mode 100644 index 0000000..b2fc2ff --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/README.md @@ -0,0 +1,42 @@ +# RTL Testcases (`case`) + +Each `.v` file in this directory is an independent testcase and can be compiled/simulated alone. + +## Case List and Purpose + +- `tc_mode2a_sanity.v` + - Verifies mode 2a (`S8xS8`) math correctness. + - Verifies `out1` is not unnecessarily updated in 2a mode (holds previous dual-path value). + +- `tc_mode2b_sanity.v` + - Verifies mode 2b (`S8xS4`) dual outputs `out0/out1`. + +- `tc_mode2c_sanity.v` + - Verifies mode 2c (`S5xS5 + E1`) dual outputs. + +- `tc_mode2d_sanity.v` + - Verifies mode 2d (`S8xS5`) dual outputs. + +- `tc_mode_switch_random.v` + - Verifies `vld -> vld_out` alignment/order under back-to-back mode switching. + - Verifies output values under mixed traffic (including `vld=0` gaps). + - Expected data must be traceable to reference models in `model/`. + +## Naming Convention + +- `tc_*`: directly usable as simulator top module names. +- Each case includes PASS/FAIL messages and `$fatal` for CI-friendly checks. + +## Automatic Expected Generation + +- Generator: `gen_rtl_case_vectors.py` resolved from `model/model.f` +- Output: `tb_rtl/case/generated/*.vh` +- Testcases use these generated files via `` `include ``; do not handwrite expected values. + +Manual regenerate (resolved through filelist): + +```bash +export PE_INT="$(pwd)" +sed "s|\$PE_INT|${PE_INT}|g" model/model.f > build/.model.resolved.f +python "$(awk '/gen_rtl_case_vectors\.py$/ {print; exit}' build/.model.resolved.f)" +``` diff --git a/designs/PE_INT/tb_rtl/case/common_wave_dump.vh b/designs/PE_INT/tb_rtl/case/common_wave_dump.vh new file mode 100644 index 0000000..f4163e1 --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/common_wave_dump.vh @@ -0,0 +1,27 @@ +// Common optional wave-dump hook for RTL testcases. +// Enable by runtime plusargs: +// +WAVE=1 (enable dump) +// +WAVE_FST=1 (optional, use wave.fst; default wave.vcd) +// +// Notes: +// - Requires DUT instance name to be `dut`. +// - For Verilator, binary must be built with --trace or --trace-fst. +// - For Icarus, VCD is the practical default. + +integer __wave_enable; +integer __wave_fst; + +initial begin + __wave_enable = 0; + __wave_fst = 0; + if ($value$plusargs("WAVE=%d", __wave_enable) && (__wave_enable != 0)) begin + if ($value$plusargs("WAVE_FST=%d", __wave_fst) && (__wave_fst != 0)) begin + $display("[INFO] Wave dump enabled: wave.fst"); + $dumpfile("wave.fst"); + end else begin + $display("[INFO] Wave dump enabled: wave.vcd"); + $dumpfile("wave.vcd"); + end + $dumpvars(0, dut); + end +end diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v new file mode 100644 index 0000000..607ce59 --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v @@ -0,0 +1,119 @@ +`timescale 1ns/1ps + +module tc_mode2a_sanity; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer got; + integer err; + integer i; + integer vec_idx; + + localparam integer N_CASE_2A = 1000; + localparam integer N_TX_2A = 2000; + localparam integer N_EXP_2A = 2000; + string gen_dir; + reg [79:0] pre_a [0:N_CASE_2A-1]; + reg [79:0] pre_b [0:N_CASE_2A-1]; + reg [79:0] a2a [0:N_CASE_2A-1]; + reg [79:0] b2a [0:N_CASE_2A-1]; + reg [15:0] exp_pre_o1 [0:N_CASE_2A-1]; + reg [18:0] exp_2a_o0 [0:N_CASE_2A-1]; + + localparam [1:0] MODE_2A = 2'b00; + localparam [1:0] MODE_2B = 2'b01; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (rst_n && vld_out) begin + got <= got + 1; + if (got >= N_EXP_2A) begin + $display("[ERR][2a] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); + err <= err + 1; + end else begin + vec_idx = got >> 1; + if ((got & 1) == 0) begin + if (out1 !== exp_pre_o1[vec_idx]) begin + $display("[ERR][2a] idx=%0d preload out1 mismatch got=%0d exp=%0d", + vec_idx, $signed(out1), $signed(exp_pre_o1[vec_idx])); + err <= err + 1; + end + end else begin + if (out0 !== exp_2a_o0[vec_idx]) begin + $display("[ERR][2a] idx=%0d out0 mismatch got=%0d exp=%0d", + vec_idx, $signed(out0), $signed(exp_2a_o0[vec_idx])); + err <= err + 1; + end + if (out1 !== exp_pre_o1[vec_idx]) begin + $display("[ERR][2a] idx=%0d out1 hold mismatch got=%0d exp=%0d", + vec_idx, $signed(out1), $signed(exp_pre_o1[vec_idx])); + err <= err + 1; + end + end + end + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2a_sanity_pre_a.mem"}, pre_a); + $readmemh({gen_dir, "/tc_mode2a_sanity_pre_b.mem"}, pre_b); + $readmemh({gen_dir, "/tc_mode2a_sanity_a2a.mem"}, a2a); + $readmemh({gen_dir, "/tc_mode2a_sanity_b2a.mem"}, b2a); + $readmemh({gen_dir, "/tc_mode2a_sanity_exp_pre_o1.mem"}, exp_pre_o1); + $readmemh({gen_dir, "/tc_mode2a_sanity_exp_2a_o0.mem"}, exp_2a_o0); + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_CASE_2A; i = i + 1) begin + @(negedge clk); + vld = 1; mode = MODE_2B; a = pre_a[i]; b = pre_b[i]; b1 = 0; + @(negedge clk); + vld = 1; mode = MODE_2A; a = a2a[i]; b = b2a[i]; b1 = 0; + end + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; + + repeat (12) @(posedge clk); + + if (got !== N_EXP_2A) begin + $display("[ERR][2a] expected %0d outputs, got %0d", N_EXP_2A, got); + err = err + 1; + end + + if (err == 0) begin + $display("[PASS] tc_mode2a_sanity"); + end else begin + $fatal(1, "[FAIL] tc_mode2a_sanity err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v new file mode 100644 index 0000000..f9708fc --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v @@ -0,0 +1,95 @@ +`timescale 1ns/1ps + +module tc_mode2b_sanity; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer got; + integer err; + integer i; + + localparam integer N_TX_2B = 1000; + localparam integer N_EXP_2B = 1000; + string gen_dir; + reg [79:0] tx_a [0:N_TX_2B-1]; + reg [79:0] tx_b [0:N_TX_2B-1]; + reg [18:0] exp_o0 [0:N_EXP_2B-1]; + reg [15:0] exp_o1 [0:N_EXP_2B-1]; + + localparam [1:0] MODE_2B = 2'b01; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (rst_n && vld_out) begin + got <= got + 1; + if (got >= N_EXP_2B) begin + $display("[ERR][2b] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); + err <= err + 1; + end else if (out0 !== exp_o0[got] || out1 !== exp_o1[got]) begin + $display("[ERR][2b] idx=%0d out0=%0d out1=%0d exp=(%0d,%0d)", + got, $signed(out0), $signed(out1), $signed(exp_o0[got]), $signed(exp_o1[got])); + err <= err + 1; + end + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2b_sanity_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2b_sanity_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode2b_sanity_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2b_sanity_exp_o1.mem"}, exp_o1); + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX_2B; i = i + 1) begin + @(negedge clk); + vld = 1; mode = MODE_2B; a = tx_a[i]; b = tx_b[i]; b1 = 0; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; + + repeat (10) @(posedge clk); + + if (got !== N_EXP_2B) begin + $display("[ERR][2b] expected %0d outputs, got %0d", N_EXP_2B, got); + err = err + 1; + end + + if (err == 0) begin + $display("[PASS] tc_mode2b_sanity"); + end else begin + $fatal(1, "[FAIL] tc_mode2b_sanity err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v new file mode 100644 index 0000000..961dfdd --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v @@ -0,0 +1,104 @@ +`timescale 1ns/1ps + +module tc_mode2c_sanity; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer got; + integer err; + integer i; + + localparam integer N_TX_2C = 1000; + localparam integer N_EXP_2C = 1000; + string gen_dir; + reg [79:0] tx_a [0:N_TX_2C-1]; + reg [79:0] tx_b0 [0:N_TX_2C-1]; + reg [79:0] tx_b1 [0:N_TX_2C-1]; + reg [1:0] tx_e1a [0:N_TX_2C-1]; + reg [1:0] tx_e1b0 [0:N_TX_2C-1]; + reg [1:0] tx_e1b1 [0:N_TX_2C-1]; + reg [18:0] exp_o0 [0:N_EXP_2C-1]; + reg [15:0] exp_o1 [0:N_EXP_2C-1]; + + localparam [1:0] MODE_2C = 2'b10; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (rst_n && vld_out) begin + got <= got + 1; + if (got >= N_EXP_2C) begin + $display("[ERR][2c] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); + err <= err + 1; + end else if (out0 !== exp_o0[got] || out1 !== exp_o1[got]) begin + $display("[ERR][2c] idx=%0d out0=%0d out1=%0d exp=(%0d,%0d)", + got, $signed(out0), $signed(out1), $signed(exp_o0[got]), $signed(exp_o1[got])); + err <= err + 1; + end + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_b0.mem"}, tx_b0); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_b1.mem"}, tx_b1); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_e1a.mem"}, tx_e1a); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_e1b0.mem"}, tx_e1b0); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_e1b1.mem"}, tx_e1b1); + $readmemh({gen_dir, "/tc_mode2c_sanity_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2c_sanity_exp_o1.mem"}, exp_o1); + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX_2C; i = i + 1) begin + @(negedge clk); + vld = 1; mode = MODE_2C; a = tx_a[i]; b = tx_b0[i]; b1 = tx_b1[i]; + e1_a = tx_e1a[i]; e1_b0 = tx_e1b0[i]; e1_b1 = tx_e1b1[i]; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (10) @(posedge clk); + + if (got !== N_EXP_2C) begin + $display("[ERR][2c] expected %0d outputs, got %0d", N_EXP_2C, got); + err = err + 1; + end + + if (err == 0) begin + $display("[PASS] tc_mode2c_sanity"); + end else begin + $fatal(1, "[FAIL] tc_mode2c_sanity err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v new file mode 100644 index 0000000..f49eb52 --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v @@ -0,0 +1,95 @@ +`timescale 1ns/1ps + +module tc_mode2d_sanity; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer got; + integer err; + integer i; + + localparam integer N_TX_2D = 1000; + localparam integer N_EXP_2D = 1000; + string gen_dir; + reg [79:0] tx_a [0:N_TX_2D-1]; + reg [79:0] tx_b [0:N_TX_2D-1]; + reg [18:0] exp_o0 [0:N_EXP_2D-1]; + reg [15:0] exp_o1 [0:N_EXP_2D-1]; + + localparam [1:0] MODE_2D = 2'b11; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (rst_n && vld_out) begin + got <= got + 1; + if (got >= N_EXP_2D) begin + $display("[ERR][2d] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); + err <= err + 1; + end else if (out0 !== exp_o0[got] || out1 !== exp_o1[got]) begin + $display("[ERR][2d] idx=%0d out0=%0d out1=%0d exp=(%0d,%0d)", + got, $signed(out0), $signed(out1), $signed(exp_o0[got]), $signed(exp_o1[got])); + err <= err + 1; + end + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2d_sanity_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2d_sanity_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode2d_sanity_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2d_sanity_exp_o1.mem"}, exp_o1); + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX_2D; i = i + 1) begin + @(negedge clk); + vld = 1; mode = MODE_2D; a = tx_a[i]; b = tx_b[i]; b1 = 0; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; + + repeat (10) @(posedge clk); + + if (got !== N_EXP_2D) begin + $display("[ERR][2d] expected %0d outputs, got %0d", N_EXP_2D, got); + err = err + 1; + end + + if (err == 0) begin + $display("[PASS] tc_mode2d_sanity"); + end else begin + $fatal(1, "[FAIL] tc_mode2d_sanity err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v b/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v new file mode 100644 index 0000000..6b26ad1 --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v @@ -0,0 +1,120 @@ +`timescale 1ns/1ps + +module tc_mode_switch_random; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer i; + integer got; + integer err; + integer exp_count; + localparam integer N_TX = 1000; + localparam integer N_EXP_MAX = 1000; + string gen_dir; + reg [31:0] meta [0:0]; + + reg tx_vld [0:N_TX-1]; + reg [1:0] tx_mode [0:N_TX-1]; + reg [79:0] tx_a [0:N_TX-1]; + reg [79:0] tx_b [0:N_TX-1]; + reg [79:0] tx_b1 [0:N_TX-1]; + reg [1:0] tx_e1a [0:N_TX-1]; + reg [1:0] tx_e1b0 [0:N_TX-1]; + reg [1:0] tx_e1b1 [0:N_TX-1]; + + reg [18:0] exp_o0 [0:N_EXP_MAX-1]; + reg [15:0] exp_o1 [0:N_EXP_MAX-1]; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (rst_n && vld_out) begin + if (got >= exp_count) begin + $display("[ERR][rand] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); + err <= err + 1; + end else begin + if (out0 !== exp_o0[got] || out1 !== exp_o1[got]) begin + $display("[ERR][rand] idx=%0d got(out0,out1)=(%0d,%0d) exp=(%0d,%0d)", + got, $signed(out0), $signed(out1), $signed(exp_o0[got]), $signed(exp_o1[got])); + err <= err + 1; + end + end + got <= got + 1; + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; + exp_count = 0; + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode_switch_random_tx_vld.mem"}, tx_vld); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_mode.mem"}, tx_mode); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_b1.mem"}, tx_b1); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_e1a.mem"}, tx_e1a); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_e1b0.mem"}, tx_e1b0); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_e1b1.mem"}, tx_e1b1); + $readmemh({gen_dir, "/tc_mode_switch_random_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode_switch_random_exp_o1.mem"}, exp_o1); + $readmemh({gen_dir, "/tc_mode_switch_random_meta.mem"}, meta); + exp_count = meta[0]; + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX; i = i + 1) begin + @(negedge clk); + vld = tx_vld[i]; + mode = tx_mode[i]; + a = tx_a[i]; + b = tx_b[i]; + b1 = tx_b1[i]; + e1_a = tx_e1a[i]; + e1_b0 = tx_e1b0[i]; + e1_b1 = tx_e1b1[i]; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (30) @(posedge clk); + + if (got !== exp_count) begin + $display("[ERR][rand] expected %0d outputs, got %0d", exp_count, got); + err = err + 1; + end + + if (err == 0) begin + $display("[PASS] tc_mode_switch_random"); + end else begin + $fatal(1, "[FAIL] tc_mode_switch_random err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/tb.f b/designs/PE_INT/tb_rtl/tb.f new file mode 100644 index 0000000..7311afc --- /dev/null +++ b/designs/PE_INT/tb_rtl/tb.f @@ -0,0 +1,6 @@ ++incdir+$PE_INT/tb_rtl/case +$PE_INT/tb_rtl/case/tc_mode2a_sanity.v +$PE_INT/tb_rtl/case/tc_mode2b_sanity.v +$PE_INT/tb_rtl/case/tc_mode2c_sanity.v +$PE_INT/tb_rtl/case/tc_mode2d_sanity.v +$PE_INT/tb_rtl/case/tc_mode_switch_random.v From d71d17e3b43a7026f7442e8e1bc0f54eaaf2ba32 Mon Sep 17 00:00:00 2001 From: HenryLee Date: Tue, 5 May 2026 17:47:48 +0800 Subject: [PATCH 02/10] feat(designs): add PE_INT verification baseline Baseline the refreshed PE_INT PyCircuit design, generated RTL, model, RTL test environment, testcase suite, and supporting debug skills after full regression passed. --- agents/skill/pe_int/SKILL.md | 48 + .../expression-width-mismatch-debug/SKILL.md | 76 + .../module-output-protocol-debug/SKILL.md | 87 + .../skills/pe-int-implementation/SKILL.md | 159 +- .../skills/pe-int-pycircuiteval-flow/SKILL.md | 291 +- designs/PE_INT/.gitignore | 3 + designs/PE_INT/README.md | 13 +- designs/PE_INT/docs/design_spec.md | 313 +- designs/PE_INT/docs/spec.md | 371 +-- designs/PE_INT/filelist/pe_int.f | 4 +- designs/PE_INT/memory.md | 6 +- designs/PE_INT/model/README.md | 44 +- designs/PE_INT/model/gen_rtl_case_vectors.py | 292 +- designs/PE_INT/model/pe_int_pycircuit_eval.py | 100 +- designs/PE_INT/model/ref_model.py | 41 +- designs/PE_INT/python/build.py | 186 +- designs/PE_INT/python/pe_int/__init__.py | 3 +- designs/PE_INT/python/pe_int/constants.py | 3 +- designs/PE_INT/python/pe_int/lane_mac.py | 21 +- designs/PE_INT/python/pe_int/mac_modes.py | 50 +- designs/PE_INT/python/pe_int/top.py | 175 +- designs/PE_INT/python/pe_int_pycircuit.py | 5 +- designs/PE_INT/rtl/README.md | 44 +- designs/PE_INT/rtl/build/pe_int_l3.v | 2533 +++++++++++++++++ .../PE_INT/rtl/{ => build}/pyc_primitives.v | 1266 ++++---- designs/PE_INT/rtl/pe_int_l3.v | 171 -- designs/PE_INT/sim/README.md | 98 +- designs/PE_INT/sim/run_all_wsl.sh | 67 +- designs/PE_INT/sim/run_sim.sh | 167 +- designs/PE_INT/tb/README.md | 28 +- designs/PE_INT/tb/tb_pe_int_pycircuit.py | 244 +- .../PE_INT/tb/tb_pe_int_pycircuit_2a_wave.py | 87 + designs/PE_INT/tb_rtl/README.md | 100 +- designs/PE_INT/tb_rtl/case/README.md | 84 +- .../case/common_exact_latency_scoreboard.vh | 92 + designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v | 223 +- .../case/tc_mode2a_sanity_rand_timing.v | 108 + designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v | 181 +- .../case/tc_mode2b_sanity_rand_timing.v | 108 + designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v | 198 +- .../case/tc_mode2c_sanity_rand_timing.v | 108 + designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v | 181 +- .../case/tc_mode2d_sanity_rand_timing.v | 108 + .../tb_rtl/case/tc_mode_switch_random.v | 26 +- designs/PE_INT/tb_rtl/tb.f | 4 + 45 files changed, 5999 insertions(+), 2518 deletions(-) create mode 100644 agents/skill/pe_int/SKILL.md create mode 100644 agents/skill/pe_int/expression-width-mismatch-debug/SKILL.md create mode 100644 agents/skill/pe_int/module-output-protocol-debug/SKILL.md create mode 100644 designs/PE_INT/rtl/build/pe_int_l3.v rename designs/PE_INT/rtl/{ => build}/pyc_primitives.v (96%) delete mode 100644 designs/PE_INT/rtl/pe_int_l3.v create mode 100644 designs/PE_INT/tb/tb_pe_int_pycircuit_2a_wave.py create mode 100644 designs/PE_INT/tb_rtl/case/common_exact_latency_scoreboard.vh create mode 100644 designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v create mode 100644 designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v create mode 100644 designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v create mode 100644 designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v diff --git a/agents/skill/pe_int/SKILL.md b/agents/skill/pe_int/SKILL.md new file mode 100644 index 0000000..a996865 --- /dev/null +++ b/agents/skill/pe_int/SKILL.md @@ -0,0 +1,48 @@ +--- +name: pipeline-latency-depth-guard +description: Checks latency consistency and stage logic-depth reasonableness for pipelined hardware designs. Use when editing stage boundaries, valid/data alignment, pipeline partitioning, or latency/depth contracts. +--- + +# Pipeline Latency and Depth Guard + +## 1) Latency Definition Must Be Explicit +- Define latency convention before implementation (0-based or 1-based). +- Define clear reference points (for example: input sample -> output commit). +- If ambiguous, stop and ask user to clarify. + +## 2) Contract Consistency Before Coding +Do this before implementation: +1. Read the latency contract in functional spec. +2. Read the stage contract in design spec. +3. Confirm both use the same semantics. +4. If mismatch exists, fix docs first. + +## 3) Real-Path Latency Validation +- Validate latency by counting real register boundaries on generated RTL signal paths. +- Never infer latency from stage names, comments, or signal naming only. +- Validate at least: + - control path (`valid` or equivalent handshake) + - each committed output datapath + +## 4) Commit-Point Alignment +- Control qualifier and committed outputs must come from the same transaction boundary. +- Avoid cross-stage mixing (early control with later data, or vice versa). +- Hold/stall policy updates must align with output commit control point. + +## 5) Logic-Depth Guidance (Guideline, Not Hard Constraint) +- Stage logic-depth target is around 25 layers. +- Merging multiple combinational blocks into one stage is allowed. +- After any merge/partition change, re-check stage logic depth. + +Decision policy: +- `<= 25`: within target, no action needed. +- `26 ~ 30`: acceptable as guideline overflow; must warn user and suggest optional repartition. +- `> 30`: strong risk; propose repartition or structural optimization and request user decision. + +## 6) Definition of Done (DoD) +- [ ] Latency convention is explicitly documented. +- [ ] Functional spec and design spec latency semantics are consistent. +- [ ] Real RTL path register-count evidence is provided. +- [ ] Stage logic depth check is recorded (including warning if 26~30). +- [ ] Regression/simulation passes. +- [ ] No transaction reorder under continuous valid traffic. diff --git a/agents/skill/pe_int/expression-width-mismatch-debug/SKILL.md b/agents/skill/pe_int/expression-width-mismatch-debug/SKILL.md new file mode 100644 index 0000000..3d3e934 --- /dev/null +++ b/agents/skill/pe_int/expression-width-mismatch-debug/SKILL.md @@ -0,0 +1,76 @@ +--- +name: expression-width-mismatch-debug +description: Debugs arithmetic expression width mismatches in RTL, PyCircuit, HLS, and generated hardware. Use when arithmetic results differ from the model, shifts/scales behave incorrectly, small-bit operands overflow unexpectedly, or generated RTL inferred narrower intermediate widths than intended. +--- + +# Expression Width Mismatch Debug + +## Trigger + +Use this when: + +- RTL arithmetic differs from the Python/C golden model. +- Only specific modes, scale factors, shift paths, or boundary values fail. +- Failures are value-only after timing, latency, and valid/data alignment are proven correct. +- Results differ by scale factors such as `x1/x2/x4`. +- Small expressions such as `1-bit + 1-bit`, shifts, masks, sign extension, or zero extension are involved. + +## Debug Flow + +1. Rule out timing first. + - Confirm output protocol, latency, and scoreboard math are correct. + - Confirm valid/control and data outputs describe the same transaction. + - If timing is wrong, use a protocol/alignment debug flow before this skill. + +2. Reduce to the first failing transaction. + - Freeze seed and vector files. + - Extract mode, operands, control fields, expected output, and actual output. + - Prefer a one-vector or ten-vector testcase with waveform enabled. + +3. Compute model intermediate values. + - Decode operands. + - Compute partial products. + - Compute reductions. + - Compute shift/control values. + - Compute final scaled/muxed outputs. + +4. Compare RTL internal signals. + - Probe decoded operands, partial sums, shift amounts, scaled values, and final output mux inputs. + - Find the first intermediate signal where RTL diverges from the model. + +5. Inspect expression widths. + - Check generated RTL declarations for intermediate wire widths. + - Check whether operands were sign-extended or zero-extended before arithmetic. + - Check whether constants were inferred too narrow. + - Remember that hardware DSLs may keep `1-bit + 1-bit` as a 1-bit result unless explicitly extended. + +6. Fix the narrowest incorrect expression. + - For signed data arithmetic, sign-extend before multiply/add. + - For control, shift, mask, and index arithmetic, zero-extend before add/compare/shift selection. + - Do not add arbitrary extra margin; choose the minimum width that covers the specified scenarios. + +## Common Pattern + +Bad pattern: + +```text +shift = e1_a_bit + e1_b_bit +``` + +If both operands are 1-bit hardware values, `1 + 1` may overflow to `0`. + +Preferred pattern: + +```text +shift = zext(e1_a_bit, 2) + zext(e1_b_bit, 2) +``` + +This covers shift values `{0,1,2}` without extra margin. + +## Done Criteria + +- First failing transaction matches the model at every inspected intermediate point. +- Generated RTL shows intended intermediate widths. +- Boundary cases for carry, sign bit, max shift, and min/max operands pass. +- Focused testcase passes. +- Full affected regression passes. diff --git a/agents/skill/pe_int/module-output-protocol-debug/SKILL.md b/agents/skill/pe_int/module-output-protocol-debug/SKILL.md new file mode 100644 index 0000000..3ad976d --- /dev/null +++ b/agents/skill/pe_int/module-output-protocol-debug/SKILL.md @@ -0,0 +1,87 @@ +--- +name: module-output-protocol-debug +description: Debugs hardware module output protocol violations. Use when module outputs do not match the waveform protocol described by the spec, including latency, valid/data alignment, hold behavior, handshake timing, output stability, or transaction ordering issues. +--- + +# Module Output Protocol Debug + +## Trigger + +Use this when a module's observed output waveform does not comply with its specified output protocol, including: + +- Output latency mismatch. +- Valid, ready, enable, or control signal timing mismatch. +- Data and qualifier signals not committed at the same transaction boundary. +- Output hold or stability policy violation. +- Unexpected output toggling. +- Missing, early, late, or reordered output transaction. +- Scoreboard reports protocol-like errors such as `unexpected valid`, `missing valid`, or a consistent cycle offset. + +## Required Spec Contract + +Before debugging, check whether the corresponding spec describes the waveform protocol. + +The spec should define, when applicable: + +- Input sampling point. +- Output commit point. +- Latency convention, for example `input sampled at t0 -> output valid at t0 + L`. +- Which output signals must be aligned. +- Valid, ready, and enable semantics. +- Output hold or stability policy. +- Reset behavior. +- Transaction ordering rules. + +If the spec does not define the waveform protocol clearly, stop. Do not edit any spec from this debug flow. Ask the user to clarify the design intent and to update the upstream spec source before continuing. + +## Debug Flow + +1. Check the spec first. + - Find the latency and waveform protocol description. + - Confirm the latency counting convention. + - Confirm which signals are required to be aligned or stable. + - If the spec is ambiguous, stop and ask the user for the design intent. + - Do not modify `design_spec.md`, generated specs, or their source specs in this debug flow. + - Ask the user to update the upstream source spec and regenerate derived specs before continuing. + +2. Use waveform evidence to identify the violating signal. + - Generate a small waveform case, preferably 1 to 10 transactions. + - Mark the first accepted input transaction. + - Mark the expected output cycle from the spec. + - Compare each output and control signal against the spec. + - Classify the violation by signal, not by assumption. + +3. Separate possible causes. + - If DUT waveform matches spec but scoreboard fails, debug the testbench or scoreboard. + - If a control or valid signal violates spec, debug the control path. + - If a data signal violates spec, debug the datapath. + - If only a hold or stability rule fails, debug the output update policy. + - If ordering fails, debug transaction queueing or pipeline alignment. + +4. Count real RTL register paths. + - Count registers on each violating signal path. + - Count control and data paths separately. + - Do not infer latency from signal names, comments, or stage labels. + - In generated RTL, look for hidden balance registers such as `_v5_bal_*`. + +5. Fix only the violating path. + - Do not delay or alter signals that already match the spec. + - If `valid` matches the spec but data is late, fix the data path. + - If data matches the spec but `valid` is early or late, fix the control path. + - If the scoreboard has the wrong latency convention, fix the scoreboard, not the DUT. + +6. Re-verify with waveform first. + - Re-run the small waveform case. + - Confirm all protocol signals match the spec. + - Then run focused regression. + - Then run full regression. + +## Done Criteria + +- Spec contains a clear waveform protocol before implementation/debug fixes proceed. +- Any spec ambiguity was clarified by the user and resolved outside this debug flow. +- Waveform shows all output signals comply with the spec. +- Real RTL path register counts support the observed latency. +- Scoreboard latency convention matches the spec. +- Focused waveform test passes. +- Full regression passes. diff --git a/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md index 674509c..f5b6b0e 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md @@ -1,78 +1,81 @@ ---- -name: pe-int-implementation -description: Project-level implementation guidance for PE_INT. Use for PE_INT coding choices, pipeline structure, latency alignment, power/area trade-offs, and debug order. ---- - -# PE_INT Implementation Guidance (Non-Formal) - -This is a project skill for implementation intent and practical trade-offs. -It does **not** override frozen rules in `docs/spec.md`. -If there is any conflict, `docs/spec.md` wins. - -## Hard Rule: RTL Source Ownership - -1. Deliverable RTL must be generated from PyCircuit source through `pycircuit.cli build` / `pycc`. -2. Do not accept model-generated RTL as deliverable output. -3. Do not hand-edit generated RTL for final delivery. -4. If spec is ambiguous, ask the user for clarification before changing behavior. - -## Fixed Debug SOP (Seed -> Model -> PyCircuit -> RTL) - -When any testcase fails, follow this order: - -1. Record failing seed, testcase, and simulator. -2. Reproduce with the same seed and regenerate vectors. -3. Run model checks first; if model fails, fix model/spec alignment first. -4. If model passes, run PyCircuit checks. -5. If PyCircuit fails, fix `python/` and rebuild RTL. -6. Only debug RTL-level issues after model and PyCircuit both pass. -7. Re-verify failing case first, then run full regression. - -Use `pass/fail` wording in reports. - -## Regression Notes - -- Sanity and random vectors are seed-dependent and reproducible. -- Runtime vector loading (`$readmemh` + `+GEN_DIR`) is preferred over compile-time baked expected data. -- Default output paths: - - logs: `sim/logs/` - - waves: `sim/waves/` - -## `vld` to `vld_out` and Pipeline Depth - -- Enforce one-to-one mapping from sampled `vld` to `vld_out`. -- Keep fixed latency `L` across all modes. -- Keep internal pipeline stage count identical across all modes. -- Use full pipeline datapath; no independent FIFOs for reordering. - -## Power and Area Priority - -After functionality and logic-depth constraints are satisfied: - -1. Reduce dynamic power as primary priority. -2. Reduce area as secondary priority. - -If area and dynamic power conflict, prioritize dynamic power. - -## PyCircuit Structure Requirements - -1. Stage boundaries must be explicit and reviewable. -2. Keep submodules split into separate files. -3. Keep each submodule core logic around 200 lines or less when possible. -4. Keep top-level focused on stage orchestration and alignment. -5. Control and datapath must advance at matching stage depth. - -## Mandatory Stage Coding Contract - -Top-level coding must be explicit: - -`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> combN -> regN -> output` - -Rules: - -1. Stage boundaries must be visible at top-level. -2. Each stage must define combinational work before register transfer. -3. Datapath and control-path must both be reviewable per stage. -4. `vld/mode/enable/select` control signals must stay aligned with payload. -5. Do not hide full pipeline register chains inside opaque helper loops. - +--- +name: pe-int-implementation +description: Project-level implementation guidance for PE_INT. Use for PE_INT coding choices, pipeline structure, latency alignment, power/area trade-offs, and debug order. +--- + +# PE_INT Implementation Guidance (Non-Formal) + +This is a project skill for implementation intent and practical trade-offs. +It does **not** override frozen rules in `docs/spec.md`. +If there is any conflict, `docs/spec.md` wins. + +## Hard Rule: RTL Source Ownership + +1. Deliverable RTL must be generated from PyCircuit source through `pycircuit.cli build` / `pycc`. +2. Do not accept model-generated RTL as deliverable output. +3. Do not hand-edit generated RTL for final delivery. +4. If spec is ambiguous, ask the user for clarification before changing behavior. + +## Fixed Debug SOP (Seed -> Model -> PyCircuit -> RTL) + +When any testcase fails, follow this order: + +1. Record failing seed, testcase, and simulator. +2. Reproduce with the same seed and regenerate vectors. +3. Run model checks first; if model fails, fix model/spec alignment first. +4. If model passes, run PyCircuit checks. +5. If PyCircuit fails, fix `python/` and rebuild RTL. +6. Only debug RTL-level issues after model and PyCircuit both pass. +7. Re-verify failing case first, then run full regression. + +Use `pass/fail` wording in reports. + +## Regression Notes + +- Sanity and random vectors are seed-dependent and reproducible. +- Runtime vector loading (`$readmemh` + `+GEN_DIR`) is preferred over compile-time baked expected data. +- Default output paths: + - logs: `sim/logs/` + - waves: `sim/waves/` + +## `vld` to `vld_out` and Pipeline Depth + +- Enforce one-to-one mapping from sampled `vld` to `vld_out`. +- Keep fixed latency `L` across all modes. +- Keep internal pipeline stage count identical across all modes. +- Use full pipeline datapath; no independent FIFOs for reordering. +- Latency must be measured by **actual register count on real paths** (control and data), + not by stage naming conventions. +- Always verify `vld_out` path and `out0/out1` paths separately, then check alignment. + +## Power and Area Priority + +After functionality and logic-depth constraints are satisfied: + +1. Reduce dynamic power as primary priority. +2. Reduce area as secondary priority. + +If area and dynamic power conflict, prioritize dynamic power. + +## PyCircuit Structure Requirements + +1. Stage boundaries must be explicit and reviewable. +2. Keep submodules split into separate files. +3. Keep each submodule core logic around 200 lines or less when possible. +4. Keep top-level focused on stage orchestration and alignment. +5. Control and datapath must advance at matching stage depth. + +## Mandatory Stage Coding Contract + +Top-level coding must be explicit: + +`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> combN -> regN -> output` + +Rules: + +1. Stage boundaries must be visible at top-level. +2. Each stage must define combinational work before register transfer. +3. Datapath and control-path must both be reviewable per stage. +4. `vld/mode/enable/select` control signals must stay aligned with payload. +5. Do not hide full pipeline register chains inside opaque helper loops. + diff --git a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md index 95c7a0f..04fbde6 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md @@ -1,138 +1,153 @@ ---- -name: pe-int-pycircuiteval-flow -description: Unified PE_INT flow using PyCircuitEval. Use when implementing PE_INT from spec, generating RTL from PyCircuit, and running model/tb/tb_rtl validation. ---- - -# PE_INT x PyCircuitEval Unified Flow - -This skill standardizes PE_INT flow across sessions and machines: - -- Single spec source: `docs/spec.md` -- Implementation language: PyCircuit frontend -- Deliverable RTL source: PyCircuit build (`pycircuit.cli build` / `pycc`) -- Verification layers: - - `model/`: golden/reference and model regressions - - `tb/`: PyCircuit test flow - - `tb_rtl/`: RTL-specific simulation flow - -## 0) When to Use - -Enable this skill when the user asks to: - -- implement PE_INT from `spec.md` -- generate RTL from PyCircuit source -- add testbench/regression coverage -- reproduce PE_INT flow on another machine - -## 1) Source-of-Truth and Forbidden Actions - -1. `docs/spec.md` is the only behavior contract. -2. Do not handwrite deliverable RTL. -3. Do not accept model-generated RTL as final deliverable. -4. If implementation conflicts with spec, fix implementation (do not silently rewrite spec). - -## 2) Fallback If Profile Is Missing - -If no existing PyCircuitEval profile is available on a fresh machine/session: - -1. Learn latest PyCircuit flow from `LinxISA/pyCircuit`. -2. Confirm understanding of: - - module/circuit structure - - `pycircuit.cli build` / `pycc` flow - - minimal device+tb compile/run pattern -3. Then start PE_INT implementation. - -## 3) Standard PE_INT Flow (Fixed Order) - -### Step A: Spec Checklist - -Extract executable checks from `docs/spec.md`: - -- top-level ports and widths -- mode 2a/2b/2c/2d math semantics -- fixed `vld -> vld_out` mapping and latency -- cross-mode stage consistency -- mode-2a `out1` stability policy - -### Step B: Implement in PyCircuit, Then Build RTL - -1. Implement in `python/`. -2. Build through `pycircuit.cli build` / `pycc`. -3. Keep generated RTL in `rtl/`; do not manually patch final RTL. - -### Step B.1: PyCircuit Structure Rules - -1. Keep pipeline stage boundaries explicit (`*_s0/*_s1/...` style). -2. Keep submodules separated under `python/pe_int/`. -3. Keep submodule core logic around 200 lines or less when practical. -4. Keep top-level focused on stage connection/alignment. -5. Keep control-path and datapath depth-aligned. - -### Step B.2: Mandatory Stage Contract - -Top-level must be reviewable as: - -`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> output` - -No hidden full register-chain helper loops. - -### Step C: Build Verification Assets - -- `model/`: math + timing model regression -- `tb/`: PyCircuit testbench comparison flow -- Validate: - - one-to-one valid mapping - - fixed latency and cross-mode consistency - - no bubble under full-pipeline working window - -### Step D (Optional): RTL Simulator Validation - -Only run this step after user confirms explicitly: - -1. Build RTL from PyCircuit source. -2. Run `tb_rtl/` testcases on both `iverilog` and `verilator`. -3. Report pass/fail and key outputs. - -## 4) Current Vector Baseline - -Current project baseline: - -- `tc_mode2a_sanity`: 1000 -- `tc_mode2b_sanity`: 1000 -- `tc_mode2c_sanity`: 1000 -- `tc_mode2d_sanity`: 1000 -- `tc_mode_switch_random`: 1000 - -Simulation script baseline: - -- multi-seed runs supported (default 10) -- runtime vector loading via `+GEN_DIR` -- logs: `sim/logs//...` -- waves: `sim/waves//...` - -## 5) Acceptance Checklist - -All of the following must pass: - -1. PyCircuit source can reproducibly rebuild RTL. -2. Deliverable RTL is generated by PyCircuit/pycc, not handwritten. -3. `model/` and `tb/` regressions pass. -4. README documents: - - build commands - - test commands - - fixed latency/alignment behavior - -If optional Step D is approved: - -- `tb_rtl/` testcases run successfully -- `iverilog` passes -- `verilator` passes - -## 6) Fixed Debug SOP - -On fail, always use: - -`Seed -> Model -> PyCircuit -> RTL` - -No step skipping. - +--- +name: pe-int-pycircuiteval-flow +description: Unified PE_INT flow using PyCircuitEval. Use when implementing PE_INT from spec, generating RTL from PyCircuit, and running model/tb/tb_rtl validation. +--- + +# PE_INT x PyCircuitEval Unified Flow + +This skill standardizes PE_INT flow across sessions and machines: + +- Single spec source: `docs/spec.md` +- Implementation language: PyCircuit frontend +- Deliverable RTL source: PyCircuit build (`pycircuit.cli build` / `pycc`) +- Verification layers: + - `model/`: golden/reference and model regressions + - `tb/`: PyCircuit test flow + - `tb_rtl/`: RTL-specific simulation flow + +## 0) When to Use + +Enable this skill when the user asks to: + +- implement PE_INT from `spec.md` +- generate RTL from PyCircuit source +- add testbench/regression coverage +- reproduce PE_INT flow on another machine + +## 1) Source-of-Truth and Forbidden Actions + +1. `docs/spec.md` is the only behavior contract. +2. Do not handwrite deliverable RTL. +3. Do not accept model-generated RTL as final deliverable. +4. If implementation conflicts with spec, fix implementation (do not silently rewrite spec). + +## 2) Fallback If Profile Is Missing + +If no existing PyCircuitEval profile is available on a fresh machine/session: + +1. Learn latest PyCircuit flow from `LinxISA/pyCircuit`. +2. Confirm understanding of: + - module/circuit structure + - `pycircuit.cli build` / `pycc` flow + - minimal device+tb compile/run pattern +3. Then start PE_INT implementation. + +## 3) Standard PE_INT Flow (Fixed Order) + +### Step A: Spec Checklist + +Extract executable checks from `docs/spec.md`: + +- top-level ports and widths +- mode 2a/2b/2c/2d math semantics +- fixed `vld -> vld_out` mapping and latency +- cross-mode stage consistency +- mode-2a `out1` stability policy + +### Step B: Implement in PyCircuit, Then Build RTL + +1. Implement in `python/`. +2. Build through `pycircuit.cli build` / `pycc`. +3. After each build, sync deliverable RTL artifacts from the build output tree into `rtl/build/`. +4. Refresh `filelist/pe_int.f` after each sync so simulations consume the latest deliverable set. +5. Do not manually patch final RTL deliverables. + +### Step B.1: PyCircuit Structure Rules + +1. Keep pipeline stage boundaries explicit (`*_s0/*_s1/...` style). +2. Keep submodules separated under `python/pe_int/`. +3. Keep submodule core logic around 200 lines or less when practical. +4. Keep top-level focused on stage connection/alignment. +5. Keep control-path and datapath depth-aligned. + +### Step B.2: Mandatory Stage Contract + +Top-level must be reviewable as: + +`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> output` + +No hidden full register-chain helper loops. + +### Step C: Build Verification Assets + +- `model/`: math + timing model regression +- `tb/`: PyCircuit testbench comparison flow +- Validate: + - one-to-one valid mapping + - fixed latency and cross-mode consistency + - no bubble under full-pipeline working window + +### Step C.1: Latency Counting Rule (Mandatory) + +When checking latency / stage counts, always count the **actual number of +registers on the real signal path** in generated RTL. + +Do **not** infer latency only from stage naming (`s0/s1/...`) or comment labels. + +Required checks: + +1. Count register depth separately for control (`vld_out`) and data (`out0/out1`). +2. Confirm control/data path depths are aligned at output boundary. +3. If mismatch exists, report effective latency based on register count. + +### Step D (Optional): RTL Simulator Validation + +Only run this step after user confirms explicitly: + +1. Build RTL from PyCircuit source. +2. Run `tb_rtl/` testcases on both `iverilog` and `verilator`. +3. Report pass/fail and key outputs. + +## 4) Current Vector Baseline + +Current project baseline: + +- `tc_mode2a_sanity`: 1000 +- `tc_mode2b_sanity`: 1000 +- `tc_mode2c_sanity`: 1000 +- `tc_mode2d_sanity`: 1000 +- `tc_mode_switch_random`: 1000 + +Simulation script baseline: + +- multi-seed runs supported (default 10) +- runtime vector loading via `+GEN_DIR` +- logs: `sim/logs//...` +- waves: `sim/waves//...` + +## 5) Acceptance Checklist + +All of the following must pass: + +1. PyCircuit source can reproducibly rebuild RTL. +2. Deliverable RTL is generated by PyCircuit/pycc, not handwritten. +3. `model/` and `tb/` regressions pass. +4. README documents: + - build commands + - test commands + - fixed latency/alignment behavior + +If optional Step D is approved: + +- `tb_rtl/` testcases run successfully +- `iverilog` passes +- `verilator` passes + +## 6) Fixed Debug SOP + +On fail, always use: + +`Seed -> Model -> PyCircuit -> RTL` + +No step skipping. + diff --git a/designs/PE_INT/.gitignore b/designs/PE_INT/.gitignore index 9ead86f..fd9adc6 100644 --- a/designs/PE_INT/.gitignore +++ b/designs/PE_INT/.gitignore @@ -1,5 +1,8 @@ # Tool-generated outputs build/ +!rtl/build/ +!rtl/build/*.v +local_issues/ obj_dir/ sim/logs/ sim/waves/ diff --git a/designs/PE_INT/README.md b/designs/PE_INT/README.md index aab4b5c..98a4aef 100644 --- a/designs/PE_INT/README.md +++ b/designs/PE_INT/README.md @@ -4,7 +4,7 @@ Fixed-point / integer vector MAC unit. Implementation flow: -`docs/spec.md` -> `python/pe_int_pycircuit.py` -> `pycircuit.cli build` -> `rtl/` + `tb/` +`docs/spec.md` -> `python/pe_int_pycircuit.py` -> `pycircuit.cli build` -> `rtl/build/` + `tb/` ## Baseline @@ -19,12 +19,12 @@ Implementation flow: - `tb/`: PyCircuit testbench flow (not RTL simulator flow) - `tb_rtl/`: dedicated RTL test environment (Verilog testbench + cases) - `sim/`: one-command simulation entrypoints (iverilog / verilator + wave options) -- `rtl/`: generated RTL deliverables only +- `rtl/build/`: generated RTL deliverables only ## Key Files - `model/ref_model.py`: reference math and pack/unpack model for all four modes -- `model/pe_int_pycircuit_eval.py`: cycle-accurate pipeline golden model (`L=3`) +- `model/pe_int_pycircuit_eval.py`: cycle-accurate pipeline golden model (`L=4`) - `model/test_pe_int.py`: model-level random regressions - `model/gen_rtl_case_vectors.py`: regenerates expected vectors for `tb_rtl/case` - `python/pe_int_pycircuit.py`: PyCircuit frontend top entry (RTL source of truth) @@ -51,6 +51,10 @@ python model/test_pe_int.py python python/build.py --target both --out-dir build/pe_int ``` +After each build, sync deliverable RTL artifacts from the build output tree into +`rtl/build/`, then refresh `filelist/pe_int.f` so simulation always resolves the +latest deliverable set. + 3) Run dedicated RTL regressions (WSL): ```bash @@ -65,6 +69,7 @@ bash sim/run_sim.sh ## Process Constraints -- Do not handwrite `rtl/*.v`. +- Do not handwrite `rtl/build/*.v`. +- After each build, sync deliverable artifacts into `rtl/build/` and refresh `filelist/pe_int.f`. - `vld_out` must align with `out0`/`out1`; under mode `2a`, `out1` uses hold policy to avoid unnecessary toggles. - On a new machine without existing profiles, bootstrap the environment from `LinxISA/pyCircuit` first. diff --git a/designs/PE_INT/docs/design_spec.md b/designs/PE_INT/docs/design_spec.md index f5aa91d..fb134b6 100644 --- a/designs/PE_INT/docs/design_spec.md +++ b/designs/PE_INT/docs/design_spec.md @@ -1,23 +1,54 @@ # PE_INT Design Spec (DS) -Version: v0.1 -Source of truth for function: `docs/spec.md` (baseline v2.0.5) +Version: v0.4 +Source of truth for function: `docs/spec.md` (baseline v2.0.6) This DS defines low-level circuit structure and stage-level implementation constraints. --- ## 1. Scope and Design Policy -- Functional behavior, interface, and mode semantics are inherited from `docs/spec.md`. -- This DS focuses on low-level RTL micro-architecture: - - bit-slice decode - - multiplier structure - - compressor/reduction structure - - adder topology - - explicit `combk -> regk` pipeline contract -- Depth budgeting follows `logic-depth-rules`: - - input pin -> first register: <= 8 effective logic layers - - each pipeline comb stage target: around 25 layers +- Functional behavior, mode semantics, and top-level contract are inherited from `docs/spec.md`. +- This DS is implementation-oriented and focuses on: + - bit-slice decode and lane mapping + - arithmetic unit structure + - pipeline partition and register boundaries + - control/data alignment at output commit points +- Pipeline partition follows logic-depth guidance: + - target per comb stage: around 25 effective logic layers + - input pin to first register: <= 8 effective logic layers + +### 1.1 Top-Level IO Behavior Contract + +| Port | Dir | Width | Behavior Contract | +|------|-----|-------|-------------------| +| `clk` | in | 1 | Single clock domain, posedge sequential behavior | +| `rst_n` | in | 1 | Active-low reset, async assert + sync release | +| `vld` | in | 1 | Input transaction qualifier, no ready backpressure | +| `mode` | in | 2 | Per-transaction mode (`2a/2b/2c/2d`) | +| `a` | in | 80 | Shared packed A bus | +| `b` | in | 80 | Shared packed B/B0 bus | +| `b1` | in | 80 | Shared packed B1 bus | +| `e1_a` | in | 2 | E1 scale bits for A groups (mode `2c`) | +| `e1_b0` | in | 2 | E1 scale bits for B0 groups (mode `2c`) | +| `e1_b1` | in | 2 | E1 scale bits for B1 groups (mode `2c`) | +| `vld_out` | out | 1 | Output valid aligned with committed outputs | +| `out0` | out | 19 | Registered signed output 0 | +| `out1` | out | 16 | Registered signed output 1 with mode-2a hold policy | + +Hard IO constraints: + +- No additional top-level reset port is allowed in deliverable RTL. +- Pipeline latency and stage count are mode-invariant. +- In mode `2a`, `out1` must remain stable by hold policy (no unnecessary toggles). + +### 1.2 Latency Convention (Normative) + +- This DS uses a 0-based latency definition. +- `t0` is the input sample cycle where one transaction is accepted (`vld=1`). +- Fixed `L=4` means the corresponding committed output valid is observed at `t0+4`. +- Latency must be validated by counting real register boundaries on generated RTL paths. +- Do not infer latency from stage naming (`s0/s1/...`) or comments alone. --- @@ -25,29 +56,32 @@ This DS defines low-level circuit structure and stage-level implementation const ### 2.1 Unified lane container -- Physical carrier is 5-bit lane: `lane[i] = x[5*i+4 : 5*i]`. -- Decode rules: - - `S8` (for 2a/2b/2d A-side and 2a B-side): combine two lanes' `[4:1]`. - - `S4` (2b B-side): take lane `[4:1]`. - - `S5` (2c, 2d B-side): take lane `[4:0]`. +- Physical carrier lane width: 5 bits. +- Lane mapping: `lane[i] = x[5*i+4 : 5*i]`. + +Decode rules: + +- `S8` (2a/2b/2d A-side and 2a B-side): combine two lanes' `[4:1]`. +- `S4` (2b B-side): lane `[4:1]`. +- `S5` (2c and 2d B-side): lane `[4:0]`. ### 2.2 Signed extension rule -- All decode outputs are sign-extended to internal arithmetic width (>= 32b in frontend model). -- Internal adder tree widths are tracked as mathematical no-loss widths (not fixed by tool inference). +- All decoded values are sign-extended before arithmetic. +- Internal width tracking follows no-loss arithmetic intent, not tool-default truncation. --- -## 3. Low-Level Compute Unit Structure +## 3. Compute Unit Structure -## 3.1 Multiplier unit (shared policy) +### 3.1 Multiplier units -All signed multipliers use the same structural template: +All signed multipliers follow the same structural intent: -1. Modified Booth recode (radix-4 equivalent grouping) -2. Partial-product selection/mux network -3. Compressor tree (4:2 / 3:2 based reduction) -4. Final carry-propagate adder (Brent-Kung prefix) +1. Modified Booth recode +2. Partial-product select/mux +3. Compressor tree (3:2 / 4:2 style reduction) +4. Final carry-propagate adder (prefix-family intent) Applied widths: @@ -56,40 +90,34 @@ Applied widths: - `M8x5` for mode 2d - `M5x5` for mode 2c -No mode is allowed to use a hidden "black-box * with unknown topology" in DS intent. - -### 3.2 Dot-product reduction unit +### 3.2 Dot-product reduction -- Dot8 reducer for 8-lane sum: - - CSA tree (3 levels, 3:2-equivalent cells) - - Final Brent-Kung CPA -- Dot16 (2c) is split into two Dot8 branches (`lo[0..7]`, `hi[8..15]`) then post-scaled and merged. +- Dot8 reduction for 2a/2b/2d branch sums +- Dot16 path for 2c split into two Dot8 branches (`lo`, `hi`) before post-scale merge -### 3.3 Post-scale / mode select unit +### 3.3 Post-scale and mode merge -- 2c scale factor: - - `shift = e1_a[k] + e1_bx[k]` (k=0/1, shift in {0,1,2}) - - implemented by 2-level muxed shift (`x1/x2/x4`), not variable barrel shifter. -- Mode select: - - one-hot style select network over precomputed mode candidates - - avoid deep priority chain muxing. +- For mode 2c, `shift = e1_a[k] + e1_bx[k]` (`k=0/1`, shift in `{0,1,2}`) +- Implement post-scale with bounded shift options (`x1/x2/x4`), not full barrel shifter intent +- Mode merge uses one-hot controls from registered control metadata +- Avoid direct `mode == const` comparator chains in late stage merge logic -### 3.4 out1 hold unit (2a toggle suppression) +### 3.4 out1 hold policy -- `out1` update condition: `vld_out=1 && mode!=2a`. -- Else hold last registered `out1_hold`. -- Implemented as explicit state register plus 2:1 mux gating. +- Update condition: committed transaction valid and `mode != 2a` +- Otherwise hold previous `out1_hold` value +- `out1_hold` update control must align with output commit boundary --- -## 4. Manual Depth Probe Data (Pre-DS Calibration) +## 4. Depth Probe Baseline -Depth probes are generated by: +Reference probes are generated by: - `model/depth_probe_units.py` - `model/estimate_logic_depth.py` -Measured structural estimates (effective logic layers): +Measured structural estimates (effective layers): - `booth_mul_8x8`: 19 - `booth_mul_8x5`: 19 @@ -100,171 +128,178 @@ Measured structural estimates (effective logic layers): - `dot8_reduce_10b`: 15 - `dot16_split8_post_scale_14b`: 11 -Suggested comb-stage budgets from probe: +Stage planning notes: -- `comb_mul_gen`: 19 -- `comb_reduce_dot`: 17 -- `comb_post_scale_mux`: 14 +- `comb1` estimate: ~19 +- `comb2` estimate: ~17 +- `comb3` estimate: ~14 -All are below the stage target (~25), leaving margin for control glue. +Logic-depth decision guidance: + +- `<= 25`: within target +- `26..30`: acceptable guideline overflow; warn user and suggest optional repartition +- `> 30`: strong risk; propose repartition or structural optimization --- -## 5. Pipeline Micro-Architecture (Explicit Stage Contract) +## 5. Pipeline Micro-Architecture (Normative) + +Top-level auditable chain: -Top-level must be auditable as: +`input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3/output` -`input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3 -> output` +This partition is the DS baseline because it keeps each major comb stage near target guidance. -Fixed latency policy in this DS: +### 5.1 `comb0` (input-side prelogic) -- `L = 3` cycles from sampled `vld` to `vld_out` (mode-invariant) +Responsibilities: -### Stage definition +- mode predecode and control fanout preparation +- input lane-wiring preparation +- valid/control preconditioning for stage entry -### 5.1 `comb0` (input-side prelogic, <=8 layers) +Constraint: -- Mode decode pre-gating -- Lane extraction wiring prep -- Optional valid-enable fanout buffering -- Constraint: input pin -> `reg0` <= 8 layers +- input pin to `reg0`: <= 8 layers ### 5.2 `reg0` (input capture) -- Capture: `vld, mode, a, b, b1, e1_a, e1_b0, e1_b1` +Capture one transaction payload: + +- `vld, mode, a, b, b1, e1_a, e1_b0, e1_b1` -### 5.3 `comb1` (multiplier generation stage) +### 5.3 `comb1` (product generation) Datapath: -- Per-lane decode (`S8/S4/S5`) -- Per-lane multiply (`M8x8`, `M8x4`, `M8x5`, `M5x5`) -- For dual-output modes, build branch-0/branch-1 product vectors in parallel +- lane decode (`S8/S4/S5`) +- per-lane multiply generation for all mode branches Control-path: -- Mode one-hot generation for downstream selection -- `out1_en` candidate generation (`mode != 2a`) +- one-hot mode controls and aligned branch-control metadata preparation -Expected depth budget: ~19 + small control glue +### 5.4 `reg1` (post-product boundary) -### 5.4 `reg1` +- register `comb1` outputs and aligned control metadata -- Register multiplier outputs and control one-hot / valid. - -### 5.5 `comb2` (dot reduction stage) +### 5.5 `comb2` (dot reduction) Datapath: -- Dot8 reduction for 2a/2b/2d branches -- Dot16 split8 partial reduction for 2c (`lo`, `hi` branch pre-sums) +- dot8 reductions for 2a/2b/2d +- split dot16 partial reductions for 2c (`lo`, `hi`) Control-path: -- Propagate valid/mode control in parallel logic cone - -Expected depth budget: ~15 to ~17 +- propagate aligned transaction controls in parallel -### 5.6 `reg2` +### 5.6 `reg2` (post-reduction boundary) -- Register reduced sums and control alignment signals. +- register reduction outputs and aligned controls -### 5.7 `comb3` (post-scale + mode merge + out policy prep) +### 5.7 `comb3` (post-scale + mode merge) Datapath: -- 2c post-scale (`x1/x2/x4`) and merge of `lo/hi` -- Final mode result selection for `out0_raw`, `out1_raw` +- 2c post-scale and `lo/hi` merge +- final mode-select merge to `out0_raw` and `out1_raw` Control-path: -- `vld_out` candidate -- `out1_en` alignment -- `out1_hold` mux next-value generation +- derive aligned output-commit control metadata + +Hard constraints: + +- `comb3` must be pure combinational logic (no state update) +- mode merge select controls come from registered one-hot metadata +- do not build independent side control chain that can drift from data order + +### 5.8 `reg3/output` (final output commit stage) + +- commit `vld_out`, `out0`, `out1` from the same transaction boundary +- this stage is mandatory for fixed `L=4` under 0-based definition -Expected depth budget: ~14 + control mux glue +Normative commit intent: -### 5.8 `reg3` (output register boundary) +- `out0_commit = out0_raw_aligned` +- `out1_commit = (vld_commit && out1_en_commit) ? out1_raw_aligned : out1_hold` +- `if (vld_commit) out1_hold <= out1_commit` -- Register outputs at top boundary: - - `vld_out` - - `out0` - - `out1` (through hold policy) +Hard constraints: -This satisfies spec requirement: output ports are register-driven. +- no extra policy state on `out0` +- `out1_hold` update point must align with commit control point +- no cross-stage mixing of control and committed data --- -## 6. Mode-Specific Datapath Mapping (Low-Level) +## 6. Mode-Specific Datapath Mapping ### 6.1 Mode 2a (`mode=00`) -- 8 lanes: - - decode `A_i: S8`, `B_i: S8` - - multiply `P_i = A_i * B_i` -- reduce: `SUM0 = Σ_i P_i` via Dot8 reducer -- output: - - `out0 = SUM0[18:0]` - - `out1` uses hold path (no unnecessary toggle) +- Decode `A_i: S8`, `B_i: S8` for 8 lanes +- `P_i = A_i * B_i` +- `out0 = sum_{i=0..7}(P_i)` sliced/extended to 19-bit contract +- `out1` follows hold policy ### 6.2 Mode 2b (`mode=01`) -- lane decode: - - `A_i: S8` - - `B0_i: S4` from `b[39:0]` - - `B1_i: S4` from `b[79:40]` -- products: - - `P0_i = A_i * B0_i` - - `P1_i = A_i * B1_i` -- reduce: - - `SUM0 = Σ_i P0_i` - - `SUM1 = Σ_i P1_i` -- output: - - `out0 = SUM0` (sign-extended/sliced to 19b port contract) - - `out1 = SUM1` (16b port contract) +- `A_i: S8` +- `B0_i: S4` from `b[39:0]`, `B1_i: S4` from `b[79:40]` +- `out0 = sum(A_i * B0_i)` +- `out1 = sum(A_i * B1_i)` ### 6.3 Mode 2d (`mode=11`) -- same dual-branch flow as 2b, but B decode is `S5`. +- Same dual-branch flow as mode 2b, with `B0/B1` as `S5` ### 6.4 Mode 2c (`mode=10`) -- 16 lanes: - - `A_i, B0_i, B1_i` all `S5` -- branch 0: - - `LO0 = Σ_{i=0..7}(A_i*B0_i)` - - `HI0 = Σ_{i=8..15}(A_i*B0_i)` +- 16-lane `S5` datapath for `A/B0/B1` +- Branch 0: + - `LO0 = sum_{i=0..7}(A_i * B0_i)` + - `HI0 = sum_{i=8..15}(A_i * B0_i)` - `SUM0 = (LO0 << (e1_a[0]+e1_b0[0])) + (HI0 << (e1_a[1]+e1_b0[1]))` -- branch 1 similarly with `B1/e1_b1`. +- Branch 1 uses `B1/e1_b1` with the same structure --- ## 7. Control Path Contract -- `vld` is sampled only at stage input boundary. -- One input valid corresponds to one output valid. -- No FIFO / no reorder buffer in datapath. -- Control registers are stage-aligned with datapath registers at every stage. -- Mode switching is allowed back-to-back; per-transaction mode must be preserved through all stages. +- one input `vld=1` transaction maps to one output `vld_out=1` transaction +- no FIFO/reorder semantics in datapath +- back-to-back mode switching is allowed +- transaction order must remain FIFO at output +- control and data must stay aligned at each register boundary --- -## 8. Verification Hooks for This DS +## 8. Verification Hooks Mandatory checks: -1. Stage-audit check: reviewer can identify `comb0/reg0 ... comb3/reg3`. -2. Depth-account check: - - `comb0 <= 8` - - `comb1/2/3` around 25 target and below estimated budget. -3. Mode-invariant latency check: fixed `L=3`. -4. 2a `out1` stability check under sustained valid traffic. -5. No-bubble check for continuous valid stream after pipeline fill. +1. **Contract consistency** + - `spec` and `DS` share same latency semantics (0-based, `t0 -> t0+L`) +2. **Stage audit** + - reviewer can identify `comb0/reg0 -> comb1/reg1 -> comb2/reg2 -> comb3/reg3/output` +3. **Real-path register count (generated RTL)** + - control path `vld -> vld_out` is exactly `L=4` + - committed data paths to `out0/out1` align with same transaction boundary +4. **Commit-point alignment** + - qualifier and outputs come from same commit stage + - `out1_hold` update aligns with commit control +5. **Logic-depth recording** + - record per-stage estimates and classify by decision guidance (`<=25`, `26..30`, `>30`) +6. **Regression and ordering** + - regression passes + - no bubble under sustained valid traffic after fill + - no reorder under alternating mode pairs (for example `2b -> 2a`) --- ## 9. Notes -- This DS is intentionally low-level and structure-first. -- If any future update changes a unit topology (e.g., adder family or multiplier tree), - re-run `model/estimate_logic_depth.py` and update section 4 + stage budgets before code update. +- This DS is low-level and structure-first. +- If arithmetic topology changes, rerun depth estimation and update Section 4. +- If stage partition changes, re-validate latency and commit alignment using generated RTL real-path counts. diff --git a/designs/PE_INT/docs/spec.md b/designs/PE_INT/docs/spec.md index 01f69ba..8c7cee0 100644 --- a/designs/PE_INT/docs/spec.md +++ b/designs/PE_INT/docs/spec.md @@ -1,184 +1,187 @@ -# PE_INT Specification (SPEC) - -This document defines the functional and timing contract for the PE_INT fixed-point / integer vector MAC unit. - -**Spec baseline: v2.0.5 (frozen baseline).** - ---- - -## 1. End-to-End Data Semantics - -### 1.1 Mode 2a (`mode=2'b00`): `A:S8 x B:S8` - -- `A` and `B` are both `8 x S8` (two's complement). -- Output math: - - `out0 = sum_{i=0..7}(A_s8[i] * B_s8[i])` - - `out1` is don't-care semantically in this mode (see stability rule in Section 5.1c). - -### 1.2 Mode 2b (`mode=2'b01`): `A:S8 x B:S4` (dual path) - -- `A` is `8 x S8`. -- `B0` and `B1` are each `8 x S4`. -- Output math: - - `out0 = sum_{i=0..7}(A_s8[i] * B0_s4[i])` - - `out1 = sum_{i=0..7}(A_s8[i] * B1_s4[i])` - -### 1.3 Mode 2c (`mode=2'b10`): `A:S5 x B:S5` with E1 scaling (dual path) - -- `A`, `B0`, `B1` are each `16 x S5`. -- Each 16-lane vector is split into two 8-lane groups with E1 bits: - - group 0: lanes `[0..7]` - - group 1: lanes `[8..15]` -- `e1_a[1:0]`, `e1_b0[1:0]`, `e1_b1[1:0]`, with each bit in `{0,1}`. -- Output math: - - `out0 = sum_lo(A,B0) * 2^(e1_a[0]+e1_b0[0]) + sum_hi(A,B0) * 2^(e1_a[1]+e1_b0[1])` - - `out1 = sum_lo(A,B1) * 2^(e1_a[0]+e1_b1[0]) + sum_hi(A,B1) * 2^(e1_a[1]+e1_b1[1])` - - where `sum_lo(X,Y)=sum_{i=0..7}(X_s5[i]*Y_s5[i])`, `sum_hi(X,Y)=sum_{i=8..15}(X_s5[i]*Y_s5[i])` - -### 1.4 Mode 2d (`mode=2'b11`): `A:S8 x B:S5` (dual path) - -- `A` is `8 x S8`. -- `B0` and `B1` are each `8 x S5`. -- Output math: - - `out0 = sum_{i=0..7}(A_s8[i] * B0_s5[i])` - - `out1 = sum_{i=0..7}(A_s8[i] * B1_s5[i])` - ---- - -## 2. Mode Summary - -| mode | Name | Datapath | -|------|------|----------| -| `2'b00` | 2a | `S8 x S8`, single effective output | -| `2'b01` | 2b | `S8 x S4`, dual output | -| `2'b10` | 2c | `S5 x S5 + E1`, dual output | -| `2'b11` | 2d | `S8 x S5`, dual output | - ---- - -## 3. Output Width (Lossless Math) - -- Mode 2a: `out0` requires 19-bit signed. -- Mode 2b: `out0/out1` each require 15-bit signed. -- Mode 2c: `out0/out1` each require 16-bit signed. -- Mode 2d: `out0/out1` each require 16-bit signed. - -Unified top-level output widths across modes: - -- `out0[18:0]` (19-bit signed) -- `out1[15:0]` (16-bit signed) -- `vld_out` (1-bit) - -Narrower mode results must be sign-extended to unified top-level width. - ---- - -## 4. Top-Level Ports - -| Port | Dir | Width | Description | -|------|-----|-------|-------------| -| `clk` | in | 1 | Single clock domain | -| `rst_n` | in | 1 | Active-low reset (async assert, sync release) | -| `vld` | in | 1 | Input valid, no `ready` backpressure | -| `mode` | in | 2 | Mode selector | -| `a` | in | 80 | Shared A input bus | -| `b` | in | 80 | Shared B/B0 packed bus | -| `b1` | in | 80 | B1 bus (used by mode 2c) | -| `e1_a` | in | 2 | E1 for A groups (mode 2c) | -| `e1_b0` | in | 2 | E1 for B0 groups (mode 2c) | -| `e1_b1` | in | 2 | E1 for B1 groups (mode 2c) | -| `out0` | out | 19 | Unified signed output 0 | -| `out1` | out | 16 | Unified signed output 1 | -| `vld_out` | out | 1 | Output valid aligned with output registers | - ---- - -## 5. Pipeline and Implementation Constraints - -### 5.0 Clock and Reset - -- Single clock domain only. -- `rst_n` uses asynchronous assertion and synchronous release. - -### 5.1 Fully-Pipelined Datapath - -- Must be implemented as a full pipeline datapath. -- Independent FIFO/queue used to bypass fixed pipeline semantics is forbidden. -- End-to-end pipeline latency is fixed and mode-invariant. -- Internal pipeline stage count is mode-invariant. - -### 5.1a Registered Top Outputs (Mandatory) - -- `out0`, `out1`, and `vld_out` must be driven by registers. -- `vld_out` and outputs must update at the same output register boundary. - -### 5.1b Input-Pin to First Register Logic Depth - -- Input-side prelogic before first pipeline register is allowed. -- Effective logic depth from input pins to first register must be `<= 8` layers. - -### 5.1c `vld_out` and Mode-2a `out1` Stability - -- `vld_out=1` marks valid output data in current output cycle. -- In mode 2a, `out1` is mathematically don't-care, but must avoid unnecessary toggles. -- Acceptable strategy: hold previous value or drive documented stable constant. - -### 5.2 Input Valid Handshake - -- No `ready` signal. -- A new transaction is sampled only when `vld=1`. - -### 5.3 Back-to-Back Mode Switching - -- Back-to-back `vld=1` with mode changes is allowed. -- Transaction ordering must remain FIFO at output. -- No mode/data cross-contamination between in-flight transactions. - -### 5.4 Stage Logic Depth Target - -- Main target for each pipeline stage is around 25 effective logic layers. -- Exact counting rules follow project logic-depth policy (`logic-depth-rules`). - ---- - -## 6. Packing Rules - -### 6.1 Lane Definition - -- Lane granularity is `lane[k] = x[5*k+4 : 5*k]`. -- `k = 0..15` across 80-bit buses. - -### 6.2 Modes 2a / 2b / 2d (`A` as S8 lanes) - -- `A` S8 values are packed by 4-bit halves into lane `[4:1]` fields. -- For mode 2b, `b[39:0]` carries B0 `8 x S4`, `b[79:40]` carries B1 `8 x S4`. -- For mode 2d, `b[39:0]` carries B0 `8 x S5`, `b[79:40]` carries B1 `8 x S5`. - -### 6.3 Mode 2c (`A/B0/B1` as `16 x S5`) - -- `x[5*i+4 : 5*i]` maps to element `i` for each of `a`, `b`, and `b1`. -- E1 group mapping: - - bit `[0]` applies to lanes `[0..7]` - - bit `[1]` applies to lanes `[8..15]` - ---- - -## 7. Validity and Latency Contract - -- One sampled `vld=1` transaction maps to one `vld_out=1` transaction. -- `vld -> vld_out` latency is fixed as `L` cycles. -- `L` must be identical for modes 2a/2b/2c/2d. -- Under sustained valid traffic after pipeline fill, no output bubbles are allowed. - ---- - -## 8. Revision Notes - -| Version | Date | Notes | -|---------|------|-------| -| `2.0.5` | 2026-04-17 | Added `vld_out` bundle requirement and mode-2a `out1` stability rule. | -| `2.0.4` | 2026-04-17 | Added `vld` contract and reset/clock-domain clarification. | -| `2.0.3` | 2026-04-17 | Enforced registered outputs and input-to-first-register depth cap. | -| `2.0.2` | 2026-04-17 | Added full-pipeline and per-stage depth target requirements. | -| `2.0.1` | 2026-04-17 | Unified top-level outputs to `out0[18:0]`, `out1[15:0]`. | -| `2.0.0` | 2026-04-17 | Frozen baseline refresh. | +# PE_INT Specification (SPEC) + +This document defines the functional and timing contract for the PE_INT fixed-point / integer vector MAC unit. + +**Spec baseline: v2.0.6 (frozen baseline).** + +--- + +## 1. End-to-End Data Semantics + +### 1.1 Mode 2a (`mode=2'b00`): `A:S8 x B:S8` + +- `A` and `B` are both `8 x S8` (two's complement). +- Output math: + - `out0 = sum_{i=0..7}(A_s8[i] * B_s8[i])` + - `out1` is don't-care semantically in this mode (see stability rule in Section 5.1c). + +### 1.2 Mode 2b (`mode=2'b01`): `A:S8 x B:S4` (dual path) + +- `A` is `8 x S8`. +- `B0` and `B1` are each `8 x S4`. +- Output math: + - `out0 = sum_{i=0..7}(A_s8[i] * B0_s4[i])` + - `out1 = sum_{i=0..7}(A_s8[i] * B1_s4[i])` + +### 1.3 Mode 2c (`mode=2'b10`): `A:S5 x B:S5` with E1 scaling (dual path) + +- `A`, `B0`, `B1` are each `16 x S5`. +- Each 16-lane vector is split into two 8-lane groups with E1 bits: + - group 0: lanes `[0..7]` + - group 1: lanes `[8..15]` +- `e1_a[1:0]`, `e1_b0[1:0]`, `e1_b1[1:0]`, with each bit in `{0,1}`. +- Output math: + - `out0 = sum_lo(A,B0) * 2^(e1_a[0]+e1_b0[0]) + sum_hi(A,B0) * 2^(e1_a[1]+e1_b0[1])` + - `out1 = sum_lo(A,B1) * 2^(e1_a[0]+e1_b1[0]) + sum_hi(A,B1) * 2^(e1_a[1]+e1_b1[1])` + - where `sum_lo(X,Y)=sum_{i=0..7}(X_s5[i]*Y_s5[i])`, `sum_hi(X,Y)=sum_{i=8..15}(X_s5[i]*Y_s5[i])` + +### 1.4 Mode 2d (`mode=2'b11`): `A:S8 x B:S5` (dual path) + +- `A` is `8 x S8`. +- `B0` and `B1` are each `8 x S5`. +- Output math: + - `out0 = sum_{i=0..7}(A_s8[i] * B0_s5[i])` + - `out1 = sum_{i=0..7}(A_s8[i] * B1_s5[i])` + +--- + +## 2. Mode Summary + +| mode | Name | Datapath | +|------|------|----------| +| `2'b00` | 2a | `S8 x S8`, single effective output | +| `2'b01` | 2b | `S8 x S4`, dual output | +| `2'b10` | 2c | `S5 x S5 + E1`, dual output | +| `2'b11` | 2d | `S8 x S5`, dual output | + +--- + +## 3. Output Width (Lossless Math) + +- Mode 2a: `out0` requires 19-bit signed. +- Mode 2b: `out0/out1` each require 15-bit signed. +- Mode 2c: `out0/out1` each require 16-bit signed. +- Mode 2d: `out0/out1` each require 16-bit signed. + +Unified top-level output widths across modes: + +- `out0[18:0]` (19-bit signed) +- `out1[15:0]` (16-bit signed) +- `vld_out` (1-bit) + +Narrower mode results must be sign-extended to unified top-level width. + +--- + +## 4. Top-Level Ports + +| Port | Dir | Width | Description | +|------|-----|-------|-------------| +| `clk` | in | 1 | Single clock domain | +| `rst_n` | in | 1 | Active-low reset (async assert, sync release) | +| `vld` | in | 1 | Input valid, no `ready` backpressure | +| `mode` | in | 2 | Mode selector | +| `a` | in | 80 | Shared A input bus | +| `b` | in | 80 | Shared B/B0 packed bus | +| `b1` | in | 80 | B1 bus (used by mode 2c) | +| `e1_a` | in | 2 | E1 for A groups (mode 2c) | +| `e1_b0` | in | 2 | E1 for B0 groups (mode 2c) | +| `e1_b1` | in | 2 | E1 for B1 groups (mode 2c) | +| `out0` | out | 19 | Unified signed output 0 | +| `out1` | out | 16 | Unified signed output 1 | +| `vld_out` | out | 1 | Output valid aligned with output registers | + +--- + +## 5. Pipeline and Implementation Constraints + +### 5.0 Clock and Reset + +- Single clock domain only. +- `rst_n` uses asynchronous assertion and synchronous release. + +### 5.1 Fully-Pipelined Datapath + +- Must be implemented as a full pipeline datapath. +- Independent FIFO/queue used to bypass fixed pipeline semantics is forbidden. +- End-to-end pipeline latency is fixed and mode-invariant. +- Internal pipeline stage count is mode-invariant. + +### 5.1a Registered Top Outputs (Mandatory) + +- `out0`, `out1`, and `vld_out` must be driven by registers. +- `vld_out` and outputs must update at the same output register boundary. + +### 5.1b Input-Pin to First Register Logic Depth + +- Input-side prelogic before first pipeline register is allowed. +- Effective logic depth from input pins to first register must be `<= 8` layers. + +### 5.1c `vld_out` and Mode-2a `out1` Stability + +- `vld_out=1` marks valid output data in current output cycle. +- In mode 2a, `out1` is mathematically don't-care, but must avoid unnecessary toggles. +- Acceptable strategy: hold previous value or drive documented stable constant. + +### 5.2 Input Valid Handshake + +- No `ready` signal. +- A new transaction is sampled only when `vld=1`. + +### 5.3 Back-to-Back Mode Switching + +- Back-to-back `vld=1` with mode changes is allowed. +- Transaction ordering must remain FIFO at output. +- No mode/data cross-contamination between in-flight transactions. + +### 5.4 Stage Logic Depth Target + +- Main target for each pipeline stage is around 25 effective logic layers. +- Exact counting rules follow project logic-depth policy (`logic-depth-rules`). + +--- + +## 6. Packing Rules + +### 6.1 Lane Definition + +- Lane granularity is `lane[k] = x[5*k+4 : 5*k]`. +- `k = 0..15` across 80-bit buses. + +### 6.2 Modes 2a / 2b / 2d (`A` as S8 lanes) + +- `A` S8 values are packed by 4-bit halves into lane `[4:1]` fields. +- For mode 2b, `b[39:0]` carries B0 `8 x S4`, `b[79:40]` carries B1 `8 x S4`. +- For mode 2d, `b[39:0]` carries B0 `8 x S5`, `b[79:40]` carries B1 `8 x S5`. + +### 6.3 Mode 2c (`A/B0/B1` as `16 x S5`) + +- `x[5*i+4 : 5*i]` maps to element `i` for each of `a`, `b`, and `b1`. +- E1 group mapping: + - bit `[0]` applies to lanes `[0..7]` + - bit `[1]` applies to lanes `[8..15]` + +--- + +## 7. Validity and Latency Contract + +- One sampled `vld=1` transaction maps to one `vld_out=1` transaction. +- `vld -> vld_out` latency is fixed as `L` cycles. +- Fixed project contract: `L = 4`. +- 0-based latency convention: if input transaction is sampled at `t0`, the corresponding committed output valid appears at `t0+L` (for this project, `t0+4`). +- `L` must be identical for modes 2a/2b/2c/2d. +- Under sustained valid traffic after pipeline fill, no output bubbles are allowed. + +--- + +## 8. Revision Notes + +| Version | Date | Notes | +|---------|------|-------| +| `2.0.6` | 2026-04-29 | Updated fixed latency contract to `L=4` and aligned verification baseline. | +| `2.0.5` | 2026-04-17 | Added `vld_out` bundle requirement and mode-2a `out1` stability rule. | +| `2.0.4` | 2026-04-17 | Added `vld` contract and reset/clock-domain clarification. | +| `2.0.3` | 2026-04-17 | Enforced registered outputs and input-to-first-register depth cap. | +| `2.0.2` | 2026-04-17 | Added full-pipeline and per-stage depth target requirements. | +| `2.0.1` | 2026-04-17 | Unified top-level outputs to `out0[18:0]`, `out1[15:0]`. | +| `2.0.0` | 2026-04-17 | Frozen baseline refresh. | diff --git a/designs/PE_INT/filelist/pe_int.f b/designs/PE_INT/filelist/pe_int.f index a5284fa..2641d74 100644 --- a/designs/PE_INT/filelist/pe_int.f +++ b/designs/PE_INT/filelist/pe_int.f @@ -1,2 +1,2 @@ -$PE_INT/rtl/pyc_primitives.v -$PE_INT/rtl/pe_int_l3.v +$PE_INT/rtl/build/pyc_primitives.v +$PE_INT/rtl/build/pe_int_l3.v diff --git a/designs/PE_INT/memory.md b/designs/PE_INT/memory.md index 42ed60c..b2dfacd 100644 --- a/designs/PE_INT/memory.md +++ b/designs/PE_INT/memory.md @@ -1,3 +1,3 @@ -# Memory - -- Test result wording preference: use only `pass/fail` (avoid phrases like "all green"). +# Memory + +- Test result wording preference: use only `pass/fail` (avoid phrases like "all green"). diff --git a/designs/PE_INT/model/README.md b/designs/PE_INT/model/README.md index 9964853..92ee004 100644 --- a/designs/PE_INT/model/README.md +++ b/designs/PE_INT/model/README.md @@ -1,22 +1,22 @@ -# model (Models and Model Tests) - -This directory centralizes all model assets used for verification and comparison. - -## Contents - -- `ref_model.py`: reference math and pack/unpack model for all four modes -- `pe_int_pycircuit_eval.py`: cycle-accurate pipeline model (`L=3`) -- `test_pe_int.py`: model-layer regression tests (without direct RTL simulator invocation) -- `gen_rtl_case_vectors.py`: generates testcase vectors and expected values for `tb_rtl/case` -- `model.f`: model filelist (prefixed with absolute `$PE_INT`) - -## Principles - -- Any verification needing golden/model comparison must use this directory as source of truth. -- If `tb/` or `tb_rtl/` uses expected values, they must be traceable back to `model/`. - -## Run - -```bash -python model/test_pe_int.py -``` +# model (Models and Model Tests) + +This directory centralizes all model assets used for verification and comparison. + +## Contents + +- `ref_model.py`: reference math and pack/unpack model for all four modes +- `pe_int_pycircuit_eval.py`: cycle-accurate pipeline model (`L=4`) +- `test_pe_int.py`: model-layer regression tests (without direct RTL simulator invocation) +- `gen_rtl_case_vectors.py`: generates testcase vectors and expected values for `tb_rtl/case` +- `model.f`: model filelist (prefixed with absolute `$PE_INT`) + +## Principles + +- Any verification needing golden/model comparison must use this directory as source of truth. +- If `tb/` or `tb_rtl/` uses expected values, they must be traceable back to `model/`. + +## Run + +```bash +python model/test_pe_int.py +``` diff --git a/designs/PE_INT/model/gen_rtl_case_vectors.py b/designs/PE_INT/model/gen_rtl_case_vectors.py index 6e3e2b4..129a283 100644 --- a/designs/PE_INT/model/gen_rtl_case_vectors.py +++ b/designs/PE_INT/model/gen_rtl_case_vectors.py @@ -1,15 +1,15 @@ from __future__ import annotations - import argparse import random from pathlib import Path +from typing import Iterable, Sequence -from pe_int_pycircuit_eval import PEIntL3Model from ref_model import ( MODE_2A, MODE_2B, MODE_2C, MODE_2D, + MacResult, compute_transaction, pack_s4x8_to_40, pack_s5x8_to_40, @@ -20,33 +20,16 @@ VEC_PER_CASE = 1000 -def _hex(width: int, value: int) -> str: - digits = (width + 3) // 4 - return f"{width}'h{(value & ((1 << width) - 1)):0{digits}x}" - - -def _sdec(width: int, value: int) -> str: - if value < 0: - return f"-{width}'sd{-value}" - return f"{width}'sd{value}" - - -def _rand_s(width: int) -> int: - lo = -(1 << (width - 1)) - hi = (1 << (width - 1)) - 1 - return random.randint(lo, hi) - - def _rand_s_rng(rng: random.Random, width: int) -> int: lo = -(1 << (width - 1)) hi = (1 << (width - 1)) - 1 return rng.randint(lo, hi) -def _make_txn(mode: int): +def _make_txn_rng(mode: int, rng: random.Random): if mode == MODE_2A: - a = [_rand_s(8) for _ in range(8)] - b = [_rand_s(8) for _ in range(8)] + a = [_rand_s_rng(rng, 8) for _ in range(8)] + b = [_rand_s_rng(rng, 8) for _ in range(8)] return ( pack_s8x8_to_laneword(a), pack_s8x8_to_laneword(b), @@ -56,23 +39,23 @@ def _make_txn(mode: int): (0, 0), ) if mode == MODE_2B: - a = [_rand_s(8) for _ in range(8)] - b0 = [_rand_s(4) for _ in range(8)] - b1 = [_rand_s(4) for _ in range(8)] + a = [_rand_s_rng(rng, 8) for _ in range(8)] + b0 = [_rand_s_rng(rng, 4) for _ in range(8)] + b1 = [_rand_s_rng(rng, 4) for _ in range(8)] b = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) if mode == MODE_2D: - a = [_rand_s(8) for _ in range(8)] - b0 = [_rand_s(5) for _ in range(8)] - b1 = [_rand_s(5) for _ in range(8)] + a = [_rand_s_rng(rng, 8) for _ in range(8)] + b0 = [_rand_s_rng(rng, 5) for _ in range(8)] + b1 = [_rand_s_rng(rng, 5) for _ in range(8)] b = pack_s5x8_to_40(b0) | (pack_s5x8_to_40(b1) << 40) return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) - a = [_rand_s(5) for _ in range(16)] - b0 = [_rand_s(5) for _ in range(16)] - b1 = [_rand_s(5) for _ in range(16)] - e1a = (random.randint(0, 1), random.randint(0, 1)) - e1b0 = (random.randint(0, 1), random.randint(0, 1)) - e1b1 = (random.randint(0, 1), random.randint(0, 1)) + a = [_rand_s_rng(rng, 5) for _ in range(16)] + b0 = [_rand_s_rng(rng, 5) for _ in range(16)] + b1 = [_rand_s_rng(rng, 5) for _ in range(16)] + e1a = (rng.randint(0, 1), rng.randint(0, 1)) + e1b0 = (rng.randint(0, 1), rng.randint(0, 1)) + e1b1 = (rng.randint(0, 1), rng.randint(0, 1)) return ( pack_s5x16_to_80(a), pack_s5x16_to_80(b0), @@ -83,181 +66,150 @@ def _make_txn(mode: int): ) -def _write(path: Path, content: str) -> None: - path.parent.mkdir(parents=True, exist_ok=True) - path.write_text(content, encoding="utf-8") - print(f"generated: {path}") - - def _hex_word(width: int, value: int) -> str: digits = (width + 3) // 4 return f"{(value & ((1 << width) - 1)):0{digits}x}" -def _write_mem(path: Path, width: int, values: list[int]) -> None: +def _write_mem(path: Path, width: int, values: Sequence[int]) -> None: path.parent.mkdir(parents=True, exist_ok=True) - path.write_text("\n".join(_hex_word(width, v) for v in values) + "\n", encoding="utf-8") + path.write_text("\n".join(_hex_word(width, item) for item in values) + "\n", encoding="utf-8") print(f"generated: {path}") +def _tx_result(mode: int, a: int, b: int, b1: int, e1_a, e1_b0, e1_b1) -> MacResult: + return compute_transaction(mode, a, b, b1, e1_a, e1_b0, e1_b1) + + +def _expected_stream_by_accepted_tx(txs: Iterable[tuple[int, int, int, int, int, tuple[int, int], tuple[int, int], tuple[int, int]]]): + exp_o0: list[int] = [] + exp_o1: list[int] = [] + out1_hold = 0 + accepted = 0 + for vld, mode, a, b, b1, e1_a, e1_b0, e1_b1 in txs: + if not vld: + continue + accepted += 1 + mac = _tx_result(mode, a, b, b1, e1_a, e1_b0, e1_b1) + exp_o0.append(mac.out0_19) + if mode == MODE_2A: + exp_o1.append(out1_hold) + else: + out1_hold = mac.out1_16 + exp_o1.append(out1_hold) + return accepted, exp_o0, exp_o1 + + def gen_sanity_case_headers(gen_dir: Path, seed: int) -> None: - # Sanity vectors are deterministic for the same seed. rng = random.Random(seed) - # 2b: 1000 vectors tx_2b = [] for _ in range(VEC_PER_CASE): - a = [_rand_s_rng(rng, 8) for _ in range(8)] - b0 = [_rand_s_rng(rng, 4) for _ in range(8)] - b1 = [_rand_s_rng(rng, 4) for _ in range(8)] - a_w = pack_s8x8_to_laneword(a) - b_w = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) - r = compute_transaction(MODE_2B, a_w, b_w, 0, (0, 0), (0, 0), (0, 0)) - tx_2b.append((a_w, b_w, r.out0_19, r.out1_16)) - _write_mem(gen_dir / "tc_mode2b_sanity_tx_a.mem", 80, [x[0] for x in tx_2b]) - _write_mem(gen_dir / "tc_mode2b_sanity_tx_b.mem", 80, [x[1] for x in tx_2b]) - _write_mem(gen_dir / "tc_mode2b_sanity_exp_o0.mem", 19, [x[2] for x in tx_2b]) - _write_mem(gen_dir / "tc_mode2b_sanity_exp_o1.mem", 16, [x[3] for x in tx_2b]) + a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(MODE_2B, rng) + tx_2b.append((1, MODE_2B, a, b, b1, e1a, e1b0, e1b1)) + _, exp2b_o0, exp2b_o1 = _expected_stream_by_accepted_tx(tx_2b) + _write_mem(gen_dir / "tc_mode2b_sanity_tx_a.mem", 80, [item[2] for item in tx_2b]) + _write_mem(gen_dir / "tc_mode2b_sanity_tx_b.mem", 80, [item[3] for item in tx_2b]) + _write_mem(gen_dir / "tc_mode2b_sanity_exp_o0.mem", 19, exp2b_o0) + _write_mem(gen_dir / "tc_mode2b_sanity_exp_o1.mem", 16, exp2b_o1) - # 2a: each case is preload-2b + mode2a cases_2a = [] + tx_2a_stream = [] for _ in range(VEC_PER_CASE): - a_pre = [_rand_s_rng(rng, 8) for _ in range(8)] - b0_pre = [_rand_s_rng(rng, 4) for _ in range(8)] - b1_pre = [_rand_s_rng(rng, 4) for _ in range(8)] - a_pre_w = pack_s8x8_to_laneword(a_pre) - b_pre_w = pack_s4x8_to_40(b0_pre) | (pack_s4x8_to_40(b1_pre) << 40) - r_pre = compute_transaction(MODE_2B, a_pre_w, b_pre_w, 0, (0, 0), (0, 0), (0, 0)) + a_pre, b_pre, b1_pre, e1a_pre, e1b0_pre, e1b1_pre = _make_txn_rng(MODE_2B, rng) + a_2a, b_2a, b1_2a, e1a_2a, e1b0_2a, e1b1_2a = _make_txn_rng(MODE_2A, rng) + cases_2a.append((a_pre, b_pre, a_2a, b_2a)) + tx_2a_stream.append((1, MODE_2B, a_pre, b_pre, b1_pre, e1a_pre, e1b0_pre, e1b1_pre)) + tx_2a_stream.append((1, MODE_2A, a_2a, b_2a, b1_2a, e1a_2a, e1b0_2a, e1b1_2a)) + _, exp2a_o0, exp2a_o1 = _expected_stream_by_accepted_tx(tx_2a_stream) + _write_mem(gen_dir / "tc_mode2a_sanity_pre_a.mem", 80, [item[0] for item in cases_2a]) + _write_mem(gen_dir / "tc_mode2a_sanity_pre_b.mem", 80, [item[1] for item in cases_2a]) + _write_mem(gen_dir / "tc_mode2a_sanity_a2a.mem", 80, [item[2] for item in cases_2a]) + _write_mem(gen_dir / "tc_mode2a_sanity_b2a.mem", 80, [item[3] for item in cases_2a]) + _write_mem(gen_dir / "tc_mode2a_sanity_exp_o0.mem", 19, exp2a_o0) + _write_mem(gen_dir / "tc_mode2a_sanity_exp_o1.mem", 16, exp2a_o1) - a2 = [_rand_s_rng(rng, 8) for _ in range(8)] - b2 = [_rand_s_rng(rng, 8) for _ in range(8)] - a2_w = pack_s8x8_to_laneword(a2) - b2_w = pack_s8x8_to_laneword(b2) - r2 = compute_transaction(MODE_2A, a2_w, b2_w, 0, (0, 0), (0, 0), (0, 0)) - cases_2a.append((a_pre_w, b_pre_w, a2_w, b2_w, r_pre.out1_16, r2.out0_19)) - _write_mem(gen_dir / "tc_mode2a_sanity_pre_a.mem", 80, [x[0] for x in cases_2a]) - _write_mem(gen_dir / "tc_mode2a_sanity_pre_b.mem", 80, [x[1] for x in cases_2a]) - _write_mem(gen_dir / "tc_mode2a_sanity_a2a.mem", 80, [x[2] for x in cases_2a]) - _write_mem(gen_dir / "tc_mode2a_sanity_b2a.mem", 80, [x[3] for x in cases_2a]) - _write_mem(gen_dir / "tc_mode2a_sanity_exp_pre_o1.mem", 16, [x[4] for x in cases_2a]) - _write_mem(gen_dir / "tc_mode2a_sanity_exp_2a_o0.mem", 19, [x[5] for x in cases_2a]) - - # 2d: 1000 vectors tx_2d = [] for _ in range(VEC_PER_CASE): - a = [_rand_s_rng(rng, 8) for _ in range(8)] - b0 = [_rand_s_rng(rng, 5) for _ in range(8)] - b1 = [_rand_s_rng(rng, 5) for _ in range(8)] - a_w = pack_s8x8_to_laneword(a) - b_w = pack_s5x8_to_40(b0) | (pack_s5x8_to_40(b1) << 40) - r = compute_transaction(MODE_2D, a_w, b_w, 0, (0, 0), (0, 0), (0, 0)) - tx_2d.append((a_w, b_w, r.out0_19, r.out1_16)) - _write_mem(gen_dir / "tc_mode2d_sanity_tx_a.mem", 80, [x[0] for x in tx_2d]) - _write_mem(gen_dir / "tc_mode2d_sanity_tx_b.mem", 80, [x[1] for x in tx_2d]) - _write_mem(gen_dir / "tc_mode2d_sanity_exp_o0.mem", 19, [x[2] for x in tx_2d]) - _write_mem(gen_dir / "tc_mode2d_sanity_exp_o1.mem", 16, [x[3] for x in tx_2d]) + a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(MODE_2D, rng) + tx_2d.append((1, MODE_2D, a, b, b1, e1a, e1b0, e1b1)) + _, exp2d_o0, exp2d_o1 = _expected_stream_by_accepted_tx(tx_2d) + _write_mem(gen_dir / "tc_mode2d_sanity_tx_a.mem", 80, [item[2] for item in tx_2d]) + _write_mem(gen_dir / "tc_mode2d_sanity_tx_b.mem", 80, [item[3] for item in tx_2d]) + _write_mem(gen_dir / "tc_mode2d_sanity_exp_o0.mem", 19, exp2d_o0) + _write_mem(gen_dir / "tc_mode2d_sanity_exp_o1.mem", 16, exp2d_o1) - # 2c: 1000 vectors tx_2c = [] for _ in range(VEC_PER_CASE): - a = [_rand_s_rng(rng, 5) for _ in range(16)] - b0 = [_rand_s_rng(rng, 5) for _ in range(16)] - b1 = [_rand_s_rng(rng, 5) for _ in range(16)] - e1a = (rng.randint(0, 1), rng.randint(0, 1)) - e1b0 = (rng.randint(0, 1), rng.randint(0, 1)) - e1b1 = (rng.randint(0, 1), rng.randint(0, 1)) - a_w = pack_s5x16_to_80(a) - b0_w = pack_s5x16_to_80(b0) - b1_w = pack_s5x16_to_80(b1) - r = compute_transaction(MODE_2C, a_w, b0_w, b1_w, e1a, e1b0, e1b1) - tx_2c.append((a_w, b0_w, b1_w, e1a, e1b0, e1b1, r.out0_19, r.out1_16)) - _write_mem(gen_dir / "tc_mode2c_sanity_tx_a.mem", 80, [x[0] for x in tx_2c]) - _write_mem(gen_dir / "tc_mode2c_sanity_tx_b0.mem", 80, [x[1] for x in tx_2c]) - _write_mem(gen_dir / "tc_mode2c_sanity_tx_b1.mem", 80, [x[2] for x in tx_2c]) - _write_mem(gen_dir / "tc_mode2c_sanity_tx_e1a.mem", 2, [x[3][0] | (x[3][1] << 1) for x in tx_2c]) - _write_mem(gen_dir / "tc_mode2c_sanity_tx_e1b0.mem", 2, [x[4][0] | (x[4][1] << 1) for x in tx_2c]) - _write_mem(gen_dir / "tc_mode2c_sanity_tx_e1b1.mem", 2, [x[5][0] | (x[5][1] << 1) for x in tx_2c]) - _write_mem(gen_dir / "tc_mode2c_sanity_exp_o0.mem", 19, [x[6] for x in tx_2c]) - _write_mem(gen_dir / "tc_mode2c_sanity_exp_o1.mem", 16, [x[7] for x in tx_2c]) + a, b0, b1, e1a, e1b0, e1b1 = _make_txn_rng(MODE_2C, rng) + tx_2c.append((1, MODE_2C, a, b0, b1, e1a, e1b0, e1b1)) + _, exp2c_o0, exp2c_o1 = _expected_stream_by_accepted_tx(tx_2c) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_a.mem", 80, [item[2] for item in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_b0.mem", 80, [item[3] for item in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_b1.mem", 80, [item[4] for item in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_e1a.mem", 2, [item[5][0] | (item[5][1] << 1) for item in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_e1b0.mem", 2, [item[6][0] | (item[6][1] << 1) for item in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_tx_e1b1.mem", 2, [item[7][0] | (item[7][1] << 1) for item in tx_2c]) + _write_mem(gen_dir / "tc_mode2c_sanity_exp_o0.mem", 19, exp2c_o0) + _write_mem(gen_dir / "tc_mode2c_sanity_exp_o1.mem", 16, exp2c_o1) def gen_mode_switch_random(gen_dir: Path, seed: int) -> None: - random.seed(seed) - modes = [MODE_2A, MODE_2B, MODE_2C, MODE_2D] + rng = random.Random(seed) tx = [] + modes = [MODE_2A, MODE_2B, MODE_2C, MODE_2D] for _ in range(VEC_PER_CASE): - vld = random.randint(0, 1) - mode = random.choice(modes) - a, b, b1, e1a, e1b0, e1b1 = _make_txn(mode) + vld = rng.randint(0, 1) + mode = rng.choice(modes) + a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(mode, rng) tx.append((vld, mode, a, b, b1, e1a, e1b0, e1b1)) - dut = PEIntL3Model() - for _ in range(3): - dut.step(rst_n=0, vld=0, mode=0, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) - for _ in range(3): - dut.step(rst_n=1, vld=0, mode=0, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) - - exp = [] - for item in tx: - r = dut.step( - rst_n=1, - vld=item[0], - mode=item[1], - a=item[2], - b=item[3], - b1=item[4], - e1_a=item[5], - e1_b0=item[6], - e1_b1=item[7], - ) - if r.vld_out: - exp.append((r.out0, r.out1)) - for _ in range(30): - r = dut.step(rst_n=1, vld=0, mode=0, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) - if r.vld_out: - exp.append((r.out0, r.out1)) - - _write( - gen_dir / "tc_mode_switch_random_sizes.vh", - "\n".join( - [ - "// Auto-generated by model/gen_rtl_case_vectors.py", - f"// seed: {seed}", - f"localparam integer N_TX = {len(tx)};", - f"localparam integer N_EXP = {len(exp)};", - "", - ] - ), - ) - _write_mem(gen_dir / "tc_mode_switch_random_tx_vld.mem", 1, [x[0] for x in tx]) - _write_mem(gen_dir / "tc_mode_switch_random_tx_mode.mem", 2, [x[1] for x in tx]) - _write_mem(gen_dir / "tc_mode_switch_random_tx_a.mem", 80, [x[2] for x in tx]) - _write_mem(gen_dir / "tc_mode_switch_random_tx_b.mem", 80, [x[3] for x in tx]) - _write_mem(gen_dir / "tc_mode_switch_random_tx_b1.mem", 80, [x[4] for x in tx]) - _write_mem(gen_dir / "tc_mode_switch_random_tx_e1a.mem", 2, [x[5][0] | (x[5][1] << 1) for x in tx]) - _write_mem(gen_dir / "tc_mode_switch_random_tx_e1b0.mem", 2, [x[6][0] | (x[6][1] << 1) for x in tx]) - _write_mem(gen_dir / "tc_mode_switch_random_tx_e1b1.mem", 2, [x[7][0] | (x[7][1] << 1) for x in tx]) - exp_o0 = [x[0] for x in exp] + [0] * (VEC_PER_CASE - len(exp)) - exp_o1 = [x[1] for x in exp] + [0] * (VEC_PER_CASE - len(exp)) - _write_mem(gen_dir / "tc_mode_switch_random_exp_o0.mem", 19, exp_o0) - _write_mem(gen_dir / "tc_mode_switch_random_exp_o1.mem", 16, exp_o1) - _write_mem(gen_dir / "tc_mode_switch_random_meta.mem", 32, [len(exp)]) + exp_count, exp_o0, exp_o1 = _expected_stream_by_accepted_tx(tx) + _write_mem(gen_dir / "tc_mode_switch_random_tx_vld.mem", 1, [item[0] for item in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_mode.mem", 2, [item[1] for item in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_a.mem", 80, [item[2] for item in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_b.mem", 80, [item[3] for item in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_b1.mem", 80, [item[4] for item in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_e1a.mem", 2, [item[5][0] | (item[5][1] << 1) for item in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_e1b0.mem", 2, [item[6][0] | (item[6][1] << 1) for item in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_tx_e1b1.mem", 2, [item[7][0] | (item[7][1] << 1) for item in tx]) + _write_mem(gen_dir / "tc_mode_switch_random_exp_o0.mem", 19, list(exp_o0) + [0] * (VEC_PER_CASE - exp_count)) + _write_mem(gen_dir / "tc_mode_switch_random_exp_o1.mem", 16, list(exp_o1) + [0] * (VEC_PER_CASE - exp_count)) + _write_mem(gen_dir / "tc_mode_switch_random_meta.mem", 32, [exp_count]) + + +def gen_mode_fixed_random_timing(gen_dir: Path, seed: int) -> None: + for case_name, mode in [("mode2a", MODE_2A), ("mode2b", MODE_2B), ("mode2c", MODE_2C), ("mode2d", MODE_2D)]: + rng = random.Random(seed + mode * 101) + tx = [] + for _ in range(VEC_PER_CASE): + vld = rng.randint(0, 1) + a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(mode, rng) + tx.append((vld, mode, a, b, b1, e1a, e1b0, e1b1)) + exp_count, exp_o0, exp_o1 = _expected_stream_by_accepted_tx(tx) + prefix = f"tc_{case_name}_sanity_rand_timing" + _write_mem(gen_dir / f"{prefix}_tx_vld.mem", 1, [item[0] for item in tx]) + _write_mem(gen_dir / f"{prefix}_tx_a.mem", 80, [item[2] for item in tx]) + _write_mem(gen_dir / f"{prefix}_tx_b.mem", 80, [item[3] for item in tx]) + _write_mem(gen_dir / f"{prefix}_tx_b1.mem", 80, [item[4] for item in tx]) + _write_mem(gen_dir / f"{prefix}_tx_e1a.mem", 2, [item[5][0] | (item[5][1] << 1) for item in tx]) + _write_mem(gen_dir / f"{prefix}_tx_e1b0.mem", 2, [item[6][0] | (item[6][1] << 1) for item in tx]) + _write_mem(gen_dir / f"{prefix}_tx_e1b1.mem", 2, [item[7][0] | (item[7][1] << 1) for item in tx]) + _write_mem(gen_dir / f"{prefix}_exp_o0.mem", 19, list(exp_o0) + [0] * (VEC_PER_CASE - exp_count)) + _write_mem(gen_dir / f"{prefix}_exp_o1.mem", 16, list(exp_o1) + [0] * (VEC_PER_CASE - exp_count)) + _write_mem(gen_dir / f"{prefix}_meta.mem", 32, [exp_count]) def main() -> None: - parser = argparse.ArgumentParser(description="Generate RTL testcase vectors from model.") - parser.add_argument( - "--seed", - type=int, - default=20260420, - help="seed for random mode-switch testcase generation", - ) + parser = argparse.ArgumentParser(description="Generate RTL testcase vectors from ref model.") + parser.add_argument("--seed", type=int, default=20260420, help="base seed for random vectors") args = parser.parse_args() repo = Path(__file__).resolve().parents[1] gen_dir = repo / "tb_rtl" / "case" / "generated" gen_sanity_case_headers(gen_dir, args.seed) gen_mode_switch_random(gen_dir, args.seed) + gen_mode_fixed_random_timing(gen_dir, args.seed) if __name__ == "__main__": diff --git a/designs/PE_INT/model/pe_int_pycircuit_eval.py b/designs/PE_INT/model/pe_int_pycircuit_eval.py index 5674958..b93679a 100644 --- a/designs/PE_INT/model/pe_int_pycircuit_eval.py +++ b/designs/PE_INT/model/pe_int_pycircuit_eval.py @@ -1,10 +1,11 @@ from __future__ import annotations from dataclasses import dataclass +from typing import List from ref_model import MODE_2A, MacResult, compute_transaction, to_signed -DEFAULT_PIPELINE_L = 3 +DEFAULT_PIPELINE_L = 4 @dataclass @@ -23,26 +24,46 @@ class StepResult: class PEIntL3Model: - """Cycle-accurate PE_INT model for golden checking.""" + """ + Cycle-accurate model with normative 0-based latency: + accepted at t0 -> committed output at t0+4. + """ def __init__(self) -> None: - self.s0 = StagePayload() - self.s1 = StagePayload() - self.s2 = StagePayload() + self.pipe: List[StagePayload] = [StagePayload() for _ in range(DEFAULT_PIPELINE_L)] self.out0 = 0 self.out1 = 0 self.vld_out = 0 - # If reset has never been asserted, skip release window at power-up. - self._rst_release_count = 2 + self.out1_hold = 0 def reset(self) -> None: - self.s0 = StagePayload() - self.s1 = StagePayload() - self.s2 = StagePayload() + self.pipe = [StagePayload() for _ in range(DEFAULT_PIPELINE_L)] self.out0 = 0 self.out1 = 0 self.vld_out = 0 - self._rst_release_count = 0 + self.out1_hold = 0 + + def _next_stage0( + self, + *, + vld: int, + mode: int, + a: int, + b: int, + b1: int, + e1_a: tuple[int, int], + e1_b0: tuple[int, int], + e1_b1: tuple[int, int], + ) -> StagePayload: + if not vld: + return StagePayload(vld=0, mode=mode & 0x3, out0_19=0, out1_16=0) + mac: MacResult = compute_transaction(mode, a, b, b1, e1_a, e1_b0, e1_b1) + return StagePayload( + vld=1, + mode=mode & 0x3, + out0_19=to_signed(mac.out0_19, 19), + out1_16=to_signed(mac.out1_16, 16), + ) def step( self, @@ -61,40 +82,25 @@ def step( self.reset() return StepResult(vld_out=0, out0=0, out1=0) - if self._rst_release_count < 2: - self._rst_release_count += 1 - self.s0 = StagePayload() - self.s1 = StagePayload() - self.s2 = StagePayload() - self.vld_out = 0 - self.out0 = 0 - self.out1 = 0 - return StepResult(vld_out=0, out0=0, out1=0) - - new_vld_out = self.s2.vld - new_out0 = self.out0 - new_out1 = self.out1 - if self.s2.vld: - new_out0 = to_signed(self.s2.out0_19, 19) - if self.s2.mode != MODE_2A: - new_out1 = to_signed(self.s2.out1_16, 16) - - if vld: - mac: MacResult = compute_transaction(mode, a, b, b1, e1_a, e1_b0, e1_b1) - next_s0 = StagePayload( - vld=1, - mode=mode & 0x3, - out0_19=to_signed(mac.out0_19, 19), - out1_16=to_signed(mac.out1_16, 16), - ) - else: - next_s0 = StagePayload(vld=0, mode=mode & 0x3, out0_19=0, out1_16=0) - - self.s2 = StagePayload(self.s1.vld, self.s1.mode, self.s1.out0_19, self.s1.out1_16) - self.s1 = StagePayload(self.s0.vld, self.s0.mode, self.s0.out0_19, self.s0.out1_16) - self.s0 = next_s0 - - self.vld_out = new_vld_out - self.out0 = to_signed(new_out0, 19) - self.out1 = to_signed(new_out1, 16) + commit = self.pipe[-1] + if commit.vld: + self.out0 = to_signed(commit.out0_19, 19) + if commit.mode != MODE_2A: + self.out1_hold = to_signed(commit.out1_16, 16) + self.vld_out = int(commit.vld) + self.out1 = to_signed(self.out1_hold, 16) + + for idx in range(DEFAULT_PIPELINE_L - 1, 0, -1): + prev = self.pipe[idx - 1] + self.pipe[idx] = StagePayload(prev.vld, prev.mode, prev.out0_19, prev.out1_16) + self.pipe[0] = self._next_stage0( + vld=vld, + mode=mode, + a=a, + b=b, + b1=b1, + e1_a=e1_a, + e1_b0=e1_b0, + e1_b1=e1_b1, + ) return StepResult(vld_out=self.vld_out, out0=self.out0, out1=self.out1) diff --git a/designs/PE_INT/model/ref_model.py b/designs/PE_INT/model/ref_model.py index 6e65942..a83fac4 100644 --- a/designs/PE_INT/model/ref_model.py +++ b/designs/PE_INT/model/ref_model.py @@ -25,27 +25,27 @@ def get_lane5(word80: int, lane_idx: int) -> int: def decode_s8x8_from_laneword(word80: int) -> List[int]: vals: List[int] = [] - for i in range(8): - lo = (get_lane5(word80, 2 * i) >> 1) & 0xF - hi = (get_lane5(word80, 2 * i + 1) >> 1) & 0xF + for idx in range(8): + lo = (get_lane5(word80, 2 * idx) >> 1) & 0xF + hi = (get_lane5(word80, 2 * idx + 1) >> 1) & 0xF vals.append(to_signed((hi << 4) | lo, 8)) return vals def decode_s4x8_from_40(word40: int) -> List[int]: vals: List[int] = [] - for i in range(8): - lane = (word40 >> (5 * i)) & 0x1F + for idx in range(8): + lane = (word40 >> (5 * idx)) & 0x1F vals.append(to_signed((lane >> 1) & 0xF, 4)) return vals def decode_s5x8_from_40(word40: int) -> List[int]: - return [to_signed((word40 >> (5 * i)) & 0x1F, 5) for i in range(8)] + return [to_signed((word40 >> (5 * idx)) & 0x1F, 5) for idx in range(8)] def decode_s5x16_from_80(word80: int) -> List[int]: - return [to_signed((word80 >> (5 * i)) & 0x1F, 5) for i in range(16)] + return [to_signed((word80 >> (5 * idx)) & 0x1F, 5) for idx in range(16)] def _e1_shift(e1_pair_a: Sequence[int], e1_pair_b: Sequence[int]) -> Tuple[int, int]: @@ -96,14 +96,13 @@ def compute_transaction( sum1 = sum(x * y for x, y in zip(a, b1)) return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) - # MODE_2C a = decode_s5x16_from_80(a80) b0 = decode_s5x16_from_80(b80) b1 = decode_s5x16_from_80(b1_80) - lo0 = sum(a[i] * b0[i] for i in range(8)) - hi0 = sum(a[i] * b0[i] for i in range(8, 16)) - lo1 = sum(a[i] * b1[i] for i in range(8)) - hi1 = sum(a[i] * b1[i] for i in range(8, 16)) + lo0 = sum(a[idx] * b0[idx] for idx in range(8)) + hi0 = sum(a[idx] * b0[idx] for idx in range(8, 16)) + lo1 = sum(a[idx] * b1[idx] for idx in range(8)) + hi1 = sum(a[idx] * b1[idx] for idx in range(8, 16)) sh0_lo, sh0_hi = _e1_shift(e1_a, e1_b0) sh1_lo, sh1_hi = _e1_shift(e1_a, e1_b1) @@ -116,12 +115,12 @@ def pack_s8x8_to_laneword(values: Sequence[int]) -> int: if len(values) != 8: raise ValueError("need 8 S8 values") word = 0 - for i, val in enumerate(values): + for idx, val in enumerate(values): raw = val & 0xFF lane_lo = (raw & 0xF) << 1 lane_hi = ((raw >> 4) & 0xF) << 1 - word |= lane_lo << (5 * (2 * i)) - word |= lane_hi << (5 * (2 * i + 1)) + word |= lane_lo << (5 * (2 * idx)) + word |= lane_hi << (5 * (2 * idx + 1)) return word @@ -129,9 +128,9 @@ def pack_s4x8_to_40(values: Sequence[int]) -> int: if len(values) != 8: raise ValueError("need 8 S4 values") word = 0 - for i, val in enumerate(values): + for idx, val in enumerate(values): lane = ((val & 0xF) << 1) & 0x1F - word |= lane << (5 * i) + word |= lane << (5 * idx) return word @@ -139,8 +138,8 @@ def pack_s5x8_to_40(values: Sequence[int]) -> int: if len(values) != 8: raise ValueError("need 8 S5 values") word = 0 - for i, val in enumerate(values): - word |= (val & 0x1F) << (5 * i) + for idx, val in enumerate(values): + word |= (val & 0x1F) << (5 * idx) return word @@ -148,6 +147,6 @@ def pack_s5x16_to_80(values: Sequence[int]) -> int: if len(values) != 16: raise ValueError("need 16 S5 values") word = 0 - for i, val in enumerate(values): - word |= (val & 0x1F) << (5 * i) + for idx, val in enumerate(values): + word |= (val & 0x1F) << (5 * idx) return word diff --git a/designs/PE_INT/python/build.py b/designs/PE_INT/python/build.py index d0be14e..15ee1ee 100644 --- a/designs/PE_INT/python/build.py +++ b/designs/PE_INT/python/build.py @@ -1,56 +1,130 @@ -from __future__ import annotations - -import argparse -import os -import subprocess -import sys -from pathlib import Path - - -def main() -> int: - parser = argparse.ArgumentParser(description="Build PE_INT via pyCircuit/pycc.") - parser.add_argument("--out-dir", default="build/pe_int", help="pycircuit build output directory") - parser.add_argument("--target", default="both", choices=("rtl", "sim", "both"), help="build target") - parser.add_argument("--jobs", default="8", help="parallel jobs for pycircuit build") - args = parser.parse_args() - - repo_root = Path(__file__).resolve().parents[1] - tb_file = repo_root / "tb" / "tb_pe_int_pycircuit.py" - out_dir = repo_root / args.out_dir - out_dir.mkdir(parents=True, exist_ok=True) - - env = os.environ.copy() - py_path = env.get("PYTHONPATH", "") - if str(repo_root / "python") not in py_path: - env["PYTHONPATH"] = str(repo_root / "python") + (os.pathsep + py_path if py_path else "") - - # Default toolchain resolution: - # PE_INT is expected under /designs/PE_INT, - # so pycircuit root can be derived by walking up two levels. - pycircuit_root = repo_root.parents[1] - default_toolchain_root = pycircuit_root / ".pycircuit_out" / "toolchain" / "install" - default_pycc = default_toolchain_root / "bin" / "pycc" - if "PYC_TOOLCHAIN_ROOT" not in env and default_toolchain_root.exists(): - env["PYC_TOOLCHAIN_ROOT"] = str(default_toolchain_root) - if "PYCC" not in env and default_pycc.exists(): - env["PYCC"] = str(default_pycc) - - cmd = [ - sys.executable, - "-m", - "pycircuit.cli", - "build", - str(tb_file), - "--out-dir", - str(out_dir), - "--target", - args.target, - "--jobs", - str(args.jobs), - ] - print("Running:", " ".join(cmd)) - return subprocess.call(cmd, cwd=str(repo_root), env=env) - - -if __name__ == "__main__": - raise SystemExit(main()) +from __future__ import annotations + +import argparse +import os +import re +import subprocess +import sys +from pathlib import Path +from shutil import copy2 + + +def _load_current_design_name(repo_root: Path) -> str: + py_dir = repo_root / "python" + if str(py_dir) not in sys.path: + sys.path.insert(0, str(py_dir)) + try: + import pe_int_pycircuit # type: ignore + except Exception as exc: # pragma: no cover - environment-dependent import path. + raise RuntimeError(f"Unable to import pe_int_pycircuit to resolve design name: {exc}") from exc + design_name = getattr(pe_int_pycircuit.build, "__pycircuit_name__", "") + if not design_name: + raise RuntimeError("Missing build.__pycircuit_name__ in pe_int_pycircuit.") + return str(design_name) + + +def _sync_generated_rtl(repo_root: Path, out_dir: Path, design_name: str) -> None: + verilog_root = out_dir / "device" / "verilog" + design_dir = verilog_root / design_name + design_verilog = design_dir / f"{design_name}.v" + primitives_verilog = design_dir / "pyc_primitives.v" + if not design_verilog.exists(): + raise RuntimeError(f"Generated design verilog not found: {design_verilog}") + if not primitives_verilog.exists(): + raise RuntimeError(f"Generated primitives verilog not found: {primitives_verilog}") + + rtl_dir = repo_root / "rtl" / "build" + rtl_dir.mkdir(parents=True, exist_ok=True) + dst_top = rtl_dir / "pe_int_l3.v" + dst_primitives = rtl_dir / "pyc_primitives.v" + + # Keep RTL TB interface stable on pe_int_l3, while always sourcing from fresh pycc output. + top_text = design_verilog.read_text(encoding="utf-8") + if design_name != "pe_int_l3": + top_text = re.sub(rf"\bmodule\s+{re.escape(design_name)}\b", "module pe_int_l3", top_text, count=1) + top_text = re.sub(rf"\bendmodule\s*//\s*{re.escape(design_name)}\b", "endmodule // pe_int_l3", top_text) + + # Normalize external reset interface to spec: keep only rst_n as top-level input. + # pycircuit v5 default CycleAwareDomain emits a top-level active-high `rst` port. + # We keep internal reset net as `rst` but derive it from `rst_n` for deliverable RTL. + if re.search(r"^\s*input\s+rst,\s*$", top_text, flags=re.MULTILINE): + top_text = re.sub(r"^\s*input\s+rst,\s*$\n?", "", top_text, count=1, flags=re.MULTILINE) + if "assign rst = ~rst_n;" not in top_text: + top_text = re.sub(r"\);\n", ");\n\nwire rst;\nassign rst = ~rst_n;\n\n", top_text, count=1) + + dst_top.write_text(top_text, encoding="utf-8") + copy2(primitives_verilog, dst_primitives) + + filelist = repo_root / "filelist" / "pe_int.f" + filelist.parent.mkdir(parents=True, exist_ok=True) + filelist.write_text("$PE_INT/rtl/build/pyc_primitives.v\n$PE_INT/rtl/build/pe_int_l3.v\n", encoding="utf-8") + + +def main() -> int: + parser = argparse.ArgumentParser(description="Build PE_INT via pyCircuit/pycc.") + parser.add_argument("--out-dir", default="build/pe_int", help="pycircuit build output directory") + parser.add_argument("--target", default="both", choices=("rtl", "sim", "both"), help="build target") + parser.add_argument("--jobs", default="8", help="parallel jobs for pycircuit build") + parser.add_argument( + "--pyc-tb-vectors", + default=os.environ.get("PE_INT_PYC_TB_VEC_PER_CASE", "8"), + help="number of vectors per PyCircuit-level testcase (default: smoke-sized 8)", + ) + args = parser.parse_args() + + repo_root = Path(__file__).resolve().parents[1] + tb_file = repo_root / "tb" / "tb_pe_int_pycircuit.py" + out_dir = repo_root / args.out_dir + out_dir.mkdir(parents=True, exist_ok=True) + + env = os.environ.copy() + py_path = env.get("PYTHONPATH", "") + if str(repo_root / "python") not in py_path: + env["PYTHONPATH"] = str(repo_root / "python") + (os.pathsep + py_path if py_path else "") + + # Default toolchain resolution: + # PE_INT is expected under /designs/PE_INT, + # so pycircuit root can be derived by walking up two levels. + pycircuit_root = repo_root.parents[1] + default_toolchain_root = pycircuit_root / ".pycircuit_out" / "toolchain" / "install" + default_pycc = default_toolchain_root / "bin" / "pycc" + if "PYC_TOOLCHAIN_ROOT" not in env and default_toolchain_root.exists(): + env["PYC_TOOLCHAIN_ROOT"] = str(default_toolchain_root) + if "PYCC" not in env and default_pycc.exists(): + env["PYCC"] = str(default_pycc) + env["PE_INT_PYC_TB_VEC_PER_CASE"] = str(args.pyc_tb_vectors) + + pycircuit_target = { + # pycircuit.cli no longer accepts a pure `rtl` target; `verilator` emits + # the Verilog device artifacts that build.py syncs into rtl/build. + "rtl": "verilator", + "sim": "verilator", + "both": "both", + }[args.target] + + cmd = [ + sys.executable, + "-m", + "pycircuit.cli", + "build", + str(tb_file), + "--out-dir", + str(out_dir), + "--target", + pycircuit_target, + "--jobs", + str(args.jobs), + ] + print("Running:", " ".join(cmd)) + rc = subprocess.call(cmd, cwd=str(repo_root), env=env) + if rc != 0: + return rc + + design_name = _load_current_design_name(repo_root) + _sync_generated_rtl(repo_root, out_dir, design_name) + print(f"Synced generated RTL into {repo_root / 'rtl' / 'build'} and refreshed filelist/pe_int.f") + return 0 + + +if __name__ == "__main__": + raise SystemExit(main()) diff --git a/designs/PE_INT/python/pe_int/__init__.py b/designs/PE_INT/python/pe_int/__init__.py index 50d90f2..1c458f7 100644 --- a/designs/PE_INT/python/pe_int/__init__.py +++ b/designs/PE_INT/python/pe_int/__init__.py @@ -1,4 +1,4 @@ -from .constants import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D +from .constants import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, SPEC_LATENCY_L from .top import build, emit_mlir __all__ = [ @@ -7,6 +7,7 @@ "MODE_2C", "MODE_2D", "DEFAULT_PIPELINE_L", + "SPEC_LATENCY_L", "build", "emit_mlir", ] diff --git a/designs/PE_INT/python/pe_int/constants.py b/designs/PE_INT/python/pe_int/constants.py index 3183576..16f7a2f 100644 --- a/designs/PE_INT/python/pe_int/constants.py +++ b/designs/PE_INT/python/pe_int/constants.py @@ -5,7 +5,8 @@ MODE_2C = 2 MODE_2D = 3 -DEFAULT_PIPELINE_L = 3 +DEFAULT_PIPELINE_L = 4 +SPEC_LATENCY_L = 4 LANE_WORD_W = 80 LANE5_W = 5 diff --git a/designs/PE_INT/python/pe_int/lane_mac.py b/designs/PE_INT/python/pe_int/lane_mac.py index 65eae7a..9ccfb0d 100644 --- a/designs/PE_INT/python/pe_int/lane_mac.py +++ b/designs/PE_INT/python/pe_int/lane_mac.py @@ -35,17 +35,16 @@ def shift_scale_x1_x2_x4(value, shift2b): """ DS §3.3: use 2-level muxed shift (x1/x2/x4), avoid barrel shifter. """ - return mux(shift2b == 0, value, mux(shift2b == 1, value * 2, value * 4)) - - -def select_one_hot4(sel0, sel1, sel2, sel3, cand0, cand1, cand2, cand3): - """ - One-hot selection network to avoid deep priority mux chain. - """ - return (cand0 * sel0) + (cand1 * sel1) + (cand2 * sel2) + (cand3 * sel3) + scale2 = value + value + scale4 = scale2 + scale2 + return mux(shift2b == 0, value, mux(shift2b == 1, scale2, scale4)) def sum_shift_pair(lo, hi, e1_a, e1_b): - sh_lo = wire_of(e1_a)[0:1] + wire_of(e1_b)[0:1] - sh_hi = wire_of(e1_a)[1:2] + wire_of(e1_b)[1:2] - return shift_scale_x1_x2_x4(lo, sh_lo) + shift_scale_x1_x2_x4(hi, sh_hi) + lo_w = wire_of(lo) + hi_w = wire_of(hi) + e1_a_w = wire_of(e1_a) + e1_b_w = wire_of(e1_b) + sh_lo = e1_a_w[0:1]._zext(width=2) + e1_b_w[0:1]._zext(width=2) + sh_hi = e1_a_w[1:2]._zext(width=2) + e1_b_w[1:2]._zext(width=2) + return shift_scale_x1_x2_x4(lo_w, sh_lo) + shift_scale_x1_x2_x4(hi_w, sh_hi) diff --git a/designs/PE_INT/python/pe_int/mac_modes.py b/designs/PE_INT/python/pe_int/mac_modes.py index 3d37850..60b5b3b 100644 --- a/designs/PE_INT/python/pe_int/mac_modes.py +++ b/designs/PE_INT/python/pe_int/mac_modes.py @@ -1,17 +1,9 @@ from __future__ import annotations -from pycircuit import wire_of +from pycircuit import mux, wire_of from .decode import decode_s4_from_40, decode_s4_hi_from_80, decode_s5, decode_s5_hi_from_80, decode_s8_from_lane_word -from .lane_mac import booth_mul_signed, dot8_reduce, dot16_split8_reduce, select_one_hot4, sum_shift_pair - - -def _mode_one_hot(mode): - is_2a = mode == 0 - is_2b = mode == 1 - is_2c = mode == 2 - is_2d = mode == 3 - return is_2a, is_2b, is_2c, is_2d +from .lane_mac import booth_mul_signed, dot8_reduce, dot16_split8_reduce, sum_shift_pair def comb1_generate_products(a, b, b1): @@ -95,34 +87,28 @@ def comb2_reduce_products(products): } -def comb3_mode_merge(reduced, mode, e1_a, e1_b0, e1_b1): +def comb3_mode_merge(reduced, e1_a, e1_b0, e1_b1, *, is_2a, is_2b, is_2c, is_2d): """ DS §5.7: - 2c post-scale x1/x2/x4 - one-hot mode merge for out0_raw/out1_raw """ - is_2a, is_2b, is_2c, is_2d = _mode_one_hot(mode) s2c0 = sum_shift_pair(reduced["s2c0_lo"], reduced["s2c0_hi"], e1_a, e1_b0) s2c1 = sum_shift_pair(reduced["s2c1_lo"], reduced["s2c1_hi"], e1_a, e1_b1) - out0_raw = select_one_hot4( - is_2a, - is_2b, - is_2c, - is_2d, - reduced["s2a"], - reduced["s2b0"], - s2c0, - reduced["s2d0"], - ) - out1_raw = select_one_hot4( - is_2a, - is_2b, - is_2c, - is_2d, - reduced["s2a"] * 0, - reduced["s2b1"], - s2c1, - reduced["s2d1"], - ) + # DS hard rule: comb3 mode merge uses registered one-hot directly; no mode==const compare here. + # Keep comb3 as raw-wire combinational logic so cycle-aware balancing does not add flops here. + is_2a_w = wire_of(is_2a) + is_2b_w = wire_of(is_2b) + is_2c_w = wire_of(is_2c) + s2a_w = wire_of(reduced["s2a"]) + s2b0_w = wire_of(reduced["s2b0"]) + s2b1_w = wire_of(reduced["s2b1"]) + s2d0_w = wire_of(reduced["s2d0"]) + s2d1_w = wire_of(reduced["s2d1"]) + + out0_raw = mux(is_2a_w, s2a_w, mux(is_2b_w, s2b0_w, mux(is_2c_w, s2c0, s2d0_w))) + # 2a does not commit out1; use a real datapath branch instead of `* 0` + # so pyCircuit does not insert multiplier balance registers in comb3. + out1_raw = mux(is_2a_w, s2b1_w, mux(is_2b_w, s2b1_w, mux(is_2c_w, s2c1, s2d1_w))) return out0_raw, out1_raw diff --git a/designs/PE_INT/python/pe_int/top.py b/designs/PE_INT/python/pe_int/top.py index 2347f6d..a5034d6 100644 --- a/designs/PE_INT/python/pe_int/top.py +++ b/designs/PE_INT/python/pe_int/top.py @@ -12,9 +12,8 @@ mux = None # type: ignore[assignment] wire_of = None # type: ignore[assignment] -from .constants import DEFAULT_PIPELINE_L, MODE_2A +from .constants import DEFAULT_PIPELINE_L, OUT0_W, OUT1_W, SPEC_LATENCY_L from .mac_modes import comb1_generate_products, comb2_reduce_products, comb3_mode_merge -from .pipeline import out1_hold_policy def _require_pycircuit() -> None: @@ -24,14 +23,22 @@ def _require_pycircuit() -> None: ) +def _reg_sig(domain: CycleAwareDomain, value, name: str): + return cas(domain, domain.cycle(value, name=name), cycle=0) + + +def _reg_vector(domain: CycleAwareDomain, values, *, prefix: str): + return [_reg_sig(domain, val, f"{prefix}_{idx}") for idx, val in enumerate(values)] + + def build(m: CycleAwareCircuit, domain: CycleAwareDomain, latency: int = DEFAULT_PIPELINE_L) -> None: """ Explicit DS pipeline: - input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3 -> output + input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3/output """ _require_pycircuit() - if int(latency) != DEFAULT_PIPELINE_L: - raise ValueError(f"This top-level implementation requires fixed latency={DEFAULT_PIPELINE_L}.") + if int(latency) != SPEC_LATENCY_L: + raise ValueError(f"This top-level implementation requires fixed latency={SPEC_LATENCY_L}.") _ = m.input("rst_n", width=1) in_vld = cas(domain, m.input("vld", width=1), cycle=0) @@ -48,100 +55,112 @@ def build(m: CycleAwareCircuit, domain: CycleAwareDomain, latency: int = DEFAULT c0_is_2b = in_mode == 1 c0_is_2c = in_mode == 2 c0_is_2d = in_mode == 3 - c0_out1_en = in_mode != MODE_2A # reg0: input capture boundary (cycle-aware sampled transaction). domain.next() - s0_vld = cas(domain, domain.cycle(in_vld, name="pe_int_s0_vld"), cycle=0) - s0_mode = cas(domain, domain.cycle(in_mode, name="pe_int_s0_mode"), cycle=0) - s0_is_2a = cas(domain, domain.cycle(c0_is_2a, name="pe_int_s0_is_2a"), cycle=0) - s0_is_2b = cas(domain, domain.cycle(c0_is_2b, name="pe_int_s0_is_2b"), cycle=0) - s0_is_2c = cas(domain, domain.cycle(c0_is_2c, name="pe_int_s0_is_2c"), cycle=0) - s0_is_2d = cas(domain, domain.cycle(c0_is_2d, name="pe_int_s0_is_2d"), cycle=0) - s0_out1_en = cas(domain, domain.cycle(c0_out1_en, name="pe_int_s0_out1_en"), cycle=0) - s0_a = cas(domain, domain.cycle(in_a, name="pe_int_s0_a"), cycle=0) - s0_b = cas(domain, domain.cycle(in_b, name="pe_int_s0_b"), cycle=0) - s0_b1 = cas(domain, domain.cycle(in_b1, name="pe_int_s0_b1"), cycle=0) - s0_e1_a = cas(domain, domain.cycle(in_e1_a, name="pe_int_s0_e1_a"), cycle=0) - s0_e1_b0 = cas(domain, domain.cycle(in_e1_b0, name="pe_int_s0_e1_b0"), cycle=0) - s0_e1_b1 = cas(domain, domain.cycle(in_e1_b1, name="pe_int_s0_e1_b1"), cycle=0) - - # comb1: lane decode + lane multipliers. + s0_vld = _reg_sig(domain, in_vld, "pe_int_s0_vld") + s0_is_2a = _reg_sig(domain, c0_is_2a, "pe_int_s0_is_2a") + s0_is_2b = _reg_sig(domain, c0_is_2b, "pe_int_s0_is_2b") + s0_is_2c = _reg_sig(domain, c0_is_2c, "pe_int_s0_is_2c") + s0_is_2d = _reg_sig(domain, c0_is_2d, "pe_int_s0_is_2d") + s0_a = _reg_sig(domain, in_a, "pe_int_s0_a") + s0_b = _reg_sig(domain, in_b, "pe_int_s0_b") + s0_b1 = _reg_sig(domain, in_b1, "pe_int_s0_b1") + s0_e1_a = _reg_sig(domain, in_e1_a, "pe_int_s0_e1_a") + s0_e1_b0 = _reg_sig(domain, in_e1_b0, "pe_int_s0_e1_b0") + s0_e1_b1 = _reg_sig(domain, in_e1_b1, "pe_int_s0_e1_b1") + + # comb1: decode + per-lane product generation. c1_products = comb1_generate_products(s0_a, s0_b, s0_b1) - # reg1: product vectors + aligned controls. + # reg1: post-product boundary. domain.next() - s1_vld = cas(domain, domain.cycle(s0_vld, name="pe_int_s1_vld"), cycle=0) - s1_mode = cas(domain, domain.cycle(s0_mode, name="pe_int_s1_mode"), cycle=0) - s1_is_2a = cas(domain, domain.cycle(s0_is_2a, name="pe_int_s1_is_2a"), cycle=0) - s1_is_2b = cas(domain, domain.cycle(s0_is_2b, name="pe_int_s1_is_2b"), cycle=0) - s1_is_2c = cas(domain, domain.cycle(s0_is_2c, name="pe_int_s1_is_2c"), cycle=0) - s1_is_2d = cas(domain, domain.cycle(s0_is_2d, name="pe_int_s1_is_2d"), cycle=0) - s1_out1_en = cas(domain, domain.cycle(s0_out1_en, name="pe_int_s1_out1_en"), cycle=0) - s1_e1_a = cas(domain, domain.cycle(s0_e1_a, name="pe_int_s1_e1_a"), cycle=0) - s1_e1_b0 = cas(domain, domain.cycle(s0_e1_b0, name="pe_int_s1_e1_b0"), cycle=0) - s1_e1_b1 = cas(domain, domain.cycle(s0_e1_b1, name="pe_int_s1_e1_b1"), cycle=0) + s1_vld = _reg_sig(domain, s0_vld, "pe_int_s1_vld") + s1_is_2a = _reg_sig(domain, s0_is_2a, "pe_int_s1_is_2a") + s1_is_2b = _reg_sig(domain, s0_is_2b, "pe_int_s1_is_2b") + s1_is_2c = _reg_sig(domain, s0_is_2c, "pe_int_s1_is_2c") + s1_is_2d = _reg_sig(domain, s0_is_2d, "pe_int_s1_is_2d") + s1_e1_a = _reg_sig(domain, s0_e1_a, "pe_int_s1_e1_a") + s1_e1_b0 = _reg_sig(domain, s0_e1_b0, "pe_int_s1_e1_b0") + s1_e1_b1 = _reg_sig(domain, s0_e1_b1, "pe_int_s1_e1_b1") s1_products = { - "p2a": [cas(domain, domain.cycle(c1_products["p2a"][i], name=f"pe_int_s1_p2a_{i}"), cycle=0) for i in range(8)], - "p2b0": [cas(domain, domain.cycle(c1_products["p2b0"][i], name=f"pe_int_s1_p2b0_{i}"), cycle=0) for i in range(8)], - "p2b1": [cas(domain, domain.cycle(c1_products["p2b1"][i], name=f"pe_int_s1_p2b1_{i}"), cycle=0) for i in range(8)], - "p2d0": [cas(domain, domain.cycle(c1_products["p2d0"][i], name=f"pe_int_s1_p2d0_{i}"), cycle=0) for i in range(8)], - "p2d1": [cas(domain, domain.cycle(c1_products["p2d1"][i], name=f"pe_int_s1_p2d1_{i}"), cycle=0) for i in range(8)], - "p2c0": [cas(domain, domain.cycle(c1_products["p2c0"][i], name=f"pe_int_s1_p2c0_{i}"), cycle=0) for i in range(16)], - "p2c1": [cas(domain, domain.cycle(c1_products["p2c1"][i], name=f"pe_int_s1_p2c1_{i}"), cycle=0) for i in range(16)], + "p2a": _reg_vector(domain, c1_products["p2a"], prefix="pe_int_s1_p2a"), + "p2b0": _reg_vector(domain, c1_products["p2b0"], prefix="pe_int_s1_p2b0"), + "p2b1": _reg_vector(domain, c1_products["p2b1"], prefix="pe_int_s1_p2b1"), + "p2d0": _reg_vector(domain, c1_products["p2d0"], prefix="pe_int_s1_p2d0"), + "p2d1": _reg_vector(domain, c1_products["p2d1"], prefix="pe_int_s1_p2d1"), + "p2c0": _reg_vector(domain, c1_products["p2c0"], prefix="pe_int_s1_p2c0"), + "p2c1": _reg_vector(domain, c1_products["p2c1"], prefix="pe_int_s1_p2c1"), } - # comb2: dot reductions. + # comb2: dot-product reductions only. c2_reduced = comb2_reduce_products(s1_products) - # reg2: reduced sums + aligned controls. + # reg2: post-reduction boundary. domain.next() - s2_vld = cas(domain, domain.cycle(s1_vld, name="pe_int_s2_vld"), cycle=0) - s2_mode = cas(domain, domain.cycle(s1_mode, name="pe_int_s2_mode"), cycle=0) - s2_is_2a = cas(domain, domain.cycle(s1_is_2a, name="pe_int_s2_is_2a"), cycle=0) - s2_is_2b = cas(domain, domain.cycle(s1_is_2b, name="pe_int_s2_is_2b"), cycle=0) - s2_is_2c = cas(domain, domain.cycle(s1_is_2c, name="pe_int_s2_is_2c"), cycle=0) - s2_is_2d = cas(domain, domain.cycle(s1_is_2d, name="pe_int_s2_is_2d"), cycle=0) - s2_out1_en = cas(domain, domain.cycle(s1_out1_en, name="pe_int_s2_out1_en"), cycle=0) - s2_e1_a = cas(domain, domain.cycle(s1_e1_a, name="pe_int_s2_e1_a"), cycle=0) - s2_e1_b0 = cas(domain, domain.cycle(s1_e1_b0, name="pe_int_s2_e1_b0"), cycle=0) - s2_e1_b1 = cas(domain, domain.cycle(s1_e1_b1, name="pe_int_s2_e1_b1"), cycle=0) - s2_reduced = { - "s2a": cas(domain, domain.cycle(c2_reduced["s2a"], name="pe_int_s2_s2a"), cycle=0), - "s2b0": cas(domain, domain.cycle(c2_reduced["s2b0"], name="pe_int_s2_s2b0"), cycle=0), - "s2b1": cas(domain, domain.cycle(c2_reduced["s2b1"], name="pe_int_s2_s2b1"), cycle=0), - "s2d0": cas(domain, domain.cycle(c2_reduced["s2d0"], name="pe_int_s2_s2d0"), cycle=0), - "s2d1": cas(domain, domain.cycle(c2_reduced["s2d1"], name="pe_int_s2_s2d1"), cycle=0), - "s2c0_lo": cas(domain, domain.cycle(c2_reduced["s2c0_lo"], name="pe_int_s2_s2c0_lo"), cycle=0), - "s2c0_hi": cas(domain, domain.cycle(c2_reduced["s2c0_hi"], name="pe_int_s2_s2c0_hi"), cycle=0), - "s2c1_lo": cas(domain, domain.cycle(c2_reduced["s2c1_lo"], name="pe_int_s2_s2c1_lo"), cycle=0), - "s2c1_hi": cas(domain, domain.cycle(c2_reduced["s2c1_hi"], name="pe_int_s2_s2c1_hi"), cycle=0), + s2_vld = _reg_sig(domain, s1_vld, "pe_int_s2_vld") + s2_is_2a = _reg_sig(domain, s1_is_2a, "pe_int_s2_is_2a") + s2_is_2b = _reg_sig(domain, s1_is_2b, "pe_int_s2_is_2b") + s2_is_2c = _reg_sig(domain, s1_is_2c, "pe_int_s2_is_2c") + s2_is_2d = _reg_sig(domain, s1_is_2d, "pe_int_s2_is_2d") + s2_e1_a = _reg_sig(domain, s1_e1_a, "pe_int_s2_e1_a") + s2_e1_b0 = _reg_sig(domain, s1_e1_b0, "pe_int_s2_e1_b0") + s2_e1_b1 = _reg_sig(domain, s1_e1_b1, "pe_int_s2_e1_b1") + s2_s2a = _reg_sig(domain, c2_reduced["s2a"], "pe_int_s2_s2a") + s2_s2b0 = _reg_sig(domain, c2_reduced["s2b0"], "pe_int_s2_s2b0") + s2_s2b1 = _reg_sig(domain, c2_reduced["s2b1"], "pe_int_s2_s2b1") + s2_s2d0 = _reg_sig(domain, c2_reduced["s2d0"], "pe_int_s2_s2d0") + s2_s2d1 = _reg_sig(domain, c2_reduced["s2d1"], "pe_int_s2_s2d1") + s2_s2c0_lo = _reg_sig(domain, c2_reduced["s2c0_lo"], "pe_int_s2_s2c0_lo") + s2_s2c0_hi = _reg_sig(domain, c2_reduced["s2c0_hi"], "pe_int_s2_s2c0_hi") + s2_s2c1_lo = _reg_sig(domain, c2_reduced["s2c1_lo"], "pe_int_s2_s2c1_lo") + s2_s2c1_hi = _reg_sig(domain, c2_reduced["s2c1_hi"], "pe_int_s2_s2c1_hi") + + # comb3: pure combinational post-scale + mode merge with reg2 one-hot controls. + c3_reduced = { + "s2a": s2_s2a, + "s2b0": s2_s2b0, + "s2b1": s2_s2b1, + "s2d0": s2_s2d0, + "s2d1": s2_s2d1, + "s2c0_lo": s2_s2c0_lo, + "s2c0_hi": s2_s2c0_hi, + "s2c1_lo": s2_s2c1_lo, + "s2c1_hi": s2_s2c1_hi, } - - # comb3: post-scale, mode-merge and out1 hold-next preparation. - c3_out0_raw, c3_out1_raw = comb3_mode_merge(s2_reduced, s2_mode, s2_e1_a, s2_e1_b0, s2_e1_b1) - c3_vld_out = s2_vld - c3_out1_update = s2_vld & s2_out1_en - - # reg3: output register boundary and explicit out1 hold register update. - out1 = out1_hold_policy( - domain, - vld_aligned=c3_vld_out, - out1_en_aligned=s2_out1_en, - out1_aligned=wire_of(c3_out1_raw)[0:16], - prefix="pe_int", + c3_out0_raw, c3_out1_raw = comb3_mode_merge( + c3_reduced, + s2_e1_a, + s2_e1_b0, + s2_e1_b1, + is_2a=s2_is_2a, + is_2b=s2_is_2b, + is_2c=s2_is_2c, + is_2d=s2_is_2d, + ) + c3_out0 = wire_of(c3_out0_raw)[0:OUT0_W] + c3_out1 = wire_of(c3_out1_raw)[0:OUT1_W] + + # reg3/output commit: vld_out/out0/out1 from the same commit boundary. + out1_hold = domain.state(width=OUT1_W, reset_value=0, name="pe_int_out1_hold") + out1_commit = mux( + wire_of(s2_vld), + mux(wire_of(s2_is_2a), wire_of(out1_hold), c3_out1), + wire_of(out1_hold), ) + out1_hold.set(out1_commit) + domain.next() - out_vld = cas(domain, domain.cycle(c3_vld_out, name="pe_int_s3_vld_out"), cycle=0) - out0 = cas(domain, domain.cycle(wire_of(c3_out0_raw)[0:19], name="pe_int_s3_out0"), cycle=0) - out1 = cas(domain, domain.cycle(out1, name="pe_int_s3_out1"), cycle=0) + out_vld = _reg_sig(domain, s2_vld, "pe_int_out_vld") + out0 = _reg_sig(domain, c3_out0, "pe_int_out0") + out1 = _reg_sig(domain, out1_commit, "pe_int_out1") m.output("vld_out", wire_of(out_vld)) m.output("out0", wire_of(out0)) m.output("out1", wire_of(out1)) -build.__pycircuit_name__ = "pe_int_fix7" +build.__pycircuit_name__ = "pe_int_ds_v05" def emit_mlir(latency: int = DEFAULT_PIPELINE_L) -> str: diff --git a/designs/PE_INT/python/pe_int_pycircuit.py b/designs/PE_INT/python/pe_int_pycircuit.py index d9d16e6..07f9dc9 100644 --- a/designs/PE_INT/python/pe_int_pycircuit.py +++ b/designs/PE_INT/python/pe_int_pycircuit.py @@ -2,9 +2,9 @@ from pathlib import Path -from pe_int import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, build, emit_mlir +from pe_int import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, SPEC_LATENCY_L, build, emit_mlir -build.__pycircuit_name__ = "pe_int_fix7" +build.__pycircuit_name__ = "pe_int_ds_v05" __all__ = [ "MODE_2A", @@ -12,6 +12,7 @@ "MODE_2C", "MODE_2D", "DEFAULT_PIPELINE_L", + "SPEC_LATENCY_L", "build", "emit_mlir", ] diff --git a/designs/PE_INT/rtl/README.md b/designs/PE_INT/rtl/README.md index 5ff95e6..b2021ee 100644 --- a/designs/PE_INT/rtl/README.md +++ b/designs/PE_INT/rtl/README.md @@ -1,19 +1,25 @@ -# Generated RTL - -`rtl/` only stores outputs generated by the `pyCircuit` / `pycc` build flow. - -## Generation - -Run at repo root: - -```bash -python python/build.py --target rtl --out-dir build/pe_int -``` - -Artifact paths may differ by `pycircuit.cli build` version, usually under `build/pe_int/`. - -## Rules - -- Do not handwrite `rtl/*.v`. -- RTL content must be sourced only from `python/pe_int_pycircuit.py` and `tb/tb_pe_int_pycircuit.py`. -- Use `tb_rtl/` for RTL simulations (do not move RTL testcases back into `tb/`). +# Generated RTL + +`rtl/build/` stores outputs generated by the `pyCircuit` / `pycc` build flow. + +## Generation + +Run at repo root: + +```bash +python python/build.py --target both --out-dir build/pe_int +``` + +Artifact paths may differ by `pycircuit.cli build` version, usually under `build/pe_int/`. + +After each build, the flow must copy deliverable RTL artifacts from the build +output tree into `rtl/build/`, then refresh `filelist/pe_int.f`. + +## Rules + +- Do not handwrite `rtl/build/*.v`. +- Keep `rtl/build/` as the delivery mirror of the latest build output artifacts. +- Refresh `filelist/pe_int.f` after each build sync. +- Deliverable top-level reset interface must match spec (`rst_n` only); do not expose extra reset IO. +- RTL content must be sourced only from `python/pe_int_pycircuit.py` and `tb/tb_pe_int_pycircuit.py`. +- Use `tb_rtl/` for RTL simulations (do not move RTL testcases back into `tb/`). diff --git a/designs/PE_INT/rtl/build/pe_int_l3.v b/designs/PE_INT/rtl/build/pe_int_l3.v new file mode 100644 index 0000000..ba6c4f4 --- /dev/null +++ b/designs/PE_INT/rtl/build/pe_int_l3.v @@ -0,0 +1,2533 @@ +// Generated by pycc (pyCircuit) +// Module: pe_int_ds_v05 + +module pe_int_l3 ( + input clk, + input rst_n, + input vld, + input [1:0] mode, + input [79:0] a, + input [79:0] b, + input [79:0] b1, + input [1:0] e1_a, + input [1:0] e1_b0, + input [1:0] e1_b1, + output vld_out, + output [18:0] out0, + output [15:0] out1 +); + +wire rst; +assign rst = ~rst_n; + + +wire [18:0] c3_out0___pycircuit_v5_strip_domain___L64; // pyc.name="c3_out0____L64" +wire [31:0] c3_out0_raw___pycircuit_v5_strip_domain___L63; // pyc.name="c3_out0_raw____L63" +wire [15:0] c3_out1___pycircuit_v5_strip_domain___L65; // pyc.name="c3_out1____L65" +wire [31:0] c3_out1_raw___pycircuit_v5_strip_domain___L63; // pyc.name="c3_out1_raw____L63" +wire [15:0] out1_commit___pycircuit_v5_strip_domain___L67; // pyc.name="out1_commit____L67" +wire [18:0] pe_int_out0; // pyc.name="pe_int_out0" +wire [18:0] pe_int_out0__next; // pyc.name="pe_int_out0__next" +wire [15:0] pe_int_out1; // pyc.name="pe_int_out1" +wire [15:0] pe_int_out1__next; // pyc.name="pe_int_out1__next" +wire [15:0] pe_int_out1_hold; // pyc.name="pe_int_out1_hold" +wire [15:0] pe_int_out1_hold__next; // pyc.name="pe_int_out1_hold__next" +wire pe_int_out_vld; // pyc.name="pe_int_out_vld" +wire pe_int_out_vld__next; // pyc.name="pe_int_out_vld__next" +wire [79:0] pe_int_s0_a; // pyc.name="pe_int_s0_a" +wire [79:0] pe_int_s0_a__next; // pyc.name="pe_int_s0_a__next" +wire [79:0] pe_int_s0_b; // pyc.name="pe_int_s0_b" +wire [79:0] pe_int_s0_b1; // pyc.name="pe_int_s0_b1" +wire [79:0] pe_int_s0_b1__next; // pyc.name="pe_int_s0_b1__next" +wire [79:0] pe_int_s0_b__next; // pyc.name="pe_int_s0_b__next" +wire [1:0] pe_int_s0_e1_a; // pyc.name="pe_int_s0_e1_a" +wire [1:0] pe_int_s0_e1_a__next; // pyc.name="pe_int_s0_e1_a__next" +wire [1:0] pe_int_s0_e1_b0; // pyc.name="pe_int_s0_e1_b0" +wire [1:0] pe_int_s0_e1_b0__next; // pyc.name="pe_int_s0_e1_b0__next" +wire [1:0] pe_int_s0_e1_b1; // pyc.name="pe_int_s0_e1_b1" +wire [1:0] pe_int_s0_e1_b1__next; // pyc.name="pe_int_s0_e1_b1__next" +wire pe_int_s0_is_2a; // pyc.name="pe_int_s0_is_2a" +wire pe_int_s0_is_2a__next; // pyc.name="pe_int_s0_is_2a__next" +wire pe_int_s0_is_2b; // pyc.name="pe_int_s0_is_2b" +wire pe_int_s0_is_2b__next; // pyc.name="pe_int_s0_is_2b__next" +wire pe_int_s0_is_2c; // pyc.name="pe_int_s0_is_2c" +wire pe_int_s0_is_2c__next; // pyc.name="pe_int_s0_is_2c__next" +wire pe_int_s0_is_2d; // pyc.name="pe_int_s0_is_2d" +wire pe_int_s0_is_2d__next; // pyc.name="pe_int_s0_is_2d__next" +wire pe_int_s0_vld; // pyc.name="pe_int_s0_vld" +wire pe_int_s0_vld__next; // pyc.name="pe_int_s0_vld__next" +wire [1:0] pe_int_s1_e1_a; // pyc.name="pe_int_s1_e1_a" +wire [1:0] pe_int_s1_e1_a__next; // pyc.name="pe_int_s1_e1_a__next" +wire [1:0] pe_int_s1_e1_b0; // pyc.name="pe_int_s1_e1_b0" +wire [1:0] pe_int_s1_e1_b0__next; // pyc.name="pe_int_s1_e1_b0__next" +wire [1:0] pe_int_s1_e1_b1; // pyc.name="pe_int_s1_e1_b1" +wire [1:0] pe_int_s1_e1_b1__next; // pyc.name="pe_int_s1_e1_b1__next" +wire pe_int_s1_is_2a; // pyc.name="pe_int_s1_is_2a" +wire pe_int_s1_is_2a__next; // pyc.name="pe_int_s1_is_2a__next" +wire pe_int_s1_is_2b; // pyc.name="pe_int_s1_is_2b" +wire pe_int_s1_is_2b__next; // pyc.name="pe_int_s1_is_2b__next" +wire pe_int_s1_is_2c; // pyc.name="pe_int_s1_is_2c" +wire pe_int_s1_is_2c__next; // pyc.name="pe_int_s1_is_2c__next" +wire pe_int_s1_is_2d__next; // pyc.name="pe_int_s1_is_2d__next" +wire [31:0] pe_int_s1_p2a_0; // pyc.name="pe_int_s1_p2a_0" +wire [31:0] pe_int_s1_p2a_0__next; // pyc.name="pe_int_s1_p2a_0__next" +wire [31:0] pe_int_s1_p2a_1; // pyc.name="pe_int_s1_p2a_1" +wire [31:0] pe_int_s1_p2a_1__next; // pyc.name="pe_int_s1_p2a_1__next" +wire [31:0] pe_int_s1_p2a_2; // pyc.name="pe_int_s1_p2a_2" +wire [31:0] pe_int_s1_p2a_2__next; // pyc.name="pe_int_s1_p2a_2__next" +wire [31:0] pe_int_s1_p2a_3; // pyc.name="pe_int_s1_p2a_3" +wire [31:0] pe_int_s1_p2a_3__next; // pyc.name="pe_int_s1_p2a_3__next" +wire [31:0] pe_int_s1_p2a_4; // pyc.name="pe_int_s1_p2a_4" +wire [31:0] pe_int_s1_p2a_4__next; // pyc.name="pe_int_s1_p2a_4__next" +wire [31:0] pe_int_s1_p2a_5; // pyc.name="pe_int_s1_p2a_5" +wire [31:0] pe_int_s1_p2a_5__next; // pyc.name="pe_int_s1_p2a_5__next" +wire [31:0] pe_int_s1_p2a_6; // pyc.name="pe_int_s1_p2a_6" +wire [31:0] pe_int_s1_p2a_6__next; // pyc.name="pe_int_s1_p2a_6__next" +wire [31:0] pe_int_s1_p2a_7; // pyc.name="pe_int_s1_p2a_7" +wire [31:0] pe_int_s1_p2a_7__next; // pyc.name="pe_int_s1_p2a_7__next" +wire [31:0] pe_int_s1_p2b0_0; // pyc.name="pe_int_s1_p2b0_0" +wire [31:0] pe_int_s1_p2b0_0__next; // pyc.name="pe_int_s1_p2b0_0__next" +wire [31:0] pe_int_s1_p2b0_1; // pyc.name="pe_int_s1_p2b0_1" +wire [31:0] pe_int_s1_p2b0_1__next; // pyc.name="pe_int_s1_p2b0_1__next" +wire [31:0] pe_int_s1_p2b0_2; // pyc.name="pe_int_s1_p2b0_2" +wire [31:0] pe_int_s1_p2b0_2__next; // pyc.name="pe_int_s1_p2b0_2__next" +wire [31:0] pe_int_s1_p2b0_3; // pyc.name="pe_int_s1_p2b0_3" +wire [31:0] pe_int_s1_p2b0_3__next; // pyc.name="pe_int_s1_p2b0_3__next" +wire [31:0] pe_int_s1_p2b0_4; // pyc.name="pe_int_s1_p2b0_4" +wire [31:0] pe_int_s1_p2b0_4__next; // pyc.name="pe_int_s1_p2b0_4__next" +wire [31:0] pe_int_s1_p2b0_5; // pyc.name="pe_int_s1_p2b0_5" +wire [31:0] pe_int_s1_p2b0_5__next; // pyc.name="pe_int_s1_p2b0_5__next" +wire [31:0] pe_int_s1_p2b0_6; // pyc.name="pe_int_s1_p2b0_6" +wire [31:0] pe_int_s1_p2b0_6__next; // pyc.name="pe_int_s1_p2b0_6__next" +wire [31:0] pe_int_s1_p2b0_7; // pyc.name="pe_int_s1_p2b0_7" +wire [31:0] pe_int_s1_p2b0_7__next; // pyc.name="pe_int_s1_p2b0_7__next" +wire [31:0] pe_int_s1_p2b1_0; // pyc.name="pe_int_s1_p2b1_0" +wire [31:0] pe_int_s1_p2b1_0__next; // pyc.name="pe_int_s1_p2b1_0__next" +wire [31:0] pe_int_s1_p2b1_1; // pyc.name="pe_int_s1_p2b1_1" +wire [31:0] pe_int_s1_p2b1_1__next; // pyc.name="pe_int_s1_p2b1_1__next" +wire [31:0] pe_int_s1_p2b1_2; // pyc.name="pe_int_s1_p2b1_2" +wire [31:0] pe_int_s1_p2b1_2__next; // pyc.name="pe_int_s1_p2b1_2__next" +wire [31:0] pe_int_s1_p2b1_3; // pyc.name="pe_int_s1_p2b1_3" +wire [31:0] pe_int_s1_p2b1_3__next; // pyc.name="pe_int_s1_p2b1_3__next" +wire [31:0] pe_int_s1_p2b1_4; // pyc.name="pe_int_s1_p2b1_4" +wire [31:0] pe_int_s1_p2b1_4__next; // pyc.name="pe_int_s1_p2b1_4__next" +wire [31:0] pe_int_s1_p2b1_5; // pyc.name="pe_int_s1_p2b1_5" +wire [31:0] pe_int_s1_p2b1_5__next; // pyc.name="pe_int_s1_p2b1_5__next" +wire [31:0] pe_int_s1_p2b1_6; // pyc.name="pe_int_s1_p2b1_6" +wire [31:0] pe_int_s1_p2b1_6__next; // pyc.name="pe_int_s1_p2b1_6__next" +wire [31:0] pe_int_s1_p2b1_7; // pyc.name="pe_int_s1_p2b1_7" +wire [31:0] pe_int_s1_p2b1_7__next; // pyc.name="pe_int_s1_p2b1_7__next" +wire [31:0] pe_int_s1_p2c0_0; // pyc.name="pe_int_s1_p2c0_0" +wire [31:0] pe_int_s1_p2c0_0__next; // pyc.name="pe_int_s1_p2c0_0__next" +wire [31:0] pe_int_s1_p2c0_1; // pyc.name="pe_int_s1_p2c0_1" +wire [31:0] pe_int_s1_p2c0_10; // pyc.name="pe_int_s1_p2c0_10" +wire [31:0] pe_int_s1_p2c0_10__next; // pyc.name="pe_int_s1_p2c0_10__next" +wire [31:0] pe_int_s1_p2c0_11; // pyc.name="pe_int_s1_p2c0_11" +wire [31:0] pe_int_s1_p2c0_11__next; // pyc.name="pe_int_s1_p2c0_11__next" +wire [31:0] pe_int_s1_p2c0_12; // pyc.name="pe_int_s1_p2c0_12" +wire [31:0] pe_int_s1_p2c0_12__next; // pyc.name="pe_int_s1_p2c0_12__next" +wire [31:0] pe_int_s1_p2c0_13; // pyc.name="pe_int_s1_p2c0_13" +wire [31:0] pe_int_s1_p2c0_13__next; // pyc.name="pe_int_s1_p2c0_13__next" +wire [31:0] pe_int_s1_p2c0_14; // pyc.name="pe_int_s1_p2c0_14" +wire [31:0] pe_int_s1_p2c0_14__next; // pyc.name="pe_int_s1_p2c0_14__next" +wire [31:0] pe_int_s1_p2c0_15; // pyc.name="pe_int_s1_p2c0_15" +wire [31:0] pe_int_s1_p2c0_15__next; // pyc.name="pe_int_s1_p2c0_15__next" +wire [31:0] pe_int_s1_p2c0_1__next; // pyc.name="pe_int_s1_p2c0_1__next" +wire [31:0] pe_int_s1_p2c0_2; // pyc.name="pe_int_s1_p2c0_2" +wire [31:0] pe_int_s1_p2c0_2__next; // pyc.name="pe_int_s1_p2c0_2__next" +wire [31:0] pe_int_s1_p2c0_3; // pyc.name="pe_int_s1_p2c0_3" +wire [31:0] pe_int_s1_p2c0_3__next; // pyc.name="pe_int_s1_p2c0_3__next" +wire [31:0] pe_int_s1_p2c0_4; // pyc.name="pe_int_s1_p2c0_4" +wire [31:0] pe_int_s1_p2c0_4__next; // pyc.name="pe_int_s1_p2c0_4__next" +wire [31:0] pe_int_s1_p2c0_5; // pyc.name="pe_int_s1_p2c0_5" +wire [31:0] pe_int_s1_p2c0_5__next; // pyc.name="pe_int_s1_p2c0_5__next" +wire [31:0] pe_int_s1_p2c0_6; // pyc.name="pe_int_s1_p2c0_6" +wire [31:0] pe_int_s1_p2c0_6__next; // pyc.name="pe_int_s1_p2c0_6__next" +wire [31:0] pe_int_s1_p2c0_7; // pyc.name="pe_int_s1_p2c0_7" +wire [31:0] pe_int_s1_p2c0_7__next; // pyc.name="pe_int_s1_p2c0_7__next" +wire [31:0] pe_int_s1_p2c0_8; // pyc.name="pe_int_s1_p2c0_8" +wire [31:0] pe_int_s1_p2c0_8__next; // pyc.name="pe_int_s1_p2c0_8__next" +wire [31:0] pe_int_s1_p2c0_9; // pyc.name="pe_int_s1_p2c0_9" +wire [31:0] pe_int_s1_p2c0_9__next; // pyc.name="pe_int_s1_p2c0_9__next" +wire [31:0] pe_int_s1_p2c1_0; // pyc.name="pe_int_s1_p2c1_0" +wire [31:0] pe_int_s1_p2c1_0__next; // pyc.name="pe_int_s1_p2c1_0__next" +wire [31:0] pe_int_s1_p2c1_1; // pyc.name="pe_int_s1_p2c1_1" +wire [31:0] pe_int_s1_p2c1_10; // pyc.name="pe_int_s1_p2c1_10" +wire [31:0] pe_int_s1_p2c1_10__next; // pyc.name="pe_int_s1_p2c1_10__next" +wire [31:0] pe_int_s1_p2c1_11; // pyc.name="pe_int_s1_p2c1_11" +wire [31:0] pe_int_s1_p2c1_11__next; // pyc.name="pe_int_s1_p2c1_11__next" +wire [31:0] pe_int_s1_p2c1_12; // pyc.name="pe_int_s1_p2c1_12" +wire [31:0] pe_int_s1_p2c1_12__next; // pyc.name="pe_int_s1_p2c1_12__next" +wire [31:0] pe_int_s1_p2c1_13; // pyc.name="pe_int_s1_p2c1_13" +wire [31:0] pe_int_s1_p2c1_13__next; // pyc.name="pe_int_s1_p2c1_13__next" +wire [31:0] pe_int_s1_p2c1_14; // pyc.name="pe_int_s1_p2c1_14" +wire [31:0] pe_int_s1_p2c1_14__next; // pyc.name="pe_int_s1_p2c1_14__next" +wire [31:0] pe_int_s1_p2c1_15; // pyc.name="pe_int_s1_p2c1_15" +wire [31:0] pe_int_s1_p2c1_15__next; // pyc.name="pe_int_s1_p2c1_15__next" +wire [31:0] pe_int_s1_p2c1_1__next; // pyc.name="pe_int_s1_p2c1_1__next" +wire [31:0] pe_int_s1_p2c1_2; // pyc.name="pe_int_s1_p2c1_2" +wire [31:0] pe_int_s1_p2c1_2__next; // pyc.name="pe_int_s1_p2c1_2__next" +wire [31:0] pe_int_s1_p2c1_3; // pyc.name="pe_int_s1_p2c1_3" +wire [31:0] pe_int_s1_p2c1_3__next; // pyc.name="pe_int_s1_p2c1_3__next" +wire [31:0] pe_int_s1_p2c1_4; // pyc.name="pe_int_s1_p2c1_4" +wire [31:0] pe_int_s1_p2c1_4__next; // pyc.name="pe_int_s1_p2c1_4__next" +wire [31:0] pe_int_s1_p2c1_5; // pyc.name="pe_int_s1_p2c1_5" +wire [31:0] pe_int_s1_p2c1_5__next; // pyc.name="pe_int_s1_p2c1_5__next" +wire [31:0] pe_int_s1_p2c1_6; // pyc.name="pe_int_s1_p2c1_6" +wire [31:0] pe_int_s1_p2c1_6__next; // pyc.name="pe_int_s1_p2c1_6__next" +wire [31:0] pe_int_s1_p2c1_7; // pyc.name="pe_int_s1_p2c1_7" +wire [31:0] pe_int_s1_p2c1_7__next; // pyc.name="pe_int_s1_p2c1_7__next" +wire [31:0] pe_int_s1_p2c1_8; // pyc.name="pe_int_s1_p2c1_8" +wire [31:0] pe_int_s1_p2c1_8__next; // pyc.name="pe_int_s1_p2c1_8__next" +wire [31:0] pe_int_s1_p2c1_9; // pyc.name="pe_int_s1_p2c1_9" +wire [31:0] pe_int_s1_p2c1_9__next; // pyc.name="pe_int_s1_p2c1_9__next" +wire [31:0] pe_int_s1_p2d0_0; // pyc.name="pe_int_s1_p2d0_0" +wire [31:0] pe_int_s1_p2d0_0__next; // pyc.name="pe_int_s1_p2d0_0__next" +wire [31:0] pe_int_s1_p2d0_1; // pyc.name="pe_int_s1_p2d0_1" +wire [31:0] pe_int_s1_p2d0_1__next; // pyc.name="pe_int_s1_p2d0_1__next" +wire [31:0] pe_int_s1_p2d0_2; // pyc.name="pe_int_s1_p2d0_2" +wire [31:0] pe_int_s1_p2d0_2__next; // pyc.name="pe_int_s1_p2d0_2__next" +wire [31:0] pe_int_s1_p2d0_3; // pyc.name="pe_int_s1_p2d0_3" +wire [31:0] pe_int_s1_p2d0_3__next; // pyc.name="pe_int_s1_p2d0_3__next" +wire [31:0] pe_int_s1_p2d0_4; // pyc.name="pe_int_s1_p2d0_4" +wire [31:0] pe_int_s1_p2d0_4__next; // pyc.name="pe_int_s1_p2d0_4__next" +wire [31:0] pe_int_s1_p2d0_5; // pyc.name="pe_int_s1_p2d0_5" +wire [31:0] pe_int_s1_p2d0_5__next; // pyc.name="pe_int_s1_p2d0_5__next" +wire [31:0] pe_int_s1_p2d0_6; // pyc.name="pe_int_s1_p2d0_6" +wire [31:0] pe_int_s1_p2d0_6__next; // pyc.name="pe_int_s1_p2d0_6__next" +wire [31:0] pe_int_s1_p2d0_7; // pyc.name="pe_int_s1_p2d0_7" +wire [31:0] pe_int_s1_p2d0_7__next; // pyc.name="pe_int_s1_p2d0_7__next" +wire [31:0] pe_int_s1_p2d1_0; // pyc.name="pe_int_s1_p2d1_0" +wire [31:0] pe_int_s1_p2d1_0__next; // pyc.name="pe_int_s1_p2d1_0__next" +wire [31:0] pe_int_s1_p2d1_1; // pyc.name="pe_int_s1_p2d1_1" +wire [31:0] pe_int_s1_p2d1_1__next; // pyc.name="pe_int_s1_p2d1_1__next" +wire [31:0] pe_int_s1_p2d1_2; // pyc.name="pe_int_s1_p2d1_2" +wire [31:0] pe_int_s1_p2d1_2__next; // pyc.name="pe_int_s1_p2d1_2__next" +wire [31:0] pe_int_s1_p2d1_3; // pyc.name="pe_int_s1_p2d1_3" +wire [31:0] pe_int_s1_p2d1_3__next; // pyc.name="pe_int_s1_p2d1_3__next" +wire [31:0] pe_int_s1_p2d1_4; // pyc.name="pe_int_s1_p2d1_4" +wire [31:0] pe_int_s1_p2d1_4__next; // pyc.name="pe_int_s1_p2d1_4__next" +wire [31:0] pe_int_s1_p2d1_5; // pyc.name="pe_int_s1_p2d1_5" +wire [31:0] pe_int_s1_p2d1_5__next; // pyc.name="pe_int_s1_p2d1_5__next" +wire [31:0] pe_int_s1_p2d1_6; // pyc.name="pe_int_s1_p2d1_6" +wire [31:0] pe_int_s1_p2d1_6__next; // pyc.name="pe_int_s1_p2d1_6__next" +wire [31:0] pe_int_s1_p2d1_7; // pyc.name="pe_int_s1_p2d1_7" +wire [31:0] pe_int_s1_p2d1_7__next; // pyc.name="pe_int_s1_p2d1_7__next" +wire pe_int_s1_vld; // pyc.name="pe_int_s1_vld" +wire pe_int_s1_vld__next; // pyc.name="pe_int_s1_vld__next" +wire [1:0] pe_int_s2_e1_a; // pyc.name="pe_int_s2_e1_a" +wire [1:0] pe_int_s2_e1_a__next; // pyc.name="pe_int_s2_e1_a__next" +wire [1:0] pe_int_s2_e1_b0; // pyc.name="pe_int_s2_e1_b0" +wire [1:0] pe_int_s2_e1_b0__next; // pyc.name="pe_int_s2_e1_b0__next" +wire [1:0] pe_int_s2_e1_b1; // pyc.name="pe_int_s2_e1_b1" +wire [1:0] pe_int_s2_e1_b1__next; // pyc.name="pe_int_s2_e1_b1__next" +wire pe_int_s2_is_2a; // pyc.name="pe_int_s2_is_2a" +wire pe_int_s2_is_2a__next; // pyc.name="pe_int_s2_is_2a__next" +wire pe_int_s2_is_2b; // pyc.name="pe_int_s2_is_2b" +wire pe_int_s2_is_2b__next; // pyc.name="pe_int_s2_is_2b__next" +wire pe_int_s2_is_2c; // pyc.name="pe_int_s2_is_2c" +wire pe_int_s2_is_2c__next; // pyc.name="pe_int_s2_is_2c__next" +wire [31:0] pe_int_s2_s2a; // pyc.name="pe_int_s2_s2a" +wire [31:0] pe_int_s2_s2a__next; // pyc.name="pe_int_s2_s2a__next" +wire [31:0] pe_int_s2_s2b0; // pyc.name="pe_int_s2_s2b0" +wire [31:0] pe_int_s2_s2b0__next; // pyc.name="pe_int_s2_s2b0__next" +wire [31:0] pe_int_s2_s2b1; // pyc.name="pe_int_s2_s2b1" +wire [31:0] pe_int_s2_s2b1__next; // pyc.name="pe_int_s2_s2b1__next" +wire [31:0] pe_int_s2_s2c0_hi; // pyc.name="pe_int_s2_s2c0_hi" +wire [31:0] pe_int_s2_s2c0_hi__next; // pyc.name="pe_int_s2_s2c0_hi__next" +wire [31:0] pe_int_s2_s2c0_lo; // pyc.name="pe_int_s2_s2c0_lo" +wire [31:0] pe_int_s2_s2c0_lo__next; // pyc.name="pe_int_s2_s2c0_lo__next" +wire [31:0] pe_int_s2_s2c1_hi; // pyc.name="pe_int_s2_s2c1_hi" +wire [31:0] pe_int_s2_s2c1_hi__next; // pyc.name="pe_int_s2_s2c1_hi__next" +wire [31:0] pe_int_s2_s2c1_lo; // pyc.name="pe_int_s2_s2c1_lo" +wire [31:0] pe_int_s2_s2c1_lo__next; // pyc.name="pe_int_s2_s2c1_lo__next" +wire [31:0] pe_int_s2_s2d0; // pyc.name="pe_int_s2_s2d0" +wire [31:0] pe_int_s2_s2d0__next; // pyc.name="pe_int_s2_s2d0__next" +wire [31:0] pe_int_s2_s2d1; // pyc.name="pe_int_s2_s2d1" +wire [31:0] pe_int_s2_s2d1__next; // pyc.name="pe_int_s2_s2d1__next" +wire pe_int_s2_vld; // pyc.name="pe_int_s2_vld" +wire pe_int_s2_vld__next; // pyc.name="pe_int_s2_vld__next" +wire [31:0] pyc_add_485; // op=pyc.add +wire [31:0] pyc_add_486; // op=pyc.add +wire [31:0] pyc_add_487; // op=pyc.add +wire [31:0] pyc_add_488; // op=pyc.add +wire [31:0] pyc_add_489; // op=pyc.add +wire [31:0] pyc_add_490; // op=pyc.add +wire [31:0] pyc_add_491; // op=pyc.add +wire [31:0] pyc_add_492; // op=pyc.add +wire [31:0] pyc_add_493; // op=pyc.add +wire [31:0] pyc_add_494; // op=pyc.add +wire [31:0] pyc_add_495; // op=pyc.add +wire [31:0] pyc_add_496; // op=pyc.add +wire [31:0] pyc_add_497; // op=pyc.add +wire [31:0] pyc_add_498; // op=pyc.add +wire [31:0] pyc_add_499; // op=pyc.add +wire [31:0] pyc_add_500; // op=pyc.add +wire [31:0] pyc_add_501; // op=pyc.add +wire [31:0] pyc_add_502; // op=pyc.add +wire [31:0] pyc_add_503; // op=pyc.add +wire [31:0] pyc_add_504; // op=pyc.add +wire [31:0] pyc_add_505; // op=pyc.add +wire [31:0] pyc_add_506; // op=pyc.add +wire [31:0] pyc_add_507; // op=pyc.add +wire [31:0] pyc_add_508; // op=pyc.add +wire [31:0] pyc_add_509; // op=pyc.add +wire [31:0] pyc_add_510; // op=pyc.add +wire [31:0] pyc_add_511; // op=pyc.add +wire [31:0] pyc_add_512; // op=pyc.add +wire [31:0] pyc_add_513; // op=pyc.add +wire [31:0] pyc_add_514; // op=pyc.add +wire [31:0] pyc_add_515; // op=pyc.add +wire [31:0] pyc_add_516; // op=pyc.add +wire [31:0] pyc_add_517; // op=pyc.add +wire [31:0] pyc_add_518; // op=pyc.add +wire [31:0] pyc_add_519; // op=pyc.add +wire [31:0] pyc_add_520; // op=pyc.add +wire [31:0] pyc_add_521; // op=pyc.add +wire [31:0] pyc_add_522; // op=pyc.add +wire [31:0] pyc_add_523; // op=pyc.add +wire [31:0] pyc_add_524; // op=pyc.add +wire [31:0] pyc_add_525; // op=pyc.add +wire [31:0] pyc_add_526; // op=pyc.add +wire [31:0] pyc_add_527; // op=pyc.add +wire [31:0] pyc_add_528; // op=pyc.add +wire [31:0] pyc_add_529; // op=pyc.add +wire [31:0] pyc_add_530; // op=pyc.add +wire [31:0] pyc_add_531; // op=pyc.add +wire [31:0] pyc_add_532; // op=pyc.add +wire [31:0] pyc_add_533; // op=pyc.add +wire [31:0] pyc_add_534; // op=pyc.add +wire [31:0] pyc_add_535; // op=pyc.add +wire [31:0] pyc_add_536; // op=pyc.add +wire [31:0] pyc_add_537; // op=pyc.add +wire [31:0] pyc_add_538; // op=pyc.add +wire [31:0] pyc_add_539; // op=pyc.add +wire [31:0] pyc_add_540; // op=pyc.add +wire [31:0] pyc_add_541; // op=pyc.add +wire [31:0] pyc_add_542; // op=pyc.add +wire [31:0] pyc_add_543; // op=pyc.add +wire [31:0] pyc_add_544; // op=pyc.add +wire [31:0] pyc_add_545; // op=pyc.add +wire [31:0] pyc_add_546; // op=pyc.add +wire [31:0] pyc_add_547; // op=pyc.add +wire [1:0] pyc_add_587; // op=pyc.add +wire [1:0] pyc_add_592; // op=pyc.add +wire [31:0] pyc_add_593; // op=pyc.add +wire [31:0] pyc_add_594; // op=pyc.add +wire [31:0] pyc_add_599; // op=pyc.add +wire [31:0] pyc_add_600; // op=pyc.add +wire [31:0] pyc_add_605; // op=pyc.add +wire [1:0] pyc_add_608; // op=pyc.add +wire [1:0] pyc_add_611; // op=pyc.add +wire [31:0] pyc_add_612; // op=pyc.add +wire [31:0] pyc_add_613; // op=pyc.add +wire [31:0] pyc_add_618; // op=pyc.add +wire [31:0] pyc_add_619; // op=pyc.add +wire [31:0] pyc_add_624; // op=pyc.add +wire [18:0] pyc_comb_15; // op=pyc.comb +wire [15:0] pyc_comb_16; // op=pyc.comb +wire [1:0] pyc_comb_17; // op=pyc.comb +wire [31:0] pyc_comb_18; // op=pyc.comb +wire [1:0] pyc_comb_19; // op=pyc.comb +wire [79:0] pyc_comb_20; // op=pyc.comb +wire pyc_comb_21; // op=pyc.comb +wire pyc_comb_22; // op=pyc.comb +wire [1:0] pyc_comb_23; // op=pyc.comb +wire [1:0] pyc_comb_24; // op=pyc.comb +wire [1:0] pyc_comb_25; // op=pyc.comb +wire [79:0] pyc_comb_26; // op=pyc.comb +wire [79:0] pyc_comb_27; // op=pyc.comb +wire [79:0] pyc_comb_28; // op=pyc.comb +wire pyc_comb_29; // op=pyc.comb +wire pyc_comb_30; // op=pyc.comb +wire pyc_comb_31; // op=pyc.comb +wire pyc_comb_32; // op=pyc.comb +wire [1:0] pyc_comb_325; // op=pyc.comb +wire [31:0] pyc_comb_326; // op=pyc.comb +wire [31:0] pyc_comb_327; // op=pyc.comb +wire [31:0] pyc_comb_328; // op=pyc.comb +wire [31:0] pyc_comb_329; // op=pyc.comb +wire pyc_comb_33; // op=pyc.comb +wire [31:0] pyc_comb_330; // op=pyc.comb +wire [31:0] pyc_comb_331; // op=pyc.comb +wire [31:0] pyc_comb_332; // op=pyc.comb +wire [31:0] pyc_comb_333; // op=pyc.comb +wire [31:0] pyc_comb_334; // op=pyc.comb +wire [31:0] pyc_comb_335; // op=pyc.comb +wire [31:0] pyc_comb_336; // op=pyc.comb +wire [31:0] pyc_comb_337; // op=pyc.comb +wire [31:0] pyc_comb_338; // op=pyc.comb +wire [31:0] pyc_comb_339; // op=pyc.comb +wire [31:0] pyc_comb_340; // op=pyc.comb +wire [31:0] pyc_comb_341; // op=pyc.comb +wire [31:0] pyc_comb_342; // op=pyc.comb +wire [31:0] pyc_comb_343; // op=pyc.comb +wire [31:0] pyc_comb_344; // op=pyc.comb +wire [31:0] pyc_comb_345; // op=pyc.comb +wire [31:0] pyc_comb_346; // op=pyc.comb +wire [31:0] pyc_comb_347; // op=pyc.comb +wire [31:0] pyc_comb_348; // op=pyc.comb +wire [31:0] pyc_comb_349; // op=pyc.comb +wire pyc_comb_35; // op=pyc.comb +wire [31:0] pyc_comb_350; // op=pyc.comb +wire [31:0] pyc_comb_351; // op=pyc.comb +wire [31:0] pyc_comb_352; // op=pyc.comb +wire [31:0] pyc_comb_353; // op=pyc.comb +wire [31:0] pyc_comb_354; // op=pyc.comb +wire [31:0] pyc_comb_355; // op=pyc.comb +wire [31:0] pyc_comb_356; // op=pyc.comb +wire [31:0] pyc_comb_357; // op=pyc.comb +wire [31:0] pyc_comb_358; // op=pyc.comb +wire [31:0] pyc_comb_359; // op=pyc.comb +wire [31:0] pyc_comb_360; // op=pyc.comb +wire [31:0] pyc_comb_361; // op=pyc.comb +wire [31:0] pyc_comb_362; // op=pyc.comb +wire [31:0] pyc_comb_363; // op=pyc.comb +wire [31:0] pyc_comb_364; // op=pyc.comb +wire [31:0] pyc_comb_365; // op=pyc.comb +wire [31:0] pyc_comb_366; // op=pyc.comb +wire [31:0] pyc_comb_367; // op=pyc.comb +wire [31:0] pyc_comb_368; // op=pyc.comb +wire [31:0] pyc_comb_369; // op=pyc.comb +wire pyc_comb_37; // op=pyc.comb +wire [31:0] pyc_comb_370; // op=pyc.comb +wire [31:0] pyc_comb_371; // op=pyc.comb +wire [31:0] pyc_comb_372; // op=pyc.comb +wire [31:0] pyc_comb_373; // op=pyc.comb +wire [31:0] pyc_comb_374; // op=pyc.comb +wire [31:0] pyc_comb_375; // op=pyc.comb +wire [31:0] pyc_comb_376; // op=pyc.comb +wire [31:0] pyc_comb_377; // op=pyc.comb +wire [31:0] pyc_comb_378; // op=pyc.comb +wire [31:0] pyc_comb_379; // op=pyc.comb +wire [31:0] pyc_comb_380; // op=pyc.comb +wire [31:0] pyc_comb_381; // op=pyc.comb +wire [31:0] pyc_comb_382; // op=pyc.comb +wire [31:0] pyc_comb_383; // op=pyc.comb +wire [31:0] pyc_comb_384; // op=pyc.comb +wire [31:0] pyc_comb_385; // op=pyc.comb +wire [31:0] pyc_comb_386; // op=pyc.comb +wire [31:0] pyc_comb_387; // op=pyc.comb +wire [31:0] pyc_comb_388; // op=pyc.comb +wire [31:0] pyc_comb_389; // op=pyc.comb +wire pyc_comb_39; // op=pyc.comb +wire [31:0] pyc_comb_390; // op=pyc.comb +wire [31:0] pyc_comb_391; // op=pyc.comb +wire [31:0] pyc_comb_392; // op=pyc.comb +wire [31:0] pyc_comb_393; // op=pyc.comb +wire [31:0] pyc_comb_394; // op=pyc.comb +wire [31:0] pyc_comb_395; // op=pyc.comb +wire [31:0] pyc_comb_396; // op=pyc.comb +wire [31:0] pyc_comb_397; // op=pyc.comb +wire pyc_comb_399; // op=pyc.comb +wire pyc_comb_401; // op=pyc.comb +wire pyc_comb_403; // op=pyc.comb +wire pyc_comb_405; // op=pyc.comb +wire [1:0] pyc_comb_408; // op=pyc.comb +wire pyc_comb_41; // op=pyc.comb +wire [1:0] pyc_comb_410; // op=pyc.comb +wire [1:0] pyc_comb_412; // op=pyc.comb +wire pyc_comb_43; // op=pyc.comb +wire [1:0] pyc_comb_48; // op=pyc.comb +wire [1:0] pyc_comb_50; // op=pyc.comb +wire [31:0] pyc_comb_548; // op=pyc.comb +wire [31:0] pyc_comb_549; // op=pyc.comb +wire [31:0] pyc_comb_550; // op=pyc.comb +wire [31:0] pyc_comb_551; // op=pyc.comb +wire [31:0] pyc_comb_552; // op=pyc.comb +wire [31:0] pyc_comb_553; // op=pyc.comb +wire [31:0] pyc_comb_554; // op=pyc.comb +wire [31:0] pyc_comb_555; // op=pyc.comb +wire [31:0] pyc_comb_556; // op=pyc.comb +wire pyc_comb_560; // op=pyc.comb +wire pyc_comb_561; // op=pyc.comb +wire [2:0] pyc_comb_562; // op=pyc.comb +wire [2:0] pyc_comb_563; // op=pyc.comb +wire pyc_comb_568; // op=pyc.comb +wire pyc_comb_569; // op=pyc.comb +wire pyc_comb_570; // op=pyc.comb +wire [18:0] pyc_comb_633; // op=pyc.comb +wire [15:0] pyc_comb_634; // op=pyc.comb +wire [15:0] pyc_comb_638; // op=pyc.comb +wire [15:0] pyc_comb_639; // op=pyc.comb +wire [7:0] pyc_concat_107; // op=pyc.concat +wire [7:0] pyc_concat_113; // op=pyc.concat +wire [7:0] pyc_concat_132; // op=pyc.concat +wire [7:0] pyc_concat_138; // op=pyc.concat +wire [7:0] pyc_concat_157; // op=pyc.concat +wire [7:0] pyc_concat_159; // op=pyc.concat +wire [7:0] pyc_concat_178; // op=pyc.concat +wire [7:0] pyc_concat_180; // op=pyc.concat +wire [7:0] pyc_concat_199; // op=pyc.concat +wire [7:0] pyc_concat_201; // op=pyc.concat +wire [7:0] pyc_concat_220; // op=pyc.concat +wire [7:0] pyc_concat_224; // op=pyc.concat +wire [2:0] pyc_concat_558; // op=pyc.concat +wire [2:0] pyc_concat_559; // op=pyc.concat +wire [7:0] pyc_concat_57; // op=pyc.concat +wire [7:0] pyc_concat_63; // op=pyc.concat +wire [7:0] pyc_concat_82; // op=pyc.concat +wire [7:0] pyc_concat_88; // op=pyc.concat +wire [18:0] pyc_constant_1; // op=pyc.constant +wire pyc_constant_10; // op=pyc.constant +wire [15:0] pyc_constant_2; // op=pyc.constant +wire [1:0] pyc_constant_3; // op=pyc.constant +wire [31:0] pyc_constant_4; // op=pyc.constant +wire [1:0] pyc_constant_5; // op=pyc.constant +wire [79:0] pyc_constant_6; // op=pyc.constant +wire [1:0] pyc_constant_7; // op=pyc.constant +wire [1:0] pyc_constant_8; // op=pyc.constant +wire pyc_constant_9; // op=pyc.constant +wire pyc_eq_11; // op=pyc.eq +wire pyc_eq_12; // op=pyc.eq +wire pyc_eq_13; // op=pyc.eq +wire pyc_eq_14; // op=pyc.eq +wire pyc_eq_595; // op=pyc.eq +wire pyc_eq_596; // op=pyc.eq +wire pyc_eq_601; // op=pyc.eq +wire pyc_eq_602; // op=pyc.eq +wire pyc_eq_614; // op=pyc.eq +wire pyc_eq_615; // op=pyc.eq +wire pyc_eq_620; // op=pyc.eq +wire pyc_eq_621; // op=pyc.eq +wire [4:0] pyc_extract_103; // op=pyc.extract +wire [4:0] pyc_extract_104; // op=pyc.extract +wire [3:0] pyc_extract_105; // op=pyc.extract +wire [3:0] pyc_extract_106; // op=pyc.extract +wire [4:0] pyc_extract_109; // op=pyc.extract +wire [4:0] pyc_extract_110; // op=pyc.extract +wire [3:0] pyc_extract_111; // op=pyc.extract +wire [3:0] pyc_extract_112; // op=pyc.extract +wire [4:0] pyc_extract_115; // op=pyc.extract +wire [3:0] pyc_extract_116; // op=pyc.extract +wire [4:0] pyc_extract_118; // op=pyc.extract +wire [3:0] pyc_extract_119; // op=pyc.extract +wire [4:0] pyc_extract_128; // op=pyc.extract +wire [4:0] pyc_extract_129; // op=pyc.extract +wire [3:0] pyc_extract_130; // op=pyc.extract +wire [3:0] pyc_extract_131; // op=pyc.extract +wire [4:0] pyc_extract_134; // op=pyc.extract +wire [4:0] pyc_extract_135; // op=pyc.extract +wire [3:0] pyc_extract_136; // op=pyc.extract +wire [3:0] pyc_extract_137; // op=pyc.extract +wire [4:0] pyc_extract_140; // op=pyc.extract +wire [3:0] pyc_extract_141; // op=pyc.extract +wire [4:0] pyc_extract_143; // op=pyc.extract +wire [3:0] pyc_extract_144; // op=pyc.extract +wire [4:0] pyc_extract_153; // op=pyc.extract +wire [4:0] pyc_extract_154; // op=pyc.extract +wire [3:0] pyc_extract_155; // op=pyc.extract +wire [3:0] pyc_extract_156; // op=pyc.extract +wire [4:0] pyc_extract_161; // op=pyc.extract +wire [3:0] pyc_extract_162; // op=pyc.extract +wire [4:0] pyc_extract_164; // op=pyc.extract +wire [3:0] pyc_extract_165; // op=pyc.extract +wire [4:0] pyc_extract_174; // op=pyc.extract +wire [4:0] pyc_extract_175; // op=pyc.extract +wire [3:0] pyc_extract_176; // op=pyc.extract +wire [3:0] pyc_extract_177; // op=pyc.extract +wire [4:0] pyc_extract_182; // op=pyc.extract +wire [3:0] pyc_extract_183; // op=pyc.extract +wire [4:0] pyc_extract_185; // op=pyc.extract +wire [3:0] pyc_extract_186; // op=pyc.extract +wire [4:0] pyc_extract_195; // op=pyc.extract +wire [4:0] pyc_extract_196; // op=pyc.extract +wire [3:0] pyc_extract_197; // op=pyc.extract +wire [3:0] pyc_extract_198; // op=pyc.extract +wire [4:0] pyc_extract_203; // op=pyc.extract +wire [3:0] pyc_extract_204; // op=pyc.extract +wire [4:0] pyc_extract_206; // op=pyc.extract +wire [3:0] pyc_extract_207; // op=pyc.extract +wire [4:0] pyc_extract_216; // op=pyc.extract +wire [4:0] pyc_extract_217; // op=pyc.extract +wire [3:0] pyc_extract_218; // op=pyc.extract +wire [3:0] pyc_extract_219; // op=pyc.extract +wire [4:0] pyc_extract_222; // op=pyc.extract +wire [3:0] pyc_extract_223; // op=pyc.extract +wire [4:0] pyc_extract_226; // op=pyc.extract +wire [3:0] pyc_extract_227; // op=pyc.extract +wire [4:0] pyc_extract_239; // op=pyc.extract +wire [4:0] pyc_extract_245; // op=pyc.extract +wire [4:0] pyc_extract_251; // op=pyc.extract +wire [4:0] pyc_extract_257; // op=pyc.extract +wire [4:0] pyc_extract_263; // op=pyc.extract +wire [4:0] pyc_extract_269; // op=pyc.extract +wire [4:0] pyc_extract_275; // op=pyc.extract +wire [4:0] pyc_extract_281; // op=pyc.extract +wire [4:0] pyc_extract_286; // op=pyc.extract +wire [4:0] pyc_extract_291; // op=pyc.extract +wire [4:0] pyc_extract_296; // op=pyc.extract +wire [4:0] pyc_extract_301; // op=pyc.extract +wire [4:0] pyc_extract_306; // op=pyc.extract +wire [4:0] pyc_extract_311; // op=pyc.extract +wire [4:0] pyc_extract_316; // op=pyc.extract +wire [4:0] pyc_extract_321; // op=pyc.extract +wire [39:0] pyc_extract_52; // op=pyc.extract +wire [4:0] pyc_extract_53; // op=pyc.extract +wire [4:0] pyc_extract_54; // op=pyc.extract +wire [3:0] pyc_extract_55; // op=pyc.extract +wire [3:0] pyc_extract_56; // op=pyc.extract +wire pyc_extract_565; // op=pyc.extract +wire pyc_extract_566; // op=pyc.extract +wire pyc_extract_567; // op=pyc.extract +wire pyc_extract_583; // op=pyc.extract +wire pyc_extract_585; // op=pyc.extract +wire pyc_extract_588; // op=pyc.extract +wire [4:0] pyc_extract_59; // op=pyc.extract +wire pyc_extract_590; // op=pyc.extract +wire [4:0] pyc_extract_60; // op=pyc.extract +wire pyc_extract_606; // op=pyc.extract +wire pyc_extract_609; // op=pyc.extract +wire [3:0] pyc_extract_61; // op=pyc.extract +wire [3:0] pyc_extract_62; // op=pyc.extract +wire [18:0] pyc_extract_631; // op=pyc.extract +wire [15:0] pyc_extract_632; // op=pyc.extract +wire [4:0] pyc_extract_65; // op=pyc.extract +wire [3:0] pyc_extract_66; // op=pyc.extract +wire [4:0] pyc_extract_68; // op=pyc.extract +wire [3:0] pyc_extract_69; // op=pyc.extract +wire [4:0] pyc_extract_78; // op=pyc.extract +wire [4:0] pyc_extract_79; // op=pyc.extract +wire [3:0] pyc_extract_80; // op=pyc.extract +wire [3:0] pyc_extract_81; // op=pyc.extract +wire [4:0] pyc_extract_84; // op=pyc.extract +wire [4:0] pyc_extract_85; // op=pyc.extract +wire [3:0] pyc_extract_86; // op=pyc.extract +wire [3:0] pyc_extract_87; // op=pyc.extract +wire [4:0] pyc_extract_90; // op=pyc.extract +wire [3:0] pyc_extract_91; // op=pyc.extract +wire [4:0] pyc_extract_93; // op=pyc.extract +wire [3:0] pyc_extract_94; // op=pyc.extract +wire [31:0] pyc_mul_100; // op=pyc.mul +wire [31:0] pyc_mul_101; // op=pyc.mul +wire [31:0] pyc_mul_102; // op=pyc.mul +wire [31:0] pyc_mul_123; // op=pyc.mul +wire [31:0] pyc_mul_124; // op=pyc.mul +wire [31:0] pyc_mul_125; // op=pyc.mul +wire [31:0] pyc_mul_126; // op=pyc.mul +wire [31:0] pyc_mul_127; // op=pyc.mul +wire [31:0] pyc_mul_148; // op=pyc.mul +wire [31:0] pyc_mul_149; // op=pyc.mul +wire [31:0] pyc_mul_150; // op=pyc.mul +wire [31:0] pyc_mul_151; // op=pyc.mul +wire [31:0] pyc_mul_152; // op=pyc.mul +wire [31:0] pyc_mul_169; // op=pyc.mul +wire [31:0] pyc_mul_170; // op=pyc.mul +wire [31:0] pyc_mul_171; // op=pyc.mul +wire [31:0] pyc_mul_172; // op=pyc.mul +wire [31:0] pyc_mul_173; // op=pyc.mul +wire [31:0] pyc_mul_190; // op=pyc.mul +wire [31:0] pyc_mul_191; // op=pyc.mul +wire [31:0] pyc_mul_192; // op=pyc.mul +wire [31:0] pyc_mul_193; // op=pyc.mul +wire [31:0] pyc_mul_194; // op=pyc.mul +wire [31:0] pyc_mul_211; // op=pyc.mul +wire [31:0] pyc_mul_212; // op=pyc.mul +wire [31:0] pyc_mul_213; // op=pyc.mul +wire [31:0] pyc_mul_214; // op=pyc.mul +wire [31:0] pyc_mul_215; // op=pyc.mul +wire [31:0] pyc_mul_232; // op=pyc.mul +wire [31:0] pyc_mul_233; // op=pyc.mul +wire [31:0] pyc_mul_234; // op=pyc.mul +wire [31:0] pyc_mul_235; // op=pyc.mul +wire [31:0] pyc_mul_236; // op=pyc.mul +wire [31:0] pyc_mul_241; // op=pyc.mul +wire [31:0] pyc_mul_242; // op=pyc.mul +wire [31:0] pyc_mul_247; // op=pyc.mul +wire [31:0] pyc_mul_248; // op=pyc.mul +wire [31:0] pyc_mul_253; // op=pyc.mul +wire [31:0] pyc_mul_254; // op=pyc.mul +wire [31:0] pyc_mul_259; // op=pyc.mul +wire [31:0] pyc_mul_260; // op=pyc.mul +wire [31:0] pyc_mul_265; // op=pyc.mul +wire [31:0] pyc_mul_266; // op=pyc.mul +wire [31:0] pyc_mul_271; // op=pyc.mul +wire [31:0] pyc_mul_272; // op=pyc.mul +wire [31:0] pyc_mul_277; // op=pyc.mul +wire [31:0] pyc_mul_278; // op=pyc.mul +wire [31:0] pyc_mul_283; // op=pyc.mul +wire [31:0] pyc_mul_284; // op=pyc.mul +wire [31:0] pyc_mul_288; // op=pyc.mul +wire [31:0] pyc_mul_289; // op=pyc.mul +wire [31:0] pyc_mul_293; // op=pyc.mul +wire [31:0] pyc_mul_294; // op=pyc.mul +wire [31:0] pyc_mul_298; // op=pyc.mul +wire [31:0] pyc_mul_299; // op=pyc.mul +wire [31:0] pyc_mul_303; // op=pyc.mul +wire [31:0] pyc_mul_304; // op=pyc.mul +wire [31:0] pyc_mul_308; // op=pyc.mul +wire [31:0] pyc_mul_309; // op=pyc.mul +wire [31:0] pyc_mul_313; // op=pyc.mul +wire [31:0] pyc_mul_314; // op=pyc.mul +wire [31:0] pyc_mul_318; // op=pyc.mul +wire [31:0] pyc_mul_319; // op=pyc.mul +wire [31:0] pyc_mul_323; // op=pyc.mul +wire [31:0] pyc_mul_324; // op=pyc.mul +wire [31:0] pyc_mul_73; // op=pyc.mul +wire [31:0] pyc_mul_74; // op=pyc.mul +wire [31:0] pyc_mul_75; // op=pyc.mul +wire [31:0] pyc_mul_76; // op=pyc.mul +wire [31:0] pyc_mul_77; // op=pyc.mul +wire [31:0] pyc_mul_98; // op=pyc.mul +wire [31:0] pyc_mul_99; // op=pyc.mul +wire [31:0] pyc_mux_597; // op=pyc.mux +wire [31:0] pyc_mux_598; // op=pyc.mux +wire [31:0] pyc_mux_603; // op=pyc.mux +wire [31:0] pyc_mux_604; // op=pyc.mux +wire [31:0] pyc_mux_616; // op=pyc.mux +wire [31:0] pyc_mux_617; // op=pyc.mux +wire [31:0] pyc_mux_622; // op=pyc.mux +wire [31:0] pyc_mux_623; // op=pyc.mux +wire [31:0] pyc_mux_625; // op=pyc.mux +wire [31:0] pyc_mux_626; // op=pyc.mux +wire [31:0] pyc_mux_627; // op=pyc.mux +wire [31:0] pyc_mux_628; // op=pyc.mux +wire [31:0] pyc_mux_629; // op=pyc.mux +wire [31:0] pyc_mux_630; // op=pyc.mux +wire [15:0] pyc_mux_636; // op=pyc.mux +wire [15:0] pyc_mux_637; // op=pyc.mux +wire pyc_reg_34; // op=pyc.reg +wire pyc_reg_36; // op=pyc.reg +wire pyc_reg_38; // op=pyc.reg +wire pyc_reg_398; // op=pyc.reg +wire pyc_reg_40; // op=pyc.reg +wire pyc_reg_400; // op=pyc.reg +wire pyc_reg_402; // op=pyc.reg +wire pyc_reg_404; // op=pyc.reg +wire pyc_reg_406; // op=pyc.reg +wire [1:0] pyc_reg_407; // op=pyc.reg +wire [1:0] pyc_reg_409; // op=pyc.reg +wire [1:0] pyc_reg_411; // op=pyc.reg +wire [31:0] pyc_reg_413; // op=pyc.reg +wire [31:0] pyc_reg_414; // op=pyc.reg +wire [31:0] pyc_reg_415; // op=pyc.reg +wire [31:0] pyc_reg_416; // op=pyc.reg +wire [31:0] pyc_reg_417; // op=pyc.reg +wire [31:0] pyc_reg_418; // op=pyc.reg +wire [31:0] pyc_reg_419; // op=pyc.reg +wire pyc_reg_42; // op=pyc.reg +wire [31:0] pyc_reg_420; // op=pyc.reg +wire [31:0] pyc_reg_421; // op=pyc.reg +wire [31:0] pyc_reg_422; // op=pyc.reg +wire [31:0] pyc_reg_423; // op=pyc.reg +wire [31:0] pyc_reg_424; // op=pyc.reg +wire [31:0] pyc_reg_425; // op=pyc.reg +wire [31:0] pyc_reg_426; // op=pyc.reg +wire [31:0] pyc_reg_427; // op=pyc.reg +wire [31:0] pyc_reg_428; // op=pyc.reg +wire [31:0] pyc_reg_429; // op=pyc.reg +wire [31:0] pyc_reg_430; // op=pyc.reg +wire [31:0] pyc_reg_431; // op=pyc.reg +wire [31:0] pyc_reg_432; // op=pyc.reg +wire [31:0] pyc_reg_433; // op=pyc.reg +wire [31:0] pyc_reg_434; // op=pyc.reg +wire [31:0] pyc_reg_435; // op=pyc.reg +wire [31:0] pyc_reg_436; // op=pyc.reg +wire [31:0] pyc_reg_437; // op=pyc.reg +wire [31:0] pyc_reg_438; // op=pyc.reg +wire [31:0] pyc_reg_439; // op=pyc.reg +wire [79:0] pyc_reg_44; // op=pyc.reg +wire [31:0] pyc_reg_440; // op=pyc.reg +wire [31:0] pyc_reg_441; // op=pyc.reg +wire [31:0] pyc_reg_442; // op=pyc.reg +wire [31:0] pyc_reg_443; // op=pyc.reg +wire [31:0] pyc_reg_444; // op=pyc.reg +wire [31:0] pyc_reg_445; // op=pyc.reg +wire [31:0] pyc_reg_446; // op=pyc.reg +wire [31:0] pyc_reg_447; // op=pyc.reg +wire [31:0] pyc_reg_448; // op=pyc.reg +wire [31:0] pyc_reg_449; // op=pyc.reg +wire [79:0] pyc_reg_45; // op=pyc.reg +wire [31:0] pyc_reg_450; // op=pyc.reg +wire [31:0] pyc_reg_451; // op=pyc.reg +wire [31:0] pyc_reg_452; // op=pyc.reg +wire [31:0] pyc_reg_453; // op=pyc.reg +wire [31:0] pyc_reg_454; // op=pyc.reg +wire [31:0] pyc_reg_455; // op=pyc.reg +wire [31:0] pyc_reg_456; // op=pyc.reg +wire [31:0] pyc_reg_457; // op=pyc.reg +wire [31:0] pyc_reg_458; // op=pyc.reg +wire [31:0] pyc_reg_459; // op=pyc.reg +wire [79:0] pyc_reg_46; // op=pyc.reg +wire [31:0] pyc_reg_460; // op=pyc.reg +wire [31:0] pyc_reg_461; // op=pyc.reg +wire [31:0] pyc_reg_462; // op=pyc.reg +wire [31:0] pyc_reg_463; // op=pyc.reg +wire [31:0] pyc_reg_464; // op=pyc.reg +wire [31:0] pyc_reg_465; // op=pyc.reg +wire [31:0] pyc_reg_466; // op=pyc.reg +wire [31:0] pyc_reg_467; // op=pyc.reg +wire [31:0] pyc_reg_468; // op=pyc.reg +wire [31:0] pyc_reg_469; // op=pyc.reg +wire [1:0] pyc_reg_47; // op=pyc.reg +wire [31:0] pyc_reg_470; // op=pyc.reg +wire [31:0] pyc_reg_471; // op=pyc.reg +wire [31:0] pyc_reg_472; // op=pyc.reg +wire [31:0] pyc_reg_473; // op=pyc.reg +wire [31:0] pyc_reg_474; // op=pyc.reg +wire [31:0] pyc_reg_475; // op=pyc.reg +wire [31:0] pyc_reg_476; // op=pyc.reg +wire [31:0] pyc_reg_477; // op=pyc.reg +wire [31:0] pyc_reg_478; // op=pyc.reg +wire [31:0] pyc_reg_479; // op=pyc.reg +wire [31:0] pyc_reg_480; // op=pyc.reg +wire [31:0] pyc_reg_481; // op=pyc.reg +wire [31:0] pyc_reg_482; // op=pyc.reg +wire [31:0] pyc_reg_483; // op=pyc.reg +wire [31:0] pyc_reg_484; // op=pyc.reg +wire [1:0] pyc_reg_49; // op=pyc.reg +wire [1:0] pyc_reg_51; // op=pyc.reg +wire pyc_reg_557; // op=pyc.reg +wire [2:0] pyc_reg_564; // op=pyc.reg +wire [1:0] pyc_reg_571; // op=pyc.reg +wire [1:0] pyc_reg_572; // op=pyc.reg +wire [1:0] pyc_reg_573; // op=pyc.reg +wire [31:0] pyc_reg_574; // op=pyc.reg +wire [31:0] pyc_reg_575; // op=pyc.reg +wire [31:0] pyc_reg_576; // op=pyc.reg +wire [31:0] pyc_reg_577; // op=pyc.reg +wire [31:0] pyc_reg_578; // op=pyc.reg +wire [31:0] pyc_reg_579; // op=pyc.reg +wire [31:0] pyc_reg_580; // op=pyc.reg +wire [31:0] pyc_reg_581; // op=pyc.reg +wire [31:0] pyc_reg_582; // op=pyc.reg +wire [15:0] pyc_reg_635; // op=pyc.reg +wire pyc_reg_640; // op=pyc.reg +wire [18:0] pyc_reg_641; // op=pyc.reg +wire [15:0] pyc_reg_642; // op=pyc.reg +wire [31:0] pyc_sext_108; // op=pyc.sext +wire [31:0] pyc_sext_114; // op=pyc.sext +wire [31:0] pyc_sext_117; // op=pyc.sext +wire [31:0] pyc_sext_120; // op=pyc.sext +wire [31:0] pyc_sext_121; // op=pyc.sext +wire [31:0] pyc_sext_122; // op=pyc.sext +wire [31:0] pyc_sext_133; // op=pyc.sext +wire [31:0] pyc_sext_139; // op=pyc.sext +wire [31:0] pyc_sext_142; // op=pyc.sext +wire [31:0] pyc_sext_145; // op=pyc.sext +wire [31:0] pyc_sext_146; // op=pyc.sext +wire [31:0] pyc_sext_147; // op=pyc.sext +wire [31:0] pyc_sext_158; // op=pyc.sext +wire [31:0] pyc_sext_160; // op=pyc.sext +wire [31:0] pyc_sext_163; // op=pyc.sext +wire [31:0] pyc_sext_166; // op=pyc.sext +wire [31:0] pyc_sext_167; // op=pyc.sext +wire [31:0] pyc_sext_168; // op=pyc.sext +wire [31:0] pyc_sext_179; // op=pyc.sext +wire [31:0] pyc_sext_181; // op=pyc.sext +wire [31:0] pyc_sext_184; // op=pyc.sext +wire [31:0] pyc_sext_187; // op=pyc.sext +wire [31:0] pyc_sext_188; // op=pyc.sext +wire [31:0] pyc_sext_189; // op=pyc.sext +wire [31:0] pyc_sext_200; // op=pyc.sext +wire [31:0] pyc_sext_202; // op=pyc.sext +wire [31:0] pyc_sext_205; // op=pyc.sext +wire [31:0] pyc_sext_208; // op=pyc.sext +wire [31:0] pyc_sext_209; // op=pyc.sext +wire [31:0] pyc_sext_210; // op=pyc.sext +wire [31:0] pyc_sext_221; // op=pyc.sext +wire [31:0] pyc_sext_225; // op=pyc.sext +wire [31:0] pyc_sext_228; // op=pyc.sext +wire [31:0] pyc_sext_229; // op=pyc.sext +wire [31:0] pyc_sext_230; // op=pyc.sext +wire [31:0] pyc_sext_231; // op=pyc.sext +wire [31:0] pyc_sext_237; // op=pyc.sext +wire [31:0] pyc_sext_238; // op=pyc.sext +wire [31:0] pyc_sext_240; // op=pyc.sext +wire [31:0] pyc_sext_243; // op=pyc.sext +wire [31:0] pyc_sext_244; // op=pyc.sext +wire [31:0] pyc_sext_246; // op=pyc.sext +wire [31:0] pyc_sext_249; // op=pyc.sext +wire [31:0] pyc_sext_250; // op=pyc.sext +wire [31:0] pyc_sext_252; // op=pyc.sext +wire [31:0] pyc_sext_255; // op=pyc.sext +wire [31:0] pyc_sext_256; // op=pyc.sext +wire [31:0] pyc_sext_258; // op=pyc.sext +wire [31:0] pyc_sext_261; // op=pyc.sext +wire [31:0] pyc_sext_262; // op=pyc.sext +wire [31:0] pyc_sext_264; // op=pyc.sext +wire [31:0] pyc_sext_267; // op=pyc.sext +wire [31:0] pyc_sext_268; // op=pyc.sext +wire [31:0] pyc_sext_270; // op=pyc.sext +wire [31:0] pyc_sext_273; // op=pyc.sext +wire [31:0] pyc_sext_274; // op=pyc.sext +wire [31:0] pyc_sext_276; // op=pyc.sext +wire [31:0] pyc_sext_279; // op=pyc.sext +wire [31:0] pyc_sext_280; // op=pyc.sext +wire [31:0] pyc_sext_282; // op=pyc.sext +wire [31:0] pyc_sext_285; // op=pyc.sext +wire [31:0] pyc_sext_287; // op=pyc.sext +wire [31:0] pyc_sext_290; // op=pyc.sext +wire [31:0] pyc_sext_292; // op=pyc.sext +wire [31:0] pyc_sext_295; // op=pyc.sext +wire [31:0] pyc_sext_297; // op=pyc.sext +wire [31:0] pyc_sext_300; // op=pyc.sext +wire [31:0] pyc_sext_302; // op=pyc.sext +wire [31:0] pyc_sext_305; // op=pyc.sext +wire [31:0] pyc_sext_307; // op=pyc.sext +wire [31:0] pyc_sext_310; // op=pyc.sext +wire [31:0] pyc_sext_312; // op=pyc.sext +wire [31:0] pyc_sext_315; // op=pyc.sext +wire [31:0] pyc_sext_317; // op=pyc.sext +wire [31:0] pyc_sext_320; // op=pyc.sext +wire [31:0] pyc_sext_322; // op=pyc.sext +wire [31:0] pyc_sext_58; // op=pyc.sext +wire [31:0] pyc_sext_64; // op=pyc.sext +wire [31:0] pyc_sext_67; // op=pyc.sext +wire [31:0] pyc_sext_70; // op=pyc.sext +wire [31:0] pyc_sext_71; // op=pyc.sext +wire [31:0] pyc_sext_72; // op=pyc.sext +wire [31:0] pyc_sext_83; // op=pyc.sext +wire [31:0] pyc_sext_89; // op=pyc.sext +wire [31:0] pyc_sext_92; // op=pyc.sext +wire [31:0] pyc_sext_95; // op=pyc.sext +wire [31:0] pyc_sext_96; // op=pyc.sext +wire [31:0] pyc_sext_97; // op=pyc.sext +wire [1:0] pyc_zext_584; // op=pyc.zext +wire [1:0] pyc_zext_586; // op=pyc.zext +wire [1:0] pyc_zext_589; // op=pyc.zext +wire [1:0] pyc_zext_591; // op=pyc.zext +wire [1:0] pyc_zext_607; // op=pyc.zext +wire [1:0] pyc_zext_610; // op=pyc.zext + +// --- Combinational (netlist) +assign pe_int_out0 = pyc_reg_641; +assign pe_int_out1 = pyc_reg_642; +assign pe_int_out_vld = pyc_reg_640; +assign pe_int_s0_a = pyc_reg_44; +assign pe_int_s0_b = pyc_reg_45; +assign pe_int_s0_b1 = pyc_reg_46; +assign pe_int_s1_p2a_0 = pyc_reg_413; +assign pe_int_s1_p2a_1 = pyc_reg_414; +assign pe_int_s1_p2a_2 = pyc_reg_415; +assign pe_int_s1_p2a_3 = pyc_reg_416; +assign pe_int_s1_p2a_4 = pyc_reg_417; +assign pe_int_s1_p2a_5 = pyc_reg_418; +assign pe_int_s1_p2a_6 = pyc_reg_419; +assign pe_int_s1_p2a_7 = pyc_reg_420; +assign pe_int_s1_p2b0_0 = pyc_reg_421; +assign pe_int_s1_p2b0_1 = pyc_reg_422; +assign pe_int_s1_p2b0_2 = pyc_reg_423; +assign pe_int_s1_p2b0_3 = pyc_reg_424; +assign pe_int_s1_p2b0_4 = pyc_reg_425; +assign pe_int_s1_p2b0_5 = pyc_reg_426; +assign pe_int_s1_p2b0_6 = pyc_reg_427; +assign pe_int_s1_p2b0_7 = pyc_reg_428; +assign pe_int_s1_p2b1_0 = pyc_reg_429; +assign pe_int_s1_p2b1_1 = pyc_reg_430; +assign pe_int_s1_p2b1_2 = pyc_reg_431; +assign pe_int_s1_p2b1_3 = pyc_reg_432; +assign pe_int_s1_p2b1_4 = pyc_reg_433; +assign pe_int_s1_p2b1_5 = pyc_reg_434; +assign pe_int_s1_p2b1_6 = pyc_reg_435; +assign pe_int_s1_p2b1_7 = pyc_reg_436; +assign pe_int_s1_p2c0_0 = pyc_reg_453; +assign pe_int_s1_p2c0_1 = pyc_reg_454; +assign pe_int_s1_p2c0_10 = pyc_reg_463; +assign pe_int_s1_p2c0_11 = pyc_reg_464; +assign pe_int_s1_p2c0_12 = pyc_reg_465; +assign pe_int_s1_p2c0_13 = pyc_reg_466; +assign pe_int_s1_p2c0_14 = pyc_reg_467; +assign pe_int_s1_p2c0_15 = pyc_reg_468; +assign pe_int_s1_p2c0_2 = pyc_reg_455; +assign pe_int_s1_p2c0_3 = pyc_reg_456; +assign pe_int_s1_p2c0_4 = pyc_reg_457; +assign pe_int_s1_p2c0_5 = pyc_reg_458; +assign pe_int_s1_p2c0_6 = pyc_reg_459; +assign pe_int_s1_p2c0_7 = pyc_reg_460; +assign pe_int_s1_p2c0_8 = pyc_reg_461; +assign pe_int_s1_p2c0_9 = pyc_reg_462; +assign pe_int_s1_p2c1_0 = pyc_reg_469; +assign pe_int_s1_p2c1_1 = pyc_reg_470; +assign pe_int_s1_p2c1_10 = pyc_reg_479; +assign pe_int_s1_p2c1_11 = pyc_reg_480; +assign pe_int_s1_p2c1_12 = pyc_reg_481; +assign pe_int_s1_p2c1_13 = pyc_reg_482; +assign pe_int_s1_p2c1_14 = pyc_reg_483; +assign pe_int_s1_p2c1_2 = pyc_reg_471; +assign pe_int_s1_p2c1_3 = pyc_reg_472; +assign pe_int_s1_p2c1_4 = pyc_reg_473; +assign pe_int_s1_p2c1_5 = pyc_reg_474; +assign pe_int_s1_p2c1_6 = pyc_reg_475; +assign pe_int_s1_p2c1_7 = pyc_reg_476; +assign pe_int_s1_p2c1_8 = pyc_reg_477; +assign pe_int_s1_p2c1_9 = pyc_reg_478; +assign pe_int_s1_p2d0_0 = pyc_reg_437; +assign pe_int_s1_p2d0_1 = pyc_reg_438; +assign pe_int_s1_p2d0_2 = pyc_reg_439; +assign pe_int_s1_p2d0_3 = pyc_reg_440; +assign pe_int_s1_p2d0_4 = pyc_reg_441; +assign pe_int_s1_p2d0_5 = pyc_reg_442; +assign pe_int_s1_p2d0_6 = pyc_reg_443; +assign pe_int_s1_p2d0_7 = pyc_reg_444; +assign pe_int_s1_p2d1_0 = pyc_reg_445; +assign pe_int_s1_p2d1_1 = pyc_reg_446; +assign pe_int_s1_p2d1_2 = pyc_reg_447; +assign pe_int_s1_p2d1_3 = pyc_reg_448; +assign pe_int_s1_p2d1_4 = pyc_reg_449; +assign pe_int_s1_p2d1_5 = pyc_reg_450; +assign pe_int_s1_p2d1_6 = pyc_reg_451; +assign pe_int_s1_p2d1_7 = pyc_reg_452; +assign pe_int_s2_e1_a = pyc_reg_571; +assign pe_int_s2_e1_b0 = pyc_reg_572; +assign pe_int_s2_e1_b1 = pyc_reg_573; +assign pe_int_s2_s2a = pyc_reg_574; +assign pe_int_s2_s2b0 = pyc_reg_575; +assign pe_int_s2_s2b1 = pyc_reg_576; +assign pe_int_s2_s2c0_hi = pyc_reg_580; +assign pe_int_s2_s2c0_lo = pyc_reg_579; +assign pe_int_s2_s2c1_lo = pyc_reg_581; +assign pe_int_s2_s2d0 = pyc_reg_577; +assign pe_int_s2_s2d1 = pyc_reg_578; +assign pyc_constant_1 = 19'd0; +assign pyc_constant_2 = 16'd0; +assign pyc_constant_3 = 2'd1; +assign pyc_constant_4 = 32'd0; +assign pyc_constant_5 = 2'd0; +assign pyc_constant_6 = 80'd0; +assign pyc_constant_7 = 2'd3; +assign pyc_constant_8 = 2'd2; +assign pyc_constant_9 = 1'd1; +assign pyc_constant_10 = 1'd0; +assign pe_int_s0_e1_b1__next = e1_b1; +assign pe_int_s0_e1_b0__next = e1_b0; +assign pe_int_s0_e1_a__next = e1_a; +assign pe_int_s0_b1__next = b1; +assign pe_int_s0_b__next = b; +assign pe_int_s0_a__next = a; +assign pe_int_s0_vld__next = vld; +assign pyc_eq_11 = (mode == pyc_constant_5); +assign pe_int_s0_is_2a__next = pyc_eq_11; +assign pyc_eq_12 = (mode == pyc_constant_3); +assign pe_int_s0_is_2b__next = pyc_eq_12; +assign pyc_eq_13 = (mode == pyc_constant_8); +assign pe_int_s0_is_2c__next = pyc_eq_13; +assign pyc_eq_14 = (mode == pyc_constant_7); +assign pe_int_s0_is_2d__next = pyc_eq_14; +assign pyc_comb_15 = pyc_constant_1; +assign pyc_comb_16 = pyc_constant_2; +assign pyc_comb_17 = pyc_constant_3; +assign pyc_comb_18 = pyc_constant_4; +assign pyc_comb_19 = pyc_constant_5; +assign pyc_comb_20 = pyc_constant_6; +assign pyc_comb_21 = pyc_constant_9; +assign pyc_comb_22 = pyc_constant_10; +assign pyc_comb_23 = pe_int_s0_e1_b1__next; +assign pyc_comb_24 = pe_int_s0_e1_b0__next; +assign pyc_comb_25 = pe_int_s0_e1_a__next; +assign pyc_comb_26 = pe_int_s0_b1__next; +assign pyc_comb_27 = pe_int_s0_b__next; +assign pyc_comb_28 = pe_int_s0_a__next; +assign pyc_comb_29 = pe_int_s0_vld__next; +assign pyc_comb_30 = pe_int_s0_is_2a__next; +assign pyc_comb_31 = pe_int_s0_is_2b__next; +assign pyc_comb_32 = pe_int_s0_is_2c__next; +assign pyc_comb_33 = pe_int_s0_is_2d__next; +assign pe_int_s0_e1_b1 = pyc_reg_51; +assign pe_int_s1_e1_b1__next = pe_int_s0_e1_b1; +assign pyc_extract_52 = pe_int_s0_b[39:0]; +assign pyc_extract_53 = pe_int_s0_a[4:0]; +assign pyc_extract_54 = pe_int_s0_a[9:5]; +assign pyc_extract_55 = pyc_extract_53[4:1]; +assign pyc_extract_56 = pyc_extract_54[4:1]; +assign pyc_concat_57 = {pyc_extract_56, pyc_extract_55}; +assign pyc_sext_58 = {{24{pyc_concat_57[7]}}, pyc_concat_57}; +assign pyc_extract_59 = pe_int_s0_b[4:0]; +assign pyc_extract_60 = pe_int_s0_b[9:5]; +assign pyc_extract_61 = pyc_extract_59[4:1]; +assign pyc_extract_62 = pyc_extract_60[4:1]; +assign pyc_concat_63 = {pyc_extract_62, pyc_extract_61}; +assign pyc_sext_64 = {{24{pyc_concat_63[7]}}, pyc_concat_63}; +assign pyc_extract_65 = pyc_extract_52[4:0]; +assign pyc_extract_66 = pyc_extract_65[4:1]; +assign pyc_sext_67 = {{28{pyc_extract_66[3]}}, pyc_extract_66}; +assign pyc_extract_68 = pe_int_s0_b[44:40]; +assign pyc_extract_69 = pyc_extract_68[4:1]; +assign pyc_sext_70 = {{28{pyc_extract_69[3]}}, pyc_extract_69}; +assign pyc_sext_71 = {{27{pyc_extract_65[4]}}, pyc_extract_65}; +assign pyc_sext_72 = {{27{pyc_extract_68[4]}}, pyc_extract_68}; +assign pyc_mul_73 = (pyc_sext_58 * pyc_sext_64); +assign pe_int_s1_p2a_0__next = pyc_mul_73; +assign pyc_mul_74 = (pyc_sext_58 * pyc_sext_67); +assign pe_int_s1_p2b0_0__next = pyc_mul_74; +assign pyc_mul_75 = (pyc_sext_58 * pyc_sext_70); +assign pe_int_s1_p2b1_0__next = pyc_mul_75; +assign pyc_mul_76 = (pyc_sext_58 * pyc_sext_71); +assign pe_int_s1_p2d0_0__next = pyc_mul_76; +assign pyc_mul_77 = (pyc_sext_58 * pyc_sext_72); +assign pe_int_s1_p2d1_0__next = pyc_mul_77; +assign pyc_extract_78 = pe_int_s0_a[14:10]; +assign pyc_extract_79 = pe_int_s0_a[19:15]; +assign pyc_extract_80 = pyc_extract_78[4:1]; +assign pyc_extract_81 = pyc_extract_79[4:1]; +assign pyc_concat_82 = {pyc_extract_81, pyc_extract_80}; +assign pyc_sext_83 = {{24{pyc_concat_82[7]}}, pyc_concat_82}; +assign pyc_extract_84 = pe_int_s0_b[14:10]; +assign pyc_extract_85 = pe_int_s0_b[19:15]; +assign pyc_extract_86 = pyc_extract_84[4:1]; +assign pyc_extract_87 = pyc_extract_85[4:1]; +assign pyc_concat_88 = {pyc_extract_87, pyc_extract_86}; +assign pyc_sext_89 = {{24{pyc_concat_88[7]}}, pyc_concat_88}; +assign pyc_extract_90 = pyc_extract_52[9:5]; +assign pyc_extract_91 = pyc_extract_90[4:1]; +assign pyc_sext_92 = {{28{pyc_extract_91[3]}}, pyc_extract_91}; +assign pyc_extract_93 = pe_int_s0_b[49:45]; +assign pyc_extract_94 = pyc_extract_93[4:1]; +assign pyc_sext_95 = {{28{pyc_extract_94[3]}}, pyc_extract_94}; +assign pyc_sext_96 = {{27{pyc_extract_90[4]}}, pyc_extract_90}; +assign pyc_sext_97 = {{27{pyc_extract_93[4]}}, pyc_extract_93}; +assign pyc_mul_98 = (pyc_sext_83 * pyc_sext_89); +assign pe_int_s1_p2a_1__next = pyc_mul_98; +assign pyc_mul_99 = (pyc_sext_83 * pyc_sext_92); +assign pe_int_s1_p2b0_1__next = pyc_mul_99; +assign pyc_mul_100 = (pyc_sext_83 * pyc_sext_95); +assign pe_int_s1_p2b1_1__next = pyc_mul_100; +assign pyc_mul_101 = (pyc_sext_83 * pyc_sext_96); +assign pe_int_s1_p2d0_1__next = pyc_mul_101; +assign pyc_mul_102 = (pyc_sext_83 * pyc_sext_97); +assign pe_int_s1_p2d1_1__next = pyc_mul_102; +assign pyc_extract_103 = pe_int_s0_a[24:20]; +assign pyc_extract_104 = pe_int_s0_a[29:25]; +assign pyc_extract_105 = pyc_extract_103[4:1]; +assign pyc_extract_106 = pyc_extract_104[4:1]; +assign pyc_concat_107 = {pyc_extract_106, pyc_extract_105}; +assign pyc_sext_108 = {{24{pyc_concat_107[7]}}, pyc_concat_107}; +assign pyc_extract_109 = pe_int_s0_b[24:20]; +assign pyc_extract_110 = pe_int_s0_b[29:25]; +assign pyc_extract_111 = pyc_extract_109[4:1]; +assign pyc_extract_112 = pyc_extract_110[4:1]; +assign pyc_concat_113 = {pyc_extract_112, pyc_extract_111}; +assign pyc_sext_114 = {{24{pyc_concat_113[7]}}, pyc_concat_113}; +assign pyc_extract_115 = pyc_extract_52[14:10]; +assign pyc_extract_116 = pyc_extract_115[4:1]; +assign pyc_sext_117 = {{28{pyc_extract_116[3]}}, pyc_extract_116}; +assign pyc_extract_118 = pe_int_s0_b[54:50]; +assign pyc_extract_119 = pyc_extract_118[4:1]; +assign pyc_sext_120 = {{28{pyc_extract_119[3]}}, pyc_extract_119}; +assign pyc_sext_121 = {{27{pyc_extract_115[4]}}, pyc_extract_115}; +assign pyc_sext_122 = {{27{pyc_extract_118[4]}}, pyc_extract_118}; +assign pyc_mul_123 = (pyc_sext_108 * pyc_sext_114); +assign pe_int_s1_p2a_2__next = pyc_mul_123; +assign pyc_mul_124 = (pyc_sext_108 * pyc_sext_117); +assign pe_int_s1_p2b0_2__next = pyc_mul_124; +assign pyc_mul_125 = (pyc_sext_108 * pyc_sext_120); +assign pe_int_s1_p2b1_2__next = pyc_mul_125; +assign pyc_mul_126 = (pyc_sext_108 * pyc_sext_121); +assign pe_int_s1_p2d0_2__next = pyc_mul_126; +assign pyc_mul_127 = (pyc_sext_108 * pyc_sext_122); +assign pe_int_s1_p2d1_2__next = pyc_mul_127; +assign pyc_extract_128 = pe_int_s0_a[34:30]; +assign pyc_extract_129 = pe_int_s0_a[39:35]; +assign pyc_extract_130 = pyc_extract_128[4:1]; +assign pyc_extract_131 = pyc_extract_129[4:1]; +assign pyc_concat_132 = {pyc_extract_131, pyc_extract_130}; +assign pyc_sext_133 = {{24{pyc_concat_132[7]}}, pyc_concat_132}; +assign pyc_extract_134 = pe_int_s0_b[34:30]; +assign pyc_extract_135 = pe_int_s0_b[39:35]; +assign pyc_extract_136 = pyc_extract_134[4:1]; +assign pyc_extract_137 = pyc_extract_135[4:1]; +assign pyc_concat_138 = {pyc_extract_137, pyc_extract_136}; +assign pyc_sext_139 = {{24{pyc_concat_138[7]}}, pyc_concat_138}; +assign pyc_extract_140 = pyc_extract_52[19:15]; +assign pyc_extract_141 = pyc_extract_140[4:1]; +assign pyc_sext_142 = {{28{pyc_extract_141[3]}}, pyc_extract_141}; +assign pyc_extract_143 = pe_int_s0_b[59:55]; +assign pyc_extract_144 = pyc_extract_143[4:1]; +assign pyc_sext_145 = {{28{pyc_extract_144[3]}}, pyc_extract_144}; +assign pyc_sext_146 = {{27{pyc_extract_140[4]}}, pyc_extract_140}; +assign pyc_sext_147 = {{27{pyc_extract_143[4]}}, pyc_extract_143}; +assign pyc_mul_148 = (pyc_sext_133 * pyc_sext_139); +assign pe_int_s1_p2a_3__next = pyc_mul_148; +assign pyc_mul_149 = (pyc_sext_133 * pyc_sext_142); +assign pe_int_s1_p2b0_3__next = pyc_mul_149; +assign pyc_mul_150 = (pyc_sext_133 * pyc_sext_145); +assign pe_int_s1_p2b1_3__next = pyc_mul_150; +assign pyc_mul_151 = (pyc_sext_133 * pyc_sext_146); +assign pe_int_s1_p2d0_3__next = pyc_mul_151; +assign pyc_mul_152 = (pyc_sext_133 * pyc_sext_147); +assign pe_int_s1_p2d1_3__next = pyc_mul_152; +assign pyc_extract_153 = pe_int_s0_a[44:40]; +assign pyc_extract_154 = pe_int_s0_a[49:45]; +assign pyc_extract_155 = pyc_extract_153[4:1]; +assign pyc_extract_156 = pyc_extract_154[4:1]; +assign pyc_concat_157 = {pyc_extract_156, pyc_extract_155}; +assign pyc_sext_158 = {{24{pyc_concat_157[7]}}, pyc_concat_157}; +assign pyc_concat_159 = {pyc_extract_94, pyc_extract_69}; +assign pyc_sext_160 = {{24{pyc_concat_159[7]}}, pyc_concat_159}; +assign pyc_extract_161 = pyc_extract_52[24:20]; +assign pyc_extract_162 = pyc_extract_161[4:1]; +assign pyc_sext_163 = {{28{pyc_extract_162[3]}}, pyc_extract_162}; +assign pyc_extract_164 = pe_int_s0_b[64:60]; +assign pyc_extract_165 = pyc_extract_164[4:1]; +assign pyc_sext_166 = {{28{pyc_extract_165[3]}}, pyc_extract_165}; +assign pyc_sext_167 = {{27{pyc_extract_161[4]}}, pyc_extract_161}; +assign pyc_sext_168 = {{27{pyc_extract_164[4]}}, pyc_extract_164}; +assign pyc_mul_169 = (pyc_sext_158 * pyc_sext_160); +assign pe_int_s1_p2a_4__next = pyc_mul_169; +assign pyc_mul_170 = (pyc_sext_158 * pyc_sext_163); +assign pe_int_s1_p2b0_4__next = pyc_mul_170; +assign pyc_mul_171 = (pyc_sext_158 * pyc_sext_166); +assign pe_int_s1_p2b1_4__next = pyc_mul_171; +assign pyc_mul_172 = (pyc_sext_158 * pyc_sext_167); +assign pe_int_s1_p2d0_4__next = pyc_mul_172; +assign pyc_mul_173 = (pyc_sext_158 * pyc_sext_168); +assign pe_int_s1_p2d1_4__next = pyc_mul_173; +assign pyc_extract_174 = pe_int_s0_a[54:50]; +assign pyc_extract_175 = pe_int_s0_a[59:55]; +assign pyc_extract_176 = pyc_extract_174[4:1]; +assign pyc_extract_177 = pyc_extract_175[4:1]; +assign pyc_concat_178 = {pyc_extract_177, pyc_extract_176}; +assign pyc_sext_179 = {{24{pyc_concat_178[7]}}, pyc_concat_178}; +assign pyc_concat_180 = {pyc_extract_144, pyc_extract_119}; +assign pyc_sext_181 = {{24{pyc_concat_180[7]}}, pyc_concat_180}; +assign pyc_extract_182 = pyc_extract_52[29:25]; +assign pyc_extract_183 = pyc_extract_182[4:1]; +assign pyc_sext_184 = {{28{pyc_extract_183[3]}}, pyc_extract_183}; +assign pyc_extract_185 = pe_int_s0_b[69:65]; +assign pyc_extract_186 = pyc_extract_185[4:1]; +assign pyc_sext_187 = {{28{pyc_extract_186[3]}}, pyc_extract_186}; +assign pyc_sext_188 = {{27{pyc_extract_182[4]}}, pyc_extract_182}; +assign pyc_sext_189 = {{27{pyc_extract_185[4]}}, pyc_extract_185}; +assign pyc_mul_190 = (pyc_sext_179 * pyc_sext_181); +assign pe_int_s1_p2a_5__next = pyc_mul_190; +assign pyc_mul_191 = (pyc_sext_179 * pyc_sext_184); +assign pe_int_s1_p2b0_5__next = pyc_mul_191; +assign pyc_mul_192 = (pyc_sext_179 * pyc_sext_187); +assign pe_int_s1_p2b1_5__next = pyc_mul_192; +assign pyc_mul_193 = (pyc_sext_179 * pyc_sext_188); +assign pe_int_s1_p2d0_5__next = pyc_mul_193; +assign pyc_mul_194 = (pyc_sext_179 * pyc_sext_189); +assign pe_int_s1_p2d1_5__next = pyc_mul_194; +assign pyc_extract_195 = pe_int_s0_a[64:60]; +assign pyc_extract_196 = pe_int_s0_a[69:65]; +assign pyc_extract_197 = pyc_extract_195[4:1]; +assign pyc_extract_198 = pyc_extract_196[4:1]; +assign pyc_concat_199 = {pyc_extract_198, pyc_extract_197}; +assign pyc_sext_200 = {{24{pyc_concat_199[7]}}, pyc_concat_199}; +assign pyc_concat_201 = {pyc_extract_186, pyc_extract_165}; +assign pyc_sext_202 = {{24{pyc_concat_201[7]}}, pyc_concat_201}; +assign pyc_extract_203 = pyc_extract_52[34:30]; +assign pyc_extract_204 = pyc_extract_203[4:1]; +assign pyc_sext_205 = {{28{pyc_extract_204[3]}}, pyc_extract_204}; +assign pyc_extract_206 = pe_int_s0_b[74:70]; +assign pyc_extract_207 = pyc_extract_206[4:1]; +assign pyc_sext_208 = {{28{pyc_extract_207[3]}}, pyc_extract_207}; +assign pyc_sext_209 = {{27{pyc_extract_203[4]}}, pyc_extract_203}; +assign pyc_sext_210 = {{27{pyc_extract_206[4]}}, pyc_extract_206}; +assign pyc_mul_211 = (pyc_sext_200 * pyc_sext_202); +assign pe_int_s1_p2a_6__next = pyc_mul_211; +assign pyc_mul_212 = (pyc_sext_200 * pyc_sext_205); +assign pe_int_s1_p2b0_6__next = pyc_mul_212; +assign pyc_mul_213 = (pyc_sext_200 * pyc_sext_208); +assign pe_int_s1_p2b1_6__next = pyc_mul_213; +assign pyc_mul_214 = (pyc_sext_200 * pyc_sext_209); +assign pe_int_s1_p2d0_6__next = pyc_mul_214; +assign pyc_mul_215 = (pyc_sext_200 * pyc_sext_210); +assign pe_int_s1_p2d1_6__next = pyc_mul_215; +assign pyc_extract_216 = pe_int_s0_a[74:70]; +assign pyc_extract_217 = pe_int_s0_a[79:75]; +assign pyc_extract_218 = pyc_extract_216[4:1]; +assign pyc_extract_219 = pyc_extract_217[4:1]; +assign pyc_concat_220 = {pyc_extract_219, pyc_extract_218}; +assign pyc_sext_221 = {{24{pyc_concat_220[7]}}, pyc_concat_220}; +assign pyc_extract_222 = pe_int_s0_b[79:75]; +assign pyc_extract_223 = pyc_extract_222[4:1]; +assign pyc_concat_224 = {pyc_extract_223, pyc_extract_207}; +assign pyc_sext_225 = {{24{pyc_concat_224[7]}}, pyc_concat_224}; +assign pyc_extract_226 = pyc_extract_52[39:35]; +assign pyc_extract_227 = pyc_extract_226[4:1]; +assign pyc_sext_228 = {{28{pyc_extract_227[3]}}, pyc_extract_227}; +assign pyc_sext_229 = {{28{pyc_extract_223[3]}}, pyc_extract_223}; +assign pyc_sext_230 = {{27{pyc_extract_226[4]}}, pyc_extract_226}; +assign pyc_sext_231 = {{27{pyc_extract_222[4]}}, pyc_extract_222}; +assign pyc_mul_232 = (pyc_sext_221 * pyc_sext_225); +assign pe_int_s1_p2a_7__next = pyc_mul_232; +assign pyc_mul_233 = (pyc_sext_221 * pyc_sext_228); +assign pe_int_s1_p2b0_7__next = pyc_mul_233; +assign pyc_mul_234 = (pyc_sext_221 * pyc_sext_229); +assign pe_int_s1_p2b1_7__next = pyc_mul_234; +assign pyc_mul_235 = (pyc_sext_221 * pyc_sext_230); +assign pe_int_s1_p2d0_7__next = pyc_mul_235; +assign pyc_mul_236 = (pyc_sext_221 * pyc_sext_231); +assign pe_int_s1_p2d1_7__next = pyc_mul_236; +assign pyc_sext_237 = {{27{pyc_extract_53[4]}}, pyc_extract_53}; +assign pyc_sext_238 = {{27{pyc_extract_59[4]}}, pyc_extract_59}; +assign pyc_extract_239 = pe_int_s0_b1[4:0]; +assign pyc_sext_240 = {{27{pyc_extract_239[4]}}, pyc_extract_239}; +assign pyc_mul_241 = (pyc_sext_237 * pyc_sext_238); +assign pe_int_s1_p2c0_0__next = pyc_mul_241; +assign pyc_mul_242 = (pyc_sext_237 * pyc_sext_240); +assign pe_int_s1_p2c1_0__next = pyc_mul_242; +assign pyc_sext_243 = {{27{pyc_extract_54[4]}}, pyc_extract_54}; +assign pyc_sext_244 = {{27{pyc_extract_60[4]}}, pyc_extract_60}; +assign pyc_extract_245 = pe_int_s0_b1[9:5]; +assign pyc_sext_246 = {{27{pyc_extract_245[4]}}, pyc_extract_245}; +assign pyc_mul_247 = (pyc_sext_243 * pyc_sext_244); +assign pe_int_s1_p2c0_1__next = pyc_mul_247; +assign pyc_mul_248 = (pyc_sext_243 * pyc_sext_246); +assign pe_int_s1_p2c1_1__next = pyc_mul_248; +assign pyc_sext_249 = {{27{pyc_extract_78[4]}}, pyc_extract_78}; +assign pyc_sext_250 = {{27{pyc_extract_84[4]}}, pyc_extract_84}; +assign pyc_extract_251 = pe_int_s0_b1[14:10]; +assign pyc_sext_252 = {{27{pyc_extract_251[4]}}, pyc_extract_251}; +assign pyc_mul_253 = (pyc_sext_249 * pyc_sext_250); +assign pe_int_s1_p2c0_2__next = pyc_mul_253; +assign pyc_mul_254 = (pyc_sext_249 * pyc_sext_252); +assign pe_int_s1_p2c1_2__next = pyc_mul_254; +assign pyc_sext_255 = {{27{pyc_extract_79[4]}}, pyc_extract_79}; +assign pyc_sext_256 = {{27{pyc_extract_85[4]}}, pyc_extract_85}; +assign pyc_extract_257 = pe_int_s0_b1[19:15]; +assign pyc_sext_258 = {{27{pyc_extract_257[4]}}, pyc_extract_257}; +assign pyc_mul_259 = (pyc_sext_255 * pyc_sext_256); +assign pe_int_s1_p2c0_3__next = pyc_mul_259; +assign pyc_mul_260 = (pyc_sext_255 * pyc_sext_258); +assign pe_int_s1_p2c1_3__next = pyc_mul_260; +assign pyc_sext_261 = {{27{pyc_extract_103[4]}}, pyc_extract_103}; +assign pyc_sext_262 = {{27{pyc_extract_109[4]}}, pyc_extract_109}; +assign pyc_extract_263 = pe_int_s0_b1[24:20]; +assign pyc_sext_264 = {{27{pyc_extract_263[4]}}, pyc_extract_263}; +assign pyc_mul_265 = (pyc_sext_261 * pyc_sext_262); +assign pe_int_s1_p2c0_4__next = pyc_mul_265; +assign pyc_mul_266 = (pyc_sext_261 * pyc_sext_264); +assign pe_int_s1_p2c1_4__next = pyc_mul_266; +assign pyc_sext_267 = {{27{pyc_extract_104[4]}}, pyc_extract_104}; +assign pyc_sext_268 = {{27{pyc_extract_110[4]}}, pyc_extract_110}; +assign pyc_extract_269 = pe_int_s0_b1[29:25]; +assign pyc_sext_270 = {{27{pyc_extract_269[4]}}, pyc_extract_269}; +assign pyc_mul_271 = (pyc_sext_267 * pyc_sext_268); +assign pe_int_s1_p2c0_5__next = pyc_mul_271; +assign pyc_mul_272 = (pyc_sext_267 * pyc_sext_270); +assign pe_int_s1_p2c1_5__next = pyc_mul_272; +assign pyc_sext_273 = {{27{pyc_extract_128[4]}}, pyc_extract_128}; +assign pyc_sext_274 = {{27{pyc_extract_134[4]}}, pyc_extract_134}; +assign pyc_extract_275 = pe_int_s0_b1[34:30]; +assign pyc_sext_276 = {{27{pyc_extract_275[4]}}, pyc_extract_275}; +assign pyc_mul_277 = (pyc_sext_273 * pyc_sext_274); +assign pe_int_s1_p2c0_6__next = pyc_mul_277; +assign pyc_mul_278 = (pyc_sext_273 * pyc_sext_276); +assign pe_int_s1_p2c1_6__next = pyc_mul_278; +assign pyc_sext_279 = {{27{pyc_extract_129[4]}}, pyc_extract_129}; +assign pyc_sext_280 = {{27{pyc_extract_135[4]}}, pyc_extract_135}; +assign pyc_extract_281 = pe_int_s0_b1[39:35]; +assign pyc_sext_282 = {{27{pyc_extract_281[4]}}, pyc_extract_281}; +assign pyc_mul_283 = (pyc_sext_279 * pyc_sext_280); +assign pe_int_s1_p2c0_7__next = pyc_mul_283; +assign pyc_mul_284 = (pyc_sext_279 * pyc_sext_282); +assign pe_int_s1_p2c1_7__next = pyc_mul_284; +assign pyc_sext_285 = {{27{pyc_extract_153[4]}}, pyc_extract_153}; +assign pyc_extract_286 = pe_int_s0_b1[44:40]; +assign pyc_sext_287 = {{27{pyc_extract_286[4]}}, pyc_extract_286}; +assign pyc_mul_288 = (pyc_sext_285 * pyc_sext_72); +assign pe_int_s1_p2c0_8__next = pyc_mul_288; +assign pyc_mul_289 = (pyc_sext_285 * pyc_sext_287); +assign pe_int_s1_p2c1_8__next = pyc_mul_289; +assign pyc_sext_290 = {{27{pyc_extract_154[4]}}, pyc_extract_154}; +assign pyc_extract_291 = pe_int_s0_b1[49:45]; +assign pyc_sext_292 = {{27{pyc_extract_291[4]}}, pyc_extract_291}; +assign pyc_mul_293 = (pyc_sext_290 * pyc_sext_97); +assign pe_int_s1_p2c0_9__next = pyc_mul_293; +assign pyc_mul_294 = (pyc_sext_290 * pyc_sext_292); +assign pe_int_s1_p2c1_9__next = pyc_mul_294; +assign pyc_sext_295 = {{27{pyc_extract_174[4]}}, pyc_extract_174}; +assign pyc_extract_296 = pe_int_s0_b1[54:50]; +assign pyc_sext_297 = {{27{pyc_extract_296[4]}}, pyc_extract_296}; +assign pyc_mul_298 = (pyc_sext_295 * pyc_sext_122); +assign pe_int_s1_p2c0_10__next = pyc_mul_298; +assign pyc_mul_299 = (pyc_sext_295 * pyc_sext_297); +assign pe_int_s1_p2c1_10__next = pyc_mul_299; +assign pyc_sext_300 = {{27{pyc_extract_175[4]}}, pyc_extract_175}; +assign pyc_extract_301 = pe_int_s0_b1[59:55]; +assign pyc_sext_302 = {{27{pyc_extract_301[4]}}, pyc_extract_301}; +assign pyc_mul_303 = (pyc_sext_300 * pyc_sext_147); +assign pe_int_s1_p2c0_11__next = pyc_mul_303; +assign pyc_mul_304 = (pyc_sext_300 * pyc_sext_302); +assign pe_int_s1_p2c1_11__next = pyc_mul_304; +assign pyc_sext_305 = {{27{pyc_extract_195[4]}}, pyc_extract_195}; +assign pyc_extract_306 = pe_int_s0_b1[64:60]; +assign pyc_sext_307 = {{27{pyc_extract_306[4]}}, pyc_extract_306}; +assign pyc_mul_308 = (pyc_sext_305 * pyc_sext_168); +assign pe_int_s1_p2c0_12__next = pyc_mul_308; +assign pyc_mul_309 = (pyc_sext_305 * pyc_sext_307); +assign pe_int_s1_p2c1_12__next = pyc_mul_309; +assign pyc_sext_310 = {{27{pyc_extract_196[4]}}, pyc_extract_196}; +assign pyc_extract_311 = pe_int_s0_b1[69:65]; +assign pyc_sext_312 = {{27{pyc_extract_311[4]}}, pyc_extract_311}; +assign pyc_mul_313 = (pyc_sext_310 * pyc_sext_189); +assign pe_int_s1_p2c0_13__next = pyc_mul_313; +assign pyc_mul_314 = (pyc_sext_310 * pyc_sext_312); +assign pe_int_s1_p2c1_13__next = pyc_mul_314; +assign pyc_sext_315 = {{27{pyc_extract_216[4]}}, pyc_extract_216}; +assign pyc_extract_316 = pe_int_s0_b1[74:70]; +assign pyc_sext_317 = {{27{pyc_extract_316[4]}}, pyc_extract_316}; +assign pyc_mul_318 = (pyc_sext_315 * pyc_sext_210); +assign pe_int_s1_p2c0_14__next = pyc_mul_318; +assign pyc_mul_319 = (pyc_sext_315 * pyc_sext_317); +assign pe_int_s1_p2c1_14__next = pyc_mul_319; +assign pyc_sext_320 = {{27{pyc_extract_217[4]}}, pyc_extract_217}; +assign pyc_extract_321 = pe_int_s0_b1[79:75]; +assign pyc_sext_322 = {{27{pyc_extract_321[4]}}, pyc_extract_321}; +assign pyc_mul_323 = (pyc_sext_320 * pyc_sext_231); +assign pe_int_s1_p2c0_15__next = pyc_mul_323; +assign pyc_mul_324 = (pyc_sext_320 * pyc_sext_322); +assign pe_int_s1_p2c1_15__next = pyc_mul_324; +assign pyc_comb_325 = pe_int_s1_e1_b1__next; +assign pyc_comb_326 = pe_int_s1_p2a_0__next; +assign pyc_comb_327 = pe_int_s1_p2b0_0__next; +assign pyc_comb_328 = pe_int_s1_p2b1_0__next; +assign pyc_comb_329 = pe_int_s1_p2d0_0__next; +assign pyc_comb_330 = pe_int_s1_p2d1_0__next; +assign pyc_comb_331 = pe_int_s1_p2a_1__next; +assign pyc_comb_332 = pe_int_s1_p2b0_1__next; +assign pyc_comb_333 = pe_int_s1_p2b1_1__next; +assign pyc_comb_334 = pe_int_s1_p2d0_1__next; +assign pyc_comb_335 = pe_int_s1_p2d1_1__next; +assign pyc_comb_336 = pe_int_s1_p2a_2__next; +assign pyc_comb_337 = pe_int_s1_p2b0_2__next; +assign pyc_comb_338 = pe_int_s1_p2b1_2__next; +assign pyc_comb_339 = pe_int_s1_p2d0_2__next; +assign pyc_comb_340 = pe_int_s1_p2d1_2__next; +assign pyc_comb_341 = pe_int_s1_p2a_3__next; +assign pyc_comb_342 = pe_int_s1_p2b0_3__next; +assign pyc_comb_343 = pe_int_s1_p2b1_3__next; +assign pyc_comb_344 = pe_int_s1_p2d0_3__next; +assign pyc_comb_345 = pe_int_s1_p2d1_3__next; +assign pyc_comb_346 = pe_int_s1_p2a_4__next; +assign pyc_comb_347 = pe_int_s1_p2b0_4__next; +assign pyc_comb_348 = pe_int_s1_p2b1_4__next; +assign pyc_comb_349 = pe_int_s1_p2d0_4__next; +assign pyc_comb_350 = pe_int_s1_p2d1_4__next; +assign pyc_comb_351 = pe_int_s1_p2a_5__next; +assign pyc_comb_352 = pe_int_s1_p2b0_5__next; +assign pyc_comb_353 = pe_int_s1_p2b1_5__next; +assign pyc_comb_354 = pe_int_s1_p2d0_5__next; +assign pyc_comb_355 = pe_int_s1_p2d1_5__next; +assign pyc_comb_356 = pe_int_s1_p2a_6__next; +assign pyc_comb_357 = pe_int_s1_p2b0_6__next; +assign pyc_comb_358 = pe_int_s1_p2b1_6__next; +assign pyc_comb_359 = pe_int_s1_p2d0_6__next; +assign pyc_comb_360 = pe_int_s1_p2d1_6__next; +assign pyc_comb_361 = pe_int_s1_p2a_7__next; +assign pyc_comb_362 = pe_int_s1_p2b0_7__next; +assign pyc_comb_363 = pe_int_s1_p2b1_7__next; +assign pyc_comb_364 = pe_int_s1_p2d0_7__next; +assign pyc_comb_365 = pe_int_s1_p2d1_7__next; +assign pyc_comb_366 = pe_int_s1_p2c0_0__next; +assign pyc_comb_367 = pe_int_s1_p2c1_0__next; +assign pyc_comb_368 = pe_int_s1_p2c0_1__next; +assign pyc_comb_369 = pe_int_s1_p2c1_1__next; +assign pyc_comb_370 = pe_int_s1_p2c0_2__next; +assign pyc_comb_371 = pe_int_s1_p2c1_2__next; +assign pyc_comb_372 = pe_int_s1_p2c0_3__next; +assign pyc_comb_373 = pe_int_s1_p2c1_3__next; +assign pyc_comb_374 = pe_int_s1_p2c0_4__next; +assign pyc_comb_375 = pe_int_s1_p2c1_4__next; +assign pyc_comb_376 = pe_int_s1_p2c0_5__next; +assign pyc_comb_377 = pe_int_s1_p2c1_5__next; +assign pyc_comb_378 = pe_int_s1_p2c0_6__next; +assign pyc_comb_379 = pe_int_s1_p2c1_6__next; +assign pyc_comb_380 = pe_int_s1_p2c0_7__next; +assign pyc_comb_381 = pe_int_s1_p2c1_7__next; +assign pyc_comb_382 = pe_int_s1_p2c0_8__next; +assign pyc_comb_383 = pe_int_s1_p2c1_8__next; +assign pyc_comb_384 = pe_int_s1_p2c0_9__next; +assign pyc_comb_385 = pe_int_s1_p2c1_9__next; +assign pyc_comb_386 = pe_int_s1_p2c0_10__next; +assign pyc_comb_387 = pe_int_s1_p2c1_10__next; +assign pyc_comb_388 = pe_int_s1_p2c0_11__next; +assign pyc_comb_389 = pe_int_s1_p2c1_11__next; +assign pyc_comb_390 = pe_int_s1_p2c0_12__next; +assign pyc_comb_391 = pe_int_s1_p2c1_12__next; +assign pyc_comb_392 = pe_int_s1_p2c0_13__next; +assign pyc_comb_393 = pe_int_s1_p2c1_13__next; +assign pyc_comb_394 = pe_int_s1_p2c0_14__next; +assign pyc_comb_395 = pe_int_s1_p2c1_14__next; +assign pyc_comb_396 = pe_int_s1_p2c0_15__next; +assign pyc_comb_397 = pe_int_s1_p2c1_15__next; +assign pe_int_s0_vld = pyc_reg_34; +assign pe_int_s1_vld__next = pe_int_s0_vld; +assign pyc_comb_35 = pe_int_s1_vld__next; +assign pe_int_s0_is_2a = pyc_reg_36; +assign pe_int_s1_is_2a__next = pe_int_s0_is_2a; +assign pyc_comb_37 = pe_int_s1_is_2a__next; +assign pe_int_s0_is_2b = pyc_reg_38; +assign pe_int_s1_is_2b__next = pe_int_s0_is_2b; +assign pyc_comb_39 = pe_int_s1_is_2b__next; +assign pe_int_s1_vld = pyc_reg_398; +assign pe_int_s2_vld__next = pe_int_s1_vld; +assign pyc_comb_399 = pe_int_s2_vld__next; +assign pe_int_s1_is_2a = pyc_reg_400; +assign pe_int_s2_is_2a__next = pe_int_s1_is_2a; +assign pyc_comb_401 = pe_int_s2_is_2a__next; +assign pe_int_s1_is_2b = pyc_reg_402; +assign pe_int_s2_is_2b__next = pe_int_s1_is_2b; +assign pyc_comb_403 = pe_int_s2_is_2b__next; +assign pe_int_s1_is_2c = pyc_reg_404; +assign pe_int_s2_is_2c__next = pe_int_s1_is_2c; +assign pyc_comb_405 = pe_int_s2_is_2c__next; +assign pe_int_s1_e1_a = pyc_reg_407; +assign pe_int_s2_e1_a__next = pe_int_s1_e1_a; +assign pyc_comb_408 = pe_int_s2_e1_a__next; +assign pe_int_s0_is_2c = pyc_reg_40; +assign pe_int_s1_is_2c__next = pe_int_s0_is_2c; +assign pyc_comb_41 = pe_int_s1_is_2c__next; +assign pe_int_s1_e1_b0 = pyc_reg_409; +assign pe_int_s2_e1_b0__next = pe_int_s1_e1_b0; +assign pyc_comb_410 = pe_int_s2_e1_b0__next; +assign pe_int_s1_e1_b1 = pyc_reg_411; +assign pe_int_s2_e1_b1__next = pe_int_s1_e1_b1; +assign pyc_comb_412 = pe_int_s2_e1_b1__next; +assign pe_int_s0_is_2d = pyc_reg_42; +assign pe_int_s1_is_2d__next = pe_int_s0_is_2d; +assign pyc_comb_43 = pe_int_s1_is_2d__next; +assign pe_int_s0_e1_a = pyc_reg_47; +assign pe_int_s1_e1_a__next = pe_int_s0_e1_a; +assign pyc_comb_48 = pe_int_s1_e1_a__next; +assign pe_int_s0_e1_b0 = pyc_reg_49; +assign pe_int_s1_e1_b0__next = pe_int_s0_e1_b0; +assign pyc_comb_50 = pe_int_s1_e1_b0__next; +assign pe_int_s1_p2c1_15 = pyc_reg_484; +assign pyc_add_485 = (pe_int_s1_p2a_0 + pe_int_s1_p2a_1); +assign pyc_add_486 = (pyc_add_485 + pe_int_s1_p2a_2); +assign pyc_add_487 = (pyc_add_486 + pe_int_s1_p2a_3); +assign pyc_add_488 = (pyc_add_487 + pe_int_s1_p2a_4); +assign pyc_add_489 = (pyc_add_488 + pe_int_s1_p2a_5); +assign pyc_add_490 = (pyc_add_489 + pe_int_s1_p2a_6); +assign pyc_add_491 = (pyc_add_490 + pe_int_s1_p2a_7); +assign pe_int_s2_s2a__next = pyc_add_491; +assign pyc_add_492 = (pe_int_s1_p2b0_0 + pe_int_s1_p2b0_1); +assign pyc_add_493 = (pyc_add_492 + pe_int_s1_p2b0_2); +assign pyc_add_494 = (pyc_add_493 + pe_int_s1_p2b0_3); +assign pyc_add_495 = (pyc_add_494 + pe_int_s1_p2b0_4); +assign pyc_add_496 = (pyc_add_495 + pe_int_s1_p2b0_5); +assign pyc_add_497 = (pyc_add_496 + pe_int_s1_p2b0_6); +assign pyc_add_498 = (pyc_add_497 + pe_int_s1_p2b0_7); +assign pe_int_s2_s2b0__next = pyc_add_498; +assign pyc_add_499 = (pe_int_s1_p2b1_0 + pe_int_s1_p2b1_1); +assign pyc_add_500 = (pyc_add_499 + pe_int_s1_p2b1_2); +assign pyc_add_501 = (pyc_add_500 + pe_int_s1_p2b1_3); +assign pyc_add_502 = (pyc_add_501 + pe_int_s1_p2b1_4); +assign pyc_add_503 = (pyc_add_502 + pe_int_s1_p2b1_5); +assign pyc_add_504 = (pyc_add_503 + pe_int_s1_p2b1_6); +assign pyc_add_505 = (pyc_add_504 + pe_int_s1_p2b1_7); +assign pe_int_s2_s2b1__next = pyc_add_505; +assign pyc_add_506 = (pe_int_s1_p2d0_0 + pe_int_s1_p2d0_1); +assign pyc_add_507 = (pyc_add_506 + pe_int_s1_p2d0_2); +assign pyc_add_508 = (pyc_add_507 + pe_int_s1_p2d0_3); +assign pyc_add_509 = (pyc_add_508 + pe_int_s1_p2d0_4); +assign pyc_add_510 = (pyc_add_509 + pe_int_s1_p2d0_5); +assign pyc_add_511 = (pyc_add_510 + pe_int_s1_p2d0_6); +assign pyc_add_512 = (pyc_add_511 + pe_int_s1_p2d0_7); +assign pe_int_s2_s2d0__next = pyc_add_512; +assign pyc_add_513 = (pe_int_s1_p2d1_0 + pe_int_s1_p2d1_1); +assign pyc_add_514 = (pyc_add_513 + pe_int_s1_p2d1_2); +assign pyc_add_515 = (pyc_add_514 + pe_int_s1_p2d1_3); +assign pyc_add_516 = (pyc_add_515 + pe_int_s1_p2d1_4); +assign pyc_add_517 = (pyc_add_516 + pe_int_s1_p2d1_5); +assign pyc_add_518 = (pyc_add_517 + pe_int_s1_p2d1_6); +assign pyc_add_519 = (pyc_add_518 + pe_int_s1_p2d1_7); +assign pe_int_s2_s2d1__next = pyc_add_519; +assign pyc_add_520 = (pe_int_s1_p2c0_0 + pe_int_s1_p2c0_1); +assign pyc_add_521 = (pyc_add_520 + pe_int_s1_p2c0_2); +assign pyc_add_522 = (pyc_add_521 + pe_int_s1_p2c0_3); +assign pyc_add_523 = (pyc_add_522 + pe_int_s1_p2c0_4); +assign pyc_add_524 = (pyc_add_523 + pe_int_s1_p2c0_5); +assign pyc_add_525 = (pyc_add_524 + pe_int_s1_p2c0_6); +assign pyc_add_526 = (pyc_add_525 + pe_int_s1_p2c0_7); +assign pe_int_s2_s2c0_lo__next = pyc_add_526; +assign pyc_add_527 = (pe_int_s1_p2c0_8 + pe_int_s1_p2c0_9); +assign pyc_add_528 = (pyc_add_527 + pe_int_s1_p2c0_10); +assign pyc_add_529 = (pyc_add_528 + pe_int_s1_p2c0_11); +assign pyc_add_530 = (pyc_add_529 + pe_int_s1_p2c0_12); +assign pyc_add_531 = (pyc_add_530 + pe_int_s1_p2c0_13); +assign pyc_add_532 = (pyc_add_531 + pe_int_s1_p2c0_14); +assign pyc_add_533 = (pyc_add_532 + pe_int_s1_p2c0_15); +assign pe_int_s2_s2c0_hi__next = pyc_add_533; +assign pyc_add_534 = (pe_int_s1_p2c1_0 + pe_int_s1_p2c1_1); +assign pyc_add_535 = (pyc_add_534 + pe_int_s1_p2c1_2); +assign pyc_add_536 = (pyc_add_535 + pe_int_s1_p2c1_3); +assign pyc_add_537 = (pyc_add_536 + pe_int_s1_p2c1_4); +assign pyc_add_538 = (pyc_add_537 + pe_int_s1_p2c1_5); +assign pyc_add_539 = (pyc_add_538 + pe_int_s1_p2c1_6); +assign pyc_add_540 = (pyc_add_539 + pe_int_s1_p2c1_7); +assign pe_int_s2_s2c1_lo__next = pyc_add_540; +assign pyc_add_541 = (pe_int_s1_p2c1_8 + pe_int_s1_p2c1_9); +assign pyc_add_542 = (pyc_add_541 + pe_int_s1_p2c1_10); +assign pyc_add_543 = (pyc_add_542 + pe_int_s1_p2c1_11); +assign pyc_add_544 = (pyc_add_543 + pe_int_s1_p2c1_12); +assign pyc_add_545 = (pyc_add_544 + pe_int_s1_p2c1_13); +assign pyc_add_546 = (pyc_add_545 + pe_int_s1_p2c1_14); +assign pyc_add_547 = (pyc_add_546 + pe_int_s1_p2c1_15); +assign pe_int_s2_s2c1_hi__next = pyc_add_547; +assign pyc_comb_548 = pe_int_s2_s2a__next; +assign pyc_comb_549 = pe_int_s2_s2b0__next; +assign pyc_comb_550 = pe_int_s2_s2b1__next; +assign pyc_comb_551 = pe_int_s2_s2d0__next; +assign pyc_comb_552 = pe_int_s2_s2d1__next; +assign pyc_comb_553 = pe_int_s2_s2c0_lo__next; +assign pyc_comb_554 = pe_int_s2_s2c0_hi__next; +assign pyc_comb_555 = pe_int_s2_s2c1_lo__next; +assign pyc_comb_556 = pe_int_s2_s2c1_hi__next; +assign pe_int_s2_vld = pyc_reg_557; +assign pe_int_out_vld__next = pe_int_s2_vld; +assign pyc_concat_558 = {pyc_comb_405, pyc_comb_403, pyc_comb_401}; +assign pyc_concat_559 = {pyc_comb_22, pyc_comb_22, pyc_comb_22}; +assign pyc_comb_560 = pe_int_s2_vld; +assign pyc_comb_561 = pe_int_out_vld__next; +assign pyc_comb_562 = pyc_concat_558; +assign pyc_comb_563 = pyc_concat_559; +assign pyc_extract_565 = pyc_reg_564[0]; +assign pyc_extract_566 = pyc_reg_564[1]; +assign pyc_extract_567 = pyc_reg_564[2]; +assign pe_int_s2_is_2a = pyc_extract_565; +assign pe_int_s2_is_2b = pyc_extract_566; +assign pe_int_s2_is_2c = pyc_extract_567; +assign pyc_comb_568 = pe_int_s2_is_2a; +assign pyc_comb_569 = pe_int_s2_is_2b; +assign pyc_comb_570 = pe_int_s2_is_2c; +assign pe_int_s2_s2c1_hi = pyc_reg_582; +assign pyc_extract_583 = pe_int_s2_e1_a[0]; +assign pyc_zext_584 = {{1{1'b0}}, pyc_extract_583}; +assign pyc_extract_585 = pe_int_s2_e1_b0[0]; +assign pyc_zext_586 = {{1{1'b0}}, pyc_extract_585}; +assign pyc_add_587 = (pyc_zext_584 + pyc_zext_586); +assign pyc_extract_588 = pe_int_s2_e1_a[1]; +assign pyc_zext_589 = {{1{1'b0}}, pyc_extract_588}; +assign pyc_extract_590 = pe_int_s2_e1_b0[1]; +assign pyc_zext_591 = {{1{1'b0}}, pyc_extract_590}; +assign pyc_add_592 = (pyc_zext_589 + pyc_zext_591); +assign pyc_add_593 = (pe_int_s2_s2c0_lo + pe_int_s2_s2c0_lo); +assign pyc_add_594 = (pyc_add_593 + pyc_add_593); +assign pyc_eq_595 = (pyc_add_587 == pyc_comb_19); +assign pyc_eq_596 = (pyc_add_587 == pyc_comb_17); +assign pyc_mux_597 = (pyc_eq_596 ? pyc_add_593 : pyc_add_594); +assign pyc_mux_598 = (pyc_eq_595 ? pe_int_s2_s2c0_lo : pyc_mux_597); +assign pyc_add_599 = (pe_int_s2_s2c0_hi + pe_int_s2_s2c0_hi); +assign pyc_add_600 = (pyc_add_599 + pyc_add_599); +assign pyc_eq_601 = (pyc_add_592 == pyc_comb_19); +assign pyc_eq_602 = (pyc_add_592 == pyc_comb_17); +assign pyc_mux_603 = (pyc_eq_602 ? pyc_add_599 : pyc_add_600); +assign pyc_mux_604 = (pyc_eq_601 ? pe_int_s2_s2c0_hi : pyc_mux_603); +assign pyc_add_605 = (pyc_mux_598 + pyc_mux_604); +assign pyc_extract_606 = pe_int_s2_e1_b1[0]; +assign pyc_zext_607 = {{1{1'b0}}, pyc_extract_606}; +assign pyc_add_608 = (pyc_zext_584 + pyc_zext_607); +assign pyc_extract_609 = pe_int_s2_e1_b1[1]; +assign pyc_zext_610 = {{1{1'b0}}, pyc_extract_609}; +assign pyc_add_611 = (pyc_zext_589 + pyc_zext_610); +assign pyc_add_612 = (pe_int_s2_s2c1_lo + pe_int_s2_s2c1_lo); +assign pyc_add_613 = (pyc_add_612 + pyc_add_612); +assign pyc_eq_614 = (pyc_add_608 == pyc_comb_19); +assign pyc_eq_615 = (pyc_add_608 == pyc_comb_17); +assign pyc_mux_616 = (pyc_eq_615 ? pyc_add_612 : pyc_add_613); +assign pyc_mux_617 = (pyc_eq_614 ? pe_int_s2_s2c1_lo : pyc_mux_616); +assign pyc_add_618 = (pe_int_s2_s2c1_hi + pe_int_s2_s2c1_hi); +assign pyc_add_619 = (pyc_add_618 + pyc_add_618); +assign pyc_eq_620 = (pyc_add_611 == pyc_comb_19); +assign pyc_eq_621 = (pyc_add_611 == pyc_comb_17); +assign pyc_mux_622 = (pyc_eq_621 ? pyc_add_618 : pyc_add_619); +assign pyc_mux_623 = (pyc_eq_620 ? pe_int_s2_s2c1_hi : pyc_mux_622); +assign pyc_add_624 = (pyc_mux_617 + pyc_mux_623); +assign pyc_mux_625 = (pyc_comb_570 ? pyc_add_605 : pe_int_s2_s2d0); +assign pyc_mux_626 = (pyc_comb_569 ? pe_int_s2_s2b0 : pyc_mux_625); +assign pyc_mux_627 = (pyc_comb_568 ? pe_int_s2_s2a : pyc_mux_626); +assign pyc_mux_628 = (pyc_comb_570 ? pyc_add_624 : pe_int_s2_s2d1); +assign pyc_mux_629 = (pyc_comb_569 ? pe_int_s2_s2b1 : pyc_mux_628); +assign pyc_mux_630 = (pyc_comb_568 ? pe_int_s2_s2b1 : pyc_mux_629); +assign c3_out0_raw___pycircuit_v5_strip_domain___L63 = pyc_mux_627; +assign c3_out1_raw___pycircuit_v5_strip_domain___L63 = pyc_mux_630; +assign pyc_extract_631 = c3_out0_raw___pycircuit_v5_strip_domain___L63[18:0]; +assign c3_out0___pycircuit_v5_strip_domain___L64 = pyc_extract_631; +assign pe_int_out0__next = c3_out0___pycircuit_v5_strip_domain___L64; +assign pyc_extract_632 = c3_out1_raw___pycircuit_v5_strip_domain___L63[15:0]; +assign c3_out1___pycircuit_v5_strip_domain___L65 = pyc_extract_632; +assign pyc_comb_633 = pe_int_out0__next; +assign pyc_comb_634 = c3_out1___pycircuit_v5_strip_domain___L65; +assign pe_int_out1_hold = pyc_reg_635; +assign pyc_mux_636 = (pyc_comb_568 ? pe_int_out1_hold : pyc_comb_634); +assign pyc_mux_637 = (pyc_comb_560 ? pyc_mux_636 : pe_int_out1_hold); +assign out1_commit___pycircuit_v5_strip_domain___L67 = pyc_mux_637; +assign pe_int_out1__next = out1_commit___pycircuit_v5_strip_domain___L67; +assign pyc_comb_638 = out1_commit___pycircuit_v5_strip_domain___L67; +assign pyc_comb_639 = pe_int_out1__next; +assign pe_int_out1_hold__next = pyc_comb_638; + +// --- Sequential primitives +pyc_reg #(.WIDTH(1)) pyc_reg_34_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_29), + .init(pyc_comb_22), + .q(pyc_reg_34) +); +pyc_reg #(.WIDTH(1)) pyc_reg_36_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_30), + .init(pyc_comb_22), + .q(pyc_reg_36) +); +pyc_reg #(.WIDTH(1)) pyc_reg_38_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_31), + .init(pyc_comb_22), + .q(pyc_reg_38) +); +pyc_reg #(.WIDTH(1)) pyc_reg_398_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_35), + .init(pyc_comb_22), + .q(pyc_reg_398) +); +pyc_reg #(.WIDTH(1)) pyc_reg_40_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_32), + .init(pyc_comb_22), + .q(pyc_reg_40) +); +pyc_reg #(.WIDTH(1)) pyc_reg_400_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_37), + .init(pyc_comb_22), + .q(pyc_reg_400) +); +pyc_reg #(.WIDTH(1)) pyc_reg_402_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_39), + .init(pyc_comb_22), + .q(pyc_reg_402) +); +pyc_reg #(.WIDTH(1)) pyc_reg_404_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_41), + .init(pyc_comb_22), + .q(pyc_reg_404) +); +pyc_reg #(.WIDTH(1)) pyc_reg_406_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_43), + .init(pyc_comb_22), + .q(pyc_reg_406) +); +pyc_reg #(.WIDTH(2)) pyc_reg_407_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_48), + .init(pyc_comb_19), + .q(pyc_reg_407) +); +pyc_reg #(.WIDTH(2)) pyc_reg_409_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_50), + .init(pyc_comb_19), + .q(pyc_reg_409) +); +pyc_reg #(.WIDTH(2)) pyc_reg_411_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_325), + .init(pyc_comb_19), + .q(pyc_reg_411) +); +pyc_reg #(.WIDTH(32)) pyc_reg_413_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_326), + .init(pyc_comb_18), + .q(pyc_reg_413) +); +pyc_reg #(.WIDTH(32)) pyc_reg_414_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_331), + .init(pyc_comb_18), + .q(pyc_reg_414) +); +pyc_reg #(.WIDTH(32)) pyc_reg_415_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_336), + .init(pyc_comb_18), + .q(pyc_reg_415) +); +pyc_reg #(.WIDTH(32)) pyc_reg_416_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_341), + .init(pyc_comb_18), + .q(pyc_reg_416) +); +pyc_reg #(.WIDTH(32)) pyc_reg_417_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_346), + .init(pyc_comb_18), + .q(pyc_reg_417) +); +pyc_reg #(.WIDTH(32)) pyc_reg_418_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_351), + .init(pyc_comb_18), + .q(pyc_reg_418) +); +pyc_reg #(.WIDTH(32)) pyc_reg_419_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_356), + .init(pyc_comb_18), + .q(pyc_reg_419) +); +pyc_reg #(.WIDTH(1)) pyc_reg_42_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_33), + .init(pyc_comb_22), + .q(pyc_reg_42) +); +pyc_reg #(.WIDTH(32)) pyc_reg_420_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_361), + .init(pyc_comb_18), + .q(pyc_reg_420) +); +pyc_reg #(.WIDTH(32)) pyc_reg_421_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_327), + .init(pyc_comb_18), + .q(pyc_reg_421) +); +pyc_reg #(.WIDTH(32)) pyc_reg_422_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_332), + .init(pyc_comb_18), + .q(pyc_reg_422) +); +pyc_reg #(.WIDTH(32)) pyc_reg_423_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_337), + .init(pyc_comb_18), + .q(pyc_reg_423) +); +pyc_reg #(.WIDTH(32)) pyc_reg_424_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_342), + .init(pyc_comb_18), + .q(pyc_reg_424) +); +pyc_reg #(.WIDTH(32)) pyc_reg_425_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_347), + .init(pyc_comb_18), + .q(pyc_reg_425) +); +pyc_reg #(.WIDTH(32)) pyc_reg_426_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_352), + .init(pyc_comb_18), + .q(pyc_reg_426) +); +pyc_reg #(.WIDTH(32)) pyc_reg_427_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_357), + .init(pyc_comb_18), + .q(pyc_reg_427) +); +pyc_reg #(.WIDTH(32)) pyc_reg_428_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_362), + .init(pyc_comb_18), + .q(pyc_reg_428) +); +pyc_reg #(.WIDTH(32)) pyc_reg_429_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_328), + .init(pyc_comb_18), + .q(pyc_reg_429) +); +pyc_reg #(.WIDTH(32)) pyc_reg_430_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_333), + .init(pyc_comb_18), + .q(pyc_reg_430) +); +pyc_reg #(.WIDTH(32)) pyc_reg_431_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_338), + .init(pyc_comb_18), + .q(pyc_reg_431) +); +pyc_reg #(.WIDTH(32)) pyc_reg_432_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_343), + .init(pyc_comb_18), + .q(pyc_reg_432) +); +pyc_reg #(.WIDTH(32)) pyc_reg_433_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_348), + .init(pyc_comb_18), + .q(pyc_reg_433) +); +pyc_reg #(.WIDTH(32)) pyc_reg_434_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_353), + .init(pyc_comb_18), + .q(pyc_reg_434) +); +pyc_reg #(.WIDTH(32)) pyc_reg_435_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_358), + .init(pyc_comb_18), + .q(pyc_reg_435) +); +pyc_reg #(.WIDTH(32)) pyc_reg_436_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_363), + .init(pyc_comb_18), + .q(pyc_reg_436) +); +pyc_reg #(.WIDTH(32)) pyc_reg_437_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_329), + .init(pyc_comb_18), + .q(pyc_reg_437) +); +pyc_reg #(.WIDTH(32)) pyc_reg_438_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_334), + .init(pyc_comb_18), + .q(pyc_reg_438) +); +pyc_reg #(.WIDTH(32)) pyc_reg_439_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_339), + .init(pyc_comb_18), + .q(pyc_reg_439) +); +pyc_reg #(.WIDTH(80)) pyc_reg_44_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_28), + .init(pyc_comb_20), + .q(pyc_reg_44) +); +pyc_reg #(.WIDTH(32)) pyc_reg_440_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_344), + .init(pyc_comb_18), + .q(pyc_reg_440) +); +pyc_reg #(.WIDTH(32)) pyc_reg_441_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_349), + .init(pyc_comb_18), + .q(pyc_reg_441) +); +pyc_reg #(.WIDTH(32)) pyc_reg_442_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_354), + .init(pyc_comb_18), + .q(pyc_reg_442) +); +pyc_reg #(.WIDTH(32)) pyc_reg_443_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_359), + .init(pyc_comb_18), + .q(pyc_reg_443) +); +pyc_reg #(.WIDTH(32)) pyc_reg_444_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_364), + .init(pyc_comb_18), + .q(pyc_reg_444) +); +pyc_reg #(.WIDTH(32)) pyc_reg_445_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_330), + .init(pyc_comb_18), + .q(pyc_reg_445) +); +pyc_reg #(.WIDTH(32)) pyc_reg_446_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_335), + .init(pyc_comb_18), + .q(pyc_reg_446) +); +pyc_reg #(.WIDTH(32)) pyc_reg_447_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_340), + .init(pyc_comb_18), + .q(pyc_reg_447) +); +pyc_reg #(.WIDTH(32)) pyc_reg_448_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_345), + .init(pyc_comb_18), + .q(pyc_reg_448) +); +pyc_reg #(.WIDTH(32)) pyc_reg_449_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_350), + .init(pyc_comb_18), + .q(pyc_reg_449) +); +pyc_reg #(.WIDTH(80)) pyc_reg_45_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_27), + .init(pyc_comb_20), + .q(pyc_reg_45) +); +pyc_reg #(.WIDTH(32)) pyc_reg_450_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_355), + .init(pyc_comb_18), + .q(pyc_reg_450) +); +pyc_reg #(.WIDTH(32)) pyc_reg_451_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_360), + .init(pyc_comb_18), + .q(pyc_reg_451) +); +pyc_reg #(.WIDTH(32)) pyc_reg_452_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_365), + .init(pyc_comb_18), + .q(pyc_reg_452) +); +pyc_reg #(.WIDTH(32)) pyc_reg_453_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_366), + .init(pyc_comb_18), + .q(pyc_reg_453) +); +pyc_reg #(.WIDTH(32)) pyc_reg_454_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_368), + .init(pyc_comb_18), + .q(pyc_reg_454) +); +pyc_reg #(.WIDTH(32)) pyc_reg_455_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_370), + .init(pyc_comb_18), + .q(pyc_reg_455) +); +pyc_reg #(.WIDTH(32)) pyc_reg_456_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_372), + .init(pyc_comb_18), + .q(pyc_reg_456) +); +pyc_reg #(.WIDTH(32)) pyc_reg_457_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_374), + .init(pyc_comb_18), + .q(pyc_reg_457) +); +pyc_reg #(.WIDTH(32)) pyc_reg_458_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_376), + .init(pyc_comb_18), + .q(pyc_reg_458) +); +pyc_reg #(.WIDTH(32)) pyc_reg_459_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_378), + .init(pyc_comb_18), + .q(pyc_reg_459) +); +pyc_reg #(.WIDTH(80)) pyc_reg_46_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_26), + .init(pyc_comb_20), + .q(pyc_reg_46) +); +pyc_reg #(.WIDTH(32)) pyc_reg_460_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_380), + .init(pyc_comb_18), + .q(pyc_reg_460) +); +pyc_reg #(.WIDTH(32)) pyc_reg_461_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_382), + .init(pyc_comb_18), + .q(pyc_reg_461) +); +pyc_reg #(.WIDTH(32)) pyc_reg_462_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_384), + .init(pyc_comb_18), + .q(pyc_reg_462) +); +pyc_reg #(.WIDTH(32)) pyc_reg_463_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_386), + .init(pyc_comb_18), + .q(pyc_reg_463) +); +pyc_reg #(.WIDTH(32)) pyc_reg_464_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_388), + .init(pyc_comb_18), + .q(pyc_reg_464) +); +pyc_reg #(.WIDTH(32)) pyc_reg_465_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_390), + .init(pyc_comb_18), + .q(pyc_reg_465) +); +pyc_reg #(.WIDTH(32)) pyc_reg_466_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_392), + .init(pyc_comb_18), + .q(pyc_reg_466) +); +pyc_reg #(.WIDTH(32)) pyc_reg_467_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_394), + .init(pyc_comb_18), + .q(pyc_reg_467) +); +pyc_reg #(.WIDTH(32)) pyc_reg_468_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_396), + .init(pyc_comb_18), + .q(pyc_reg_468) +); +pyc_reg #(.WIDTH(32)) pyc_reg_469_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_367), + .init(pyc_comb_18), + .q(pyc_reg_469) +); +pyc_reg #(.WIDTH(2)) pyc_reg_47_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_25), + .init(pyc_comb_19), + .q(pyc_reg_47) +); +pyc_reg #(.WIDTH(32)) pyc_reg_470_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_369), + .init(pyc_comb_18), + .q(pyc_reg_470) +); +pyc_reg #(.WIDTH(32)) pyc_reg_471_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_371), + .init(pyc_comb_18), + .q(pyc_reg_471) +); +pyc_reg #(.WIDTH(32)) pyc_reg_472_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_373), + .init(pyc_comb_18), + .q(pyc_reg_472) +); +pyc_reg #(.WIDTH(32)) pyc_reg_473_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_375), + .init(pyc_comb_18), + .q(pyc_reg_473) +); +pyc_reg #(.WIDTH(32)) pyc_reg_474_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_377), + .init(pyc_comb_18), + .q(pyc_reg_474) +); +pyc_reg #(.WIDTH(32)) pyc_reg_475_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_379), + .init(pyc_comb_18), + .q(pyc_reg_475) +); +pyc_reg #(.WIDTH(32)) pyc_reg_476_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_381), + .init(pyc_comb_18), + .q(pyc_reg_476) +); +pyc_reg #(.WIDTH(32)) pyc_reg_477_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_383), + .init(pyc_comb_18), + .q(pyc_reg_477) +); +pyc_reg #(.WIDTH(32)) pyc_reg_478_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_385), + .init(pyc_comb_18), + .q(pyc_reg_478) +); +pyc_reg #(.WIDTH(32)) pyc_reg_479_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_387), + .init(pyc_comb_18), + .q(pyc_reg_479) +); +pyc_reg #(.WIDTH(32)) pyc_reg_480_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_389), + .init(pyc_comb_18), + .q(pyc_reg_480) +); +pyc_reg #(.WIDTH(32)) pyc_reg_481_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_391), + .init(pyc_comb_18), + .q(pyc_reg_481) +); +pyc_reg #(.WIDTH(32)) pyc_reg_482_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_393), + .init(pyc_comb_18), + .q(pyc_reg_482) +); +pyc_reg #(.WIDTH(32)) pyc_reg_483_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_395), + .init(pyc_comb_18), + .q(pyc_reg_483) +); +pyc_reg #(.WIDTH(32)) pyc_reg_484_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_397), + .init(pyc_comb_18), + .q(pyc_reg_484) +); +pyc_reg #(.WIDTH(2)) pyc_reg_49_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_24), + .init(pyc_comb_19), + .q(pyc_reg_49) +); +pyc_reg #(.WIDTH(2)) pyc_reg_51_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_23), + .init(pyc_comb_19), + .q(pyc_reg_51) +); +pyc_reg #(.WIDTH(1)) pyc_reg_557_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_399), + .init(pyc_comb_22), + .q(pyc_reg_557) +); +pyc_reg #(.WIDTH(3)) pyc_reg_564_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_562), + .init(pyc_comb_563), + .q(pyc_reg_564) +); +pyc_reg #(.WIDTH(2)) pyc_reg_571_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_408), + .init(pyc_comb_19), + .q(pyc_reg_571) +); +pyc_reg #(.WIDTH(2)) pyc_reg_572_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_410), + .init(pyc_comb_19), + .q(pyc_reg_572) +); +pyc_reg #(.WIDTH(2)) pyc_reg_573_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_412), + .init(pyc_comb_19), + .q(pyc_reg_573) +); +pyc_reg #(.WIDTH(32)) pyc_reg_574_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_548), + .init(pyc_comb_18), + .q(pyc_reg_574) +); +pyc_reg #(.WIDTH(32)) pyc_reg_575_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_549), + .init(pyc_comb_18), + .q(pyc_reg_575) +); +pyc_reg #(.WIDTH(32)) pyc_reg_576_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_550), + .init(pyc_comb_18), + .q(pyc_reg_576) +); +pyc_reg #(.WIDTH(32)) pyc_reg_577_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_551), + .init(pyc_comb_18), + .q(pyc_reg_577) +); +pyc_reg #(.WIDTH(32)) pyc_reg_578_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_552), + .init(pyc_comb_18), + .q(pyc_reg_578) +); +pyc_reg #(.WIDTH(32)) pyc_reg_579_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_553), + .init(pyc_comb_18), + .q(pyc_reg_579) +); +pyc_reg #(.WIDTH(32)) pyc_reg_580_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_554), + .init(pyc_comb_18), + .q(pyc_reg_580) +); +pyc_reg #(.WIDTH(32)) pyc_reg_581_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_555), + .init(pyc_comb_18), + .q(pyc_reg_581) +); +pyc_reg #(.WIDTH(32)) pyc_reg_582_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_556), + .init(pyc_comb_18), + .q(pyc_reg_582) +); +pyc_reg #(.WIDTH(16)) pyc_reg_635_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pe_int_out1_hold__next), + .init(pyc_comb_16), + .q(pyc_reg_635) +); +pyc_reg #(.WIDTH(1)) pyc_reg_640_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_561), + .init(pyc_comb_22), + .q(pyc_reg_640) +); +pyc_reg #(.WIDTH(19)) pyc_reg_641_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_633), + .init(pyc_comb_15), + .q(pyc_reg_641) +); +pyc_reg #(.WIDTH(16)) pyc_reg_642_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_639), + .init(pyc_comb_16), + .q(pyc_reg_642) +); + +assign vld_out = pe_int_out_vld; +assign out0 = pe_int_out0; +assign out1 = pe_int_out1; + +endmodule + diff --git a/designs/PE_INT/rtl/pyc_primitives.v b/designs/PE_INT/rtl/build/pyc_primitives.v similarity index 96% rename from designs/PE_INT/rtl/pyc_primitives.v rename to designs/PE_INT/rtl/build/pyc_primitives.v index 6ae1348..6aa34a7 100644 --- a/designs/PE_INT/rtl/pyc_primitives.v +++ b/designs/PE_INT/rtl/build/pyc_primitives.v @@ -2,657 +2,657 @@ /* verilator lint_off DECLFILENAME */ // --- pyc_reg.v -// Simple synchronous reset register (prototype). -module pyc_reg #( - parameter WIDTH = 1 -) ( - input clk, - input rst, - input en, - input [WIDTH-1:0] d, - input [WIDTH-1:0] init, - output reg [WIDTH-1:0] q -); - always @(posedge clk) begin - if (rst) - q <= init; - else if (en) - q <= d; - end -endmodule +// Simple synchronous reset register (prototype). +module pyc_reg #( + parameter WIDTH = 1 +) ( + input clk, + input rst, + input en, + input [WIDTH-1:0] d, + input [WIDTH-1:0] init, + output reg [WIDTH-1:0] q +); + always @(posedge clk) begin + if (rst) + q <= init; + else if (en) + q <= d; + end +endmodule // --- pyc_fifo.v -// Ready/valid FIFO with synchronous reset (prototype). -module pyc_fifo #( - parameter WIDTH = 1, - parameter DEPTH = 2 -) ( - input clk, - input rst, - - // Input (producer -> fifo) - input in_valid, - output in_ready, - input [WIDTH-1:0] in_data, - - // Output (fifo -> consumer) - output out_valid, - input out_ready, - output [WIDTH-1:0] out_data -); - `ifndef SYNTHESIS - initial begin - if (DEPTH <= 0) begin - $display("ERROR: pyc_fifo DEPTH must be > 0"); - $finish; - end - end - `endif - - function integer pyc_clog2; - input integer value; - integer i; - begin - pyc_clog2 = 0; - for (i = value - 1; i > 0; i = i >> 1) - pyc_clog2 = pyc_clog2 + 1; - end - endfunction - - localparam PTR_W = (DEPTH <= 1) ? 1 : pyc_clog2(DEPTH); - - reg [WIDTH-1:0] storage [0:DEPTH-1]; - reg [PTR_W-1:0] rd_ptr; - reg [PTR_W-1:0] wr_ptr; - reg [PTR_W:0] count; - - assign in_ready = (count < DEPTH) || (out_ready && out_valid); - assign out_valid = (count != 0); - // Define out_data when empty to keep C++/Verilog equivalence deterministic. - assign out_data = out_valid ? storage[rd_ptr] : {WIDTH{1'b0}}; - - wire do_pop; - wire do_push; - assign do_pop = out_valid && out_ready; - assign do_push = in_valid && in_ready; - - function [PTR_W-1:0] bump_ptr; - input [PTR_W-1:0] p; - begin - if (DEPTH <= 1) - bump_ptr = {PTR_W{1'b0}}; - else if (p == (DEPTH - 1)) - bump_ptr = {PTR_W{1'b0}}; - else - bump_ptr = p + 1'b1; - end - endfunction - - always @(posedge clk) begin - if (rst) begin - rd_ptr <= {PTR_W{1'b0}}; - wr_ptr <= {PTR_W{1'b0}}; - count <= {(PTR_W + 1){1'b0}}; - end else begin - case ({do_push, do_pop}) - 2'b00: begin - // hold - end - 2'b01: begin - rd_ptr <= bump_ptr(rd_ptr); - count <= count - 1'b1; - end - 2'b10: begin - storage[wr_ptr] <= in_data; - wr_ptr <= bump_ptr(wr_ptr); - count <= count + 1'b1; - end - 2'b11: begin - // push + pop in the same cycle - storage[wr_ptr] <= in_data; - rd_ptr <= bump_ptr(rd_ptr); - wr_ptr <= bump_ptr(wr_ptr); - count <= count; - end - endcase - end - end -endmodule +// Ready/valid FIFO with synchronous reset (prototype). +module pyc_fifo #( + parameter WIDTH = 1, + parameter DEPTH = 2 +) ( + input clk, + input rst, + + // Input (producer -> fifo) + input in_valid, + output in_ready, + input [WIDTH-1:0] in_data, + + // Output (fifo -> consumer) + output out_valid, + input out_ready, + output [WIDTH-1:0] out_data +); + `ifndef SYNTHESIS + initial begin + if (DEPTH <= 0) begin + $display("ERROR: pyc_fifo DEPTH must be > 0"); + $finish; + end + end + `endif + + function integer pyc_clog2; + input integer value; + integer i; + begin + pyc_clog2 = 0; + for (i = value - 1; i > 0; i = i >> 1) + pyc_clog2 = pyc_clog2 + 1; + end + endfunction + + localparam PTR_W = (DEPTH <= 1) ? 1 : pyc_clog2(DEPTH); + + reg [WIDTH-1:0] storage [0:DEPTH-1]; + reg [PTR_W-1:0] rd_ptr; + reg [PTR_W-1:0] wr_ptr; + reg [PTR_W:0] count; + + assign in_ready = (count < DEPTH) || (out_ready && out_valid); + assign out_valid = (count != 0); + // Define out_data when empty to keep C++/Verilog equivalence deterministic. + assign out_data = out_valid ? storage[rd_ptr] : {WIDTH{1'b0}}; + + wire do_pop; + wire do_push; + assign do_pop = out_valid && out_ready; + assign do_push = in_valid && in_ready; + + function [PTR_W-1:0] bump_ptr; + input [PTR_W-1:0] p; + begin + if (DEPTH <= 1) + bump_ptr = {PTR_W{1'b0}}; + else if (p == (DEPTH - 1)) + bump_ptr = {PTR_W{1'b0}}; + else + bump_ptr = p + 1'b1; + end + endfunction + + always @(posedge clk) begin + if (rst) begin + rd_ptr <= {PTR_W{1'b0}}; + wr_ptr <= {PTR_W{1'b0}}; + count <= {(PTR_W + 1){1'b0}}; + end else begin + case ({do_push, do_pop}) + 2'b00: begin + // hold + end + 2'b01: begin + rd_ptr <= bump_ptr(rd_ptr); + count <= count - 1'b1; + end + 2'b10: begin + storage[wr_ptr] <= in_data; + wr_ptr <= bump_ptr(wr_ptr); + count <= count + 1'b1; + end + 2'b11: begin + // push + pop in the same cycle + storage[wr_ptr] <= in_data; + rd_ptr <= bump_ptr(rd_ptr); + wr_ptr <= bump_ptr(wr_ptr); + count <= count; + end + endcase + end + end +endmodule // --- pyc_byte_mem.v -// Byte-addressed memory (prototype). -// -// - `DEPTH` is in bytes. -// - Combinational little-endian read window. -// - Byte-enable write on posedge. -module pyc_byte_mem #( - parameter ADDR_WIDTH = 64, - parameter DATA_WIDTH = 64, - parameter DEPTH = 1024, - // Optional init file (Vivado: can be used for BRAM init; simulation: $readmemh). - // If the file cannot be opened, initialization is skipped. - parameter INIT_MEMH = "" -) ( - input clk, - input rst, - - input [ADDR_WIDTH-1:0] raddr, - output reg [DATA_WIDTH-1:0] rdata, - - input wvalid, - input [ADDR_WIDTH-1:0] waddr, - input [DATA_WIDTH-1:0] wdata, - input [(DATA_WIDTH+7)/8-1:0] wstrb -); - localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; - - // Byte storage. - reg [7:0] mem [0:DEPTH-1]; - - // Optional initialization. - integer init_fd; - integer init_i; - initial begin - `ifndef SYNTHESIS - // Deterministic simulation init: keep C++/Verilog equivalence stable. - for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) - mem[init_i] = 8'h00; - `endif - if (INIT_MEMH != "") begin - init_fd = $fopen(INIT_MEMH, "r"); - if (init_fd != 0) begin - $fclose(init_fd); - $readmemh(INIT_MEMH, mem); - end - end - end - - // Combinational read: assemble DATA_WIDTH bits from successive bytes. - integer i; - integer a; - always @* begin - a = raddr[31:0]; - rdata = {DATA_WIDTH{1'b0}}; - for (i = 0; i < STRB_WIDTH; i = i + 1) begin - if ((a + i) < DEPTH) - rdata[8 * i +: 8] = mem[a + i]; - end - end - - // Byte-enable write. - integer j; - integer wa; - always @(posedge clk) begin - if (rst) begin - // Reset does not clear memory (init happens via INIT_MEMH or sim-default 0s). - end else if (wvalid) begin - wa = waddr[31:0]; - for (j = 0; j < STRB_WIDTH; j = j + 1) begin - if (wstrb[j] && ((wa + j) < DEPTH)) - mem[wa + j] <= wdata[8 * j +: 8]; - end - end - end -endmodule +// Byte-addressed memory (prototype). +// +// - `DEPTH` is in bytes. +// - Combinational little-endian read window. +// - Byte-enable write on posedge. +module pyc_byte_mem #( + parameter ADDR_WIDTH = 64, + parameter DATA_WIDTH = 64, + parameter DEPTH = 1024, + // Optional init file (Vivado: can be used for BRAM init; simulation: $readmemh). + // If the file cannot be opened, initialization is skipped. + parameter INIT_MEMH = "" +) ( + input clk, + input rst, + + input [ADDR_WIDTH-1:0] raddr, + output reg [DATA_WIDTH-1:0] rdata, + + input wvalid, + input [ADDR_WIDTH-1:0] waddr, + input [DATA_WIDTH-1:0] wdata, + input [(DATA_WIDTH+7)/8-1:0] wstrb +); + localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; + + // Byte storage. + reg [7:0] mem [0:DEPTH-1]; + + // Optional initialization. + integer init_fd; + integer init_i; + initial begin + `ifndef SYNTHESIS + // Deterministic simulation init: keep C++/Verilog equivalence stable. + for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) + mem[init_i] = 8'h00; + `endif + if (INIT_MEMH != "") begin + init_fd = $fopen(INIT_MEMH, "r"); + if (init_fd != 0) begin + $fclose(init_fd); + $readmemh(INIT_MEMH, mem); + end + end + end + + // Combinational read: assemble DATA_WIDTH bits from successive bytes. + integer i; + integer a; + always @* begin + a = raddr[31:0]; + rdata = {DATA_WIDTH{1'b0}}; + for (i = 0; i < STRB_WIDTH; i = i + 1) begin + if ((a + i) < DEPTH) + rdata[8 * i +: 8] = mem[a + i]; + end + end + + // Byte-enable write. + integer j; + integer wa; + always @(posedge clk) begin + if (rst) begin + // Reset does not clear memory (init happens via INIT_MEMH or sim-default 0s). + end else if (wvalid) begin + wa = waddr[31:0]; + for (j = 0; j < STRB_WIDTH; j = j + 1) begin + if (wstrb[j] && ((wa + j) < DEPTH)) + mem[wa + j] <= wdata[8 * j +: 8]; + end + end + end +endmodule // --- pyc_sync_mem.v -// Synchronous 1R1W memory with registered read data (prototype). -// -// - `DEPTH` is in entries (not bytes). -// - Read is synchronous: when `ren` is asserted, `rdata` updates on the next -// rising edge of `clk`. -// - Write is synchronous with byte enables `wstrb`. -// -// Note: Read-during-write to the same address returns the pre-write data -// ("old-data") by default. -module pyc_sync_mem #( - parameter ADDR_WIDTH = 64, - parameter DATA_WIDTH = 64, - parameter DEPTH = 1024 -) ( - input clk, - input rst, - - input ren, - input [ADDR_WIDTH-1:0] raddr, - output reg [DATA_WIDTH-1:0] rdata, - - input wvalid, - input [ADDR_WIDTH-1:0] waddr, - input [DATA_WIDTH-1:0] wdata, - input [(DATA_WIDTH+7)/8-1:0] wstrb -); - `ifndef SYNTHESIS - initial begin - if (DEPTH <= 0) begin - $display("ERROR: pyc_sync_mem DEPTH must be > 0"); - $finish; - end - end - `endif - - localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; - localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); - // Use a compact address for FPGA-friendly inference. For non-power-of-two - // depths, some addresses in [DEPTH, 2**ADDR_BITS) are unused. - localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); - - // Storage. - `ifdef PYC_TARGET_FPGA - (* ram_style = "block" *) - (* ramstyle = "M20K" *) - reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; - `else - reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; - `endif - - `ifndef SYNTHESIS - // Deterministic simulation init: keep C++/Verilog equivalence stable. - integer init_i; - initial begin - for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) - mem[init_i] = {DATA_WIDTH{1'b0}}; - end - `endif - - integer i; - reg [DATA_WIDTH-1:0] rd_word; - wire [ADDR_BITS-1:0] ra = raddr[ADDR_BITS-1:0]; - wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; - - always @(posedge clk) begin - if (rst) begin - rdata <= {DATA_WIDTH{1'b0}}; - end else begin - // Write with per-lane strobes; last lane may be narrower than 8 bits. - if (wvalid) begin - `ifndef SYNTHESIS - if (wa < DEPTH) begin - for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin - if (wstrb[i]) - mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; - end - if (wstrb[STRB_WIDTH-1]) - mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; - end - `else - for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin - if (wstrb[i]) - mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; - end - if (wstrb[STRB_WIDTH-1]) - mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; - `endif - end - - // Registered read. - if (ren) begin - `ifndef SYNTHESIS - if (ra < DEPTH) begin - rd_word = mem[ra]; - rdata <= rd_word; - end else begin - rdata <= {DATA_WIDTH{1'b0}}; - end - `else - rd_word = mem[ra]; - rdata <= rd_word; - `endif - end - end - end -endmodule +// Synchronous 1R1W memory with registered read data (prototype). +// +// - `DEPTH` is in entries (not bytes). +// - Read is synchronous: when `ren` is asserted, `rdata` updates on the next +// rising edge of `clk`. +// - Write is synchronous with byte enables `wstrb`. +// +// Note: Read-during-write to the same address returns the pre-write data +// ("old-data") by default. +module pyc_sync_mem #( + parameter ADDR_WIDTH = 64, + parameter DATA_WIDTH = 64, + parameter DEPTH = 1024 +) ( + input clk, + input rst, + + input ren, + input [ADDR_WIDTH-1:0] raddr, + output reg [DATA_WIDTH-1:0] rdata, + + input wvalid, + input [ADDR_WIDTH-1:0] waddr, + input [DATA_WIDTH-1:0] wdata, + input [(DATA_WIDTH+7)/8-1:0] wstrb +); + `ifndef SYNTHESIS + initial begin + if (DEPTH <= 0) begin + $display("ERROR: pyc_sync_mem DEPTH must be > 0"); + $finish; + end + end + `endif + + localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; + localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); + // Use a compact address for FPGA-friendly inference. For non-power-of-two + // depths, some addresses in [DEPTH, 2**ADDR_BITS) are unused. + localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); + + // Storage. + `ifdef PYC_TARGET_FPGA + (* ram_style = "block" *) + (* ramstyle = "M20K" *) + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `else + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `endif + + `ifndef SYNTHESIS + // Deterministic simulation init: keep C++/Verilog equivalence stable. + integer init_i; + initial begin + for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) + mem[init_i] = {DATA_WIDTH{1'b0}}; + end + `endif + + integer i; + reg [DATA_WIDTH-1:0] rd_word; + wire [ADDR_BITS-1:0] ra = raddr[ADDR_BITS-1:0]; + wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; + + always @(posedge clk) begin + if (rst) begin + rdata <= {DATA_WIDTH{1'b0}}; + end else begin + // Write with per-lane strobes; last lane may be narrower than 8 bits. + if (wvalid) begin + `ifndef SYNTHESIS + if (wa < DEPTH) begin + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + end + `else + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + `endif + end + + // Registered read. + if (ren) begin + `ifndef SYNTHESIS + if (ra < DEPTH) begin + rd_word = mem[ra]; + rdata <= rd_word; + end else begin + rdata <= {DATA_WIDTH{1'b0}}; + end + `else + rd_word = mem[ra]; + rdata <= rd_word; + `endif + end + end + end +endmodule // --- pyc_sync_mem_dp.v -// Synchronous 2R1W memory with registered read data (prototype). -// -// - `DEPTH` is in entries (not bytes). -// - Both reads are synchronous (registered outputs). -// - One write port with byte enables `wstrb`. -// - Read-during-write to the same address returns pre-write data ("old-data") by default. -module pyc_sync_mem_dp #( - parameter ADDR_WIDTH = 64, - parameter DATA_WIDTH = 64, - parameter DEPTH = 1024 -) ( - input clk, - input rst, - - input ren0, - input [ADDR_WIDTH-1:0] raddr0, - output reg [DATA_WIDTH-1:0] rdata0, - - input ren1, - input [ADDR_WIDTH-1:0] raddr1, - output reg [DATA_WIDTH-1:0] rdata1, - - input wvalid, - input [ADDR_WIDTH-1:0] waddr, - input [DATA_WIDTH-1:0] wdata, - input [(DATA_WIDTH+7)/8-1:0] wstrb -); - `ifndef SYNTHESIS - initial begin - if (DEPTH <= 0) begin - $display("ERROR: pyc_sync_mem_dp DEPTH must be > 0"); - $finish; - end - end - `endif - - localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; - localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); - localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); - - `ifdef PYC_TARGET_FPGA - (* ram_style = "block" *) - (* ramstyle = "M20K" *) - reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; - `else - reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; - `endif - - `ifndef SYNTHESIS - // Deterministic simulation init: keep C++/Verilog equivalence stable. - integer init_i; - initial begin - for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) - mem[init_i] = {DATA_WIDTH{1'b0}}; - end - `endif - - integer i; - reg [DATA_WIDTH-1:0] rd0; - reg [DATA_WIDTH-1:0] rd1; - wire [ADDR_BITS-1:0] ra0 = raddr0[ADDR_BITS-1:0]; - wire [ADDR_BITS-1:0] ra1 = raddr1[ADDR_BITS-1:0]; - wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; - - always @(posedge clk) begin - if (rst) begin - rdata0 <= {DATA_WIDTH{1'b0}}; - rdata1 <= {DATA_WIDTH{1'b0}}; - end else begin - // Write with per-lane strobes; last lane may be narrower than 8 bits. - if (wvalid) begin - `ifndef SYNTHESIS - if (wa < DEPTH) begin - for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin - if (wstrb[i]) - mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; - end - if (wstrb[STRB_WIDTH-1]) - mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; - end - `else - for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin - if (wstrb[i]) - mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; - end - if (wstrb[STRB_WIDTH-1]) - mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; - `endif - end - - // Registered read port 0. - if (ren0) begin - `ifndef SYNTHESIS - if (ra0 < DEPTH) begin - rd0 = mem[ra0]; - rdata0 <= rd0; - end else begin - rdata0 <= {DATA_WIDTH{1'b0}}; - end - `else - rd0 = mem[ra0]; - rdata0 <= rd0; - `endif - end - - // Registered read port 1. - if (ren1) begin - `ifndef SYNTHESIS - if (ra1 < DEPTH) begin - rd1 = mem[ra1]; - rdata1 <= rd1; - end else begin - rdata1 <= {DATA_WIDTH{1'b0}}; - end - `else - rd1 = mem[ra1]; - rdata1 <= rd1; - `endif - end - end - end -endmodule +// Synchronous 2R1W memory with registered read data (prototype). +// +// - `DEPTH` is in entries (not bytes). +// - Both reads are synchronous (registered outputs). +// - One write port with byte enables `wstrb`. +// - Read-during-write to the same address returns pre-write data ("old-data") by default. +module pyc_sync_mem_dp #( + parameter ADDR_WIDTH = 64, + parameter DATA_WIDTH = 64, + parameter DEPTH = 1024 +) ( + input clk, + input rst, + + input ren0, + input [ADDR_WIDTH-1:0] raddr0, + output reg [DATA_WIDTH-1:0] rdata0, + + input ren1, + input [ADDR_WIDTH-1:0] raddr1, + output reg [DATA_WIDTH-1:0] rdata1, + + input wvalid, + input [ADDR_WIDTH-1:0] waddr, + input [DATA_WIDTH-1:0] wdata, + input [(DATA_WIDTH+7)/8-1:0] wstrb +); + `ifndef SYNTHESIS + initial begin + if (DEPTH <= 0) begin + $display("ERROR: pyc_sync_mem_dp DEPTH must be > 0"); + $finish; + end + end + `endif + + localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; + localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); + localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); + + `ifdef PYC_TARGET_FPGA + (* ram_style = "block" *) + (* ramstyle = "M20K" *) + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `else + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `endif + + `ifndef SYNTHESIS + // Deterministic simulation init: keep C++/Verilog equivalence stable. + integer init_i; + initial begin + for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) + mem[init_i] = {DATA_WIDTH{1'b0}}; + end + `endif + + integer i; + reg [DATA_WIDTH-1:0] rd0; + reg [DATA_WIDTH-1:0] rd1; + wire [ADDR_BITS-1:0] ra0 = raddr0[ADDR_BITS-1:0]; + wire [ADDR_BITS-1:0] ra1 = raddr1[ADDR_BITS-1:0]; + wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; + + always @(posedge clk) begin + if (rst) begin + rdata0 <= {DATA_WIDTH{1'b0}}; + rdata1 <= {DATA_WIDTH{1'b0}}; + end else begin + // Write with per-lane strobes; last lane may be narrower than 8 bits. + if (wvalid) begin + `ifndef SYNTHESIS + if (wa < DEPTH) begin + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + end + `else + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + `endif + end + + // Registered read port 0. + if (ren0) begin + `ifndef SYNTHESIS + if (ra0 < DEPTH) begin + rd0 = mem[ra0]; + rdata0 <= rd0; + end else begin + rdata0 <= {DATA_WIDTH{1'b0}}; + end + `else + rd0 = mem[ra0]; + rdata0 <= rd0; + `endif + end + + // Registered read port 1. + if (ren1) begin + `ifndef SYNTHESIS + if (ra1 < DEPTH) begin + rd1 = mem[ra1]; + rdata1 <= rd1; + end else begin + rdata1 <= {DATA_WIDTH{1'b0}}; + end + `else + rd1 = mem[ra1]; + rdata1 <= rd1; + `endif + end + end + end +endmodule // --- pyc_async_fifo.v -// Async ready/valid FIFO with gray-code pointers (prototype). -// -// - Strict ready/valid handshake (no combinational cross-domain paths). -// - `DEPTH` must be a power of two and >= 2. -// - Synchronous resets (per domain). -// -// This is a minimal, synthesizable async FIFO suitable for CDC of data streams. -module pyc_async_fifo #( - parameter WIDTH = 1, - parameter DEPTH = 2 -) ( - // Write domain (producer -> fifo) - input in_clk, - input in_rst, - input in_valid, - output in_ready, - input [WIDTH-1:0] in_data, - - // Read domain (fifo -> consumer) - input out_clk, - input out_rst, - output out_valid, - input out_ready, - output [WIDTH-1:0] out_data -); - `ifndef SYNTHESIS - initial begin - if (DEPTH < 2) begin - $display("ERROR: pyc_async_fifo DEPTH must be >= 2"); - $finish; - end - if ((DEPTH & (DEPTH - 1)) != 0) begin - $display("ERROR: pyc_async_fifo DEPTH must be a power of two"); - $finish; - end - end - `endif - - function integer pyc_clog2; - input integer value; - integer i; - begin - pyc_clog2 = 0; - for (i = value - 1; i > 0; i = i >> 1) - pyc_clog2 = pyc_clog2 + 1; - end - endfunction - - localparam AW = pyc_clog2(DEPTH); - - // Storage. - reg [WIDTH-1:0] mem [0:DEPTH-1]; - - // --- pointer helpers --- - function [AW:0] bin2gray; - input [AW:0] b; - begin - bin2gray = (b >> 1) ^ b; - end - endfunction - - // --- write domain --- - reg [AW:0] wptr_bin; - reg [AW:0] wptr_gray; - wire [AW:0] wptr_bin_next; - wire [AW:0] wptr_gray_next; - reg wfull; - - // Read pointer gray (owned by read domain), referenced for synchronization. - reg [AW:0] rptr_gray; - - reg [AW:0] rptr_gray_w1; - reg [AW:0] rptr_gray_w2; - - wire wfull_next; - wire do_push; - - assign in_ready = ~wfull; - assign do_push = in_valid && in_ready; - assign wptr_bin_next = wptr_bin + (do_push ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); - assign wptr_gray_next = bin2gray(wptr_bin_next); - // Full detection compares next wptr gray against synchronized rptr gray with - // the top 2 bits inverted (classic async FIFO technique). For DEPTH=2, AW=1 - // and there are no "lower" bits to append. - generate - if (AW == 1) begin : gen_wfull_aw1 - assign wfull_next = (wptr_gray_next == ~rptr_gray_w2); - end else begin : gen_wfull_awn - assign wfull_next = (wptr_gray_next == {~rptr_gray_w2[AW:AW-1], rptr_gray_w2[AW-2:0]}); - end - endgenerate - - integer wi; - always @(posedge in_clk) begin - if (in_rst) begin - wptr_bin <= {AW+1{1'b0}}; - wptr_gray <= {AW+1{1'b0}}; - wfull <= 1'b0; - rptr_gray_w1 <= {AW+1{1'b0}}; - rptr_gray_w2 <= {AW+1{1'b0}}; - end else begin - // Sync read pointer into write clock domain. - rptr_gray_w1 <= rptr_gray; - rptr_gray_w2 <= rptr_gray_w1; - - if (do_push) begin - mem[wptr_bin[AW-1:0]] <= in_data; - end - wptr_bin <= wptr_bin_next; - wptr_gray <= wptr_gray_next; - wfull <= wfull_next; - end - end - - reg [AW:0] rptr_bin; - // rptr_gray is declared above (referenced by the write domain sync flops). - wire [AW:0] rptr_bin_next; - wire [AW:0] rptr_gray_next; - - reg [AW:0] wptr_gray_r1; - reg [AW:0] wptr_gray_r2; - - reg out_valid_r; - reg [WIDTH-1:0] out_data_r; - - wire empty_now; - wire empty_next; - wire do_pop; - - assign empty_now = (rptr_gray == wptr_gray_r2); - assign out_valid = out_valid_r; - assign out_data = out_data_r; - - assign do_pop = out_valid_r && out_ready; - assign rptr_bin_next = rptr_bin + (do_pop ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); - assign rptr_gray_next = bin2gray(rptr_bin_next); - assign empty_next = (rptr_gray_next == wptr_gray_r2); - - integer ri; - always @(posedge out_clk) begin - if (out_rst) begin - rptr_bin <= {AW+1{1'b0}}; - rptr_gray <= {AW+1{1'b0}}; - wptr_gray_r1 <= {AW+1{1'b0}}; - wptr_gray_r2 <= {AW+1{1'b0}}; - out_valid_r <= 1'b0; - out_data_r <= {WIDTH{1'b0}}; - end else begin - // Sync write pointer into read clock domain. - wptr_gray_r1 <= wptr_gray; - wptr_gray_r2 <= wptr_gray_r1; - - if (!out_valid_r) begin - // Fill output register when data becomes available. - if (!empty_now) begin - out_valid_r <= 1'b1; - out_data_r <= mem[rptr_bin[AW-1:0]]; - end - end else if (do_pop) begin - // Pop current word; either refill with next word or go empty. - rptr_bin <= rptr_bin_next; - rptr_gray <= rptr_gray_next; - if (empty_next) begin - out_valid_r <= 1'b0; - out_data_r <= {WIDTH{1'b0}}; - end else begin - out_valid_r <= 1'b1; - out_data_r <= mem[rptr_bin_next[AW-1:0]]; - end - end - end - end -endmodule +// Async ready/valid FIFO with gray-code pointers (prototype). +// +// - Strict ready/valid handshake (no combinational cross-domain paths). +// - `DEPTH` must be a power of two and >= 2. +// - Synchronous resets (per domain). +// +// This is a minimal, synthesizable async FIFO suitable for CDC of data streams. +module pyc_async_fifo #( + parameter WIDTH = 1, + parameter DEPTH = 2 +) ( + // Write domain (producer -> fifo) + input in_clk, + input in_rst, + input in_valid, + output in_ready, + input [WIDTH-1:0] in_data, + + // Read domain (fifo -> consumer) + input out_clk, + input out_rst, + output out_valid, + input out_ready, + output [WIDTH-1:0] out_data +); + `ifndef SYNTHESIS + initial begin + if (DEPTH < 2) begin + $display("ERROR: pyc_async_fifo DEPTH must be >= 2"); + $finish; + end + if ((DEPTH & (DEPTH - 1)) != 0) begin + $display("ERROR: pyc_async_fifo DEPTH must be a power of two"); + $finish; + end + end + `endif + + function integer pyc_clog2; + input integer value; + integer i; + begin + pyc_clog2 = 0; + for (i = value - 1; i > 0; i = i >> 1) + pyc_clog2 = pyc_clog2 + 1; + end + endfunction + + localparam AW = pyc_clog2(DEPTH); + + // Storage. + reg [WIDTH-1:0] mem [0:DEPTH-1]; + + // --- pointer helpers --- + function [AW:0] bin2gray; + input [AW:0] b; + begin + bin2gray = (b >> 1) ^ b; + end + endfunction + + // --- write domain --- + reg [AW:0] wptr_bin; + reg [AW:0] wptr_gray; + wire [AW:0] wptr_bin_next; + wire [AW:0] wptr_gray_next; + reg wfull; + + // Read pointer gray (owned by read domain), referenced for synchronization. + reg [AW:0] rptr_gray; + + reg [AW:0] rptr_gray_w1; + reg [AW:0] rptr_gray_w2; + + wire wfull_next; + wire do_push; + + assign in_ready = ~wfull; + assign do_push = in_valid && in_ready; + assign wptr_bin_next = wptr_bin + (do_push ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); + assign wptr_gray_next = bin2gray(wptr_bin_next); + // Full detection compares next wptr gray against synchronized rptr gray with + // the top 2 bits inverted (classic async FIFO technique). For DEPTH=2, AW=1 + // and there are no "lower" bits to append. + generate + if (AW == 1) begin : gen_wfull_aw1 + assign wfull_next = (wptr_gray_next == ~rptr_gray_w2); + end else begin : gen_wfull_awn + assign wfull_next = (wptr_gray_next == {~rptr_gray_w2[AW:AW-1], rptr_gray_w2[AW-2:0]}); + end + endgenerate + + integer wi; + always @(posedge in_clk) begin + if (in_rst) begin + wptr_bin <= {AW+1{1'b0}}; + wptr_gray <= {AW+1{1'b0}}; + wfull <= 1'b0; + rptr_gray_w1 <= {AW+1{1'b0}}; + rptr_gray_w2 <= {AW+1{1'b0}}; + end else begin + // Sync read pointer into write clock domain. + rptr_gray_w1 <= rptr_gray; + rptr_gray_w2 <= rptr_gray_w1; + + if (do_push) begin + mem[wptr_bin[AW-1:0]] <= in_data; + end + wptr_bin <= wptr_bin_next; + wptr_gray <= wptr_gray_next; + wfull <= wfull_next; + end + end + + reg [AW:0] rptr_bin; + // rptr_gray is declared above (referenced by the write domain sync flops). + wire [AW:0] rptr_bin_next; + wire [AW:0] rptr_gray_next; + + reg [AW:0] wptr_gray_r1; + reg [AW:0] wptr_gray_r2; + + reg out_valid_r; + reg [WIDTH-1:0] out_data_r; + + wire empty_now; + wire empty_next; + wire do_pop; + + assign empty_now = (rptr_gray == wptr_gray_r2); + assign out_valid = out_valid_r; + assign out_data = out_data_r; + + assign do_pop = out_valid_r && out_ready; + assign rptr_bin_next = rptr_bin + (do_pop ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); + assign rptr_gray_next = bin2gray(rptr_bin_next); + assign empty_next = (rptr_gray_next == wptr_gray_r2); + + integer ri; + always @(posedge out_clk) begin + if (out_rst) begin + rptr_bin <= {AW+1{1'b0}}; + rptr_gray <= {AW+1{1'b0}}; + wptr_gray_r1 <= {AW+1{1'b0}}; + wptr_gray_r2 <= {AW+1{1'b0}}; + out_valid_r <= 1'b0; + out_data_r <= {WIDTH{1'b0}}; + end else begin + // Sync write pointer into read clock domain. + wptr_gray_r1 <= wptr_gray; + wptr_gray_r2 <= wptr_gray_r1; + + if (!out_valid_r) begin + // Fill output register when data becomes available. + if (!empty_now) begin + out_valid_r <= 1'b1; + out_data_r <= mem[rptr_bin[AW-1:0]]; + end + end else if (do_pop) begin + // Pop current word; either refill with next word or go empty. + rptr_bin <= rptr_bin_next; + rptr_gray <= rptr_gray_next; + if (empty_next) begin + out_valid_r <= 1'b0; + out_data_r <= {WIDTH{1'b0}}; + end else begin + out_valid_r <= 1'b1; + out_data_r <= mem[rptr_bin_next[AW-1:0]]; + end + end + end + end +endmodule // --- pyc_cdc_sync.v -// CDC synchronizer (prototype). -// -// This is a simple multi-stage flop pipeline in the destination clock domain. -// It is suitable for single-bit control signals. For multi-bit buses, prefer a -// proper CDC protocol (async FIFO, handshake, etc). -module pyc_cdc_sync #( - parameter WIDTH = 1, - parameter STAGES = 2 -) ( - input clk, - input rst, - input [WIDTH-1:0] in, - output [WIDTH-1:0] out -); - `ifndef SYNTHESIS - initial begin - if (STAGES < 1) begin - $display("ERROR: pyc_cdc_sync STAGES must be >= 1"); - $finish; - end - end - `endif - - `ifdef PYC_TARGET_FPGA - (* async_reg = "true" *) - reg [WIDTH-1:0] pipe [0:STAGES-1]; - `else - reg [WIDTH-1:0] pipe [0:STAGES-1]; - `endif - - integer i; - always @(posedge clk) begin - if (rst) begin - for (i = 0; i < STAGES; i = i + 1) - pipe[i] <= {WIDTH{1'b0}}; - end else begin - pipe[0] <= in; - for (i = 1; i < STAGES; i = i + 1) - pipe[i] <= pipe[i - 1]; - end - end - - assign out = pipe[STAGES-1]; -endmodule +// CDC synchronizer (prototype). +// +// This is a simple multi-stage flop pipeline in the destination clock domain. +// It is suitable for single-bit control signals. For multi-bit buses, prefer a +// proper CDC protocol (async FIFO, handshake, etc). +module pyc_cdc_sync #( + parameter WIDTH = 1, + parameter STAGES = 2 +) ( + input clk, + input rst, + input [WIDTH-1:0] in, + output [WIDTH-1:0] out +); + `ifndef SYNTHESIS + initial begin + if (STAGES < 1) begin + $display("ERROR: pyc_cdc_sync STAGES must be >= 1"); + $finish; + end + end + `endif + + `ifdef PYC_TARGET_FPGA + (* async_reg = "true" *) + reg [WIDTH-1:0] pipe [0:STAGES-1]; + `else + reg [WIDTH-1:0] pipe [0:STAGES-1]; + `endif + + integer i; + always @(posedge clk) begin + if (rst) begin + for (i = 0; i < STAGES; i = i + 1) + pipe[i] <= {WIDTH{1'b0}}; + end else begin + pipe[0] <= in; + for (i = 1; i < STAGES; i = i + 1) + pipe[i] <= pipe[i - 1]; + end + end + + assign out = pipe[STAGES-1]; +endmodule /* verilator lint_on DECLFILENAME */ diff --git a/designs/PE_INT/rtl/pe_int_l3.v b/designs/PE_INT/rtl/pe_int_l3.v deleted file mode 100644 index 7761bef..0000000 --- a/designs/PE_INT/rtl/pe_int_l3.v +++ /dev/null @@ -1,171 +0,0 @@ -module pe_int_l3 ( - input wire clk, - input wire rst_n, - input wire vld, - input wire [1:0] mode, - input wire [79:0] a, - input wire [79:0] b, - input wire [79:0] b1, - input wire [1:0] e1_a, - input wire [1:0] e1_b0, - input wire [1:0] e1_b1, - output reg signed [18:0] out0, - output reg signed [15:0] out1, - output reg vld_out -); - -localparam MODE_2A = 2'b00; -localparam MODE_2B = 2'b01; -localparam MODE_2C = 2'b10; -localparam MODE_2D = 2'b11; - -reg [1:0] rst_rel; -wire rst_pipe_n; -assign rst_pipe_n = rst_rel[1]; - -reg s0_vld, s1_vld, s2_vld; -reg [1:0] s0_mode, s1_mode, s2_mode; -reg signed [31:0] s0_sum0, s0_sum1; -reg signed [31:0] s1_sum0, s1_sum1; -reg signed [31:0] s2_sum0, s2_sum1; - -integer i; -reg signed [7:0] a_s8, b_s8; -reg signed [3:0] b0_s4, b1_s4; -reg signed [4:0] a_s5, b0_s5, b1_s5; -reg signed [31:0] c_sum0, c_sum1; -reg signed [31:0] lo0, hi0, lo1, hi1; -reg [1:0] sh_lo0, sh_hi0, sh_lo1, sh_hi1; - -always @* begin - c_sum0 = 32'sd0; - c_sum1 = 32'sd0; - lo0 = 32'sd0; - hi0 = 32'sd0; - lo1 = 32'sd0; - hi1 = 32'sd0; - sh_lo0 = e1_a[0] + e1_b0[0]; - sh_hi0 = e1_a[1] + e1_b0[1]; - sh_lo1 = e1_a[0] + e1_b1[0]; - sh_hi1 = e1_a[1] + e1_b1[1]; - - case (mode) - MODE_2A: begin - for (i = 0; i < 8; i = i + 1) begin - a_s8 = $signed({a[5*(2*i+1)+4 -: 4], a[5*(2*i)+4 -: 4]}); - b_s8 = $signed({b[5*(2*i+1)+4 -: 4], b[5*(2*i)+4 -: 4]}); - c_sum0 = c_sum0 + a_s8 * b_s8; - end - end - MODE_2B: begin - for (i = 0; i < 8; i = i + 1) begin - a_s8 = $signed({a[5*(2*i+1)+4 -: 4], a[5*(2*i)+4 -: 4]}); - b0_s4 = $signed(b[5*i+4 -: 4]); - b1_s4 = $signed(b[40 + 5*i + 4 -: 4]); - c_sum0 = c_sum0 + a_s8 * b0_s4; - c_sum1 = c_sum1 + a_s8 * b1_s4; - end - end - MODE_2C: begin - for (i = 0; i < 16; i = i + 1) begin - a_s5 = $signed(a[5*i+4 -: 5]); - b0_s5 = $signed(b[5*i+4 -: 5]); - b1_s5 = $signed(b1[5*i+4 -: 5]); - if (i < 8) begin - lo0 = lo0 + a_s5 * b0_s5; - lo1 = lo1 + a_s5 * b1_s5; - end else begin - hi0 = hi0 + a_s5 * b0_s5; - hi1 = hi1 + a_s5 * b1_s5; - end - end - c_sum0 = (lo0 <<< sh_lo0) + (hi0 <<< sh_hi0); - c_sum1 = (lo1 <<< sh_lo1) + (hi1 <<< sh_hi1); - end - default: begin - for (i = 0; i < 8; i = i + 1) begin - a_s8 = $signed({a[5*(2*i+1)+4 -: 4], a[5*(2*i)+4 -: 4]}); - b0_s5 = $signed(b[5*i+4 -: 5]); - b1_s5 = $signed(b[40 + 5*i + 4 -: 5]); - c_sum0 = c_sum0 + a_s8 * b0_s5; - c_sum1 = c_sum1 + a_s8 * b1_s5; - end - end - endcase -end - -always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - rst_rel <= 2'b00; - end else begin - rst_rel <= {rst_rel[0], 1'b1}; - end -end - -always @(posedge clk or negedge rst_n) begin - if (!rst_n) begin - s0_vld <= 1'b0; - s1_vld <= 1'b0; - s2_vld <= 1'b0; - s0_mode <= MODE_2A; - s1_mode <= MODE_2A; - s2_mode <= MODE_2A; - s0_sum0 <= 32'sd0; - s0_sum1 <= 32'sd0; - s1_sum0 <= 32'sd0; - s1_sum1 <= 32'sd0; - s2_sum0 <= 32'sd0; - s2_sum1 <= 32'sd0; - vld_out <= 1'b0; - out0 <= 19'sd0; - out1 <= 16'sd0; - end else if (!rst_pipe_n) begin - s0_vld <= 1'b0; - s1_vld <= 1'b0; - s2_vld <= 1'b0; - s0_mode <= MODE_2A; - s1_mode <= MODE_2A; - s2_mode <= MODE_2A; - s0_sum0 <= 32'sd0; - s0_sum1 <= 32'sd0; - s1_sum0 <= 32'sd0; - s1_sum1 <= 32'sd0; - s2_sum0 <= 32'sd0; - s2_sum1 <= 32'sd0; - vld_out <= 1'b0; - out0 <= 19'sd0; - out1 <= 16'sd0; - end else begin - vld_out <= s2_vld; - if (s2_vld) begin - out0 <= s2_sum0[18:0]; - out1 <= s2_sum1[15:0]; - end - - s2_vld <= s1_vld; - s2_mode <= s1_mode; - s2_sum0 <= s1_sum0; - s2_sum1 <= s1_sum1; - s1_vld <= s0_vld; - s1_mode <= s0_mode; - s1_sum0 <= s0_sum0; - s1_sum1 <= s0_sum1; - - s0_vld <= vld; - s0_mode <= mode; - if (vld) begin - s0_sum0 <= c_sum0; - if (mode == MODE_2A) begin - // Keep previous secondary-lane value in 2a to preserve out1 hold behavior. - s0_sum1 <= s0_sum1; - end else begin - s0_sum1 <= c_sum1; - end - end else begin - s0_sum0 <= 32'sd0; - s0_sum1 <= s0_sum1; - end - end -end - -endmodule diff --git a/designs/PE_INT/sim/README.md b/designs/PE_INT/sim/README.md index dbb8f5c..947f8dc 100644 --- a/designs/PE_INT/sim/README.md +++ b/designs/PE_INT/sim/README.md @@ -1,49 +1,49 @@ -# sim (One-Command Simulation) - -This directory provides an interactive one-command script: - -- `run_sim.sh` - -## Features - -Before execution, the script prompts for options (5-second timeout per prompt, then default is used): - -1. testcase vector seed (default: current timestamp) -2. simulator: `iverilog` / `verilator` (default: `iverilog`) -3. generate waveform or not (default: `No`) -4. waveform format: `vcd` / `fst` (default: `vcd`) - -The script first resolves and runs the model vector generator from `model/model.f`: - -```bash -python3 --seed -``` - -Then it runs all testcases in `tb_rtl/case` via filelists (`filelist/pe_int.f` + `tb_rtl/tb.f`). - -## Reproducibility - -- The same seed always generates identical `tc_mode_switch_random` vectors and expected values. -- The same seed also generates identical sanity vectors (`tc_mode2a/2b/2c/2d_sanity`); different seeds produce different vectors. -- Both `iverilog` and `verilator` use the same seed generation flow, so seed behavior is consistent across simulators. -- Each testcase has an independent log, and the seed is recorded at the beginning for replay. -- Log path: - - `sim/logs//_run/seed__.log` - -## Run - -```bash -bash sim/run_sim.sh -``` - -## Waveform Output - -- When waveform output is enabled, files are written to: - - `sim/waves///wave.` - -## Simulator Differences (Handled by Script) - -- `iverilog`: runs through `iverilog + vvp`; waveform via `$dumpfile/$dumpvars` (commonly VCD). -- `verilator`: automatically adds: - - `--trace`（VCD） - - `--trace-fst`（FST） +# sim (One-Command Simulation) + +This directory provides an interactive one-command script: + +- `run_sim.sh` + +## Features + +Before execution, the script prompts for options (5-second timeout per prompt, then default is used): + +1. testcase vector seed (default: current timestamp) +2. simulator: `iverilog` / `verilator` (default: `iverilog`) +3. generate waveform or not (default: `No`) +4. waveform format: `vcd` / `fst` (default: `vcd`) + +The script first resolves and runs the model vector generator from `model/model.f`: + +```bash +python3 --seed +``` + +Then it runs all testcases in `tb_rtl/case` via filelists (`filelist/pe_int.f` + `tb_rtl/tb.f`). + +## Reproducibility + +- The same seed always generates identical `tc_mode_switch_random` vectors and expected values. +- The same seed also generates identical sanity vectors (`tc_mode2a/2b/2c/2d_sanity`); different seeds produce different vectors. +- Both `iverilog` and `verilator` use the same seed generation flow, so seed behavior is consistent across simulators. +- Each testcase has an independent log, and the seed is recorded at the beginning for replay. +- Log path: + - `sim/logs//_run/seed__.log` + +## Run + +```bash +bash sim/run_sim.sh +``` + +## Waveform Output + +- When waveform output is enabled, files are written to: + - `sim/waves///wave.` + +## Simulator Differences (Handled by Script) + +- `iverilog`: runs through `iverilog + vvp`; waveform via `$dumpfile/$dumpvars` (commonly VCD). +- `verilator`: automatically adds: + - `--trace`（VCD） + - `--trace-fst`（FST） diff --git a/designs/PE_INT/sim/run_all_wsl.sh b/designs/PE_INT/sim/run_all_wsl.sh index 0244ecd..d2302cd 100644 --- a/designs/PE_INT/sim/run_all_wsl.sh +++ b/designs/PE_INT/sim/run_all_wsl.sh @@ -35,19 +35,64 @@ CASES=( "tc_mode2b_sanity" "tc_mode2c_sanity" "tc_mode2d_sanity" + "tc_mode2a_sanity_rand_timing" + "tc_mode2b_sanity_rand_timing" + "tc_mode2c_sanity_rand_timing" + "tc_mode2d_sanity_rand_timing" "tc_mode_switch_random" ) -echo "[INFO] Running RTL cases with iverilog..." -for c in "${CASES[@]}"; do - iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" - vvp "build/${c}.iv.out" -done - -echo "[INFO] Running RTL cases with verilator..." -for c in "${CASES[@]}"; do - verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" - "./obj_dir/${c}.vlt.out" -done +LOG_DIR="build/logs" +mkdir -p "$LOG_DIR" + +run_parallel_cases() { + local tool="$1" + local failures=0 + local -a pids=() + local -a names=() + + for c in "${CASES[@]}"; do + local log="$LOG_DIR/${tool}_${c}.log" + echo "[INFO] [$tool] launch $c (log: $log)" + if [[ "$tool" == "iverilog" ]]; then + ( + set -euo pipefail + iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" + vvp "build/${c}.iv.out" + ) >"$log" 2>&1 & + else + ( + set -euo pipefail + verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + "./obj_dir/${c}.vlt.out" + ) >"$log" 2>&1 & + fi + pids+=("$!") + names+=("$c") + done + + for idx in "${!pids[@]}"; do + local pid="${pids[$idx]}" + local name="${names[$idx]}" + local log="$LOG_DIR/${tool}_${name}.log" + if wait "$pid"; then + echo "[PASS] [$tool] $name" + else + failures=$((failures + 1)) + echo "[FAIL] [$tool] $name (see $log)" + fi + done + + if (( failures > 0 )); then + echo "[ERR] [$tool] failed cases: $failures" + exit 1 + fi +} + +echo "[INFO] Running RTL cases with iverilog (parallel)..." +run_parallel_cases "iverilog" + +echo "[INFO] Running RTL cases with verilator (parallel)..." +run_parallel_cases "verilator" echo "[PASS] all tb_rtl cases passed on iverilog + verilator." diff --git a/designs/PE_INT/sim/run_sim.sh b/designs/PE_INT/sim/run_sim.sh index 702ff7c..725cfea 100644 --- a/designs/PE_INT/sim/run_sim.sh +++ b/designs/PE_INT/sim/run_sim.sh @@ -14,6 +14,10 @@ CASES=( "tc_mode2b_sanity" "tc_mode2c_sanity" "tc_mode2d_sanity" + "tc_mode2a_sanity_rand_timing" + "tc_mode2b_sanity_rand_timing" + "tc_mode2c_sanity_rand_timing" + "tc_mode2d_sanity_rand_timing" "tc_mode_switch_random" ) @@ -185,6 +189,118 @@ cleanup_pass_logs() { fi } +run_cases_parallel_iverilog() { + local seed="$1" + local log_root="$2" + local failures=0 + local -a pids=() + local -a names=() + + for c in "${CASES[@]}"; do + local case_log="${log_root}/seed_${seed}_${c}.log" + ( + set -euo pipefail + echo "[INFO] simulator=iverilog case=${c} seed=${seed}" + iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" + if [[ "$WAVE_ON" -eq 1 ]]; then + CASE_WAVE_DIR="${WAVE_ROOT}/${c}" + mkdir -p "$CASE_WAVE_DIR" + ( + cd "$CASE_WAVE_DIR" + vvp "${ROOT}/build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 + ) + else + vvp "build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" + fi + ) >"$case_log" 2>&1 & + pids+=("$!") + names+=("$c") + echo "[INFO] launch iverilog case=${c} (log=${case_log})" + done + + for idx in "${!pids[@]}"; do + local pid="${pids[$idx]}" + local case_name="${names[$idx]}" + local case_log="${log_root}/seed_${seed}_${case_name}.log" + if wait "$pid"; then + echo "[PASS] [iverilog] ${case_name}" + else + failures=$((failures + 1)) + echo "[FAIL] [iverilog] ${case_name} (see ${case_log})" + fi + done + + if (( failures > 0 )); then + echo "[ERR] [iverilog] failed cases: ${failures}" + return 1 + fi +} + +run_cases_parallel_verilator() { + local seed="$1" + local log_root="$2" + local failures=0 + local -a pids=() + local -a names=() + + if [[ "$seed_idx" -eq 0 ]]; then + echo "[INFO] build verilator binaries for all cases..." + for c in "${CASES[@]}"; do + if [[ "$WAVE_ON" -eq 1 && "$WAVE_FMT" == "fst" ]]; then + verilator --binary --timing -Wall -Wno-fatal --trace-fst -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + elif [[ "$WAVE_ON" -eq 1 ]]; then + verilator --binary --timing -Wall -Wno-fatal --trace -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + else + verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + fi + done + else + echo "[INFO] reuse existing verilator binaries for all cases" + fi + + for c in "${CASES[@]}"; do + local case_log="${log_root}/seed_${seed}_${c}.log" + ( + set -euo pipefail + echo "[INFO] simulator=verilator case=${c} seed=${seed}" + if [[ "$WAVE_ON" -eq 1 ]]; then + CASE_WAVE_DIR="${WAVE_ROOT}/${c}" + mkdir -p "$CASE_WAVE_DIR" + ( + cd "$CASE_WAVE_DIR" + if [[ "$WAVE_FMT" == "fst" ]]; then + "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=1 + else + "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 + fi + ) + else + "./obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" + fi + ) >"$case_log" 2>&1 & + pids+=("$!") + names+=("$c") + echo "[INFO] launch verilator case=${c} (log=${case_log})" + done + + for idx in "${!pids[@]}"; do + local pid="${pids[$idx]}" + local case_name="${names[$idx]}" + local case_log="${log_root}/seed_${seed}_${case_name}.log" + if wait "$pid"; then + echo "[PASS] [verilator] ${case_name}" + else + failures=$((failures + 1)) + echo "[FAIL] [verilator] ${case_name} (see ${case_log})" + fi + done + + if (( failures > 0 )); then + echo "[ERR] [verilator] failed cases: ${failures}" + return 1 + fi +} + echo echo "[INFO] simulator=$SIM wave=$WAVE_ON format=$WAVE_FMT base_seed=$BASE_SEED seed_runs=$SEED_RUNS" @@ -208,56 +324,9 @@ for ((seed_idx = 0; seed_idx < SEED_RUNS; seed_idx++)); do echo "[INFO] testcase logs are under ${LOG_ROOT}" if [[ "$SIM" == "iverilog" ]]; then - for c in "${CASES[@]}"; do - CASE_LOG="${LOG_ROOT}/seed_${SEED}_${c}.log" - { - echo "[INFO] simulator=iverilog case=${c} seed=${SEED}" - iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" - if [[ "$WAVE_ON" -eq 1 ]]; then - CASE_WAVE_DIR="${WAVE_ROOT}/${c}" - mkdir -p "$CASE_WAVE_DIR" - ( - cd "$CASE_WAVE_DIR" - vvp "${ROOT}/build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 - ) - else - vvp "build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" - fi - } 2>&1 | tee "$CASE_LOG" - done + run_cases_parallel_iverilog "$SEED" "$LOG_ROOT" else - for c in "${CASES[@]}"; do - CASE_LOG="${LOG_ROOT}/seed_${SEED}_${c}.log" - { - echo "[INFO] simulator=verilator case=${c} seed=${SEED}" - if [[ "$seed_idx" -eq 0 ]]; then - if [[ "$WAVE_ON" -eq 1 && "$WAVE_FMT" == "fst" ]]; then - verilator --binary --timing -Wall -Wno-fatal --trace-fst -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" - elif [[ "$WAVE_ON" -eq 1 ]]; then - verilator --binary --timing -Wall -Wno-fatal --trace -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" - else - verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" - fi - else - echo "[INFO] reuse existing verilator binary for ${c}" - fi - - if [[ "$WAVE_ON" -eq 1 ]]; then - CASE_WAVE_DIR="${WAVE_ROOT}/${c}" - mkdir -p "$CASE_WAVE_DIR" - ( - cd "$CASE_WAVE_DIR" - if [[ "$WAVE_FMT" == "fst" ]]; then - "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=1 - else - "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 - fi - ) - else - "./obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" - fi - } 2>&1 | tee "$CASE_LOG" - done + run_cases_parallel_verilator "$SEED" "$LOG_ROOT" fi done diff --git a/designs/PE_INT/tb/README.md b/designs/PE_INT/tb/README.md index 96d3a79..97f2e2b 100644 --- a/designs/PE_INT/tb/README.md +++ b/designs/PE_INT/tb/README.md @@ -1,14 +1,14 @@ -# tb (PyCircuit / Model-Oriented Testbench) - -This directory only contains: - -- PyCircuit testbenches (for example `tb_pe_int_pycircuit.py`) -- PyCircuit-related test flow files - -## Do Not Put Here - -- Model implementation and model regression files (put in `model/`) -- RTL-specific Verilog testbenches -- RTL testcase datasets - -Those artifacts belong in `model/` and `tb_rtl/` respectively. +# tb (PyCircuit / Model-Oriented Testbench) + +This directory only contains: + +- PyCircuit testbenches (for example `tb_pe_int_pycircuit.py`) +- PyCircuit-related test flow files + +## Do Not Put Here + +- Model implementation and model regression files (put in `model/`) +- RTL-specific Verilog testbenches +- RTL testcase datasets + +Those artifacts belong in `model/` and `tb_rtl/` respectively. diff --git a/designs/PE_INT/tb/tb_pe_int_pycircuit.py b/designs/PE_INT/tb/tb_pe_int_pycircuit.py index 5397132..588d12b 100644 --- a/designs/PE_INT/tb/tb_pe_int_pycircuit.py +++ b/designs/PE_INT/tb/tb_pe_int_pycircuit.py @@ -1,5 +1,7 @@ from __future__ import annotations +import random +import os import sys from pathlib import Path @@ -21,80 +23,202 @@ sys.path.insert(0, str(_MODEL_DIR)) from pe_int_pycircuit import build # noqa: E402 -from ref_model import MODE_2A, MODE_2B, compute_transaction, pack_s4x8_to_40, pack_s8x8_to_laneword # noqa: E402 +from pe_int_pycircuit_eval import PEIntL3Model # noqa: E402 +from ref_model import ( # noqa: E402 + MODE_2A, + MODE_2B, + MODE_2C, + MODE_2D, + pack_s4x8_to_40, + pack_s5x8_to_40, + pack_s5x16_to_80, + pack_s8x8_to_laneword, +) -DEFAULT_PARAMS = {"latency": 3} +DEFAULT_PARAMS = {"latency": 4} +VEC_PER_CASE = int(os.environ.get("PE_INT_PYC_TB_VEC_PER_CASE", "8")) +BASE_SEED = 20260420 def _to_u(value: int, bits: int) -> int: return value & ((1 << bits) - 1) -def _mode2b_vector(): - a = [1, -2, 3, -4, 5, -6, 7, -8] - b0 = [1, 2, -3, 4, -5, 6, -7, -8] - b1 = [-1, 2, 3, -4, 5, -6, 7, 0] - a80 = pack_s8x8_to_laneword(a) - b80 = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) - exp = compute_transaction(MODE_2B, a80, b80, 0, (0, 0), (0, 0), (0, 0)) - return a80, b80, exp +def _rand_s_rng(rng: random.Random, width: int) -> int: + lo = -(1 << (width - 1)) + hi = (1 << (width - 1)) - 1 + return rng.randint(lo, hi) + + +def _make_txn_rng(mode: int, rng: random.Random): + if mode == MODE_2A: + a = [_rand_s_rng(rng, 8) for _ in range(8)] + b = [_rand_s_rng(rng, 8) for _ in range(8)] + return ( + pack_s8x8_to_laneword(a), + pack_s8x8_to_laneword(b), + 0, + (0, 0), + (0, 0), + (0, 0), + ) + if mode == MODE_2B: + a = [_rand_s_rng(rng, 8) for _ in range(8)] + b0 = [_rand_s_rng(rng, 4) for _ in range(8)] + b1 = [_rand_s_rng(rng, 4) for _ in range(8)] + b = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) + return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) + if mode == MODE_2D: + a = [_rand_s_rng(rng, 8) for _ in range(8)] + b0 = [_rand_s_rng(rng, 5) for _ in range(8)] + b1 = [_rand_s_rng(rng, 5) for _ in range(8)] + b = pack_s5x8_to_40(b0) | (pack_s5x8_to_40(b1) << 40) + return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) + a = [_rand_s_rng(rng, 5) for _ in range(16)] + b0 = [_rand_s_rng(rng, 5) for _ in range(16)] + b1 = [_rand_s_rng(rng, 5) for _ in range(16)] + e1a = (rng.randint(0, 1), rng.randint(0, 1)) + e1b0 = (rng.randint(0, 1), rng.randint(0, 1)) + e1b1 = (rng.randint(0, 1), rng.randint(0, 1)) + return ( + pack_s5x16_to_80(a), + pack_s5x16_to_80(b0), + pack_s5x16_to_80(b1), + e1a, + e1b0, + e1b1, + ) + + +def _tx(vld: int, mode: int, a: int, b: int, b1: int, e1a, e1b0, e1b1): + return { + "vld": int(vld), + "mode": int(mode) & 0x3, + "a": int(a), + "b": int(b), + "b1": int(b1), + "e1_a": tuple(e1a), + "e1_b0": tuple(e1b0), + "e1_b1": tuple(e1b1), + } + + +def _build_sequences(): + seqs = [] + rng = random.Random(BASE_SEED) + + tx_2a = [] + for _ in range(VEC_PER_CASE): + a_pre, b_pre, _, e1a, e1b0, e1b1 = _make_txn_rng(MODE_2B, rng) + tx_2a.append(_tx(1, MODE_2B, a_pre, b_pre, 0, e1a, e1b0, e1b1)) + a2, b2, b12, e1a2, e1b02, e1b12 = _make_txn_rng(MODE_2A, rng) + tx_2a.append(_tx(1, MODE_2A, a2, b2, b12, e1a2, e1b02, e1b12)) + seqs.append(("mode2a_sanity", tx_2a)) + + for name, mode in [("mode2b_sanity", MODE_2B), ("mode2c_sanity", MODE_2C), ("mode2d_sanity", MODE_2D)]: + txs = [] + for _ in range(VEC_PER_CASE): + a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(mode, rng) + txs.append(_tx(1, mode, a, b, b1, e1a, e1b0, e1b1)) + seqs.append((name, txs)) + + tx_switch = [] + for _ in range(VEC_PER_CASE): + vld = rng.randint(0, 1) + mode = rng.choice([MODE_2A, MODE_2B, MODE_2C, MODE_2D]) + a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(mode, rng) + tx_switch.append(_tx(vld, mode, a, b, b1, e1a, e1b0, e1b1)) + seqs.append(("mode_switch_random", tx_switch)) + + for name, mode in [ + ("mode2a_sanity_rand_timing", MODE_2A), + ("mode2b_sanity_rand_timing", MODE_2B), + ("mode2c_sanity_rand_timing", MODE_2C), + ("mode2d_sanity_rand_timing", MODE_2D), + ]: + rr = random.Random(BASE_SEED + mode * 101) + txs = [] + for _ in range(VEC_PER_CASE): + vld = rr.randint(0, 1) + a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(mode, rr) + txs.append(_tx(vld, mode, a, b, b1, e1a, e1b0, e1b1)) + seqs.append((name, txs)) + + return seqs + + +def _idle_tx(rst_n: int): + return _tx(0, MODE_2A, 0, 0, 0, (0, 0), (0, 0), (0, 0)) | {"rst_n": rst_n} + + +def _run_one_sequence(tb: CycleAwareTb, name: str, txs) -> None: + model = PEIntL3Model() + timeline = [] + + for _ in range(3): + timeline.append(_idle_tx(0)) + for _ in range(3): + timeline.append(_idle_tx(1)) + for item in txs: + timeline.append(item | {"rst_n": 1}) + for _ in range(30): + timeline.append(_idle_tx(1)) + + exp = [] + for item in timeline: + step = model.step( + rst_n=item["rst_n"], + vld=item["vld"], + mode=item["mode"], + a=item["a"], + b=item["b"], + b1=item["b1"], + e1_a=item["e1_a"], + e1_b0=item["e1_b0"], + e1_b1=item["e1_b1"], + ) + exp.append(step) + + first = timeline[0] + tb.drive("rst_n", first["rst_n"]) + tb.drive("vld", first["vld"]) + tb.drive("mode", first["mode"]) + tb.drive("a", _to_u(first["a"], 80)) + tb.drive("b", _to_u(first["b"], 80)) + tb.drive("b1", _to_u(first["b1"], 80)) + tb.drive("e1_a", _to_u(first["e1_a"][0] | (first["e1_a"][1] << 1), 2)) + tb.drive("e1_b0", _to_u(first["e1_b0"][0] | (first["e1_b0"][1] << 1), 2)) + tb.drive("e1_b1", _to_u(first["e1_b1"][0] | (first["e1_b1"][1] << 1), 2)) + + for idx in range(len(timeline)): + tb.next() + tb.expect("vld_out", exp[idx].vld_out) + if exp[idx].vld_out: + tb.expect("out0", _to_u(exp[idx].out0, 19)) + tb.expect("out1", _to_u(exp[idx].out1, 16)) + + if idx + 1 < len(timeline): + nxt = timeline[idx + 1] + tb.drive("rst_n", nxt["rst_n"]) + tb.drive("vld", nxt["vld"]) + tb.drive("mode", nxt["mode"]) + tb.drive("a", _to_u(nxt["a"], 80)) + tb.drive("b", _to_u(nxt["b"], 80)) + tb.drive("b1", _to_u(nxt["b1"], 80)) + tb.drive("e1_a", _to_u(nxt["e1_a"][0] | (nxt["e1_a"][1] << 1), 2)) + tb.drive("e1_b0", _to_u(nxt["e1_b0"][0] | (nxt["e1_b0"][1] << 1), 2)) + tb.drive("e1_b1", _to_u(nxt["e1_b1"][0] | (nxt["e1_b1"][1] << 1), 2)) @testbench def tb(t: Tb) -> None: tb = CycleAwareTb(t) tb.clock("clk") - tb.reset("rst_n", cycles_asserted=2, cycles_deasserted=1) - tb.timeout(200) - - a80, b80, exp2b = _mode2b_vector() - exp2a = compute_transaction( - MODE_2A, - pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), - pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), - 0, - (0, 0), - (0, 0), - (0, 0), - ) + tb.timeout(25000) - tb.drive("vld", 0) - tb.drive("mode", MODE_2A) - tb.drive("a", 0) - tb.drive("b", 0) - tb.drive("b1", 0) - tb.drive("e1_a", 0) - tb.drive("e1_b0", 0) - tb.drive("e1_b1", 0) - tb.expect("vld_out", 0) - - # cycle 0: inject 2b - tb.next() - tb.drive("vld", 1) - tb.drive("mode", MODE_2B) - tb.drive("a", _to_u(a80, 80)) - tb.drive("b", _to_u(b80, 80)) - tb.drive("b1", 0) - - # cycle 1: inject 2a - tb.next() - tb.drive("vld", 1) - tb.drive("mode", MODE_2A) - tb.drive("a", _to_u(pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), 80)) - tb.drive("b", _to_u(pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), 80)) - tb.drive("b1", 0) - - # drain and check outputs on target cycles. - for _ in range(20): - tb.next() - tb.drive("vld", 0) - if tb.cycle == 5: - tb.expect("vld_out", 1) - tb.expect("out0", _to_u(exp2b.out0_19, 19)) - tb.expect("out1", _to_u(exp2b.out1_16, 16)) - if tb.cycle == 6: - tb.expect("vld_out", 1) - tb.expect("out0", _to_u(exp2a.out0_19, 19)) + for name, seq in _build_sequences(): + print(f"[pyc-tb] run {name}, tx_count={len(seq)}") + _run_one_sequence(tb, name, seq) tb.finish() diff --git a/designs/PE_INT/tb/tb_pe_int_pycircuit_2a_wave.py b/designs/PE_INT/tb/tb_pe_int_pycircuit_2a_wave.py new file mode 100644 index 0000000..4e62215 --- /dev/null +++ b/designs/PE_INT/tb/tb_pe_int_pycircuit_2a_wave.py @@ -0,0 +1,87 @@ +from __future__ import annotations + +import os +import sys +from pathlib import Path + +from pycircuit import CycleAwareTb, Tb, testbench + +_THIS_DIR = Path(__file__).resolve().parent +_PY_DIR = _THIS_DIR.parent / "python" +_MODEL_DIR = _THIS_DIR.parent / "model" +if str(_PY_DIR) not in sys.path: + sys.path.insert(0, str(_PY_DIR)) +if str(_MODEL_DIR) not in sys.path: + sys.path.insert(0, str(_MODEL_DIR)) + +from pe_int_pycircuit import build # noqa: E402 +from ref_model import MODE_2A, MODE_2B # noqa: E402 + + +def _read_mem(path: Path) -> list[int]: + return [int(line.strip(), 16) for line in path.read_text(encoding="utf-8").splitlines() if line.strip()] + + +def _to_u(value: int, bits: int) -> int: + return value & ((1 << bits) - 1) + + +def _drive(tb: CycleAwareTb, *, rst_n: int, vld: int, mode: int, a: int, b: int) -> None: + tb.drive("rst_n", rst_n) + tb.drive("vld", vld) + tb.drive("mode", mode) + tb.drive("a", _to_u(a, 80)) + tb.drive("b", _to_u(b, 80)) + tb.drive("b1", 0) + tb.drive("e1_a", 0) + tb.drive("e1_b0", 0) + tb.drive("e1_b1", 0) + + +def _load_2a_sanity_tx() -> list[dict[str, int]]: + repo = _THIS_DIR.parent + gen_dir = Path(os.environ.get("PE_INT_WAVE_GEN_DIR", repo / "tb_rtl" / "case" / "generated")) + tx_count = int(os.environ.get("PE_INT_WAVE_TX_COUNT", "10")) + if tx_count < 1: + raise ValueError("PE_INT_WAVE_TX_COUNT must be >= 1") + + pre_a = _read_mem(gen_dir / "tc_mode2a_sanity_pre_a.mem") + pre_b = _read_mem(gen_dir / "tc_mode2a_sanity_pre_b.mem") + a2a = _read_mem(gen_dir / "tc_mode2a_sanity_a2a.mem") + b2a = _read_mem(gen_dir / "tc_mode2a_sanity_b2a.mem") + + txs: list[dict[str, int]] = [] + for idx in range(len(pre_a)): + txs.append({"vld": 1, "mode": MODE_2B, "a": pre_a[idx], "b": pre_b[idx]}) + txs.append({"vld": 1, "mode": MODE_2A, "a": a2a[idx], "b": b2a[idx]}) + if len(txs) >= tx_count: + return txs[:tx_count] + return txs + + +@testbench +def tb(t: Tb) -> None: + tb = CycleAwareTb(t) + tb.clock("clk") + tb.timeout(200) + + timeline: list[dict[str, int]] = [] + idle = {"vld": 0, "mode": MODE_2A, "a": 0, "b": 0} + for _ in range(3): + timeline.append(idle | {"rst_n": 0}) + for _ in range(3): + timeline.append(idle | {"rst_n": 1}) + for item in _load_2a_sanity_tx(): + timeline.append(item | {"rst_n": 1}) + for _ in range(12): + timeline.append(idle | {"rst_n": 1}) + + first = timeline[0] + _drive(tb, rst_n=first["rst_n"], vld=first["vld"], mode=first["mode"], a=first["a"], b=first["b"]) + for idx in range(len(timeline)): + tb.next() + if idx + 1 < len(timeline): + nxt = timeline[idx + 1] + _drive(tb, rst_n=nxt["rst_n"], vld=nxt["vld"], mode=nxt["mode"], a=nxt["a"], b=nxt["b"]) + + tb.finish() diff --git a/designs/PE_INT/tb_rtl/README.md b/designs/PE_INT/tb_rtl/README.md index 2714328..ffa8a77 100644 --- a/designs/PE_INT/tb_rtl/README.md +++ b/designs/PE_INT/tb_rtl/README.md @@ -1,50 +1,50 @@ -# RTL Test Environment (`tb_rtl`) - -This directory stores files required for **RTL simulation**, separated from `tb/` (PyCircuit testbenches). - -## Directory Layout - -- `case/`: RTL testcases (single-mode sanity + mode-switch random) -- `case/generated/`: testcase vectors and expected data generated by `model/gen_rtl_case_vectors.py` -- `tb.f`: testbench/case filelist (prefixed with absolute `$PE_INT`) -- `sim/run_all_wsl.sh`: batch-run `iverilog` / `verilator` in WSL - -## Quick Run (WSL) - -Run at repo root (e.g. `/mnt/d/git-repo/pycircuit/designs/PE_INT`): - -```bash -bash sim/run_all_wsl.sh -``` - -This script first resolves and runs: - -```bash -python3 -``` - -Then it runs simulator regressions with filelists (`filelist/pe_int.f` + `tb_rtl/tb.f`). - -## Single-Case Run Examples - -### iverilog - -```bash -export PE_INT="$(pwd)" -sed "s|\$PE_INT|${PE_INT}|g" filelist/pe_int.f > build/.pe_int.resolved.f -sed "s|\$PE_INT|${PE_INT}|g" tb_rtl/tb.f > build/.tb.resolved.f -iverilog -g2012 -s tc_mode2b_sanity -f build/.pe_int.resolved.f -f build/.tb.resolved.f -o build/tc_mode2b_sanity.out -vvp build/tc_mode2b_sanity.out -``` - -### verilator - -```bash -export PE_INT="$(pwd)" -sed "s|\$PE_INT|${PE_INT}|g" filelist/pe_int.f > build/.pe_int.resolved.f -sed "s|\$PE_INT|${PE_INT}|g" tb_rtl/tb.f > build/.tb.resolved.f -verilator --binary --timing -Wall -Wno-fatal \ - -f build/.pe_int.resolved.f -f build/.tb.resolved.f \ - --top-module tc_mode2b_sanity -o tc_mode2b_sanity -./obj_dir/tc_mode2b_sanity -``` +# RTL Test Environment (`tb_rtl`) + +This directory stores files required for **RTL simulation**, separated from `tb/` (PyCircuit testbenches). + +## Directory Layout + +- `case/`: RTL testcases (single-mode sanity + mode-switch random) +- `case/generated/`: testcase vectors and expected data generated by `model/gen_rtl_case_vectors.py` +- `tb.f`: testbench/case filelist (prefixed with absolute `$PE_INT`) +- `sim/run_all_wsl.sh`: batch-run `iverilog` / `verilator` in WSL + +## Quick Run (WSL) + +Run at repo root (e.g. `/mnt/d/git-repo/pycircuit/designs/PE_INT`): + +```bash +bash sim/run_all_wsl.sh +``` + +This script first resolves and runs: + +```bash +python3 +``` + +Then it runs simulator regressions with filelists (`filelist/pe_int.f` + `tb_rtl/tb.f`). + +## Single-Case Run Examples + +### iverilog + +```bash +export PE_INT="$(pwd)" +sed "s|\$PE_INT|${PE_INT}|g" filelist/pe_int.f > build/.pe_int.resolved.f +sed "s|\$PE_INT|${PE_INT}|g" tb_rtl/tb.f > build/.tb.resolved.f +iverilog -g2012 -s tc_mode2b_sanity -f build/.pe_int.resolved.f -f build/.tb.resolved.f -o build/tc_mode2b_sanity.out +vvp build/tc_mode2b_sanity.out +``` + +### verilator + +```bash +export PE_INT="$(pwd)" +sed "s|\$PE_INT|${PE_INT}|g" filelist/pe_int.f > build/.pe_int.resolved.f +sed "s|\$PE_INT|${PE_INT}|g" tb_rtl/tb.f > build/.tb.resolved.f +verilator --binary --timing -Wall -Wno-fatal \ + -f build/.pe_int.resolved.f -f build/.tb.resolved.f \ + --top-module tc_mode2b_sanity -o tc_mode2b_sanity +./obj_dir/tc_mode2b_sanity +``` diff --git a/designs/PE_INT/tb_rtl/case/README.md b/designs/PE_INT/tb_rtl/case/README.md index b2fc2ff..44838b1 100644 --- a/designs/PE_INT/tb_rtl/case/README.md +++ b/designs/PE_INT/tb_rtl/case/README.md @@ -1,42 +1,42 @@ -# RTL Testcases (`case`) - -Each `.v` file in this directory is an independent testcase and can be compiled/simulated alone. - -## Case List and Purpose - -- `tc_mode2a_sanity.v` - - Verifies mode 2a (`S8xS8`) math correctness. - - Verifies `out1` is not unnecessarily updated in 2a mode (holds previous dual-path value). - -- `tc_mode2b_sanity.v` - - Verifies mode 2b (`S8xS4`) dual outputs `out0/out1`. - -- `tc_mode2c_sanity.v` - - Verifies mode 2c (`S5xS5 + E1`) dual outputs. - -- `tc_mode2d_sanity.v` - - Verifies mode 2d (`S8xS5`) dual outputs. - -- `tc_mode_switch_random.v` - - Verifies `vld -> vld_out` alignment/order under back-to-back mode switching. - - Verifies output values under mixed traffic (including `vld=0` gaps). - - Expected data must be traceable to reference models in `model/`. - -## Naming Convention - -- `tc_*`: directly usable as simulator top module names. -- Each case includes PASS/FAIL messages and `$fatal` for CI-friendly checks. - -## Automatic Expected Generation - -- Generator: `gen_rtl_case_vectors.py` resolved from `model/model.f` -- Output: `tb_rtl/case/generated/*.vh` -- Testcases use these generated files via `` `include ``; do not handwrite expected values. - -Manual regenerate (resolved through filelist): - -```bash -export PE_INT="$(pwd)" -sed "s|\$PE_INT|${PE_INT}|g" model/model.f > build/.model.resolved.f -python "$(awk '/gen_rtl_case_vectors\.py$/ {print; exit}' build/.model.resolved.f)" -``` +# RTL Testcases (`case`) + +Each `.v` file in this directory is an independent testcase and can be compiled/simulated alone. + +## Case List and Purpose + +- `tc_mode2a_sanity.v` + - Verifies mode 2a (`S8xS8`) math correctness. + - Verifies `out1` is not unnecessarily updated in 2a mode (holds previous dual-path value). + +- `tc_mode2b_sanity.v` + - Verifies mode 2b (`S8xS4`) dual outputs `out0/out1`. + +- `tc_mode2c_sanity.v` + - Verifies mode 2c (`S5xS5 + E1`) dual outputs. + +- `tc_mode2d_sanity.v` + - Verifies mode 2d (`S8xS5`) dual outputs. + +- `tc_mode_switch_random.v` + - Verifies `vld -> vld_out` alignment/order under back-to-back mode switching. + - Verifies output values under mixed traffic (including `vld=0` gaps). + - Expected data must be traceable to reference models in `model/`. + +## Naming Convention + +- `tc_*`: directly usable as simulator top module names. +- Each case includes PASS/FAIL messages and `$fatal` for CI-friendly checks. + +## Automatic Expected Generation + +- Generator: `gen_rtl_case_vectors.py` resolved from `model/model.f` +- Output: `tb_rtl/case/generated/*.vh` +- Testcases use these generated files via `` `include ``; do not handwrite expected values. + +Manual regenerate (resolved through filelist): + +```bash +export PE_INT="$(pwd)" +sed "s|\$PE_INT|${PE_INT}|g" model/model.f > build/.model.resolved.f +python "$(awk '/gen_rtl_case_vectors\.py$/ {print; exit}' build/.model.resolved.f)" +``` diff --git a/designs/PE_INT/tb_rtl/case/common_exact_latency_scoreboard.vh b/designs/PE_INT/tb_rtl/case/common_exact_latency_scoreboard.vh new file mode 100644 index 0000000..3b847fd --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/common_exact_latency_scoreboard.vh @@ -0,0 +1,92 @@ +localparam integer SPEC_LATENCY = 4; +localparam integer SB_LAST = SPEC_LATENCY - 1; + +integer sb_i; +integer exp_rd; +integer checked; +integer accepted; +reg exp_pipe_vld [0:SB_LAST]; +reg [18:0] exp_pipe_o0 [0:SB_LAST]; +reg [15:0] exp_pipe_o1 [0:SB_LAST]; + +task sb_reset; + begin + exp_rd = 0; + checked = 0; + accepted = 0; + for (sb_i = 0; sb_i <= SB_LAST; sb_i = sb_i + 1) begin + exp_pipe_vld[sb_i] = 0; + exp_pipe_o0[sb_i] = 0; + exp_pipe_o1[sb_i] = 0; + end + end +endtask + +task sb_tick; + reg [18:0] next_o0; + reg [15:0] next_o1; + begin + if (exp_pipe_vld[SB_LAST]) begin + if (!vld_out) begin + $display("[ERR][%s] missing vld_out at checked=%0d", CASE_NAME, checked); + err = err + 1; + end else begin + if (out0 !== exp_pipe_o0[SB_LAST] || out1 !== exp_pipe_o1[SB_LAST]) begin + $display("[ERR][%s] idx=%0d got(out0,out1)=(%0d,%0d) exp=(%0d,%0d)", + CASE_NAME, + checked, + $signed(out0), + $signed(out1), + $signed(exp_pipe_o0[SB_LAST]), + $signed(exp_pipe_o1[SB_LAST])); + err = err + 1; + end + end + checked = checked + 1; + end else if (vld_out) begin + $display("[ERR][%s] unexpected vld_out out0=%0d out1=%0d", CASE_NAME, $signed(out0), $signed(out1)); + err = err + 1; + end + + for (sb_i = SB_LAST; sb_i > 0; sb_i = sb_i - 1) begin + exp_pipe_vld[sb_i] = exp_pipe_vld[sb_i - 1]; + exp_pipe_o0[sb_i] = exp_pipe_o0[sb_i - 1]; + exp_pipe_o1[sb_i] = exp_pipe_o1[sb_i - 1]; + end + + if (vld) begin + if (exp_rd >= exp_count) begin + $display("[ERR][%s] input transaction exceeds expected count exp_rd=%0d exp_count=%0d", + CASE_NAME, exp_rd, exp_count); + err = err + 1; + next_o0 = 0; + next_o1 = 0; + end else begin + next_o0 = exp_o0[exp_rd]; + next_o1 = exp_o1[exp_rd]; + end + exp_pipe_vld[0] = 1; + exp_pipe_o0[0] = next_o0; + exp_pipe_o1[0] = next_o1; + exp_rd = exp_rd + 1; + accepted = accepted + 1; + end else begin + exp_pipe_vld[0] = 0; + exp_pipe_o0[0] = 0; + exp_pipe_o1[0] = 0; + end + end +endtask + +task sb_final_check; + begin + if (accepted !== exp_count) begin + $display("[ERR][%s] expected %0d accepted inputs, accepted %0d", CASE_NAME, exp_count, accepted); + err = err + 1; + end + if (checked !== exp_count) begin + $display("[ERR][%s] expected %0d checked outputs, checked %0d", CASE_NAME, exp_count, checked); + err = err + 1; + end + end +endtask diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v index 607ce59..85b92bc 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v @@ -1,119 +1,104 @@ -`timescale 1ns/1ps - -module tc_mode2a_sanity; - reg clk; - reg rst_n; - reg vld; - reg [1:0] mode; - reg [79:0] a; - reg [79:0] b; - reg [79:0] b1; - reg [1:0] e1_a; - reg [1:0] e1_b0; - reg [1:0] e1_b1; - - wire signed [18:0] out0; - wire signed [15:0] out1; - wire vld_out; - - integer got; - integer err; - integer i; - integer vec_idx; - - localparam integer N_CASE_2A = 1000; - localparam integer N_TX_2A = 2000; - localparam integer N_EXP_2A = 2000; - string gen_dir; - reg [79:0] pre_a [0:N_CASE_2A-1]; - reg [79:0] pre_b [0:N_CASE_2A-1]; - reg [79:0] a2a [0:N_CASE_2A-1]; - reg [79:0] b2a [0:N_CASE_2A-1]; - reg [15:0] exp_pre_o1 [0:N_CASE_2A-1]; - reg [18:0] exp_2a_o0 [0:N_CASE_2A-1]; - - localparam [1:0] MODE_2A = 2'b00; - localparam [1:0] MODE_2B = 2'b01; - - pe_int_l3 dut ( - .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), - .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) - ); - - `include "common_wave_dump.vh" - - always #5 clk = ~clk; - - always @(posedge clk) begin - if (rst_n && vld_out) begin - got <= got + 1; - if (got >= N_EXP_2A) begin - $display("[ERR][2a] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); - err <= err + 1; - end else begin - vec_idx = got >> 1; - if ((got & 1) == 0) begin - if (out1 !== exp_pre_o1[vec_idx]) begin - $display("[ERR][2a] idx=%0d preload out1 mismatch got=%0d exp=%0d", - vec_idx, $signed(out1), $signed(exp_pre_o1[vec_idx])); - err <= err + 1; - end - end else begin - if (out0 !== exp_2a_o0[vec_idx]) begin - $display("[ERR][2a] idx=%0d out0 mismatch got=%0d exp=%0d", - vec_idx, $signed(out0), $signed(exp_2a_o0[vec_idx])); - err <= err + 1; - end - if (out1 !== exp_pre_o1[vec_idx]) begin - $display("[ERR][2a] idx=%0d out1 hold mismatch got=%0d exp=%0d", - vec_idx, $signed(out1), $signed(exp_pre_o1[vec_idx])); - err <= err + 1; - end - end - end - end - end - - initial begin - clk = 0; rst_n = 0; vld = 0; mode = 0; - a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; - - if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin - gen_dir = "tb_rtl/case/generated"; - end - $readmemh({gen_dir, "/tc_mode2a_sanity_pre_a.mem"}, pre_a); - $readmemh({gen_dir, "/tc_mode2a_sanity_pre_b.mem"}, pre_b); - $readmemh({gen_dir, "/tc_mode2a_sanity_a2a.mem"}, a2a); - $readmemh({gen_dir, "/tc_mode2a_sanity_b2a.mem"}, b2a); - $readmemh({gen_dir, "/tc_mode2a_sanity_exp_pre_o1.mem"}, exp_pre_o1); - $readmemh({gen_dir, "/tc_mode2a_sanity_exp_2a_o0.mem"}, exp_2a_o0); - - repeat (3) @(posedge clk); - rst_n = 1; - repeat (3) @(posedge clk); - - for (i = 0; i < N_CASE_2A; i = i + 1) begin - @(negedge clk); - vld = 1; mode = MODE_2B; a = pre_a[i]; b = pre_b[i]; b1 = 0; - @(negedge clk); - vld = 1; mode = MODE_2A; a = a2a[i]; b = b2a[i]; b1 = 0; - end - @(negedge clk); - vld = 0; mode = 0; a = 0; b = 0; b1 = 0; - - repeat (12) @(posedge clk); - - if (got !== N_EXP_2A) begin - $display("[ERR][2a] expected %0d outputs, got %0d", N_EXP_2A, got); - err = err + 1; - end - - if (err == 0) begin - $display("[PASS] tc_mode2a_sanity"); - end else begin - $fatal(1, "[FAIL] tc_mode2a_sanity err=%0d", err); - end - $finish; - end -endmodule +`timescale 1ns/1ps + +module tc_mode2a_sanity; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer err; + integer i; + integer exp_count; + integer n_case_2a; + integer n_tx_2a; + localparam integer MAX_CASE_2A = 1000; + localparam integer MAX_TX_2A = 2000; + string gen_dir; + reg [79:0] pre_a [0:MAX_CASE_2A-1]; + reg [79:0] pre_b [0:MAX_CASE_2A-1]; + reg [79:0] a2a [0:MAX_CASE_2A-1]; + reg [79:0] b2a [0:MAX_CASE_2A-1]; + reg [18:0] exp_o0 [0:MAX_TX_2A-1]; + reg [15:0] exp_o1 [0:MAX_TX_2A-1]; + + localparam [1:0] MODE_2A = 2'b00; + localparam [1:0] MODE_2B = 2'b01; + localparam string CASE_NAME = "2a"; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + n_case_2a = MAX_CASE_2A; + if ($value$plusargs("N_CASE_2A=%d", n_case_2a)) begin + if (n_case_2a < 1 || n_case_2a > MAX_CASE_2A) begin + $fatal(1, "[FAIL] invalid N_CASE_2A=%0d, valid range is 1..%0d", n_case_2a, MAX_CASE_2A); + end + end + n_tx_2a = n_case_2a * 2; + err = 0; exp_count = n_tx_2a; sb_reset(); + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2a_sanity_pre_a.mem"}, pre_a); + $readmemh({gen_dir, "/tc_mode2a_sanity_pre_b.mem"}, pre_b); + $readmemh({gen_dir, "/tc_mode2a_sanity_a2a.mem"}, a2a); + $readmemh({gen_dir, "/tc_mode2a_sanity_b2a.mem"}, b2a); + $readmemh({gen_dir, "/tc_mode2a_sanity_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2a_sanity_exp_o1.mem"}, exp_o1); + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < n_case_2a; i = i + 1) begin + @(negedge clk); + vld = 1; mode = MODE_2B; a = pre_a[i]; b = pre_b[i]; b1 = 0; + e1_a = 0; e1_b0 = 0; e1_b1 = 0; + @(negedge clk); + vld = 1; mode = MODE_2A; a = a2a[i]; b = b2a[i]; b1 = 0; + e1_a = 0; e1_b0 = 0; e1_b1 = 0; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (12) @(posedge clk); + sb_final_check(); + + if (err == 0) begin + $display("[PASS] tc_mode2a_sanity"); + end else begin + $fatal(1, "[FAIL] tc_mode2a_sanity err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v new file mode 100644 index 0000000..1706e65 --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v @@ -0,0 +1,108 @@ +`timescale 1ns/1ps + +module tc_mode2a_sanity_rand_timing; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer i; + integer got; + integer err; + integer exp_count; + localparam integer N_TX = 1000; + localparam integer N_EXP_MAX = 1000; + string gen_dir; + reg [31:0] meta [0:0]; + + reg tx_vld [0:N_TX-1]; + reg [79:0] tx_a [0:N_TX-1]; + reg [79:0] tx_b [0:N_TX-1]; + reg [79:0] tx_b1 [0:N_TX-1]; + reg [1:0] tx_e1a [0:N_TX-1]; + reg [1:0] tx_e1b0 [0:N_TX-1]; + reg [1:0] tx_e1b1 [0:N_TX-1]; + reg [18:0] exp_o0 [0:N_EXP_MAX-1]; + reg [15:0] exp_o1 [0:N_EXP_MAX-1]; + + localparam [1:0] MODE_FIXED = 2'b00; + localparam string CASE_NAME = "2a_rand"; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; exp_count = 0; sb_reset(); + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_tx_vld.mem"}, tx_vld); + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_tx_b1.mem"}, tx_b1); + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_tx_e1a.mem"}, tx_e1a); + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_tx_e1b0.mem"}, tx_e1b0); + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_tx_e1b1.mem"}, tx_e1b1); + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_exp_o1.mem"}, exp_o1); + $readmemh({gen_dir, "/tc_mode2a_sanity_rand_timing_meta.mem"}, meta); + exp_count = meta[0]; + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX; i = i + 1) begin + @(negedge clk); + vld = tx_vld[i]; + mode = MODE_FIXED; + a = tx_a[i]; + b = tx_b[i]; + b1 = tx_b1[i]; + e1_a = tx_e1a[i]; + e1_b0 = tx_e1b0[i]; + e1_b1 = tx_e1b1[i]; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (30) @(posedge clk); + sb_final_check(); + + if (err == 0) begin + $display("[PASS] tc_mode2a_sanity_rand_timing"); + end else begin + $fatal(1, "[FAIL] tc_mode2a_sanity_rand_timing err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v index f9708fc..c8008e0 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v @@ -1,95 +1,86 @@ -`timescale 1ns/1ps - -module tc_mode2b_sanity; - reg clk; - reg rst_n; - reg vld; - reg [1:0] mode; - reg [79:0] a; - reg [79:0] b; - reg [79:0] b1; - reg [1:0] e1_a; - reg [1:0] e1_b0; - reg [1:0] e1_b1; - - wire signed [18:0] out0; - wire signed [15:0] out1; - wire vld_out; - - integer got; - integer err; - integer i; - - localparam integer N_TX_2B = 1000; - localparam integer N_EXP_2B = 1000; - string gen_dir; - reg [79:0] tx_a [0:N_TX_2B-1]; - reg [79:0] tx_b [0:N_TX_2B-1]; - reg [18:0] exp_o0 [0:N_EXP_2B-1]; - reg [15:0] exp_o1 [0:N_EXP_2B-1]; - - localparam [1:0] MODE_2B = 2'b01; - - pe_int_l3 dut ( - .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), - .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) - ); - - `include "common_wave_dump.vh" - - always #5 clk = ~clk; - - always @(posedge clk) begin - if (rst_n && vld_out) begin - got <= got + 1; - if (got >= N_EXP_2B) begin - $display("[ERR][2b] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); - err <= err + 1; - end else if (out0 !== exp_o0[got] || out1 !== exp_o1[got]) begin - $display("[ERR][2b] idx=%0d out0=%0d out1=%0d exp=(%0d,%0d)", - got, $signed(out0), $signed(out1), $signed(exp_o0[got]), $signed(exp_o1[got])); - err <= err + 1; - end - end - end - - initial begin - clk = 0; rst_n = 0; vld = 0; mode = 0; - a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; - - if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin - gen_dir = "tb_rtl/case/generated"; - end - $readmemh({gen_dir, "/tc_mode2b_sanity_tx_a.mem"}, tx_a); - $readmemh({gen_dir, "/tc_mode2b_sanity_tx_b.mem"}, tx_b); - $readmemh({gen_dir, "/tc_mode2b_sanity_exp_o0.mem"}, exp_o0); - $readmemh({gen_dir, "/tc_mode2b_sanity_exp_o1.mem"}, exp_o1); - - repeat (3) @(posedge clk); - rst_n = 1; - repeat (3) @(posedge clk); - - for (i = 0; i < N_TX_2B; i = i + 1) begin - @(negedge clk); - vld = 1; mode = MODE_2B; a = tx_a[i]; b = tx_b[i]; b1 = 0; - end - - @(negedge clk); - vld = 0; mode = 0; a = 0; b = 0; b1 = 0; - - repeat (10) @(posedge clk); - - if (got !== N_EXP_2B) begin - $display("[ERR][2b] expected %0d outputs, got %0d", N_EXP_2B, got); - err = err + 1; - end - - if (err == 0) begin - $display("[PASS] tc_mode2b_sanity"); - end else begin - $fatal(1, "[FAIL] tc_mode2b_sanity err=%0d", err); - end - $finish; - end -endmodule +`timescale 1ns/1ps + +module tc_mode2b_sanity; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer err; + integer i; + integer exp_count; + localparam integer N_TX_2B = 1000; + string gen_dir; + reg [79:0] tx_a [0:N_TX_2B-1]; + reg [79:0] tx_b [0:N_TX_2B-1]; + reg [18:0] exp_o0 [0:N_TX_2B-1]; + reg [15:0] exp_o1 [0:N_TX_2B-1]; + + localparam [1:0] MODE_2B = 2'b01; + localparam string CASE_NAME = "2b"; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + err = 0; exp_count = N_TX_2B; sb_reset(); + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2b_sanity_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2b_sanity_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode2b_sanity_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2b_sanity_exp_o1.mem"}, exp_o1); + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX_2B; i = i + 1) begin + @(negedge clk); + vld = 1; mode = MODE_2B; a = tx_a[i]; b = tx_b[i]; b1 = 0; + e1_a = 0; e1_b0 = 0; e1_b1 = 0; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (12) @(posedge clk); + sb_final_check(); + + if (err == 0) begin + $display("[PASS] tc_mode2b_sanity"); + end else begin + $fatal(1, "[FAIL] tc_mode2b_sanity err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v new file mode 100644 index 0000000..72f2263 --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v @@ -0,0 +1,108 @@ +`timescale 1ns/1ps + +module tc_mode2b_sanity_rand_timing; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer i; + integer got; + integer err; + integer exp_count; + localparam integer N_TX = 1000; + localparam integer N_EXP_MAX = 1000; + string gen_dir; + reg [31:0] meta [0:0]; + + reg tx_vld [0:N_TX-1]; + reg [79:0] tx_a [0:N_TX-1]; + reg [79:0] tx_b [0:N_TX-1]; + reg [79:0] tx_b1 [0:N_TX-1]; + reg [1:0] tx_e1a [0:N_TX-1]; + reg [1:0] tx_e1b0 [0:N_TX-1]; + reg [1:0] tx_e1b1 [0:N_TX-1]; + reg [18:0] exp_o0 [0:N_EXP_MAX-1]; + reg [15:0] exp_o1 [0:N_EXP_MAX-1]; + + localparam [1:0] MODE_FIXED = 2'b01; + localparam string CASE_NAME = "2b_rand"; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; exp_count = 0; sb_reset(); + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_tx_vld.mem"}, tx_vld); + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_tx_b1.mem"}, tx_b1); + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_tx_e1a.mem"}, tx_e1a); + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_tx_e1b0.mem"}, tx_e1b0); + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_tx_e1b1.mem"}, tx_e1b1); + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_exp_o1.mem"}, exp_o1); + $readmemh({gen_dir, "/tc_mode2b_sanity_rand_timing_meta.mem"}, meta); + exp_count = meta[0]; + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX; i = i + 1) begin + @(negedge clk); + vld = tx_vld[i]; + mode = MODE_FIXED; + a = tx_a[i]; + b = tx_b[i]; + b1 = tx_b1[i]; + e1_a = tx_e1a[i]; + e1_b0 = tx_e1b0[i]; + e1_b1 = tx_e1b1[i]; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (30) @(posedge clk); + sb_final_check(); + + if (err == 0) begin + $display("[PASS] tc_mode2b_sanity_rand_timing"); + end else begin + $fatal(1, "[FAIL] tc_mode2b_sanity_rand_timing err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v index 961dfdd..0d6afa5 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v @@ -1,104 +1,94 @@ -`timescale 1ns/1ps - -module tc_mode2c_sanity; - reg clk; - reg rst_n; - reg vld; - reg [1:0] mode; - reg [79:0] a; - reg [79:0] b; - reg [79:0] b1; - reg [1:0] e1_a; - reg [1:0] e1_b0; - reg [1:0] e1_b1; - - wire signed [18:0] out0; - wire signed [15:0] out1; - wire vld_out; - - integer got; - integer err; - integer i; - - localparam integer N_TX_2C = 1000; - localparam integer N_EXP_2C = 1000; - string gen_dir; - reg [79:0] tx_a [0:N_TX_2C-1]; - reg [79:0] tx_b0 [0:N_TX_2C-1]; - reg [79:0] tx_b1 [0:N_TX_2C-1]; - reg [1:0] tx_e1a [0:N_TX_2C-1]; - reg [1:0] tx_e1b0 [0:N_TX_2C-1]; - reg [1:0] tx_e1b1 [0:N_TX_2C-1]; - reg [18:0] exp_o0 [0:N_EXP_2C-1]; - reg [15:0] exp_o1 [0:N_EXP_2C-1]; - - localparam [1:0] MODE_2C = 2'b10; - - pe_int_l3 dut ( - .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), - .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) - ); - - `include "common_wave_dump.vh" - - always #5 clk = ~clk; - - always @(posedge clk) begin - if (rst_n && vld_out) begin - got <= got + 1; - if (got >= N_EXP_2C) begin - $display("[ERR][2c] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); - err <= err + 1; - end else if (out0 !== exp_o0[got] || out1 !== exp_o1[got]) begin - $display("[ERR][2c] idx=%0d out0=%0d out1=%0d exp=(%0d,%0d)", - got, $signed(out0), $signed(out1), $signed(exp_o0[got]), $signed(exp_o1[got])); - err <= err + 1; - end - end - end - - initial begin - clk = 0; rst_n = 0; vld = 0; mode = 0; - a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; - - if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin - gen_dir = "tb_rtl/case/generated"; - end - $readmemh({gen_dir, "/tc_mode2c_sanity_tx_a.mem"}, tx_a); - $readmemh({gen_dir, "/tc_mode2c_sanity_tx_b0.mem"}, tx_b0); - $readmemh({gen_dir, "/tc_mode2c_sanity_tx_b1.mem"}, tx_b1); - $readmemh({gen_dir, "/tc_mode2c_sanity_tx_e1a.mem"}, tx_e1a); - $readmemh({gen_dir, "/tc_mode2c_sanity_tx_e1b0.mem"}, tx_e1b0); - $readmemh({gen_dir, "/tc_mode2c_sanity_tx_e1b1.mem"}, tx_e1b1); - $readmemh({gen_dir, "/tc_mode2c_sanity_exp_o0.mem"}, exp_o0); - $readmemh({gen_dir, "/tc_mode2c_sanity_exp_o1.mem"}, exp_o1); - - repeat (3) @(posedge clk); - rst_n = 1; - repeat (3) @(posedge clk); - - for (i = 0; i < N_TX_2C; i = i + 1) begin - @(negedge clk); - vld = 1; mode = MODE_2C; a = tx_a[i]; b = tx_b0[i]; b1 = tx_b1[i]; - e1_a = tx_e1a[i]; e1_b0 = tx_e1b0[i]; e1_b1 = tx_e1b1[i]; - end - - @(negedge clk); - vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - - repeat (10) @(posedge clk); - - if (got !== N_EXP_2C) begin - $display("[ERR][2c] expected %0d outputs, got %0d", N_EXP_2C, got); - err = err + 1; - end - - if (err == 0) begin - $display("[PASS] tc_mode2c_sanity"); - end else begin - $fatal(1, "[FAIL] tc_mode2c_sanity err=%0d", err); - end - $finish; - end -endmodule +`timescale 1ns/1ps + +module tc_mode2c_sanity; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer err; + integer i; + integer exp_count; + localparam integer N_TX_2C = 1000; + string gen_dir; + reg [79:0] tx_a [0:N_TX_2C-1]; + reg [79:0] tx_b0 [0:N_TX_2C-1]; + reg [79:0] tx_b1 [0:N_TX_2C-1]; + reg [1:0] tx_e1a [0:N_TX_2C-1]; + reg [1:0] tx_e1b0 [0:N_TX_2C-1]; + reg [1:0] tx_e1b1 [0:N_TX_2C-1]; + reg [18:0] exp_o0 [0:N_TX_2C-1]; + reg [15:0] exp_o1 [0:N_TX_2C-1]; + + localparam [1:0] MODE_2C = 2'b10; + localparam string CASE_NAME = "2c"; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + err = 0; exp_count = N_TX_2C; sb_reset(); + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_b0.mem"}, tx_b0); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_b1.mem"}, tx_b1); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_e1a.mem"}, tx_e1a); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_e1b0.mem"}, tx_e1b0); + $readmemh({gen_dir, "/tc_mode2c_sanity_tx_e1b1.mem"}, tx_e1b1); + $readmemh({gen_dir, "/tc_mode2c_sanity_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2c_sanity_exp_o1.mem"}, exp_o1); + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX_2C; i = i + 1) begin + @(negedge clk); + vld = 1; mode = MODE_2C; a = tx_a[i]; b = tx_b0[i]; b1 = tx_b1[i]; + e1_a = tx_e1a[i]; e1_b0 = tx_e1b0[i]; e1_b1 = tx_e1b1[i]; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (12) @(posedge clk); + sb_final_check(); + + if (err == 0) begin + $display("[PASS] tc_mode2c_sanity"); + end else begin + $fatal(1, "[FAIL] tc_mode2c_sanity err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v new file mode 100644 index 0000000..8d62aae --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v @@ -0,0 +1,108 @@ +`timescale 1ns/1ps + +module tc_mode2c_sanity_rand_timing; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer i; + integer got; + integer err; + integer exp_count; + localparam integer N_TX = 1000; + localparam integer N_EXP_MAX = 1000; + string gen_dir; + reg [31:0] meta [0:0]; + + reg tx_vld [0:N_TX-1]; + reg [79:0] tx_a [0:N_TX-1]; + reg [79:0] tx_b [0:N_TX-1]; + reg [79:0] tx_b1 [0:N_TX-1]; + reg [1:0] tx_e1a [0:N_TX-1]; + reg [1:0] tx_e1b0 [0:N_TX-1]; + reg [1:0] tx_e1b1 [0:N_TX-1]; + reg [18:0] exp_o0 [0:N_EXP_MAX-1]; + reg [15:0] exp_o1 [0:N_EXP_MAX-1]; + + localparam [1:0] MODE_FIXED = 2'b10; + localparam string CASE_NAME = "2c_rand"; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; exp_count = 0; sb_reset(); + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_tx_vld.mem"}, tx_vld); + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_tx_b1.mem"}, tx_b1); + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_tx_e1a.mem"}, tx_e1a); + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_tx_e1b0.mem"}, tx_e1b0); + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_tx_e1b1.mem"}, tx_e1b1); + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_exp_o1.mem"}, exp_o1); + $readmemh({gen_dir, "/tc_mode2c_sanity_rand_timing_meta.mem"}, meta); + exp_count = meta[0]; + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX; i = i + 1) begin + @(negedge clk); + vld = tx_vld[i]; + mode = MODE_FIXED; + a = tx_a[i]; + b = tx_b[i]; + b1 = tx_b1[i]; + e1_a = tx_e1a[i]; + e1_b0 = tx_e1b0[i]; + e1_b1 = tx_e1b1[i]; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (30) @(posedge clk); + sb_final_check(); + + if (err == 0) begin + $display("[PASS] tc_mode2c_sanity_rand_timing"); + end else begin + $fatal(1, "[FAIL] tc_mode2c_sanity_rand_timing err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v index f49eb52..faa7f4f 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v @@ -1,95 +1,86 @@ -`timescale 1ns/1ps - -module tc_mode2d_sanity; - reg clk; - reg rst_n; - reg vld; - reg [1:0] mode; - reg [79:0] a; - reg [79:0] b; - reg [79:0] b1; - reg [1:0] e1_a; - reg [1:0] e1_b0; - reg [1:0] e1_b1; - - wire signed [18:0] out0; - wire signed [15:0] out1; - wire vld_out; - - integer got; - integer err; - integer i; - - localparam integer N_TX_2D = 1000; - localparam integer N_EXP_2D = 1000; - string gen_dir; - reg [79:0] tx_a [0:N_TX_2D-1]; - reg [79:0] tx_b [0:N_TX_2D-1]; - reg [18:0] exp_o0 [0:N_EXP_2D-1]; - reg [15:0] exp_o1 [0:N_EXP_2D-1]; - - localparam [1:0] MODE_2D = 2'b11; - - pe_int_l3 dut ( - .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), - .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) - ); - - `include "common_wave_dump.vh" - - always #5 clk = ~clk; - - always @(posedge clk) begin - if (rst_n && vld_out) begin - got <= got + 1; - if (got >= N_EXP_2D) begin - $display("[ERR][2d] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); - err <= err + 1; - end else if (out0 !== exp_o0[got] || out1 !== exp_o1[got]) begin - $display("[ERR][2d] idx=%0d out0=%0d out1=%0d exp=(%0d,%0d)", - got, $signed(out0), $signed(out1), $signed(exp_o0[got]), $signed(exp_o1[got])); - err <= err + 1; - end - end - end - - initial begin - clk = 0; rst_n = 0; vld = 0; mode = 0; - a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; - - if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin - gen_dir = "tb_rtl/case/generated"; - end - $readmemh({gen_dir, "/tc_mode2d_sanity_tx_a.mem"}, tx_a); - $readmemh({gen_dir, "/tc_mode2d_sanity_tx_b.mem"}, tx_b); - $readmemh({gen_dir, "/tc_mode2d_sanity_exp_o0.mem"}, exp_o0); - $readmemh({gen_dir, "/tc_mode2d_sanity_exp_o1.mem"}, exp_o1); - - repeat (3) @(posedge clk); - rst_n = 1; - repeat (3) @(posedge clk); - - for (i = 0; i < N_TX_2D; i = i + 1) begin - @(negedge clk); - vld = 1; mode = MODE_2D; a = tx_a[i]; b = tx_b[i]; b1 = 0; - end - - @(negedge clk); - vld = 0; mode = 0; a = 0; b = 0; b1 = 0; - - repeat (10) @(posedge clk); - - if (got !== N_EXP_2D) begin - $display("[ERR][2d] expected %0d outputs, got %0d", N_EXP_2D, got); - err = err + 1; - end - - if (err == 0) begin - $display("[PASS] tc_mode2d_sanity"); - end else begin - $fatal(1, "[FAIL] tc_mode2d_sanity err=%0d", err); - end - $finish; - end -endmodule +`timescale 1ns/1ps + +module tc_mode2d_sanity; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer err; + integer i; + integer exp_count; + localparam integer N_TX_2D = 1000; + string gen_dir; + reg [79:0] tx_a [0:N_TX_2D-1]; + reg [79:0] tx_b [0:N_TX_2D-1]; + reg [18:0] exp_o0 [0:N_TX_2D-1]; + reg [15:0] exp_o1 [0:N_TX_2D-1]; + + localparam [1:0] MODE_2D = 2'b11; + localparam string CASE_NAME = "2d"; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + err = 0; exp_count = N_TX_2D; sb_reset(); + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2d_sanity_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2d_sanity_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode2d_sanity_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2d_sanity_exp_o1.mem"}, exp_o1); + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX_2D; i = i + 1) begin + @(negedge clk); + vld = 1; mode = MODE_2D; a = tx_a[i]; b = tx_b[i]; b1 = 0; + e1_a = 0; e1_b0 = 0; e1_b1 = 0; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (12) @(posedge clk); + sb_final_check(); + + if (err == 0) begin + $display("[PASS] tc_mode2d_sanity"); + end else begin + $fatal(1, "[FAIL] tc_mode2d_sanity err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v new file mode 100644 index 0000000..a7ac1f0 --- /dev/null +++ b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v @@ -0,0 +1,108 @@ +`timescale 1ns/1ps + +module tc_mode2d_sanity_rand_timing; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer i; + integer got; + integer err; + integer exp_count; + localparam integer N_TX = 1000; + localparam integer N_EXP_MAX = 1000; + string gen_dir; + reg [31:0] meta [0:0]; + + reg tx_vld [0:N_TX-1]; + reg [79:0] tx_a [0:N_TX-1]; + reg [79:0] tx_b [0:N_TX-1]; + reg [79:0] tx_b1 [0:N_TX-1]; + reg [1:0] tx_e1a [0:N_TX-1]; + reg [1:0] tx_e1b0 [0:N_TX-1]; + reg [1:0] tx_e1b1 [0:N_TX-1]; + reg [18:0] exp_o0 [0:N_EXP_MAX-1]; + reg [15:0] exp_o1 [0:N_EXP_MAX-1]; + + localparam [1:0] MODE_FIXED = 2'b11; + localparam string CASE_NAME = "2d_rand"; + + pe_int_l3 dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; exp_count = 0; sb_reset(); + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_tx_vld.mem"}, tx_vld); + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_tx_b1.mem"}, tx_b1); + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_tx_e1a.mem"}, tx_e1a); + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_tx_e1b0.mem"}, tx_e1b0); + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_tx_e1b1.mem"}, tx_e1b1); + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_exp_o1.mem"}, exp_o1); + $readmemh({gen_dir, "/tc_mode2d_sanity_rand_timing_meta.mem"}, meta); + exp_count = meta[0]; + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX; i = i + 1) begin + @(negedge clk); + vld = tx_vld[i]; + mode = MODE_FIXED; + a = tx_a[i]; + b = tx_b[i]; + b1 = tx_b1[i]; + e1_a = tx_e1a[i]; + e1_b0 = tx_e1b0[i]; + e1_b1 = tx_e1b1[i]; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (30) @(posedge clk); + sb_final_check(); + + if (err == 0) begin + $display("[PASS] tc_mode2d_sanity_rand_timing"); + end else begin + $fatal(1, "[FAIL] tc_mode2d_sanity_rand_timing err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v b/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v index 6b26ad1..0fe3e66 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v @@ -36,6 +36,7 @@ module tc_mode_switch_random; reg [18:0] exp_o0 [0:N_EXP_MAX-1]; reg [15:0] exp_o1 [0:N_EXP_MAX-1]; + localparam string CASE_NAME = "rand"; pe_int_l3 dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), @@ -43,22 +44,15 @@ module tc_mode_switch_random; ); `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" always #5 clk = ~clk; always @(posedge clk) begin - if (rst_n && vld_out) begin - if (got >= exp_count) begin - $display("[ERR][rand] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); - err <= err + 1; - end else begin - if (out0 !== exp_o0[got] || out1 !== exp_o1[got]) begin - $display("[ERR][rand] idx=%0d got(out0,out1)=(%0d,%0d) exp=(%0d,%0d)", - got, $signed(out0), $signed(out1), $signed(exp_o0[got]), $signed(exp_o1[got])); - err <= err + 1; - end - end - got <= got + 1; + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); end end @@ -66,7 +60,7 @@ module tc_mode_switch_random; clk = 0; rst_n = 0; vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; got = 0; err = 0; - exp_count = 0; + exp_count = 0; sb_reset(); if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin gen_dir = "tb_rtl/case/generated"; @@ -104,11 +98,7 @@ module tc_mode_switch_random; vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; repeat (30) @(posedge clk); - - if (got !== exp_count) begin - $display("[ERR][rand] expected %0d outputs, got %0d", exp_count, got); - err = err + 1; - end + sb_final_check(); if (err == 0) begin $display("[PASS] tc_mode_switch_random"); diff --git a/designs/PE_INT/tb_rtl/tb.f b/designs/PE_INT/tb_rtl/tb.f index 7311afc..cb33bfe 100644 --- a/designs/PE_INT/tb_rtl/tb.f +++ b/designs/PE_INT/tb_rtl/tb.f @@ -3,4 +3,8 @@ $PE_INT/tb_rtl/case/tc_mode2b_sanity.v $PE_INT/tb_rtl/case/tc_mode2c_sanity.v $PE_INT/tb_rtl/case/tc_mode2d_sanity.v +$PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v +$PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v +$PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v +$PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v $PE_INT/tb_rtl/case/tc_mode_switch_random.v From 36fc7bee8470ac8e949d2b9163e35edfff2ff9c9 Mon Sep 17 00:00:00 2001 From: HLEE80 Date: Tue, 5 May 2026 18:08:34 +0800 Subject: [PATCH 03/10] Update designs/PE_INT/python/pe_int/top.py Consistent To English documentation Co-authored-by: gemini-code-assist[bot] <176961590+gemini-code-assist[bot]@users.noreply.github.com> --- designs/PE_INT/python/pe_int/top.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/designs/PE_INT/python/pe_int/top.py b/designs/PE_INT/python/pe_int/top.py index a5034d6..0e019ed 100644 --- a/designs/PE_INT/python/pe_int/top.py +++ b/designs/PE_INT/python/pe_int/top.py @@ -19,7 +19,7 @@ def _require_pycircuit() -> None: if cas is None or compile_cycle_aware is None or wire_of is None or mux is None: raise RuntimeError( - "pyCircuit 未安裝。請先依 README 設定 PYTHONPATH，或安裝 LinxISA/pyCircuit frontend。" + "pyCircuit is not installed. Please set PYTHONPATH according to README, or install LinxISA/pyCircuit frontend." ) From a81bb6afe4c9f1d891c9e59696bbd375c5bcbbdb Mon Sep 17 00:00:00 2001 From: HenryLee Date: Tue, 5 May 2026 20:51:47 +0800 Subject: [PATCH 04/10] fix(designs): address PE_INT review feedback Tighten generated RTL contracts and PE_INT implementation structure so the deliverables match review expectations for reset style, naming, Wallace reduction, and output state ownership. --- .../api-codebase-consistency-review/SKILL.md | 38 + .../generated-code-postprocess-guard/SKILL.md | 40 + .../generated-rtl-contract-audit/SKILL.md | 40 + .../skills/pe-int-pycircuiteval-flow/SKILL.md | 2 + .../rtl-state-redundancy-review/SKILL.md | 38 + .../spec-structural-intent-review/SKILL.md | 45 + designs/PE_INT/filelist/pe_int.f | 3 +- designs/PE_INT/python/build.py | 89 +- designs/PE_INT/python/pe_int/__init__.py | 3 +- designs/PE_INT/python/pe_int/constants.py | 3 +- designs/PE_INT/python/pe_int/lane_mac.py | 21 +- designs/PE_INT/python/pe_int/mac_modes.py | 50 +- designs/PE_INT/python/pe_int/top.py | 175 +- designs/PE_INT/python/pe_int_pycircuit.py | 5 +- .../rtl/build/{pe_int_l3.v => pe_int.v} | 953 +++-- .../rtl/build/pe_int_wallace_dot8_tree.v | 3130 +++++++++++++++++ designs/PE_INT/rtl/build/pyc_primitives.v | 1304 +++---- designs/PE_INT/tb/tb_pe_int_pycircuit.py | 244 +- 18 files changed, 4631 insertions(+), 1552 deletions(-) create mode 100644 designs/PE_INT/.cursor/skills/api-codebase-consistency-review/SKILL.md create mode 100644 designs/PE_INT/.cursor/skills/generated-code-postprocess-guard/SKILL.md create mode 100644 designs/PE_INT/.cursor/skills/generated-rtl-contract-audit/SKILL.md create mode 100644 designs/PE_INT/.cursor/skills/rtl-state-redundancy-review/SKILL.md create mode 100644 designs/PE_INT/.cursor/skills/spec-structural-intent-review/SKILL.md rename designs/PE_INT/rtl/build/{pe_int_l3.v => pe_int.v} (77%) create mode 100644 designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree.v diff --git a/designs/PE_INT/.cursor/skills/api-codebase-consistency-review/SKILL.md b/designs/PE_INT/.cursor/skills/api-codebase-consistency-review/SKILL.md new file mode 100644 index 0000000..b9f71d4 --- /dev/null +++ b/designs/PE_INT/.cursor/skills/api-codebase-consistency-review/SKILL.md @@ -0,0 +1,38 @@ +--- +name: api-codebase-consistency-review +description: Reviews API usage and repository consistency. Use when code calls framework/private APIs, adds helper wrappers, introduces error messages, documentation text, naming conventions, or style-sensitive changes. +--- + +# API And Codebase Consistency Review + +## Instructions + +Use this skill during implementation and PR review to catch issues that functional tests rarely expose. + +Check whether the change fits the repository's API style, language style, naming conventions, and helper patterns. + +## Review Checklist + +1. Search for private/protected API usage such as leading-underscore methods. +2. Prefer local public helpers when they exist. +3. If adding one helper in a pair, check whether the symmetric helper is needed. +4. Match repository language for errors, docs, comments, and user-facing messages. +5. Match existing naming style for modules, files, functions, variables, and tests. +6. Avoid introducing one-off local conventions unless the user explicitly asks. +7. Check generated artifacts if API choices affect emitted code. + +## Common Failure Patterns + +- Calling `_zext` directly while a public `sext` wrapper exists. +- Adding English docs but leaving non-English runtime errors in source. +- Using a module name convention different from the project rule. +- Fixing source naming but not generated artifact naming. +- Adding compatibility wrappers without documenting why they are needed. + +## Required Evidence + +When closing the task, mention: + +- Any private API usage found and removed. +- Any language/style inconsistency fixed. +- Any naming convention verified in source and generated output. diff --git a/designs/PE_INT/.cursor/skills/generated-code-postprocess-guard/SKILL.md b/designs/PE_INT/.cursor/skills/generated-code-postprocess-guard/SKILL.md new file mode 100644 index 0000000..d33b6ae --- /dev/null +++ b/designs/PE_INT/.cursor/skills/generated-code-postprocess-guard/SKILL.md @@ -0,0 +1,40 @@ +--- +name: generated-code-postprocess-guard +description: Guards scripts that post-process generated code. Use when build scripts patch generated Verilog/SystemVerilog/C/C++/MLIR text, normalize ports/resets/names, rewrite filelists, or sync generated artifacts. +--- + +# Generated Code Postprocess Guard + +## Instructions + +Use this skill whenever generated output is modified by scripts after the generator runs. + +Post-processing must be deterministic, repeatable, and fail-fast. Avoid fragile string edits that only work for today's generated text. + +## Guard Checklist + +1. Prefer structured parsing or narrowly scoped module-aware scanning over broad regex. +2. Never use "first occurrence" edits for syntax boundaries such as `);` unless the scope is proven. +3. Make transformations idempotent. +4. Fail with a clear error if the expected pattern is absent. +5. Clean stale generated directories before regeneration when names can change. +6. Clean stale synced deliverables before copying new artifacts. +7. Sync all required submodules and update filelists in the same step. +8. Verify post-processed output by searching generated artifacts, not only by trusting script success. + +## Fragile Patterns To Avoid + +- Inserting text after the first `);` in a Verilog file. +- Rewriting module names without checking endmodule comments and instantiation sites. +- Copying new generated files without deleting stale old files. +- Updating top RTL but forgetting filelist and submodule files. +- Patching generated RTL manually instead of making the build script reproducible. + +## Required Validation + +After changing a post-process script: + +1. Force a clean regeneration. +2. Inspect generated output for the expected transformation. +3. Search for stale names/files. +4. Run the relevant build and simulation regression. diff --git a/designs/PE_INT/.cursor/skills/generated-rtl-contract-audit/SKILL.md b/designs/PE_INT/.cursor/skills/generated-rtl-contract-audit/SKILL.md new file mode 100644 index 0000000..61855e7 --- /dev/null +++ b/designs/PE_INT/.cursor/skills/generated-rtl-contract-audit/SKILL.md @@ -0,0 +1,40 @@ +--- +name: generated-rtl-contract-audit +description: Audits generated RTL deliverables against module contracts. Use after PyCircuit/DSL/HLS RTL builds, before PR review, or when checking generated Verilog reset style, ports, module names, filenames, filelists, stale artifacts, and deliverable compliance. +--- + +# Generated RTL Contract Audit + +## Instructions + +Use this skill whenever implementation source generates RTL deliverables. + +Do not treat source-level tests or model regressions as sufficient proof that deliverable RTL matches the contract. After every RTL generation step, inspect generated artifacts directly. + +## Audit Checklist + +1. Confirm top-level module ports, widths, clock, reset, valid/ready, and naming match the spec. +2. Confirm reset polarity and reset assertion/release style in generated registers and primitives. +3. Confirm module identifiers follow the project naming rule. +4. Confirm RTL filenames follow the project filename rule. +5. Confirm filelists reference the latest generated deliverables. +6. Confirm stale generated modules/files are removed or excluded. +7. Confirm submodules instantiated by the top are present in the filelist. +8. Confirm generated RTL has no unexpected compatibility wrapper unless explicitly required. + +## Required Evidence + +When closing the task, report: + +- Which generated files were audited. +- The key contract points checked. +- The command or search used to prove there are no stale names/files. +- Regression status after the audit. + +## Common Failure Patterns + +- A build passes but filelist still points at an older RTL file. +- Generated primitives use a reset style different from the spec. +- Top module name is patched but submodule or primitive names are not. +- Source module names are correct but deliverable filenames violate repo convention. +- Old build directories leak stale modules into synced RTL. diff --git a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md index 04fbde6..659f610 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md @@ -61,6 +61,8 @@ Extract executable checks from `docs/spec.md`: 3. After each build, sync deliverable RTL artifacts from the build output tree into `rtl/build/`. 4. Refresh `filelist/pe_int.f` after each sync so simulations consume the latest deliverable set. 5. Do not manually patch final RTL deliverables. +6. Use uppercase Verilog/PyCircuit module identifiers for deliverable RTL modules (for example `PE_INT`). +7. Use lowercase snake_case filenames for RTL deliverables (for example `pe_int.v`). ### Step B.1: PyCircuit Structure Rules diff --git a/designs/PE_INT/.cursor/skills/rtl-state-redundancy-review/SKILL.md b/designs/PE_INT/.cursor/skills/rtl-state-redundancy-review/SKILL.md new file mode 100644 index 0000000..a2d556d --- /dev/null +++ b/designs/PE_INT/.cursor/skills/rtl-state-redundancy-review/SKILL.md @@ -0,0 +1,38 @@ +--- +name: rtl-state-redundancy-review +description: Reviews RTL/PyCircuit state for redundant registers and feedback paths. Use when output hold logic, valid/data alignment, state registers, feedback muxes, or pipeline output commits are added or modified. +--- + +# RTL State Redundancy Review + +## Instructions + +Use this skill when reviewing or editing stateful RTL or DSL-generated hardware. + +Functional tests may pass even when the implementation contains duplicated registers. Inspect state ownership and generated RTL register names directly. + +## Review Checklist + +1. Identify every state/register introduced by the change. +2. For each register, ask what unique value it owns. +3. Check whether an output register can serve as its own feedback/hold state. +4. Check whether two registers are loaded from the same next-value expression under the same clock/reset. +5. Check whether removing a register changes latency, valid alignment, reset value, or hold behavior. +6. After refactor, search generated RTL to confirm the redundant register disappeared. + +## Common Failure Patterns + +- Separate `*_hold` and output registers store the same committed value. +- Valid/data signals use different commit boundaries. +- A helper register is added to make a mux easier but later becomes redundant. +- A state register is kept for "stability" even though the output register already provides stability. + +## Required Validation + +After removing or merging state: + +1. Run source-level regression. +2. Regenerate RTL. +3. Search generated RTL for removed register names. +4. Run RTL regression. +5. Report whether output protocol and latency remained unchanged. diff --git a/designs/PE_INT/.cursor/skills/spec-structural-intent-review/SKILL.md b/designs/PE_INT/.cursor/skills/spec-structural-intent-review/SKILL.md new file mode 100644 index 0000000..c857c12 --- /dev/null +++ b/designs/PE_INT/.cursor/skills/spec-structural-intent-review/SKILL.md @@ -0,0 +1,45 @@ +--- +name: spec-structural-intent-review +description: Reviews implementation against structural intent in specs, not just functional behavior. Use when specs mention pipeline stages, latency, logic depth, compressor trees, hierarchy, arithmetic topology, datapath width contracts, or other implementation structure. +--- + +# Spec Structural Intent Review + +## Instructions + +Use this skill when a spec or design spec describes how the hardware should be structured. + +Passing functional tests is not enough when the spec requires a particular structure. Check whether the implementation matches the intended pipeline, hierarchy, arithmetic topology, and width/depth contracts. + +## Review Checklist + +1. Identify structural requirements in the spec before reading code: + - pipeline stage boundaries + - latency definition + - control/data alignment + - arithmetic topology + - logic depth guidance + - submodule hierarchy + - datapath input/output widths +2. Compare source implementation with each structural requirement. +3. Compare generated RTL with the same requirements when available. +4. For latency, count actual registers on the real signal path. +5. For arithmetic, verify the requested topology is present, not just functionally equivalent. +6. For width contracts, verify each operation's input/output width has no arbitrary margin and no overflow in covered scenarios. + +## When To Warn + +Warn the user when: + +- A linear reduction is used where a tree/compressor structure was specified. +- A pipeline stage label exists but the actual register path differs. +- Multiple comb blocks are merged without checking logic depth. +- A generated design adds hidden balancing registers that change effective latency. +- A datapath expression relies on implicit or private width behavior. + +## Required Evidence + +Report both: + +- Functional result: whether model/PyCircuit/RTL tests pass. +- Structural result: whether the implementation matches the spec's structural intent. diff --git a/designs/PE_INT/filelist/pe_int.f b/designs/PE_INT/filelist/pe_int.f index 2641d74..3f1fe44 100644 --- a/designs/PE_INT/filelist/pe_int.f +++ b/designs/PE_INT/filelist/pe_int.f @@ -1,2 +1,3 @@ $PE_INT/rtl/build/pyc_primitives.v -$PE_INT/rtl/build/pe_int_l3.v +$PE_INT/rtl/build/pe_int_wallace_dot8_tree.v +$PE_INT/rtl/build/pe_int.v diff --git a/designs/PE_INT/python/build.py b/designs/PE_INT/python/build.py index 15ee1ee..2895665 100644 --- a/designs/PE_INT/python/build.py +++ b/designs/PE_INT/python/build.py @@ -2,62 +2,9 @@ import argparse import os -import re import subprocess import sys from pathlib import Path -from shutil import copy2 - - -def _load_current_design_name(repo_root: Path) -> str: - py_dir = repo_root / "python" - if str(py_dir) not in sys.path: - sys.path.insert(0, str(py_dir)) - try: - import pe_int_pycircuit # type: ignore - except Exception as exc: # pragma: no cover - environment-dependent import path. - raise RuntimeError(f"Unable to import pe_int_pycircuit to resolve design name: {exc}") from exc - design_name = getattr(pe_int_pycircuit.build, "__pycircuit_name__", "") - if not design_name: - raise RuntimeError("Missing build.__pycircuit_name__ in pe_int_pycircuit.") - return str(design_name) - - -def _sync_generated_rtl(repo_root: Path, out_dir: Path, design_name: str) -> None: - verilog_root = out_dir / "device" / "verilog" - design_dir = verilog_root / design_name - design_verilog = design_dir / f"{design_name}.v" - primitives_verilog = design_dir / "pyc_primitives.v" - if not design_verilog.exists(): - raise RuntimeError(f"Generated design verilog not found: {design_verilog}") - if not primitives_verilog.exists(): - raise RuntimeError(f"Generated primitives verilog not found: {primitives_verilog}") - - rtl_dir = repo_root / "rtl" / "build" - rtl_dir.mkdir(parents=True, exist_ok=True) - dst_top = rtl_dir / "pe_int_l3.v" - dst_primitives = rtl_dir / "pyc_primitives.v" - - # Keep RTL TB interface stable on pe_int_l3, while always sourcing from fresh pycc output. - top_text = design_verilog.read_text(encoding="utf-8") - if design_name != "pe_int_l3": - top_text = re.sub(rf"\bmodule\s+{re.escape(design_name)}\b", "module pe_int_l3", top_text, count=1) - top_text = re.sub(rf"\bendmodule\s*//\s*{re.escape(design_name)}\b", "endmodule // pe_int_l3", top_text) - - # Normalize external reset interface to spec: keep only rst_n as top-level input. - # pycircuit v5 default CycleAwareDomain emits a top-level active-high `rst` port. - # We keep internal reset net as `rst` but derive it from `rst_n` for deliverable RTL. - if re.search(r"^\s*input\s+rst,\s*$", top_text, flags=re.MULTILINE): - top_text = re.sub(r"^\s*input\s+rst,\s*$\n?", "", top_text, count=1, flags=re.MULTILINE) - if "assign rst = ~rst_n;" not in top_text: - top_text = re.sub(r"\);\n", ");\n\nwire rst;\nassign rst = ~rst_n;\n\n", top_text, count=1) - - dst_top.write_text(top_text, encoding="utf-8") - copy2(primitives_verilog, dst_primitives) - - filelist = repo_root / "filelist" / "pe_int.f" - filelist.parent.mkdir(parents=True, exist_ok=True) - filelist.write_text("$PE_INT/rtl/build/pyc_primitives.v\n$PE_INT/rtl/build/pe_int_l3.v\n", encoding="utf-8") def main() -> int: @@ -65,11 +12,6 @@ def main() -> int: parser.add_argument("--out-dir", default="build/pe_int", help="pycircuit build output directory") parser.add_argument("--target", default="both", choices=("rtl", "sim", "both"), help="build target") parser.add_argument("--jobs", default="8", help="parallel jobs for pycircuit build") - parser.add_argument( - "--pyc-tb-vectors", - default=os.environ.get("PE_INT_PYC_TB_VEC_PER_CASE", "8"), - help="number of vectors per PyCircuit-level testcase (default: smoke-sized 8)", - ) args = parser.parse_args() repo_root = Path(__file__).resolve().parents[1] @@ -82,26 +24,6 @@ def main() -> int: if str(repo_root / "python") not in py_path: env["PYTHONPATH"] = str(repo_root / "python") + (os.pathsep + py_path if py_path else "") - # Default toolchain resolution: - # PE_INT is expected under /designs/PE_INT, - # so pycircuit root can be derived by walking up two levels. - pycircuit_root = repo_root.parents[1] - default_toolchain_root = pycircuit_root / ".pycircuit_out" / "toolchain" / "install" - default_pycc = default_toolchain_root / "bin" / "pycc" - if "PYC_TOOLCHAIN_ROOT" not in env and default_toolchain_root.exists(): - env["PYC_TOOLCHAIN_ROOT"] = str(default_toolchain_root) - if "PYCC" not in env and default_pycc.exists(): - env["PYCC"] = str(default_pycc) - env["PE_INT_PYC_TB_VEC_PER_CASE"] = str(args.pyc_tb_vectors) - - pycircuit_target = { - # pycircuit.cli no longer accepts a pure `rtl` target; `verilator` emits - # the Verilog device artifacts that build.py syncs into rtl/build. - "rtl": "verilator", - "sim": "verilator", - "both": "both", - }[args.target] - cmd = [ sys.executable, "-m", @@ -111,19 +33,12 @@ def main() -> int: "--out-dir", str(out_dir), "--target", - pycircuit_target, + args.target, "--jobs", str(args.jobs), ] print("Running:", " ".join(cmd)) - rc = subprocess.call(cmd, cwd=str(repo_root), env=env) - if rc != 0: - return rc - - design_name = _load_current_design_name(repo_root) - _sync_generated_rtl(repo_root, out_dir, design_name) - print(f"Synced generated RTL into {repo_root / 'rtl' / 'build'} and refreshed filelist/pe_int.f") - return 0 + return subprocess.call(cmd, cwd=str(repo_root), env=env) if __name__ == "__main__": diff --git a/designs/PE_INT/python/pe_int/__init__.py b/designs/PE_INT/python/pe_int/__init__.py index 1c458f7..50d90f2 100644 --- a/designs/PE_INT/python/pe_int/__init__.py +++ b/designs/PE_INT/python/pe_int/__init__.py @@ -1,4 +1,4 @@ -from .constants import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, SPEC_LATENCY_L +from .constants import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D from .top import build, emit_mlir __all__ = [ @@ -7,7 +7,6 @@ "MODE_2C", "MODE_2D", "DEFAULT_PIPELINE_L", - "SPEC_LATENCY_L", "build", "emit_mlir", ] diff --git a/designs/PE_INT/python/pe_int/constants.py b/designs/PE_INT/python/pe_int/constants.py index 16f7a2f..3183576 100644 --- a/designs/PE_INT/python/pe_int/constants.py +++ b/designs/PE_INT/python/pe_int/constants.py @@ -5,8 +5,7 @@ MODE_2C = 2 MODE_2D = 3 -DEFAULT_PIPELINE_L = 4 -SPEC_LATENCY_L = 4 +DEFAULT_PIPELINE_L = 3 LANE_WORD_W = 80 LANE5_W = 5 diff --git a/designs/PE_INT/python/pe_int/lane_mac.py b/designs/PE_INT/python/pe_int/lane_mac.py index 9ccfb0d..65eae7a 100644 --- a/designs/PE_INT/python/pe_int/lane_mac.py +++ b/designs/PE_INT/python/pe_int/lane_mac.py @@ -35,16 +35,17 @@ def shift_scale_x1_x2_x4(value, shift2b): """ DS §3.3: use 2-level muxed shift (x1/x2/x4), avoid barrel shifter. """ - scale2 = value + value - scale4 = scale2 + scale2 - return mux(shift2b == 0, value, mux(shift2b == 1, scale2, scale4)) + return mux(shift2b == 0, value, mux(shift2b == 1, value * 2, value * 4)) + + +def select_one_hot4(sel0, sel1, sel2, sel3, cand0, cand1, cand2, cand3): + """ + One-hot selection network to avoid deep priority mux chain. + """ + return (cand0 * sel0) + (cand1 * sel1) + (cand2 * sel2) + (cand3 * sel3) def sum_shift_pair(lo, hi, e1_a, e1_b): - lo_w = wire_of(lo) - hi_w = wire_of(hi) - e1_a_w = wire_of(e1_a) - e1_b_w = wire_of(e1_b) - sh_lo = e1_a_w[0:1]._zext(width=2) + e1_b_w[0:1]._zext(width=2) - sh_hi = e1_a_w[1:2]._zext(width=2) + e1_b_w[1:2]._zext(width=2) - return shift_scale_x1_x2_x4(lo_w, sh_lo) + shift_scale_x1_x2_x4(hi_w, sh_hi) + sh_lo = wire_of(e1_a)[0:1] + wire_of(e1_b)[0:1] + sh_hi = wire_of(e1_a)[1:2] + wire_of(e1_b)[1:2] + return shift_scale_x1_x2_x4(lo, sh_lo) + shift_scale_x1_x2_x4(hi, sh_hi) diff --git a/designs/PE_INT/python/pe_int/mac_modes.py b/designs/PE_INT/python/pe_int/mac_modes.py index 60b5b3b..3d37850 100644 --- a/designs/PE_INT/python/pe_int/mac_modes.py +++ b/designs/PE_INT/python/pe_int/mac_modes.py @@ -1,9 +1,17 @@ from __future__ import annotations -from pycircuit import mux, wire_of +from pycircuit import wire_of from .decode import decode_s4_from_40, decode_s4_hi_from_80, decode_s5, decode_s5_hi_from_80, decode_s8_from_lane_word -from .lane_mac import booth_mul_signed, dot8_reduce, dot16_split8_reduce, sum_shift_pair +from .lane_mac import booth_mul_signed, dot8_reduce, dot16_split8_reduce, select_one_hot4, sum_shift_pair + + +def _mode_one_hot(mode): + is_2a = mode == 0 + is_2b = mode == 1 + is_2c = mode == 2 + is_2d = mode == 3 + return is_2a, is_2b, is_2c, is_2d def comb1_generate_products(a, b, b1): @@ -87,28 +95,34 @@ def comb2_reduce_products(products): } -def comb3_mode_merge(reduced, e1_a, e1_b0, e1_b1, *, is_2a, is_2b, is_2c, is_2d): +def comb3_mode_merge(reduced, mode, e1_a, e1_b0, e1_b1): """ DS §5.7: - 2c post-scale x1/x2/x4 - one-hot mode merge for out0_raw/out1_raw """ + is_2a, is_2b, is_2c, is_2d = _mode_one_hot(mode) s2c0 = sum_shift_pair(reduced["s2c0_lo"], reduced["s2c0_hi"], e1_a, e1_b0) s2c1 = sum_shift_pair(reduced["s2c1_lo"], reduced["s2c1_hi"], e1_a, e1_b1) - # DS hard rule: comb3 mode merge uses registered one-hot directly; no mode==const compare here. - # Keep comb3 as raw-wire combinational logic so cycle-aware balancing does not add flops here. - is_2a_w = wire_of(is_2a) - is_2b_w = wire_of(is_2b) - is_2c_w = wire_of(is_2c) - s2a_w = wire_of(reduced["s2a"]) - s2b0_w = wire_of(reduced["s2b0"]) - s2b1_w = wire_of(reduced["s2b1"]) - s2d0_w = wire_of(reduced["s2d0"]) - s2d1_w = wire_of(reduced["s2d1"]) - - out0_raw = mux(is_2a_w, s2a_w, mux(is_2b_w, s2b0_w, mux(is_2c_w, s2c0, s2d0_w))) - # 2a does not commit out1; use a real datapath branch instead of `* 0` - # so pyCircuit does not insert multiplier balance registers in comb3. - out1_raw = mux(is_2a_w, s2b1_w, mux(is_2b_w, s2b1_w, mux(is_2c_w, s2c1, s2d1_w))) + out0_raw = select_one_hot4( + is_2a, + is_2b, + is_2c, + is_2d, + reduced["s2a"], + reduced["s2b0"], + s2c0, + reduced["s2d0"], + ) + out1_raw = select_one_hot4( + is_2a, + is_2b, + is_2c, + is_2d, + reduced["s2a"] * 0, + reduced["s2b1"], + s2c1, + reduced["s2d1"], + ) return out0_raw, out1_raw diff --git a/designs/PE_INT/python/pe_int/top.py b/designs/PE_INT/python/pe_int/top.py index a5034d6..2347f6d 100644 --- a/designs/PE_INT/python/pe_int/top.py +++ b/designs/PE_INT/python/pe_int/top.py @@ -12,8 +12,9 @@ mux = None # type: ignore[assignment] wire_of = None # type: ignore[assignment] -from .constants import DEFAULT_PIPELINE_L, OUT0_W, OUT1_W, SPEC_LATENCY_L +from .constants import DEFAULT_PIPELINE_L, MODE_2A from .mac_modes import comb1_generate_products, comb2_reduce_products, comb3_mode_merge +from .pipeline import out1_hold_policy def _require_pycircuit() -> None: @@ -23,22 +24,14 @@ def _require_pycircuit() -> None: ) -def _reg_sig(domain: CycleAwareDomain, value, name: str): - return cas(domain, domain.cycle(value, name=name), cycle=0) - - -def _reg_vector(domain: CycleAwareDomain, values, *, prefix: str): - return [_reg_sig(domain, val, f"{prefix}_{idx}") for idx, val in enumerate(values)] - - def build(m: CycleAwareCircuit, domain: CycleAwareDomain, latency: int = DEFAULT_PIPELINE_L) -> None: """ Explicit DS pipeline: - input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3/output + input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3 -> output """ _require_pycircuit() - if int(latency) != SPEC_LATENCY_L: - raise ValueError(f"This top-level implementation requires fixed latency={SPEC_LATENCY_L}.") + if int(latency) != DEFAULT_PIPELINE_L: + raise ValueError(f"This top-level implementation requires fixed latency={DEFAULT_PIPELINE_L}.") _ = m.input("rst_n", width=1) in_vld = cas(domain, m.input("vld", width=1), cycle=0) @@ -55,112 +48,100 @@ def build(m: CycleAwareCircuit, domain: CycleAwareDomain, latency: int = DEFAULT c0_is_2b = in_mode == 1 c0_is_2c = in_mode == 2 c0_is_2d = in_mode == 3 + c0_out1_en = in_mode != MODE_2A # reg0: input capture boundary (cycle-aware sampled transaction). domain.next() - s0_vld = _reg_sig(domain, in_vld, "pe_int_s0_vld") - s0_is_2a = _reg_sig(domain, c0_is_2a, "pe_int_s0_is_2a") - s0_is_2b = _reg_sig(domain, c0_is_2b, "pe_int_s0_is_2b") - s0_is_2c = _reg_sig(domain, c0_is_2c, "pe_int_s0_is_2c") - s0_is_2d = _reg_sig(domain, c0_is_2d, "pe_int_s0_is_2d") - s0_a = _reg_sig(domain, in_a, "pe_int_s0_a") - s0_b = _reg_sig(domain, in_b, "pe_int_s0_b") - s0_b1 = _reg_sig(domain, in_b1, "pe_int_s0_b1") - s0_e1_a = _reg_sig(domain, in_e1_a, "pe_int_s0_e1_a") - s0_e1_b0 = _reg_sig(domain, in_e1_b0, "pe_int_s0_e1_b0") - s0_e1_b1 = _reg_sig(domain, in_e1_b1, "pe_int_s0_e1_b1") - - # comb1: decode + per-lane product generation. + s0_vld = cas(domain, domain.cycle(in_vld, name="pe_int_s0_vld"), cycle=0) + s0_mode = cas(domain, domain.cycle(in_mode, name="pe_int_s0_mode"), cycle=0) + s0_is_2a = cas(domain, domain.cycle(c0_is_2a, name="pe_int_s0_is_2a"), cycle=0) + s0_is_2b = cas(domain, domain.cycle(c0_is_2b, name="pe_int_s0_is_2b"), cycle=0) + s0_is_2c = cas(domain, domain.cycle(c0_is_2c, name="pe_int_s0_is_2c"), cycle=0) + s0_is_2d = cas(domain, domain.cycle(c0_is_2d, name="pe_int_s0_is_2d"), cycle=0) + s0_out1_en = cas(domain, domain.cycle(c0_out1_en, name="pe_int_s0_out1_en"), cycle=0) + s0_a = cas(domain, domain.cycle(in_a, name="pe_int_s0_a"), cycle=0) + s0_b = cas(domain, domain.cycle(in_b, name="pe_int_s0_b"), cycle=0) + s0_b1 = cas(domain, domain.cycle(in_b1, name="pe_int_s0_b1"), cycle=0) + s0_e1_a = cas(domain, domain.cycle(in_e1_a, name="pe_int_s0_e1_a"), cycle=0) + s0_e1_b0 = cas(domain, domain.cycle(in_e1_b0, name="pe_int_s0_e1_b0"), cycle=0) + s0_e1_b1 = cas(domain, domain.cycle(in_e1_b1, name="pe_int_s0_e1_b1"), cycle=0) + + # comb1: lane decode + lane multipliers. c1_products = comb1_generate_products(s0_a, s0_b, s0_b1) - # reg1: post-product boundary. + # reg1: product vectors + aligned controls. domain.next() - s1_vld = _reg_sig(domain, s0_vld, "pe_int_s1_vld") - s1_is_2a = _reg_sig(domain, s0_is_2a, "pe_int_s1_is_2a") - s1_is_2b = _reg_sig(domain, s0_is_2b, "pe_int_s1_is_2b") - s1_is_2c = _reg_sig(domain, s0_is_2c, "pe_int_s1_is_2c") - s1_is_2d = _reg_sig(domain, s0_is_2d, "pe_int_s1_is_2d") - s1_e1_a = _reg_sig(domain, s0_e1_a, "pe_int_s1_e1_a") - s1_e1_b0 = _reg_sig(domain, s0_e1_b0, "pe_int_s1_e1_b0") - s1_e1_b1 = _reg_sig(domain, s0_e1_b1, "pe_int_s1_e1_b1") + s1_vld = cas(domain, domain.cycle(s0_vld, name="pe_int_s1_vld"), cycle=0) + s1_mode = cas(domain, domain.cycle(s0_mode, name="pe_int_s1_mode"), cycle=0) + s1_is_2a = cas(domain, domain.cycle(s0_is_2a, name="pe_int_s1_is_2a"), cycle=0) + s1_is_2b = cas(domain, domain.cycle(s0_is_2b, name="pe_int_s1_is_2b"), cycle=0) + s1_is_2c = cas(domain, domain.cycle(s0_is_2c, name="pe_int_s1_is_2c"), cycle=0) + s1_is_2d = cas(domain, domain.cycle(s0_is_2d, name="pe_int_s1_is_2d"), cycle=0) + s1_out1_en = cas(domain, domain.cycle(s0_out1_en, name="pe_int_s1_out1_en"), cycle=0) + s1_e1_a = cas(domain, domain.cycle(s0_e1_a, name="pe_int_s1_e1_a"), cycle=0) + s1_e1_b0 = cas(domain, domain.cycle(s0_e1_b0, name="pe_int_s1_e1_b0"), cycle=0) + s1_e1_b1 = cas(domain, domain.cycle(s0_e1_b1, name="pe_int_s1_e1_b1"), cycle=0) s1_products = { - "p2a": _reg_vector(domain, c1_products["p2a"], prefix="pe_int_s1_p2a"), - "p2b0": _reg_vector(domain, c1_products["p2b0"], prefix="pe_int_s1_p2b0"), - "p2b1": _reg_vector(domain, c1_products["p2b1"], prefix="pe_int_s1_p2b1"), - "p2d0": _reg_vector(domain, c1_products["p2d0"], prefix="pe_int_s1_p2d0"), - "p2d1": _reg_vector(domain, c1_products["p2d1"], prefix="pe_int_s1_p2d1"), - "p2c0": _reg_vector(domain, c1_products["p2c0"], prefix="pe_int_s1_p2c0"), - "p2c1": _reg_vector(domain, c1_products["p2c1"], prefix="pe_int_s1_p2c1"), + "p2a": [cas(domain, domain.cycle(c1_products["p2a"][i], name=f"pe_int_s1_p2a_{i}"), cycle=0) for i in range(8)], + "p2b0": [cas(domain, domain.cycle(c1_products["p2b0"][i], name=f"pe_int_s1_p2b0_{i}"), cycle=0) for i in range(8)], + "p2b1": [cas(domain, domain.cycle(c1_products["p2b1"][i], name=f"pe_int_s1_p2b1_{i}"), cycle=0) for i in range(8)], + "p2d0": [cas(domain, domain.cycle(c1_products["p2d0"][i], name=f"pe_int_s1_p2d0_{i}"), cycle=0) for i in range(8)], + "p2d1": [cas(domain, domain.cycle(c1_products["p2d1"][i], name=f"pe_int_s1_p2d1_{i}"), cycle=0) for i in range(8)], + "p2c0": [cas(domain, domain.cycle(c1_products["p2c0"][i], name=f"pe_int_s1_p2c0_{i}"), cycle=0) for i in range(16)], + "p2c1": [cas(domain, domain.cycle(c1_products["p2c1"][i], name=f"pe_int_s1_p2c1_{i}"), cycle=0) for i in range(16)], } - # comb2: dot-product reductions only. + # comb2: dot reductions. c2_reduced = comb2_reduce_products(s1_products) - # reg2: post-reduction boundary. + # reg2: reduced sums + aligned controls. domain.next() - s2_vld = _reg_sig(domain, s1_vld, "pe_int_s2_vld") - s2_is_2a = _reg_sig(domain, s1_is_2a, "pe_int_s2_is_2a") - s2_is_2b = _reg_sig(domain, s1_is_2b, "pe_int_s2_is_2b") - s2_is_2c = _reg_sig(domain, s1_is_2c, "pe_int_s2_is_2c") - s2_is_2d = _reg_sig(domain, s1_is_2d, "pe_int_s2_is_2d") - s2_e1_a = _reg_sig(domain, s1_e1_a, "pe_int_s2_e1_a") - s2_e1_b0 = _reg_sig(domain, s1_e1_b0, "pe_int_s2_e1_b0") - s2_e1_b1 = _reg_sig(domain, s1_e1_b1, "pe_int_s2_e1_b1") - s2_s2a = _reg_sig(domain, c2_reduced["s2a"], "pe_int_s2_s2a") - s2_s2b0 = _reg_sig(domain, c2_reduced["s2b0"], "pe_int_s2_s2b0") - s2_s2b1 = _reg_sig(domain, c2_reduced["s2b1"], "pe_int_s2_s2b1") - s2_s2d0 = _reg_sig(domain, c2_reduced["s2d0"], "pe_int_s2_s2d0") - s2_s2d1 = _reg_sig(domain, c2_reduced["s2d1"], "pe_int_s2_s2d1") - s2_s2c0_lo = _reg_sig(domain, c2_reduced["s2c0_lo"], "pe_int_s2_s2c0_lo") - s2_s2c0_hi = _reg_sig(domain, c2_reduced["s2c0_hi"], "pe_int_s2_s2c0_hi") - s2_s2c1_lo = _reg_sig(domain, c2_reduced["s2c1_lo"], "pe_int_s2_s2c1_lo") - s2_s2c1_hi = _reg_sig(domain, c2_reduced["s2c1_hi"], "pe_int_s2_s2c1_hi") - - # comb3: pure combinational post-scale + mode merge with reg2 one-hot controls. - c3_reduced = { - "s2a": s2_s2a, - "s2b0": s2_s2b0, - "s2b1": s2_s2b1, - "s2d0": s2_s2d0, - "s2d1": s2_s2d1, - "s2c0_lo": s2_s2c0_lo, - "s2c0_hi": s2_s2c0_hi, - "s2c1_lo": s2_s2c1_lo, - "s2c1_hi": s2_s2c1_hi, + s2_vld = cas(domain, domain.cycle(s1_vld, name="pe_int_s2_vld"), cycle=0) + s2_mode = cas(domain, domain.cycle(s1_mode, name="pe_int_s2_mode"), cycle=0) + s2_is_2a = cas(domain, domain.cycle(s1_is_2a, name="pe_int_s2_is_2a"), cycle=0) + s2_is_2b = cas(domain, domain.cycle(s1_is_2b, name="pe_int_s2_is_2b"), cycle=0) + s2_is_2c = cas(domain, domain.cycle(s1_is_2c, name="pe_int_s2_is_2c"), cycle=0) + s2_is_2d = cas(domain, domain.cycle(s1_is_2d, name="pe_int_s2_is_2d"), cycle=0) + s2_out1_en = cas(domain, domain.cycle(s1_out1_en, name="pe_int_s2_out1_en"), cycle=0) + s2_e1_a = cas(domain, domain.cycle(s1_e1_a, name="pe_int_s2_e1_a"), cycle=0) + s2_e1_b0 = cas(domain, domain.cycle(s1_e1_b0, name="pe_int_s2_e1_b0"), cycle=0) + s2_e1_b1 = cas(domain, domain.cycle(s1_e1_b1, name="pe_int_s2_e1_b1"), cycle=0) + s2_reduced = { + "s2a": cas(domain, domain.cycle(c2_reduced["s2a"], name="pe_int_s2_s2a"), cycle=0), + "s2b0": cas(domain, domain.cycle(c2_reduced["s2b0"], name="pe_int_s2_s2b0"), cycle=0), + "s2b1": cas(domain, domain.cycle(c2_reduced["s2b1"], name="pe_int_s2_s2b1"), cycle=0), + "s2d0": cas(domain, domain.cycle(c2_reduced["s2d0"], name="pe_int_s2_s2d0"), cycle=0), + "s2d1": cas(domain, domain.cycle(c2_reduced["s2d1"], name="pe_int_s2_s2d1"), cycle=0), + "s2c0_lo": cas(domain, domain.cycle(c2_reduced["s2c0_lo"], name="pe_int_s2_s2c0_lo"), cycle=0), + "s2c0_hi": cas(domain, domain.cycle(c2_reduced["s2c0_hi"], name="pe_int_s2_s2c0_hi"), cycle=0), + "s2c1_lo": cas(domain, domain.cycle(c2_reduced["s2c1_lo"], name="pe_int_s2_s2c1_lo"), cycle=0), + "s2c1_hi": cas(domain, domain.cycle(c2_reduced["s2c1_hi"], name="pe_int_s2_s2c1_hi"), cycle=0), } - c3_out0_raw, c3_out1_raw = comb3_mode_merge( - c3_reduced, - s2_e1_a, - s2_e1_b0, - s2_e1_b1, - is_2a=s2_is_2a, - is_2b=s2_is_2b, - is_2c=s2_is_2c, - is_2d=s2_is_2d, - ) - c3_out0 = wire_of(c3_out0_raw)[0:OUT0_W] - c3_out1 = wire_of(c3_out1_raw)[0:OUT1_W] - - # reg3/output commit: vld_out/out0/out1 from the same commit boundary. - out1_hold = domain.state(width=OUT1_W, reset_value=0, name="pe_int_out1_hold") - out1_commit = mux( - wire_of(s2_vld), - mux(wire_of(s2_is_2a), wire_of(out1_hold), c3_out1), - wire_of(out1_hold), - ) - out1_hold.set(out1_commit) + # comb3: post-scale, mode-merge and out1 hold-next preparation. + c3_out0_raw, c3_out1_raw = comb3_mode_merge(s2_reduced, s2_mode, s2_e1_a, s2_e1_b0, s2_e1_b1) + c3_vld_out = s2_vld + c3_out1_update = s2_vld & s2_out1_en + + # reg3: output register boundary and explicit out1 hold register update. + out1 = out1_hold_policy( + domain, + vld_aligned=c3_vld_out, + out1_en_aligned=s2_out1_en, + out1_aligned=wire_of(c3_out1_raw)[0:16], + prefix="pe_int", + ) domain.next() - out_vld = _reg_sig(domain, s2_vld, "pe_int_out_vld") - out0 = _reg_sig(domain, c3_out0, "pe_int_out0") - out1 = _reg_sig(domain, out1_commit, "pe_int_out1") + out_vld = cas(domain, domain.cycle(c3_vld_out, name="pe_int_s3_vld_out"), cycle=0) + out0 = cas(domain, domain.cycle(wire_of(c3_out0_raw)[0:19], name="pe_int_s3_out0"), cycle=0) + out1 = cas(domain, domain.cycle(out1, name="pe_int_s3_out1"), cycle=0) m.output("vld_out", wire_of(out_vld)) m.output("out0", wire_of(out0)) m.output("out1", wire_of(out1)) -build.__pycircuit_name__ = "pe_int_ds_v05" +build.__pycircuit_name__ = "pe_int_fix7" def emit_mlir(latency: int = DEFAULT_PIPELINE_L) -> str: diff --git a/designs/PE_INT/python/pe_int_pycircuit.py b/designs/PE_INT/python/pe_int_pycircuit.py index 07f9dc9..d9d16e6 100644 --- a/designs/PE_INT/python/pe_int_pycircuit.py +++ b/designs/PE_INT/python/pe_int_pycircuit.py @@ -2,9 +2,9 @@ from pathlib import Path -from pe_int import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, SPEC_LATENCY_L, build, emit_mlir +from pe_int import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, build, emit_mlir -build.__pycircuit_name__ = "pe_int_ds_v05" +build.__pycircuit_name__ = "pe_int_fix7" __all__ = [ "MODE_2A", @@ -12,7 +12,6 @@ "MODE_2C", "MODE_2D", "DEFAULT_PIPELINE_L", - "SPEC_LATENCY_L", "build", "emit_mlir", ] diff --git a/designs/PE_INT/rtl/build/pe_int_l3.v b/designs/PE_INT/rtl/build/pe_int.v similarity index 77% rename from designs/PE_INT/rtl/build/pe_int_l3.v rename to designs/PE_INT/rtl/build/pe_int.v index ba6c4f4..08ce97b 100644 --- a/designs/PE_INT/rtl/build/pe_int_l3.v +++ b/designs/PE_INT/rtl/build/pe_int.v @@ -1,7 +1,7 @@ // Generated by pycc (pyCircuit) -// Module: pe_int_ds_v05 +// Module: PE_INT -module pe_int_l3 ( +module PE_INT ( input clk, input rst_n, input vld, @@ -21,17 +21,10 @@ wire rst; assign rst = ~rst_n; -wire [18:0] c3_out0___pycircuit_v5_strip_domain___L64; // pyc.name="c3_out0____L64" -wire [31:0] c3_out0_raw___pycircuit_v5_strip_domain___L63; // pyc.name="c3_out0_raw____L63" -wire [15:0] c3_out1___pycircuit_v5_strip_domain___L65; // pyc.name="c3_out1____L65" -wire [31:0] c3_out1_raw___pycircuit_v5_strip_domain___L63; // pyc.name="c3_out1_raw____L63" -wire [15:0] out1_commit___pycircuit_v5_strip_domain___L67; // pyc.name="out1_commit____L67" wire [18:0] pe_int_out0; // pyc.name="pe_int_out0" wire [18:0] pe_int_out0__next; // pyc.name="pe_int_out0__next" wire [15:0] pe_int_out1; // pyc.name="pe_int_out1" wire [15:0] pe_int_out1__next; // pyc.name="pe_int_out1__next" -wire [15:0] pe_int_out1_hold; // pyc.name="pe_int_out1_hold" -wire [15:0] pe_int_out1_hold__next; // pyc.name="pe_int_out1_hold__next" wire pe_int_out_vld; // pyc.name="pe_int_out_vld" wire pe_int_out_vld__next; // pyc.name="pe_int_out_vld__next" wire [79:0] pe_int_s0_a; // pyc.name="pe_int_s0_a" @@ -247,83 +240,20 @@ wire [31:0] pe_int_s2_s2d1; // pyc.name="pe_int_s2_s2d1" wire [31:0] pe_int_s2_s2d1__next; // pyc.name="pe_int_s2_s2d1__next" wire pe_int_s2_vld; // pyc.name="pe_int_s2_vld" wire pe_int_s2_vld__next; // pyc.name="pe_int_s2_vld__next" -wire [31:0] pyc_add_485; // op=pyc.add -wire [31:0] pyc_add_486; // op=pyc.add -wire [31:0] pyc_add_487; // op=pyc.add -wire [31:0] pyc_add_488; // op=pyc.add -wire [31:0] pyc_add_489; // op=pyc.add -wire [31:0] pyc_add_490; // op=pyc.add -wire [31:0] pyc_add_491; // op=pyc.add -wire [31:0] pyc_add_492; // op=pyc.add -wire [31:0] pyc_add_493; // op=pyc.add -wire [31:0] pyc_add_494; // op=pyc.add -wire [31:0] pyc_add_495; // op=pyc.add -wire [31:0] pyc_add_496; // op=pyc.add -wire [31:0] pyc_add_497; // op=pyc.add -wire [31:0] pyc_add_498; // op=pyc.add -wire [31:0] pyc_add_499; // op=pyc.add -wire [31:0] pyc_add_500; // op=pyc.add -wire [31:0] pyc_add_501; // op=pyc.add -wire [31:0] pyc_add_502; // op=pyc.add -wire [31:0] pyc_add_503; // op=pyc.add -wire [31:0] pyc_add_504; // op=pyc.add -wire [31:0] pyc_add_505; // op=pyc.add -wire [31:0] pyc_add_506; // op=pyc.add -wire [31:0] pyc_add_507; // op=pyc.add -wire [31:0] pyc_add_508; // op=pyc.add -wire [31:0] pyc_add_509; // op=pyc.add -wire [31:0] pyc_add_510; // op=pyc.add -wire [31:0] pyc_add_511; // op=pyc.add -wire [31:0] pyc_add_512; // op=pyc.add -wire [31:0] pyc_add_513; // op=pyc.add -wire [31:0] pyc_add_514; // op=pyc.add -wire [31:0] pyc_add_515; // op=pyc.add -wire [31:0] pyc_add_516; // op=pyc.add -wire [31:0] pyc_add_517; // op=pyc.add -wire [31:0] pyc_add_518; // op=pyc.add -wire [31:0] pyc_add_519; // op=pyc.add -wire [31:0] pyc_add_520; // op=pyc.add -wire [31:0] pyc_add_521; // op=pyc.add -wire [31:0] pyc_add_522; // op=pyc.add -wire [31:0] pyc_add_523; // op=pyc.add -wire [31:0] pyc_add_524; // op=pyc.add -wire [31:0] pyc_add_525; // op=pyc.add -wire [31:0] pyc_add_526; // op=pyc.add -wire [31:0] pyc_add_527; // op=pyc.add -wire [31:0] pyc_add_528; // op=pyc.add -wire [31:0] pyc_add_529; // op=pyc.add +wire [1:0] pyc_add_524; // op=pyc.add +wire [1:0] pyc_add_529; // op=pyc.add wire [31:0] pyc_add_530; // op=pyc.add wire [31:0] pyc_add_531; // op=pyc.add -wire [31:0] pyc_add_532; // op=pyc.add -wire [31:0] pyc_add_533; // op=pyc.add -wire [31:0] pyc_add_534; // op=pyc.add -wire [31:0] pyc_add_535; // op=pyc.add wire [31:0] pyc_add_536; // op=pyc.add wire [31:0] pyc_add_537; // op=pyc.add -wire [31:0] pyc_add_538; // op=pyc.add -wire [31:0] pyc_add_539; // op=pyc.add -wire [31:0] pyc_add_540; // op=pyc.add -wire [31:0] pyc_add_541; // op=pyc.add wire [31:0] pyc_add_542; // op=pyc.add -wire [31:0] pyc_add_543; // op=pyc.add -wire [31:0] pyc_add_544; // op=pyc.add -wire [31:0] pyc_add_545; // op=pyc.add -wire [31:0] pyc_add_546; // op=pyc.add -wire [31:0] pyc_add_547; // op=pyc.add -wire [1:0] pyc_add_587; // op=pyc.add -wire [1:0] pyc_add_592; // op=pyc.add -wire [31:0] pyc_add_593; // op=pyc.add -wire [31:0] pyc_add_594; // op=pyc.add -wire [31:0] pyc_add_599; // op=pyc.add -wire [31:0] pyc_add_600; // op=pyc.add -wire [31:0] pyc_add_605; // op=pyc.add -wire [1:0] pyc_add_608; // op=pyc.add -wire [1:0] pyc_add_611; // op=pyc.add -wire [31:0] pyc_add_612; // op=pyc.add -wire [31:0] pyc_add_613; // op=pyc.add -wire [31:0] pyc_add_618; // op=pyc.add -wire [31:0] pyc_add_619; // op=pyc.add -wire [31:0] pyc_add_624; // op=pyc.add +wire [1:0] pyc_add_545; // op=pyc.add +wire [1:0] pyc_add_548; // op=pyc.add +wire [31:0] pyc_add_549; // op=pyc.add +wire [31:0] pyc_add_550; // op=pyc.add +wire [31:0] pyc_add_555; // op=pyc.add +wire [31:0] pyc_add_556; // op=pyc.add +wire [31:0] pyc_add_561; // op=pyc.add wire [18:0] pyc_comb_15; // op=pyc.comb wire [15:0] pyc_comb_16; // op=pyc.comb wire [1:0] pyc_comb_17; // op=pyc.comb @@ -429,27 +359,18 @@ wire [1:0] pyc_comb_410; // op=pyc.comb wire [1:0] pyc_comb_412; // op=pyc.comb wire pyc_comb_43; // op=pyc.comb wire [1:0] pyc_comb_48; // op=pyc.comb +wire pyc_comb_497; // op=pyc.comb +wire pyc_comb_498; // op=pyc.comb +wire [2:0] pyc_comb_499; // op=pyc.comb wire [1:0] pyc_comb_50; // op=pyc.comb -wire [31:0] pyc_comb_548; // op=pyc.comb -wire [31:0] pyc_comb_549; // op=pyc.comb -wire [31:0] pyc_comb_550; // op=pyc.comb -wire [31:0] pyc_comb_551; // op=pyc.comb -wire [31:0] pyc_comb_552; // op=pyc.comb -wire [31:0] pyc_comb_553; // op=pyc.comb -wire [31:0] pyc_comb_554; // op=pyc.comb -wire [31:0] pyc_comb_555; // op=pyc.comb -wire [31:0] pyc_comb_556; // op=pyc.comb -wire pyc_comb_560; // op=pyc.comb -wire pyc_comb_561; // op=pyc.comb -wire [2:0] pyc_comb_562; // op=pyc.comb -wire [2:0] pyc_comb_563; // op=pyc.comb -wire pyc_comb_568; // op=pyc.comb -wire pyc_comb_569; // op=pyc.comb -wire pyc_comb_570; // op=pyc.comb -wire [18:0] pyc_comb_633; // op=pyc.comb -wire [15:0] pyc_comb_634; // op=pyc.comb -wire [15:0] pyc_comb_638; // op=pyc.comb -wire [15:0] pyc_comb_639; // op=pyc.comb +wire [2:0] pyc_comb_500; // op=pyc.comb +wire pyc_comb_505; // op=pyc.comb +wire pyc_comb_506; // op=pyc.comb +wire pyc_comb_507; // op=pyc.comb +wire [18:0] pyc_comb_570; // op=pyc.comb +wire [15:0] pyc_comb_571; // op=pyc.comb +wire [15:0] pyc_comb_575; // op=pyc.comb +wire [15:0] pyc_comb_576; // op=pyc.comb wire [7:0] pyc_concat_107; // op=pyc.concat wire [7:0] pyc_concat_113; // op=pyc.concat wire [7:0] pyc_concat_132; // op=pyc.concat @@ -462,8 +383,8 @@ wire [7:0] pyc_concat_199; // op=pyc.concat wire [7:0] pyc_concat_201; // op=pyc.concat wire [7:0] pyc_concat_220; // op=pyc.concat wire [7:0] pyc_concat_224; // op=pyc.concat -wire [2:0] pyc_concat_558; // op=pyc.concat -wire [2:0] pyc_concat_559; // op=pyc.concat +wire [2:0] pyc_concat_495; // op=pyc.concat +wire [2:0] pyc_concat_496; // op=pyc.concat wire [7:0] pyc_concat_57; // op=pyc.concat wire [7:0] pyc_concat_63; // op=pyc.concat wire [7:0] pyc_concat_82; // op=pyc.concat @@ -482,14 +403,14 @@ wire pyc_eq_11; // op=pyc.eq wire pyc_eq_12; // op=pyc.eq wire pyc_eq_13; // op=pyc.eq wire pyc_eq_14; // op=pyc.eq -wire pyc_eq_595; // op=pyc.eq -wire pyc_eq_596; // op=pyc.eq -wire pyc_eq_601; // op=pyc.eq -wire pyc_eq_602; // op=pyc.eq -wire pyc_eq_614; // op=pyc.eq -wire pyc_eq_615; // op=pyc.eq -wire pyc_eq_620; // op=pyc.eq -wire pyc_eq_621; // op=pyc.eq +wire pyc_eq_532; // op=pyc.eq +wire pyc_eq_533; // op=pyc.eq +wire pyc_eq_538; // op=pyc.eq +wire pyc_eq_539; // op=pyc.eq +wire pyc_eq_551; // op=pyc.eq +wire pyc_eq_552; // op=pyc.eq +wire pyc_eq_557; // op=pyc.eq +wire pyc_eq_558; // op=pyc.eq wire [4:0] pyc_extract_103; // op=pyc.extract wire [4:0] pyc_extract_104; // op=pyc.extract wire [3:0] pyc_extract_105; // op=pyc.extract @@ -562,26 +483,26 @@ wire [4:0] pyc_extract_306; // op=pyc.extract wire [4:0] pyc_extract_311; // op=pyc.extract wire [4:0] pyc_extract_316; // op=pyc.extract wire [4:0] pyc_extract_321; // op=pyc.extract +wire pyc_extract_502; // op=pyc.extract +wire pyc_extract_503; // op=pyc.extract +wire pyc_extract_504; // op=pyc.extract wire [39:0] pyc_extract_52; // op=pyc.extract +wire pyc_extract_520; // op=pyc.extract +wire pyc_extract_522; // op=pyc.extract +wire pyc_extract_525; // op=pyc.extract +wire pyc_extract_527; // op=pyc.extract wire [4:0] pyc_extract_53; // op=pyc.extract wire [4:0] pyc_extract_54; // op=pyc.extract +wire pyc_extract_543; // op=pyc.extract +wire pyc_extract_546; // op=pyc.extract wire [3:0] pyc_extract_55; // op=pyc.extract wire [3:0] pyc_extract_56; // op=pyc.extract -wire pyc_extract_565; // op=pyc.extract -wire pyc_extract_566; // op=pyc.extract -wire pyc_extract_567; // op=pyc.extract -wire pyc_extract_583; // op=pyc.extract -wire pyc_extract_585; // op=pyc.extract -wire pyc_extract_588; // op=pyc.extract +wire [18:0] pyc_extract_568; // op=pyc.extract +wire [15:0] pyc_extract_569; // op=pyc.extract wire [4:0] pyc_extract_59; // op=pyc.extract -wire pyc_extract_590; // op=pyc.extract wire [4:0] pyc_extract_60; // op=pyc.extract -wire pyc_extract_606; // op=pyc.extract -wire pyc_extract_609; // op=pyc.extract wire [3:0] pyc_extract_61; // op=pyc.extract wire [3:0] pyc_extract_62; // op=pyc.extract -wire [18:0] pyc_extract_631; // op=pyc.extract -wire [15:0] pyc_extract_632; // op=pyc.extract wire [4:0] pyc_extract_65; // op=pyc.extract wire [3:0] pyc_extract_66; // op=pyc.extract wire [4:0] pyc_extract_68; // op=pyc.extract @@ -598,6 +519,15 @@ wire [4:0] pyc_extract_90; // op=pyc.extract wire [3:0] pyc_extract_91; // op=pyc.extract wire [4:0] pyc_extract_93; // op=pyc.extract wire [3:0] pyc_extract_94; // op=pyc.extract +wire [31:0] pyc_instance_485; // op=pyc.instance +wire [31:0] pyc_instance_486; // op=pyc.instance +wire [31:0] pyc_instance_487; // op=pyc.instance +wire [31:0] pyc_instance_488; // op=pyc.instance +wire [31:0] pyc_instance_489; // op=pyc.instance +wire [31:0] pyc_instance_490; // op=pyc.instance +wire [31:0] pyc_instance_491; // op=pyc.instance +wire [31:0] pyc_instance_492; // op=pyc.instance +wire [31:0] pyc_instance_493; // op=pyc.instance wire [31:0] pyc_mul_100; // op=pyc.mul wire [31:0] pyc_mul_101; // op=pyc.mul wire [31:0] pyc_mul_102; // op=pyc.mul @@ -670,22 +600,22 @@ wire [31:0] pyc_mul_76; // op=pyc.mul wire [31:0] pyc_mul_77; // op=pyc.mul wire [31:0] pyc_mul_98; // op=pyc.mul wire [31:0] pyc_mul_99; // op=pyc.mul -wire [31:0] pyc_mux_597; // op=pyc.mux -wire [31:0] pyc_mux_598; // op=pyc.mux -wire [31:0] pyc_mux_603; // op=pyc.mux -wire [31:0] pyc_mux_604; // op=pyc.mux -wire [31:0] pyc_mux_616; // op=pyc.mux -wire [31:0] pyc_mux_617; // op=pyc.mux -wire [31:0] pyc_mux_622; // op=pyc.mux -wire [31:0] pyc_mux_623; // op=pyc.mux -wire [31:0] pyc_mux_625; // op=pyc.mux -wire [31:0] pyc_mux_626; // op=pyc.mux -wire [31:0] pyc_mux_627; // op=pyc.mux -wire [31:0] pyc_mux_628; // op=pyc.mux -wire [31:0] pyc_mux_629; // op=pyc.mux -wire [31:0] pyc_mux_630; // op=pyc.mux -wire [15:0] pyc_mux_636; // op=pyc.mux -wire [15:0] pyc_mux_637; // op=pyc.mux +wire [31:0] pyc_mux_534; // op=pyc.mux +wire [31:0] pyc_mux_535; // op=pyc.mux +wire [31:0] pyc_mux_540; // op=pyc.mux +wire [31:0] pyc_mux_541; // op=pyc.mux +wire [31:0] pyc_mux_553; // op=pyc.mux +wire [31:0] pyc_mux_554; // op=pyc.mux +wire [31:0] pyc_mux_559; // op=pyc.mux +wire [31:0] pyc_mux_560; // op=pyc.mux +wire [31:0] pyc_mux_562; // op=pyc.mux +wire [31:0] pyc_mux_563; // op=pyc.mux +wire [31:0] pyc_mux_564; // op=pyc.mux +wire [31:0] pyc_mux_565; // op=pyc.mux +wire [31:0] pyc_mux_566; // op=pyc.mux +wire [31:0] pyc_mux_567; // op=pyc.mux +wire [15:0] pyc_mux_573; // op=pyc.mux +wire [15:0] pyc_mux_574; // op=pyc.mux wire pyc_reg_34; // op=pyc.reg wire pyc_reg_36; // op=pyc.reg wire pyc_reg_38; // op=pyc.reg @@ -776,25 +706,24 @@ wire [31:0] pyc_reg_482; // op=pyc.reg wire [31:0] pyc_reg_483; // op=pyc.reg wire [31:0] pyc_reg_484; // op=pyc.reg wire [1:0] pyc_reg_49; // op=pyc.reg +wire pyc_reg_494; // op=pyc.reg +wire [2:0] pyc_reg_501; // op=pyc.reg +wire [1:0] pyc_reg_508; // op=pyc.reg +wire [1:0] pyc_reg_509; // op=pyc.reg wire [1:0] pyc_reg_51; // op=pyc.reg -wire pyc_reg_557; // op=pyc.reg -wire [2:0] pyc_reg_564; // op=pyc.reg -wire [1:0] pyc_reg_571; // op=pyc.reg -wire [1:0] pyc_reg_572; // op=pyc.reg -wire [1:0] pyc_reg_573; // op=pyc.reg -wire [31:0] pyc_reg_574; // op=pyc.reg -wire [31:0] pyc_reg_575; // op=pyc.reg -wire [31:0] pyc_reg_576; // op=pyc.reg -wire [31:0] pyc_reg_577; // op=pyc.reg -wire [31:0] pyc_reg_578; // op=pyc.reg -wire [31:0] pyc_reg_579; // op=pyc.reg -wire [31:0] pyc_reg_580; // op=pyc.reg -wire [31:0] pyc_reg_581; // op=pyc.reg -wire [31:0] pyc_reg_582; // op=pyc.reg -wire [15:0] pyc_reg_635; // op=pyc.reg -wire pyc_reg_640; // op=pyc.reg -wire [18:0] pyc_reg_641; // op=pyc.reg -wire [15:0] pyc_reg_642; // op=pyc.reg +wire [1:0] pyc_reg_510; // op=pyc.reg +wire [31:0] pyc_reg_511; // op=pyc.reg +wire [31:0] pyc_reg_512; // op=pyc.reg +wire [31:0] pyc_reg_513; // op=pyc.reg +wire [31:0] pyc_reg_514; // op=pyc.reg +wire [31:0] pyc_reg_515; // op=pyc.reg +wire [31:0] pyc_reg_516; // op=pyc.reg +wire [31:0] pyc_reg_517; // op=pyc.reg +wire [31:0] pyc_reg_518; // op=pyc.reg +wire [31:0] pyc_reg_519; // op=pyc.reg +wire [15:0] pyc_reg_572; // op=pyc.reg +wire pyc_reg_577; // op=pyc.reg +wire [18:0] pyc_reg_578; // op=pyc.reg wire [31:0] pyc_sext_108; // op=pyc.sext wire [31:0] pyc_sext_114; // op=pyc.sext wire [31:0] pyc_sext_117; // op=pyc.sext @@ -883,17 +812,16 @@ wire [31:0] pyc_sext_92; // op=pyc.sext wire [31:0] pyc_sext_95; // op=pyc.sext wire [31:0] pyc_sext_96; // op=pyc.sext wire [31:0] pyc_sext_97; // op=pyc.sext -wire [1:0] pyc_zext_584; // op=pyc.zext -wire [1:0] pyc_zext_586; // op=pyc.zext -wire [1:0] pyc_zext_589; // op=pyc.zext -wire [1:0] pyc_zext_591; // op=pyc.zext -wire [1:0] pyc_zext_607; // op=pyc.zext -wire [1:0] pyc_zext_610; // op=pyc.zext +wire [1:0] pyc_zext_521; // op=pyc.zext +wire [1:0] pyc_zext_523; // op=pyc.zext +wire [1:0] pyc_zext_526; // op=pyc.zext +wire [1:0] pyc_zext_528; // op=pyc.zext +wire [1:0] pyc_zext_544; // op=pyc.zext +wire [1:0] pyc_zext_547; // op=pyc.zext // --- Combinational (netlist) -assign pe_int_out0 = pyc_reg_641; -assign pe_int_out1 = pyc_reg_642; -assign pe_int_out_vld = pyc_reg_640; +assign pe_int_out0 = pyc_reg_578; +assign pe_int_out_vld = pyc_reg_577; assign pe_int_s0_a = pyc_reg_44; assign pe_int_s0_b = pyc_reg_45; assign pe_int_s0_b1 = pyc_reg_46; @@ -944,6 +872,7 @@ assign pe_int_s1_p2c1_11 = pyc_reg_480; assign pe_int_s1_p2c1_12 = pyc_reg_481; assign pe_int_s1_p2c1_13 = pyc_reg_482; assign pe_int_s1_p2c1_14 = pyc_reg_483; +assign pe_int_s1_p2c1_15 = pyc_reg_484; assign pe_int_s1_p2c1_2 = pyc_reg_471; assign pe_int_s1_p2c1_3 = pyc_reg_472; assign pe_int_s1_p2c1_4 = pyc_reg_473; @@ -968,17 +897,26 @@ assign pe_int_s1_p2d1_4 = pyc_reg_449; assign pe_int_s1_p2d1_5 = pyc_reg_450; assign pe_int_s1_p2d1_6 = pyc_reg_451; assign pe_int_s1_p2d1_7 = pyc_reg_452; -assign pe_int_s2_e1_a = pyc_reg_571; -assign pe_int_s2_e1_b0 = pyc_reg_572; -assign pe_int_s2_e1_b1 = pyc_reg_573; -assign pe_int_s2_s2a = pyc_reg_574; -assign pe_int_s2_s2b0 = pyc_reg_575; -assign pe_int_s2_s2b1 = pyc_reg_576; -assign pe_int_s2_s2c0_hi = pyc_reg_580; -assign pe_int_s2_s2c0_lo = pyc_reg_579; -assign pe_int_s2_s2c1_lo = pyc_reg_581; -assign pe_int_s2_s2d0 = pyc_reg_577; -assign pe_int_s2_s2d1 = pyc_reg_578; +assign pe_int_s2_e1_a = pyc_reg_508; +assign pe_int_s2_e1_b0 = pyc_reg_509; +assign pe_int_s2_e1_b1 = pyc_reg_510; +assign pe_int_s2_s2a = pyc_reg_511; +assign pe_int_s2_s2a__next = pyc_instance_485; +assign pe_int_s2_s2b0 = pyc_reg_512; +assign pe_int_s2_s2b0__next = pyc_instance_486; +assign pe_int_s2_s2b1 = pyc_reg_513; +assign pe_int_s2_s2b1__next = pyc_instance_487; +assign pe_int_s2_s2c0_hi = pyc_reg_517; +assign pe_int_s2_s2c0_hi__next = pyc_instance_491; +assign pe_int_s2_s2c0_lo = pyc_reg_516; +assign pe_int_s2_s2c0_lo__next = pyc_instance_490; +assign pe_int_s2_s2c1_hi__next = pyc_instance_493; +assign pe_int_s2_s2c1_lo = pyc_reg_518; +assign pe_int_s2_s2c1_lo__next = pyc_instance_492; +assign pe_int_s2_s2d0 = pyc_reg_514; +assign pe_int_s2_s2d0__next = pyc_instance_488; +assign pe_int_s2_s2d1 = pyc_reg_515; +assign pe_int_s2_s2d1__next = pyc_instance_489; assign pyc_constant_1 = 19'd0; assign pyc_constant_2 = 16'd0; assign pyc_constant_3 = 2'd1; @@ -1482,177 +1420,208 @@ assign pyc_comb_43 = pe_int_s1_is_2d__next; assign pe_int_s0_e1_a = pyc_reg_47; assign pe_int_s1_e1_a__next = pe_int_s0_e1_a; assign pyc_comb_48 = pe_int_s1_e1_a__next; +assign pe_int_s2_vld = pyc_reg_494; +assign pe_int_out_vld__next = pe_int_s2_vld; +assign pyc_concat_495 = {pyc_comb_405, pyc_comb_403, pyc_comb_401}; +assign pyc_concat_496 = {pyc_comb_22, pyc_comb_22, pyc_comb_22}; +assign pyc_comb_497 = pe_int_s2_vld; +assign pyc_comb_498 = pe_int_out_vld__next; +assign pyc_comb_499 = pyc_concat_495; +assign pyc_comb_500 = pyc_concat_496; assign pe_int_s0_e1_b0 = pyc_reg_49; assign pe_int_s1_e1_b0__next = pe_int_s0_e1_b0; assign pyc_comb_50 = pe_int_s1_e1_b0__next; -assign pe_int_s1_p2c1_15 = pyc_reg_484; -assign pyc_add_485 = (pe_int_s1_p2a_0 + pe_int_s1_p2a_1); -assign pyc_add_486 = (pyc_add_485 + pe_int_s1_p2a_2); -assign pyc_add_487 = (pyc_add_486 + pe_int_s1_p2a_3); -assign pyc_add_488 = (pyc_add_487 + pe_int_s1_p2a_4); -assign pyc_add_489 = (pyc_add_488 + pe_int_s1_p2a_5); -assign pyc_add_490 = (pyc_add_489 + pe_int_s1_p2a_6); -assign pyc_add_491 = (pyc_add_490 + pe_int_s1_p2a_7); -assign pe_int_s2_s2a__next = pyc_add_491; -assign pyc_add_492 = (pe_int_s1_p2b0_0 + pe_int_s1_p2b0_1); -assign pyc_add_493 = (pyc_add_492 + pe_int_s1_p2b0_2); -assign pyc_add_494 = (pyc_add_493 + pe_int_s1_p2b0_3); -assign pyc_add_495 = (pyc_add_494 + pe_int_s1_p2b0_4); -assign pyc_add_496 = (pyc_add_495 + pe_int_s1_p2b0_5); -assign pyc_add_497 = (pyc_add_496 + pe_int_s1_p2b0_6); -assign pyc_add_498 = (pyc_add_497 + pe_int_s1_p2b0_7); -assign pe_int_s2_s2b0__next = pyc_add_498; -assign pyc_add_499 = (pe_int_s1_p2b1_0 + pe_int_s1_p2b1_1); -assign pyc_add_500 = (pyc_add_499 + pe_int_s1_p2b1_2); -assign pyc_add_501 = (pyc_add_500 + pe_int_s1_p2b1_3); -assign pyc_add_502 = (pyc_add_501 + pe_int_s1_p2b1_4); -assign pyc_add_503 = (pyc_add_502 + pe_int_s1_p2b1_5); -assign pyc_add_504 = (pyc_add_503 + pe_int_s1_p2b1_6); -assign pyc_add_505 = (pyc_add_504 + pe_int_s1_p2b1_7); -assign pe_int_s2_s2b1__next = pyc_add_505; -assign pyc_add_506 = (pe_int_s1_p2d0_0 + pe_int_s1_p2d0_1); -assign pyc_add_507 = (pyc_add_506 + pe_int_s1_p2d0_2); -assign pyc_add_508 = (pyc_add_507 + pe_int_s1_p2d0_3); -assign pyc_add_509 = (pyc_add_508 + pe_int_s1_p2d0_4); -assign pyc_add_510 = (pyc_add_509 + pe_int_s1_p2d0_5); -assign pyc_add_511 = (pyc_add_510 + pe_int_s1_p2d0_6); -assign pyc_add_512 = (pyc_add_511 + pe_int_s1_p2d0_7); -assign pe_int_s2_s2d0__next = pyc_add_512; -assign pyc_add_513 = (pe_int_s1_p2d1_0 + pe_int_s1_p2d1_1); -assign pyc_add_514 = (pyc_add_513 + pe_int_s1_p2d1_2); -assign pyc_add_515 = (pyc_add_514 + pe_int_s1_p2d1_3); -assign pyc_add_516 = (pyc_add_515 + pe_int_s1_p2d1_4); -assign pyc_add_517 = (pyc_add_516 + pe_int_s1_p2d1_5); -assign pyc_add_518 = (pyc_add_517 + pe_int_s1_p2d1_6); -assign pyc_add_519 = (pyc_add_518 + pe_int_s1_p2d1_7); -assign pe_int_s2_s2d1__next = pyc_add_519; -assign pyc_add_520 = (pe_int_s1_p2c0_0 + pe_int_s1_p2c0_1); -assign pyc_add_521 = (pyc_add_520 + pe_int_s1_p2c0_2); -assign pyc_add_522 = (pyc_add_521 + pe_int_s1_p2c0_3); -assign pyc_add_523 = (pyc_add_522 + pe_int_s1_p2c0_4); -assign pyc_add_524 = (pyc_add_523 + pe_int_s1_p2c0_5); -assign pyc_add_525 = (pyc_add_524 + pe_int_s1_p2c0_6); -assign pyc_add_526 = (pyc_add_525 + pe_int_s1_p2c0_7); -assign pe_int_s2_s2c0_lo__next = pyc_add_526; -assign pyc_add_527 = (pe_int_s1_p2c0_8 + pe_int_s1_p2c0_9); -assign pyc_add_528 = (pyc_add_527 + pe_int_s1_p2c0_10); -assign pyc_add_529 = (pyc_add_528 + pe_int_s1_p2c0_11); -assign pyc_add_530 = (pyc_add_529 + pe_int_s1_p2c0_12); -assign pyc_add_531 = (pyc_add_530 + pe_int_s1_p2c0_13); -assign pyc_add_532 = (pyc_add_531 + pe_int_s1_p2c0_14); -assign pyc_add_533 = (pyc_add_532 + pe_int_s1_p2c0_15); -assign pe_int_s2_s2c0_hi__next = pyc_add_533; -assign pyc_add_534 = (pe_int_s1_p2c1_0 + pe_int_s1_p2c1_1); -assign pyc_add_535 = (pyc_add_534 + pe_int_s1_p2c1_2); -assign pyc_add_536 = (pyc_add_535 + pe_int_s1_p2c1_3); -assign pyc_add_537 = (pyc_add_536 + pe_int_s1_p2c1_4); -assign pyc_add_538 = (pyc_add_537 + pe_int_s1_p2c1_5); -assign pyc_add_539 = (pyc_add_538 + pe_int_s1_p2c1_6); -assign pyc_add_540 = (pyc_add_539 + pe_int_s1_p2c1_7); -assign pe_int_s2_s2c1_lo__next = pyc_add_540; -assign pyc_add_541 = (pe_int_s1_p2c1_8 + pe_int_s1_p2c1_9); -assign pyc_add_542 = (pyc_add_541 + pe_int_s1_p2c1_10); -assign pyc_add_543 = (pyc_add_542 + pe_int_s1_p2c1_11); -assign pyc_add_544 = (pyc_add_543 + pe_int_s1_p2c1_12); -assign pyc_add_545 = (pyc_add_544 + pe_int_s1_p2c1_13); -assign pyc_add_546 = (pyc_add_545 + pe_int_s1_p2c1_14); -assign pyc_add_547 = (pyc_add_546 + pe_int_s1_p2c1_15); -assign pe_int_s2_s2c1_hi__next = pyc_add_547; -assign pyc_comb_548 = pe_int_s2_s2a__next; -assign pyc_comb_549 = pe_int_s2_s2b0__next; -assign pyc_comb_550 = pe_int_s2_s2b1__next; -assign pyc_comb_551 = pe_int_s2_s2d0__next; -assign pyc_comb_552 = pe_int_s2_s2d1__next; -assign pyc_comb_553 = pe_int_s2_s2c0_lo__next; -assign pyc_comb_554 = pe_int_s2_s2c0_hi__next; -assign pyc_comb_555 = pe_int_s2_s2c1_lo__next; -assign pyc_comb_556 = pe_int_s2_s2c1_hi__next; -assign pe_int_s2_vld = pyc_reg_557; -assign pe_int_out_vld__next = pe_int_s2_vld; -assign pyc_concat_558 = {pyc_comb_405, pyc_comb_403, pyc_comb_401}; -assign pyc_concat_559 = {pyc_comb_22, pyc_comb_22, pyc_comb_22}; -assign pyc_comb_560 = pe_int_s2_vld; -assign pyc_comb_561 = pe_int_out_vld__next; -assign pyc_comb_562 = pyc_concat_558; -assign pyc_comb_563 = pyc_concat_559; -assign pyc_extract_565 = pyc_reg_564[0]; -assign pyc_extract_566 = pyc_reg_564[1]; -assign pyc_extract_567 = pyc_reg_564[2]; -assign pe_int_s2_is_2a = pyc_extract_565; -assign pe_int_s2_is_2b = pyc_extract_566; -assign pe_int_s2_is_2c = pyc_extract_567; -assign pyc_comb_568 = pe_int_s2_is_2a; -assign pyc_comb_569 = pe_int_s2_is_2b; -assign pyc_comb_570 = pe_int_s2_is_2c; -assign pe_int_s2_s2c1_hi = pyc_reg_582; -assign pyc_extract_583 = pe_int_s2_e1_a[0]; -assign pyc_zext_584 = {{1{1'b0}}, pyc_extract_583}; -assign pyc_extract_585 = pe_int_s2_e1_b0[0]; -assign pyc_zext_586 = {{1{1'b0}}, pyc_extract_585}; -assign pyc_add_587 = (pyc_zext_584 + pyc_zext_586); -assign pyc_extract_588 = pe_int_s2_e1_a[1]; -assign pyc_zext_589 = {{1{1'b0}}, pyc_extract_588}; -assign pyc_extract_590 = pe_int_s2_e1_b0[1]; -assign pyc_zext_591 = {{1{1'b0}}, pyc_extract_590}; -assign pyc_add_592 = (pyc_zext_589 + pyc_zext_591); -assign pyc_add_593 = (pe_int_s2_s2c0_lo + pe_int_s2_s2c0_lo); -assign pyc_add_594 = (pyc_add_593 + pyc_add_593); -assign pyc_eq_595 = (pyc_add_587 == pyc_comb_19); -assign pyc_eq_596 = (pyc_add_587 == pyc_comb_17); -assign pyc_mux_597 = (pyc_eq_596 ? pyc_add_593 : pyc_add_594); -assign pyc_mux_598 = (pyc_eq_595 ? pe_int_s2_s2c0_lo : pyc_mux_597); -assign pyc_add_599 = (pe_int_s2_s2c0_hi + pe_int_s2_s2c0_hi); -assign pyc_add_600 = (pyc_add_599 + pyc_add_599); -assign pyc_eq_601 = (pyc_add_592 == pyc_comb_19); -assign pyc_eq_602 = (pyc_add_592 == pyc_comb_17); -assign pyc_mux_603 = (pyc_eq_602 ? pyc_add_599 : pyc_add_600); -assign pyc_mux_604 = (pyc_eq_601 ? pe_int_s2_s2c0_hi : pyc_mux_603); -assign pyc_add_605 = (pyc_mux_598 + pyc_mux_604); -assign pyc_extract_606 = pe_int_s2_e1_b1[0]; -assign pyc_zext_607 = {{1{1'b0}}, pyc_extract_606}; -assign pyc_add_608 = (pyc_zext_584 + pyc_zext_607); -assign pyc_extract_609 = pe_int_s2_e1_b1[1]; -assign pyc_zext_610 = {{1{1'b0}}, pyc_extract_609}; -assign pyc_add_611 = (pyc_zext_589 + pyc_zext_610); -assign pyc_add_612 = (pe_int_s2_s2c1_lo + pe_int_s2_s2c1_lo); -assign pyc_add_613 = (pyc_add_612 + pyc_add_612); -assign pyc_eq_614 = (pyc_add_608 == pyc_comb_19); -assign pyc_eq_615 = (pyc_add_608 == pyc_comb_17); -assign pyc_mux_616 = (pyc_eq_615 ? pyc_add_612 : pyc_add_613); -assign pyc_mux_617 = (pyc_eq_614 ? pe_int_s2_s2c1_lo : pyc_mux_616); -assign pyc_add_618 = (pe_int_s2_s2c1_hi + pe_int_s2_s2c1_hi); -assign pyc_add_619 = (pyc_add_618 + pyc_add_618); -assign pyc_eq_620 = (pyc_add_611 == pyc_comb_19); -assign pyc_eq_621 = (pyc_add_611 == pyc_comb_17); -assign pyc_mux_622 = (pyc_eq_621 ? pyc_add_618 : pyc_add_619); -assign pyc_mux_623 = (pyc_eq_620 ? pe_int_s2_s2c1_hi : pyc_mux_622); -assign pyc_add_624 = (pyc_mux_617 + pyc_mux_623); -assign pyc_mux_625 = (pyc_comb_570 ? pyc_add_605 : pe_int_s2_s2d0); -assign pyc_mux_626 = (pyc_comb_569 ? pe_int_s2_s2b0 : pyc_mux_625); -assign pyc_mux_627 = (pyc_comb_568 ? pe_int_s2_s2a : pyc_mux_626); -assign pyc_mux_628 = (pyc_comb_570 ? pyc_add_624 : pe_int_s2_s2d1); -assign pyc_mux_629 = (pyc_comb_569 ? pe_int_s2_s2b1 : pyc_mux_628); -assign pyc_mux_630 = (pyc_comb_568 ? pe_int_s2_s2b1 : pyc_mux_629); -assign c3_out0_raw___pycircuit_v5_strip_domain___L63 = pyc_mux_627; -assign c3_out1_raw___pycircuit_v5_strip_domain___L63 = pyc_mux_630; -assign pyc_extract_631 = c3_out0_raw___pycircuit_v5_strip_domain___L63[18:0]; -assign c3_out0___pycircuit_v5_strip_domain___L64 = pyc_extract_631; -assign pe_int_out0__next = c3_out0___pycircuit_v5_strip_domain___L64; -assign pyc_extract_632 = c3_out1_raw___pycircuit_v5_strip_domain___L63[15:0]; -assign c3_out1___pycircuit_v5_strip_domain___L65 = pyc_extract_632; -assign pyc_comb_633 = pe_int_out0__next; -assign pyc_comb_634 = c3_out1___pycircuit_v5_strip_domain___L65; -assign pe_int_out1_hold = pyc_reg_635; -assign pyc_mux_636 = (pyc_comb_568 ? pe_int_out1_hold : pyc_comb_634); -assign pyc_mux_637 = (pyc_comb_560 ? pyc_mux_636 : pe_int_out1_hold); -assign out1_commit___pycircuit_v5_strip_domain___L67 = pyc_mux_637; -assign pe_int_out1__next = out1_commit___pycircuit_v5_strip_domain___L67; -assign pyc_comb_638 = out1_commit___pycircuit_v5_strip_domain___L67; -assign pyc_comb_639 = pe_int_out1__next; -assign pe_int_out1_hold__next = pyc_comb_638; +assign pyc_extract_502 = pyc_reg_501[0]; +assign pyc_extract_503 = pyc_reg_501[1]; +assign pyc_extract_504 = pyc_reg_501[2]; +assign pe_int_s2_is_2a = pyc_extract_502; +assign pe_int_s2_is_2b = pyc_extract_503; +assign pe_int_s2_is_2c = pyc_extract_504; +assign pyc_comb_505 = pe_int_s2_is_2a; +assign pyc_comb_506 = pe_int_s2_is_2b; +assign pyc_comb_507 = pe_int_s2_is_2c; +assign pe_int_s2_s2c1_hi = pyc_reg_519; +assign pyc_extract_520 = pe_int_s2_e1_a[0]; +assign pyc_zext_521 = {{1{1'b0}}, pyc_extract_520}; +assign pyc_extract_522 = pe_int_s2_e1_b0[0]; +assign pyc_zext_523 = {{1{1'b0}}, pyc_extract_522}; +assign pyc_add_524 = (pyc_zext_521 + pyc_zext_523); +assign pyc_extract_525 = pe_int_s2_e1_a[1]; +assign pyc_zext_526 = {{1{1'b0}}, pyc_extract_525}; +assign pyc_extract_527 = pe_int_s2_e1_b0[1]; +assign pyc_zext_528 = {{1{1'b0}}, pyc_extract_527}; +assign pyc_add_529 = (pyc_zext_526 + pyc_zext_528); +assign pyc_add_530 = (pe_int_s2_s2c0_lo + pe_int_s2_s2c0_lo); +assign pyc_add_531 = (pyc_add_530 + pyc_add_530); +assign pyc_eq_532 = (pyc_add_524 == pyc_comb_19); +assign pyc_eq_533 = (pyc_add_524 == pyc_comb_17); +assign pyc_mux_534 = (pyc_eq_533 ? pyc_add_530 : pyc_add_531); +assign pyc_mux_535 = (pyc_eq_532 ? pe_int_s2_s2c0_lo : pyc_mux_534); +assign pyc_add_536 = (pe_int_s2_s2c0_hi + pe_int_s2_s2c0_hi); +assign pyc_add_537 = (pyc_add_536 + pyc_add_536); +assign pyc_eq_538 = (pyc_add_529 == pyc_comb_19); +assign pyc_eq_539 = (pyc_add_529 == pyc_comb_17); +assign pyc_mux_540 = (pyc_eq_539 ? pyc_add_536 : pyc_add_537); +assign pyc_mux_541 = (pyc_eq_538 ? pe_int_s2_s2c0_hi : pyc_mux_540); +assign pyc_add_542 = (pyc_mux_535 + pyc_mux_541); +assign pyc_extract_543 = pe_int_s2_e1_b1[0]; +assign pyc_zext_544 = {{1{1'b0}}, pyc_extract_543}; +assign pyc_add_545 = (pyc_zext_521 + pyc_zext_544); +assign pyc_extract_546 = pe_int_s2_e1_b1[1]; +assign pyc_zext_547 = {{1{1'b0}}, pyc_extract_546}; +assign pyc_add_548 = (pyc_zext_526 + pyc_zext_547); +assign pyc_add_549 = (pe_int_s2_s2c1_lo + pe_int_s2_s2c1_lo); +assign pyc_add_550 = (pyc_add_549 + pyc_add_549); +assign pyc_eq_551 = (pyc_add_545 == pyc_comb_19); +assign pyc_eq_552 = (pyc_add_545 == pyc_comb_17); +assign pyc_mux_553 = (pyc_eq_552 ? pyc_add_549 : pyc_add_550); +assign pyc_mux_554 = (pyc_eq_551 ? pe_int_s2_s2c1_lo : pyc_mux_553); +assign pyc_add_555 = (pe_int_s2_s2c1_hi + pe_int_s2_s2c1_hi); +assign pyc_add_556 = (pyc_add_555 + pyc_add_555); +assign pyc_eq_557 = (pyc_add_548 == pyc_comb_19); +assign pyc_eq_558 = (pyc_add_548 == pyc_comb_17); +assign pyc_mux_559 = (pyc_eq_558 ? pyc_add_555 : pyc_add_556); +assign pyc_mux_560 = (pyc_eq_557 ? pe_int_s2_s2c1_hi : pyc_mux_559); +assign pyc_add_561 = (pyc_mux_554 + pyc_mux_560); +assign pyc_mux_562 = (pyc_comb_507 ? pyc_add_542 : pe_int_s2_s2d0); +assign pyc_mux_563 = (pyc_comb_506 ? pe_int_s2_s2b0 : pyc_mux_562); +assign pyc_mux_564 = (pyc_comb_505 ? pe_int_s2_s2a : pyc_mux_563); +assign pyc_mux_565 = (pyc_comb_507 ? pyc_add_561 : pe_int_s2_s2d1); +assign pyc_mux_566 = (pyc_comb_506 ? pe_int_s2_s2b1 : pyc_mux_565); +assign pyc_mux_567 = (pyc_comb_505 ? pe_int_s2_s2b1 : pyc_mux_566); +assign pyc_extract_568 = pyc_mux_564[18:0]; +assign pe_int_out0__next = pyc_extract_568; +assign pyc_extract_569 = pyc_mux_567[15:0]; +assign pyc_comb_570 = pe_int_out0__next; +assign pyc_comb_571 = pyc_extract_569; +assign pe_int_out1 = pyc_reg_572; +assign pyc_mux_573 = (pyc_comb_505 ? pe_int_out1 : pyc_comb_571); +assign pyc_mux_574 = (pyc_comb_497 ? pyc_mux_573 : pe_int_out1); +assign pyc_comb_575 = pe_int_out1; +assign pyc_comb_576 = pyc_mux_574; +assign pe_int_out1__next = pyc_comb_576; + +// --- Submodules +PE_INT_WALLACE_DOT8_TREE pe_int_s2a_wallace ( + .clk(clk), + .rst(rst), + .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2a_0), + .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2a_1), + .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2a_2), + .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2a_3), + .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2a_4), + .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2a_5), + .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2a_6), + .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2a_7), + .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_485) +); +PE_INT_WALLACE_DOT8_TREE pe_int_s2b0_wallace ( + .clk(clk), + .rst(rst), + .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2b0_0), + .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2b0_1), + .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2b0_2), + .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2b0_3), + .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2b0_4), + .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2b0_5), + .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2b0_6), + .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2b0_7), + .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_486) +); +PE_INT_WALLACE_DOT8_TREE pe_int_s2b1_wallace ( + .clk(clk), + .rst(rst), + .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2b1_0), + .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2b1_1), + .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2b1_2), + .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2b1_3), + .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2b1_4), + .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2b1_5), + .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2b1_6), + .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2b1_7), + .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_487) +); +PE_INT_WALLACE_DOT8_TREE pe_int_s2d0_wallace ( + .clk(clk), + .rst(rst), + .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2d0_0), + .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2d0_1), + .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2d0_2), + .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2d0_3), + .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2d0_4), + .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2d0_5), + .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2d0_6), + .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2d0_7), + .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_488) +); +PE_INT_WALLACE_DOT8_TREE pe_int_s2d1_wallace ( + .clk(clk), + .rst(rst), + .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2d1_0), + .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2d1_1), + .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2d1_2), + .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2d1_3), + .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2d1_4), + .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2d1_5), + .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2d1_6), + .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2d1_7), + .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_489) +); +PE_INT_WALLACE_DOT8_TREE pe_int_s2c0_lo_wallace ( + .clk(clk), + .rst(rst), + .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2c0_0), + .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2c0_1), + .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2c0_2), + .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2c0_3), + .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2c0_4), + .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2c0_5), + .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2c0_6), + .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2c0_7), + .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_490) +); +PE_INT_WALLACE_DOT8_TREE pe_int_s2c0_hi_wallace ( + .clk(clk), + .rst(rst), + .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2c0_8), + .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2c0_9), + .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2c0_10), + .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2c0_11), + .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2c0_12), + .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2c0_13), + .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2c0_14), + .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2c0_15), + .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_491) +); +PE_INT_WALLACE_DOT8_TREE pe_int_s2c1_lo_wallace ( + .clk(clk), + .rst(rst), + .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2c1_0), + .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2c1_1), + .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2c1_2), + .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2c1_3), + .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2c1_4), + .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2c1_5), + .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2c1_6), + .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2c1_7), + .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_492) +); +PE_INT_WALLACE_DOT8_TREE pe_int_s2c1_hi_wallace ( + .clk(clk), + .rst(rst), + .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2c1_8), + .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2c1_9), + .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2c1_10), + .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2c1_11), + .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2c1_12), + .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2c1_13), + .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2c1_14), + .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2c1_15), + .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_493) +); // --- Sequential primitives -pyc_reg #(.WIDTH(1)) pyc_reg_34_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_34_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1660,7 +1629,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_34_inst ( .init(pyc_comb_22), .q(pyc_reg_34) ); -pyc_reg #(.WIDTH(1)) pyc_reg_36_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_36_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1668,7 +1637,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_36_inst ( .init(pyc_comb_22), .q(pyc_reg_36) ); -pyc_reg #(.WIDTH(1)) pyc_reg_38_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_38_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1676,7 +1645,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_38_inst ( .init(pyc_comb_22), .q(pyc_reg_38) ); -pyc_reg #(.WIDTH(1)) pyc_reg_398_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_398_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1684,7 +1653,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_398_inst ( .init(pyc_comb_22), .q(pyc_reg_398) ); -pyc_reg #(.WIDTH(1)) pyc_reg_40_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_40_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1692,7 +1661,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_40_inst ( .init(pyc_comb_22), .q(pyc_reg_40) ); -pyc_reg #(.WIDTH(1)) pyc_reg_400_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_400_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1700,7 +1669,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_400_inst ( .init(pyc_comb_22), .q(pyc_reg_400) ); -pyc_reg #(.WIDTH(1)) pyc_reg_402_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_402_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1708,7 +1677,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_402_inst ( .init(pyc_comb_22), .q(pyc_reg_402) ); -pyc_reg #(.WIDTH(1)) pyc_reg_404_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_404_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1716,7 +1685,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_404_inst ( .init(pyc_comb_22), .q(pyc_reg_404) ); -pyc_reg #(.WIDTH(1)) pyc_reg_406_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_406_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1724,7 +1693,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_406_inst ( .init(pyc_comb_22), .q(pyc_reg_406) ); -pyc_reg #(.WIDTH(2)) pyc_reg_407_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_407_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1732,7 +1701,7 @@ pyc_reg #(.WIDTH(2)) pyc_reg_407_inst ( .init(pyc_comb_19), .q(pyc_reg_407) ); -pyc_reg #(.WIDTH(2)) pyc_reg_409_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_409_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1740,7 +1709,7 @@ pyc_reg #(.WIDTH(2)) pyc_reg_409_inst ( .init(pyc_comb_19), .q(pyc_reg_409) ); -pyc_reg #(.WIDTH(2)) pyc_reg_411_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_411_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1748,7 +1717,7 @@ pyc_reg #(.WIDTH(2)) pyc_reg_411_inst ( .init(pyc_comb_19), .q(pyc_reg_411) ); -pyc_reg #(.WIDTH(32)) pyc_reg_413_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_413_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1756,7 +1725,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_413_inst ( .init(pyc_comb_18), .q(pyc_reg_413) ); -pyc_reg #(.WIDTH(32)) pyc_reg_414_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_414_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1764,7 +1733,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_414_inst ( .init(pyc_comb_18), .q(pyc_reg_414) ); -pyc_reg #(.WIDTH(32)) pyc_reg_415_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_415_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1772,7 +1741,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_415_inst ( .init(pyc_comb_18), .q(pyc_reg_415) ); -pyc_reg #(.WIDTH(32)) pyc_reg_416_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_416_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1780,7 +1749,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_416_inst ( .init(pyc_comb_18), .q(pyc_reg_416) ); -pyc_reg #(.WIDTH(32)) pyc_reg_417_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_417_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1788,7 +1757,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_417_inst ( .init(pyc_comb_18), .q(pyc_reg_417) ); -pyc_reg #(.WIDTH(32)) pyc_reg_418_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_418_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1796,7 +1765,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_418_inst ( .init(pyc_comb_18), .q(pyc_reg_418) ); -pyc_reg #(.WIDTH(32)) pyc_reg_419_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_419_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1804,7 +1773,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_419_inst ( .init(pyc_comb_18), .q(pyc_reg_419) ); -pyc_reg #(.WIDTH(1)) pyc_reg_42_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_42_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1812,7 +1781,7 @@ pyc_reg #(.WIDTH(1)) pyc_reg_42_inst ( .init(pyc_comb_22), .q(pyc_reg_42) ); -pyc_reg #(.WIDTH(32)) pyc_reg_420_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_420_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1820,7 +1789,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_420_inst ( .init(pyc_comb_18), .q(pyc_reg_420) ); -pyc_reg #(.WIDTH(32)) pyc_reg_421_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_421_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1828,7 +1797,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_421_inst ( .init(pyc_comb_18), .q(pyc_reg_421) ); -pyc_reg #(.WIDTH(32)) pyc_reg_422_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_422_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1836,7 +1805,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_422_inst ( .init(pyc_comb_18), .q(pyc_reg_422) ); -pyc_reg #(.WIDTH(32)) pyc_reg_423_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_423_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1844,7 +1813,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_423_inst ( .init(pyc_comb_18), .q(pyc_reg_423) ); -pyc_reg #(.WIDTH(32)) pyc_reg_424_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_424_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1852,7 +1821,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_424_inst ( .init(pyc_comb_18), .q(pyc_reg_424) ); -pyc_reg #(.WIDTH(32)) pyc_reg_425_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_425_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1860,7 +1829,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_425_inst ( .init(pyc_comb_18), .q(pyc_reg_425) ); -pyc_reg #(.WIDTH(32)) pyc_reg_426_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_426_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1868,7 +1837,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_426_inst ( .init(pyc_comb_18), .q(pyc_reg_426) ); -pyc_reg #(.WIDTH(32)) pyc_reg_427_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_427_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1876,7 +1845,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_427_inst ( .init(pyc_comb_18), .q(pyc_reg_427) ); -pyc_reg #(.WIDTH(32)) pyc_reg_428_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_428_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1884,7 +1853,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_428_inst ( .init(pyc_comb_18), .q(pyc_reg_428) ); -pyc_reg #(.WIDTH(32)) pyc_reg_429_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_429_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1892,7 +1861,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_429_inst ( .init(pyc_comb_18), .q(pyc_reg_429) ); -pyc_reg #(.WIDTH(32)) pyc_reg_430_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_430_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1900,7 +1869,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_430_inst ( .init(pyc_comb_18), .q(pyc_reg_430) ); -pyc_reg #(.WIDTH(32)) pyc_reg_431_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_431_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1908,7 +1877,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_431_inst ( .init(pyc_comb_18), .q(pyc_reg_431) ); -pyc_reg #(.WIDTH(32)) pyc_reg_432_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_432_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1916,7 +1885,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_432_inst ( .init(pyc_comb_18), .q(pyc_reg_432) ); -pyc_reg #(.WIDTH(32)) pyc_reg_433_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_433_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1924,7 +1893,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_433_inst ( .init(pyc_comb_18), .q(pyc_reg_433) ); -pyc_reg #(.WIDTH(32)) pyc_reg_434_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_434_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1932,7 +1901,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_434_inst ( .init(pyc_comb_18), .q(pyc_reg_434) ); -pyc_reg #(.WIDTH(32)) pyc_reg_435_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_435_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1940,7 +1909,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_435_inst ( .init(pyc_comb_18), .q(pyc_reg_435) ); -pyc_reg #(.WIDTH(32)) pyc_reg_436_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_436_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1948,7 +1917,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_436_inst ( .init(pyc_comb_18), .q(pyc_reg_436) ); -pyc_reg #(.WIDTH(32)) pyc_reg_437_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_437_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1956,7 +1925,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_437_inst ( .init(pyc_comb_18), .q(pyc_reg_437) ); -pyc_reg #(.WIDTH(32)) pyc_reg_438_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_438_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1964,7 +1933,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_438_inst ( .init(pyc_comb_18), .q(pyc_reg_438) ); -pyc_reg #(.WIDTH(32)) pyc_reg_439_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_439_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1972,7 +1941,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_439_inst ( .init(pyc_comb_18), .q(pyc_reg_439) ); -pyc_reg #(.WIDTH(80)) pyc_reg_44_inst ( +PYC_REG #(.WIDTH(80)) pyc_reg_44_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1980,7 +1949,7 @@ pyc_reg #(.WIDTH(80)) pyc_reg_44_inst ( .init(pyc_comb_20), .q(pyc_reg_44) ); -pyc_reg #(.WIDTH(32)) pyc_reg_440_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_440_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1988,7 +1957,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_440_inst ( .init(pyc_comb_18), .q(pyc_reg_440) ); -pyc_reg #(.WIDTH(32)) pyc_reg_441_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_441_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -1996,7 +1965,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_441_inst ( .init(pyc_comb_18), .q(pyc_reg_441) ); -pyc_reg #(.WIDTH(32)) pyc_reg_442_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_442_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2004,7 +1973,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_442_inst ( .init(pyc_comb_18), .q(pyc_reg_442) ); -pyc_reg #(.WIDTH(32)) pyc_reg_443_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_443_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2012,7 +1981,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_443_inst ( .init(pyc_comb_18), .q(pyc_reg_443) ); -pyc_reg #(.WIDTH(32)) pyc_reg_444_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_444_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2020,7 +1989,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_444_inst ( .init(pyc_comb_18), .q(pyc_reg_444) ); -pyc_reg #(.WIDTH(32)) pyc_reg_445_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_445_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2028,7 +1997,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_445_inst ( .init(pyc_comb_18), .q(pyc_reg_445) ); -pyc_reg #(.WIDTH(32)) pyc_reg_446_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_446_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2036,7 +2005,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_446_inst ( .init(pyc_comb_18), .q(pyc_reg_446) ); -pyc_reg #(.WIDTH(32)) pyc_reg_447_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_447_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2044,7 +2013,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_447_inst ( .init(pyc_comb_18), .q(pyc_reg_447) ); -pyc_reg #(.WIDTH(32)) pyc_reg_448_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_448_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2052,7 +2021,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_448_inst ( .init(pyc_comb_18), .q(pyc_reg_448) ); -pyc_reg #(.WIDTH(32)) pyc_reg_449_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_449_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2060,7 +2029,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_449_inst ( .init(pyc_comb_18), .q(pyc_reg_449) ); -pyc_reg #(.WIDTH(80)) pyc_reg_45_inst ( +PYC_REG #(.WIDTH(80)) pyc_reg_45_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2068,7 +2037,7 @@ pyc_reg #(.WIDTH(80)) pyc_reg_45_inst ( .init(pyc_comb_20), .q(pyc_reg_45) ); -pyc_reg #(.WIDTH(32)) pyc_reg_450_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_450_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2076,7 +2045,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_450_inst ( .init(pyc_comb_18), .q(pyc_reg_450) ); -pyc_reg #(.WIDTH(32)) pyc_reg_451_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_451_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2084,7 +2053,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_451_inst ( .init(pyc_comb_18), .q(pyc_reg_451) ); -pyc_reg #(.WIDTH(32)) pyc_reg_452_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_452_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2092,7 +2061,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_452_inst ( .init(pyc_comb_18), .q(pyc_reg_452) ); -pyc_reg #(.WIDTH(32)) pyc_reg_453_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_453_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2100,7 +2069,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_453_inst ( .init(pyc_comb_18), .q(pyc_reg_453) ); -pyc_reg #(.WIDTH(32)) pyc_reg_454_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_454_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2108,7 +2077,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_454_inst ( .init(pyc_comb_18), .q(pyc_reg_454) ); -pyc_reg #(.WIDTH(32)) pyc_reg_455_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_455_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2116,7 +2085,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_455_inst ( .init(pyc_comb_18), .q(pyc_reg_455) ); -pyc_reg #(.WIDTH(32)) pyc_reg_456_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_456_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2124,7 +2093,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_456_inst ( .init(pyc_comb_18), .q(pyc_reg_456) ); -pyc_reg #(.WIDTH(32)) pyc_reg_457_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_457_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2132,7 +2101,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_457_inst ( .init(pyc_comb_18), .q(pyc_reg_457) ); -pyc_reg #(.WIDTH(32)) pyc_reg_458_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_458_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2140,7 +2109,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_458_inst ( .init(pyc_comb_18), .q(pyc_reg_458) ); -pyc_reg #(.WIDTH(32)) pyc_reg_459_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_459_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2148,7 +2117,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_459_inst ( .init(pyc_comb_18), .q(pyc_reg_459) ); -pyc_reg #(.WIDTH(80)) pyc_reg_46_inst ( +PYC_REG #(.WIDTH(80)) pyc_reg_46_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2156,7 +2125,7 @@ pyc_reg #(.WIDTH(80)) pyc_reg_46_inst ( .init(pyc_comb_20), .q(pyc_reg_46) ); -pyc_reg #(.WIDTH(32)) pyc_reg_460_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_460_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2164,7 +2133,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_460_inst ( .init(pyc_comb_18), .q(pyc_reg_460) ); -pyc_reg #(.WIDTH(32)) pyc_reg_461_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_461_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2172,7 +2141,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_461_inst ( .init(pyc_comb_18), .q(pyc_reg_461) ); -pyc_reg #(.WIDTH(32)) pyc_reg_462_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_462_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2180,7 +2149,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_462_inst ( .init(pyc_comb_18), .q(pyc_reg_462) ); -pyc_reg #(.WIDTH(32)) pyc_reg_463_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_463_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2188,7 +2157,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_463_inst ( .init(pyc_comb_18), .q(pyc_reg_463) ); -pyc_reg #(.WIDTH(32)) pyc_reg_464_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_464_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2196,7 +2165,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_464_inst ( .init(pyc_comb_18), .q(pyc_reg_464) ); -pyc_reg #(.WIDTH(32)) pyc_reg_465_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_465_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2204,7 +2173,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_465_inst ( .init(pyc_comb_18), .q(pyc_reg_465) ); -pyc_reg #(.WIDTH(32)) pyc_reg_466_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_466_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2212,7 +2181,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_466_inst ( .init(pyc_comb_18), .q(pyc_reg_466) ); -pyc_reg #(.WIDTH(32)) pyc_reg_467_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_467_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2220,7 +2189,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_467_inst ( .init(pyc_comb_18), .q(pyc_reg_467) ); -pyc_reg #(.WIDTH(32)) pyc_reg_468_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_468_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2228,7 +2197,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_468_inst ( .init(pyc_comb_18), .q(pyc_reg_468) ); -pyc_reg #(.WIDTH(32)) pyc_reg_469_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_469_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2236,7 +2205,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_469_inst ( .init(pyc_comb_18), .q(pyc_reg_469) ); -pyc_reg #(.WIDTH(2)) pyc_reg_47_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_47_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2244,7 +2213,7 @@ pyc_reg #(.WIDTH(2)) pyc_reg_47_inst ( .init(pyc_comb_19), .q(pyc_reg_47) ); -pyc_reg #(.WIDTH(32)) pyc_reg_470_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_470_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2252,7 +2221,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_470_inst ( .init(pyc_comb_18), .q(pyc_reg_470) ); -pyc_reg #(.WIDTH(32)) pyc_reg_471_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_471_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2260,7 +2229,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_471_inst ( .init(pyc_comb_18), .q(pyc_reg_471) ); -pyc_reg #(.WIDTH(32)) pyc_reg_472_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_472_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2268,7 +2237,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_472_inst ( .init(pyc_comb_18), .q(pyc_reg_472) ); -pyc_reg #(.WIDTH(32)) pyc_reg_473_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_473_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2276,7 +2245,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_473_inst ( .init(pyc_comb_18), .q(pyc_reg_473) ); -pyc_reg #(.WIDTH(32)) pyc_reg_474_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_474_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2284,7 +2253,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_474_inst ( .init(pyc_comb_18), .q(pyc_reg_474) ); -pyc_reg #(.WIDTH(32)) pyc_reg_475_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_475_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2292,7 +2261,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_475_inst ( .init(pyc_comb_18), .q(pyc_reg_475) ); -pyc_reg #(.WIDTH(32)) pyc_reg_476_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_476_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2300,7 +2269,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_476_inst ( .init(pyc_comb_18), .q(pyc_reg_476) ); -pyc_reg #(.WIDTH(32)) pyc_reg_477_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_477_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2308,7 +2277,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_477_inst ( .init(pyc_comb_18), .q(pyc_reg_477) ); -pyc_reg #(.WIDTH(32)) pyc_reg_478_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_478_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2316,7 +2285,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_478_inst ( .init(pyc_comb_18), .q(pyc_reg_478) ); -pyc_reg #(.WIDTH(32)) pyc_reg_479_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_479_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2324,7 +2293,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_479_inst ( .init(pyc_comb_18), .q(pyc_reg_479) ); -pyc_reg #(.WIDTH(32)) pyc_reg_480_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_480_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2332,7 +2301,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_480_inst ( .init(pyc_comb_18), .q(pyc_reg_480) ); -pyc_reg #(.WIDTH(32)) pyc_reg_481_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_481_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2340,7 +2309,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_481_inst ( .init(pyc_comb_18), .q(pyc_reg_481) ); -pyc_reg #(.WIDTH(32)) pyc_reg_482_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_482_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2348,7 +2317,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_482_inst ( .init(pyc_comb_18), .q(pyc_reg_482) ); -pyc_reg #(.WIDTH(32)) pyc_reg_483_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_483_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2356,7 +2325,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_483_inst ( .init(pyc_comb_18), .q(pyc_reg_483) ); -pyc_reg #(.WIDTH(32)) pyc_reg_484_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_484_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2364,7 +2333,7 @@ pyc_reg #(.WIDTH(32)) pyc_reg_484_inst ( .init(pyc_comb_18), .q(pyc_reg_484) ); -pyc_reg #(.WIDTH(2)) pyc_reg_49_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_49_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), @@ -2372,162 +2341,154 @@ pyc_reg #(.WIDTH(2)) pyc_reg_49_inst ( .init(pyc_comb_19), .q(pyc_reg_49) ); -pyc_reg #(.WIDTH(2)) pyc_reg_51_inst ( - .clk(clk), - .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_23), - .init(pyc_comb_19), - .q(pyc_reg_51) -); -pyc_reg #(.WIDTH(1)) pyc_reg_557_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_494_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pyc_comb_399), .init(pyc_comb_22), - .q(pyc_reg_557) + .q(pyc_reg_494) ); -pyc_reg #(.WIDTH(3)) pyc_reg_564_inst ( +PYC_REG #(.WIDTH(3)) pyc_reg_501_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_562), - .init(pyc_comb_563), - .q(pyc_reg_564) + .d(pyc_comb_499), + .init(pyc_comb_500), + .q(pyc_reg_501) ); -pyc_reg #(.WIDTH(2)) pyc_reg_571_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_508_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pyc_comb_408), .init(pyc_comb_19), - .q(pyc_reg_571) + .q(pyc_reg_508) ); -pyc_reg #(.WIDTH(2)) pyc_reg_572_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_509_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pyc_comb_410), .init(pyc_comb_19), - .q(pyc_reg_572) + .q(pyc_reg_509) ); -pyc_reg #(.WIDTH(2)) pyc_reg_573_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_51_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_23), + .init(pyc_comb_19), + .q(pyc_reg_51) +); +PYC_REG #(.WIDTH(2)) pyc_reg_510_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pyc_comb_412), .init(pyc_comb_19), - .q(pyc_reg_573) + .q(pyc_reg_510) ); -pyc_reg #(.WIDTH(32)) pyc_reg_574_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_511_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_548), + .d(pe_int_s2_s2a__next), .init(pyc_comb_18), - .q(pyc_reg_574) + .q(pyc_reg_511) ); -pyc_reg #(.WIDTH(32)) pyc_reg_575_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_512_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_549), + .d(pe_int_s2_s2b0__next), .init(pyc_comb_18), - .q(pyc_reg_575) + .q(pyc_reg_512) ); -pyc_reg #(.WIDTH(32)) pyc_reg_576_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_513_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_550), + .d(pe_int_s2_s2b1__next), .init(pyc_comb_18), - .q(pyc_reg_576) + .q(pyc_reg_513) ); -pyc_reg #(.WIDTH(32)) pyc_reg_577_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_514_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_551), + .d(pe_int_s2_s2d0__next), .init(pyc_comb_18), - .q(pyc_reg_577) + .q(pyc_reg_514) ); -pyc_reg #(.WIDTH(32)) pyc_reg_578_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_515_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_552), + .d(pe_int_s2_s2d1__next), .init(pyc_comb_18), - .q(pyc_reg_578) + .q(pyc_reg_515) ); -pyc_reg #(.WIDTH(32)) pyc_reg_579_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_516_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_553), + .d(pe_int_s2_s2c0_lo__next), .init(pyc_comb_18), - .q(pyc_reg_579) + .q(pyc_reg_516) ); -pyc_reg #(.WIDTH(32)) pyc_reg_580_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_517_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_554), + .d(pe_int_s2_s2c0_hi__next), .init(pyc_comb_18), - .q(pyc_reg_580) + .q(pyc_reg_517) ); -pyc_reg #(.WIDTH(32)) pyc_reg_581_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_518_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_555), + .d(pe_int_s2_s2c1_lo__next), .init(pyc_comb_18), - .q(pyc_reg_581) + .q(pyc_reg_518) ); -pyc_reg #(.WIDTH(32)) pyc_reg_582_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_519_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_556), + .d(pe_int_s2_s2c1_hi__next), .init(pyc_comb_18), - .q(pyc_reg_582) + .q(pyc_reg_519) ); -pyc_reg #(.WIDTH(16)) pyc_reg_635_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_572_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pe_int_out1_hold__next), + .d(pe_int_out1__next), .init(pyc_comb_16), - .q(pyc_reg_635) + .q(pyc_reg_572) ); -pyc_reg #(.WIDTH(1)) pyc_reg_640_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_577_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_561), + .d(pyc_comb_498), .init(pyc_comb_22), - .q(pyc_reg_640) + .q(pyc_reg_577) ); -pyc_reg #(.WIDTH(19)) pyc_reg_641_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_578_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_633), + .d(pyc_comb_570), .init(pyc_comb_15), - .q(pyc_reg_641) -); -pyc_reg #(.WIDTH(16)) pyc_reg_642_inst ( - .clk(clk), - .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_639), - .init(pyc_comb_16), - .q(pyc_reg_642) + .q(pyc_reg_578) ); assign vld_out = pe_int_out_vld; assign out0 = pe_int_out0; -assign out1 = pe_int_out1; +assign out1 = pyc_comb_575; endmodule diff --git a/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree.v b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree.v new file mode 100644 index 0000000..7f8e2b3 --- /dev/null +++ b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree.v @@ -0,0 +1,3130 @@ +// Generated by pycc (pyCircuit) +// Module: PE_INT_WALLACE_DOT8_TREE + +module PE_INT_WALLACE_DOT8_TREE ( + input clk, + input rst, + input [31:0] PE_INT_WALLACE_DOT8_TREE_in0, + input [31:0] PE_INT_WALLACE_DOT8_TREE_in1, + input [31:0] PE_INT_WALLACE_DOT8_TREE_in2, + input [31:0] PE_INT_WALLACE_DOT8_TREE_in3, + input [31:0] PE_INT_WALLACE_DOT8_TREE_in4, + input [31:0] PE_INT_WALLACE_DOT8_TREE_in5, + input [31:0] PE_INT_WALLACE_DOT8_TREE_in6, + input [31:0] PE_INT_WALLACE_DOT8_TREE_in7, + output [31:0] PE_INT_WALLACE_DOT8_TREE_sum +); + +wire [31:0] pyc_add_1552; // op=pyc.add +wire pyc_and_10; // op=pyc.and +wire pyc_and_100; // op=pyc.and +wire pyc_and_1003; // op=pyc.and +wire pyc_and_1004; // op=pyc.and +wire pyc_and_1006; // op=pyc.and +wire pyc_and_101; // op=pyc.and +wire pyc_and_1013; // op=pyc.and +wire pyc_and_1014; // op=pyc.and +wire pyc_and_1016; // op=pyc.and +wire pyc_and_1021; // op=pyc.and +wire pyc_and_1022; // op=pyc.and +wire pyc_and_1024; // op=pyc.and +wire pyc_and_103; // op=pyc.and +wire pyc_and_1031; // op=pyc.and +wire pyc_and_1032; // op=pyc.and +wire pyc_and_1034; // op=pyc.and +wire pyc_and_1039; // op=pyc.and +wire pyc_and_1040; // op=pyc.and +wire pyc_and_1042; // op=pyc.and +wire pyc_and_1049; // op=pyc.and +wire pyc_and_1050; // op=pyc.and +wire pyc_and_1052; // op=pyc.and +wire pyc_and_1057; // op=pyc.and +wire pyc_and_1058; // op=pyc.and +wire pyc_and_1060; // op=pyc.and +wire pyc_and_1067; // op=pyc.and +wire pyc_and_1068; // op=pyc.and +wire pyc_and_1070; // op=pyc.and +wire pyc_and_1075; // op=pyc.and +wire pyc_and_1076; // op=pyc.and +wire pyc_and_1078; // op=pyc.and +wire pyc_and_1085; // op=pyc.and +wire pyc_and_1086; // op=pyc.and +wire pyc_and_1088; // op=pyc.and +wire pyc_and_1093; // op=pyc.and +wire pyc_and_1094; // op=pyc.and +wire pyc_and_1096; // op=pyc.and +wire pyc_and_110; // op=pyc.and +wire pyc_and_1103; // op=pyc.and +wire pyc_and_1104; // op=pyc.and +wire pyc_and_1106; // op=pyc.and +wire pyc_and_111; // op=pyc.and +wire pyc_and_1111; // op=pyc.and +wire pyc_and_1112; // op=pyc.and +wire pyc_and_1114; // op=pyc.and +wire pyc_and_1125; // op=pyc.and +wire pyc_and_1128; // op=pyc.and +wire pyc_and_1129; // op=pyc.and +wire pyc_and_113; // op=pyc.and +wire pyc_and_1131; // op=pyc.and +wire pyc_and_1135; // op=pyc.and +wire pyc_and_1136; // op=pyc.and +wire pyc_and_1138; // op=pyc.and +wire pyc_and_1142; // op=pyc.and +wire pyc_and_1143; // op=pyc.and +wire pyc_and_1145; // op=pyc.and +wire pyc_and_1149; // op=pyc.and +wire pyc_and_1150; // op=pyc.and +wire pyc_and_1152; // op=pyc.and +wire pyc_and_1156; // op=pyc.and +wire pyc_and_1157; // op=pyc.and +wire pyc_and_1159; // op=pyc.and +wire pyc_and_1163; // op=pyc.and +wire pyc_and_1164; // op=pyc.and +wire pyc_and_1166; // op=pyc.and +wire pyc_and_1170; // op=pyc.and +wire pyc_and_1171; // op=pyc.and +wire pyc_and_1173; // op=pyc.and +wire pyc_and_1177; // op=pyc.and +wire pyc_and_1178; // op=pyc.and +wire pyc_and_118; // op=pyc.and +wire pyc_and_1180; // op=pyc.and +wire pyc_and_1184; // op=pyc.and +wire pyc_and_1185; // op=pyc.and +wire pyc_and_1187; // op=pyc.and +wire pyc_and_119; // op=pyc.and +wire pyc_and_1191; // op=pyc.and +wire pyc_and_1192; // op=pyc.and +wire pyc_and_1194; // op=pyc.and +wire pyc_and_1198; // op=pyc.and +wire pyc_and_1199; // op=pyc.and +wire pyc_and_1201; // op=pyc.and +wire pyc_and_1205; // op=pyc.and +wire pyc_and_1206; // op=pyc.and +wire pyc_and_1208; // op=pyc.and +wire pyc_and_121; // op=pyc.and +wire pyc_and_1212; // op=pyc.and +wire pyc_and_1213; // op=pyc.and +wire pyc_and_1215; // op=pyc.and +wire pyc_and_1219; // op=pyc.and +wire pyc_and_1220; // op=pyc.and +wire pyc_and_1222; // op=pyc.and +wire pyc_and_1226; // op=pyc.and +wire pyc_and_1227; // op=pyc.and +wire pyc_and_1229; // op=pyc.and +wire pyc_and_1233; // op=pyc.and +wire pyc_and_1234; // op=pyc.and +wire pyc_and_1236; // op=pyc.and +wire pyc_and_1240; // op=pyc.and +wire pyc_and_1241; // op=pyc.and +wire pyc_and_1243; // op=pyc.and +wire pyc_and_1247; // op=pyc.and +wire pyc_and_1248; // op=pyc.and +wire pyc_and_1250; // op=pyc.and +wire pyc_and_1254; // op=pyc.and +wire pyc_and_1255; // op=pyc.and +wire pyc_and_1257; // op=pyc.and +wire pyc_and_1261; // op=pyc.and +wire pyc_and_1262; // op=pyc.and +wire pyc_and_1264; // op=pyc.and +wire pyc_and_1268; // op=pyc.and +wire pyc_and_1269; // op=pyc.and +wire pyc_and_1271; // op=pyc.and +wire pyc_and_1275; // op=pyc.and +wire pyc_and_1276; // op=pyc.and +wire pyc_and_1278; // op=pyc.and +wire pyc_and_128; // op=pyc.and +wire pyc_and_1282; // op=pyc.and +wire pyc_and_1283; // op=pyc.and +wire pyc_and_1285; // op=pyc.and +wire pyc_and_1289; // op=pyc.and +wire pyc_and_129; // op=pyc.and +wire pyc_and_1290; // op=pyc.and +wire pyc_and_1292; // op=pyc.and +wire pyc_and_1296; // op=pyc.and +wire pyc_and_1297; // op=pyc.and +wire pyc_and_1299; // op=pyc.and +wire pyc_and_1303; // op=pyc.and +wire pyc_and_1304; // op=pyc.and +wire pyc_and_1306; // op=pyc.and +wire pyc_and_131; // op=pyc.and +wire pyc_and_1310; // op=pyc.and +wire pyc_and_1311; // op=pyc.and +wire pyc_and_1313; // op=pyc.and +wire pyc_and_1317; // op=pyc.and +wire pyc_and_1318; // op=pyc.and +wire pyc_and_1320; // op=pyc.and +wire pyc_and_1324; // op=pyc.and +wire pyc_and_1325; // op=pyc.and +wire pyc_and_1327; // op=pyc.and +wire pyc_and_1331; // op=pyc.and +wire pyc_and_1332; // op=pyc.and +wire pyc_and_1334; // op=pyc.and +wire pyc_and_1338; // op=pyc.and +wire pyc_and_1339; // op=pyc.and +wire pyc_and_1341; // op=pyc.and +wire pyc_and_1345; // op=pyc.and +wire pyc_and_1346; // op=pyc.and +wire pyc_and_1348; // op=pyc.and +wire pyc_and_1352; // op=pyc.and +wire pyc_and_1353; // op=pyc.and +wire pyc_and_1355; // op=pyc.and +wire pyc_and_1359; // op=pyc.and +wire pyc_and_136; // op=pyc.and +wire pyc_and_1360; // op=pyc.and +wire pyc_and_1362; // op=pyc.and +wire pyc_and_1366; // op=pyc.and +wire pyc_and_1367; // op=pyc.and +wire pyc_and_1369; // op=pyc.and +wire pyc_and_137; // op=pyc.and +wire pyc_and_1373; // op=pyc.and +wire pyc_and_1374; // op=pyc.and +wire pyc_and_1376; // op=pyc.and +wire pyc_and_1380; // op=pyc.and +wire pyc_and_1381; // op=pyc.and +wire pyc_and_1383; // op=pyc.and +wire pyc_and_1387; // op=pyc.and +wire pyc_and_1388; // op=pyc.and +wire pyc_and_139; // op=pyc.and +wire pyc_and_1390; // op=pyc.and +wire pyc_and_1394; // op=pyc.and +wire pyc_and_1395; // op=pyc.and +wire pyc_and_1397; // op=pyc.and +wire pyc_and_14; // op=pyc.and +wire pyc_and_1401; // op=pyc.and +wire pyc_and_1402; // op=pyc.and +wire pyc_and_1404; // op=pyc.and +wire pyc_and_1408; // op=pyc.and +wire pyc_and_1409; // op=pyc.and +wire pyc_and_1411; // op=pyc.and +wire pyc_and_1415; // op=pyc.and +wire pyc_and_1416; // op=pyc.and +wire pyc_and_1418; // op=pyc.and +wire pyc_and_1422; // op=pyc.and +wire pyc_and_1423; // op=pyc.and +wire pyc_and_1425; // op=pyc.and +wire pyc_and_1429; // op=pyc.and +wire pyc_and_1430; // op=pyc.and +wire pyc_and_1432; // op=pyc.and +wire pyc_and_1436; // op=pyc.and +wire pyc_and_1437; // op=pyc.and +wire pyc_and_1439; // op=pyc.and +wire pyc_and_1443; // op=pyc.and +wire pyc_and_1444; // op=pyc.and +wire pyc_and_1446; // op=pyc.and +wire pyc_and_1450; // op=pyc.and +wire pyc_and_1451; // op=pyc.and +wire pyc_and_1453; // op=pyc.and +wire pyc_and_1457; // op=pyc.and +wire pyc_and_1458; // op=pyc.and +wire pyc_and_146; // op=pyc.and +wire pyc_and_1460; // op=pyc.and +wire pyc_and_1464; // op=pyc.and +wire pyc_and_1465; // op=pyc.and +wire pyc_and_1467; // op=pyc.and +wire pyc_and_147; // op=pyc.and +wire pyc_and_1471; // op=pyc.and +wire pyc_and_1472; // op=pyc.and +wire pyc_and_1474; // op=pyc.and +wire pyc_and_1478; // op=pyc.and +wire pyc_and_1479; // op=pyc.and +wire pyc_and_1481; // op=pyc.and +wire pyc_and_1485; // op=pyc.and +wire pyc_and_1486; // op=pyc.and +wire pyc_and_1488; // op=pyc.and +wire pyc_and_149; // op=pyc.and +wire pyc_and_1492; // op=pyc.and +wire pyc_and_1493; // op=pyc.and +wire pyc_and_1495; // op=pyc.and +wire pyc_and_1499; // op=pyc.and +wire pyc_and_1500; // op=pyc.and +wire pyc_and_1502; // op=pyc.and +wire pyc_and_1506; // op=pyc.and +wire pyc_and_1507; // op=pyc.and +wire pyc_and_1509; // op=pyc.and +wire pyc_and_1513; // op=pyc.and +wire pyc_and_1514; // op=pyc.and +wire pyc_and_1516; // op=pyc.and +wire pyc_and_1520; // op=pyc.and +wire pyc_and_1521; // op=pyc.and +wire pyc_and_1523; // op=pyc.and +wire pyc_and_1527; // op=pyc.and +wire pyc_and_1528; // op=pyc.and +wire pyc_and_1530; // op=pyc.and +wire pyc_and_1534; // op=pyc.and +wire pyc_and_1535; // op=pyc.and +wire pyc_and_1537; // op=pyc.and +wire pyc_and_154; // op=pyc.and +wire pyc_and_1541; // op=pyc.and +wire pyc_and_1542; // op=pyc.and +wire pyc_and_1544; // op=pyc.and +wire pyc_and_155; // op=pyc.and +wire pyc_and_157; // op=pyc.and +wire pyc_and_164; // op=pyc.and +wire pyc_and_165; // op=pyc.and +wire pyc_and_167; // op=pyc.and +wire pyc_and_172; // op=pyc.and +wire pyc_and_173; // op=pyc.and +wire pyc_and_175; // op=pyc.and +wire pyc_and_182; // op=pyc.and +wire pyc_and_183; // op=pyc.and +wire pyc_and_185; // op=pyc.and +wire pyc_and_190; // op=pyc.and +wire pyc_and_191; // op=pyc.and +wire pyc_and_193; // op=pyc.and +wire pyc_and_20; // op=pyc.and +wire pyc_and_200; // op=pyc.and +wire pyc_and_201; // op=pyc.and +wire pyc_and_203; // op=pyc.and +wire pyc_and_208; // op=pyc.and +wire pyc_and_209; // op=pyc.and +wire pyc_and_21; // op=pyc.and +wire pyc_and_211; // op=pyc.and +wire pyc_and_218; // op=pyc.and +wire pyc_and_219; // op=pyc.and +wire pyc_and_221; // op=pyc.and +wire pyc_and_226; // op=pyc.and +wire pyc_and_227; // op=pyc.and +wire pyc_and_229; // op=pyc.and +wire pyc_and_23; // op=pyc.and +wire pyc_and_236; // op=pyc.and +wire pyc_and_237; // op=pyc.and +wire pyc_and_239; // op=pyc.and +wire pyc_and_244; // op=pyc.and +wire pyc_and_245; // op=pyc.and +wire pyc_and_247; // op=pyc.and +wire pyc_and_254; // op=pyc.and +wire pyc_and_255; // op=pyc.and +wire pyc_and_257; // op=pyc.and +wire pyc_and_262; // op=pyc.and +wire pyc_and_263; // op=pyc.and +wire pyc_and_265; // op=pyc.and +wire pyc_and_272; // op=pyc.and +wire pyc_and_273; // op=pyc.and +wire pyc_and_275; // op=pyc.and +wire pyc_and_28; // op=pyc.and +wire pyc_and_280; // op=pyc.and +wire pyc_and_281; // op=pyc.and +wire pyc_and_283; // op=pyc.and +wire pyc_and_29; // op=pyc.and +wire pyc_and_290; // op=pyc.and +wire pyc_and_291; // op=pyc.and +wire pyc_and_293; // op=pyc.and +wire pyc_and_298; // op=pyc.and +wire pyc_and_299; // op=pyc.and +wire pyc_and_301; // op=pyc.and +wire pyc_and_308; // op=pyc.and +wire pyc_and_309; // op=pyc.and +wire pyc_and_31; // op=pyc.and +wire pyc_and_311; // op=pyc.and +wire pyc_and_316; // op=pyc.and +wire pyc_and_317; // op=pyc.and +wire pyc_and_319; // op=pyc.and +wire pyc_and_326; // op=pyc.and +wire pyc_and_327; // op=pyc.and +wire pyc_and_329; // op=pyc.and +wire pyc_and_334; // op=pyc.and +wire pyc_and_335; // op=pyc.and +wire pyc_and_337; // op=pyc.and +wire pyc_and_344; // op=pyc.and +wire pyc_and_345; // op=pyc.and +wire pyc_and_347; // op=pyc.and +wire pyc_and_352; // op=pyc.and +wire pyc_and_353; // op=pyc.and +wire pyc_and_355; // op=pyc.and +wire pyc_and_362; // op=pyc.and +wire pyc_and_363; // op=pyc.and +wire pyc_and_365; // op=pyc.and +wire pyc_and_370; // op=pyc.and +wire pyc_and_371; // op=pyc.and +wire pyc_and_373; // op=pyc.and +wire pyc_and_38; // op=pyc.and +wire pyc_and_380; // op=pyc.and +wire pyc_and_381; // op=pyc.and +wire pyc_and_383; // op=pyc.and +wire pyc_and_388; // op=pyc.and +wire pyc_and_389; // op=pyc.and +wire pyc_and_39; // op=pyc.and +wire pyc_and_391; // op=pyc.and +wire pyc_and_398; // op=pyc.and +wire pyc_and_399; // op=pyc.and +wire pyc_and_401; // op=pyc.and +wire pyc_and_406; // op=pyc.and +wire pyc_and_407; // op=pyc.and +wire pyc_and_409; // op=pyc.and +wire pyc_and_41; // op=pyc.and +wire pyc_and_416; // op=pyc.and +wire pyc_and_417; // op=pyc.and +wire pyc_and_419; // op=pyc.and +wire pyc_and_424; // op=pyc.and +wire pyc_and_425; // op=pyc.and +wire pyc_and_427; // op=pyc.and +wire pyc_and_434; // op=pyc.and +wire pyc_and_435; // op=pyc.and +wire pyc_and_437; // op=pyc.and +wire pyc_and_442; // op=pyc.and +wire pyc_and_443; // op=pyc.and +wire pyc_and_445; // op=pyc.and +wire pyc_and_452; // op=pyc.and +wire pyc_and_453; // op=pyc.and +wire pyc_and_455; // op=pyc.and +wire pyc_and_46; // op=pyc.and +wire pyc_and_460; // op=pyc.and +wire pyc_and_461; // op=pyc.and +wire pyc_and_463; // op=pyc.and +wire pyc_and_47; // op=pyc.and +wire pyc_and_470; // op=pyc.and +wire pyc_and_471; // op=pyc.and +wire pyc_and_473; // op=pyc.and +wire pyc_and_478; // op=pyc.and +wire pyc_and_479; // op=pyc.and +wire pyc_and_481; // op=pyc.and +wire pyc_and_488; // op=pyc.and +wire pyc_and_489; // op=pyc.and +wire pyc_and_49; // op=pyc.and +wire pyc_and_491; // op=pyc.and +wire pyc_and_496; // op=pyc.and +wire pyc_and_497; // op=pyc.and +wire pyc_and_499; // op=pyc.and +wire pyc_and_506; // op=pyc.and +wire pyc_and_507; // op=pyc.and +wire pyc_and_509; // op=pyc.and +wire pyc_and_514; // op=pyc.and +wire pyc_and_515; // op=pyc.and +wire pyc_and_517; // op=pyc.and +wire pyc_and_524; // op=pyc.and +wire pyc_and_525; // op=pyc.and +wire pyc_and_527; // op=pyc.and +wire pyc_and_532; // op=pyc.and +wire pyc_and_533; // op=pyc.and +wire pyc_and_535; // op=pyc.and +wire pyc_and_542; // op=pyc.and +wire pyc_and_543; // op=pyc.and +wire pyc_and_545; // op=pyc.and +wire pyc_and_550; // op=pyc.and +wire pyc_and_551; // op=pyc.and +wire pyc_and_553; // op=pyc.and +wire pyc_and_56; // op=pyc.and +wire pyc_and_568; // op=pyc.and +wire pyc_and_569; // op=pyc.and +wire pyc_and_57; // op=pyc.and +wire pyc_and_571; // op=pyc.and +wire pyc_and_575; // op=pyc.and +wire pyc_and_581; // op=pyc.and +wire pyc_and_582; // op=pyc.and +wire pyc_and_584; // op=pyc.and +wire pyc_and_589; // op=pyc.and +wire pyc_and_59; // op=pyc.and +wire pyc_and_590; // op=pyc.and +wire pyc_and_592; // op=pyc.and +wire pyc_and_599; // op=pyc.and +wire pyc_and_600; // op=pyc.and +wire pyc_and_602; // op=pyc.and +wire pyc_and_607; // op=pyc.and +wire pyc_and_608; // op=pyc.and +wire pyc_and_610; // op=pyc.and +wire pyc_and_617; // op=pyc.and +wire pyc_and_618; // op=pyc.and +wire pyc_and_620; // op=pyc.and +wire pyc_and_625; // op=pyc.and +wire pyc_and_626; // op=pyc.and +wire pyc_and_628; // op=pyc.and +wire pyc_and_635; // op=pyc.and +wire pyc_and_636; // op=pyc.and +wire pyc_and_638; // op=pyc.and +wire pyc_and_64; // op=pyc.and +wire pyc_and_643; // op=pyc.and +wire pyc_and_644; // op=pyc.and +wire pyc_and_646; // op=pyc.and +wire pyc_and_65; // op=pyc.and +wire pyc_and_653; // op=pyc.and +wire pyc_and_654; // op=pyc.and +wire pyc_and_656; // op=pyc.and +wire pyc_and_661; // op=pyc.and +wire pyc_and_662; // op=pyc.and +wire pyc_and_664; // op=pyc.and +wire pyc_and_67; // op=pyc.and +wire pyc_and_671; // op=pyc.and +wire pyc_and_672; // op=pyc.and +wire pyc_and_674; // op=pyc.and +wire pyc_and_679; // op=pyc.and +wire pyc_and_680; // op=pyc.and +wire pyc_and_682; // op=pyc.and +wire pyc_and_689; // op=pyc.and +wire pyc_and_690; // op=pyc.and +wire pyc_and_692; // op=pyc.and +wire pyc_and_697; // op=pyc.and +wire pyc_and_698; // op=pyc.and +wire pyc_and_7; // op=pyc.and +wire pyc_and_700; // op=pyc.and +wire pyc_and_707; // op=pyc.and +wire pyc_and_708; // op=pyc.and +wire pyc_and_710; // op=pyc.and +wire pyc_and_715; // op=pyc.and +wire pyc_and_716; // op=pyc.and +wire pyc_and_718; // op=pyc.and +wire pyc_and_725; // op=pyc.and +wire pyc_and_726; // op=pyc.and +wire pyc_and_728; // op=pyc.and +wire pyc_and_733; // op=pyc.and +wire pyc_and_734; // op=pyc.and +wire pyc_and_736; // op=pyc.and +wire pyc_and_74; // op=pyc.and +wire pyc_and_743; // op=pyc.and +wire pyc_and_744; // op=pyc.and +wire pyc_and_746; // op=pyc.and +wire pyc_and_75; // op=pyc.and +wire pyc_and_751; // op=pyc.and +wire pyc_and_752; // op=pyc.and +wire pyc_and_754; // op=pyc.and +wire pyc_and_761; // op=pyc.and +wire pyc_and_762; // op=pyc.and +wire pyc_and_764; // op=pyc.and +wire pyc_and_769; // op=pyc.and +wire pyc_and_77; // op=pyc.and +wire pyc_and_770; // op=pyc.and +wire pyc_and_772; // op=pyc.and +wire pyc_and_779; // op=pyc.and +wire pyc_and_780; // op=pyc.and +wire pyc_and_782; // op=pyc.and +wire pyc_and_787; // op=pyc.and +wire pyc_and_788; // op=pyc.and +wire pyc_and_790; // op=pyc.and +wire pyc_and_797; // op=pyc.and +wire pyc_and_798; // op=pyc.and +wire pyc_and_8; // op=pyc.and +wire pyc_and_800; // op=pyc.and +wire pyc_and_805; // op=pyc.and +wire pyc_and_806; // op=pyc.and +wire pyc_and_808; // op=pyc.and +wire pyc_and_815; // op=pyc.and +wire pyc_and_816; // op=pyc.and +wire pyc_and_818; // op=pyc.and +wire pyc_and_82; // op=pyc.and +wire pyc_and_823; // op=pyc.and +wire pyc_and_824; // op=pyc.and +wire pyc_and_826; // op=pyc.and +wire pyc_and_83; // op=pyc.and +wire pyc_and_833; // op=pyc.and +wire pyc_and_834; // op=pyc.and +wire pyc_and_836; // op=pyc.and +wire pyc_and_841; // op=pyc.and +wire pyc_and_842; // op=pyc.and +wire pyc_and_844; // op=pyc.and +wire pyc_and_85; // op=pyc.and +wire pyc_and_851; // op=pyc.and +wire pyc_and_852; // op=pyc.and +wire pyc_and_854; // op=pyc.and +wire pyc_and_859; // op=pyc.and +wire pyc_and_860; // op=pyc.and +wire pyc_and_862; // op=pyc.and +wire pyc_and_869; // op=pyc.and +wire pyc_and_870; // op=pyc.and +wire pyc_and_872; // op=pyc.and +wire pyc_and_877; // op=pyc.and +wire pyc_and_878; // op=pyc.and +wire pyc_and_880; // op=pyc.and +wire pyc_and_887; // op=pyc.and +wire pyc_and_888; // op=pyc.and +wire pyc_and_890; // op=pyc.and +wire pyc_and_895; // op=pyc.and +wire pyc_and_896; // op=pyc.and +wire pyc_and_898; // op=pyc.and +wire pyc_and_905; // op=pyc.and +wire pyc_and_906; // op=pyc.and +wire pyc_and_908; // op=pyc.and +wire pyc_and_913; // op=pyc.and +wire pyc_and_914; // op=pyc.and +wire pyc_and_916; // op=pyc.and +wire pyc_and_92; // op=pyc.and +wire pyc_and_923; // op=pyc.and +wire pyc_and_924; // op=pyc.and +wire pyc_and_926; // op=pyc.and +wire pyc_and_93; // op=pyc.and +wire pyc_and_931; // op=pyc.and +wire pyc_and_932; // op=pyc.and +wire pyc_and_934; // op=pyc.and +wire pyc_and_941; // op=pyc.and +wire pyc_and_942; // op=pyc.and +wire pyc_and_944; // op=pyc.and +wire pyc_and_949; // op=pyc.and +wire pyc_and_95; // op=pyc.and +wire pyc_and_950; // op=pyc.and +wire pyc_and_952; // op=pyc.and +wire pyc_and_959; // op=pyc.and +wire pyc_and_960; // op=pyc.and +wire pyc_and_962; // op=pyc.and +wire pyc_and_967; // op=pyc.and +wire pyc_and_968; // op=pyc.and +wire pyc_and_970; // op=pyc.and +wire pyc_and_977; // op=pyc.and +wire pyc_and_978; // op=pyc.and +wire pyc_and_980; // op=pyc.and +wire pyc_and_985; // op=pyc.and +wire pyc_and_986; // op=pyc.and +wire pyc_and_988; // op=pyc.and +wire pyc_and_995; // op=pyc.and +wire pyc_and_996; // op=pyc.and +wire pyc_and_998; // op=pyc.and +wire [31:0] pyc_comb_1553; // op=pyc.comb +wire [31:0] pyc_concat_1550; // op=pyc.concat +wire [31:0] pyc_concat_1551; // op=pyc.concat +wire pyc_constant_1; // op=pyc.constant +wire pyc_extract_1000; // op=pyc.extract +wire pyc_extract_1008; // op=pyc.extract +wire pyc_extract_1009; // op=pyc.extract +wire pyc_extract_1010; // op=pyc.extract +wire pyc_extract_1018; // op=pyc.extract +wire pyc_extract_1026; // op=pyc.extract +wire pyc_extract_1027; // op=pyc.extract +wire pyc_extract_1028; // op=pyc.extract +wire pyc_extract_1036; // op=pyc.extract +wire pyc_extract_1044; // op=pyc.extract +wire pyc_extract_1045; // op=pyc.extract +wire pyc_extract_1046; // op=pyc.extract +wire pyc_extract_105; // op=pyc.extract +wire pyc_extract_1054; // op=pyc.extract +wire pyc_extract_106; // op=pyc.extract +wire pyc_extract_1062; // op=pyc.extract +wire pyc_extract_1063; // op=pyc.extract +wire pyc_extract_1064; // op=pyc.extract +wire pyc_extract_107; // op=pyc.extract +wire pyc_extract_1072; // op=pyc.extract +wire pyc_extract_1080; // op=pyc.extract +wire pyc_extract_1081; // op=pyc.extract +wire pyc_extract_1082; // op=pyc.extract +wire pyc_extract_1090; // op=pyc.extract +wire pyc_extract_1098; // op=pyc.extract +wire pyc_extract_1099; // op=pyc.extract +wire pyc_extract_1100; // op=pyc.extract +wire pyc_extract_1108; // op=pyc.extract +wire pyc_extract_1116; // op=pyc.extract +wire pyc_extract_1117; // op=pyc.extract +wire pyc_extract_1118; // op=pyc.extract +wire pyc_extract_1121; // op=pyc.extract +wire pyc_extract_115; // op=pyc.extract +wire pyc_extract_12; // op=pyc.extract +wire pyc_extract_123; // op=pyc.extract +wire pyc_extract_124; // op=pyc.extract +wire pyc_extract_125; // op=pyc.extract +wire pyc_extract_133; // op=pyc.extract +wire pyc_extract_141; // op=pyc.extract +wire pyc_extract_142; // op=pyc.extract +wire pyc_extract_143; // op=pyc.extract +wire pyc_extract_15; // op=pyc.extract +wire pyc_extract_151; // op=pyc.extract +wire pyc_extract_159; // op=pyc.extract +wire pyc_extract_16; // op=pyc.extract +wire pyc_extract_160; // op=pyc.extract +wire pyc_extract_161; // op=pyc.extract +wire pyc_extract_169; // op=pyc.extract +wire pyc_extract_17; // op=pyc.extract +wire pyc_extract_177; // op=pyc.extract +wire pyc_extract_178; // op=pyc.extract +wire pyc_extract_179; // op=pyc.extract +wire pyc_extract_187; // op=pyc.extract +wire pyc_extract_195; // op=pyc.extract +wire pyc_extract_196; // op=pyc.extract +wire pyc_extract_197; // op=pyc.extract +wire pyc_extract_2; // op=pyc.extract +wire pyc_extract_205; // op=pyc.extract +wire pyc_extract_213; // op=pyc.extract +wire pyc_extract_214; // op=pyc.extract +wire pyc_extract_215; // op=pyc.extract +wire pyc_extract_223; // op=pyc.extract +wire pyc_extract_231; // op=pyc.extract +wire pyc_extract_232; // op=pyc.extract +wire pyc_extract_233; // op=pyc.extract +wire pyc_extract_241; // op=pyc.extract +wire pyc_extract_249; // op=pyc.extract +wire pyc_extract_25; // op=pyc.extract +wire pyc_extract_250; // op=pyc.extract +wire pyc_extract_251; // op=pyc.extract +wire pyc_extract_259; // op=pyc.extract +wire pyc_extract_267; // op=pyc.extract +wire pyc_extract_268; // op=pyc.extract +wire pyc_extract_269; // op=pyc.extract +wire pyc_extract_277; // op=pyc.extract +wire pyc_extract_285; // op=pyc.extract +wire pyc_extract_286; // op=pyc.extract +wire pyc_extract_287; // op=pyc.extract +wire pyc_extract_295; // op=pyc.extract +wire pyc_extract_3; // op=pyc.extract +wire pyc_extract_303; // op=pyc.extract +wire pyc_extract_304; // op=pyc.extract +wire pyc_extract_305; // op=pyc.extract +wire pyc_extract_313; // op=pyc.extract +wire pyc_extract_321; // op=pyc.extract +wire pyc_extract_322; // op=pyc.extract +wire pyc_extract_323; // op=pyc.extract +wire pyc_extract_33; // op=pyc.extract +wire pyc_extract_331; // op=pyc.extract +wire pyc_extract_339; // op=pyc.extract +wire pyc_extract_34; // op=pyc.extract +wire pyc_extract_340; // op=pyc.extract +wire pyc_extract_341; // op=pyc.extract +wire pyc_extract_349; // op=pyc.extract +wire pyc_extract_35; // op=pyc.extract +wire pyc_extract_357; // op=pyc.extract +wire pyc_extract_358; // op=pyc.extract +wire pyc_extract_359; // op=pyc.extract +wire pyc_extract_367; // op=pyc.extract +wire pyc_extract_375; // op=pyc.extract +wire pyc_extract_376; // op=pyc.extract +wire pyc_extract_377; // op=pyc.extract +wire pyc_extract_385; // op=pyc.extract +wire pyc_extract_393; // op=pyc.extract +wire pyc_extract_394; // op=pyc.extract +wire pyc_extract_395; // op=pyc.extract +wire pyc_extract_4; // op=pyc.extract +wire pyc_extract_403; // op=pyc.extract +wire pyc_extract_411; // op=pyc.extract +wire pyc_extract_412; // op=pyc.extract +wire pyc_extract_413; // op=pyc.extract +wire pyc_extract_421; // op=pyc.extract +wire pyc_extract_429; // op=pyc.extract +wire pyc_extract_43; // op=pyc.extract +wire pyc_extract_430; // op=pyc.extract +wire pyc_extract_431; // op=pyc.extract +wire pyc_extract_439; // op=pyc.extract +wire pyc_extract_447; // op=pyc.extract +wire pyc_extract_448; // op=pyc.extract +wire pyc_extract_449; // op=pyc.extract +wire pyc_extract_457; // op=pyc.extract +wire pyc_extract_465; // op=pyc.extract +wire pyc_extract_466; // op=pyc.extract +wire pyc_extract_467; // op=pyc.extract +wire pyc_extract_475; // op=pyc.extract +wire pyc_extract_483; // op=pyc.extract +wire pyc_extract_484; // op=pyc.extract +wire pyc_extract_485; // op=pyc.extract +wire pyc_extract_493; // op=pyc.extract +wire pyc_extract_501; // op=pyc.extract +wire pyc_extract_502; // op=pyc.extract +wire pyc_extract_503; // op=pyc.extract +wire pyc_extract_51; // op=pyc.extract +wire pyc_extract_511; // op=pyc.extract +wire pyc_extract_519; // op=pyc.extract +wire pyc_extract_52; // op=pyc.extract +wire pyc_extract_520; // op=pyc.extract +wire pyc_extract_521; // op=pyc.extract +wire pyc_extract_529; // op=pyc.extract +wire pyc_extract_53; // op=pyc.extract +wire pyc_extract_537; // op=pyc.extract +wire pyc_extract_538; // op=pyc.extract +wire pyc_extract_539; // op=pyc.extract +wire pyc_extract_547; // op=pyc.extract +wire pyc_extract_555; // op=pyc.extract +wire pyc_extract_556; // op=pyc.extract +wire pyc_extract_557; // op=pyc.extract +wire pyc_extract_560; // op=pyc.extract +wire pyc_extract_563; // op=pyc.extract +wire pyc_extract_564; // op=pyc.extract +wire pyc_extract_565; // op=pyc.extract +wire pyc_extract_573; // op=pyc.extract +wire pyc_extract_576; // op=pyc.extract +wire pyc_extract_577; // op=pyc.extract +wire pyc_extract_578; // op=pyc.extract +wire pyc_extract_586; // op=pyc.extract +wire pyc_extract_594; // op=pyc.extract +wire pyc_extract_595; // op=pyc.extract +wire pyc_extract_596; // op=pyc.extract +wire pyc_extract_604; // op=pyc.extract +wire pyc_extract_61; // op=pyc.extract +wire pyc_extract_612; // op=pyc.extract +wire pyc_extract_613; // op=pyc.extract +wire pyc_extract_614; // op=pyc.extract +wire pyc_extract_622; // op=pyc.extract +wire pyc_extract_630; // op=pyc.extract +wire pyc_extract_631; // op=pyc.extract +wire pyc_extract_632; // op=pyc.extract +wire pyc_extract_640; // op=pyc.extract +wire pyc_extract_648; // op=pyc.extract +wire pyc_extract_649; // op=pyc.extract +wire pyc_extract_650; // op=pyc.extract +wire pyc_extract_658; // op=pyc.extract +wire pyc_extract_666; // op=pyc.extract +wire pyc_extract_667; // op=pyc.extract +wire pyc_extract_668; // op=pyc.extract +wire pyc_extract_676; // op=pyc.extract +wire pyc_extract_684; // op=pyc.extract +wire pyc_extract_685; // op=pyc.extract +wire pyc_extract_686; // op=pyc.extract +wire pyc_extract_69; // op=pyc.extract +wire pyc_extract_694; // op=pyc.extract +wire pyc_extract_70; // op=pyc.extract +wire pyc_extract_702; // op=pyc.extract +wire pyc_extract_703; // op=pyc.extract +wire pyc_extract_704; // op=pyc.extract +wire pyc_extract_71; // op=pyc.extract +wire pyc_extract_712; // op=pyc.extract +wire pyc_extract_720; // op=pyc.extract +wire pyc_extract_721; // op=pyc.extract +wire pyc_extract_722; // op=pyc.extract +wire pyc_extract_730; // op=pyc.extract +wire pyc_extract_738; // op=pyc.extract +wire pyc_extract_739; // op=pyc.extract +wire pyc_extract_740; // op=pyc.extract +wire pyc_extract_748; // op=pyc.extract +wire pyc_extract_756; // op=pyc.extract +wire pyc_extract_757; // op=pyc.extract +wire pyc_extract_758; // op=pyc.extract +wire pyc_extract_766; // op=pyc.extract +wire pyc_extract_774; // op=pyc.extract +wire pyc_extract_775; // op=pyc.extract +wire pyc_extract_776; // op=pyc.extract +wire pyc_extract_784; // op=pyc.extract +wire pyc_extract_79; // op=pyc.extract +wire pyc_extract_792; // op=pyc.extract +wire pyc_extract_793; // op=pyc.extract +wire pyc_extract_794; // op=pyc.extract +wire pyc_extract_802; // op=pyc.extract +wire pyc_extract_810; // op=pyc.extract +wire pyc_extract_811; // op=pyc.extract +wire pyc_extract_812; // op=pyc.extract +wire pyc_extract_820; // op=pyc.extract +wire pyc_extract_828; // op=pyc.extract +wire pyc_extract_829; // op=pyc.extract +wire pyc_extract_830; // op=pyc.extract +wire pyc_extract_838; // op=pyc.extract +wire pyc_extract_846; // op=pyc.extract +wire pyc_extract_847; // op=pyc.extract +wire pyc_extract_848; // op=pyc.extract +wire pyc_extract_856; // op=pyc.extract +wire pyc_extract_864; // op=pyc.extract +wire pyc_extract_865; // op=pyc.extract +wire pyc_extract_866; // op=pyc.extract +wire pyc_extract_87; // op=pyc.extract +wire pyc_extract_874; // op=pyc.extract +wire pyc_extract_88; // op=pyc.extract +wire pyc_extract_882; // op=pyc.extract +wire pyc_extract_883; // op=pyc.extract +wire pyc_extract_884; // op=pyc.extract +wire pyc_extract_89; // op=pyc.extract +wire pyc_extract_892; // op=pyc.extract +wire pyc_extract_900; // op=pyc.extract +wire pyc_extract_901; // op=pyc.extract +wire pyc_extract_902; // op=pyc.extract +wire pyc_extract_910; // op=pyc.extract +wire pyc_extract_918; // op=pyc.extract +wire pyc_extract_919; // op=pyc.extract +wire pyc_extract_920; // op=pyc.extract +wire pyc_extract_928; // op=pyc.extract +wire pyc_extract_936; // op=pyc.extract +wire pyc_extract_937; // op=pyc.extract +wire pyc_extract_938; // op=pyc.extract +wire pyc_extract_946; // op=pyc.extract +wire pyc_extract_954; // op=pyc.extract +wire pyc_extract_955; // op=pyc.extract +wire pyc_extract_956; // op=pyc.extract +wire pyc_extract_964; // op=pyc.extract +wire pyc_extract_97; // op=pyc.extract +wire pyc_extract_972; // op=pyc.extract +wire pyc_extract_973; // op=pyc.extract +wire pyc_extract_974; // op=pyc.extract +wire pyc_extract_982; // op=pyc.extract +wire pyc_extract_990; // op=pyc.extract +wire pyc_extract_991; // op=pyc.extract +wire pyc_extract_992; // op=pyc.extract +wire pyc_or_1005; // op=pyc.or +wire pyc_or_1007; // op=pyc.or +wire pyc_or_1015; // op=pyc.or +wire pyc_or_1017; // op=pyc.or +wire pyc_or_102; // op=pyc.or +wire pyc_or_1023; // op=pyc.or +wire pyc_or_1025; // op=pyc.or +wire pyc_or_1033; // op=pyc.or +wire pyc_or_1035; // op=pyc.or +wire pyc_or_104; // op=pyc.or +wire pyc_or_1041; // op=pyc.or +wire pyc_or_1043; // op=pyc.or +wire pyc_or_1051; // op=pyc.or +wire pyc_or_1053; // op=pyc.or +wire pyc_or_1059; // op=pyc.or +wire pyc_or_1061; // op=pyc.or +wire pyc_or_1069; // op=pyc.or +wire pyc_or_1071; // op=pyc.or +wire pyc_or_1077; // op=pyc.or +wire pyc_or_1079; // op=pyc.or +wire pyc_or_1087; // op=pyc.or +wire pyc_or_1089; // op=pyc.or +wire pyc_or_1095; // op=pyc.or +wire pyc_or_1097; // op=pyc.or +wire pyc_or_11; // op=pyc.or +wire pyc_or_1105; // op=pyc.or +wire pyc_or_1107; // op=pyc.or +wire pyc_or_1113; // op=pyc.or +wire pyc_or_1115; // op=pyc.or +wire pyc_or_112; // op=pyc.or +wire pyc_or_1130; // op=pyc.or +wire pyc_or_1132; // op=pyc.or +wire pyc_or_1137; // op=pyc.or +wire pyc_or_1139; // op=pyc.or +wire pyc_or_114; // op=pyc.or +wire pyc_or_1144; // op=pyc.or +wire pyc_or_1146; // op=pyc.or +wire pyc_or_1151; // op=pyc.or +wire pyc_or_1153; // op=pyc.or +wire pyc_or_1158; // op=pyc.or +wire pyc_or_1160; // op=pyc.or +wire pyc_or_1165; // op=pyc.or +wire pyc_or_1167; // op=pyc.or +wire pyc_or_1172; // op=pyc.or +wire pyc_or_1174; // op=pyc.or +wire pyc_or_1179; // op=pyc.or +wire pyc_or_1181; // op=pyc.or +wire pyc_or_1186; // op=pyc.or +wire pyc_or_1188; // op=pyc.or +wire pyc_or_1193; // op=pyc.or +wire pyc_or_1195; // op=pyc.or +wire pyc_or_120; // op=pyc.or +wire pyc_or_1200; // op=pyc.or +wire pyc_or_1202; // op=pyc.or +wire pyc_or_1207; // op=pyc.or +wire pyc_or_1209; // op=pyc.or +wire pyc_or_1214; // op=pyc.or +wire pyc_or_1216; // op=pyc.or +wire pyc_or_122; // op=pyc.or +wire pyc_or_1221; // op=pyc.or +wire pyc_or_1223; // op=pyc.or +wire pyc_or_1228; // op=pyc.or +wire pyc_or_1230; // op=pyc.or +wire pyc_or_1235; // op=pyc.or +wire pyc_or_1237; // op=pyc.or +wire pyc_or_1242; // op=pyc.or +wire pyc_or_1244; // op=pyc.or +wire pyc_or_1249; // op=pyc.or +wire pyc_or_1251; // op=pyc.or +wire pyc_or_1256; // op=pyc.or +wire pyc_or_1258; // op=pyc.or +wire pyc_or_1263; // op=pyc.or +wire pyc_or_1265; // op=pyc.or +wire pyc_or_1270; // op=pyc.or +wire pyc_or_1272; // op=pyc.or +wire pyc_or_1277; // op=pyc.or +wire pyc_or_1279; // op=pyc.or +wire pyc_or_1284; // op=pyc.or +wire pyc_or_1286; // op=pyc.or +wire pyc_or_1291; // op=pyc.or +wire pyc_or_1293; // op=pyc.or +wire pyc_or_1298; // op=pyc.or +wire pyc_or_130; // op=pyc.or +wire pyc_or_1300; // op=pyc.or +wire pyc_or_1305; // op=pyc.or +wire pyc_or_1307; // op=pyc.or +wire pyc_or_1312; // op=pyc.or +wire pyc_or_1314; // op=pyc.or +wire pyc_or_1319; // op=pyc.or +wire pyc_or_132; // op=pyc.or +wire pyc_or_1321; // op=pyc.or +wire pyc_or_1326; // op=pyc.or +wire pyc_or_1328; // op=pyc.or +wire pyc_or_1333; // op=pyc.or +wire pyc_or_1335; // op=pyc.or +wire pyc_or_1340; // op=pyc.or +wire pyc_or_1342; // op=pyc.or +wire pyc_or_1347; // op=pyc.or +wire pyc_or_1349; // op=pyc.or +wire pyc_or_1354; // op=pyc.or +wire pyc_or_1356; // op=pyc.or +wire pyc_or_1361; // op=pyc.or +wire pyc_or_1363; // op=pyc.or +wire pyc_or_1368; // op=pyc.or +wire pyc_or_1370; // op=pyc.or +wire pyc_or_1375; // op=pyc.or +wire pyc_or_1377; // op=pyc.or +wire pyc_or_138; // op=pyc.or +wire pyc_or_1382; // op=pyc.or +wire pyc_or_1384; // op=pyc.or +wire pyc_or_1389; // op=pyc.or +wire pyc_or_1391; // op=pyc.or +wire pyc_or_1396; // op=pyc.or +wire pyc_or_1398; // op=pyc.or +wire pyc_or_140; // op=pyc.or +wire pyc_or_1403; // op=pyc.or +wire pyc_or_1405; // op=pyc.or +wire pyc_or_1410; // op=pyc.or +wire pyc_or_1412; // op=pyc.or +wire pyc_or_1417; // op=pyc.or +wire pyc_or_1419; // op=pyc.or +wire pyc_or_1424; // op=pyc.or +wire pyc_or_1426; // op=pyc.or +wire pyc_or_1431; // op=pyc.or +wire pyc_or_1433; // op=pyc.or +wire pyc_or_1438; // op=pyc.or +wire pyc_or_1440; // op=pyc.or +wire pyc_or_1445; // op=pyc.or +wire pyc_or_1447; // op=pyc.or +wire pyc_or_1452; // op=pyc.or +wire pyc_or_1454; // op=pyc.or +wire pyc_or_1459; // op=pyc.or +wire pyc_or_1461; // op=pyc.or +wire pyc_or_1466; // op=pyc.or +wire pyc_or_1468; // op=pyc.or +wire pyc_or_1473; // op=pyc.or +wire pyc_or_1475; // op=pyc.or +wire pyc_or_148; // op=pyc.or +wire pyc_or_1480; // op=pyc.or +wire pyc_or_1482; // op=pyc.or +wire pyc_or_1487; // op=pyc.or +wire pyc_or_1489; // op=pyc.or +wire pyc_or_1494; // op=pyc.or +wire pyc_or_1496; // op=pyc.or +wire pyc_or_150; // op=pyc.or +wire pyc_or_1501; // op=pyc.or +wire pyc_or_1503; // op=pyc.or +wire pyc_or_1508; // op=pyc.or +wire pyc_or_1510; // op=pyc.or +wire pyc_or_1515; // op=pyc.or +wire pyc_or_1517; // op=pyc.or +wire pyc_or_1522; // op=pyc.or +wire pyc_or_1524; // op=pyc.or +wire pyc_or_1529; // op=pyc.or +wire pyc_or_1531; // op=pyc.or +wire pyc_or_1536; // op=pyc.or +wire pyc_or_1538; // op=pyc.or +wire pyc_or_1543; // op=pyc.or +wire pyc_or_1545; // op=pyc.or +wire pyc_or_156; // op=pyc.or +wire pyc_or_158; // op=pyc.or +wire pyc_or_166; // op=pyc.or +wire pyc_or_168; // op=pyc.or +wire pyc_or_174; // op=pyc.or +wire pyc_or_176; // op=pyc.or +wire pyc_or_184; // op=pyc.or +wire pyc_or_186; // op=pyc.or +wire pyc_or_192; // op=pyc.or +wire pyc_or_194; // op=pyc.or +wire pyc_or_202; // op=pyc.or +wire pyc_or_204; // op=pyc.or +wire pyc_or_210; // op=pyc.or +wire pyc_or_212; // op=pyc.or +wire pyc_or_22; // op=pyc.or +wire pyc_or_220; // op=pyc.or +wire pyc_or_222; // op=pyc.or +wire pyc_or_228; // op=pyc.or +wire pyc_or_230; // op=pyc.or +wire pyc_or_238; // op=pyc.or +wire pyc_or_24; // op=pyc.or +wire pyc_or_240; // op=pyc.or +wire pyc_or_246; // op=pyc.or +wire pyc_or_248; // op=pyc.or +wire pyc_or_256; // op=pyc.or +wire pyc_or_258; // op=pyc.or +wire pyc_or_264; // op=pyc.or +wire pyc_or_266; // op=pyc.or +wire pyc_or_274; // op=pyc.or +wire pyc_or_276; // op=pyc.or +wire pyc_or_282; // op=pyc.or +wire pyc_or_284; // op=pyc.or +wire pyc_or_292; // op=pyc.or +wire pyc_or_294; // op=pyc.or +wire pyc_or_30; // op=pyc.or +wire pyc_or_300; // op=pyc.or +wire pyc_or_302; // op=pyc.or +wire pyc_or_310; // op=pyc.or +wire pyc_or_312; // op=pyc.or +wire pyc_or_318; // op=pyc.or +wire pyc_or_32; // op=pyc.or +wire pyc_or_320; // op=pyc.or +wire pyc_or_328; // op=pyc.or +wire pyc_or_330; // op=pyc.or +wire pyc_or_336; // op=pyc.or +wire pyc_or_338; // op=pyc.or +wire pyc_or_346; // op=pyc.or +wire pyc_or_348; // op=pyc.or +wire pyc_or_354; // op=pyc.or +wire pyc_or_356; // op=pyc.or +wire pyc_or_364; // op=pyc.or +wire pyc_or_366; // op=pyc.or +wire pyc_or_372; // op=pyc.or +wire pyc_or_374; // op=pyc.or +wire pyc_or_382; // op=pyc.or +wire pyc_or_384; // op=pyc.or +wire pyc_or_390; // op=pyc.or +wire pyc_or_392; // op=pyc.or +wire pyc_or_40; // op=pyc.or +wire pyc_or_400; // op=pyc.or +wire pyc_or_402; // op=pyc.or +wire pyc_or_408; // op=pyc.or +wire pyc_or_410; // op=pyc.or +wire pyc_or_418; // op=pyc.or +wire pyc_or_42; // op=pyc.or +wire pyc_or_420; // op=pyc.or +wire pyc_or_426; // op=pyc.or +wire pyc_or_428; // op=pyc.or +wire pyc_or_436; // op=pyc.or +wire pyc_or_438; // op=pyc.or +wire pyc_or_444; // op=pyc.or +wire pyc_or_446; // op=pyc.or +wire pyc_or_454; // op=pyc.or +wire pyc_or_456; // op=pyc.or +wire pyc_or_462; // op=pyc.or +wire pyc_or_464; // op=pyc.or +wire pyc_or_472; // op=pyc.or +wire pyc_or_474; // op=pyc.or +wire pyc_or_48; // op=pyc.or +wire pyc_or_480; // op=pyc.or +wire pyc_or_482; // op=pyc.or +wire pyc_or_490; // op=pyc.or +wire pyc_or_492; // op=pyc.or +wire pyc_or_498; // op=pyc.or +wire pyc_or_50; // op=pyc.or +wire pyc_or_500; // op=pyc.or +wire pyc_or_508; // op=pyc.or +wire pyc_or_510; // op=pyc.or +wire pyc_or_516; // op=pyc.or +wire pyc_or_518; // op=pyc.or +wire pyc_or_526; // op=pyc.or +wire pyc_or_528; // op=pyc.or +wire pyc_or_534; // op=pyc.or +wire pyc_or_536; // op=pyc.or +wire pyc_or_544; // op=pyc.or +wire pyc_or_546; // op=pyc.or +wire pyc_or_552; // op=pyc.or +wire pyc_or_554; // op=pyc.or +wire pyc_or_570; // op=pyc.or +wire pyc_or_572; // op=pyc.or +wire pyc_or_58; // op=pyc.or +wire pyc_or_583; // op=pyc.or +wire pyc_or_585; // op=pyc.or +wire pyc_or_591; // op=pyc.or +wire pyc_or_593; // op=pyc.or +wire pyc_or_60; // op=pyc.or +wire pyc_or_601; // op=pyc.or +wire pyc_or_603; // op=pyc.or +wire pyc_or_609; // op=pyc.or +wire pyc_or_611; // op=pyc.or +wire pyc_or_619; // op=pyc.or +wire pyc_or_621; // op=pyc.or +wire pyc_or_627; // op=pyc.or +wire pyc_or_629; // op=pyc.or +wire pyc_or_637; // op=pyc.or +wire pyc_or_639; // op=pyc.or +wire pyc_or_645; // op=pyc.or +wire pyc_or_647; // op=pyc.or +wire pyc_or_655; // op=pyc.or +wire pyc_or_657; // op=pyc.or +wire pyc_or_66; // op=pyc.or +wire pyc_or_663; // op=pyc.or +wire pyc_or_665; // op=pyc.or +wire pyc_or_673; // op=pyc.or +wire pyc_or_675; // op=pyc.or +wire pyc_or_68; // op=pyc.or +wire pyc_or_681; // op=pyc.or +wire pyc_or_683; // op=pyc.or +wire pyc_or_691; // op=pyc.or +wire pyc_or_693; // op=pyc.or +wire pyc_or_699; // op=pyc.or +wire pyc_or_701; // op=pyc.or +wire pyc_or_709; // op=pyc.or +wire pyc_or_711; // op=pyc.or +wire pyc_or_717; // op=pyc.or +wire pyc_or_719; // op=pyc.or +wire pyc_or_727; // op=pyc.or +wire pyc_or_729; // op=pyc.or +wire pyc_or_735; // op=pyc.or +wire pyc_or_737; // op=pyc.or +wire pyc_or_745; // op=pyc.or +wire pyc_or_747; // op=pyc.or +wire pyc_or_753; // op=pyc.or +wire pyc_or_755; // op=pyc.or +wire pyc_or_76; // op=pyc.or +wire pyc_or_763; // op=pyc.or +wire pyc_or_765; // op=pyc.or +wire pyc_or_771; // op=pyc.or +wire pyc_or_773; // op=pyc.or +wire pyc_or_78; // op=pyc.or +wire pyc_or_781; // op=pyc.or +wire pyc_or_783; // op=pyc.or +wire pyc_or_789; // op=pyc.or +wire pyc_or_791; // op=pyc.or +wire pyc_or_799; // op=pyc.or +wire pyc_or_801; // op=pyc.or +wire pyc_or_807; // op=pyc.or +wire pyc_or_809; // op=pyc.or +wire pyc_or_817; // op=pyc.or +wire pyc_or_819; // op=pyc.or +wire pyc_or_825; // op=pyc.or +wire pyc_or_827; // op=pyc.or +wire pyc_or_835; // op=pyc.or +wire pyc_or_837; // op=pyc.or +wire pyc_or_84; // op=pyc.or +wire pyc_or_843; // op=pyc.or +wire pyc_or_845; // op=pyc.or +wire pyc_or_853; // op=pyc.or +wire pyc_or_855; // op=pyc.or +wire pyc_or_86; // op=pyc.or +wire pyc_or_861; // op=pyc.or +wire pyc_or_863; // op=pyc.or +wire pyc_or_871; // op=pyc.or +wire pyc_or_873; // op=pyc.or +wire pyc_or_879; // op=pyc.or +wire pyc_or_881; // op=pyc.or +wire pyc_or_889; // op=pyc.or +wire pyc_or_891; // op=pyc.or +wire pyc_or_897; // op=pyc.or +wire pyc_or_899; // op=pyc.or +wire pyc_or_9; // op=pyc.or +wire pyc_or_907; // op=pyc.or +wire pyc_or_909; // op=pyc.or +wire pyc_or_915; // op=pyc.or +wire pyc_or_917; // op=pyc.or +wire pyc_or_925; // op=pyc.or +wire pyc_or_927; // op=pyc.or +wire pyc_or_933; // op=pyc.or +wire pyc_or_935; // op=pyc.or +wire pyc_or_94; // op=pyc.or +wire pyc_or_943; // op=pyc.or +wire pyc_or_945; // op=pyc.or +wire pyc_or_951; // op=pyc.or +wire pyc_or_953; // op=pyc.or +wire pyc_or_96; // op=pyc.or +wire pyc_or_961; // op=pyc.or +wire pyc_or_963; // op=pyc.or +wire pyc_or_969; // op=pyc.or +wire pyc_or_971; // op=pyc.or +wire pyc_or_979; // op=pyc.or +wire pyc_or_981; // op=pyc.or +wire pyc_or_987; // op=pyc.or +wire pyc_or_989; // op=pyc.or +wire pyc_or_997; // op=pyc.or +wire pyc_or_999; // op=pyc.or +wire pyc_xor_1001; // op=pyc.xor +wire pyc_xor_1002; // op=pyc.xor +wire pyc_xor_1011; // op=pyc.xor +wire pyc_xor_1012; // op=pyc.xor +wire pyc_xor_1019; // op=pyc.xor +wire pyc_xor_1020; // op=pyc.xor +wire pyc_xor_1029; // op=pyc.xor +wire pyc_xor_1030; // op=pyc.xor +wire pyc_xor_1037; // op=pyc.xor +wire pyc_xor_1038; // op=pyc.xor +wire pyc_xor_1047; // op=pyc.xor +wire pyc_xor_1048; // op=pyc.xor +wire pyc_xor_1055; // op=pyc.xor +wire pyc_xor_1056; // op=pyc.xor +wire pyc_xor_1065; // op=pyc.xor +wire pyc_xor_1066; // op=pyc.xor +wire pyc_xor_1073; // op=pyc.xor +wire pyc_xor_1074; // op=pyc.xor +wire pyc_xor_108; // op=pyc.xor +wire pyc_xor_1083; // op=pyc.xor +wire pyc_xor_1084; // op=pyc.xor +wire pyc_xor_109; // op=pyc.xor +wire pyc_xor_1091; // op=pyc.xor +wire pyc_xor_1092; // op=pyc.xor +wire pyc_xor_1101; // op=pyc.xor +wire pyc_xor_1102; // op=pyc.xor +wire pyc_xor_1109; // op=pyc.xor +wire pyc_xor_1110; // op=pyc.xor +wire pyc_xor_1119; // op=pyc.xor +wire pyc_xor_1120; // op=pyc.xor +wire pyc_xor_1122; // op=pyc.xor +wire pyc_xor_1123; // op=pyc.xor +wire pyc_xor_1124; // op=pyc.xor +wire pyc_xor_1126; // op=pyc.xor +wire pyc_xor_1127; // op=pyc.xor +wire pyc_xor_1133; // op=pyc.xor +wire pyc_xor_1134; // op=pyc.xor +wire pyc_xor_1140; // op=pyc.xor +wire pyc_xor_1141; // op=pyc.xor +wire pyc_xor_1147; // op=pyc.xor +wire pyc_xor_1148; // op=pyc.xor +wire pyc_xor_1154; // op=pyc.xor +wire pyc_xor_1155; // op=pyc.xor +wire pyc_xor_116; // op=pyc.xor +wire pyc_xor_1161; // op=pyc.xor +wire pyc_xor_1162; // op=pyc.xor +wire pyc_xor_1168; // op=pyc.xor +wire pyc_xor_1169; // op=pyc.xor +wire pyc_xor_117; // op=pyc.xor +wire pyc_xor_1175; // op=pyc.xor +wire pyc_xor_1176; // op=pyc.xor +wire pyc_xor_1182; // op=pyc.xor +wire pyc_xor_1183; // op=pyc.xor +wire pyc_xor_1189; // op=pyc.xor +wire pyc_xor_1190; // op=pyc.xor +wire pyc_xor_1196; // op=pyc.xor +wire pyc_xor_1197; // op=pyc.xor +wire pyc_xor_1203; // op=pyc.xor +wire pyc_xor_1204; // op=pyc.xor +wire pyc_xor_1210; // op=pyc.xor +wire pyc_xor_1211; // op=pyc.xor +wire pyc_xor_1217; // op=pyc.xor +wire pyc_xor_1218; // op=pyc.xor +wire pyc_xor_1224; // op=pyc.xor +wire pyc_xor_1225; // op=pyc.xor +wire pyc_xor_1231; // op=pyc.xor +wire pyc_xor_1232; // op=pyc.xor +wire pyc_xor_1238; // op=pyc.xor +wire pyc_xor_1239; // op=pyc.xor +wire pyc_xor_1245; // op=pyc.xor +wire pyc_xor_1246; // op=pyc.xor +wire pyc_xor_1252; // op=pyc.xor +wire pyc_xor_1253; // op=pyc.xor +wire pyc_xor_1259; // op=pyc.xor +wire pyc_xor_126; // op=pyc.xor +wire pyc_xor_1260; // op=pyc.xor +wire pyc_xor_1266; // op=pyc.xor +wire pyc_xor_1267; // op=pyc.xor +wire pyc_xor_127; // op=pyc.xor +wire pyc_xor_1273; // op=pyc.xor +wire pyc_xor_1274; // op=pyc.xor +wire pyc_xor_1280; // op=pyc.xor +wire pyc_xor_1281; // op=pyc.xor +wire pyc_xor_1287; // op=pyc.xor +wire pyc_xor_1288; // op=pyc.xor +wire pyc_xor_1294; // op=pyc.xor +wire pyc_xor_1295; // op=pyc.xor +wire pyc_xor_13; // op=pyc.xor +wire pyc_xor_1301; // op=pyc.xor +wire pyc_xor_1302; // op=pyc.xor +wire pyc_xor_1308; // op=pyc.xor +wire pyc_xor_1309; // op=pyc.xor +wire pyc_xor_1315; // op=pyc.xor +wire pyc_xor_1316; // op=pyc.xor +wire pyc_xor_1322; // op=pyc.xor +wire pyc_xor_1323; // op=pyc.xor +wire pyc_xor_1329; // op=pyc.xor +wire pyc_xor_1330; // op=pyc.xor +wire pyc_xor_1336; // op=pyc.xor +wire pyc_xor_1337; // op=pyc.xor +wire pyc_xor_134; // op=pyc.xor +wire pyc_xor_1343; // op=pyc.xor +wire pyc_xor_1344; // op=pyc.xor +wire pyc_xor_135; // op=pyc.xor +wire pyc_xor_1350; // op=pyc.xor +wire pyc_xor_1351; // op=pyc.xor +wire pyc_xor_1357; // op=pyc.xor +wire pyc_xor_1358; // op=pyc.xor +wire pyc_xor_1364; // op=pyc.xor +wire pyc_xor_1365; // op=pyc.xor +wire pyc_xor_1371; // op=pyc.xor +wire pyc_xor_1372; // op=pyc.xor +wire pyc_xor_1378; // op=pyc.xor +wire pyc_xor_1379; // op=pyc.xor +wire pyc_xor_1385; // op=pyc.xor +wire pyc_xor_1386; // op=pyc.xor +wire pyc_xor_1392; // op=pyc.xor +wire pyc_xor_1393; // op=pyc.xor +wire pyc_xor_1399; // op=pyc.xor +wire pyc_xor_1400; // op=pyc.xor +wire pyc_xor_1406; // op=pyc.xor +wire pyc_xor_1407; // op=pyc.xor +wire pyc_xor_1413; // op=pyc.xor +wire pyc_xor_1414; // op=pyc.xor +wire pyc_xor_1420; // op=pyc.xor +wire pyc_xor_1421; // op=pyc.xor +wire pyc_xor_1427; // op=pyc.xor +wire pyc_xor_1428; // op=pyc.xor +wire pyc_xor_1434; // op=pyc.xor +wire pyc_xor_1435; // op=pyc.xor +wire pyc_xor_144; // op=pyc.xor +wire pyc_xor_1441; // op=pyc.xor +wire pyc_xor_1442; // op=pyc.xor +wire pyc_xor_1448; // op=pyc.xor +wire pyc_xor_1449; // op=pyc.xor +wire pyc_xor_145; // op=pyc.xor +wire pyc_xor_1455; // op=pyc.xor +wire pyc_xor_1456; // op=pyc.xor +wire pyc_xor_1462; // op=pyc.xor +wire pyc_xor_1463; // op=pyc.xor +wire pyc_xor_1469; // op=pyc.xor +wire pyc_xor_1470; // op=pyc.xor +wire pyc_xor_1476; // op=pyc.xor +wire pyc_xor_1477; // op=pyc.xor +wire pyc_xor_1483; // op=pyc.xor +wire pyc_xor_1484; // op=pyc.xor +wire pyc_xor_1490; // op=pyc.xor +wire pyc_xor_1491; // op=pyc.xor +wire pyc_xor_1497; // op=pyc.xor +wire pyc_xor_1498; // op=pyc.xor +wire pyc_xor_1504; // op=pyc.xor +wire pyc_xor_1505; // op=pyc.xor +wire pyc_xor_1511; // op=pyc.xor +wire pyc_xor_1512; // op=pyc.xor +wire pyc_xor_1518; // op=pyc.xor +wire pyc_xor_1519; // op=pyc.xor +wire pyc_xor_152; // op=pyc.xor +wire pyc_xor_1525; // op=pyc.xor +wire pyc_xor_1526; // op=pyc.xor +wire pyc_xor_153; // op=pyc.xor +wire pyc_xor_1532; // op=pyc.xor +wire pyc_xor_1533; // op=pyc.xor +wire pyc_xor_1539; // op=pyc.xor +wire pyc_xor_1540; // op=pyc.xor +wire pyc_xor_1546; // op=pyc.xor +wire pyc_xor_1547; // op=pyc.xor +wire pyc_xor_1548; // op=pyc.xor +wire pyc_xor_1549; // op=pyc.xor +wire pyc_xor_162; // op=pyc.xor +wire pyc_xor_163; // op=pyc.xor +wire pyc_xor_170; // op=pyc.xor +wire pyc_xor_171; // op=pyc.xor +wire pyc_xor_18; // op=pyc.xor +wire pyc_xor_180; // op=pyc.xor +wire pyc_xor_181; // op=pyc.xor +wire pyc_xor_188; // op=pyc.xor +wire pyc_xor_189; // op=pyc.xor +wire pyc_xor_19; // op=pyc.xor +wire pyc_xor_198; // op=pyc.xor +wire pyc_xor_199; // op=pyc.xor +wire pyc_xor_206; // op=pyc.xor +wire pyc_xor_207; // op=pyc.xor +wire pyc_xor_216; // op=pyc.xor +wire pyc_xor_217; // op=pyc.xor +wire pyc_xor_224; // op=pyc.xor +wire pyc_xor_225; // op=pyc.xor +wire pyc_xor_234; // op=pyc.xor +wire pyc_xor_235; // op=pyc.xor +wire pyc_xor_242; // op=pyc.xor +wire pyc_xor_243; // op=pyc.xor +wire pyc_xor_252; // op=pyc.xor +wire pyc_xor_253; // op=pyc.xor +wire pyc_xor_26; // op=pyc.xor +wire pyc_xor_260; // op=pyc.xor +wire pyc_xor_261; // op=pyc.xor +wire pyc_xor_27; // op=pyc.xor +wire pyc_xor_270; // op=pyc.xor +wire pyc_xor_271; // op=pyc.xor +wire pyc_xor_278; // op=pyc.xor +wire pyc_xor_279; // op=pyc.xor +wire pyc_xor_288; // op=pyc.xor +wire pyc_xor_289; // op=pyc.xor +wire pyc_xor_296; // op=pyc.xor +wire pyc_xor_297; // op=pyc.xor +wire pyc_xor_306; // op=pyc.xor +wire pyc_xor_307; // op=pyc.xor +wire pyc_xor_314; // op=pyc.xor +wire pyc_xor_315; // op=pyc.xor +wire pyc_xor_324; // op=pyc.xor +wire pyc_xor_325; // op=pyc.xor +wire pyc_xor_332; // op=pyc.xor +wire pyc_xor_333; // op=pyc.xor +wire pyc_xor_342; // op=pyc.xor +wire pyc_xor_343; // op=pyc.xor +wire pyc_xor_350; // op=pyc.xor +wire pyc_xor_351; // op=pyc.xor +wire pyc_xor_36; // op=pyc.xor +wire pyc_xor_360; // op=pyc.xor +wire pyc_xor_361; // op=pyc.xor +wire pyc_xor_368; // op=pyc.xor +wire pyc_xor_369; // op=pyc.xor +wire pyc_xor_37; // op=pyc.xor +wire pyc_xor_378; // op=pyc.xor +wire pyc_xor_379; // op=pyc.xor +wire pyc_xor_386; // op=pyc.xor +wire pyc_xor_387; // op=pyc.xor +wire pyc_xor_396; // op=pyc.xor +wire pyc_xor_397; // op=pyc.xor +wire pyc_xor_404; // op=pyc.xor +wire pyc_xor_405; // op=pyc.xor +wire pyc_xor_414; // op=pyc.xor +wire pyc_xor_415; // op=pyc.xor +wire pyc_xor_422; // op=pyc.xor +wire pyc_xor_423; // op=pyc.xor +wire pyc_xor_432; // op=pyc.xor +wire pyc_xor_433; // op=pyc.xor +wire pyc_xor_44; // op=pyc.xor +wire pyc_xor_440; // op=pyc.xor +wire pyc_xor_441; // op=pyc.xor +wire pyc_xor_45; // op=pyc.xor +wire pyc_xor_450; // op=pyc.xor +wire pyc_xor_451; // op=pyc.xor +wire pyc_xor_458; // op=pyc.xor +wire pyc_xor_459; // op=pyc.xor +wire pyc_xor_468; // op=pyc.xor +wire pyc_xor_469; // op=pyc.xor +wire pyc_xor_476; // op=pyc.xor +wire pyc_xor_477; // op=pyc.xor +wire pyc_xor_486; // op=pyc.xor +wire pyc_xor_487; // op=pyc.xor +wire pyc_xor_494; // op=pyc.xor +wire pyc_xor_495; // op=pyc.xor +wire pyc_xor_5; // op=pyc.xor +wire pyc_xor_504; // op=pyc.xor +wire pyc_xor_505; // op=pyc.xor +wire pyc_xor_512; // op=pyc.xor +wire pyc_xor_513; // op=pyc.xor +wire pyc_xor_522; // op=pyc.xor +wire pyc_xor_523; // op=pyc.xor +wire pyc_xor_530; // op=pyc.xor +wire pyc_xor_531; // op=pyc.xor +wire pyc_xor_54; // op=pyc.xor +wire pyc_xor_540; // op=pyc.xor +wire pyc_xor_541; // op=pyc.xor +wire pyc_xor_548; // op=pyc.xor +wire pyc_xor_549; // op=pyc.xor +wire pyc_xor_55; // op=pyc.xor +wire pyc_xor_558; // op=pyc.xor +wire pyc_xor_559; // op=pyc.xor +wire pyc_xor_561; // op=pyc.xor +wire pyc_xor_562; // op=pyc.xor +wire pyc_xor_566; // op=pyc.xor +wire pyc_xor_567; // op=pyc.xor +wire pyc_xor_574; // op=pyc.xor +wire pyc_xor_579; // op=pyc.xor +wire pyc_xor_580; // op=pyc.xor +wire pyc_xor_587; // op=pyc.xor +wire pyc_xor_588; // op=pyc.xor +wire pyc_xor_597; // op=pyc.xor +wire pyc_xor_598; // op=pyc.xor +wire pyc_xor_6; // op=pyc.xor +wire pyc_xor_605; // op=pyc.xor +wire pyc_xor_606; // op=pyc.xor +wire pyc_xor_615; // op=pyc.xor +wire pyc_xor_616; // op=pyc.xor +wire pyc_xor_62; // op=pyc.xor +wire pyc_xor_623; // op=pyc.xor +wire pyc_xor_624; // op=pyc.xor +wire pyc_xor_63; // op=pyc.xor +wire pyc_xor_633; // op=pyc.xor +wire pyc_xor_634; // op=pyc.xor +wire pyc_xor_641; // op=pyc.xor +wire pyc_xor_642; // op=pyc.xor +wire pyc_xor_651; // op=pyc.xor +wire pyc_xor_652; // op=pyc.xor +wire pyc_xor_659; // op=pyc.xor +wire pyc_xor_660; // op=pyc.xor +wire pyc_xor_669; // op=pyc.xor +wire pyc_xor_670; // op=pyc.xor +wire pyc_xor_677; // op=pyc.xor +wire pyc_xor_678; // op=pyc.xor +wire pyc_xor_687; // op=pyc.xor +wire pyc_xor_688; // op=pyc.xor +wire pyc_xor_695; // op=pyc.xor +wire pyc_xor_696; // op=pyc.xor +wire pyc_xor_705; // op=pyc.xor +wire pyc_xor_706; // op=pyc.xor +wire pyc_xor_713; // op=pyc.xor +wire pyc_xor_714; // op=pyc.xor +wire pyc_xor_72; // op=pyc.xor +wire pyc_xor_723; // op=pyc.xor +wire pyc_xor_724; // op=pyc.xor +wire pyc_xor_73; // op=pyc.xor +wire pyc_xor_731; // op=pyc.xor +wire pyc_xor_732; // op=pyc.xor +wire pyc_xor_741; // op=pyc.xor +wire pyc_xor_742; // op=pyc.xor +wire pyc_xor_749; // op=pyc.xor +wire pyc_xor_750; // op=pyc.xor +wire pyc_xor_759; // op=pyc.xor +wire pyc_xor_760; // op=pyc.xor +wire pyc_xor_767; // op=pyc.xor +wire pyc_xor_768; // op=pyc.xor +wire pyc_xor_777; // op=pyc.xor +wire pyc_xor_778; // op=pyc.xor +wire pyc_xor_785; // op=pyc.xor +wire pyc_xor_786; // op=pyc.xor +wire pyc_xor_795; // op=pyc.xor +wire pyc_xor_796; // op=pyc.xor +wire pyc_xor_80; // op=pyc.xor +wire pyc_xor_803; // op=pyc.xor +wire pyc_xor_804; // op=pyc.xor +wire pyc_xor_81; // op=pyc.xor +wire pyc_xor_813; // op=pyc.xor +wire pyc_xor_814; // op=pyc.xor +wire pyc_xor_821; // op=pyc.xor +wire pyc_xor_822; // op=pyc.xor +wire pyc_xor_831; // op=pyc.xor +wire pyc_xor_832; // op=pyc.xor +wire pyc_xor_839; // op=pyc.xor +wire pyc_xor_840; // op=pyc.xor +wire pyc_xor_849; // op=pyc.xor +wire pyc_xor_850; // op=pyc.xor +wire pyc_xor_857; // op=pyc.xor +wire pyc_xor_858; // op=pyc.xor +wire pyc_xor_867; // op=pyc.xor +wire pyc_xor_868; // op=pyc.xor +wire pyc_xor_875; // op=pyc.xor +wire pyc_xor_876; // op=pyc.xor +wire pyc_xor_885; // op=pyc.xor +wire pyc_xor_886; // op=pyc.xor +wire pyc_xor_893; // op=pyc.xor +wire pyc_xor_894; // op=pyc.xor +wire pyc_xor_90; // op=pyc.xor +wire pyc_xor_903; // op=pyc.xor +wire pyc_xor_904; // op=pyc.xor +wire pyc_xor_91; // op=pyc.xor +wire pyc_xor_911; // op=pyc.xor +wire pyc_xor_912; // op=pyc.xor +wire pyc_xor_921; // op=pyc.xor +wire pyc_xor_922; // op=pyc.xor +wire pyc_xor_929; // op=pyc.xor +wire pyc_xor_930; // op=pyc.xor +wire pyc_xor_939; // op=pyc.xor +wire pyc_xor_940; // op=pyc.xor +wire pyc_xor_947; // op=pyc.xor +wire pyc_xor_948; // op=pyc.xor +wire pyc_xor_957; // op=pyc.xor +wire pyc_xor_958; // op=pyc.xor +wire pyc_xor_965; // op=pyc.xor +wire pyc_xor_966; // op=pyc.xor +wire pyc_xor_975; // op=pyc.xor +wire pyc_xor_976; // op=pyc.xor +wire pyc_xor_98; // op=pyc.xor +wire pyc_xor_983; // op=pyc.xor +wire pyc_xor_984; // op=pyc.xor +wire pyc_xor_99; // op=pyc.xor +wire pyc_xor_993; // op=pyc.xor +wire pyc_xor_994; // op=pyc.xor + +// --- Combinational (netlist) +assign pyc_constant_1 = 1'd0; +assign pyc_extract_2 = PE_INT_WALLACE_DOT8_TREE_in0[0]; +assign pyc_extract_3 = PE_INT_WALLACE_DOT8_TREE_in1[0]; +assign pyc_extract_4 = PE_INT_WALLACE_DOT8_TREE_in2[0]; +assign pyc_xor_5 = (pyc_extract_2 ^ pyc_extract_3); +assign pyc_xor_6 = (pyc_xor_5 ^ pyc_extract_4); +assign pyc_and_7 = (pyc_extract_2 & pyc_extract_3); +assign pyc_and_8 = (pyc_extract_2 & pyc_extract_4); +assign pyc_or_9 = (pyc_and_7 | pyc_and_8); +assign pyc_and_10 = (pyc_extract_3 & pyc_extract_4); +assign pyc_or_11 = (pyc_or_9 | pyc_and_10); +assign pyc_extract_12 = PE_INT_WALLACE_DOT8_TREE_in3[0]; +assign pyc_xor_13 = (pyc_xor_6 ^ pyc_extract_12); +assign pyc_and_14 = (pyc_xor_6 & pyc_extract_12); +assign pyc_extract_15 = PE_INT_WALLACE_DOT8_TREE_in0[1]; +assign pyc_extract_16 = PE_INT_WALLACE_DOT8_TREE_in1[1]; +assign pyc_extract_17 = PE_INT_WALLACE_DOT8_TREE_in2[1]; +assign pyc_xor_18 = (pyc_extract_15 ^ pyc_extract_16); +assign pyc_xor_19 = (pyc_xor_18 ^ pyc_extract_17); +assign pyc_and_20 = (pyc_extract_15 & pyc_extract_16); +assign pyc_and_21 = (pyc_extract_15 & pyc_extract_17); +assign pyc_or_22 = (pyc_and_20 | pyc_and_21); +assign pyc_and_23 = (pyc_extract_16 & pyc_extract_17); +assign pyc_or_24 = (pyc_or_22 | pyc_and_23); +assign pyc_extract_25 = PE_INT_WALLACE_DOT8_TREE_in3[1]; +assign pyc_xor_26 = (pyc_xor_19 ^ pyc_extract_25); +assign pyc_xor_27 = (pyc_xor_26 ^ pyc_or_11); +assign pyc_and_28 = (pyc_xor_19 & pyc_extract_25); +assign pyc_and_29 = (pyc_xor_19 & pyc_or_11); +assign pyc_or_30 = (pyc_and_28 | pyc_and_29); +assign pyc_and_31 = (pyc_extract_25 & pyc_or_11); +assign pyc_or_32 = (pyc_or_30 | pyc_and_31); +assign pyc_extract_33 = PE_INT_WALLACE_DOT8_TREE_in0[2]; +assign pyc_extract_34 = PE_INT_WALLACE_DOT8_TREE_in1[2]; +assign pyc_extract_35 = PE_INT_WALLACE_DOT8_TREE_in2[2]; +assign pyc_xor_36 = (pyc_extract_33 ^ pyc_extract_34); +assign pyc_xor_37 = (pyc_xor_36 ^ pyc_extract_35); +assign pyc_and_38 = (pyc_extract_33 & pyc_extract_34); +assign pyc_and_39 = (pyc_extract_33 & pyc_extract_35); +assign pyc_or_40 = (pyc_and_38 | pyc_and_39); +assign pyc_and_41 = (pyc_extract_34 & pyc_extract_35); +assign pyc_or_42 = (pyc_or_40 | pyc_and_41); +assign pyc_extract_43 = PE_INT_WALLACE_DOT8_TREE_in3[2]; +assign pyc_xor_44 = (pyc_xor_37 ^ pyc_extract_43); +assign pyc_xor_45 = (pyc_xor_44 ^ pyc_or_24); +assign pyc_and_46 = (pyc_xor_37 & pyc_extract_43); +assign pyc_and_47 = (pyc_xor_37 & pyc_or_24); +assign pyc_or_48 = (pyc_and_46 | pyc_and_47); +assign pyc_and_49 = (pyc_extract_43 & pyc_or_24); +assign pyc_or_50 = (pyc_or_48 | pyc_and_49); +assign pyc_extract_51 = PE_INT_WALLACE_DOT8_TREE_in0[3]; +assign pyc_extract_52 = PE_INT_WALLACE_DOT8_TREE_in1[3]; +assign pyc_extract_53 = PE_INT_WALLACE_DOT8_TREE_in2[3]; +assign pyc_xor_54 = (pyc_extract_51 ^ pyc_extract_52); +assign pyc_xor_55 = (pyc_xor_54 ^ pyc_extract_53); +assign pyc_and_56 = (pyc_extract_51 & pyc_extract_52); +assign pyc_and_57 = (pyc_extract_51 & pyc_extract_53); +assign pyc_or_58 = (pyc_and_56 | pyc_and_57); +assign pyc_and_59 = (pyc_extract_52 & pyc_extract_53); +assign pyc_or_60 = (pyc_or_58 | pyc_and_59); +assign pyc_extract_61 = PE_INT_WALLACE_DOT8_TREE_in3[3]; +assign pyc_xor_62 = (pyc_xor_55 ^ pyc_extract_61); +assign pyc_xor_63 = (pyc_xor_62 ^ pyc_or_42); +assign pyc_and_64 = (pyc_xor_55 & pyc_extract_61); +assign pyc_and_65 = (pyc_xor_55 & pyc_or_42); +assign pyc_or_66 = (pyc_and_64 | pyc_and_65); +assign pyc_and_67 = (pyc_extract_61 & pyc_or_42); +assign pyc_or_68 = (pyc_or_66 | pyc_and_67); +assign pyc_extract_69 = PE_INT_WALLACE_DOT8_TREE_in0[4]; +assign pyc_extract_70 = PE_INT_WALLACE_DOT8_TREE_in1[4]; +assign pyc_extract_71 = PE_INT_WALLACE_DOT8_TREE_in2[4]; +assign pyc_xor_72 = (pyc_extract_69 ^ pyc_extract_70); +assign pyc_xor_73 = (pyc_xor_72 ^ pyc_extract_71); +assign pyc_and_74 = (pyc_extract_69 & pyc_extract_70); +assign pyc_and_75 = (pyc_extract_69 & pyc_extract_71); +assign pyc_or_76 = (pyc_and_74 | pyc_and_75); +assign pyc_and_77 = (pyc_extract_70 & pyc_extract_71); +assign pyc_or_78 = (pyc_or_76 | pyc_and_77); +assign pyc_extract_79 = PE_INT_WALLACE_DOT8_TREE_in3[4]; +assign pyc_xor_80 = (pyc_xor_73 ^ pyc_extract_79); +assign pyc_xor_81 = (pyc_xor_80 ^ pyc_or_60); +assign pyc_and_82 = (pyc_xor_73 & pyc_extract_79); +assign pyc_and_83 = (pyc_xor_73 & pyc_or_60); +assign pyc_or_84 = (pyc_and_82 | pyc_and_83); +assign pyc_and_85 = (pyc_extract_79 & pyc_or_60); +assign pyc_or_86 = (pyc_or_84 | pyc_and_85); +assign pyc_extract_87 = PE_INT_WALLACE_DOT8_TREE_in0[5]; +assign pyc_extract_88 = PE_INT_WALLACE_DOT8_TREE_in1[5]; +assign pyc_extract_89 = PE_INT_WALLACE_DOT8_TREE_in2[5]; +assign pyc_xor_90 = (pyc_extract_87 ^ pyc_extract_88); +assign pyc_xor_91 = (pyc_xor_90 ^ pyc_extract_89); +assign pyc_and_92 = (pyc_extract_87 & pyc_extract_88); +assign pyc_and_93 = (pyc_extract_87 & pyc_extract_89); +assign pyc_or_94 = (pyc_and_92 | pyc_and_93); +assign pyc_and_95 = (pyc_extract_88 & pyc_extract_89); +assign pyc_or_96 = (pyc_or_94 | pyc_and_95); +assign pyc_extract_97 = PE_INT_WALLACE_DOT8_TREE_in3[5]; +assign pyc_xor_98 = (pyc_xor_91 ^ pyc_extract_97); +assign pyc_xor_99 = (pyc_xor_98 ^ pyc_or_78); +assign pyc_and_100 = (pyc_xor_91 & pyc_extract_97); +assign pyc_and_101 = (pyc_xor_91 & pyc_or_78); +assign pyc_or_102 = (pyc_and_100 | pyc_and_101); +assign pyc_and_103 = (pyc_extract_97 & pyc_or_78); +assign pyc_or_104 = (pyc_or_102 | pyc_and_103); +assign pyc_extract_105 = PE_INT_WALLACE_DOT8_TREE_in0[6]; +assign pyc_extract_106 = PE_INT_WALLACE_DOT8_TREE_in1[6]; +assign pyc_extract_107 = PE_INT_WALLACE_DOT8_TREE_in2[6]; +assign pyc_xor_108 = (pyc_extract_105 ^ pyc_extract_106); +assign pyc_xor_109 = (pyc_xor_108 ^ pyc_extract_107); +assign pyc_and_110 = (pyc_extract_105 & pyc_extract_106); +assign pyc_and_111 = (pyc_extract_105 & pyc_extract_107); +assign pyc_or_112 = (pyc_and_110 | pyc_and_111); +assign pyc_and_113 = (pyc_extract_106 & pyc_extract_107); +assign pyc_or_114 = (pyc_or_112 | pyc_and_113); +assign pyc_extract_115 = PE_INT_WALLACE_DOT8_TREE_in3[6]; +assign pyc_xor_116 = (pyc_xor_109 ^ pyc_extract_115); +assign pyc_xor_117 = (pyc_xor_116 ^ pyc_or_96); +assign pyc_and_118 = (pyc_xor_109 & pyc_extract_115); +assign pyc_and_119 = (pyc_xor_109 & pyc_or_96); +assign pyc_or_120 = (pyc_and_118 | pyc_and_119); +assign pyc_and_121 = (pyc_extract_115 & pyc_or_96); +assign pyc_or_122 = (pyc_or_120 | pyc_and_121); +assign pyc_extract_123 = PE_INT_WALLACE_DOT8_TREE_in0[7]; +assign pyc_extract_124 = PE_INT_WALLACE_DOT8_TREE_in1[7]; +assign pyc_extract_125 = PE_INT_WALLACE_DOT8_TREE_in2[7]; +assign pyc_xor_126 = (pyc_extract_123 ^ pyc_extract_124); +assign pyc_xor_127 = (pyc_xor_126 ^ pyc_extract_125); +assign pyc_and_128 = (pyc_extract_123 & pyc_extract_124); +assign pyc_and_129 = (pyc_extract_123 & pyc_extract_125); +assign pyc_or_130 = (pyc_and_128 | pyc_and_129); +assign pyc_and_131 = (pyc_extract_124 & pyc_extract_125); +assign pyc_or_132 = (pyc_or_130 | pyc_and_131); +assign pyc_extract_133 = PE_INT_WALLACE_DOT8_TREE_in3[7]; +assign pyc_xor_134 = (pyc_xor_127 ^ pyc_extract_133); +assign pyc_xor_135 = (pyc_xor_134 ^ pyc_or_114); +assign pyc_and_136 = (pyc_xor_127 & pyc_extract_133); +assign pyc_and_137 = (pyc_xor_127 & pyc_or_114); +assign pyc_or_138 = (pyc_and_136 | pyc_and_137); +assign pyc_and_139 = (pyc_extract_133 & pyc_or_114); +assign pyc_or_140 = (pyc_or_138 | pyc_and_139); +assign pyc_extract_141 = PE_INT_WALLACE_DOT8_TREE_in0[8]; +assign pyc_extract_142 = PE_INT_WALLACE_DOT8_TREE_in1[8]; +assign pyc_extract_143 = PE_INT_WALLACE_DOT8_TREE_in2[8]; +assign pyc_xor_144 = (pyc_extract_141 ^ pyc_extract_142); +assign pyc_xor_145 = (pyc_xor_144 ^ pyc_extract_143); +assign pyc_and_146 = (pyc_extract_141 & pyc_extract_142); +assign pyc_and_147 = (pyc_extract_141 & pyc_extract_143); +assign pyc_or_148 = (pyc_and_146 | pyc_and_147); +assign pyc_and_149 = (pyc_extract_142 & pyc_extract_143); +assign pyc_or_150 = (pyc_or_148 | pyc_and_149); +assign pyc_extract_151 = PE_INT_WALLACE_DOT8_TREE_in3[8]; +assign pyc_xor_152 = (pyc_xor_145 ^ pyc_extract_151); +assign pyc_xor_153 = (pyc_xor_152 ^ pyc_or_132); +assign pyc_and_154 = (pyc_xor_145 & pyc_extract_151); +assign pyc_and_155 = (pyc_xor_145 & pyc_or_132); +assign pyc_or_156 = (pyc_and_154 | pyc_and_155); +assign pyc_and_157 = (pyc_extract_151 & pyc_or_132); +assign pyc_or_158 = (pyc_or_156 | pyc_and_157); +assign pyc_extract_159 = PE_INT_WALLACE_DOT8_TREE_in0[9]; +assign pyc_extract_160 = PE_INT_WALLACE_DOT8_TREE_in1[9]; +assign pyc_extract_161 = PE_INT_WALLACE_DOT8_TREE_in2[9]; +assign pyc_xor_162 = (pyc_extract_159 ^ pyc_extract_160); +assign pyc_xor_163 = (pyc_xor_162 ^ pyc_extract_161); +assign pyc_and_164 = (pyc_extract_159 & pyc_extract_160); +assign pyc_and_165 = (pyc_extract_159 & pyc_extract_161); +assign pyc_or_166 = (pyc_and_164 | pyc_and_165); +assign pyc_and_167 = (pyc_extract_160 & pyc_extract_161); +assign pyc_or_168 = (pyc_or_166 | pyc_and_167); +assign pyc_extract_169 = PE_INT_WALLACE_DOT8_TREE_in3[9]; +assign pyc_xor_170 = (pyc_xor_163 ^ pyc_extract_169); +assign pyc_xor_171 = (pyc_xor_170 ^ pyc_or_150); +assign pyc_and_172 = (pyc_xor_163 & pyc_extract_169); +assign pyc_and_173 = (pyc_xor_163 & pyc_or_150); +assign pyc_or_174 = (pyc_and_172 | pyc_and_173); +assign pyc_and_175 = (pyc_extract_169 & pyc_or_150); +assign pyc_or_176 = (pyc_or_174 | pyc_and_175); +assign pyc_extract_177 = PE_INT_WALLACE_DOT8_TREE_in0[10]; +assign pyc_extract_178 = PE_INT_WALLACE_DOT8_TREE_in1[10]; +assign pyc_extract_179 = PE_INT_WALLACE_DOT8_TREE_in2[10]; +assign pyc_xor_180 = (pyc_extract_177 ^ pyc_extract_178); +assign pyc_xor_181 = (pyc_xor_180 ^ pyc_extract_179); +assign pyc_and_182 = (pyc_extract_177 & pyc_extract_178); +assign pyc_and_183 = (pyc_extract_177 & pyc_extract_179); +assign pyc_or_184 = (pyc_and_182 | pyc_and_183); +assign pyc_and_185 = (pyc_extract_178 & pyc_extract_179); +assign pyc_or_186 = (pyc_or_184 | pyc_and_185); +assign pyc_extract_187 = PE_INT_WALLACE_DOT8_TREE_in3[10]; +assign pyc_xor_188 = (pyc_xor_181 ^ pyc_extract_187); +assign pyc_xor_189 = (pyc_xor_188 ^ pyc_or_168); +assign pyc_and_190 = (pyc_xor_181 & pyc_extract_187); +assign pyc_and_191 = (pyc_xor_181 & pyc_or_168); +assign pyc_or_192 = (pyc_and_190 | pyc_and_191); +assign pyc_and_193 = (pyc_extract_187 & pyc_or_168); +assign pyc_or_194 = (pyc_or_192 | pyc_and_193); +assign pyc_extract_195 = PE_INT_WALLACE_DOT8_TREE_in0[11]; +assign pyc_extract_196 = PE_INT_WALLACE_DOT8_TREE_in1[11]; +assign pyc_extract_197 = PE_INT_WALLACE_DOT8_TREE_in2[11]; +assign pyc_xor_198 = (pyc_extract_195 ^ pyc_extract_196); +assign pyc_xor_199 = (pyc_xor_198 ^ pyc_extract_197); +assign pyc_and_200 = (pyc_extract_195 & pyc_extract_196); +assign pyc_and_201 = (pyc_extract_195 & pyc_extract_197); +assign pyc_or_202 = (pyc_and_200 | pyc_and_201); +assign pyc_and_203 = (pyc_extract_196 & pyc_extract_197); +assign pyc_or_204 = (pyc_or_202 | pyc_and_203); +assign pyc_extract_205 = PE_INT_WALLACE_DOT8_TREE_in3[11]; +assign pyc_xor_206 = (pyc_xor_199 ^ pyc_extract_205); +assign pyc_xor_207 = (pyc_xor_206 ^ pyc_or_186); +assign pyc_and_208 = (pyc_xor_199 & pyc_extract_205); +assign pyc_and_209 = (pyc_xor_199 & pyc_or_186); +assign pyc_or_210 = (pyc_and_208 | pyc_and_209); +assign pyc_and_211 = (pyc_extract_205 & pyc_or_186); +assign pyc_or_212 = (pyc_or_210 | pyc_and_211); +assign pyc_extract_213 = PE_INT_WALLACE_DOT8_TREE_in0[12]; +assign pyc_extract_214 = PE_INT_WALLACE_DOT8_TREE_in1[12]; +assign pyc_extract_215 = PE_INT_WALLACE_DOT8_TREE_in2[12]; +assign pyc_xor_216 = (pyc_extract_213 ^ pyc_extract_214); +assign pyc_xor_217 = (pyc_xor_216 ^ pyc_extract_215); +assign pyc_and_218 = (pyc_extract_213 & pyc_extract_214); +assign pyc_and_219 = (pyc_extract_213 & pyc_extract_215); +assign pyc_or_220 = (pyc_and_218 | pyc_and_219); +assign pyc_and_221 = (pyc_extract_214 & pyc_extract_215); +assign pyc_or_222 = (pyc_or_220 | pyc_and_221); +assign pyc_extract_223 = PE_INT_WALLACE_DOT8_TREE_in3[12]; +assign pyc_xor_224 = (pyc_xor_217 ^ pyc_extract_223); +assign pyc_xor_225 = (pyc_xor_224 ^ pyc_or_204); +assign pyc_and_226 = (pyc_xor_217 & pyc_extract_223); +assign pyc_and_227 = (pyc_xor_217 & pyc_or_204); +assign pyc_or_228 = (pyc_and_226 | pyc_and_227); +assign pyc_and_229 = (pyc_extract_223 & pyc_or_204); +assign pyc_or_230 = (pyc_or_228 | pyc_and_229); +assign pyc_extract_231 = PE_INT_WALLACE_DOT8_TREE_in0[13]; +assign pyc_extract_232 = PE_INT_WALLACE_DOT8_TREE_in1[13]; +assign pyc_extract_233 = PE_INT_WALLACE_DOT8_TREE_in2[13]; +assign pyc_xor_234 = (pyc_extract_231 ^ pyc_extract_232); +assign pyc_xor_235 = (pyc_xor_234 ^ pyc_extract_233); +assign pyc_and_236 = (pyc_extract_231 & pyc_extract_232); +assign pyc_and_237 = (pyc_extract_231 & pyc_extract_233); +assign pyc_or_238 = (pyc_and_236 | pyc_and_237); +assign pyc_and_239 = (pyc_extract_232 & pyc_extract_233); +assign pyc_or_240 = (pyc_or_238 | pyc_and_239); +assign pyc_extract_241 = PE_INT_WALLACE_DOT8_TREE_in3[13]; +assign pyc_xor_242 = (pyc_xor_235 ^ pyc_extract_241); +assign pyc_xor_243 = (pyc_xor_242 ^ pyc_or_222); +assign pyc_and_244 = (pyc_xor_235 & pyc_extract_241); +assign pyc_and_245 = (pyc_xor_235 & pyc_or_222); +assign pyc_or_246 = (pyc_and_244 | pyc_and_245); +assign pyc_and_247 = (pyc_extract_241 & pyc_or_222); +assign pyc_or_248 = (pyc_or_246 | pyc_and_247); +assign pyc_extract_249 = PE_INT_WALLACE_DOT8_TREE_in0[14]; +assign pyc_extract_250 = PE_INT_WALLACE_DOT8_TREE_in1[14]; +assign pyc_extract_251 = PE_INT_WALLACE_DOT8_TREE_in2[14]; +assign pyc_xor_252 = (pyc_extract_249 ^ pyc_extract_250); +assign pyc_xor_253 = (pyc_xor_252 ^ pyc_extract_251); +assign pyc_and_254 = (pyc_extract_249 & pyc_extract_250); +assign pyc_and_255 = (pyc_extract_249 & pyc_extract_251); +assign pyc_or_256 = (pyc_and_254 | pyc_and_255); +assign pyc_and_257 = (pyc_extract_250 & pyc_extract_251); +assign pyc_or_258 = (pyc_or_256 | pyc_and_257); +assign pyc_extract_259 = PE_INT_WALLACE_DOT8_TREE_in3[14]; +assign pyc_xor_260 = (pyc_xor_253 ^ pyc_extract_259); +assign pyc_xor_261 = (pyc_xor_260 ^ pyc_or_240); +assign pyc_and_262 = (pyc_xor_253 & pyc_extract_259); +assign pyc_and_263 = (pyc_xor_253 & pyc_or_240); +assign pyc_or_264 = (pyc_and_262 | pyc_and_263); +assign pyc_and_265 = (pyc_extract_259 & pyc_or_240); +assign pyc_or_266 = (pyc_or_264 | pyc_and_265); +assign pyc_extract_267 = PE_INT_WALLACE_DOT8_TREE_in0[15]; +assign pyc_extract_268 = PE_INT_WALLACE_DOT8_TREE_in1[15]; +assign pyc_extract_269 = PE_INT_WALLACE_DOT8_TREE_in2[15]; +assign pyc_xor_270 = (pyc_extract_267 ^ pyc_extract_268); +assign pyc_xor_271 = (pyc_xor_270 ^ pyc_extract_269); +assign pyc_and_272 = (pyc_extract_267 & pyc_extract_268); +assign pyc_and_273 = (pyc_extract_267 & pyc_extract_269); +assign pyc_or_274 = (pyc_and_272 | pyc_and_273); +assign pyc_and_275 = (pyc_extract_268 & pyc_extract_269); +assign pyc_or_276 = (pyc_or_274 | pyc_and_275); +assign pyc_extract_277 = PE_INT_WALLACE_DOT8_TREE_in3[15]; +assign pyc_xor_278 = (pyc_xor_271 ^ pyc_extract_277); +assign pyc_xor_279 = (pyc_xor_278 ^ pyc_or_258); +assign pyc_and_280 = (pyc_xor_271 & pyc_extract_277); +assign pyc_and_281 = (pyc_xor_271 & pyc_or_258); +assign pyc_or_282 = (pyc_and_280 | pyc_and_281); +assign pyc_and_283 = (pyc_extract_277 & pyc_or_258); +assign pyc_or_284 = (pyc_or_282 | pyc_and_283); +assign pyc_extract_285 = PE_INT_WALLACE_DOT8_TREE_in0[16]; +assign pyc_extract_286 = PE_INT_WALLACE_DOT8_TREE_in1[16]; +assign pyc_extract_287 = PE_INT_WALLACE_DOT8_TREE_in2[16]; +assign pyc_xor_288 = (pyc_extract_285 ^ pyc_extract_286); +assign pyc_xor_289 = (pyc_xor_288 ^ pyc_extract_287); +assign pyc_and_290 = (pyc_extract_285 & pyc_extract_286); +assign pyc_and_291 = (pyc_extract_285 & pyc_extract_287); +assign pyc_or_292 = (pyc_and_290 | pyc_and_291); +assign pyc_and_293 = (pyc_extract_286 & pyc_extract_287); +assign pyc_or_294 = (pyc_or_292 | pyc_and_293); +assign pyc_extract_295 = PE_INT_WALLACE_DOT8_TREE_in3[16]; +assign pyc_xor_296 = (pyc_xor_289 ^ pyc_extract_295); +assign pyc_xor_297 = (pyc_xor_296 ^ pyc_or_276); +assign pyc_and_298 = (pyc_xor_289 & pyc_extract_295); +assign pyc_and_299 = (pyc_xor_289 & pyc_or_276); +assign pyc_or_300 = (pyc_and_298 | pyc_and_299); +assign pyc_and_301 = (pyc_extract_295 & pyc_or_276); +assign pyc_or_302 = (pyc_or_300 | pyc_and_301); +assign pyc_extract_303 = PE_INT_WALLACE_DOT8_TREE_in0[17]; +assign pyc_extract_304 = PE_INT_WALLACE_DOT8_TREE_in1[17]; +assign pyc_extract_305 = PE_INT_WALLACE_DOT8_TREE_in2[17]; +assign pyc_xor_306 = (pyc_extract_303 ^ pyc_extract_304); +assign pyc_xor_307 = (pyc_xor_306 ^ pyc_extract_305); +assign pyc_and_308 = (pyc_extract_303 & pyc_extract_304); +assign pyc_and_309 = (pyc_extract_303 & pyc_extract_305); +assign pyc_or_310 = (pyc_and_308 | pyc_and_309); +assign pyc_and_311 = (pyc_extract_304 & pyc_extract_305); +assign pyc_or_312 = (pyc_or_310 | pyc_and_311); +assign pyc_extract_313 = PE_INT_WALLACE_DOT8_TREE_in3[17]; +assign pyc_xor_314 = (pyc_xor_307 ^ pyc_extract_313); +assign pyc_xor_315 = (pyc_xor_314 ^ pyc_or_294); +assign pyc_and_316 = (pyc_xor_307 & pyc_extract_313); +assign pyc_and_317 = (pyc_xor_307 & pyc_or_294); +assign pyc_or_318 = (pyc_and_316 | pyc_and_317); +assign pyc_and_319 = (pyc_extract_313 & pyc_or_294); +assign pyc_or_320 = (pyc_or_318 | pyc_and_319); +assign pyc_extract_321 = PE_INT_WALLACE_DOT8_TREE_in0[18]; +assign pyc_extract_322 = PE_INT_WALLACE_DOT8_TREE_in1[18]; +assign pyc_extract_323 = PE_INT_WALLACE_DOT8_TREE_in2[18]; +assign pyc_xor_324 = (pyc_extract_321 ^ pyc_extract_322); +assign pyc_xor_325 = (pyc_xor_324 ^ pyc_extract_323); +assign pyc_and_326 = (pyc_extract_321 & pyc_extract_322); +assign pyc_and_327 = (pyc_extract_321 & pyc_extract_323); +assign pyc_or_328 = (pyc_and_326 | pyc_and_327); +assign pyc_and_329 = (pyc_extract_322 & pyc_extract_323); +assign pyc_or_330 = (pyc_or_328 | pyc_and_329); +assign pyc_extract_331 = PE_INT_WALLACE_DOT8_TREE_in3[18]; +assign pyc_xor_332 = (pyc_xor_325 ^ pyc_extract_331); +assign pyc_xor_333 = (pyc_xor_332 ^ pyc_or_312); +assign pyc_and_334 = (pyc_xor_325 & pyc_extract_331); +assign pyc_and_335 = (pyc_xor_325 & pyc_or_312); +assign pyc_or_336 = (pyc_and_334 | pyc_and_335); +assign pyc_and_337 = (pyc_extract_331 & pyc_or_312); +assign pyc_or_338 = (pyc_or_336 | pyc_and_337); +assign pyc_extract_339 = PE_INT_WALLACE_DOT8_TREE_in0[19]; +assign pyc_extract_340 = PE_INT_WALLACE_DOT8_TREE_in1[19]; +assign pyc_extract_341 = PE_INT_WALLACE_DOT8_TREE_in2[19]; +assign pyc_xor_342 = (pyc_extract_339 ^ pyc_extract_340); +assign pyc_xor_343 = (pyc_xor_342 ^ pyc_extract_341); +assign pyc_and_344 = (pyc_extract_339 & pyc_extract_340); +assign pyc_and_345 = (pyc_extract_339 & pyc_extract_341); +assign pyc_or_346 = (pyc_and_344 | pyc_and_345); +assign pyc_and_347 = (pyc_extract_340 & pyc_extract_341); +assign pyc_or_348 = (pyc_or_346 | pyc_and_347); +assign pyc_extract_349 = PE_INT_WALLACE_DOT8_TREE_in3[19]; +assign pyc_xor_350 = (pyc_xor_343 ^ pyc_extract_349); +assign pyc_xor_351 = (pyc_xor_350 ^ pyc_or_330); +assign pyc_and_352 = (pyc_xor_343 & pyc_extract_349); +assign pyc_and_353 = (pyc_xor_343 & pyc_or_330); +assign pyc_or_354 = (pyc_and_352 | pyc_and_353); +assign pyc_and_355 = (pyc_extract_349 & pyc_or_330); +assign pyc_or_356 = (pyc_or_354 | pyc_and_355); +assign pyc_extract_357 = PE_INT_WALLACE_DOT8_TREE_in0[20]; +assign pyc_extract_358 = PE_INT_WALLACE_DOT8_TREE_in1[20]; +assign pyc_extract_359 = PE_INT_WALLACE_DOT8_TREE_in2[20]; +assign pyc_xor_360 = (pyc_extract_357 ^ pyc_extract_358); +assign pyc_xor_361 = (pyc_xor_360 ^ pyc_extract_359); +assign pyc_and_362 = (pyc_extract_357 & pyc_extract_358); +assign pyc_and_363 = (pyc_extract_357 & pyc_extract_359); +assign pyc_or_364 = (pyc_and_362 | pyc_and_363); +assign pyc_and_365 = (pyc_extract_358 & pyc_extract_359); +assign pyc_or_366 = (pyc_or_364 | pyc_and_365); +assign pyc_extract_367 = PE_INT_WALLACE_DOT8_TREE_in3[20]; +assign pyc_xor_368 = (pyc_xor_361 ^ pyc_extract_367); +assign pyc_xor_369 = (pyc_xor_368 ^ pyc_or_348); +assign pyc_and_370 = (pyc_xor_361 & pyc_extract_367); +assign pyc_and_371 = (pyc_xor_361 & pyc_or_348); +assign pyc_or_372 = (pyc_and_370 | pyc_and_371); +assign pyc_and_373 = (pyc_extract_367 & pyc_or_348); +assign pyc_or_374 = (pyc_or_372 | pyc_and_373); +assign pyc_extract_375 = PE_INT_WALLACE_DOT8_TREE_in0[21]; +assign pyc_extract_376 = PE_INT_WALLACE_DOT8_TREE_in1[21]; +assign pyc_extract_377 = PE_INT_WALLACE_DOT8_TREE_in2[21]; +assign pyc_xor_378 = (pyc_extract_375 ^ pyc_extract_376); +assign pyc_xor_379 = (pyc_xor_378 ^ pyc_extract_377); +assign pyc_and_380 = (pyc_extract_375 & pyc_extract_376); +assign pyc_and_381 = (pyc_extract_375 & pyc_extract_377); +assign pyc_or_382 = (pyc_and_380 | pyc_and_381); +assign pyc_and_383 = (pyc_extract_376 & pyc_extract_377); +assign pyc_or_384 = (pyc_or_382 | pyc_and_383); +assign pyc_extract_385 = PE_INT_WALLACE_DOT8_TREE_in3[21]; +assign pyc_xor_386 = (pyc_xor_379 ^ pyc_extract_385); +assign pyc_xor_387 = (pyc_xor_386 ^ pyc_or_366); +assign pyc_and_388 = (pyc_xor_379 & pyc_extract_385); +assign pyc_and_389 = (pyc_xor_379 & pyc_or_366); +assign pyc_or_390 = (pyc_and_388 | pyc_and_389); +assign pyc_and_391 = (pyc_extract_385 & pyc_or_366); +assign pyc_or_392 = (pyc_or_390 | pyc_and_391); +assign pyc_extract_393 = PE_INT_WALLACE_DOT8_TREE_in0[22]; +assign pyc_extract_394 = PE_INT_WALLACE_DOT8_TREE_in1[22]; +assign pyc_extract_395 = PE_INT_WALLACE_DOT8_TREE_in2[22]; +assign pyc_xor_396 = (pyc_extract_393 ^ pyc_extract_394); +assign pyc_xor_397 = (pyc_xor_396 ^ pyc_extract_395); +assign pyc_and_398 = (pyc_extract_393 & pyc_extract_394); +assign pyc_and_399 = (pyc_extract_393 & pyc_extract_395); +assign pyc_or_400 = (pyc_and_398 | pyc_and_399); +assign pyc_and_401 = (pyc_extract_394 & pyc_extract_395); +assign pyc_or_402 = (pyc_or_400 | pyc_and_401); +assign pyc_extract_403 = PE_INT_WALLACE_DOT8_TREE_in3[22]; +assign pyc_xor_404 = (pyc_xor_397 ^ pyc_extract_403); +assign pyc_xor_405 = (pyc_xor_404 ^ pyc_or_384); +assign pyc_and_406 = (pyc_xor_397 & pyc_extract_403); +assign pyc_and_407 = (pyc_xor_397 & pyc_or_384); +assign pyc_or_408 = (pyc_and_406 | pyc_and_407); +assign pyc_and_409 = (pyc_extract_403 & pyc_or_384); +assign pyc_or_410 = (pyc_or_408 | pyc_and_409); +assign pyc_extract_411 = PE_INT_WALLACE_DOT8_TREE_in0[23]; +assign pyc_extract_412 = PE_INT_WALLACE_DOT8_TREE_in1[23]; +assign pyc_extract_413 = PE_INT_WALLACE_DOT8_TREE_in2[23]; +assign pyc_xor_414 = (pyc_extract_411 ^ pyc_extract_412); +assign pyc_xor_415 = (pyc_xor_414 ^ pyc_extract_413); +assign pyc_and_416 = (pyc_extract_411 & pyc_extract_412); +assign pyc_and_417 = (pyc_extract_411 & pyc_extract_413); +assign pyc_or_418 = (pyc_and_416 | pyc_and_417); +assign pyc_and_419 = (pyc_extract_412 & pyc_extract_413); +assign pyc_or_420 = (pyc_or_418 | pyc_and_419); +assign pyc_extract_421 = PE_INT_WALLACE_DOT8_TREE_in3[23]; +assign pyc_xor_422 = (pyc_xor_415 ^ pyc_extract_421); +assign pyc_xor_423 = (pyc_xor_422 ^ pyc_or_402); +assign pyc_and_424 = (pyc_xor_415 & pyc_extract_421); +assign pyc_and_425 = (pyc_xor_415 & pyc_or_402); +assign pyc_or_426 = (pyc_and_424 | pyc_and_425); +assign pyc_and_427 = (pyc_extract_421 & pyc_or_402); +assign pyc_or_428 = (pyc_or_426 | pyc_and_427); +assign pyc_extract_429 = PE_INT_WALLACE_DOT8_TREE_in0[24]; +assign pyc_extract_430 = PE_INT_WALLACE_DOT8_TREE_in1[24]; +assign pyc_extract_431 = PE_INT_WALLACE_DOT8_TREE_in2[24]; +assign pyc_xor_432 = (pyc_extract_429 ^ pyc_extract_430); +assign pyc_xor_433 = (pyc_xor_432 ^ pyc_extract_431); +assign pyc_and_434 = (pyc_extract_429 & pyc_extract_430); +assign pyc_and_435 = (pyc_extract_429 & pyc_extract_431); +assign pyc_or_436 = (pyc_and_434 | pyc_and_435); +assign pyc_and_437 = (pyc_extract_430 & pyc_extract_431); +assign pyc_or_438 = (pyc_or_436 | pyc_and_437); +assign pyc_extract_439 = PE_INT_WALLACE_DOT8_TREE_in3[24]; +assign pyc_xor_440 = (pyc_xor_433 ^ pyc_extract_439); +assign pyc_xor_441 = (pyc_xor_440 ^ pyc_or_420); +assign pyc_and_442 = (pyc_xor_433 & pyc_extract_439); +assign pyc_and_443 = (pyc_xor_433 & pyc_or_420); +assign pyc_or_444 = (pyc_and_442 | pyc_and_443); +assign pyc_and_445 = (pyc_extract_439 & pyc_or_420); +assign pyc_or_446 = (pyc_or_444 | pyc_and_445); +assign pyc_extract_447 = PE_INT_WALLACE_DOT8_TREE_in0[25]; +assign pyc_extract_448 = PE_INT_WALLACE_DOT8_TREE_in1[25]; +assign pyc_extract_449 = PE_INT_WALLACE_DOT8_TREE_in2[25]; +assign pyc_xor_450 = (pyc_extract_447 ^ pyc_extract_448); +assign pyc_xor_451 = (pyc_xor_450 ^ pyc_extract_449); +assign pyc_and_452 = (pyc_extract_447 & pyc_extract_448); +assign pyc_and_453 = (pyc_extract_447 & pyc_extract_449); +assign pyc_or_454 = (pyc_and_452 | pyc_and_453); +assign pyc_and_455 = (pyc_extract_448 & pyc_extract_449); +assign pyc_or_456 = (pyc_or_454 | pyc_and_455); +assign pyc_extract_457 = PE_INT_WALLACE_DOT8_TREE_in3[25]; +assign pyc_xor_458 = (pyc_xor_451 ^ pyc_extract_457); +assign pyc_xor_459 = (pyc_xor_458 ^ pyc_or_438); +assign pyc_and_460 = (pyc_xor_451 & pyc_extract_457); +assign pyc_and_461 = (pyc_xor_451 & pyc_or_438); +assign pyc_or_462 = (pyc_and_460 | pyc_and_461); +assign pyc_and_463 = (pyc_extract_457 & pyc_or_438); +assign pyc_or_464 = (pyc_or_462 | pyc_and_463); +assign pyc_extract_465 = PE_INT_WALLACE_DOT8_TREE_in0[26]; +assign pyc_extract_466 = PE_INT_WALLACE_DOT8_TREE_in1[26]; +assign pyc_extract_467 = PE_INT_WALLACE_DOT8_TREE_in2[26]; +assign pyc_xor_468 = (pyc_extract_465 ^ pyc_extract_466); +assign pyc_xor_469 = (pyc_xor_468 ^ pyc_extract_467); +assign pyc_and_470 = (pyc_extract_465 & pyc_extract_466); +assign pyc_and_471 = (pyc_extract_465 & pyc_extract_467); +assign pyc_or_472 = (pyc_and_470 | pyc_and_471); +assign pyc_and_473 = (pyc_extract_466 & pyc_extract_467); +assign pyc_or_474 = (pyc_or_472 | pyc_and_473); +assign pyc_extract_475 = PE_INT_WALLACE_DOT8_TREE_in3[26]; +assign pyc_xor_476 = (pyc_xor_469 ^ pyc_extract_475); +assign pyc_xor_477 = (pyc_xor_476 ^ pyc_or_456); +assign pyc_and_478 = (pyc_xor_469 & pyc_extract_475); +assign pyc_and_479 = (pyc_xor_469 & pyc_or_456); +assign pyc_or_480 = (pyc_and_478 | pyc_and_479); +assign pyc_and_481 = (pyc_extract_475 & pyc_or_456); +assign pyc_or_482 = (pyc_or_480 | pyc_and_481); +assign pyc_extract_483 = PE_INT_WALLACE_DOT8_TREE_in0[27]; +assign pyc_extract_484 = PE_INT_WALLACE_DOT8_TREE_in1[27]; +assign pyc_extract_485 = PE_INT_WALLACE_DOT8_TREE_in2[27]; +assign pyc_xor_486 = (pyc_extract_483 ^ pyc_extract_484); +assign pyc_xor_487 = (pyc_xor_486 ^ pyc_extract_485); +assign pyc_and_488 = (pyc_extract_483 & pyc_extract_484); +assign pyc_and_489 = (pyc_extract_483 & pyc_extract_485); +assign pyc_or_490 = (pyc_and_488 | pyc_and_489); +assign pyc_and_491 = (pyc_extract_484 & pyc_extract_485); +assign pyc_or_492 = (pyc_or_490 | pyc_and_491); +assign pyc_extract_493 = PE_INT_WALLACE_DOT8_TREE_in3[27]; +assign pyc_xor_494 = (pyc_xor_487 ^ pyc_extract_493); +assign pyc_xor_495 = (pyc_xor_494 ^ pyc_or_474); +assign pyc_and_496 = (pyc_xor_487 & pyc_extract_493); +assign pyc_and_497 = (pyc_xor_487 & pyc_or_474); +assign pyc_or_498 = (pyc_and_496 | pyc_and_497); +assign pyc_and_499 = (pyc_extract_493 & pyc_or_474); +assign pyc_or_500 = (pyc_or_498 | pyc_and_499); +assign pyc_extract_501 = PE_INT_WALLACE_DOT8_TREE_in0[28]; +assign pyc_extract_502 = PE_INT_WALLACE_DOT8_TREE_in1[28]; +assign pyc_extract_503 = PE_INT_WALLACE_DOT8_TREE_in2[28]; +assign pyc_xor_504 = (pyc_extract_501 ^ pyc_extract_502); +assign pyc_xor_505 = (pyc_xor_504 ^ pyc_extract_503); +assign pyc_and_506 = (pyc_extract_501 & pyc_extract_502); +assign pyc_and_507 = (pyc_extract_501 & pyc_extract_503); +assign pyc_or_508 = (pyc_and_506 | pyc_and_507); +assign pyc_and_509 = (pyc_extract_502 & pyc_extract_503); +assign pyc_or_510 = (pyc_or_508 | pyc_and_509); +assign pyc_extract_511 = PE_INT_WALLACE_DOT8_TREE_in3[28]; +assign pyc_xor_512 = (pyc_xor_505 ^ pyc_extract_511); +assign pyc_xor_513 = (pyc_xor_512 ^ pyc_or_492); +assign pyc_and_514 = (pyc_xor_505 & pyc_extract_511); +assign pyc_and_515 = (pyc_xor_505 & pyc_or_492); +assign pyc_or_516 = (pyc_and_514 | pyc_and_515); +assign pyc_and_517 = (pyc_extract_511 & pyc_or_492); +assign pyc_or_518 = (pyc_or_516 | pyc_and_517); +assign pyc_extract_519 = PE_INT_WALLACE_DOT8_TREE_in0[29]; +assign pyc_extract_520 = PE_INT_WALLACE_DOT8_TREE_in1[29]; +assign pyc_extract_521 = PE_INT_WALLACE_DOT8_TREE_in2[29]; +assign pyc_xor_522 = (pyc_extract_519 ^ pyc_extract_520); +assign pyc_xor_523 = (pyc_xor_522 ^ pyc_extract_521); +assign pyc_and_524 = (pyc_extract_519 & pyc_extract_520); +assign pyc_and_525 = (pyc_extract_519 & pyc_extract_521); +assign pyc_or_526 = (pyc_and_524 | pyc_and_525); +assign pyc_and_527 = (pyc_extract_520 & pyc_extract_521); +assign pyc_or_528 = (pyc_or_526 | pyc_and_527); +assign pyc_extract_529 = PE_INT_WALLACE_DOT8_TREE_in3[29]; +assign pyc_xor_530 = (pyc_xor_523 ^ pyc_extract_529); +assign pyc_xor_531 = (pyc_xor_530 ^ pyc_or_510); +assign pyc_and_532 = (pyc_xor_523 & pyc_extract_529); +assign pyc_and_533 = (pyc_xor_523 & pyc_or_510); +assign pyc_or_534 = (pyc_and_532 | pyc_and_533); +assign pyc_and_535 = (pyc_extract_529 & pyc_or_510); +assign pyc_or_536 = (pyc_or_534 | pyc_and_535); +assign pyc_extract_537 = PE_INT_WALLACE_DOT8_TREE_in0[30]; +assign pyc_extract_538 = PE_INT_WALLACE_DOT8_TREE_in1[30]; +assign pyc_extract_539 = PE_INT_WALLACE_DOT8_TREE_in2[30]; +assign pyc_xor_540 = (pyc_extract_537 ^ pyc_extract_538); +assign pyc_xor_541 = (pyc_xor_540 ^ pyc_extract_539); +assign pyc_and_542 = (pyc_extract_537 & pyc_extract_538); +assign pyc_and_543 = (pyc_extract_537 & pyc_extract_539); +assign pyc_or_544 = (pyc_and_542 | pyc_and_543); +assign pyc_and_545 = (pyc_extract_538 & pyc_extract_539); +assign pyc_or_546 = (pyc_or_544 | pyc_and_545); +assign pyc_extract_547 = PE_INT_WALLACE_DOT8_TREE_in3[30]; +assign pyc_xor_548 = (pyc_xor_541 ^ pyc_extract_547); +assign pyc_xor_549 = (pyc_xor_548 ^ pyc_or_528); +assign pyc_and_550 = (pyc_xor_541 & pyc_extract_547); +assign pyc_and_551 = (pyc_xor_541 & pyc_or_528); +assign pyc_or_552 = (pyc_and_550 | pyc_and_551); +assign pyc_and_553 = (pyc_extract_547 & pyc_or_528); +assign pyc_or_554 = (pyc_or_552 | pyc_and_553); +assign pyc_extract_555 = PE_INT_WALLACE_DOT8_TREE_in0[31]; +assign pyc_extract_556 = PE_INT_WALLACE_DOT8_TREE_in1[31]; +assign pyc_extract_557 = PE_INT_WALLACE_DOT8_TREE_in2[31]; +assign pyc_xor_558 = (pyc_extract_555 ^ pyc_extract_556); +assign pyc_xor_559 = (pyc_xor_558 ^ pyc_extract_557); +assign pyc_extract_560 = PE_INT_WALLACE_DOT8_TREE_in3[31]; +assign pyc_xor_561 = (pyc_xor_559 ^ pyc_extract_560); +assign pyc_xor_562 = (pyc_xor_561 ^ pyc_or_546); +assign pyc_extract_563 = PE_INT_WALLACE_DOT8_TREE_in4[0]; +assign pyc_extract_564 = PE_INT_WALLACE_DOT8_TREE_in5[0]; +assign pyc_extract_565 = PE_INT_WALLACE_DOT8_TREE_in6[0]; +assign pyc_xor_566 = (pyc_extract_563 ^ pyc_extract_564); +assign pyc_xor_567 = (pyc_xor_566 ^ pyc_extract_565); +assign pyc_and_568 = (pyc_extract_563 & pyc_extract_564); +assign pyc_and_569 = (pyc_extract_563 & pyc_extract_565); +assign pyc_or_570 = (pyc_and_568 | pyc_and_569); +assign pyc_and_571 = (pyc_extract_564 & pyc_extract_565); +assign pyc_or_572 = (pyc_or_570 | pyc_and_571); +assign pyc_extract_573 = PE_INT_WALLACE_DOT8_TREE_in7[0]; +assign pyc_xor_574 = (pyc_xor_567 ^ pyc_extract_573); +assign pyc_and_575 = (pyc_xor_567 & pyc_extract_573); +assign pyc_extract_576 = PE_INT_WALLACE_DOT8_TREE_in4[1]; +assign pyc_extract_577 = PE_INT_WALLACE_DOT8_TREE_in5[1]; +assign pyc_extract_578 = PE_INT_WALLACE_DOT8_TREE_in6[1]; +assign pyc_xor_579 = (pyc_extract_576 ^ pyc_extract_577); +assign pyc_xor_580 = (pyc_xor_579 ^ pyc_extract_578); +assign pyc_and_581 = (pyc_extract_576 & pyc_extract_577); +assign pyc_and_582 = (pyc_extract_576 & pyc_extract_578); +assign pyc_or_583 = (pyc_and_581 | pyc_and_582); +assign pyc_and_584 = (pyc_extract_577 & pyc_extract_578); +assign pyc_or_585 = (pyc_or_583 | pyc_and_584); +assign pyc_extract_586 = PE_INT_WALLACE_DOT8_TREE_in7[1]; +assign pyc_xor_587 = (pyc_xor_580 ^ pyc_extract_586); +assign pyc_xor_588 = (pyc_xor_587 ^ pyc_or_572); +assign pyc_and_589 = (pyc_xor_580 & pyc_extract_586); +assign pyc_and_590 = (pyc_xor_580 & pyc_or_572); +assign pyc_or_591 = (pyc_and_589 | pyc_and_590); +assign pyc_and_592 = (pyc_extract_586 & pyc_or_572); +assign pyc_or_593 = (pyc_or_591 | pyc_and_592); +assign pyc_extract_594 = PE_INT_WALLACE_DOT8_TREE_in4[2]; +assign pyc_extract_595 = PE_INT_WALLACE_DOT8_TREE_in5[2]; +assign pyc_extract_596 = PE_INT_WALLACE_DOT8_TREE_in6[2]; +assign pyc_xor_597 = (pyc_extract_594 ^ pyc_extract_595); +assign pyc_xor_598 = (pyc_xor_597 ^ pyc_extract_596); +assign pyc_and_599 = (pyc_extract_594 & pyc_extract_595); +assign pyc_and_600 = (pyc_extract_594 & pyc_extract_596); +assign pyc_or_601 = (pyc_and_599 | pyc_and_600); +assign pyc_and_602 = (pyc_extract_595 & pyc_extract_596); +assign pyc_or_603 = (pyc_or_601 | pyc_and_602); +assign pyc_extract_604 = PE_INT_WALLACE_DOT8_TREE_in7[2]; +assign pyc_xor_605 = (pyc_xor_598 ^ pyc_extract_604); +assign pyc_xor_606 = (pyc_xor_605 ^ pyc_or_585); +assign pyc_and_607 = (pyc_xor_598 & pyc_extract_604); +assign pyc_and_608 = (pyc_xor_598 & pyc_or_585); +assign pyc_or_609 = (pyc_and_607 | pyc_and_608); +assign pyc_and_610 = (pyc_extract_604 & pyc_or_585); +assign pyc_or_611 = (pyc_or_609 | pyc_and_610); +assign pyc_extract_612 = PE_INT_WALLACE_DOT8_TREE_in4[3]; +assign pyc_extract_613 = PE_INT_WALLACE_DOT8_TREE_in5[3]; +assign pyc_extract_614 = PE_INT_WALLACE_DOT8_TREE_in6[3]; +assign pyc_xor_615 = (pyc_extract_612 ^ pyc_extract_613); +assign pyc_xor_616 = (pyc_xor_615 ^ pyc_extract_614); +assign pyc_and_617 = (pyc_extract_612 & pyc_extract_613); +assign pyc_and_618 = (pyc_extract_612 & pyc_extract_614); +assign pyc_or_619 = (pyc_and_617 | pyc_and_618); +assign pyc_and_620 = (pyc_extract_613 & pyc_extract_614); +assign pyc_or_621 = (pyc_or_619 | pyc_and_620); +assign pyc_extract_622 = PE_INT_WALLACE_DOT8_TREE_in7[3]; +assign pyc_xor_623 = (pyc_xor_616 ^ pyc_extract_622); +assign pyc_xor_624 = (pyc_xor_623 ^ pyc_or_603); +assign pyc_and_625 = (pyc_xor_616 & pyc_extract_622); +assign pyc_and_626 = (pyc_xor_616 & pyc_or_603); +assign pyc_or_627 = (pyc_and_625 | pyc_and_626); +assign pyc_and_628 = (pyc_extract_622 & pyc_or_603); +assign pyc_or_629 = (pyc_or_627 | pyc_and_628); +assign pyc_extract_630 = PE_INT_WALLACE_DOT8_TREE_in4[4]; +assign pyc_extract_631 = PE_INT_WALLACE_DOT8_TREE_in5[4]; +assign pyc_extract_632 = PE_INT_WALLACE_DOT8_TREE_in6[4]; +assign pyc_xor_633 = (pyc_extract_630 ^ pyc_extract_631); +assign pyc_xor_634 = (pyc_xor_633 ^ pyc_extract_632); +assign pyc_and_635 = (pyc_extract_630 & pyc_extract_631); +assign pyc_and_636 = (pyc_extract_630 & pyc_extract_632); +assign pyc_or_637 = (pyc_and_635 | pyc_and_636); +assign pyc_and_638 = (pyc_extract_631 & pyc_extract_632); +assign pyc_or_639 = (pyc_or_637 | pyc_and_638); +assign pyc_extract_640 = PE_INT_WALLACE_DOT8_TREE_in7[4]; +assign pyc_xor_641 = (pyc_xor_634 ^ pyc_extract_640); +assign pyc_xor_642 = (pyc_xor_641 ^ pyc_or_621); +assign pyc_and_643 = (pyc_xor_634 & pyc_extract_640); +assign pyc_and_644 = (pyc_xor_634 & pyc_or_621); +assign pyc_or_645 = (pyc_and_643 | pyc_and_644); +assign pyc_and_646 = (pyc_extract_640 & pyc_or_621); +assign pyc_or_647 = (pyc_or_645 | pyc_and_646); +assign pyc_extract_648 = PE_INT_WALLACE_DOT8_TREE_in4[5]; +assign pyc_extract_649 = PE_INT_WALLACE_DOT8_TREE_in5[5]; +assign pyc_extract_650 = PE_INT_WALLACE_DOT8_TREE_in6[5]; +assign pyc_xor_651 = (pyc_extract_648 ^ pyc_extract_649); +assign pyc_xor_652 = (pyc_xor_651 ^ pyc_extract_650); +assign pyc_and_653 = (pyc_extract_648 & pyc_extract_649); +assign pyc_and_654 = (pyc_extract_648 & pyc_extract_650); +assign pyc_or_655 = (pyc_and_653 | pyc_and_654); +assign pyc_and_656 = (pyc_extract_649 & pyc_extract_650); +assign pyc_or_657 = (pyc_or_655 | pyc_and_656); +assign pyc_extract_658 = PE_INT_WALLACE_DOT8_TREE_in7[5]; +assign pyc_xor_659 = (pyc_xor_652 ^ pyc_extract_658); +assign pyc_xor_660 = (pyc_xor_659 ^ pyc_or_639); +assign pyc_and_661 = (pyc_xor_652 & pyc_extract_658); +assign pyc_and_662 = (pyc_xor_652 & pyc_or_639); +assign pyc_or_663 = (pyc_and_661 | pyc_and_662); +assign pyc_and_664 = (pyc_extract_658 & pyc_or_639); +assign pyc_or_665 = (pyc_or_663 | pyc_and_664); +assign pyc_extract_666 = PE_INT_WALLACE_DOT8_TREE_in4[6]; +assign pyc_extract_667 = PE_INT_WALLACE_DOT8_TREE_in5[6]; +assign pyc_extract_668 = PE_INT_WALLACE_DOT8_TREE_in6[6]; +assign pyc_xor_669 = (pyc_extract_666 ^ pyc_extract_667); +assign pyc_xor_670 = (pyc_xor_669 ^ pyc_extract_668); +assign pyc_and_671 = (pyc_extract_666 & pyc_extract_667); +assign pyc_and_672 = (pyc_extract_666 & pyc_extract_668); +assign pyc_or_673 = (pyc_and_671 | pyc_and_672); +assign pyc_and_674 = (pyc_extract_667 & pyc_extract_668); +assign pyc_or_675 = (pyc_or_673 | pyc_and_674); +assign pyc_extract_676 = PE_INT_WALLACE_DOT8_TREE_in7[6]; +assign pyc_xor_677 = (pyc_xor_670 ^ pyc_extract_676); +assign pyc_xor_678 = (pyc_xor_677 ^ pyc_or_657); +assign pyc_and_679 = (pyc_xor_670 & pyc_extract_676); +assign pyc_and_680 = (pyc_xor_670 & pyc_or_657); +assign pyc_or_681 = (pyc_and_679 | pyc_and_680); +assign pyc_and_682 = (pyc_extract_676 & pyc_or_657); +assign pyc_or_683 = (pyc_or_681 | pyc_and_682); +assign pyc_extract_684 = PE_INT_WALLACE_DOT8_TREE_in4[7]; +assign pyc_extract_685 = PE_INT_WALLACE_DOT8_TREE_in5[7]; +assign pyc_extract_686 = PE_INT_WALLACE_DOT8_TREE_in6[7]; +assign pyc_xor_687 = (pyc_extract_684 ^ pyc_extract_685); +assign pyc_xor_688 = (pyc_xor_687 ^ pyc_extract_686); +assign pyc_and_689 = (pyc_extract_684 & pyc_extract_685); +assign pyc_and_690 = (pyc_extract_684 & pyc_extract_686); +assign pyc_or_691 = (pyc_and_689 | pyc_and_690); +assign pyc_and_692 = (pyc_extract_685 & pyc_extract_686); +assign pyc_or_693 = (pyc_or_691 | pyc_and_692); +assign pyc_extract_694 = PE_INT_WALLACE_DOT8_TREE_in7[7]; +assign pyc_xor_695 = (pyc_xor_688 ^ pyc_extract_694); +assign pyc_xor_696 = (pyc_xor_695 ^ pyc_or_675); +assign pyc_and_697 = (pyc_xor_688 & pyc_extract_694); +assign pyc_and_698 = (pyc_xor_688 & pyc_or_675); +assign pyc_or_699 = (pyc_and_697 | pyc_and_698); +assign pyc_and_700 = (pyc_extract_694 & pyc_or_675); +assign pyc_or_701 = (pyc_or_699 | pyc_and_700); +assign pyc_extract_702 = PE_INT_WALLACE_DOT8_TREE_in4[8]; +assign pyc_extract_703 = PE_INT_WALLACE_DOT8_TREE_in5[8]; +assign pyc_extract_704 = PE_INT_WALLACE_DOT8_TREE_in6[8]; +assign pyc_xor_705 = (pyc_extract_702 ^ pyc_extract_703); +assign pyc_xor_706 = (pyc_xor_705 ^ pyc_extract_704); +assign pyc_and_707 = (pyc_extract_702 & pyc_extract_703); +assign pyc_and_708 = (pyc_extract_702 & pyc_extract_704); +assign pyc_or_709 = (pyc_and_707 | pyc_and_708); +assign pyc_and_710 = (pyc_extract_703 & pyc_extract_704); +assign pyc_or_711 = (pyc_or_709 | pyc_and_710); +assign pyc_extract_712 = PE_INT_WALLACE_DOT8_TREE_in7[8]; +assign pyc_xor_713 = (pyc_xor_706 ^ pyc_extract_712); +assign pyc_xor_714 = (pyc_xor_713 ^ pyc_or_693); +assign pyc_and_715 = (pyc_xor_706 & pyc_extract_712); +assign pyc_and_716 = (pyc_xor_706 & pyc_or_693); +assign pyc_or_717 = (pyc_and_715 | pyc_and_716); +assign pyc_and_718 = (pyc_extract_712 & pyc_or_693); +assign pyc_or_719 = (pyc_or_717 | pyc_and_718); +assign pyc_extract_720 = PE_INT_WALLACE_DOT8_TREE_in4[9]; +assign pyc_extract_721 = PE_INT_WALLACE_DOT8_TREE_in5[9]; +assign pyc_extract_722 = PE_INT_WALLACE_DOT8_TREE_in6[9]; +assign pyc_xor_723 = (pyc_extract_720 ^ pyc_extract_721); +assign pyc_xor_724 = (pyc_xor_723 ^ pyc_extract_722); +assign pyc_and_725 = (pyc_extract_720 & pyc_extract_721); +assign pyc_and_726 = (pyc_extract_720 & pyc_extract_722); +assign pyc_or_727 = (pyc_and_725 | pyc_and_726); +assign pyc_and_728 = (pyc_extract_721 & pyc_extract_722); +assign pyc_or_729 = (pyc_or_727 | pyc_and_728); +assign pyc_extract_730 = PE_INT_WALLACE_DOT8_TREE_in7[9]; +assign pyc_xor_731 = (pyc_xor_724 ^ pyc_extract_730); +assign pyc_xor_732 = (pyc_xor_731 ^ pyc_or_711); +assign pyc_and_733 = (pyc_xor_724 & pyc_extract_730); +assign pyc_and_734 = (pyc_xor_724 & pyc_or_711); +assign pyc_or_735 = (pyc_and_733 | pyc_and_734); +assign pyc_and_736 = (pyc_extract_730 & pyc_or_711); +assign pyc_or_737 = (pyc_or_735 | pyc_and_736); +assign pyc_extract_738 = PE_INT_WALLACE_DOT8_TREE_in4[10]; +assign pyc_extract_739 = PE_INT_WALLACE_DOT8_TREE_in5[10]; +assign pyc_extract_740 = PE_INT_WALLACE_DOT8_TREE_in6[10]; +assign pyc_xor_741 = (pyc_extract_738 ^ pyc_extract_739); +assign pyc_xor_742 = (pyc_xor_741 ^ pyc_extract_740); +assign pyc_and_743 = (pyc_extract_738 & pyc_extract_739); +assign pyc_and_744 = (pyc_extract_738 & pyc_extract_740); +assign pyc_or_745 = (pyc_and_743 | pyc_and_744); +assign pyc_and_746 = (pyc_extract_739 & pyc_extract_740); +assign pyc_or_747 = (pyc_or_745 | pyc_and_746); +assign pyc_extract_748 = PE_INT_WALLACE_DOT8_TREE_in7[10]; +assign pyc_xor_749 = (pyc_xor_742 ^ pyc_extract_748); +assign pyc_xor_750 = (pyc_xor_749 ^ pyc_or_729); +assign pyc_and_751 = (pyc_xor_742 & pyc_extract_748); +assign pyc_and_752 = (pyc_xor_742 & pyc_or_729); +assign pyc_or_753 = (pyc_and_751 | pyc_and_752); +assign pyc_and_754 = (pyc_extract_748 & pyc_or_729); +assign pyc_or_755 = (pyc_or_753 | pyc_and_754); +assign pyc_extract_756 = PE_INT_WALLACE_DOT8_TREE_in4[11]; +assign pyc_extract_757 = PE_INT_WALLACE_DOT8_TREE_in5[11]; +assign pyc_extract_758 = PE_INT_WALLACE_DOT8_TREE_in6[11]; +assign pyc_xor_759 = (pyc_extract_756 ^ pyc_extract_757); +assign pyc_xor_760 = (pyc_xor_759 ^ pyc_extract_758); +assign pyc_and_761 = (pyc_extract_756 & pyc_extract_757); +assign pyc_and_762 = (pyc_extract_756 & pyc_extract_758); +assign pyc_or_763 = (pyc_and_761 | pyc_and_762); +assign pyc_and_764 = (pyc_extract_757 & pyc_extract_758); +assign pyc_or_765 = (pyc_or_763 | pyc_and_764); +assign pyc_extract_766 = PE_INT_WALLACE_DOT8_TREE_in7[11]; +assign pyc_xor_767 = (pyc_xor_760 ^ pyc_extract_766); +assign pyc_xor_768 = (pyc_xor_767 ^ pyc_or_747); +assign pyc_and_769 = (pyc_xor_760 & pyc_extract_766); +assign pyc_and_770 = (pyc_xor_760 & pyc_or_747); +assign pyc_or_771 = (pyc_and_769 | pyc_and_770); +assign pyc_and_772 = (pyc_extract_766 & pyc_or_747); +assign pyc_or_773 = (pyc_or_771 | pyc_and_772); +assign pyc_extract_774 = PE_INT_WALLACE_DOT8_TREE_in4[12]; +assign pyc_extract_775 = PE_INT_WALLACE_DOT8_TREE_in5[12]; +assign pyc_extract_776 = PE_INT_WALLACE_DOT8_TREE_in6[12]; +assign pyc_xor_777 = (pyc_extract_774 ^ pyc_extract_775); +assign pyc_xor_778 = (pyc_xor_777 ^ pyc_extract_776); +assign pyc_and_779 = (pyc_extract_774 & pyc_extract_775); +assign pyc_and_780 = (pyc_extract_774 & pyc_extract_776); +assign pyc_or_781 = (pyc_and_779 | pyc_and_780); +assign pyc_and_782 = (pyc_extract_775 & pyc_extract_776); +assign pyc_or_783 = (pyc_or_781 | pyc_and_782); +assign pyc_extract_784 = PE_INT_WALLACE_DOT8_TREE_in7[12]; +assign pyc_xor_785 = (pyc_xor_778 ^ pyc_extract_784); +assign pyc_xor_786 = (pyc_xor_785 ^ pyc_or_765); +assign pyc_and_787 = (pyc_xor_778 & pyc_extract_784); +assign pyc_and_788 = (pyc_xor_778 & pyc_or_765); +assign pyc_or_789 = (pyc_and_787 | pyc_and_788); +assign pyc_and_790 = (pyc_extract_784 & pyc_or_765); +assign pyc_or_791 = (pyc_or_789 | pyc_and_790); +assign pyc_extract_792 = PE_INT_WALLACE_DOT8_TREE_in4[13]; +assign pyc_extract_793 = PE_INT_WALLACE_DOT8_TREE_in5[13]; +assign pyc_extract_794 = PE_INT_WALLACE_DOT8_TREE_in6[13]; +assign pyc_xor_795 = (pyc_extract_792 ^ pyc_extract_793); +assign pyc_xor_796 = (pyc_xor_795 ^ pyc_extract_794); +assign pyc_and_797 = (pyc_extract_792 & pyc_extract_793); +assign pyc_and_798 = (pyc_extract_792 & pyc_extract_794); +assign pyc_or_799 = (pyc_and_797 | pyc_and_798); +assign pyc_and_800 = (pyc_extract_793 & pyc_extract_794); +assign pyc_or_801 = (pyc_or_799 | pyc_and_800); +assign pyc_extract_802 = PE_INT_WALLACE_DOT8_TREE_in7[13]; +assign pyc_xor_803 = (pyc_xor_796 ^ pyc_extract_802); +assign pyc_xor_804 = (pyc_xor_803 ^ pyc_or_783); +assign pyc_and_805 = (pyc_xor_796 & pyc_extract_802); +assign pyc_and_806 = (pyc_xor_796 & pyc_or_783); +assign pyc_or_807 = (pyc_and_805 | pyc_and_806); +assign pyc_and_808 = (pyc_extract_802 & pyc_or_783); +assign pyc_or_809 = (pyc_or_807 | pyc_and_808); +assign pyc_extract_810 = PE_INT_WALLACE_DOT8_TREE_in4[14]; +assign pyc_extract_811 = PE_INT_WALLACE_DOT8_TREE_in5[14]; +assign pyc_extract_812 = PE_INT_WALLACE_DOT8_TREE_in6[14]; +assign pyc_xor_813 = (pyc_extract_810 ^ pyc_extract_811); +assign pyc_xor_814 = (pyc_xor_813 ^ pyc_extract_812); +assign pyc_and_815 = (pyc_extract_810 & pyc_extract_811); +assign pyc_and_816 = (pyc_extract_810 & pyc_extract_812); +assign pyc_or_817 = (pyc_and_815 | pyc_and_816); +assign pyc_and_818 = (pyc_extract_811 & pyc_extract_812); +assign pyc_or_819 = (pyc_or_817 | pyc_and_818); +assign pyc_extract_820 = PE_INT_WALLACE_DOT8_TREE_in7[14]; +assign pyc_xor_821 = (pyc_xor_814 ^ pyc_extract_820); +assign pyc_xor_822 = (pyc_xor_821 ^ pyc_or_801); +assign pyc_and_823 = (pyc_xor_814 & pyc_extract_820); +assign pyc_and_824 = (pyc_xor_814 & pyc_or_801); +assign pyc_or_825 = (pyc_and_823 | pyc_and_824); +assign pyc_and_826 = (pyc_extract_820 & pyc_or_801); +assign pyc_or_827 = (pyc_or_825 | pyc_and_826); +assign pyc_extract_828 = PE_INT_WALLACE_DOT8_TREE_in4[15]; +assign pyc_extract_829 = PE_INT_WALLACE_DOT8_TREE_in5[15]; +assign pyc_extract_830 = PE_INT_WALLACE_DOT8_TREE_in6[15]; +assign pyc_xor_831 = (pyc_extract_828 ^ pyc_extract_829); +assign pyc_xor_832 = (pyc_xor_831 ^ pyc_extract_830); +assign pyc_and_833 = (pyc_extract_828 & pyc_extract_829); +assign pyc_and_834 = (pyc_extract_828 & pyc_extract_830); +assign pyc_or_835 = (pyc_and_833 | pyc_and_834); +assign pyc_and_836 = (pyc_extract_829 & pyc_extract_830); +assign pyc_or_837 = (pyc_or_835 | pyc_and_836); +assign pyc_extract_838 = PE_INT_WALLACE_DOT8_TREE_in7[15]; +assign pyc_xor_839 = (pyc_xor_832 ^ pyc_extract_838); +assign pyc_xor_840 = (pyc_xor_839 ^ pyc_or_819); +assign pyc_and_841 = (pyc_xor_832 & pyc_extract_838); +assign pyc_and_842 = (pyc_xor_832 & pyc_or_819); +assign pyc_or_843 = (pyc_and_841 | pyc_and_842); +assign pyc_and_844 = (pyc_extract_838 & pyc_or_819); +assign pyc_or_845 = (pyc_or_843 | pyc_and_844); +assign pyc_extract_846 = PE_INT_WALLACE_DOT8_TREE_in4[16]; +assign pyc_extract_847 = PE_INT_WALLACE_DOT8_TREE_in5[16]; +assign pyc_extract_848 = PE_INT_WALLACE_DOT8_TREE_in6[16]; +assign pyc_xor_849 = (pyc_extract_846 ^ pyc_extract_847); +assign pyc_xor_850 = (pyc_xor_849 ^ pyc_extract_848); +assign pyc_and_851 = (pyc_extract_846 & pyc_extract_847); +assign pyc_and_852 = (pyc_extract_846 & pyc_extract_848); +assign pyc_or_853 = (pyc_and_851 | pyc_and_852); +assign pyc_and_854 = (pyc_extract_847 & pyc_extract_848); +assign pyc_or_855 = (pyc_or_853 | pyc_and_854); +assign pyc_extract_856 = PE_INT_WALLACE_DOT8_TREE_in7[16]; +assign pyc_xor_857 = (pyc_xor_850 ^ pyc_extract_856); +assign pyc_xor_858 = (pyc_xor_857 ^ pyc_or_837); +assign pyc_and_859 = (pyc_xor_850 & pyc_extract_856); +assign pyc_and_860 = (pyc_xor_850 & pyc_or_837); +assign pyc_or_861 = (pyc_and_859 | pyc_and_860); +assign pyc_and_862 = (pyc_extract_856 & pyc_or_837); +assign pyc_or_863 = (pyc_or_861 | pyc_and_862); +assign pyc_extract_864 = PE_INT_WALLACE_DOT8_TREE_in4[17]; +assign pyc_extract_865 = PE_INT_WALLACE_DOT8_TREE_in5[17]; +assign pyc_extract_866 = PE_INT_WALLACE_DOT8_TREE_in6[17]; +assign pyc_xor_867 = (pyc_extract_864 ^ pyc_extract_865); +assign pyc_xor_868 = (pyc_xor_867 ^ pyc_extract_866); +assign pyc_and_869 = (pyc_extract_864 & pyc_extract_865); +assign pyc_and_870 = (pyc_extract_864 & pyc_extract_866); +assign pyc_or_871 = (pyc_and_869 | pyc_and_870); +assign pyc_and_872 = (pyc_extract_865 & pyc_extract_866); +assign pyc_or_873 = (pyc_or_871 | pyc_and_872); +assign pyc_extract_874 = PE_INT_WALLACE_DOT8_TREE_in7[17]; +assign pyc_xor_875 = (pyc_xor_868 ^ pyc_extract_874); +assign pyc_xor_876 = (pyc_xor_875 ^ pyc_or_855); +assign pyc_and_877 = (pyc_xor_868 & pyc_extract_874); +assign pyc_and_878 = (pyc_xor_868 & pyc_or_855); +assign pyc_or_879 = (pyc_and_877 | pyc_and_878); +assign pyc_and_880 = (pyc_extract_874 & pyc_or_855); +assign pyc_or_881 = (pyc_or_879 | pyc_and_880); +assign pyc_extract_882 = PE_INT_WALLACE_DOT8_TREE_in4[18]; +assign pyc_extract_883 = PE_INT_WALLACE_DOT8_TREE_in5[18]; +assign pyc_extract_884 = PE_INT_WALLACE_DOT8_TREE_in6[18]; +assign pyc_xor_885 = (pyc_extract_882 ^ pyc_extract_883); +assign pyc_xor_886 = (pyc_xor_885 ^ pyc_extract_884); +assign pyc_and_887 = (pyc_extract_882 & pyc_extract_883); +assign pyc_and_888 = (pyc_extract_882 & pyc_extract_884); +assign pyc_or_889 = (pyc_and_887 | pyc_and_888); +assign pyc_and_890 = (pyc_extract_883 & pyc_extract_884); +assign pyc_or_891 = (pyc_or_889 | pyc_and_890); +assign pyc_extract_892 = PE_INT_WALLACE_DOT8_TREE_in7[18]; +assign pyc_xor_893 = (pyc_xor_886 ^ pyc_extract_892); +assign pyc_xor_894 = (pyc_xor_893 ^ pyc_or_873); +assign pyc_and_895 = (pyc_xor_886 & pyc_extract_892); +assign pyc_and_896 = (pyc_xor_886 & pyc_or_873); +assign pyc_or_897 = (pyc_and_895 | pyc_and_896); +assign pyc_and_898 = (pyc_extract_892 & pyc_or_873); +assign pyc_or_899 = (pyc_or_897 | pyc_and_898); +assign pyc_extract_900 = PE_INT_WALLACE_DOT8_TREE_in4[19]; +assign pyc_extract_901 = PE_INT_WALLACE_DOT8_TREE_in5[19]; +assign pyc_extract_902 = PE_INT_WALLACE_DOT8_TREE_in6[19]; +assign pyc_xor_903 = (pyc_extract_900 ^ pyc_extract_901); +assign pyc_xor_904 = (pyc_xor_903 ^ pyc_extract_902); +assign pyc_and_905 = (pyc_extract_900 & pyc_extract_901); +assign pyc_and_906 = (pyc_extract_900 & pyc_extract_902); +assign pyc_or_907 = (pyc_and_905 | pyc_and_906); +assign pyc_and_908 = (pyc_extract_901 & pyc_extract_902); +assign pyc_or_909 = (pyc_or_907 | pyc_and_908); +assign pyc_extract_910 = PE_INT_WALLACE_DOT8_TREE_in7[19]; +assign pyc_xor_911 = (pyc_xor_904 ^ pyc_extract_910); +assign pyc_xor_912 = (pyc_xor_911 ^ pyc_or_891); +assign pyc_and_913 = (pyc_xor_904 & pyc_extract_910); +assign pyc_and_914 = (pyc_xor_904 & pyc_or_891); +assign pyc_or_915 = (pyc_and_913 | pyc_and_914); +assign pyc_and_916 = (pyc_extract_910 & pyc_or_891); +assign pyc_or_917 = (pyc_or_915 | pyc_and_916); +assign pyc_extract_918 = PE_INT_WALLACE_DOT8_TREE_in4[20]; +assign pyc_extract_919 = PE_INT_WALLACE_DOT8_TREE_in5[20]; +assign pyc_extract_920 = PE_INT_WALLACE_DOT8_TREE_in6[20]; +assign pyc_xor_921 = (pyc_extract_918 ^ pyc_extract_919); +assign pyc_xor_922 = (pyc_xor_921 ^ pyc_extract_920); +assign pyc_and_923 = (pyc_extract_918 & pyc_extract_919); +assign pyc_and_924 = (pyc_extract_918 & pyc_extract_920); +assign pyc_or_925 = (pyc_and_923 | pyc_and_924); +assign pyc_and_926 = (pyc_extract_919 & pyc_extract_920); +assign pyc_or_927 = (pyc_or_925 | pyc_and_926); +assign pyc_extract_928 = PE_INT_WALLACE_DOT8_TREE_in7[20]; +assign pyc_xor_929 = (pyc_xor_922 ^ pyc_extract_928); +assign pyc_xor_930 = (pyc_xor_929 ^ pyc_or_909); +assign pyc_and_931 = (pyc_xor_922 & pyc_extract_928); +assign pyc_and_932 = (pyc_xor_922 & pyc_or_909); +assign pyc_or_933 = (pyc_and_931 | pyc_and_932); +assign pyc_and_934 = (pyc_extract_928 & pyc_or_909); +assign pyc_or_935 = (pyc_or_933 | pyc_and_934); +assign pyc_extract_936 = PE_INT_WALLACE_DOT8_TREE_in4[21]; +assign pyc_extract_937 = PE_INT_WALLACE_DOT8_TREE_in5[21]; +assign pyc_extract_938 = PE_INT_WALLACE_DOT8_TREE_in6[21]; +assign pyc_xor_939 = (pyc_extract_936 ^ pyc_extract_937); +assign pyc_xor_940 = (pyc_xor_939 ^ pyc_extract_938); +assign pyc_and_941 = (pyc_extract_936 & pyc_extract_937); +assign pyc_and_942 = (pyc_extract_936 & pyc_extract_938); +assign pyc_or_943 = (pyc_and_941 | pyc_and_942); +assign pyc_and_944 = (pyc_extract_937 & pyc_extract_938); +assign pyc_or_945 = (pyc_or_943 | pyc_and_944); +assign pyc_extract_946 = PE_INT_WALLACE_DOT8_TREE_in7[21]; +assign pyc_xor_947 = (pyc_xor_940 ^ pyc_extract_946); +assign pyc_xor_948 = (pyc_xor_947 ^ pyc_or_927); +assign pyc_and_949 = (pyc_xor_940 & pyc_extract_946); +assign pyc_and_950 = (pyc_xor_940 & pyc_or_927); +assign pyc_or_951 = (pyc_and_949 | pyc_and_950); +assign pyc_and_952 = (pyc_extract_946 & pyc_or_927); +assign pyc_or_953 = (pyc_or_951 | pyc_and_952); +assign pyc_extract_954 = PE_INT_WALLACE_DOT8_TREE_in4[22]; +assign pyc_extract_955 = PE_INT_WALLACE_DOT8_TREE_in5[22]; +assign pyc_extract_956 = PE_INT_WALLACE_DOT8_TREE_in6[22]; +assign pyc_xor_957 = (pyc_extract_954 ^ pyc_extract_955); +assign pyc_xor_958 = (pyc_xor_957 ^ pyc_extract_956); +assign pyc_and_959 = (pyc_extract_954 & pyc_extract_955); +assign pyc_and_960 = (pyc_extract_954 & pyc_extract_956); +assign pyc_or_961 = (pyc_and_959 | pyc_and_960); +assign pyc_and_962 = (pyc_extract_955 & pyc_extract_956); +assign pyc_or_963 = (pyc_or_961 | pyc_and_962); +assign pyc_extract_964 = PE_INT_WALLACE_DOT8_TREE_in7[22]; +assign pyc_xor_965 = (pyc_xor_958 ^ pyc_extract_964); +assign pyc_xor_966 = (pyc_xor_965 ^ pyc_or_945); +assign pyc_and_967 = (pyc_xor_958 & pyc_extract_964); +assign pyc_and_968 = (pyc_xor_958 & pyc_or_945); +assign pyc_or_969 = (pyc_and_967 | pyc_and_968); +assign pyc_and_970 = (pyc_extract_964 & pyc_or_945); +assign pyc_or_971 = (pyc_or_969 | pyc_and_970); +assign pyc_extract_972 = PE_INT_WALLACE_DOT8_TREE_in4[23]; +assign pyc_extract_973 = PE_INT_WALLACE_DOT8_TREE_in5[23]; +assign pyc_extract_974 = PE_INT_WALLACE_DOT8_TREE_in6[23]; +assign pyc_xor_975 = (pyc_extract_972 ^ pyc_extract_973); +assign pyc_xor_976 = (pyc_xor_975 ^ pyc_extract_974); +assign pyc_and_977 = (pyc_extract_972 & pyc_extract_973); +assign pyc_and_978 = (pyc_extract_972 & pyc_extract_974); +assign pyc_or_979 = (pyc_and_977 | pyc_and_978); +assign pyc_and_980 = (pyc_extract_973 & pyc_extract_974); +assign pyc_or_981 = (pyc_or_979 | pyc_and_980); +assign pyc_extract_982 = PE_INT_WALLACE_DOT8_TREE_in7[23]; +assign pyc_xor_983 = (pyc_xor_976 ^ pyc_extract_982); +assign pyc_xor_984 = (pyc_xor_983 ^ pyc_or_963); +assign pyc_and_985 = (pyc_xor_976 & pyc_extract_982); +assign pyc_and_986 = (pyc_xor_976 & pyc_or_963); +assign pyc_or_987 = (pyc_and_985 | pyc_and_986); +assign pyc_and_988 = (pyc_extract_982 & pyc_or_963); +assign pyc_or_989 = (pyc_or_987 | pyc_and_988); +assign pyc_extract_990 = PE_INT_WALLACE_DOT8_TREE_in4[24]; +assign pyc_extract_991 = PE_INT_WALLACE_DOT8_TREE_in5[24]; +assign pyc_extract_992 = PE_INT_WALLACE_DOT8_TREE_in6[24]; +assign pyc_xor_993 = (pyc_extract_990 ^ pyc_extract_991); +assign pyc_xor_994 = (pyc_xor_993 ^ pyc_extract_992); +assign pyc_and_995 = (pyc_extract_990 & pyc_extract_991); +assign pyc_and_996 = (pyc_extract_990 & pyc_extract_992); +assign pyc_or_997 = (pyc_and_995 | pyc_and_996); +assign pyc_and_998 = (pyc_extract_991 & pyc_extract_992); +assign pyc_or_999 = (pyc_or_997 | pyc_and_998); +assign pyc_extract_1000 = PE_INT_WALLACE_DOT8_TREE_in7[24]; +assign pyc_xor_1001 = (pyc_xor_994 ^ pyc_extract_1000); +assign pyc_xor_1002 = (pyc_xor_1001 ^ pyc_or_981); +assign pyc_and_1003 = (pyc_xor_994 & pyc_extract_1000); +assign pyc_and_1004 = (pyc_xor_994 & pyc_or_981); +assign pyc_or_1005 = (pyc_and_1003 | pyc_and_1004); +assign pyc_and_1006 = (pyc_extract_1000 & pyc_or_981); +assign pyc_or_1007 = (pyc_or_1005 | pyc_and_1006); +assign pyc_extract_1008 = PE_INT_WALLACE_DOT8_TREE_in4[25]; +assign pyc_extract_1009 = PE_INT_WALLACE_DOT8_TREE_in5[25]; +assign pyc_extract_1010 = PE_INT_WALLACE_DOT8_TREE_in6[25]; +assign pyc_xor_1011 = (pyc_extract_1008 ^ pyc_extract_1009); +assign pyc_xor_1012 = (pyc_xor_1011 ^ pyc_extract_1010); +assign pyc_and_1013 = (pyc_extract_1008 & pyc_extract_1009); +assign pyc_and_1014 = (pyc_extract_1008 & pyc_extract_1010); +assign pyc_or_1015 = (pyc_and_1013 | pyc_and_1014); +assign pyc_and_1016 = (pyc_extract_1009 & pyc_extract_1010); +assign pyc_or_1017 = (pyc_or_1015 | pyc_and_1016); +assign pyc_extract_1018 = PE_INT_WALLACE_DOT8_TREE_in7[25]; +assign pyc_xor_1019 = (pyc_xor_1012 ^ pyc_extract_1018); +assign pyc_xor_1020 = (pyc_xor_1019 ^ pyc_or_999); +assign pyc_and_1021 = (pyc_xor_1012 & pyc_extract_1018); +assign pyc_and_1022 = (pyc_xor_1012 & pyc_or_999); +assign pyc_or_1023 = (pyc_and_1021 | pyc_and_1022); +assign pyc_and_1024 = (pyc_extract_1018 & pyc_or_999); +assign pyc_or_1025 = (pyc_or_1023 | pyc_and_1024); +assign pyc_extract_1026 = PE_INT_WALLACE_DOT8_TREE_in4[26]; +assign pyc_extract_1027 = PE_INT_WALLACE_DOT8_TREE_in5[26]; +assign pyc_extract_1028 = PE_INT_WALLACE_DOT8_TREE_in6[26]; +assign pyc_xor_1029 = (pyc_extract_1026 ^ pyc_extract_1027); +assign pyc_xor_1030 = (pyc_xor_1029 ^ pyc_extract_1028); +assign pyc_and_1031 = (pyc_extract_1026 & pyc_extract_1027); +assign pyc_and_1032 = (pyc_extract_1026 & pyc_extract_1028); +assign pyc_or_1033 = (pyc_and_1031 | pyc_and_1032); +assign pyc_and_1034 = (pyc_extract_1027 & pyc_extract_1028); +assign pyc_or_1035 = (pyc_or_1033 | pyc_and_1034); +assign pyc_extract_1036 = PE_INT_WALLACE_DOT8_TREE_in7[26]; +assign pyc_xor_1037 = (pyc_xor_1030 ^ pyc_extract_1036); +assign pyc_xor_1038 = (pyc_xor_1037 ^ pyc_or_1017); +assign pyc_and_1039 = (pyc_xor_1030 & pyc_extract_1036); +assign pyc_and_1040 = (pyc_xor_1030 & pyc_or_1017); +assign pyc_or_1041 = (pyc_and_1039 | pyc_and_1040); +assign pyc_and_1042 = (pyc_extract_1036 & pyc_or_1017); +assign pyc_or_1043 = (pyc_or_1041 | pyc_and_1042); +assign pyc_extract_1044 = PE_INT_WALLACE_DOT8_TREE_in4[27]; +assign pyc_extract_1045 = PE_INT_WALLACE_DOT8_TREE_in5[27]; +assign pyc_extract_1046 = PE_INT_WALLACE_DOT8_TREE_in6[27]; +assign pyc_xor_1047 = (pyc_extract_1044 ^ pyc_extract_1045); +assign pyc_xor_1048 = (pyc_xor_1047 ^ pyc_extract_1046); +assign pyc_and_1049 = (pyc_extract_1044 & pyc_extract_1045); +assign pyc_and_1050 = (pyc_extract_1044 & pyc_extract_1046); +assign pyc_or_1051 = (pyc_and_1049 | pyc_and_1050); +assign pyc_and_1052 = (pyc_extract_1045 & pyc_extract_1046); +assign pyc_or_1053 = (pyc_or_1051 | pyc_and_1052); +assign pyc_extract_1054 = PE_INT_WALLACE_DOT8_TREE_in7[27]; +assign pyc_xor_1055 = (pyc_xor_1048 ^ pyc_extract_1054); +assign pyc_xor_1056 = (pyc_xor_1055 ^ pyc_or_1035); +assign pyc_and_1057 = (pyc_xor_1048 & pyc_extract_1054); +assign pyc_and_1058 = (pyc_xor_1048 & pyc_or_1035); +assign pyc_or_1059 = (pyc_and_1057 | pyc_and_1058); +assign pyc_and_1060 = (pyc_extract_1054 & pyc_or_1035); +assign pyc_or_1061 = (pyc_or_1059 | pyc_and_1060); +assign pyc_extract_1062 = PE_INT_WALLACE_DOT8_TREE_in4[28]; +assign pyc_extract_1063 = PE_INT_WALLACE_DOT8_TREE_in5[28]; +assign pyc_extract_1064 = PE_INT_WALLACE_DOT8_TREE_in6[28]; +assign pyc_xor_1065 = (pyc_extract_1062 ^ pyc_extract_1063); +assign pyc_xor_1066 = (pyc_xor_1065 ^ pyc_extract_1064); +assign pyc_and_1067 = (pyc_extract_1062 & pyc_extract_1063); +assign pyc_and_1068 = (pyc_extract_1062 & pyc_extract_1064); +assign pyc_or_1069 = (pyc_and_1067 | pyc_and_1068); +assign pyc_and_1070 = (pyc_extract_1063 & pyc_extract_1064); +assign pyc_or_1071 = (pyc_or_1069 | pyc_and_1070); +assign pyc_extract_1072 = PE_INT_WALLACE_DOT8_TREE_in7[28]; +assign pyc_xor_1073 = (pyc_xor_1066 ^ pyc_extract_1072); +assign pyc_xor_1074 = (pyc_xor_1073 ^ pyc_or_1053); +assign pyc_and_1075 = (pyc_xor_1066 & pyc_extract_1072); +assign pyc_and_1076 = (pyc_xor_1066 & pyc_or_1053); +assign pyc_or_1077 = (pyc_and_1075 | pyc_and_1076); +assign pyc_and_1078 = (pyc_extract_1072 & pyc_or_1053); +assign pyc_or_1079 = (pyc_or_1077 | pyc_and_1078); +assign pyc_extract_1080 = PE_INT_WALLACE_DOT8_TREE_in4[29]; +assign pyc_extract_1081 = PE_INT_WALLACE_DOT8_TREE_in5[29]; +assign pyc_extract_1082 = PE_INT_WALLACE_DOT8_TREE_in6[29]; +assign pyc_xor_1083 = (pyc_extract_1080 ^ pyc_extract_1081); +assign pyc_xor_1084 = (pyc_xor_1083 ^ pyc_extract_1082); +assign pyc_and_1085 = (pyc_extract_1080 & pyc_extract_1081); +assign pyc_and_1086 = (pyc_extract_1080 & pyc_extract_1082); +assign pyc_or_1087 = (pyc_and_1085 | pyc_and_1086); +assign pyc_and_1088 = (pyc_extract_1081 & pyc_extract_1082); +assign pyc_or_1089 = (pyc_or_1087 | pyc_and_1088); +assign pyc_extract_1090 = PE_INT_WALLACE_DOT8_TREE_in7[29]; +assign pyc_xor_1091 = (pyc_xor_1084 ^ pyc_extract_1090); +assign pyc_xor_1092 = (pyc_xor_1091 ^ pyc_or_1071); +assign pyc_and_1093 = (pyc_xor_1084 & pyc_extract_1090); +assign pyc_and_1094 = (pyc_xor_1084 & pyc_or_1071); +assign pyc_or_1095 = (pyc_and_1093 | pyc_and_1094); +assign pyc_and_1096 = (pyc_extract_1090 & pyc_or_1071); +assign pyc_or_1097 = (pyc_or_1095 | pyc_and_1096); +assign pyc_extract_1098 = PE_INT_WALLACE_DOT8_TREE_in4[30]; +assign pyc_extract_1099 = PE_INT_WALLACE_DOT8_TREE_in5[30]; +assign pyc_extract_1100 = PE_INT_WALLACE_DOT8_TREE_in6[30]; +assign pyc_xor_1101 = (pyc_extract_1098 ^ pyc_extract_1099); +assign pyc_xor_1102 = (pyc_xor_1101 ^ pyc_extract_1100); +assign pyc_and_1103 = (pyc_extract_1098 & pyc_extract_1099); +assign pyc_and_1104 = (pyc_extract_1098 & pyc_extract_1100); +assign pyc_or_1105 = (pyc_and_1103 | pyc_and_1104); +assign pyc_and_1106 = (pyc_extract_1099 & pyc_extract_1100); +assign pyc_or_1107 = (pyc_or_1105 | pyc_and_1106); +assign pyc_extract_1108 = PE_INT_WALLACE_DOT8_TREE_in7[30]; +assign pyc_xor_1109 = (pyc_xor_1102 ^ pyc_extract_1108); +assign pyc_xor_1110 = (pyc_xor_1109 ^ pyc_or_1089); +assign pyc_and_1111 = (pyc_xor_1102 & pyc_extract_1108); +assign pyc_and_1112 = (pyc_xor_1102 & pyc_or_1089); +assign pyc_or_1113 = (pyc_and_1111 | pyc_and_1112); +assign pyc_and_1114 = (pyc_extract_1108 & pyc_or_1089); +assign pyc_or_1115 = (pyc_or_1113 | pyc_and_1114); +assign pyc_extract_1116 = PE_INT_WALLACE_DOT8_TREE_in4[31]; +assign pyc_extract_1117 = PE_INT_WALLACE_DOT8_TREE_in5[31]; +assign pyc_extract_1118 = PE_INT_WALLACE_DOT8_TREE_in6[31]; +assign pyc_xor_1119 = (pyc_extract_1116 ^ pyc_extract_1117); +assign pyc_xor_1120 = (pyc_xor_1119 ^ pyc_extract_1118); +assign pyc_extract_1121 = PE_INT_WALLACE_DOT8_TREE_in7[31]; +assign pyc_xor_1122 = (pyc_xor_1120 ^ pyc_extract_1121); +assign pyc_xor_1123 = (pyc_xor_1122 ^ pyc_or_1107); +assign pyc_xor_1124 = (pyc_xor_13 ^ pyc_xor_574); +assign pyc_and_1125 = (pyc_xor_13 & pyc_xor_574); +assign pyc_xor_1126 = (pyc_xor_27 ^ pyc_and_14); +assign pyc_xor_1127 = (pyc_xor_1126 ^ pyc_xor_588); +assign pyc_and_1128 = (pyc_xor_27 & pyc_and_14); +assign pyc_and_1129 = (pyc_xor_27 & pyc_xor_588); +assign pyc_or_1130 = (pyc_and_1128 | pyc_and_1129); +assign pyc_and_1131 = (pyc_and_14 & pyc_xor_588); +assign pyc_or_1132 = (pyc_or_1130 | pyc_and_1131); +assign pyc_xor_1133 = (pyc_xor_1127 ^ pyc_and_575); +assign pyc_xor_1134 = (pyc_xor_1133 ^ pyc_and_1125); +assign pyc_and_1135 = (pyc_xor_1127 & pyc_and_575); +assign pyc_and_1136 = (pyc_xor_1127 & pyc_and_1125); +assign pyc_or_1137 = (pyc_and_1135 | pyc_and_1136); +assign pyc_and_1138 = (pyc_and_575 & pyc_and_1125); +assign pyc_or_1139 = (pyc_or_1137 | pyc_and_1138); +assign pyc_xor_1140 = (pyc_xor_45 ^ pyc_or_32); +assign pyc_xor_1141 = (pyc_xor_1140 ^ pyc_xor_606); +assign pyc_and_1142 = (pyc_xor_45 & pyc_or_32); +assign pyc_and_1143 = (pyc_xor_45 & pyc_xor_606); +assign pyc_or_1144 = (pyc_and_1142 | pyc_and_1143); +assign pyc_and_1145 = (pyc_or_32 & pyc_xor_606); +assign pyc_or_1146 = (pyc_or_1144 | pyc_and_1145); +assign pyc_xor_1147 = (pyc_xor_1141 ^ pyc_or_593); +assign pyc_xor_1148 = (pyc_xor_1147 ^ pyc_or_1132); +assign pyc_and_1149 = (pyc_xor_1141 & pyc_or_593); +assign pyc_and_1150 = (pyc_xor_1141 & pyc_or_1132); +assign pyc_or_1151 = (pyc_and_1149 | pyc_and_1150); +assign pyc_and_1152 = (pyc_or_593 & pyc_or_1132); +assign pyc_or_1153 = (pyc_or_1151 | pyc_and_1152); +assign pyc_xor_1154 = (pyc_xor_63 ^ pyc_or_50); +assign pyc_xor_1155 = (pyc_xor_1154 ^ pyc_xor_624); +assign pyc_and_1156 = (pyc_xor_63 & pyc_or_50); +assign pyc_and_1157 = (pyc_xor_63 & pyc_xor_624); +assign pyc_or_1158 = (pyc_and_1156 | pyc_and_1157); +assign pyc_and_1159 = (pyc_or_50 & pyc_xor_624); +assign pyc_or_1160 = (pyc_or_1158 | pyc_and_1159); +assign pyc_xor_1161 = (pyc_xor_1155 ^ pyc_or_611); +assign pyc_xor_1162 = (pyc_xor_1161 ^ pyc_or_1146); +assign pyc_and_1163 = (pyc_xor_1155 & pyc_or_611); +assign pyc_and_1164 = (pyc_xor_1155 & pyc_or_1146); +assign pyc_or_1165 = (pyc_and_1163 | pyc_and_1164); +assign pyc_and_1166 = (pyc_or_611 & pyc_or_1146); +assign pyc_or_1167 = (pyc_or_1165 | pyc_and_1166); +assign pyc_xor_1168 = (pyc_xor_81 ^ pyc_or_68); +assign pyc_xor_1169 = (pyc_xor_1168 ^ pyc_xor_642); +assign pyc_and_1170 = (pyc_xor_81 & pyc_or_68); +assign pyc_and_1171 = (pyc_xor_81 & pyc_xor_642); +assign pyc_or_1172 = (pyc_and_1170 | pyc_and_1171); +assign pyc_and_1173 = (pyc_or_68 & pyc_xor_642); +assign pyc_or_1174 = (pyc_or_1172 | pyc_and_1173); +assign pyc_xor_1175 = (pyc_xor_1169 ^ pyc_or_629); +assign pyc_xor_1176 = (pyc_xor_1175 ^ pyc_or_1160); +assign pyc_and_1177 = (pyc_xor_1169 & pyc_or_629); +assign pyc_and_1178 = (pyc_xor_1169 & pyc_or_1160); +assign pyc_or_1179 = (pyc_and_1177 | pyc_and_1178); +assign pyc_and_1180 = (pyc_or_629 & pyc_or_1160); +assign pyc_or_1181 = (pyc_or_1179 | pyc_and_1180); +assign pyc_xor_1182 = (pyc_xor_99 ^ pyc_or_86); +assign pyc_xor_1183 = (pyc_xor_1182 ^ pyc_xor_660); +assign pyc_and_1184 = (pyc_xor_99 & pyc_or_86); +assign pyc_and_1185 = (pyc_xor_99 & pyc_xor_660); +assign pyc_or_1186 = (pyc_and_1184 | pyc_and_1185); +assign pyc_and_1187 = (pyc_or_86 & pyc_xor_660); +assign pyc_or_1188 = (pyc_or_1186 | pyc_and_1187); +assign pyc_xor_1189 = (pyc_xor_1183 ^ pyc_or_647); +assign pyc_xor_1190 = (pyc_xor_1189 ^ pyc_or_1174); +assign pyc_and_1191 = (pyc_xor_1183 & pyc_or_647); +assign pyc_and_1192 = (pyc_xor_1183 & pyc_or_1174); +assign pyc_or_1193 = (pyc_and_1191 | pyc_and_1192); +assign pyc_and_1194 = (pyc_or_647 & pyc_or_1174); +assign pyc_or_1195 = (pyc_or_1193 | pyc_and_1194); +assign pyc_xor_1196 = (pyc_xor_117 ^ pyc_or_104); +assign pyc_xor_1197 = (pyc_xor_1196 ^ pyc_xor_678); +assign pyc_and_1198 = (pyc_xor_117 & pyc_or_104); +assign pyc_and_1199 = (pyc_xor_117 & pyc_xor_678); +assign pyc_or_1200 = (pyc_and_1198 | pyc_and_1199); +assign pyc_and_1201 = (pyc_or_104 & pyc_xor_678); +assign pyc_or_1202 = (pyc_or_1200 | pyc_and_1201); +assign pyc_xor_1203 = (pyc_xor_1197 ^ pyc_or_665); +assign pyc_xor_1204 = (pyc_xor_1203 ^ pyc_or_1188); +assign pyc_and_1205 = (pyc_xor_1197 & pyc_or_665); +assign pyc_and_1206 = (pyc_xor_1197 & pyc_or_1188); +assign pyc_or_1207 = (pyc_and_1205 | pyc_and_1206); +assign pyc_and_1208 = (pyc_or_665 & pyc_or_1188); +assign pyc_or_1209 = (pyc_or_1207 | pyc_and_1208); +assign pyc_xor_1210 = (pyc_xor_135 ^ pyc_or_122); +assign pyc_xor_1211 = (pyc_xor_1210 ^ pyc_xor_696); +assign pyc_and_1212 = (pyc_xor_135 & pyc_or_122); +assign pyc_and_1213 = (pyc_xor_135 & pyc_xor_696); +assign pyc_or_1214 = (pyc_and_1212 | pyc_and_1213); +assign pyc_and_1215 = (pyc_or_122 & pyc_xor_696); +assign pyc_or_1216 = (pyc_or_1214 | pyc_and_1215); +assign pyc_xor_1217 = (pyc_xor_1211 ^ pyc_or_683); +assign pyc_xor_1218 = (pyc_xor_1217 ^ pyc_or_1202); +assign pyc_and_1219 = (pyc_xor_1211 & pyc_or_683); +assign pyc_and_1220 = (pyc_xor_1211 & pyc_or_1202); +assign pyc_or_1221 = (pyc_and_1219 | pyc_and_1220); +assign pyc_and_1222 = (pyc_or_683 & pyc_or_1202); +assign pyc_or_1223 = (pyc_or_1221 | pyc_and_1222); +assign pyc_xor_1224 = (pyc_xor_153 ^ pyc_or_140); +assign pyc_xor_1225 = (pyc_xor_1224 ^ pyc_xor_714); +assign pyc_and_1226 = (pyc_xor_153 & pyc_or_140); +assign pyc_and_1227 = (pyc_xor_153 & pyc_xor_714); +assign pyc_or_1228 = (pyc_and_1226 | pyc_and_1227); +assign pyc_and_1229 = (pyc_or_140 & pyc_xor_714); +assign pyc_or_1230 = (pyc_or_1228 | pyc_and_1229); +assign pyc_xor_1231 = (pyc_xor_1225 ^ pyc_or_701); +assign pyc_xor_1232 = (pyc_xor_1231 ^ pyc_or_1216); +assign pyc_and_1233 = (pyc_xor_1225 & pyc_or_701); +assign pyc_and_1234 = (pyc_xor_1225 & pyc_or_1216); +assign pyc_or_1235 = (pyc_and_1233 | pyc_and_1234); +assign pyc_and_1236 = (pyc_or_701 & pyc_or_1216); +assign pyc_or_1237 = (pyc_or_1235 | pyc_and_1236); +assign pyc_xor_1238 = (pyc_xor_171 ^ pyc_or_158); +assign pyc_xor_1239 = (pyc_xor_1238 ^ pyc_xor_732); +assign pyc_and_1240 = (pyc_xor_171 & pyc_or_158); +assign pyc_and_1241 = (pyc_xor_171 & pyc_xor_732); +assign pyc_or_1242 = (pyc_and_1240 | pyc_and_1241); +assign pyc_and_1243 = (pyc_or_158 & pyc_xor_732); +assign pyc_or_1244 = (pyc_or_1242 | pyc_and_1243); +assign pyc_xor_1245 = (pyc_xor_1239 ^ pyc_or_719); +assign pyc_xor_1246 = (pyc_xor_1245 ^ pyc_or_1230); +assign pyc_and_1247 = (pyc_xor_1239 & pyc_or_719); +assign pyc_and_1248 = (pyc_xor_1239 & pyc_or_1230); +assign pyc_or_1249 = (pyc_and_1247 | pyc_and_1248); +assign pyc_and_1250 = (pyc_or_719 & pyc_or_1230); +assign pyc_or_1251 = (pyc_or_1249 | pyc_and_1250); +assign pyc_xor_1252 = (pyc_xor_189 ^ pyc_or_176); +assign pyc_xor_1253 = (pyc_xor_1252 ^ pyc_xor_750); +assign pyc_and_1254 = (pyc_xor_189 & pyc_or_176); +assign pyc_and_1255 = (pyc_xor_189 & pyc_xor_750); +assign pyc_or_1256 = (pyc_and_1254 | pyc_and_1255); +assign pyc_and_1257 = (pyc_or_176 & pyc_xor_750); +assign pyc_or_1258 = (pyc_or_1256 | pyc_and_1257); +assign pyc_xor_1259 = (pyc_xor_1253 ^ pyc_or_737); +assign pyc_xor_1260 = (pyc_xor_1259 ^ pyc_or_1244); +assign pyc_and_1261 = (pyc_xor_1253 & pyc_or_737); +assign pyc_and_1262 = (pyc_xor_1253 & pyc_or_1244); +assign pyc_or_1263 = (pyc_and_1261 | pyc_and_1262); +assign pyc_and_1264 = (pyc_or_737 & pyc_or_1244); +assign pyc_or_1265 = (pyc_or_1263 | pyc_and_1264); +assign pyc_xor_1266 = (pyc_xor_207 ^ pyc_or_194); +assign pyc_xor_1267 = (pyc_xor_1266 ^ pyc_xor_768); +assign pyc_and_1268 = (pyc_xor_207 & pyc_or_194); +assign pyc_and_1269 = (pyc_xor_207 & pyc_xor_768); +assign pyc_or_1270 = (pyc_and_1268 | pyc_and_1269); +assign pyc_and_1271 = (pyc_or_194 & pyc_xor_768); +assign pyc_or_1272 = (pyc_or_1270 | pyc_and_1271); +assign pyc_xor_1273 = (pyc_xor_1267 ^ pyc_or_755); +assign pyc_xor_1274 = (pyc_xor_1273 ^ pyc_or_1258); +assign pyc_and_1275 = (pyc_xor_1267 & pyc_or_755); +assign pyc_and_1276 = (pyc_xor_1267 & pyc_or_1258); +assign pyc_or_1277 = (pyc_and_1275 | pyc_and_1276); +assign pyc_and_1278 = (pyc_or_755 & pyc_or_1258); +assign pyc_or_1279 = (pyc_or_1277 | pyc_and_1278); +assign pyc_xor_1280 = (pyc_xor_225 ^ pyc_or_212); +assign pyc_xor_1281 = (pyc_xor_1280 ^ pyc_xor_786); +assign pyc_and_1282 = (pyc_xor_225 & pyc_or_212); +assign pyc_and_1283 = (pyc_xor_225 & pyc_xor_786); +assign pyc_or_1284 = (pyc_and_1282 | pyc_and_1283); +assign pyc_and_1285 = (pyc_or_212 & pyc_xor_786); +assign pyc_or_1286 = (pyc_or_1284 | pyc_and_1285); +assign pyc_xor_1287 = (pyc_xor_1281 ^ pyc_or_773); +assign pyc_xor_1288 = (pyc_xor_1287 ^ pyc_or_1272); +assign pyc_and_1289 = (pyc_xor_1281 & pyc_or_773); +assign pyc_and_1290 = (pyc_xor_1281 & pyc_or_1272); +assign pyc_or_1291 = (pyc_and_1289 | pyc_and_1290); +assign pyc_and_1292 = (pyc_or_773 & pyc_or_1272); +assign pyc_or_1293 = (pyc_or_1291 | pyc_and_1292); +assign pyc_xor_1294 = (pyc_xor_243 ^ pyc_or_230); +assign pyc_xor_1295 = (pyc_xor_1294 ^ pyc_xor_804); +assign pyc_and_1296 = (pyc_xor_243 & pyc_or_230); +assign pyc_and_1297 = (pyc_xor_243 & pyc_xor_804); +assign pyc_or_1298 = (pyc_and_1296 | pyc_and_1297); +assign pyc_and_1299 = (pyc_or_230 & pyc_xor_804); +assign pyc_or_1300 = (pyc_or_1298 | pyc_and_1299); +assign pyc_xor_1301 = (pyc_xor_1295 ^ pyc_or_791); +assign pyc_xor_1302 = (pyc_xor_1301 ^ pyc_or_1286); +assign pyc_and_1303 = (pyc_xor_1295 & pyc_or_791); +assign pyc_and_1304 = (pyc_xor_1295 & pyc_or_1286); +assign pyc_or_1305 = (pyc_and_1303 | pyc_and_1304); +assign pyc_and_1306 = (pyc_or_791 & pyc_or_1286); +assign pyc_or_1307 = (pyc_or_1305 | pyc_and_1306); +assign pyc_xor_1308 = (pyc_xor_261 ^ pyc_or_248); +assign pyc_xor_1309 = (pyc_xor_1308 ^ pyc_xor_822); +assign pyc_and_1310 = (pyc_xor_261 & pyc_or_248); +assign pyc_and_1311 = (pyc_xor_261 & pyc_xor_822); +assign pyc_or_1312 = (pyc_and_1310 | pyc_and_1311); +assign pyc_and_1313 = (pyc_or_248 & pyc_xor_822); +assign pyc_or_1314 = (pyc_or_1312 | pyc_and_1313); +assign pyc_xor_1315 = (pyc_xor_1309 ^ pyc_or_809); +assign pyc_xor_1316 = (pyc_xor_1315 ^ pyc_or_1300); +assign pyc_and_1317 = (pyc_xor_1309 & pyc_or_809); +assign pyc_and_1318 = (pyc_xor_1309 & pyc_or_1300); +assign pyc_or_1319 = (pyc_and_1317 | pyc_and_1318); +assign pyc_and_1320 = (pyc_or_809 & pyc_or_1300); +assign pyc_or_1321 = (pyc_or_1319 | pyc_and_1320); +assign pyc_xor_1322 = (pyc_xor_279 ^ pyc_or_266); +assign pyc_xor_1323 = (pyc_xor_1322 ^ pyc_xor_840); +assign pyc_and_1324 = (pyc_xor_279 & pyc_or_266); +assign pyc_and_1325 = (pyc_xor_279 & pyc_xor_840); +assign pyc_or_1326 = (pyc_and_1324 | pyc_and_1325); +assign pyc_and_1327 = (pyc_or_266 & pyc_xor_840); +assign pyc_or_1328 = (pyc_or_1326 | pyc_and_1327); +assign pyc_xor_1329 = (pyc_xor_1323 ^ pyc_or_827); +assign pyc_xor_1330 = (pyc_xor_1329 ^ pyc_or_1314); +assign pyc_and_1331 = (pyc_xor_1323 & pyc_or_827); +assign pyc_and_1332 = (pyc_xor_1323 & pyc_or_1314); +assign pyc_or_1333 = (pyc_and_1331 | pyc_and_1332); +assign pyc_and_1334 = (pyc_or_827 & pyc_or_1314); +assign pyc_or_1335 = (pyc_or_1333 | pyc_and_1334); +assign pyc_xor_1336 = (pyc_xor_297 ^ pyc_or_284); +assign pyc_xor_1337 = (pyc_xor_1336 ^ pyc_xor_858); +assign pyc_and_1338 = (pyc_xor_297 & pyc_or_284); +assign pyc_and_1339 = (pyc_xor_297 & pyc_xor_858); +assign pyc_or_1340 = (pyc_and_1338 | pyc_and_1339); +assign pyc_and_1341 = (pyc_or_284 & pyc_xor_858); +assign pyc_or_1342 = (pyc_or_1340 | pyc_and_1341); +assign pyc_xor_1343 = (pyc_xor_1337 ^ pyc_or_845); +assign pyc_xor_1344 = (pyc_xor_1343 ^ pyc_or_1328); +assign pyc_and_1345 = (pyc_xor_1337 & pyc_or_845); +assign pyc_and_1346 = (pyc_xor_1337 & pyc_or_1328); +assign pyc_or_1347 = (pyc_and_1345 | pyc_and_1346); +assign pyc_and_1348 = (pyc_or_845 & pyc_or_1328); +assign pyc_or_1349 = (pyc_or_1347 | pyc_and_1348); +assign pyc_xor_1350 = (pyc_xor_315 ^ pyc_or_302); +assign pyc_xor_1351 = (pyc_xor_1350 ^ pyc_xor_876); +assign pyc_and_1352 = (pyc_xor_315 & pyc_or_302); +assign pyc_and_1353 = (pyc_xor_315 & pyc_xor_876); +assign pyc_or_1354 = (pyc_and_1352 | pyc_and_1353); +assign pyc_and_1355 = (pyc_or_302 & pyc_xor_876); +assign pyc_or_1356 = (pyc_or_1354 | pyc_and_1355); +assign pyc_xor_1357 = (pyc_xor_1351 ^ pyc_or_863); +assign pyc_xor_1358 = (pyc_xor_1357 ^ pyc_or_1342); +assign pyc_and_1359 = (pyc_xor_1351 & pyc_or_863); +assign pyc_and_1360 = (pyc_xor_1351 & pyc_or_1342); +assign pyc_or_1361 = (pyc_and_1359 | pyc_and_1360); +assign pyc_and_1362 = (pyc_or_863 & pyc_or_1342); +assign pyc_or_1363 = (pyc_or_1361 | pyc_and_1362); +assign pyc_xor_1364 = (pyc_xor_333 ^ pyc_or_320); +assign pyc_xor_1365 = (pyc_xor_1364 ^ pyc_xor_894); +assign pyc_and_1366 = (pyc_xor_333 & pyc_or_320); +assign pyc_and_1367 = (pyc_xor_333 & pyc_xor_894); +assign pyc_or_1368 = (pyc_and_1366 | pyc_and_1367); +assign pyc_and_1369 = (pyc_or_320 & pyc_xor_894); +assign pyc_or_1370 = (pyc_or_1368 | pyc_and_1369); +assign pyc_xor_1371 = (pyc_xor_1365 ^ pyc_or_881); +assign pyc_xor_1372 = (pyc_xor_1371 ^ pyc_or_1356); +assign pyc_and_1373 = (pyc_xor_1365 & pyc_or_881); +assign pyc_and_1374 = (pyc_xor_1365 & pyc_or_1356); +assign pyc_or_1375 = (pyc_and_1373 | pyc_and_1374); +assign pyc_and_1376 = (pyc_or_881 & pyc_or_1356); +assign pyc_or_1377 = (pyc_or_1375 | pyc_and_1376); +assign pyc_xor_1378 = (pyc_xor_351 ^ pyc_or_338); +assign pyc_xor_1379 = (pyc_xor_1378 ^ pyc_xor_912); +assign pyc_and_1380 = (pyc_xor_351 & pyc_or_338); +assign pyc_and_1381 = (pyc_xor_351 & pyc_xor_912); +assign pyc_or_1382 = (pyc_and_1380 | pyc_and_1381); +assign pyc_and_1383 = (pyc_or_338 & pyc_xor_912); +assign pyc_or_1384 = (pyc_or_1382 | pyc_and_1383); +assign pyc_xor_1385 = (pyc_xor_1379 ^ pyc_or_899); +assign pyc_xor_1386 = (pyc_xor_1385 ^ pyc_or_1370); +assign pyc_and_1387 = (pyc_xor_1379 & pyc_or_899); +assign pyc_and_1388 = (pyc_xor_1379 & pyc_or_1370); +assign pyc_or_1389 = (pyc_and_1387 | pyc_and_1388); +assign pyc_and_1390 = (pyc_or_899 & pyc_or_1370); +assign pyc_or_1391 = (pyc_or_1389 | pyc_and_1390); +assign pyc_xor_1392 = (pyc_xor_369 ^ pyc_or_356); +assign pyc_xor_1393 = (pyc_xor_1392 ^ pyc_xor_930); +assign pyc_and_1394 = (pyc_xor_369 & pyc_or_356); +assign pyc_and_1395 = (pyc_xor_369 & pyc_xor_930); +assign pyc_or_1396 = (pyc_and_1394 | pyc_and_1395); +assign pyc_and_1397 = (pyc_or_356 & pyc_xor_930); +assign pyc_or_1398 = (pyc_or_1396 | pyc_and_1397); +assign pyc_xor_1399 = (pyc_xor_1393 ^ pyc_or_917); +assign pyc_xor_1400 = (pyc_xor_1399 ^ pyc_or_1384); +assign pyc_and_1401 = (pyc_xor_1393 & pyc_or_917); +assign pyc_and_1402 = (pyc_xor_1393 & pyc_or_1384); +assign pyc_or_1403 = (pyc_and_1401 | pyc_and_1402); +assign pyc_and_1404 = (pyc_or_917 & pyc_or_1384); +assign pyc_or_1405 = (pyc_or_1403 | pyc_and_1404); +assign pyc_xor_1406 = (pyc_xor_387 ^ pyc_or_374); +assign pyc_xor_1407 = (pyc_xor_1406 ^ pyc_xor_948); +assign pyc_and_1408 = (pyc_xor_387 & pyc_or_374); +assign pyc_and_1409 = (pyc_xor_387 & pyc_xor_948); +assign pyc_or_1410 = (pyc_and_1408 | pyc_and_1409); +assign pyc_and_1411 = (pyc_or_374 & pyc_xor_948); +assign pyc_or_1412 = (pyc_or_1410 | pyc_and_1411); +assign pyc_xor_1413 = (pyc_xor_1407 ^ pyc_or_935); +assign pyc_xor_1414 = (pyc_xor_1413 ^ pyc_or_1398); +assign pyc_and_1415 = (pyc_xor_1407 & pyc_or_935); +assign pyc_and_1416 = (pyc_xor_1407 & pyc_or_1398); +assign pyc_or_1417 = (pyc_and_1415 | pyc_and_1416); +assign pyc_and_1418 = (pyc_or_935 & pyc_or_1398); +assign pyc_or_1419 = (pyc_or_1417 | pyc_and_1418); +assign pyc_xor_1420 = (pyc_xor_405 ^ pyc_or_392); +assign pyc_xor_1421 = (pyc_xor_1420 ^ pyc_xor_966); +assign pyc_and_1422 = (pyc_xor_405 & pyc_or_392); +assign pyc_and_1423 = (pyc_xor_405 & pyc_xor_966); +assign pyc_or_1424 = (pyc_and_1422 | pyc_and_1423); +assign pyc_and_1425 = (pyc_or_392 & pyc_xor_966); +assign pyc_or_1426 = (pyc_or_1424 | pyc_and_1425); +assign pyc_xor_1427 = (pyc_xor_1421 ^ pyc_or_953); +assign pyc_xor_1428 = (pyc_xor_1427 ^ pyc_or_1412); +assign pyc_and_1429 = (pyc_xor_1421 & pyc_or_953); +assign pyc_and_1430 = (pyc_xor_1421 & pyc_or_1412); +assign pyc_or_1431 = (pyc_and_1429 | pyc_and_1430); +assign pyc_and_1432 = (pyc_or_953 & pyc_or_1412); +assign pyc_or_1433 = (pyc_or_1431 | pyc_and_1432); +assign pyc_xor_1434 = (pyc_xor_423 ^ pyc_or_410); +assign pyc_xor_1435 = (pyc_xor_1434 ^ pyc_xor_984); +assign pyc_and_1436 = (pyc_xor_423 & pyc_or_410); +assign pyc_and_1437 = (pyc_xor_423 & pyc_xor_984); +assign pyc_or_1438 = (pyc_and_1436 | pyc_and_1437); +assign pyc_and_1439 = (pyc_or_410 & pyc_xor_984); +assign pyc_or_1440 = (pyc_or_1438 | pyc_and_1439); +assign pyc_xor_1441 = (pyc_xor_1435 ^ pyc_or_971); +assign pyc_xor_1442 = (pyc_xor_1441 ^ pyc_or_1426); +assign pyc_and_1443 = (pyc_xor_1435 & pyc_or_971); +assign pyc_and_1444 = (pyc_xor_1435 & pyc_or_1426); +assign pyc_or_1445 = (pyc_and_1443 | pyc_and_1444); +assign pyc_and_1446 = (pyc_or_971 & pyc_or_1426); +assign pyc_or_1447 = (pyc_or_1445 | pyc_and_1446); +assign pyc_xor_1448 = (pyc_xor_441 ^ pyc_or_428); +assign pyc_xor_1449 = (pyc_xor_1448 ^ pyc_xor_1002); +assign pyc_and_1450 = (pyc_xor_441 & pyc_or_428); +assign pyc_and_1451 = (pyc_xor_441 & pyc_xor_1002); +assign pyc_or_1452 = (pyc_and_1450 | pyc_and_1451); +assign pyc_and_1453 = (pyc_or_428 & pyc_xor_1002); +assign pyc_or_1454 = (pyc_or_1452 | pyc_and_1453); +assign pyc_xor_1455 = (pyc_xor_1449 ^ pyc_or_989); +assign pyc_xor_1456 = (pyc_xor_1455 ^ pyc_or_1440); +assign pyc_and_1457 = (pyc_xor_1449 & pyc_or_989); +assign pyc_and_1458 = (pyc_xor_1449 & pyc_or_1440); +assign pyc_or_1459 = (pyc_and_1457 | pyc_and_1458); +assign pyc_and_1460 = (pyc_or_989 & pyc_or_1440); +assign pyc_or_1461 = (pyc_or_1459 | pyc_and_1460); +assign pyc_xor_1462 = (pyc_xor_459 ^ pyc_or_446); +assign pyc_xor_1463 = (pyc_xor_1462 ^ pyc_xor_1020); +assign pyc_and_1464 = (pyc_xor_459 & pyc_or_446); +assign pyc_and_1465 = (pyc_xor_459 & pyc_xor_1020); +assign pyc_or_1466 = (pyc_and_1464 | pyc_and_1465); +assign pyc_and_1467 = (pyc_or_446 & pyc_xor_1020); +assign pyc_or_1468 = (pyc_or_1466 | pyc_and_1467); +assign pyc_xor_1469 = (pyc_xor_1463 ^ pyc_or_1007); +assign pyc_xor_1470 = (pyc_xor_1469 ^ pyc_or_1454); +assign pyc_and_1471 = (pyc_xor_1463 & pyc_or_1007); +assign pyc_and_1472 = (pyc_xor_1463 & pyc_or_1454); +assign pyc_or_1473 = (pyc_and_1471 | pyc_and_1472); +assign pyc_and_1474 = (pyc_or_1007 & pyc_or_1454); +assign pyc_or_1475 = (pyc_or_1473 | pyc_and_1474); +assign pyc_xor_1476 = (pyc_xor_477 ^ pyc_or_464); +assign pyc_xor_1477 = (pyc_xor_1476 ^ pyc_xor_1038); +assign pyc_and_1478 = (pyc_xor_477 & pyc_or_464); +assign pyc_and_1479 = (pyc_xor_477 & pyc_xor_1038); +assign pyc_or_1480 = (pyc_and_1478 | pyc_and_1479); +assign pyc_and_1481 = (pyc_or_464 & pyc_xor_1038); +assign pyc_or_1482 = (pyc_or_1480 | pyc_and_1481); +assign pyc_xor_1483 = (pyc_xor_1477 ^ pyc_or_1025); +assign pyc_xor_1484 = (pyc_xor_1483 ^ pyc_or_1468); +assign pyc_and_1485 = (pyc_xor_1477 & pyc_or_1025); +assign pyc_and_1486 = (pyc_xor_1477 & pyc_or_1468); +assign pyc_or_1487 = (pyc_and_1485 | pyc_and_1486); +assign pyc_and_1488 = (pyc_or_1025 & pyc_or_1468); +assign pyc_or_1489 = (pyc_or_1487 | pyc_and_1488); +assign pyc_xor_1490 = (pyc_xor_495 ^ pyc_or_482); +assign pyc_xor_1491 = (pyc_xor_1490 ^ pyc_xor_1056); +assign pyc_and_1492 = (pyc_xor_495 & pyc_or_482); +assign pyc_and_1493 = (pyc_xor_495 & pyc_xor_1056); +assign pyc_or_1494 = (pyc_and_1492 | pyc_and_1493); +assign pyc_and_1495 = (pyc_or_482 & pyc_xor_1056); +assign pyc_or_1496 = (pyc_or_1494 | pyc_and_1495); +assign pyc_xor_1497 = (pyc_xor_1491 ^ pyc_or_1043); +assign pyc_xor_1498 = (pyc_xor_1497 ^ pyc_or_1482); +assign pyc_and_1499 = (pyc_xor_1491 & pyc_or_1043); +assign pyc_and_1500 = (pyc_xor_1491 & pyc_or_1482); +assign pyc_or_1501 = (pyc_and_1499 | pyc_and_1500); +assign pyc_and_1502 = (pyc_or_1043 & pyc_or_1482); +assign pyc_or_1503 = (pyc_or_1501 | pyc_and_1502); +assign pyc_xor_1504 = (pyc_xor_513 ^ pyc_or_500); +assign pyc_xor_1505 = (pyc_xor_1504 ^ pyc_xor_1074); +assign pyc_and_1506 = (pyc_xor_513 & pyc_or_500); +assign pyc_and_1507 = (pyc_xor_513 & pyc_xor_1074); +assign pyc_or_1508 = (pyc_and_1506 | pyc_and_1507); +assign pyc_and_1509 = (pyc_or_500 & pyc_xor_1074); +assign pyc_or_1510 = (pyc_or_1508 | pyc_and_1509); +assign pyc_xor_1511 = (pyc_xor_1505 ^ pyc_or_1061); +assign pyc_xor_1512 = (pyc_xor_1511 ^ pyc_or_1496); +assign pyc_and_1513 = (pyc_xor_1505 & pyc_or_1061); +assign pyc_and_1514 = (pyc_xor_1505 & pyc_or_1496); +assign pyc_or_1515 = (pyc_and_1513 | pyc_and_1514); +assign pyc_and_1516 = (pyc_or_1061 & pyc_or_1496); +assign pyc_or_1517 = (pyc_or_1515 | pyc_and_1516); +assign pyc_xor_1518 = (pyc_xor_531 ^ pyc_or_518); +assign pyc_xor_1519 = (pyc_xor_1518 ^ pyc_xor_1092); +assign pyc_and_1520 = (pyc_xor_531 & pyc_or_518); +assign pyc_and_1521 = (pyc_xor_531 & pyc_xor_1092); +assign pyc_or_1522 = (pyc_and_1520 | pyc_and_1521); +assign pyc_and_1523 = (pyc_or_518 & pyc_xor_1092); +assign pyc_or_1524 = (pyc_or_1522 | pyc_and_1523); +assign pyc_xor_1525 = (pyc_xor_1519 ^ pyc_or_1079); +assign pyc_xor_1526 = (pyc_xor_1525 ^ pyc_or_1510); +assign pyc_and_1527 = (pyc_xor_1519 & pyc_or_1079); +assign pyc_and_1528 = (pyc_xor_1519 & pyc_or_1510); +assign pyc_or_1529 = (pyc_and_1527 | pyc_and_1528); +assign pyc_and_1530 = (pyc_or_1079 & pyc_or_1510); +assign pyc_or_1531 = (pyc_or_1529 | pyc_and_1530); +assign pyc_xor_1532 = (pyc_xor_549 ^ pyc_or_536); +assign pyc_xor_1533 = (pyc_xor_1532 ^ pyc_xor_1110); +assign pyc_and_1534 = (pyc_xor_549 & pyc_or_536); +assign pyc_and_1535 = (pyc_xor_549 & pyc_xor_1110); +assign pyc_or_1536 = (pyc_and_1534 | pyc_and_1535); +assign pyc_and_1537 = (pyc_or_536 & pyc_xor_1110); +assign pyc_or_1538 = (pyc_or_1536 | pyc_and_1537); +assign pyc_xor_1539 = (pyc_xor_1533 ^ pyc_or_1097); +assign pyc_xor_1540 = (pyc_xor_1539 ^ pyc_or_1524); +assign pyc_and_1541 = (pyc_xor_1533 & pyc_or_1097); +assign pyc_and_1542 = (pyc_xor_1533 & pyc_or_1524); +assign pyc_or_1543 = (pyc_and_1541 | pyc_and_1542); +assign pyc_and_1544 = (pyc_or_1097 & pyc_or_1524); +assign pyc_or_1545 = (pyc_or_1543 | pyc_and_1544); +assign pyc_xor_1546 = (pyc_xor_562 ^ pyc_or_554); +assign pyc_xor_1547 = (pyc_xor_1546 ^ pyc_xor_1123); +assign pyc_xor_1548 = (pyc_xor_1547 ^ pyc_or_1115); +assign pyc_xor_1549 = (pyc_xor_1548 ^ pyc_or_1538); +assign pyc_concat_1550 = {pyc_xor_1549, pyc_xor_1540, pyc_xor_1526, pyc_xor_1512, pyc_xor_1498, pyc_xor_1484, pyc_xor_1470, pyc_xor_1456, pyc_xor_1442, pyc_xor_1428, pyc_xor_1414, pyc_xor_1400, pyc_xor_1386, pyc_xor_1372, pyc_xor_1358, pyc_xor_1344, pyc_xor_1330, pyc_xor_1316, pyc_xor_1302, pyc_xor_1288, pyc_xor_1274, pyc_xor_1260, pyc_xor_1246, pyc_xor_1232, pyc_xor_1218, pyc_xor_1204, pyc_xor_1190, pyc_xor_1176, pyc_xor_1162, pyc_xor_1148, pyc_xor_1134, pyc_xor_1124}; +assign pyc_concat_1551 = {pyc_or_1545, pyc_or_1531, pyc_or_1517, pyc_or_1503, pyc_or_1489, pyc_or_1475, pyc_or_1461, pyc_or_1447, pyc_or_1433, pyc_or_1419, pyc_or_1405, pyc_or_1391, pyc_or_1377, pyc_or_1363, pyc_or_1349, pyc_or_1335, pyc_or_1321, pyc_or_1307, pyc_or_1293, pyc_or_1279, pyc_or_1265, pyc_or_1251, pyc_or_1237, pyc_or_1223, pyc_or_1209, pyc_or_1195, pyc_or_1181, pyc_or_1167, pyc_or_1153, pyc_or_1139, pyc_constant_1, pyc_constant_1}; +assign pyc_add_1552 = (pyc_concat_1550 + pyc_concat_1551); +assign pyc_comb_1553 = pyc_add_1552; + +assign PE_INT_WALLACE_DOT8_TREE_sum = pyc_comb_1553; + +endmodule + diff --git a/designs/PE_INT/rtl/build/pyc_primitives.v b/designs/PE_INT/rtl/build/pyc_primitives.v index 6aa34a7..8aab4b2 100644 --- a/designs/PE_INT/rtl/build/pyc_primitives.v +++ b/designs/PE_INT/rtl/build/pyc_primitives.v @@ -1,658 +1,658 @@ // pyCircuit Verilog primitives (concatenated) /* verilator lint_off DECLFILENAME */ -// --- pyc_reg.v -// Simple synchronous reset register (prototype). -module pyc_reg #( - parameter WIDTH = 1 -) ( - input clk, - input rst, - input en, - input [WIDTH-1:0] d, - input [WIDTH-1:0] init, - output reg [WIDTH-1:0] q -); - always @(posedge clk) begin - if (rst) - q <= init; - else if (en) - q <= d; - end -endmodule - - -// --- pyc_fifo.v -// Ready/valid FIFO with synchronous reset (prototype). -module pyc_fifo #( - parameter WIDTH = 1, - parameter DEPTH = 2 -) ( - input clk, - input rst, - - // Input (producer -> fifo) - input in_valid, - output in_ready, - input [WIDTH-1:0] in_data, - - // Output (fifo -> consumer) - output out_valid, - input out_ready, - output [WIDTH-1:0] out_data -); - `ifndef SYNTHESIS - initial begin - if (DEPTH <= 0) begin - $display("ERROR: pyc_fifo DEPTH must be > 0"); - $finish; - end - end - `endif - - function integer pyc_clog2; - input integer value; - integer i; - begin - pyc_clog2 = 0; - for (i = value - 1; i > 0; i = i >> 1) - pyc_clog2 = pyc_clog2 + 1; - end - endfunction - - localparam PTR_W = (DEPTH <= 1) ? 1 : pyc_clog2(DEPTH); - - reg [WIDTH-1:0] storage [0:DEPTH-1]; - reg [PTR_W-1:0] rd_ptr; - reg [PTR_W-1:0] wr_ptr; - reg [PTR_W:0] count; - - assign in_ready = (count < DEPTH) || (out_ready && out_valid); - assign out_valid = (count != 0); - // Define out_data when empty to keep C++/Verilog equivalence deterministic. - assign out_data = out_valid ? storage[rd_ptr] : {WIDTH{1'b0}}; - - wire do_pop; - wire do_push; - assign do_pop = out_valid && out_ready; - assign do_push = in_valid && in_ready; - - function [PTR_W-1:0] bump_ptr; - input [PTR_W-1:0] p; - begin - if (DEPTH <= 1) - bump_ptr = {PTR_W{1'b0}}; - else if (p == (DEPTH - 1)) - bump_ptr = {PTR_W{1'b0}}; - else - bump_ptr = p + 1'b1; - end - endfunction - - always @(posedge clk) begin - if (rst) begin - rd_ptr <= {PTR_W{1'b0}}; - wr_ptr <= {PTR_W{1'b0}}; - count <= {(PTR_W + 1){1'b0}}; - end else begin - case ({do_push, do_pop}) - 2'b00: begin - // hold - end - 2'b01: begin - rd_ptr <= bump_ptr(rd_ptr); - count <= count - 1'b1; - end - 2'b10: begin - storage[wr_ptr] <= in_data; - wr_ptr <= bump_ptr(wr_ptr); - count <= count + 1'b1; - end - 2'b11: begin - // push + pop in the same cycle - storage[wr_ptr] <= in_data; - rd_ptr <= bump_ptr(rd_ptr); - wr_ptr <= bump_ptr(wr_ptr); - count <= count; - end - endcase - end - end -endmodule - - -// --- pyc_byte_mem.v -// Byte-addressed memory (prototype). -// -// - `DEPTH` is in bytes. -// - Combinational little-endian read window. -// - Byte-enable write on posedge. -module pyc_byte_mem #( - parameter ADDR_WIDTH = 64, - parameter DATA_WIDTH = 64, - parameter DEPTH = 1024, - // Optional init file (Vivado: can be used for BRAM init; simulation: $readmemh). - // If the file cannot be opened, initialization is skipped. - parameter INIT_MEMH = "" -) ( - input clk, - input rst, - - input [ADDR_WIDTH-1:0] raddr, - output reg [DATA_WIDTH-1:0] rdata, - - input wvalid, - input [ADDR_WIDTH-1:0] waddr, - input [DATA_WIDTH-1:0] wdata, - input [(DATA_WIDTH+7)/8-1:0] wstrb -); - localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; - - // Byte storage. - reg [7:0] mem [0:DEPTH-1]; - - // Optional initialization. - integer init_fd; - integer init_i; - initial begin - `ifndef SYNTHESIS - // Deterministic simulation init: keep C++/Verilog equivalence stable. - for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) - mem[init_i] = 8'h00; - `endif - if (INIT_MEMH != "") begin - init_fd = $fopen(INIT_MEMH, "r"); - if (init_fd != 0) begin - $fclose(init_fd); - $readmemh(INIT_MEMH, mem); - end - end - end - - // Combinational read: assemble DATA_WIDTH bits from successive bytes. - integer i; - integer a; - always @* begin - a = raddr[31:0]; - rdata = {DATA_WIDTH{1'b0}}; - for (i = 0; i < STRB_WIDTH; i = i + 1) begin - if ((a + i) < DEPTH) - rdata[8 * i +: 8] = mem[a + i]; - end - end - - // Byte-enable write. - integer j; - integer wa; - always @(posedge clk) begin - if (rst) begin - // Reset does not clear memory (init happens via INIT_MEMH or sim-default 0s). - end else if (wvalid) begin - wa = waddr[31:0]; - for (j = 0; j < STRB_WIDTH; j = j + 1) begin - if (wstrb[j] && ((wa + j) < DEPTH)) - mem[wa + j] <= wdata[8 * j +: 8]; - end - end - end -endmodule - - -// --- pyc_sync_mem.v -// Synchronous 1R1W memory with registered read data (prototype). -// -// - `DEPTH` is in entries (not bytes). -// - Read is synchronous: when `ren` is asserted, `rdata` updates on the next -// rising edge of `clk`. -// - Write is synchronous with byte enables `wstrb`. -// -// Note: Read-during-write to the same address returns the pre-write data -// ("old-data") by default. -module pyc_sync_mem #( - parameter ADDR_WIDTH = 64, - parameter DATA_WIDTH = 64, - parameter DEPTH = 1024 -) ( - input clk, - input rst, - - input ren, - input [ADDR_WIDTH-1:0] raddr, - output reg [DATA_WIDTH-1:0] rdata, - - input wvalid, - input [ADDR_WIDTH-1:0] waddr, - input [DATA_WIDTH-1:0] wdata, - input [(DATA_WIDTH+7)/8-1:0] wstrb -); - `ifndef SYNTHESIS - initial begin - if (DEPTH <= 0) begin - $display("ERROR: pyc_sync_mem DEPTH must be > 0"); - $finish; - end - end - `endif - - localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; - localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); - // Use a compact address for FPGA-friendly inference. For non-power-of-two - // depths, some addresses in [DEPTH, 2**ADDR_BITS) are unused. - localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); - - // Storage. - `ifdef PYC_TARGET_FPGA - (* ram_style = "block" *) - (* ramstyle = "M20K" *) - reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; - `else - reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; - `endif - - `ifndef SYNTHESIS - // Deterministic simulation init: keep C++/Verilog equivalence stable. - integer init_i; - initial begin - for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) - mem[init_i] = {DATA_WIDTH{1'b0}}; - end - `endif - - integer i; - reg [DATA_WIDTH-1:0] rd_word; - wire [ADDR_BITS-1:0] ra = raddr[ADDR_BITS-1:0]; - wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; - - always @(posedge clk) begin - if (rst) begin - rdata <= {DATA_WIDTH{1'b0}}; - end else begin - // Write with per-lane strobes; last lane may be narrower than 8 bits. - if (wvalid) begin - `ifndef SYNTHESIS - if (wa < DEPTH) begin - for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin - if (wstrb[i]) - mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; - end - if (wstrb[STRB_WIDTH-1]) - mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; - end - `else - for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin - if (wstrb[i]) - mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; - end - if (wstrb[STRB_WIDTH-1]) - mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; - `endif - end - - // Registered read. - if (ren) begin - `ifndef SYNTHESIS - if (ra < DEPTH) begin - rd_word = mem[ra]; - rdata <= rd_word; - end else begin - rdata <= {DATA_WIDTH{1'b0}}; - end - `else - rd_word = mem[ra]; - rdata <= rd_word; - `endif - end - end - end -endmodule - - -// --- pyc_sync_mem_dp.v -// Synchronous 2R1W memory with registered read data (prototype). -// -// - `DEPTH` is in entries (not bytes). -// - Both reads are synchronous (registered outputs). -// - One write port with byte enables `wstrb`. -// - Read-during-write to the same address returns pre-write data ("old-data") by default. -module pyc_sync_mem_dp #( - parameter ADDR_WIDTH = 64, - parameter DATA_WIDTH = 64, - parameter DEPTH = 1024 -) ( - input clk, - input rst, - - input ren0, - input [ADDR_WIDTH-1:0] raddr0, - output reg [DATA_WIDTH-1:0] rdata0, - - input ren1, - input [ADDR_WIDTH-1:0] raddr1, - output reg [DATA_WIDTH-1:0] rdata1, - - input wvalid, - input [ADDR_WIDTH-1:0] waddr, - input [DATA_WIDTH-1:0] wdata, - input [(DATA_WIDTH+7)/8-1:0] wstrb -); - `ifndef SYNTHESIS - initial begin - if (DEPTH <= 0) begin - $display("ERROR: pyc_sync_mem_dp DEPTH must be > 0"); - $finish; - end - end - `endif - - localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; - localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); - localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); - - `ifdef PYC_TARGET_FPGA - (* ram_style = "block" *) - (* ramstyle = "M20K" *) - reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; - `else - reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; - `endif - - `ifndef SYNTHESIS - // Deterministic simulation init: keep C++/Verilog equivalence stable. - integer init_i; - initial begin - for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) - mem[init_i] = {DATA_WIDTH{1'b0}}; - end - `endif - - integer i; - reg [DATA_WIDTH-1:0] rd0; - reg [DATA_WIDTH-1:0] rd1; - wire [ADDR_BITS-1:0] ra0 = raddr0[ADDR_BITS-1:0]; - wire [ADDR_BITS-1:0] ra1 = raddr1[ADDR_BITS-1:0]; - wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; - - always @(posedge clk) begin - if (rst) begin - rdata0 <= {DATA_WIDTH{1'b0}}; - rdata1 <= {DATA_WIDTH{1'b0}}; - end else begin - // Write with per-lane strobes; last lane may be narrower than 8 bits. - if (wvalid) begin - `ifndef SYNTHESIS - if (wa < DEPTH) begin - for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin - if (wstrb[i]) - mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; - end - if (wstrb[STRB_WIDTH-1]) - mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; - end - `else - for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin - if (wstrb[i]) - mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; - end - if (wstrb[STRB_WIDTH-1]) - mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; - `endif - end - - // Registered read port 0. - if (ren0) begin - `ifndef SYNTHESIS - if (ra0 < DEPTH) begin - rd0 = mem[ra0]; - rdata0 <= rd0; - end else begin - rdata0 <= {DATA_WIDTH{1'b0}}; - end - `else - rd0 = mem[ra0]; - rdata0 <= rd0; - `endif - end - - // Registered read port 1. - if (ren1) begin - `ifndef SYNTHESIS - if (ra1 < DEPTH) begin - rd1 = mem[ra1]; - rdata1 <= rd1; - end else begin - rdata1 <= {DATA_WIDTH{1'b0}}; - end - `else - rd1 = mem[ra1]; - rdata1 <= rd1; - `endif - end - end - end -endmodule - - -// --- pyc_async_fifo.v -// Async ready/valid FIFO with gray-code pointers (prototype). -// -// - Strict ready/valid handshake (no combinational cross-domain paths). -// - `DEPTH` must be a power of two and >= 2. -// - Synchronous resets (per domain). -// -// This is a minimal, synthesizable async FIFO suitable for CDC of data streams. -module pyc_async_fifo #( - parameter WIDTH = 1, - parameter DEPTH = 2 -) ( - // Write domain (producer -> fifo) - input in_clk, - input in_rst, - input in_valid, - output in_ready, - input [WIDTH-1:0] in_data, - - // Read domain (fifo -> consumer) - input out_clk, - input out_rst, - output out_valid, - input out_ready, - output [WIDTH-1:0] out_data -); - `ifndef SYNTHESIS - initial begin - if (DEPTH < 2) begin - $display("ERROR: pyc_async_fifo DEPTH must be >= 2"); - $finish; - end - if ((DEPTH & (DEPTH - 1)) != 0) begin - $display("ERROR: pyc_async_fifo DEPTH must be a power of two"); - $finish; - end - end - `endif - - function integer pyc_clog2; - input integer value; - integer i; - begin - pyc_clog2 = 0; - for (i = value - 1; i > 0; i = i >> 1) - pyc_clog2 = pyc_clog2 + 1; - end - endfunction - - localparam AW = pyc_clog2(DEPTH); - - // Storage. - reg [WIDTH-1:0] mem [0:DEPTH-1]; - - // --- pointer helpers --- - function [AW:0] bin2gray; - input [AW:0] b; - begin - bin2gray = (b >> 1) ^ b; - end - endfunction - - // --- write domain --- - reg [AW:0] wptr_bin; - reg [AW:0] wptr_gray; - wire [AW:0] wptr_bin_next; - wire [AW:0] wptr_gray_next; - reg wfull; - - // Read pointer gray (owned by read domain), referenced for synchronization. - reg [AW:0] rptr_gray; - - reg [AW:0] rptr_gray_w1; - reg [AW:0] rptr_gray_w2; - - wire wfull_next; - wire do_push; - - assign in_ready = ~wfull; - assign do_push = in_valid && in_ready; - assign wptr_bin_next = wptr_bin + (do_push ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); - assign wptr_gray_next = bin2gray(wptr_bin_next); - // Full detection compares next wptr gray against synchronized rptr gray with - // the top 2 bits inverted (classic async FIFO technique). For DEPTH=2, AW=1 - // and there are no "lower" bits to append. - generate - if (AW == 1) begin : gen_wfull_aw1 - assign wfull_next = (wptr_gray_next == ~rptr_gray_w2); - end else begin : gen_wfull_awn - assign wfull_next = (wptr_gray_next == {~rptr_gray_w2[AW:AW-1], rptr_gray_w2[AW-2:0]}); - end - endgenerate - - integer wi; - always @(posedge in_clk) begin - if (in_rst) begin - wptr_bin <= {AW+1{1'b0}}; - wptr_gray <= {AW+1{1'b0}}; - wfull <= 1'b0; - rptr_gray_w1 <= {AW+1{1'b0}}; - rptr_gray_w2 <= {AW+1{1'b0}}; - end else begin - // Sync read pointer into write clock domain. - rptr_gray_w1 <= rptr_gray; - rptr_gray_w2 <= rptr_gray_w1; - - if (do_push) begin - mem[wptr_bin[AW-1:0]] <= in_data; - end - wptr_bin <= wptr_bin_next; - wptr_gray <= wptr_gray_next; - wfull <= wfull_next; - end - end - - reg [AW:0] rptr_bin; - // rptr_gray is declared above (referenced by the write domain sync flops). - wire [AW:0] rptr_bin_next; - wire [AW:0] rptr_gray_next; - - reg [AW:0] wptr_gray_r1; - reg [AW:0] wptr_gray_r2; - - reg out_valid_r; - reg [WIDTH-1:0] out_data_r; - - wire empty_now; - wire empty_next; - wire do_pop; - - assign empty_now = (rptr_gray == wptr_gray_r2); - assign out_valid = out_valid_r; - assign out_data = out_data_r; - - assign do_pop = out_valid_r && out_ready; - assign rptr_bin_next = rptr_bin + (do_pop ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); - assign rptr_gray_next = bin2gray(rptr_bin_next); - assign empty_next = (rptr_gray_next == wptr_gray_r2); - - integer ri; - always @(posedge out_clk) begin - if (out_rst) begin - rptr_bin <= {AW+1{1'b0}}; - rptr_gray <= {AW+1{1'b0}}; - wptr_gray_r1 <= {AW+1{1'b0}}; - wptr_gray_r2 <= {AW+1{1'b0}}; - out_valid_r <= 1'b0; - out_data_r <= {WIDTH{1'b0}}; - end else begin - // Sync write pointer into read clock domain. - wptr_gray_r1 <= wptr_gray; - wptr_gray_r2 <= wptr_gray_r1; - - if (!out_valid_r) begin - // Fill output register when data becomes available. - if (!empty_now) begin - out_valid_r <= 1'b1; - out_data_r <= mem[rptr_bin[AW-1:0]]; - end - end else if (do_pop) begin - // Pop current word; either refill with next word or go empty. - rptr_bin <= rptr_bin_next; - rptr_gray <= rptr_gray_next; - if (empty_next) begin - out_valid_r <= 1'b0; - out_data_r <= {WIDTH{1'b0}}; - end else begin - out_valid_r <= 1'b1; - out_data_r <= mem[rptr_bin_next[AW-1:0]]; - end - end - end - end -endmodule - - -// --- pyc_cdc_sync.v -// CDC synchronizer (prototype). -// -// This is a simple multi-stage flop pipeline in the destination clock domain. -// It is suitable for single-bit control signals. For multi-bit buses, prefer a -// proper CDC protocol (async FIFO, handshake, etc). -module pyc_cdc_sync #( - parameter WIDTH = 1, - parameter STAGES = 2 -) ( - input clk, - input rst, - input [WIDTH-1:0] in, - output [WIDTH-1:0] out -); - `ifndef SYNTHESIS - initial begin - if (STAGES < 1) begin - $display("ERROR: pyc_cdc_sync STAGES must be >= 1"); - $finish; - end - end - `endif - - `ifdef PYC_TARGET_FPGA - (* async_reg = "true" *) - reg [WIDTH-1:0] pipe [0:STAGES-1]; - `else - reg [WIDTH-1:0] pipe [0:STAGES-1]; - `endif - - integer i; - always @(posedge clk) begin - if (rst) begin - for (i = 0; i < STAGES; i = i + 1) - pipe[i] <= {WIDTH{1'b0}}; - end else begin - pipe[0] <= in; - for (i = 1; i < STAGES; i = i + 1) - pipe[i] <= pipe[i - 1]; - end - end - - assign out = pipe[STAGES-1]; -endmodule +// --- PYC_REG.v +// Register with asynchronous reset assertion for PE_INT deliverable RTL. +module PYC_REG #( + parameter WIDTH = 1 +) ( + input clk, + input rst, + input en, + input [WIDTH-1:0] d, + input [WIDTH-1:0] init, + output reg [WIDTH-1:0] q +); + always @(posedge clk or posedge rst) begin + if (rst) + q <= init; + else if (en) + q <= d; + end +endmodule + + +// --- PYC_FIFO.v +// Ready/valid FIFO with synchronous reset (prototype). +module PYC_FIFO #( + parameter WIDTH = 1, + parameter DEPTH = 2 +) ( + input clk, + input rst, + + // Input (producer -> fifo) + input in_valid, + output in_ready, + input [WIDTH-1:0] in_data, + + // Output (fifo -> consumer) + output out_valid, + input out_ready, + output [WIDTH-1:0] out_data +); + `ifndef SYNTHESIS + initial begin + if (DEPTH <= 0) begin + $display("ERROR: PYC_FIFO DEPTH must be > 0"); + $finish; + end + end + `endif + + function integer pyc_clog2; + input integer value; + integer i; + begin + pyc_clog2 = 0; + for (i = value - 1; i > 0; i = i >> 1) + pyc_clog2 = pyc_clog2 + 1; + end + endfunction + + localparam PTR_W = (DEPTH <= 1) ? 1 : pyc_clog2(DEPTH); + + reg [WIDTH-1:0] storage [0:DEPTH-1]; + reg [PTR_W-1:0] rd_ptr; + reg [PTR_W-1:0] wr_ptr; + reg [PTR_W:0] count; + + assign in_ready = (count < DEPTH) || (out_ready && out_valid); + assign out_valid = (count != 0); + // Define out_data when empty to keep C++/Verilog equivalence deterministic. + assign out_data = out_valid ? storage[rd_ptr] : {WIDTH{1'b0}}; + + wire do_pop; + wire do_push; + assign do_pop = out_valid && out_ready; + assign do_push = in_valid && in_ready; + + function [PTR_W-1:0] bump_ptr; + input [PTR_W-1:0] p; + begin + if (DEPTH <= 1) + bump_ptr = {PTR_W{1'b0}}; + else if (p == (DEPTH - 1)) + bump_ptr = {PTR_W{1'b0}}; + else + bump_ptr = p + 1'b1; + end + endfunction + + always @(posedge clk) begin + if (rst) begin + rd_ptr <= {PTR_W{1'b0}}; + wr_ptr <= {PTR_W{1'b0}}; + count <= {(PTR_W + 1){1'b0}}; + end else begin + case ({do_push, do_pop}) + 2'b00: begin + // hold + end + 2'b01: begin + rd_ptr <= bump_ptr(rd_ptr); + count <= count - 1'b1; + end + 2'b10: begin + storage[wr_ptr] <= in_data; + wr_ptr <= bump_ptr(wr_ptr); + count <= count + 1'b1; + end + 2'b11: begin + // push + pop in the same cycle + storage[wr_ptr] <= in_data; + rd_ptr <= bump_ptr(rd_ptr); + wr_ptr <= bump_ptr(wr_ptr); + count <= count; + end + endcase + end + end +endmodule + + +// --- PYC_BYTE_MEM.v +// Byte-addressed memory (prototype). +// +// - `DEPTH` is in bytes. +// - Combinational little-endian read window. +// - Byte-enable write on posedge. +module PYC_BYTE_MEM #( + parameter ADDR_WIDTH = 64, + parameter DATA_WIDTH = 64, + parameter DEPTH = 1024, + // Optional init file (Vivado: can be used for BRAM init; simulation: $readmemh). + // If the file cannot be opened, initialization is skipped. + parameter INIT_MEMH = "" +) ( + input clk, + input rst, + + input [ADDR_WIDTH-1:0] raddr, + output reg [DATA_WIDTH-1:0] rdata, + + input wvalid, + input [ADDR_WIDTH-1:0] waddr, + input [DATA_WIDTH-1:0] wdata, + input [(DATA_WIDTH+7)/8-1:0] wstrb +); + localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; + + // Byte storage. + reg [7:0] mem [0:DEPTH-1]; + + // Optional initialization. + integer init_fd; + integer init_i; + initial begin + `ifndef SYNTHESIS + // Deterministic simulation init: keep C++/Verilog equivalence stable. + for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) + mem[init_i] = 8'h00; + `endif + if (INIT_MEMH != "") begin + init_fd = $fopen(INIT_MEMH, "r"); + if (init_fd != 0) begin + $fclose(init_fd); + $readmemh(INIT_MEMH, mem); + end + end + end + + // Combinational read: assemble DATA_WIDTH bits from successive bytes. + integer i; + integer a; + always @* begin + a = raddr[31:0]; + rdata = {DATA_WIDTH{1'b0}}; + for (i = 0; i < STRB_WIDTH; i = i + 1) begin + if ((a + i) < DEPTH) + rdata[8 * i +: 8] = mem[a + i]; + end + end + + // Byte-enable write. + integer j; + integer wa; + always @(posedge clk) begin + if (rst) begin + // Reset does not clear memory (init happens via INIT_MEMH or sim-default 0s). + end else if (wvalid) begin + wa = waddr[31:0]; + for (j = 0; j < STRB_WIDTH; j = j + 1) begin + if (wstrb[j] && ((wa + j) < DEPTH)) + mem[wa + j] <= wdata[8 * j +: 8]; + end + end + end +endmodule + + +// --- PYC_SYNC_MEM.v +// Synchronous 1R1W memory with registered read data (prototype). +// +// - `DEPTH` is in entries (not bytes). +// - Read is synchronous: when `ren` is asserted, `rdata` updates on the next +// rising edge of `clk`. +// - Write is synchronous with byte enables `wstrb`. +// +// Note: Read-during-write to the same address returns the pre-write data +// ("old-data") by default. +module PYC_SYNC_MEM #( + parameter ADDR_WIDTH = 64, + parameter DATA_WIDTH = 64, + parameter DEPTH = 1024 +) ( + input clk, + input rst, + + input ren, + input [ADDR_WIDTH-1:0] raddr, + output reg [DATA_WIDTH-1:0] rdata, + + input wvalid, + input [ADDR_WIDTH-1:0] waddr, + input [DATA_WIDTH-1:0] wdata, + input [(DATA_WIDTH+7)/8-1:0] wstrb +); + `ifndef SYNTHESIS + initial begin + if (DEPTH <= 0) begin + $display("ERROR: PYC_SYNC_MEM DEPTH must be > 0"); + $finish; + end + end + `endif + + localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; + localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); + // Use a compact address for FPGA-friendly inference. For non-power-of-two + // depths, some addresses in [DEPTH, 2**ADDR_BITS) are unused. + localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); + + // Storage. + `ifdef PYC_TARGET_FPGA + (* ram_style = "block" *) + (* ramstyle = "M20K" *) + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `else + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `endif + + `ifndef SYNTHESIS + // Deterministic simulation init: keep C++/Verilog equivalence stable. + integer init_i; + initial begin + for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) + mem[init_i] = {DATA_WIDTH{1'b0}}; + end + `endif + + integer i; + reg [DATA_WIDTH-1:0] rd_word; + wire [ADDR_BITS-1:0] ra = raddr[ADDR_BITS-1:0]; + wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; + + always @(posedge clk) begin + if (rst) begin + rdata <= {DATA_WIDTH{1'b0}}; + end else begin + // Write with per-lane strobes; last lane may be narrower than 8 bits. + if (wvalid) begin + `ifndef SYNTHESIS + if (wa < DEPTH) begin + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + end + `else + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + `endif + end + + // Registered read. + if (ren) begin + `ifndef SYNTHESIS + if (ra < DEPTH) begin + rd_word = mem[ra]; + rdata <= rd_word; + end else begin + rdata <= {DATA_WIDTH{1'b0}}; + end + `else + rd_word = mem[ra]; + rdata <= rd_word; + `endif + end + end + end +endmodule + + +// --- PYC_SYNC_MEM_DP.v +// Synchronous 2R1W memory with registered read data (prototype). +// +// - `DEPTH` is in entries (not bytes). +// - Both reads are synchronous (registered outputs). +// - One write port with byte enables `wstrb`. +// - Read-during-write to the same address returns pre-write data ("old-data") by default. +module PYC_SYNC_MEM_DP #( + parameter ADDR_WIDTH = 64, + parameter DATA_WIDTH = 64, + parameter DEPTH = 1024 +) ( + input clk, + input rst, + + input ren0, + input [ADDR_WIDTH-1:0] raddr0, + output reg [DATA_WIDTH-1:0] rdata0, + + input ren1, + input [ADDR_WIDTH-1:0] raddr1, + output reg [DATA_WIDTH-1:0] rdata1, + + input wvalid, + input [ADDR_WIDTH-1:0] waddr, + input [DATA_WIDTH-1:0] wdata, + input [(DATA_WIDTH+7)/8-1:0] wstrb +); + `ifndef SYNTHESIS + initial begin + if (DEPTH <= 0) begin + $display("ERROR: PYC_SYNC_MEM_DP DEPTH must be > 0"); + $finish; + end + end + `endif + + localparam STRB_WIDTH = (DATA_WIDTH + 7) / 8; + localparam LAST_LANE_BITS = DATA_WIDTH - 8 * (STRB_WIDTH - 1); + localparam ADDR_BITS = (DEPTH <= 1) ? 1 : $clog2(DEPTH); + + `ifdef PYC_TARGET_FPGA + (* ram_style = "block" *) + (* ramstyle = "M20K" *) + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `else + reg [DATA_WIDTH-1:0] mem [0:DEPTH-1]; + `endif + + `ifndef SYNTHESIS + // Deterministic simulation init: keep C++/Verilog equivalence stable. + integer init_i; + initial begin + for (init_i = 0; init_i < DEPTH; init_i = init_i + 1) + mem[init_i] = {DATA_WIDTH{1'b0}}; + end + `endif + + integer i; + reg [DATA_WIDTH-1:0] rd0; + reg [DATA_WIDTH-1:0] rd1; + wire [ADDR_BITS-1:0] ra0 = raddr0[ADDR_BITS-1:0]; + wire [ADDR_BITS-1:0] ra1 = raddr1[ADDR_BITS-1:0]; + wire [ADDR_BITS-1:0] wa = waddr[ADDR_BITS-1:0]; + + always @(posedge clk) begin + if (rst) begin + rdata0 <= {DATA_WIDTH{1'b0}}; + rdata1 <= {DATA_WIDTH{1'b0}}; + end else begin + // Write with per-lane strobes; last lane may be narrower than 8 bits. + if (wvalid) begin + `ifndef SYNTHESIS + if (wa < DEPTH) begin + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + end + `else + for (i = 0; i < STRB_WIDTH - 1; i = i + 1) begin + if (wstrb[i]) + mem[wa][8 * i +: 8] <= wdata[8 * i +: 8]; + end + if (wstrb[STRB_WIDTH-1]) + mem[wa][8*(STRB_WIDTH-1) +: LAST_LANE_BITS] <= wdata[8*(STRB_WIDTH-1) +: LAST_LANE_BITS]; + `endif + end + + // Registered read port 0. + if (ren0) begin + `ifndef SYNTHESIS + if (ra0 < DEPTH) begin + rd0 = mem[ra0]; + rdata0 <= rd0; + end else begin + rdata0 <= {DATA_WIDTH{1'b0}}; + end + `else + rd0 = mem[ra0]; + rdata0 <= rd0; + `endif + end + + // Registered read port 1. + if (ren1) begin + `ifndef SYNTHESIS + if (ra1 < DEPTH) begin + rd1 = mem[ra1]; + rdata1 <= rd1; + end else begin + rdata1 <= {DATA_WIDTH{1'b0}}; + end + `else + rd1 = mem[ra1]; + rdata1 <= rd1; + `endif + end + end + end +endmodule + + +// --- PYC_ASYNC_FIFO.v +// Async ready/valid FIFO with gray-code pointers (prototype). +// +// - Strict ready/valid handshake (no combinational cross-domain paths). +// - `DEPTH` must be a power of two and >= 2. +// - Synchronous resets (per domain). +// +// This is a minimal, synthesizable async FIFO suitable for CDC of data streams. +module PYC_ASYNC_FIFO #( + parameter WIDTH = 1, + parameter DEPTH = 2 +) ( + // Write domain (producer -> fifo) + input in_clk, + input in_rst, + input in_valid, + output in_ready, + input [WIDTH-1:0] in_data, + + // Read domain (fifo -> consumer) + input out_clk, + input out_rst, + output out_valid, + input out_ready, + output [WIDTH-1:0] out_data +); + `ifndef SYNTHESIS + initial begin + if (DEPTH < 2) begin + $display("ERROR: PYC_ASYNC_FIFO DEPTH must be >= 2"); + $finish; + end + if ((DEPTH & (DEPTH - 1)) != 0) begin + $display("ERROR: PYC_ASYNC_FIFO DEPTH must be a power of two"); + $finish; + end + end + `endif + + function integer pyc_clog2; + input integer value; + integer i; + begin + pyc_clog2 = 0; + for (i = value - 1; i > 0; i = i >> 1) + pyc_clog2 = pyc_clog2 + 1; + end + endfunction + + localparam AW = pyc_clog2(DEPTH); + + // Storage. + reg [WIDTH-1:0] mem [0:DEPTH-1]; + + // --- pointer helpers --- + function [AW:0] bin2gray; + input [AW:0] b; + begin + bin2gray = (b >> 1) ^ b; + end + endfunction + + // --- write domain --- + reg [AW:0] wptr_bin; + reg [AW:0] wptr_gray; + wire [AW:0] wptr_bin_next; + wire [AW:0] wptr_gray_next; + reg wfull; + + // Read pointer gray (owned by read domain), referenced for synchronization. + reg [AW:0] rptr_gray; + + reg [AW:0] rptr_gray_w1; + reg [AW:0] rptr_gray_w2; + + wire wfull_next; + wire do_push; + + assign in_ready = ~wfull; + assign do_push = in_valid && in_ready; + assign wptr_bin_next = wptr_bin + (do_push ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); + assign wptr_gray_next = bin2gray(wptr_bin_next); + // Full detection compares next wptr gray against synchronized rptr gray with + // the top 2 bits inverted (classic async FIFO technique). For DEPTH=2, AW=1 + // and there are no "lower" bits to append. + generate + if (AW == 1) begin : gen_wfull_aw1 + assign wfull_next = (wptr_gray_next == ~rptr_gray_w2); + end else begin : gen_wfull_awn + assign wfull_next = (wptr_gray_next == {~rptr_gray_w2[AW:AW-1], rptr_gray_w2[AW-2:0]}); + end + endgenerate + + integer wi; + always @(posedge in_clk) begin + if (in_rst) begin + wptr_bin <= {AW+1{1'b0}}; + wptr_gray <= {AW+1{1'b0}}; + wfull <= 1'b0; + rptr_gray_w1 <= {AW+1{1'b0}}; + rptr_gray_w2 <= {AW+1{1'b0}}; + end else begin + // Sync read pointer into write clock domain. + rptr_gray_w1 <= rptr_gray; + rptr_gray_w2 <= rptr_gray_w1; + + if (do_push) begin + mem[wptr_bin[AW-1:0]] <= in_data; + end + wptr_bin <= wptr_bin_next; + wptr_gray <= wptr_gray_next; + wfull <= wfull_next; + end + end + + reg [AW:0] rptr_bin; + // rptr_gray is declared above (referenced by the write domain sync flops). + wire [AW:0] rptr_bin_next; + wire [AW:0] rptr_gray_next; + + reg [AW:0] wptr_gray_r1; + reg [AW:0] wptr_gray_r2; + + reg out_valid_r; + reg [WIDTH-1:0] out_data_r; + + wire empty_now; + wire empty_next; + wire do_pop; + + assign empty_now = (rptr_gray == wptr_gray_r2); + assign out_valid = out_valid_r; + assign out_data = out_data_r; + + assign do_pop = out_valid_r && out_ready; + assign rptr_bin_next = rptr_bin + (do_pop ? {{AW{1'b0}}, 1'b1} : {AW+1{1'b0}}); + assign rptr_gray_next = bin2gray(rptr_bin_next); + assign empty_next = (rptr_gray_next == wptr_gray_r2); + + integer ri; + always @(posedge out_clk) begin + if (out_rst) begin + rptr_bin <= {AW+1{1'b0}}; + rptr_gray <= {AW+1{1'b0}}; + wptr_gray_r1 <= {AW+1{1'b0}}; + wptr_gray_r2 <= {AW+1{1'b0}}; + out_valid_r <= 1'b0; + out_data_r <= {WIDTH{1'b0}}; + end else begin + // Sync write pointer into read clock domain. + wptr_gray_r1 <= wptr_gray; + wptr_gray_r2 <= wptr_gray_r1; + + if (!out_valid_r) begin + // Fill output register when data becomes available. + if (!empty_now) begin + out_valid_r <= 1'b1; + out_data_r <= mem[rptr_bin[AW-1:0]]; + end + end else if (do_pop) begin + // Pop current word; either refill with next word or go empty. + rptr_bin <= rptr_bin_next; + rptr_gray <= rptr_gray_next; + if (empty_next) begin + out_valid_r <= 1'b0; + out_data_r <= {WIDTH{1'b0}}; + end else begin + out_valid_r <= 1'b1; + out_data_r <= mem[rptr_bin_next[AW-1:0]]; + end + end + end + end +endmodule + + +// --- PYC_CDC_SYNC.v +// CDC synchronizer (prototype). +// +// This is a simple multi-stage flop pipeline in the destination clock domain. +// It is suitable for single-bit control signals. For multi-bit buses, prefer a +// proper CDC protocol (async FIFO, handshake, etc). +module PYC_CDC_SYNC #( + parameter WIDTH = 1, + parameter STAGES = 2 +) ( + input clk, + input rst, + input [WIDTH-1:0] in, + output [WIDTH-1:0] out +); + `ifndef SYNTHESIS + initial begin + if (STAGES < 1) begin + $display("ERROR: PYC_CDC_SYNC STAGES must be >= 1"); + $finish; + end + end + `endif + + `ifdef PYC_TARGET_FPGA + (* async_reg = "true" *) + reg [WIDTH-1:0] pipe [0:STAGES-1]; + `else + reg [WIDTH-1:0] pipe [0:STAGES-1]; + `endif + + integer i; + always @(posedge clk) begin + if (rst) begin + for (i = 0; i < STAGES; i = i + 1) + pipe[i] <= {WIDTH{1'b0}}; + end else begin + pipe[0] <= in; + for (i = 1; i < STAGES; i = i + 1) + pipe[i] <= pipe[i - 1]; + end + end + + assign out = pipe[STAGES-1]; +endmodule /* verilator lint_on DECLFILENAME */ diff --git a/designs/PE_INT/tb/tb_pe_int_pycircuit.py b/designs/PE_INT/tb/tb_pe_int_pycircuit.py index 588d12b..5397132 100644 --- a/designs/PE_INT/tb/tb_pe_int_pycircuit.py +++ b/designs/PE_INT/tb/tb_pe_int_pycircuit.py @@ -1,7 +1,5 @@ from __future__ import annotations -import random -import os import sys from pathlib import Path @@ -23,202 +21,80 @@ sys.path.insert(0, str(_MODEL_DIR)) from pe_int_pycircuit import build # noqa: E402 -from pe_int_pycircuit_eval import PEIntL3Model # noqa: E402 -from ref_model import ( # noqa: E402 - MODE_2A, - MODE_2B, - MODE_2C, - MODE_2D, - pack_s4x8_to_40, - pack_s5x8_to_40, - pack_s5x16_to_80, - pack_s8x8_to_laneword, -) +from ref_model import MODE_2A, MODE_2B, compute_transaction, pack_s4x8_to_40, pack_s8x8_to_laneword # noqa: E402 -DEFAULT_PARAMS = {"latency": 4} -VEC_PER_CASE = int(os.environ.get("PE_INT_PYC_TB_VEC_PER_CASE", "8")) -BASE_SEED = 20260420 +DEFAULT_PARAMS = {"latency": 3} def _to_u(value: int, bits: int) -> int: return value & ((1 << bits) - 1) -def _rand_s_rng(rng: random.Random, width: int) -> int: - lo = -(1 << (width - 1)) - hi = (1 << (width - 1)) - 1 - return rng.randint(lo, hi) - - -def _make_txn_rng(mode: int, rng: random.Random): - if mode == MODE_2A: - a = [_rand_s_rng(rng, 8) for _ in range(8)] - b = [_rand_s_rng(rng, 8) for _ in range(8)] - return ( - pack_s8x8_to_laneword(a), - pack_s8x8_to_laneword(b), - 0, - (0, 0), - (0, 0), - (0, 0), - ) - if mode == MODE_2B: - a = [_rand_s_rng(rng, 8) for _ in range(8)] - b0 = [_rand_s_rng(rng, 4) for _ in range(8)] - b1 = [_rand_s_rng(rng, 4) for _ in range(8)] - b = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) - return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) - if mode == MODE_2D: - a = [_rand_s_rng(rng, 8) for _ in range(8)] - b0 = [_rand_s_rng(rng, 5) for _ in range(8)] - b1 = [_rand_s_rng(rng, 5) for _ in range(8)] - b = pack_s5x8_to_40(b0) | (pack_s5x8_to_40(b1) << 40) - return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) - a = [_rand_s_rng(rng, 5) for _ in range(16)] - b0 = [_rand_s_rng(rng, 5) for _ in range(16)] - b1 = [_rand_s_rng(rng, 5) for _ in range(16)] - e1a = (rng.randint(0, 1), rng.randint(0, 1)) - e1b0 = (rng.randint(0, 1), rng.randint(0, 1)) - e1b1 = (rng.randint(0, 1), rng.randint(0, 1)) - return ( - pack_s5x16_to_80(a), - pack_s5x16_to_80(b0), - pack_s5x16_to_80(b1), - e1a, - e1b0, - e1b1, - ) - - -def _tx(vld: int, mode: int, a: int, b: int, b1: int, e1a, e1b0, e1b1): - return { - "vld": int(vld), - "mode": int(mode) & 0x3, - "a": int(a), - "b": int(b), - "b1": int(b1), - "e1_a": tuple(e1a), - "e1_b0": tuple(e1b0), - "e1_b1": tuple(e1b1), - } - - -def _build_sequences(): - seqs = [] - rng = random.Random(BASE_SEED) - - tx_2a = [] - for _ in range(VEC_PER_CASE): - a_pre, b_pre, _, e1a, e1b0, e1b1 = _make_txn_rng(MODE_2B, rng) - tx_2a.append(_tx(1, MODE_2B, a_pre, b_pre, 0, e1a, e1b0, e1b1)) - a2, b2, b12, e1a2, e1b02, e1b12 = _make_txn_rng(MODE_2A, rng) - tx_2a.append(_tx(1, MODE_2A, a2, b2, b12, e1a2, e1b02, e1b12)) - seqs.append(("mode2a_sanity", tx_2a)) - - for name, mode in [("mode2b_sanity", MODE_2B), ("mode2c_sanity", MODE_2C), ("mode2d_sanity", MODE_2D)]: - txs = [] - for _ in range(VEC_PER_CASE): - a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(mode, rng) - txs.append(_tx(1, mode, a, b, b1, e1a, e1b0, e1b1)) - seqs.append((name, txs)) - - tx_switch = [] - for _ in range(VEC_PER_CASE): - vld = rng.randint(0, 1) - mode = rng.choice([MODE_2A, MODE_2B, MODE_2C, MODE_2D]) - a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(mode, rng) - tx_switch.append(_tx(vld, mode, a, b, b1, e1a, e1b0, e1b1)) - seqs.append(("mode_switch_random", tx_switch)) - - for name, mode in [ - ("mode2a_sanity_rand_timing", MODE_2A), - ("mode2b_sanity_rand_timing", MODE_2B), - ("mode2c_sanity_rand_timing", MODE_2C), - ("mode2d_sanity_rand_timing", MODE_2D), - ]: - rr = random.Random(BASE_SEED + mode * 101) - txs = [] - for _ in range(VEC_PER_CASE): - vld = rr.randint(0, 1) - a, b, b1, e1a, e1b0, e1b1 = _make_txn_rng(mode, rr) - txs.append(_tx(vld, mode, a, b, b1, e1a, e1b0, e1b1)) - seqs.append((name, txs)) - - return seqs - - -def _idle_tx(rst_n: int): - return _tx(0, MODE_2A, 0, 0, 0, (0, 0), (0, 0), (0, 0)) | {"rst_n": rst_n} - - -def _run_one_sequence(tb: CycleAwareTb, name: str, txs) -> None: - model = PEIntL3Model() - timeline = [] - - for _ in range(3): - timeline.append(_idle_tx(0)) - for _ in range(3): - timeline.append(_idle_tx(1)) - for item in txs: - timeline.append(item | {"rst_n": 1}) - for _ in range(30): - timeline.append(_idle_tx(1)) - - exp = [] - for item in timeline: - step = model.step( - rst_n=item["rst_n"], - vld=item["vld"], - mode=item["mode"], - a=item["a"], - b=item["b"], - b1=item["b1"], - e1_a=item["e1_a"], - e1_b0=item["e1_b0"], - e1_b1=item["e1_b1"], - ) - exp.append(step) - - first = timeline[0] - tb.drive("rst_n", first["rst_n"]) - tb.drive("vld", first["vld"]) - tb.drive("mode", first["mode"]) - tb.drive("a", _to_u(first["a"], 80)) - tb.drive("b", _to_u(first["b"], 80)) - tb.drive("b1", _to_u(first["b1"], 80)) - tb.drive("e1_a", _to_u(first["e1_a"][0] | (first["e1_a"][1] << 1), 2)) - tb.drive("e1_b0", _to_u(first["e1_b0"][0] | (first["e1_b0"][1] << 1), 2)) - tb.drive("e1_b1", _to_u(first["e1_b1"][0] | (first["e1_b1"][1] << 1), 2)) - - for idx in range(len(timeline)): - tb.next() - tb.expect("vld_out", exp[idx].vld_out) - if exp[idx].vld_out: - tb.expect("out0", _to_u(exp[idx].out0, 19)) - tb.expect("out1", _to_u(exp[idx].out1, 16)) - - if idx + 1 < len(timeline): - nxt = timeline[idx + 1] - tb.drive("rst_n", nxt["rst_n"]) - tb.drive("vld", nxt["vld"]) - tb.drive("mode", nxt["mode"]) - tb.drive("a", _to_u(nxt["a"], 80)) - tb.drive("b", _to_u(nxt["b"], 80)) - tb.drive("b1", _to_u(nxt["b1"], 80)) - tb.drive("e1_a", _to_u(nxt["e1_a"][0] | (nxt["e1_a"][1] << 1), 2)) - tb.drive("e1_b0", _to_u(nxt["e1_b0"][0] | (nxt["e1_b0"][1] << 1), 2)) - tb.drive("e1_b1", _to_u(nxt["e1_b1"][0] | (nxt["e1_b1"][1] << 1), 2)) +def _mode2b_vector(): + a = [1, -2, 3, -4, 5, -6, 7, -8] + b0 = [1, 2, -3, 4, -5, 6, -7, -8] + b1 = [-1, 2, 3, -4, 5, -6, 7, 0] + a80 = pack_s8x8_to_laneword(a) + b80 = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) + exp = compute_transaction(MODE_2B, a80, b80, 0, (0, 0), (0, 0), (0, 0)) + return a80, b80, exp @testbench def tb(t: Tb) -> None: tb = CycleAwareTb(t) tb.clock("clk") - tb.timeout(25000) + tb.reset("rst_n", cycles_asserted=2, cycles_deasserted=1) + tb.timeout(200) + + a80, b80, exp2b = _mode2b_vector() + exp2a = compute_transaction( + MODE_2A, + pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), + pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), + 0, + (0, 0), + (0, 0), + (0, 0), + ) - for name, seq in _build_sequences(): - print(f"[pyc-tb] run {name}, tx_count={len(seq)}") - _run_one_sequence(tb, name, seq) + tb.drive("vld", 0) + tb.drive("mode", MODE_2A) + tb.drive("a", 0) + tb.drive("b", 0) + tb.drive("b1", 0) + tb.drive("e1_a", 0) + tb.drive("e1_b0", 0) + tb.drive("e1_b1", 0) + tb.expect("vld_out", 0) + + # cycle 0: inject 2b + tb.next() + tb.drive("vld", 1) + tb.drive("mode", MODE_2B) + tb.drive("a", _to_u(a80, 80)) + tb.drive("b", _to_u(b80, 80)) + tb.drive("b1", 0) + + # cycle 1: inject 2a + tb.next() + tb.drive("vld", 1) + tb.drive("mode", MODE_2A) + tb.drive("a", _to_u(pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), 80)) + tb.drive("b", _to_u(pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), 80)) + tb.drive("b1", 0) + + # drain and check outputs on target cycles. + for _ in range(20): + tb.next() + tb.drive("vld", 0) + if tb.cycle == 5: + tb.expect("vld_out", 1) + tb.expect("out0", _to_u(exp2b.out0_19, 19)) + tb.expect("out1", _to_u(exp2b.out1_16, 16)) + if tb.cycle == 6: + tb.expect("vld_out", 1) + tb.expect("out0", _to_u(exp2a.out0_19, 19)) tb.finish() From 0ffed31131632d75dd9b89325c163386f0d7357d Mon Sep 17 00:00:00 2001 From: HenryLee Date: Tue, 5 May 2026 21:23:44 +0800 Subject: [PATCH 05/10] fix(designs): restore PE_INT consistent generated flow Restore the PE_INT PyCircuit, generated RTL, and verification files to a coherent L=4 flow after local edits drifted out of sync. --- compiler/frontend/pycircuit/cli.py | 6 +- designs/PE_INT/.gitignore | 3 - designs/PE_INT/README.md | 77 ++--- designs/PE_INT/memory.md | 2 +- designs/PE_INT/model/README.md | 24 +- designs/PE_INT/model/pe_int_pycircuit_eval.py | 206 ++++++------ designs/PE_INT/model/ref_model.py | 305 ++++++++--------- designs/PE_INT/python/build.py | 207 +++++++++++- designs/PE_INT/python/pe_int/__init__.py | 3 +- designs/PE_INT/python/pe_int/constants.py | 3 +- designs/PE_INT/python/pe_int/decode.py | 9 + designs/PE_INT/python/pe_int/lane_mac.py | 118 ++++++- designs/PE_INT/python/pe_int/mac_modes.py | 31 +- designs/PE_INT/python/pe_int/top.py | 198 ++++++----- designs/PE_INT/python/pe_int_pycircuit.py | 49 +-- designs/PE_INT/rtl/README.md | 24 +- designs/PE_INT/rtl/build/pe_int.v | 308 ++++++++++-------- designs/PE_INT/sim/README.md | 44 +-- designs/PE_INT/sim/run_all_wsl.sh | 67 +--- designs/PE_INT/sim/run_sim.sh | 167 +++------- designs/PE_INT/tb/README.md | 18 +- designs/PE_INT/tb/tb_pe_int_pycircuit.py | 206 ++++++------ designs/PE_INT/tb_rtl/README.md | 24 +- designs/PE_INT/tb_rtl/case/README.md | 38 +-- designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v | 2 +- .../case/tc_mode2a_sanity_rand_timing.v | 2 +- designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v | 2 +- .../case/tc_mode2b_sanity_rand_timing.v | 2 +- designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v | 2 +- .../case/tc_mode2c_sanity_rand_timing.v | 2 +- designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v | 2 +- .../case/tc_mode2d_sanity_rand_timing.v | 2 +- .../tb_rtl/case/tc_mode_switch_random.v | 220 ++++++------- designs/PE_INT/tb_rtl/tb.f | 4 - 34 files changed, 1316 insertions(+), 1061 deletions(-) diff --git a/compiler/frontend/pycircuit/cli.py b/compiler/frontend/pycircuit/cli.py index 5d3d123..030307a 100644 --- a/compiler/frontend/pycircuit/cli.py +++ b/compiler/frontend/pycircuit/cli.py @@ -182,7 +182,11 @@ def _compile_entrypoint( build: Any, *, top_name: str, jit_params: Mapping[str, object] ) -> Module | Design: if _is_timed_domain_build(build): - return compile_cycle_aware(build, name=top_name, **dict(jit_params)) + compiled = compile_cycle_aware(build, name=top_name, **dict(jit_params)) + hierarchical_design = getattr(compiled, "_v5_design", None) + if isinstance(hierarchical_design, Design): + return hierarchical_design + return compiled return jit_compile(build, name=top_name, **dict(jit_params)) diff --git a/designs/PE_INT/.gitignore b/designs/PE_INT/.gitignore index fd9adc6..9ead86f 100644 --- a/designs/PE_INT/.gitignore +++ b/designs/PE_INT/.gitignore @@ -1,8 +1,5 @@ # Tool-generated outputs build/ -!rtl/build/ -!rtl/build/*.v -local_issues/ obj_dir/ sim/logs/ sim/waves/ diff --git a/designs/PE_INT/README.md b/designs/PE_INT/README.md index 98a4aef..dc9bef0 100644 --- a/designs/PE_INT/README.md +++ b/designs/PE_INT/README.md @@ -1,75 +1,68 @@ # PE_INT -Fixed-point / integer vector MAC unit. +定點／整數向量 MAC 單元。實作流程固定為： -Implementation flow: - -`docs/spec.md` -> `python/pe_int_pycircuit.py` -> `pycircuit.cli build` -> `rtl/build/` + `tb/` +`spec.md` -> `python/pe_int_pycircuit.py` -> `pycircuit.cli build` -> `rtl/` + `tb/` ## Baseline -- Spec source: `docs/spec.md` -- Current baseline: `v2.0.5` (see the header in `docs/spec.md`) +- 規格來源：`docs/spec.md` +- 當前 baseline：`v2.0.5`（以 `docs/spec.md` 檔首標註為準） -## Directory Overview +## 目錄 -- `docs/`: formal specifications -- `python/`: PyCircuit design sources and build scripts -- `model/`: golden models and model regressions -- `tb/`: PyCircuit testbench flow (not RTL simulator flow) -- `tb_rtl/`: dedicated RTL test environment (Verilog testbench + cases) -- `sim/`: one-command simulation entrypoints (iverilog / verilator + wave options) -- `rtl/build/`: generated RTL deliverables only +- `docs/`: 正式規格 +- `python/`: PyCircuit 設計與建構腳本 +- `model/`: golden 模型與模型回歸測試 +- `tb/`: pyCircuit 測試（非 RTL 模擬） +- `tb_rtl/`: 專用 RTL 測試環境（Verilog testbench + cases） +- `sim/`: 互動式一鍵仿真入口（可選 iverilog / verilator + 波形） +- `rtl/`: 僅放「由 build 產生」之 RTL 產物說明 -## Key Files +## 主要檔案 -- `model/ref_model.py`: reference math and pack/unpack model for all four modes -- `model/pe_int_pycircuit_eval.py`: cycle-accurate pipeline golden model (`L=4`) -- `model/test_pe_int.py`: model-level random regressions -- `model/gen_rtl_case_vectors.py`: regenerates expected vectors for `tb_rtl/case` -- `python/pe_int_pycircuit.py`: PyCircuit frontend top entry (RTL source of truth) -- `python/build.py`: unified build entry (`python -m pycircuit.cli build`) -- `tb/tb_pe_int_pycircuit.py`: native PyCircuit testbench for `pycc`/sim flow -- `tb_rtl/case/*.v`: RTL testcases (single-mode sanity + mode-switch random) -- `sim/run_all_wsl.sh`: one-command RTL regression (`iverilog` + `verilator`) -- `sim/run_sim.sh`: interactive one-command simulation (seed + simulator + wave) -- `filelist/pe_int.f`: RTL filelist (prefixed with absolute `$PE_INT`) -- `tb_rtl/tb.f`: testbench/case filelist (prefixed with absolute `$PE_INT`) -- `model/model.f`: model filelist (prefixed with absolute `$PE_INT`) +- `model/ref_model.py`: 四模式數學與打包/解包參考模型 +- `model/pe_int_pycircuit_eval.py`: cycle-accurate golden pipeline model（L=3） +- `model/test_pe_int.py`: 模型層隨機回歸（功能與時序對齊） +- `model/gen_rtl_case_vectors.py`: 自動重生 `tb_rtl/case` 的 expected 向量 +- `python/pe_int_pycircuit.py`: pyCircuit frontend 設計入口（source of RTL） +- `python/build.py`: 統一 build 指令（呼叫 `python -m pycircuit.cli build`） +- `tb/tb_pe_int_pycircuit.py`: pyCircuit 原生 testbench（給 `pycc`/sim flow） +- `tb_rtl/case/*.v`: RTL 專用測試案例（單模式 sanity + mode switch random） +- `sim/run_all_wsl.sh`: 一鍵跑 `iverilog` + `verilator` RTL 回歸 +- `sim/run_sim.sh`: 互動式一鍵仿真（每題 5 秒 timeout，含 seed 輸入） +- `filelist/pe_int.f`: RTL filelist（以 `$PE_INT` 絕對路徑為開頭） +- `tb_rtl/tb.f`: 驗證環境/用例 filelist（以 `$PE_INT` 絕對路徑為開頭） +- `model/model.f`: model filelist（以 `$PE_INT` 絕對路徑為開頭） -## Quick Start +## 快速使用 -1) Run golden model tests: +1) 先跑 golden model 測試： ```bash python model/test_pe_int.py ``` -2) Build RTL/simulation artifacts (requires a ready PyCircuit environment): +2) 產生 RTL / sim 產物（需先具備 pyCircuit 環境）： ```bash python python/build.py --target both --out-dir build/pe_int ``` -After each build, sync deliverable RTL artifacts from the build output tree into -`rtl/build/`, then refresh `filelist/pe_int.f` so simulation always resolves the -latest deliverable set. - -3) Run dedicated RTL regressions (WSL): +3) 執行 RTL 專用回歸（WSL）： ```bash bash sim/run_all_wsl.sh ``` -Or use interactive one-command simulation (WSL): +或使用互動式一鍵仿真入口（WSL）： ```bash bash sim/run_sim.sh ``` -## Process Constraints +## 流程約束 -- Do not handwrite `rtl/build/*.v`. -- After each build, sync deliverable artifacts into `rtl/build/` and refresh `filelist/pe_int.f`. -- `vld_out` must align with `out0`/`out1`; under mode `2a`, `out1` uses hold policy to avoid unnecessary toggles. -- On a new machine without existing profiles, bootstrap the environment from `LinxISA/pyCircuit` first. +- 不手寫 `rtl/*.v`。 +- `vld_out` 與 `out0`/`out1` 對齊，`2a` 下 `out1` 採 hold 策略以避免無謂切換。 +- 任何新機器若沒有既有 profile，先依 `LinxISA/pyCircuit` repo 完成環境再執行本流程。 diff --git a/designs/PE_INT/memory.md b/designs/PE_INT/memory.md index b2dfacd..d1181be 100644 --- a/designs/PE_INT/memory.md +++ b/designs/PE_INT/memory.md @@ -1,3 +1,3 @@ # Memory -- Test result wording preference: use only `pass/fail` (avoid phrases like "all green"). +- 測試結果回報格式偏好：僅使用 `pass/fail`（避免使用「全綠」等說法）。 diff --git a/designs/PE_INT/model/README.md b/designs/PE_INT/model/README.md index 92ee004..c65fb8b 100644 --- a/designs/PE_INT/model/README.md +++ b/designs/PE_INT/model/README.md @@ -1,21 +1,21 @@ -# model (Models and Model Tests) +# model（模型與模型測試） -This directory centralizes all model assets used for verification and comparison. +本目錄集中管理所有「驗證比對所依據的模型」與模型測試。 -## Contents +## 內容 -- `ref_model.py`: reference math and pack/unpack model for all four modes -- `pe_int_pycircuit_eval.py`: cycle-accurate pipeline model (`L=4`) -- `test_pe_int.py`: model-layer regression tests (without direct RTL simulator invocation) -- `gen_rtl_case_vectors.py`: generates testcase vectors and expected values for `tb_rtl/case` -- `model.f`: model filelist (prefixed with absolute `$PE_INT`) +- `ref_model.py`: 四模式數學語義與打包/解包參考模型 +- `pe_int_pycircuit_eval.py`: cycle-accurate pipeline 模型（L=3） +- `test_pe_int.py`: 模型層回歸測試（不直接跑 RTL simulator） +- `gen_rtl_case_vectors.py`: 依模型自動產生 `tb_rtl/case` 的 testcase 向量與 expected +- `model.f`: model 檔案清單（以 `$PE_INT` 絕對路徑為開頭） -## Principles +## 原則 -- Any verification needing golden/model comparison must use this directory as source of truth. -- If `tb/` or `tb_rtl/` uses expected values, they must be traceable back to `model/`. +- 凡是驗證需要 golden/model 比對，應以本目錄內容為依據。 +- `tb/` 與 `tb_rtl/` 的用例若有 expected 值，來源需可追溯到 `model/`。 -## Run +## 執行 ```bash python model/test_pe_int.py diff --git a/designs/PE_INT/model/pe_int_pycircuit_eval.py b/designs/PE_INT/model/pe_int_pycircuit_eval.py index b93679a..00f4363 100644 --- a/designs/PE_INT/model/pe_int_pycircuit_eval.py +++ b/designs/PE_INT/model/pe_int_pycircuit_eval.py @@ -1,106 +1,100 @@ -from __future__ import annotations - -from dataclasses import dataclass -from typing import List - -from ref_model import MODE_2A, MacResult, compute_transaction, to_signed - -DEFAULT_PIPELINE_L = 4 - - -@dataclass -class StagePayload: - vld: int = 0 - mode: int = 0 - out0_19: int = 0 - out1_16: int = 0 - - -@dataclass -class StepResult: - vld_out: int - out0: int - out1: int - - -class PEIntL3Model: - """ - Cycle-accurate model with normative 0-based latency: - accepted at t0 -> committed output at t0+4. - """ - - def __init__(self) -> None: - self.pipe: List[StagePayload] = [StagePayload() for _ in range(DEFAULT_PIPELINE_L)] - self.out0 = 0 - self.out1 = 0 - self.vld_out = 0 - self.out1_hold = 0 - - def reset(self) -> None: - self.pipe = [StagePayload() for _ in range(DEFAULT_PIPELINE_L)] - self.out0 = 0 - self.out1 = 0 - self.vld_out = 0 - self.out1_hold = 0 - - def _next_stage0( - self, - *, - vld: int, - mode: int, - a: int, - b: int, - b1: int, - e1_a: tuple[int, int], - e1_b0: tuple[int, int], - e1_b1: tuple[int, int], - ) -> StagePayload: - if not vld: - return StagePayload(vld=0, mode=mode & 0x3, out0_19=0, out1_16=0) - mac: MacResult = compute_transaction(mode, a, b, b1, e1_a, e1_b0, e1_b1) - return StagePayload( - vld=1, - mode=mode & 0x3, - out0_19=to_signed(mac.out0_19, 19), - out1_16=to_signed(mac.out1_16, 16), - ) - - def step( - self, - *, - rst_n: int, - vld: int, - mode: int, - a: int, - b: int, - b1: int, - e1_a: tuple[int, int], - e1_b0: tuple[int, int], - e1_b1: tuple[int, int], - ) -> StepResult: - if not rst_n: - self.reset() - return StepResult(vld_out=0, out0=0, out1=0) - - commit = self.pipe[-1] - if commit.vld: - self.out0 = to_signed(commit.out0_19, 19) - if commit.mode != MODE_2A: - self.out1_hold = to_signed(commit.out1_16, 16) - self.vld_out = int(commit.vld) - self.out1 = to_signed(self.out1_hold, 16) - - for idx in range(DEFAULT_PIPELINE_L - 1, 0, -1): - prev = self.pipe[idx - 1] - self.pipe[idx] = StagePayload(prev.vld, prev.mode, prev.out0_19, prev.out1_16) - self.pipe[0] = self._next_stage0( - vld=vld, - mode=mode, - a=a, - b=b, - b1=b1, - e1_a=e1_a, - e1_b0=e1_b0, - e1_b1=e1_b1, - ) - return StepResult(vld_out=self.vld_out, out0=self.out0, out1=self.out1) +from __future__ import annotations + +from dataclasses import dataclass + +from ref_model import MODE_2A, MacResult, compute_transaction, to_signed + +DEFAULT_PIPELINE_L = 3 + + +@dataclass +class StagePayload: + vld: int = 0 + mode: int = 0 + out0_19: int = 0 + out1_16: int = 0 + + +@dataclass +class StepResult: + vld_out: int + out0: int + out1: int + + +class PEIntL3Model: + """Cycle-accurate PE_INT model for golden checking.""" + + def __init__(self) -> None: + self.s0 = StagePayload() + self.s1 = StagePayload() + self.s2 = StagePayload() + self.out0 = 0 + self.out1 = 0 + self.vld_out = 0 + # If reset has never been asserted, skip release window at power-up. + self._rst_release_count = 2 + + def reset(self) -> None: + self.s0 = StagePayload() + self.s1 = StagePayload() + self.s2 = StagePayload() + self.out0 = 0 + self.out1 = 0 + self.vld_out = 0 + self._rst_release_count = 0 + + def step( + self, + *, + rst_n: int, + vld: int, + mode: int, + a: int, + b: int, + b1: int, + e1_a: tuple[int, int], + e1_b0: tuple[int, int], + e1_b1: tuple[int, int], + ) -> StepResult: + if not rst_n: + self.reset() + return StepResult(vld_out=0, out0=0, out1=0) + + if self._rst_release_count < 2: + self._rst_release_count += 1 + self.s0 = StagePayload() + self.s1 = StagePayload() + self.s2 = StagePayload() + self.vld_out = 0 + self.out0 = 0 + self.out1 = 0 + return StepResult(vld_out=0, out0=0, out1=0) + + new_vld_out = self.s2.vld + new_out0 = self.out0 + new_out1 = self.out1 + if self.s2.vld: + new_out0 = to_signed(self.s2.out0_19, 19) + if self.s2.mode != MODE_2A: + new_out1 = to_signed(self.s2.out1_16, 16) + + if vld: + mac: MacResult = compute_transaction(mode, a, b, b1, e1_a, e1_b0, e1_b1) + next_s0 = StagePayload( + vld=1, + mode=mode & 0x3, + out0_19=to_signed(mac.out0_19, 19), + out1_16=to_signed(mac.out1_16, 16), + ) + else: + next_s0 = StagePayload(vld=0, mode=mode & 0x3, out0_19=0, out1_16=0) + + self.s2 = StagePayload(self.s1.vld, self.s1.mode, self.s1.out0_19, self.s1.out1_16) + self.s1 = StagePayload(self.s0.vld, self.s0.mode, self.s0.out0_19, self.s0.out1_16) + self.s0 = next_s0 + + self.vld_out = new_vld_out + self.out0 = to_signed(new_out0, 19) + self.out1 = to_signed(new_out1, 16) + return StepResult(vld_out=self.vld_out, out0=self.out0, out1=self.out1) diff --git a/designs/PE_INT/model/ref_model.py b/designs/PE_INT/model/ref_model.py index a83fac4..a29deb9 100644 --- a/designs/PE_INT/model/ref_model.py +++ b/designs/PE_INT/model/ref_model.py @@ -1,152 +1,153 @@ -from __future__ import annotations - -from dataclasses import dataclass -from typing import List, Sequence, Tuple - -MODE_2A = 0 -MODE_2B = 1 -MODE_2C = 2 -MODE_2D = 3 - - -def _mask(width: int) -> int: - return (1 << width) - 1 - - -def to_signed(value: int, width: int) -> int: - value &= _mask(width) - sign = 1 << (width - 1) - return value - (1 << width) if value & sign else value - - -def get_lane5(word80: int, lane_idx: int) -> int: - return (word80 >> (5 * lane_idx)) & 0x1F - - -def decode_s8x8_from_laneword(word80: int) -> List[int]: - vals: List[int] = [] - for idx in range(8): - lo = (get_lane5(word80, 2 * idx) >> 1) & 0xF - hi = (get_lane5(word80, 2 * idx + 1) >> 1) & 0xF - vals.append(to_signed((hi << 4) | lo, 8)) - return vals - - -def decode_s4x8_from_40(word40: int) -> List[int]: - vals: List[int] = [] - for idx in range(8): - lane = (word40 >> (5 * idx)) & 0x1F - vals.append(to_signed((lane >> 1) & 0xF, 4)) - return vals - - -def decode_s5x8_from_40(word40: int) -> List[int]: - return [to_signed((word40 >> (5 * idx)) & 0x1F, 5) for idx in range(8)] - - -def decode_s5x16_from_80(word80: int) -> List[int]: - return [to_signed((word80 >> (5 * idx)) & 0x1F, 5) for idx in range(16)] - - -def _e1_shift(e1_pair_a: Sequence[int], e1_pair_b: Sequence[int]) -> Tuple[int, int]: - sh_lo = int(e1_pair_a[0]) + int(e1_pair_b[0]) - sh_hi = int(e1_pair_a[1]) + int(e1_pair_b[1]) - return sh_lo, sh_hi - - -@dataclass(frozen=True) -class MacResult: - out0_19: int - out1_16: int - - -def compute_transaction( - mode: int, - a80: int, - b80: int, - b1_80: int, - e1_a: Sequence[int], - e1_b0: Sequence[int], - e1_b1: Sequence[int], -) -> MacResult: - mode &= 0x3 - a80 &= _mask(80) - b80 &= _mask(80) - b1_80 &= _mask(80) - - if mode == MODE_2A: - a = decode_s8x8_from_laneword(a80) - b = decode_s8x8_from_laneword(b80) - sum0 = sum(x * y for x, y in zip(a, b)) - return MacResult(to_signed(sum0, 19), 0) - - if mode == MODE_2B: - a = decode_s8x8_from_laneword(a80) - b0 = decode_s4x8_from_40(b80 & _mask(40)) - b1 = decode_s4x8_from_40((b80 >> 40) & _mask(40)) - sum0 = sum(x * y for x, y in zip(a, b0)) - sum1 = sum(x * y for x, y in zip(a, b1)) - return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) - - if mode == MODE_2D: - a = decode_s8x8_from_laneword(a80) - b0 = decode_s5x8_from_40(b80 & _mask(40)) - b1 = decode_s5x8_from_40((b80 >> 40) & _mask(40)) - sum0 = sum(x * y for x, y in zip(a, b0)) - sum1 = sum(x * y for x, y in zip(a, b1)) - return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) - - a = decode_s5x16_from_80(a80) - b0 = decode_s5x16_from_80(b80) - b1 = decode_s5x16_from_80(b1_80) - lo0 = sum(a[idx] * b0[idx] for idx in range(8)) - hi0 = sum(a[idx] * b0[idx] for idx in range(8, 16)) - lo1 = sum(a[idx] * b1[idx] for idx in range(8)) - hi1 = sum(a[idx] * b1[idx] for idx in range(8, 16)) - - sh0_lo, sh0_hi = _e1_shift(e1_a, e1_b0) - sh1_lo, sh1_hi = _e1_shift(e1_a, e1_b1) - sum0 = (lo0 << sh0_lo) + (hi0 << sh0_hi) - sum1 = (lo1 << sh1_lo) + (hi1 << sh1_hi) - return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) - - -def pack_s8x8_to_laneword(values: Sequence[int]) -> int: - if len(values) != 8: - raise ValueError("need 8 S8 values") - word = 0 - for idx, val in enumerate(values): - raw = val & 0xFF - lane_lo = (raw & 0xF) << 1 - lane_hi = ((raw >> 4) & 0xF) << 1 - word |= lane_lo << (5 * (2 * idx)) - word |= lane_hi << (5 * (2 * idx + 1)) - return word - - -def pack_s4x8_to_40(values: Sequence[int]) -> int: - if len(values) != 8: - raise ValueError("need 8 S4 values") - word = 0 - for idx, val in enumerate(values): - lane = ((val & 0xF) << 1) & 0x1F - word |= lane << (5 * idx) - return word - - -def pack_s5x8_to_40(values: Sequence[int]) -> int: - if len(values) != 8: - raise ValueError("need 8 S5 values") - word = 0 - for idx, val in enumerate(values): - word |= (val & 0x1F) << (5 * idx) - return word - - -def pack_s5x16_to_80(values: Sequence[int]) -> int: - if len(values) != 16: - raise ValueError("need 16 S5 values") - word = 0 - for idx, val in enumerate(values): - word |= (val & 0x1F) << (5 * idx) - return word +from __future__ import annotations + +from dataclasses import dataclass +from typing import List, Sequence, Tuple + +MODE_2A = 0 +MODE_2B = 1 +MODE_2C = 2 +MODE_2D = 3 + + +def _mask(width: int) -> int: + return (1 << width) - 1 + + +def to_signed(value: int, width: int) -> int: + value &= _mask(width) + sign = 1 << (width - 1) + return value - (1 << width) if value & sign else value + + +def get_lane5(word80: int, lane_idx: int) -> int: + return (word80 >> (5 * lane_idx)) & 0x1F + + +def decode_s8x8_from_laneword(word80: int) -> List[int]: + vals: List[int] = [] + for i in range(8): + lo = (get_lane5(word80, 2 * i) >> 1) & 0xF + hi = (get_lane5(word80, 2 * i + 1) >> 1) & 0xF + vals.append(to_signed((hi << 4) | lo, 8)) + return vals + + +def decode_s4x8_from_40(word40: int) -> List[int]: + vals: List[int] = [] + for i in range(8): + lane = (word40 >> (5 * i)) & 0x1F + vals.append(to_signed((lane >> 1) & 0xF, 4)) + return vals + + +def decode_s5x8_from_40(word40: int) -> List[int]: + return [to_signed((word40 >> (5 * i)) & 0x1F, 5) for i in range(8)] + + +def decode_s5x16_from_80(word80: int) -> List[int]: + return [to_signed((word80 >> (5 * i)) & 0x1F, 5) for i in range(16)] + + +def _e1_shift(e1_pair_a: Sequence[int], e1_pair_b: Sequence[int]) -> Tuple[int, int]: + sh_lo = int(e1_pair_a[0]) + int(e1_pair_b[0]) + sh_hi = int(e1_pair_a[1]) + int(e1_pair_b[1]) + return sh_lo, sh_hi + + +@dataclass(frozen=True) +class MacResult: + out0_19: int + out1_16: int + + +def compute_transaction( + mode: int, + a80: int, + b80: int, + b1_80: int, + e1_a: Sequence[int], + e1_b0: Sequence[int], + e1_b1: Sequence[int], +) -> MacResult: + mode &= 0x3 + a80 &= _mask(80) + b80 &= _mask(80) + b1_80 &= _mask(80) + + if mode == MODE_2A: + a = decode_s8x8_from_laneword(a80) + b = decode_s8x8_from_laneword(b80) + sum0 = sum(x * y for x, y in zip(a, b)) + return MacResult(to_signed(sum0, 19), 0) + + if mode == MODE_2B: + a = decode_s8x8_from_laneword(a80) + b0 = decode_s4x8_from_40(b80 & _mask(40)) + b1 = decode_s4x8_from_40((b80 >> 40) & _mask(40)) + sum0 = sum(x * y for x, y in zip(a, b0)) + sum1 = sum(x * y for x, y in zip(a, b1)) + return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) + + if mode == MODE_2D: + a = decode_s8x8_from_laneword(a80) + b0 = decode_s5x8_from_40(b80 & _mask(40)) + b1 = decode_s5x8_from_40((b80 >> 40) & _mask(40)) + sum0 = sum(x * y for x, y in zip(a, b0)) + sum1 = sum(x * y for x, y in zip(a, b1)) + return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) + + # MODE_2C + a = decode_s5x16_from_80(a80) + b0 = decode_s5x16_from_80(b80) + b1 = decode_s5x16_from_80(b1_80) + lo0 = sum(a[i] * b0[i] for i in range(8)) + hi0 = sum(a[i] * b0[i] for i in range(8, 16)) + lo1 = sum(a[i] * b1[i] for i in range(8)) + hi1 = sum(a[i] * b1[i] for i in range(8, 16)) + + sh0_lo, sh0_hi = _e1_shift(e1_a, e1_b0) + sh1_lo, sh1_hi = _e1_shift(e1_a, e1_b1) + sum0 = (lo0 << sh0_lo) + (hi0 << sh0_hi) + sum1 = (lo1 << sh1_lo) + (hi1 << sh1_hi) + return MacResult(to_signed(sum0, 19), to_signed(sum1, 16)) + + +def pack_s8x8_to_laneword(values: Sequence[int]) -> int: + if len(values) != 8: + raise ValueError("need 8 S8 values") + word = 0 + for i, val in enumerate(values): + raw = val & 0xFF + lane_lo = (raw & 0xF) << 1 + lane_hi = ((raw >> 4) & 0xF) << 1 + word |= lane_lo << (5 * (2 * i)) + word |= lane_hi << (5 * (2 * i + 1)) + return word + + +def pack_s4x8_to_40(values: Sequence[int]) -> int: + if len(values) != 8: + raise ValueError("need 8 S4 values") + word = 0 + for i, val in enumerate(values): + lane = ((val & 0xF) << 1) & 0x1F + word |= lane << (5 * i) + return word + + +def pack_s5x8_to_40(values: Sequence[int]) -> int: + if len(values) != 8: + raise ValueError("need 8 S5 values") + word = 0 + for i, val in enumerate(values): + word |= (val & 0x1F) << (5 * i) + return word + + +def pack_s5x16_to_80(values: Sequence[int]) -> int: + if len(values) != 16: + raise ValueError("need 16 S5 values") + word = 0 + for i, val in enumerate(values): + word |= (val & 0x1F) << (5 * i) + return word diff --git a/designs/PE_INT/python/build.py b/designs/PE_INT/python/build.py index 2895665..ed5de26 100644 --- a/designs/PE_INT/python/build.py +++ b/designs/PE_INT/python/build.py @@ -2,27 +2,225 @@ import argparse import os +import re +import shutil import subprocess import sys from pathlib import Path +_DELIVERABLE_MODULE_RENAMES = { + "pyc_reg": "PYC_REG", + "pyc_fifo": "PYC_FIFO", + "pyc_byte_mem": "PYC_BYTE_MEM", + "pyc_sync_mem": "PYC_SYNC_MEM", + "pyc_sync_mem_dp": "PYC_SYNC_MEM_DP", + "pyc_async_fifo": "PYC_ASYNC_FIFO", + "pyc_cdc_sync": "PYC_CDC_SYNC", +} + + +def _normalize_module_identifier_case(verilog_text: str) -> str: + """Use uppercase module identifiers in deliverable RTL while keeping net names intact.""" + for source_name, deliverable_name in _DELIVERABLE_MODULE_RENAMES.items(): + verilog_text = re.sub(rf"\b{re.escape(source_name)}\b", deliverable_name, verilog_text) + return verilog_text + + +def _normalize_primitives_reset_style(primitives_text: str) -> str: + """Make generated PE_INT primitives match the deliverable reset contract.""" + sync_reg = """// --- pyc_reg.v +// Simple synchronous reset register (prototype). +module pyc_reg #( + parameter WIDTH = 1 +) ( + input clk, + input rst, + input en, + input [WIDTH-1:0] d, + input [WIDTH-1:0] init, + output reg [WIDTH-1:0] q +); + always @(posedge clk) begin + if (rst) + q <= init; + else if (en) + q <= d; + end +endmodule +""" + async_reg = """// --- pyc_reg.v +// Register with asynchronous reset assertion for PE_INT deliverable RTL. +module pyc_reg #( + parameter WIDTH = 1 +) ( + input clk, + input rst, + input en, + input [WIDTH-1:0] d, + input [WIDTH-1:0] init, + output reg [WIDTH-1:0] q +); + always @(posedge clk or posedge rst) begin + if (rst) + q <= init; + else if (en) + q <= d; + end +endmodule +""" + if async_reg in primitives_text: + return primitives_text + if sync_reg not in primitives_text: + raise RuntimeError("Unable to locate expected pyc_reg primitive for reset normalization.") + return primitives_text.replace(sync_reg, async_reg, 1) + + +def _find_module_port_list_end(verilog_text: str, module_name: str) -> int: + match = re.search(rf"\bmodule\s+{re.escape(module_name)}\b", verilog_text) + if not match: + raise RuntimeError(f"Unable to locate module declaration for {module_name}.") + + idx = match.end() + while idx < len(verilog_text): + if verilog_text.startswith("//", idx): + newline = verilog_text.find("\n", idx) + idx = len(verilog_text) if newline < 0 else newline + 1 + continue + if verilog_text.startswith("/*", idx): + end_comment = verilog_text.find("*/", idx + 2) + if end_comment < 0: + raise RuntimeError(f"Unterminated block comment in module {module_name} declaration.") + idx = end_comment + 2 + continue + if verilog_text[idx] == "(": + depth = 1 + idx += 1 + while idx < len(verilog_text) and depth: + if verilog_text.startswith("//", idx): + newline = verilog_text.find("\n", idx) + idx = len(verilog_text) if newline < 0 else newline + 1 + continue + if verilog_text.startswith("/*", idx): + end_comment = verilog_text.find("*/", idx + 2) + if end_comment < 0: + raise RuntimeError(f"Unterminated block comment in module {module_name} port list.") + idx = end_comment + 2 + continue + if verilog_text[idx] == "(": + depth += 1 + elif verilog_text[idx] == ")": + depth -= 1 + idx += 1 + if depth: + raise RuntimeError(f"Unterminated module port list for {module_name}.") + while idx < len(verilog_text) and verilog_text[idx].isspace(): + idx += 1 + if idx < len(verilog_text) and verilog_text[idx] == ";": + return idx + 1 + raise RuntimeError(f"Module {module_name} port list is not followed by a semicolon.") + idx += 1 + + raise RuntimeError(f"Unable to find end of port list for module {module_name}.") + + +def _insert_internal_reset_wire(top_text: str, module_name: str = "PE_INT") -> str: + reset_decl = "\n\nwire rst;\nassign rst = ~rst_n;\n" + if "assign rst = ~rst_n;" in top_text: + return top_text + insert_idx = _find_module_port_list_end(top_text, module_name) + return top_text[:insert_idx] + reset_decl + top_text[insert_idx:] + + +def _load_current_design_name(repo_root: Path) -> str: + py_dir = repo_root / "python" + if str(py_dir) not in sys.path: + sys.path.insert(0, str(py_dir)) + try: + import pe_int_pycircuit # type: ignore + except Exception as exc: # pragma: no cover - environment-dependent import path. + raise RuntimeError(f"Unable to import pe_int_pycircuit to resolve design name: {exc}") from exc + design_name = getattr(pe_int_pycircuit.build, "__pycircuit_name__", "") + if not design_name: + raise RuntimeError("Missing build.__pycircuit_name__ in pe_int_pycircuit.") + return str(design_name) + + +def _sync_generated_rtl(repo_root: Path, out_dir: Path, design_name: str) -> None: + verilog_root = out_dir / "device" / "verilog" + design_dir = verilog_root / design_name + design_verilog = design_dir / f"{design_name}.v" + primitives_verilog = design_dir / "pyc_primitives.v" + if not design_verilog.exists(): + raise RuntimeError(f"Generated design verilog not found: {design_verilog}") + if not primitives_verilog.exists(): + raise RuntimeError(f"Generated primitives verilog not found: {primitives_verilog}") + + rtl_dir = repo_root / "rtl" / "build" + rtl_dir.mkdir(parents=True, exist_ok=True) + for stale_verilog in rtl_dir.glob("*.v"): + stale_verilog.unlink() + dst_top = rtl_dir / "pe_int.v" + dst_primitives = rtl_dir / "pyc_primitives.v" + dst_submodules: list[Path] = [] + + top_text = design_verilog.read_text(encoding="utf-8") + if design_name != "PE_INT": + top_text = re.sub(rf"\bmodule\s+{re.escape(design_name)}\b", "module PE_INT", top_text, count=1) + top_text = re.sub(rf"\bendmodule\s*//\s*{re.escape(design_name)}\b", "endmodule // PE_INT", top_text) + + if re.search(r"^\s*input\s+rst,\s*$", top_text, flags=re.MULTILINE): + top_text = re.sub(r"^\s*input\s+rst,\s*$\n?", "", top_text, count=1, flags=re.MULTILINE) + top_text = _insert_internal_reset_wire(top_text) + + dst_top.write_text(_normalize_module_identifier_case(top_text), encoding="utf-8") + primitives_text = primitives_verilog.read_text(encoding="utf-8") + primitives_text = _normalize_primitives_reset_style(primitives_text) + dst_primitives.write_text(_normalize_module_identifier_case(primitives_text), encoding="utf-8") + + for module_dir in sorted(path for path in verilog_root.iterdir() if path.is_dir()): + if module_dir.name == design_name: + continue + module_verilog = module_dir / f"{module_dir.name}.v" + if not module_verilog.exists(): + continue + dst_module = rtl_dir / f"{module_dir.name.lower()}.v" + module_text = module_verilog.read_text(encoding="utf-8") + dst_module.write_text(_normalize_module_identifier_case(module_text), encoding="utf-8") + dst_submodules.append(dst_module) + + filelist = repo_root / "filelist" / "pe_int.f" + filelist.parent.mkdir(parents=True, exist_ok=True) + filelist_lines = ["$PE_INT/rtl/build/pyc_primitives.v"] + filelist_lines.extend(f"$PE_INT/rtl/build/{path.name}" for path in dst_submodules) + filelist_lines.append("$PE_INT/rtl/build/pe_int.v") + filelist.write_text("\n".join(filelist_lines) + "\n", encoding="utf-8") + + def main() -> int: parser = argparse.ArgumentParser(description="Build PE_INT via pyCircuit/pycc.") parser.add_argument("--out-dir", default="build/pe_int", help="pycircuit build output directory") parser.add_argument("--target", default="both", choices=("rtl", "sim", "both"), help="build target") parser.add_argument("--jobs", default="8", help="parallel jobs for pycircuit build") + parser.add_argument( + "--pyc-tb-vectors", + default=os.environ.get("PE_INT_PYC_TB_VEC_PER_CASE", "8"), + help="number of vectors per PyCircuit-level testcase (default: smoke-sized 8)", + ) args = parser.parse_args() repo_root = Path(__file__).resolve().parents[1] tb_file = repo_root / "tb" / "tb_pe_int_pycircuit.py" out_dir = repo_root / args.out_dir out_dir.mkdir(parents=True, exist_ok=True) + shutil.rmtree(out_dir / "device", ignore_errors=True) + shutil.rmtree(out_dir / "cpp_build", ignore_errors=True) env = os.environ.copy() py_path = env.get("PYTHONPATH", "") if str(repo_root / "python") not in py_path: env["PYTHONPATH"] = str(repo_root / "python") + (os.pathsep + py_path if py_path else "") + env["PE_INT_PYC_TB_VEC_PER_CASE"] = str(args.pyc_tb_vectors) cmd = [ sys.executable, @@ -38,7 +236,14 @@ def main() -> int: str(args.jobs), ] print("Running:", " ".join(cmd)) - return subprocess.call(cmd, cwd=str(repo_root), env=env) + result = subprocess.call(cmd, cwd=str(repo_root), env=env) + if result: + return int(result) + + design_name = _load_current_design_name(repo_root) + _sync_generated_rtl(repo_root, out_dir, design_name) + print(f"Synced generated RTL into {repo_root / 'rtl' / 'build'} and refreshed filelist/pe_int.f") + return 0 if __name__ == "__main__": diff --git a/designs/PE_INT/python/pe_int/__init__.py b/designs/PE_INT/python/pe_int/__init__.py index 50d90f2..1c458f7 100644 --- a/designs/PE_INT/python/pe_int/__init__.py +++ b/designs/PE_INT/python/pe_int/__init__.py @@ -1,4 +1,4 @@ -from .constants import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D +from .constants import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, SPEC_LATENCY_L from .top import build, emit_mlir __all__ = [ @@ -7,6 +7,7 @@ "MODE_2C", "MODE_2D", "DEFAULT_PIPELINE_L", + "SPEC_LATENCY_L", "build", "emit_mlir", ] diff --git a/designs/PE_INT/python/pe_int/constants.py b/designs/PE_INT/python/pe_int/constants.py index 3183576..2a5db38 100644 --- a/designs/PE_INT/python/pe_int/constants.py +++ b/designs/PE_INT/python/pe_int/constants.py @@ -5,7 +5,8 @@ MODE_2C = 2 MODE_2D = 3 -DEFAULT_PIPELINE_L = 3 +DEFAULT_PIPELINE_L = 4 +SPEC_LATENCY_L = DEFAULT_PIPELINE_L LANE_WORD_W = 80 LANE5_W = 5 diff --git a/designs/PE_INT/python/pe_int/decode.py b/designs/PE_INT/python/pe_int/decode.py index c2ec31b..32808d4 100644 --- a/designs/PE_INT/python/pe_int/decode.py +++ b/designs/PE_INT/python/pe_int/decode.py @@ -12,6 +12,15 @@ def sext(value, bits: int): return raw._sext(width=bits) +def zext(value, bits: int): + if hasattr(value, "zext"): + return value.zext(width=bits) + raw = wire_of(value) + if hasattr(raw, "zext"): + return raw.zext(width=bits) + return raw._zext(width=bits) + + def lane5(word, idx: int): lo = 5 * idx return wire_of(word)[lo : lo + 5] diff --git a/designs/PE_INT/python/pe_int/lane_mac.py b/designs/PE_INT/python/pe_int/lane_mac.py index 65eae7a..7e3402b 100644 --- a/designs/PE_INT/python/pe_int/lane_mac.py +++ b/designs/PE_INT/python/pe_int/lane_mac.py @@ -2,7 +2,12 @@ from typing import Sequence -from pycircuit import mux, wire_of +from pycircuit import cas, cat, mux, wire_of + +from .decode import zext + + +REDUCE_W = 32 def booth_mul_signed(lhs, rhs): @@ -14,13 +19,90 @@ def booth_mul_signed(lhs, rhs): return lhs * rhs -def dot8_reduce(products: Sequence[object]): +def _pack_lsb_bits(bits: Sequence[object]): + return cat(*reversed(bits)) + + +def _bit(value, idx: int): + return wire_of(value)[idx : idx + 1] + + +def _shift_carry_bits(carry_bits: Sequence[object], *, width: int = REDUCE_W): + return cat(*reversed(carry_bits[: width - 1]), 0) + + +def ha(lhs, rhs): + lhs_w = wire_of(lhs)[0:1] + rhs_w = wire_of(rhs)[0:1] + return lhs_w ^ rhs_w, lhs_w & rhs_w + + +def fa(lhs, rhs, carry_in): + lhs_w = wire_of(lhs)[0:1] + rhs_w = wire_of(rhs)[0:1] + carry_in_w = wire_of(carry_in)[0:1] + + sum_bit = lhs_w ^ rhs_w ^ carry_in_w + carry_bit = (lhs_w & rhs_w) | (lhs_w & carry_in_w) | (rhs_w & carry_in_w) + return sum_bit, carry_bit + + +def cmpe42(in0, in1, in2, in3, cix, *, width: int = REDUCE_W): + in0_w = wire_of(in0)[0:width] + in1_w = wire_of(in1)[0:width] + in2_w = wire_of(in2)[0:width] + in3_w = wire_of(in3)[0:width] + cix_bit = wire_of(cix)[0:1] + + sum_bits = [] + carry_bits = [] + cox_bits = [] + for bit_idx in range(width): + pre_sum, cox_bit = fa(_bit(in0_w, bit_idx), _bit(in1_w, bit_idx), _bit(in2_w, bit_idx)) + sum_bit, carry_bit = fa(pre_sum, _bit(in3_w, bit_idx), cix_bit) + sum_bits.append(sum_bit) + carry_bits.append(carry_bit) + cox_bits.append(cox_bit) + cix_bit = cox_bit + + return _pack_lsb_bits(sum_bits), _shift_carry_bits(carry_bits, width=width), cox_bits[-1] + + +def _wallace_dot8_reduce(products: Sequence[object], *, width: int = REDUCE_W): if len(products) != 8: raise ValueError("dot8_reduce expects exactly 8 products") - acc = products[0] - for idx in range(1, 8): - acc = acc + products[idx] - return acc + terms = [wire_of(product)[0:width] for product in products] + zero_cix = _bit(terms[0], 0) & 0 + + # Wallace-style carry-save tree using explicit 4:2 compressors. The final + # row merge is intentionally left as the only CPA in this reduction. + lo_sum, lo_carry, _ = cmpe42(terms[0], terms[1], terms[2], terms[3], zero_cix, width=width) + hi_sum, hi_carry, _ = cmpe42(terms[4], terms[5], terms[6], terms[7], zero_cix, width=width) + final_sum, final_carry, _ = cmpe42(lo_sum, lo_carry, hi_sum, hi_carry, zero_cix, width=width) + return final_sum + final_carry + + +def wallace_dot8_tree(m, domain, *, inputs: dict | None = None, width: int = REDUCE_W, prefix: str = "wallace_dot8"): + terms = [] + for idx in range(8): + key = f"in{idx}" + if inputs is not None and key in inputs: + terms.append(inputs[key]) + else: + terms.append(m.input(f"{prefix}_{key}", width=width)) + + result = cas(domain, _wallace_dot8_reduce(terms, width=width), cycle=0) + outs = {"sum": result} + if inputs is None: + m.output(f"{prefix}_sum", wire_of(result)) + return outs + + +wallace_dot8_tree.__pycircuit_name__ = "PE_INT_WALLACE_DOT8_TREE" + + +def dot8_reduce(products: Sequence[object]): + return _wallace_dot8_reduce(products) def dot16_split8_reduce(products: Sequence[object]): @@ -35,17 +117,31 @@ def shift_scale_x1_x2_x4(value, shift2b): """ DS §3.3: use 2-level muxed shift (x1/x2/x4), avoid barrel shifter. """ - return mux(shift2b == 0, value, mux(shift2b == 1, value * 2, value * 4)) + value_w = wire_of(value) + return wire_of(shift2b == 0)._select_internal( + value_w, + wire_of(shift2b == 1)._select_internal(value_w << 1, value_w << 2), + ) def select_one_hot4(sel0, sel1, sel2, sel3, cand0, cand1, cand2, cand3): """ - One-hot selection network to avoid deep priority mux chain. + One-hot mode selection. Use muxes instead of boolean-masked + multiplication so PyCircuit does not insert balancing registers in comb3. """ - return (cand0 * sel0) + (cand1 * sel1) + (cand2 * sel2) + (cand3 * sel3) + _ = sel3 + return wire_of(sel0)._select_internal( + wire_of(cand0), + wire_of(sel1)._select_internal( + wire_of(cand1), + wire_of(sel2)._select_internal(wire_of(cand2), wire_of(cand3)), + ), + ) def sum_shift_pair(lo, hi, e1_a, e1_b): - sh_lo = wire_of(e1_a)[0:1] + wire_of(e1_b)[0:1] - sh_hi = wire_of(e1_a)[1:2] + wire_of(e1_b)[1:2] + e1_a_w = wire_of(e1_a) + e1_b_w = wire_of(e1_b) + sh_lo = zext(e1_a_w[0:1], 2) + zext(e1_b_w[0:1], 2) + sh_hi = zext(e1_a_w[1:2], 2) + zext(e1_b_w[1:2], 2) return shift_scale_x1_x2_x4(lo, sh_lo) + shift_scale_x1_x2_x4(hi, sh_hi) diff --git a/designs/PE_INT/python/pe_int/mac_modes.py b/designs/PE_INT/python/pe_int/mac_modes.py index 3d37850..684a2eb 100644 --- a/designs/PE_INT/python/pe_int/mac_modes.py +++ b/designs/PE_INT/python/pe_int/mac_modes.py @@ -3,7 +3,7 @@ from pycircuit import wire_of from .decode import decode_s4_from_40, decode_s4_hi_from_80, decode_s5, decode_s5_hi_from_80, decode_s8_from_lane_word -from .lane_mac import booth_mul_signed, dot8_reduce, dot16_split8_reduce, select_one_hot4, sum_shift_pair +from .lane_mac import booth_mul_signed, select_one_hot4, sum_shift_pair, wallace_dot8_tree def _mode_one_hot(mode): @@ -61,7 +61,15 @@ def comb1_generate_products(a, b, b1): } -def comb2_reduce_products(products): +def _wallace_dot8(domain, products, *, prefix: str): + return domain.call( + wallace_dot8_tree, + inputs={f"in{idx}": product for idx, product in enumerate(products)}, + prefix=prefix, + )["sum"] + + +def comb2_reduce_products(domain, products): """ DS §5.5: - dot8 reduction for 2a/2b/2d @@ -75,13 +83,15 @@ def comb2_reduce_products(products): p2c0 = products["p2c0"] p2c1 = products["p2c1"] - s2a = dot8_reduce(p2a) - s2b0 = dot8_reduce(p2b0) - s2b1 = dot8_reduce(p2b1) - s2d0 = dot8_reduce(p2d0) - s2d1 = dot8_reduce(p2d1) - s2c0_lo, s2c0_hi = dot16_split8_reduce(p2c0) - s2c1_lo, s2c1_hi = dot16_split8_reduce(p2c1) + s2a = _wallace_dot8(domain, p2a, prefix="pe_int_s2a_wallace") + s2b0 = _wallace_dot8(domain, p2b0, prefix="pe_int_s2b0_wallace") + s2b1 = _wallace_dot8(domain, p2b1, prefix="pe_int_s2b1_wallace") + s2d0 = _wallace_dot8(domain, p2d0, prefix="pe_int_s2d0_wallace") + s2d1 = _wallace_dot8(domain, p2d1, prefix="pe_int_s2d1_wallace") + s2c0_lo = _wallace_dot8(domain, p2c0[0:8], prefix="pe_int_s2c0_lo_wallace") + s2c0_hi = _wallace_dot8(domain, p2c0[8:16], prefix="pe_int_s2c0_hi_wallace") + s2c1_lo = _wallace_dot8(domain, p2c1[0:8], prefix="pe_int_s2c1_lo_wallace") + s2c1_hi = _wallace_dot8(domain, p2c1[8:16], prefix="pe_int_s2c1_hi_wallace") return { "s2a": s2a, "s2b0": s2b0, @@ -95,13 +105,12 @@ def comb2_reduce_products(products): } -def comb3_mode_merge(reduced, mode, e1_a, e1_b0, e1_b1): +def comb3_mode_merge(reduced, e1_a, e1_b0, e1_b1, *, is_2a, is_2b, is_2c, is_2d): """ DS §5.7: - 2c post-scale x1/x2/x4 - one-hot mode merge for out0_raw/out1_raw """ - is_2a, is_2b, is_2c, is_2d = _mode_one_hot(mode) s2c0 = sum_shift_pair(reduced["s2c0_lo"], reduced["s2c0_hi"], e1_a, e1_b0) s2c1 = sum_shift_pair(reduced["s2c1_lo"], reduced["s2c1_hi"], e1_a, e1_b1) diff --git a/designs/PE_INT/python/pe_int/top.py b/designs/PE_INT/python/pe_int/top.py index 2347f6d..d54f261 100644 --- a/designs/PE_INT/python/pe_int/top.py +++ b/designs/PE_INT/python/pe_int/top.py @@ -12,26 +12,41 @@ mux = None # type: ignore[assignment] wire_of = None # type: ignore[assignment] -from .constants import DEFAULT_PIPELINE_L, MODE_2A +from .constants import DEFAULT_PIPELINE_L, OUT0_W, OUT1_W, SPEC_LATENCY_L from .mac_modes import comb1_generate_products, comb2_reduce_products, comb3_mode_merge -from .pipeline import out1_hold_policy def _require_pycircuit() -> None: if cas is None or compile_cycle_aware is None or wire_of is None or mux is None: raise RuntimeError( - "pyCircuit 未安裝。請先依 README 設定 PYTHONPATH，或安裝 LinxISA/pyCircuit frontend。" + "pyCircuit is not installed. Please set PYTHONPATH according to README, " + "or install LinxISA/pyCircuit frontend." ) -def build(m: CycleAwareCircuit, domain: CycleAwareDomain, latency: int = DEFAULT_PIPELINE_L) -> None: +def _reg_sig(domain: CycleAwareDomain, value, name: str): + return cas(domain, domain.cycle(value, name=name), cycle=0) + + +def _reg_vector(domain: CycleAwareDomain, values, *, prefix: str): + return [_reg_sig(domain, val, f"{prefix}_{idx}") for idx, val in enumerate(values)] + + +def build( + m: CycleAwareCircuit, + domain: CycleAwareDomain, + latency: int = DEFAULT_PIPELINE_L, + eager: bool = True, + hierarchical: bool = True, +) -> None: """ Explicit DS pipeline: - input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3 -> output + input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3/output """ _require_pycircuit() - if int(latency) != DEFAULT_PIPELINE_L: - raise ValueError(f"This top-level implementation requires fixed latency={DEFAULT_PIPELINE_L}.") + _ = (eager, hierarchical) + if int(latency) != SPEC_LATENCY_L: + raise ValueError(f"This top-level implementation requires fixed latency={SPEC_LATENCY_L}.") _ = m.input("rst_n", width=1) in_vld = cas(domain, m.input("vld", width=1), cycle=0) @@ -48,105 +63,124 @@ def build(m: CycleAwareCircuit, domain: CycleAwareDomain, latency: int = DEFAULT c0_is_2b = in_mode == 1 c0_is_2c = in_mode == 2 c0_is_2d = in_mode == 3 - c0_out1_en = in_mode != MODE_2A # reg0: input capture boundary (cycle-aware sampled transaction). domain.next() - s0_vld = cas(domain, domain.cycle(in_vld, name="pe_int_s0_vld"), cycle=0) - s0_mode = cas(domain, domain.cycle(in_mode, name="pe_int_s0_mode"), cycle=0) - s0_is_2a = cas(domain, domain.cycle(c0_is_2a, name="pe_int_s0_is_2a"), cycle=0) - s0_is_2b = cas(domain, domain.cycle(c0_is_2b, name="pe_int_s0_is_2b"), cycle=0) - s0_is_2c = cas(domain, domain.cycle(c0_is_2c, name="pe_int_s0_is_2c"), cycle=0) - s0_is_2d = cas(domain, domain.cycle(c0_is_2d, name="pe_int_s0_is_2d"), cycle=0) - s0_out1_en = cas(domain, domain.cycle(c0_out1_en, name="pe_int_s0_out1_en"), cycle=0) - s0_a = cas(domain, domain.cycle(in_a, name="pe_int_s0_a"), cycle=0) - s0_b = cas(domain, domain.cycle(in_b, name="pe_int_s0_b"), cycle=0) - s0_b1 = cas(domain, domain.cycle(in_b1, name="pe_int_s0_b1"), cycle=0) - s0_e1_a = cas(domain, domain.cycle(in_e1_a, name="pe_int_s0_e1_a"), cycle=0) - s0_e1_b0 = cas(domain, domain.cycle(in_e1_b0, name="pe_int_s0_e1_b0"), cycle=0) - s0_e1_b1 = cas(domain, domain.cycle(in_e1_b1, name="pe_int_s0_e1_b1"), cycle=0) - - # comb1: lane decode + lane multipliers. + s0_vld = _reg_sig(domain, in_vld, "pe_int_s0_vld") + s0_is_2a = _reg_sig(domain, c0_is_2a, "pe_int_s0_is_2a") + s0_is_2b = _reg_sig(domain, c0_is_2b, "pe_int_s0_is_2b") + s0_is_2c = _reg_sig(domain, c0_is_2c, "pe_int_s0_is_2c") + s0_is_2d = _reg_sig(domain, c0_is_2d, "pe_int_s0_is_2d") + s0_a = _reg_sig(domain, in_a, "pe_int_s0_a") + s0_b = _reg_sig(domain, in_b, "pe_int_s0_b") + s0_b1 = _reg_sig(domain, in_b1, "pe_int_s0_b1") + s0_e1_a = _reg_sig(domain, in_e1_a, "pe_int_s0_e1_a") + s0_e1_b0 = _reg_sig(domain, in_e1_b0, "pe_int_s0_e1_b0") + s0_e1_b1 = _reg_sig(domain, in_e1_b1, "pe_int_s0_e1_b1") + + # comb1: decode + per-lane product generation. c1_products = comb1_generate_products(s0_a, s0_b, s0_b1) - # reg1: product vectors + aligned controls. + # reg1: post-product boundary. domain.next() - s1_vld = cas(domain, domain.cycle(s0_vld, name="pe_int_s1_vld"), cycle=0) - s1_mode = cas(domain, domain.cycle(s0_mode, name="pe_int_s1_mode"), cycle=0) - s1_is_2a = cas(domain, domain.cycle(s0_is_2a, name="pe_int_s1_is_2a"), cycle=0) - s1_is_2b = cas(domain, domain.cycle(s0_is_2b, name="pe_int_s1_is_2b"), cycle=0) - s1_is_2c = cas(domain, domain.cycle(s0_is_2c, name="pe_int_s1_is_2c"), cycle=0) - s1_is_2d = cas(domain, domain.cycle(s0_is_2d, name="pe_int_s1_is_2d"), cycle=0) - s1_out1_en = cas(domain, domain.cycle(s0_out1_en, name="pe_int_s1_out1_en"), cycle=0) - s1_e1_a = cas(domain, domain.cycle(s0_e1_a, name="pe_int_s1_e1_a"), cycle=0) - s1_e1_b0 = cas(domain, domain.cycle(s0_e1_b0, name="pe_int_s1_e1_b0"), cycle=0) - s1_e1_b1 = cas(domain, domain.cycle(s0_e1_b1, name="pe_int_s1_e1_b1"), cycle=0) + s1_vld = _reg_sig(domain, s0_vld, "pe_int_s1_vld") + s1_is_2a = _reg_sig(domain, s0_is_2a, "pe_int_s1_is_2a") + s1_is_2b = _reg_sig(domain, s0_is_2b, "pe_int_s1_is_2b") + s1_is_2c = _reg_sig(domain, s0_is_2c, "pe_int_s1_is_2c") + s1_is_2d = _reg_sig(domain, s0_is_2d, "pe_int_s1_is_2d") + s1_e1_a = _reg_sig(domain, s0_e1_a, "pe_int_s1_e1_a") + s1_e1_b0 = _reg_sig(domain, s0_e1_b0, "pe_int_s1_e1_b0") + s1_e1_b1 = _reg_sig(domain, s0_e1_b1, "pe_int_s1_e1_b1") s1_products = { - "p2a": [cas(domain, domain.cycle(c1_products["p2a"][i], name=f"pe_int_s1_p2a_{i}"), cycle=0) for i in range(8)], - "p2b0": [cas(domain, domain.cycle(c1_products["p2b0"][i], name=f"pe_int_s1_p2b0_{i}"), cycle=0) for i in range(8)], - "p2b1": [cas(domain, domain.cycle(c1_products["p2b1"][i], name=f"pe_int_s1_p2b1_{i}"), cycle=0) for i in range(8)], - "p2d0": [cas(domain, domain.cycle(c1_products["p2d0"][i], name=f"pe_int_s1_p2d0_{i}"), cycle=0) for i in range(8)], - "p2d1": [cas(domain, domain.cycle(c1_products["p2d1"][i], name=f"pe_int_s1_p2d1_{i}"), cycle=0) for i in range(8)], - "p2c0": [cas(domain, domain.cycle(c1_products["p2c0"][i], name=f"pe_int_s1_p2c0_{i}"), cycle=0) for i in range(16)], - "p2c1": [cas(domain, domain.cycle(c1_products["p2c1"][i], name=f"pe_int_s1_p2c1_{i}"), cycle=0) for i in range(16)], + "p2a": _reg_vector(domain, c1_products["p2a"], prefix="pe_int_s1_p2a"), + "p2b0": _reg_vector(domain, c1_products["p2b0"], prefix="pe_int_s1_p2b0"), + "p2b1": _reg_vector(domain, c1_products["p2b1"], prefix="pe_int_s1_p2b1"), + "p2d0": _reg_vector(domain, c1_products["p2d0"], prefix="pe_int_s1_p2d0"), + "p2d1": _reg_vector(domain, c1_products["p2d1"], prefix="pe_int_s1_p2d1"), + "p2c0": _reg_vector(domain, c1_products["p2c0"], prefix="pe_int_s1_p2c0"), + "p2c1": _reg_vector(domain, c1_products["p2c1"], prefix="pe_int_s1_p2c1"), } - # comb2: dot reductions. - c2_reduced = comb2_reduce_products(s1_products) + # comb2: dot-product reductions only. + c2_reduced = comb2_reduce_products(domain, s1_products) - # reg2: reduced sums + aligned controls. + # reg2: post-reduction boundary. domain.next() - s2_vld = cas(domain, domain.cycle(s1_vld, name="pe_int_s2_vld"), cycle=0) - s2_mode = cas(domain, domain.cycle(s1_mode, name="pe_int_s2_mode"), cycle=0) - s2_is_2a = cas(domain, domain.cycle(s1_is_2a, name="pe_int_s2_is_2a"), cycle=0) - s2_is_2b = cas(domain, domain.cycle(s1_is_2b, name="pe_int_s2_is_2b"), cycle=0) - s2_is_2c = cas(domain, domain.cycle(s1_is_2c, name="pe_int_s2_is_2c"), cycle=0) - s2_is_2d = cas(domain, domain.cycle(s1_is_2d, name="pe_int_s2_is_2d"), cycle=0) - s2_out1_en = cas(domain, domain.cycle(s1_out1_en, name="pe_int_s2_out1_en"), cycle=0) - s2_e1_a = cas(domain, domain.cycle(s1_e1_a, name="pe_int_s2_e1_a"), cycle=0) - s2_e1_b0 = cas(domain, domain.cycle(s1_e1_b0, name="pe_int_s2_e1_b0"), cycle=0) - s2_e1_b1 = cas(domain, domain.cycle(s1_e1_b1, name="pe_int_s2_e1_b1"), cycle=0) - s2_reduced = { - "s2a": cas(domain, domain.cycle(c2_reduced["s2a"], name="pe_int_s2_s2a"), cycle=0), - "s2b0": cas(domain, domain.cycle(c2_reduced["s2b0"], name="pe_int_s2_s2b0"), cycle=0), - "s2b1": cas(domain, domain.cycle(c2_reduced["s2b1"], name="pe_int_s2_s2b1"), cycle=0), - "s2d0": cas(domain, domain.cycle(c2_reduced["s2d0"], name="pe_int_s2_s2d0"), cycle=0), - "s2d1": cas(domain, domain.cycle(c2_reduced["s2d1"], name="pe_int_s2_s2d1"), cycle=0), - "s2c0_lo": cas(domain, domain.cycle(c2_reduced["s2c0_lo"], name="pe_int_s2_s2c0_lo"), cycle=0), - "s2c0_hi": cas(domain, domain.cycle(c2_reduced["s2c0_hi"], name="pe_int_s2_s2c0_hi"), cycle=0), - "s2c1_lo": cas(domain, domain.cycle(c2_reduced["s2c1_lo"], name="pe_int_s2_s2c1_lo"), cycle=0), - "s2c1_hi": cas(domain, domain.cycle(c2_reduced["s2c1_hi"], name="pe_int_s2_s2c1_hi"), cycle=0), + s2_vld = _reg_sig(domain, s1_vld, "pe_int_s2_vld") + s2_is_2a = _reg_sig(domain, s1_is_2a, "pe_int_s2_is_2a") + s2_is_2b = _reg_sig(domain, s1_is_2b, "pe_int_s2_is_2b") + s2_is_2c = _reg_sig(domain, s1_is_2c, "pe_int_s2_is_2c") + s2_is_2d = _reg_sig(domain, s1_is_2d, "pe_int_s2_is_2d") + s2_e1_a = _reg_sig(domain, s1_e1_a, "pe_int_s2_e1_a") + s2_e1_b0 = _reg_sig(domain, s1_e1_b0, "pe_int_s2_e1_b0") + s2_e1_b1 = _reg_sig(domain, s1_e1_b1, "pe_int_s2_e1_b1") + s2_s2a = _reg_sig(domain, c2_reduced["s2a"], "pe_int_s2_s2a") + s2_s2b0 = _reg_sig(domain, c2_reduced["s2b0"], "pe_int_s2_s2b0") + s2_s2b1 = _reg_sig(domain, c2_reduced["s2b1"], "pe_int_s2_s2b1") + s2_s2d0 = _reg_sig(domain, c2_reduced["s2d0"], "pe_int_s2_s2d0") + s2_s2d1 = _reg_sig(domain, c2_reduced["s2d1"], "pe_int_s2_s2d1") + s2_s2c0_lo = _reg_sig(domain, c2_reduced["s2c0_lo"], "pe_int_s2_s2c0_lo") + s2_s2c0_hi = _reg_sig(domain, c2_reduced["s2c0_hi"], "pe_int_s2_s2c0_hi") + s2_s2c1_lo = _reg_sig(domain, c2_reduced["s2c1_lo"], "pe_int_s2_s2c1_lo") + s2_s2c1_hi = _reg_sig(domain, c2_reduced["s2c1_hi"], "pe_int_s2_s2c1_hi") + + # comb3: pure combinational post-scale + mode merge with reg2 one-hot controls. + c3_reduced = { + "s2a": s2_s2a, + "s2b0": s2_s2b0, + "s2b1": s2_s2b1, + "s2d0": s2_s2d0, + "s2d1": s2_s2d1, + "s2c0_lo": s2_s2c0_lo, + "s2c0_hi": s2_s2c0_hi, + "s2c1_lo": s2_s2c1_lo, + "s2c1_hi": s2_s2c1_hi, } - - # comb3: post-scale, mode-merge and out1 hold-next preparation. - c3_out0_raw, c3_out1_raw = comb3_mode_merge(s2_reduced, s2_mode, s2_e1_a, s2_e1_b0, s2_e1_b1) - c3_vld_out = s2_vld - c3_out1_update = s2_vld & s2_out1_en - - # reg3: output register boundary and explicit out1 hold register update. - out1 = out1_hold_policy( - domain, - vld_aligned=c3_vld_out, - out1_en_aligned=s2_out1_en, - out1_aligned=wire_of(c3_out1_raw)[0:16], - prefix="pe_int", + c3_out0_raw, c3_out1_raw = comb3_mode_merge( + c3_reduced, + s2_e1_a, + s2_e1_b0, + s2_e1_b1, + is_2a=s2_is_2a, + is_2b=s2_is_2b, + is_2c=s2_is_2c, + is_2d=s2_is_2d, + ) + c3_out0_raw = cas(domain, wire_of(c3_out0_raw), cycle=0) + c3_out1_raw = cas(domain, wire_of(c3_out1_raw), cycle=0) + c3_out0 = wire_of(c3_out0_raw)[0:OUT0_W] + c3_out1 = wire_of(c3_out1_raw)[0:OUT1_W] + + # reg3/output commit: vld_out/out0/out1 from the same commit boundary. + out1 = domain.state(width=OUT1_W, reset_value=0, name="pe_int_out1") + out1_commit = mux( + wire_of(s2_vld), + mux(wire_of(s2_is_2a), wire_of(out1), c3_out1), + wire_of(out1), ) + out1.set(out1_commit) + domain.next() - out_vld = cas(domain, domain.cycle(c3_vld_out, name="pe_int_s3_vld_out"), cycle=0) - out0 = cas(domain, domain.cycle(wire_of(c3_out0_raw)[0:19], name="pe_int_s3_out0"), cycle=0) - out1 = cas(domain, domain.cycle(out1, name="pe_int_s3_out1"), cycle=0) + out_vld = _reg_sig(domain, s2_vld, "pe_int_out_vld") + out0 = _reg_sig(domain, c3_out0, "pe_int_out0") m.output("vld_out", wire_of(out_vld)) m.output("out0", wire_of(out0)) m.output("out1", wire_of(out1)) -build.__pycircuit_name__ = "pe_int_fix7" +build.__pycircuit_name__ = "PE_INT" def emit_mlir(latency: int = DEFAULT_PIPELINE_L) -> str: _require_pycircuit() - return compile_cycle_aware(build, name="pe_int", eager=True, latency=int(latency)).emit_mlir() + return compile_cycle_aware( + build, + name="pe_int", + eager=True, + hierarchical=True, + latency=int(latency), + ).emit_mlir() if __name__ == "__main__": diff --git a/designs/PE_INT/python/pe_int_pycircuit.py b/designs/PE_INT/python/pe_int_pycircuit.py index d9d16e6..6a8d845 100644 --- a/designs/PE_INT/python/pe_int_pycircuit.py +++ b/designs/PE_INT/python/pe_int_pycircuit.py @@ -1,24 +1,25 @@ -from __future__ import annotations - -from pathlib import Path - -from pe_int import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, build, emit_mlir - -build.__pycircuit_name__ = "pe_int_fix7" - -__all__ = [ - "MODE_2A", - "MODE_2B", - "MODE_2C", - "MODE_2D", - "DEFAULT_PIPELINE_L", - "build", - "emit_mlir", -] - - -if __name__ == "__main__": - out = Path(__file__).resolve().parents[1] / "build" / "pe_int.mlir" - out.parent.mkdir(parents=True, exist_ok=True) - out.write_text(emit_mlir(), encoding="utf-8") - print(f"Wrote {out}") +from __future__ import annotations + +from pathlib import Path + +from pe_int import DEFAULT_PIPELINE_L, MODE_2A, MODE_2B, MODE_2C, MODE_2D, SPEC_LATENCY_L, build, emit_mlir + +build.__pycircuit_name__ = "PE_INT" + +__all__ = [ + "MODE_2A", + "MODE_2B", + "MODE_2C", + "MODE_2D", + "DEFAULT_PIPELINE_L", + "SPEC_LATENCY_L", + "build", + "emit_mlir", +] + + +if __name__ == "__main__": + out = Path(__file__).resolve().parents[1] / "build" / "pe_int.mlir" + out.parent.mkdir(parents=True, exist_ok=True) + out.write_text(emit_mlir(), encoding="utf-8") + print(f"Wrote {out}") diff --git a/designs/PE_INT/rtl/README.md b/designs/PE_INT/rtl/README.md index b2021ee..cb316a2 100644 --- a/designs/PE_INT/rtl/README.md +++ b/designs/PE_INT/rtl/README.md @@ -1,25 +1,19 @@ # Generated RTL -`rtl/build/` stores outputs generated by the `pyCircuit` / `pycc` build flow. +`rtl/` 只存放由 `pyCircuit` / `pycc` 建構流程產生的輸出。 -## Generation +## 產生方式 -Run at repo root: +在 repo 根目錄執行： ```bash -python python/build.py --target both --out-dir build/pe_int +python python/build.py --target rtl --out-dir build/pe_int ``` -Artifact paths may differ by `pycircuit.cli build` version, usually under `build/pe_int/`. +產物位置依 `pycircuit.cli build` 版本可能有差異，通常在 `build/pe_int/` 下。 -After each build, the flow must copy deliverable RTL artifacts from the build -output tree into `rtl/build/`, then refresh `filelist/pe_int.f`. +## 原則 -## Rules - -- Do not handwrite `rtl/build/*.v`. -- Keep `rtl/build/` as the delivery mirror of the latest build output artifacts. -- Refresh `filelist/pe_int.f` after each build sync. -- Deliverable top-level reset interface must match spec (`rst_n` only); do not expose extra reset IO. -- RTL content must be sourced only from `python/pe_int_pycircuit.py` and `tb/tb_pe_int_pycircuit.py`. -- Use `tb_rtl/` for RTL simulations (do not move RTL testcases back into `tb/`). +- 不手寫 `rtl/*.v`。 +- RTL 內容以 `python/pe_int_pycircuit.py` 與 `tb/tb_pe_int_pycircuit.py` 為唯一來源。 +- RTL 功能仿真請使用 `tb_rtl/`（不要把 RTL testcase 放回 `tb/`）。 diff --git a/designs/PE_INT/rtl/build/pe_int.v b/designs/PE_INT/rtl/build/pe_int.v index 08ce97b..b1e81aa 100644 --- a/designs/PE_INT/rtl/build/pe_int.v +++ b/designs/PE_INT/rtl/build/pe_int.v @@ -21,6 +21,9 @@ wire rst; assign rst = ~rst_n; +wire [31:0] _v5_bal_1; // pyc.name="_v5_bal_1" +wire [31:0] _v5_bal_1__next; // pyc.name="_v5_bal_1__next" +wire [31:0] _v5_bal_2__next; // pyc.name="_v5_bal_2__next" wire [18:0] pe_int_out0; // pyc.name="pe_int_out0" wire [18:0] pe_int_out0__next; // pyc.name="pe_int_out0__next" wire [15:0] pe_int_out1; // pyc.name="pe_int_out1" @@ -240,20 +243,12 @@ wire [31:0] pe_int_s2_s2d1; // pyc.name="pe_int_s2_s2d1" wire [31:0] pe_int_s2_s2d1__next; // pyc.name="pe_int_s2_s2d1__next" wire pe_int_s2_vld; // pyc.name="pe_int_s2_vld" wire pe_int_s2_vld__next; // pyc.name="pe_int_s2_vld__next" -wire [1:0] pyc_add_524; // op=pyc.add -wire [1:0] pyc_add_529; // op=pyc.add -wire [31:0] pyc_add_530; // op=pyc.add -wire [31:0] pyc_add_531; // op=pyc.add -wire [31:0] pyc_add_536; // op=pyc.add -wire [31:0] pyc_add_537; // op=pyc.add -wire [31:0] pyc_add_542; // op=pyc.add -wire [1:0] pyc_add_545; // op=pyc.add -wire [1:0] pyc_add_548; // op=pyc.add -wire [31:0] pyc_add_549; // op=pyc.add -wire [31:0] pyc_add_550; // op=pyc.add -wire [31:0] pyc_add_555; // op=pyc.add -wire [31:0] pyc_add_556; // op=pyc.add -wire [31:0] pyc_add_561; // op=pyc.add +wire [1:0] pyc_add_526; // op=pyc.add +wire [1:0] pyc_add_531; // op=pyc.add +wire [31:0] pyc_add_544; // op=pyc.add +wire [1:0] pyc_add_547; // op=pyc.add +wire [1:0] pyc_add_550; // op=pyc.add +wire [31:0] pyc_add_563; // op=pyc.add wire [18:0] pyc_comb_15; // op=pyc.comb wire [15:0] pyc_comb_16; // op=pyc.comb wire [1:0] pyc_comb_17; // op=pyc.comb @@ -367,10 +362,15 @@ wire [2:0] pyc_comb_500; // op=pyc.comb wire pyc_comb_505; // op=pyc.comb wire pyc_comb_506; // op=pyc.comb wire pyc_comb_507; // op=pyc.comb -wire [18:0] pyc_comb_570; // op=pyc.comb -wire [15:0] pyc_comb_571; // op=pyc.comb -wire [15:0] pyc_comb_575; // op=pyc.comb -wire [15:0] pyc_comb_576; // op=pyc.comb +wire [31:0] pyc_comb_512; // op=pyc.comb +wire [31:0] pyc_comb_513; // op=pyc.comb +wire [31:0] pyc_comb_567; // op=pyc.comb +wire [31:0] pyc_comb_568; // op=pyc.comb +wire [31:0] pyc_comb_570; // op=pyc.comb +wire [18:0] pyc_comb_577; // op=pyc.comb +wire [15:0] pyc_comb_578; // op=pyc.comb +wire [15:0] pyc_comb_582; // op=pyc.comb +wire [15:0] pyc_comb_583; // op=pyc.comb wire [7:0] pyc_concat_107; // op=pyc.concat wire [7:0] pyc_concat_113; // op=pyc.concat wire [7:0] pyc_concat_132; // op=pyc.concat @@ -487,18 +487,18 @@ wire pyc_extract_502; // op=pyc.extract wire pyc_extract_503; // op=pyc.extract wire pyc_extract_504; // op=pyc.extract wire [39:0] pyc_extract_52; // op=pyc.extract -wire pyc_extract_520; // op=pyc.extract wire pyc_extract_522; // op=pyc.extract -wire pyc_extract_525; // op=pyc.extract +wire pyc_extract_524; // op=pyc.extract wire pyc_extract_527; // op=pyc.extract +wire pyc_extract_529; // op=pyc.extract wire [4:0] pyc_extract_53; // op=pyc.extract wire [4:0] pyc_extract_54; // op=pyc.extract -wire pyc_extract_543; // op=pyc.extract -wire pyc_extract_546; // op=pyc.extract +wire pyc_extract_545; // op=pyc.extract +wire pyc_extract_548; // op=pyc.extract wire [3:0] pyc_extract_55; // op=pyc.extract wire [3:0] pyc_extract_56; // op=pyc.extract -wire [18:0] pyc_extract_568; // op=pyc.extract -wire [15:0] pyc_extract_569; // op=pyc.extract +wire [18:0] pyc_extract_575; // op=pyc.extract +wire [15:0] pyc_extract_576; // op=pyc.extract wire [4:0] pyc_extract_59; // op=pyc.extract wire [4:0] pyc_extract_60; // op=pyc.extract wire [3:0] pyc_extract_61; // op=pyc.extract @@ -600,22 +600,22 @@ wire [31:0] pyc_mul_76; // op=pyc.mul wire [31:0] pyc_mul_77; // op=pyc.mul wire [31:0] pyc_mul_98; // op=pyc.mul wire [31:0] pyc_mul_99; // op=pyc.mul -wire [31:0] pyc_mux_534; // op=pyc.mux -wire [31:0] pyc_mux_535; // op=pyc.mux -wire [31:0] pyc_mux_540; // op=pyc.mux -wire [31:0] pyc_mux_541; // op=pyc.mux -wire [31:0] pyc_mux_553; // op=pyc.mux -wire [31:0] pyc_mux_554; // op=pyc.mux -wire [31:0] pyc_mux_559; // op=pyc.mux -wire [31:0] pyc_mux_560; // op=pyc.mux +wire [31:0] pyc_mux_536; // op=pyc.mux +wire [31:0] pyc_mux_537; // op=pyc.mux +wire [31:0] pyc_mux_542; // op=pyc.mux +wire [31:0] pyc_mux_543; // op=pyc.mux +wire [31:0] pyc_mux_555; // op=pyc.mux +wire [31:0] pyc_mux_556; // op=pyc.mux +wire [31:0] pyc_mux_561; // op=pyc.mux wire [31:0] pyc_mux_562; // op=pyc.mux -wire [31:0] pyc_mux_563; // op=pyc.mux wire [31:0] pyc_mux_564; // op=pyc.mux wire [31:0] pyc_mux_565; // op=pyc.mux wire [31:0] pyc_mux_566; // op=pyc.mux -wire [31:0] pyc_mux_567; // op=pyc.mux -wire [15:0] pyc_mux_573; // op=pyc.mux -wire [15:0] pyc_mux_574; // op=pyc.mux +wire [31:0] pyc_mux_572; // op=pyc.mux +wire [31:0] pyc_mux_573; // op=pyc.mux +wire [31:0] pyc_mux_574; // op=pyc.mux +wire [15:0] pyc_mux_580; // op=pyc.mux +wire [15:0] pyc_mux_581; // op=pyc.mux wire pyc_reg_34; // op=pyc.reg wire pyc_reg_36; // op=pyc.reg wire pyc_reg_38; // op=pyc.reg @@ -713,17 +713,19 @@ wire [1:0] pyc_reg_509; // op=pyc.reg wire [1:0] pyc_reg_51; // op=pyc.reg wire [1:0] pyc_reg_510; // op=pyc.reg wire [31:0] pyc_reg_511; // op=pyc.reg -wire [31:0] pyc_reg_512; // op=pyc.reg -wire [31:0] pyc_reg_513; // op=pyc.reg wire [31:0] pyc_reg_514; // op=pyc.reg wire [31:0] pyc_reg_515; // op=pyc.reg wire [31:0] pyc_reg_516; // op=pyc.reg wire [31:0] pyc_reg_517; // op=pyc.reg wire [31:0] pyc_reg_518; // op=pyc.reg wire [31:0] pyc_reg_519; // op=pyc.reg -wire [15:0] pyc_reg_572; // op=pyc.reg -wire pyc_reg_577; // op=pyc.reg -wire [18:0] pyc_reg_578; // op=pyc.reg +wire [31:0] pyc_reg_520; // op=pyc.reg +wire [31:0] pyc_reg_521; // op=pyc.reg +wire [31:0] pyc_reg_569; // op=pyc.reg +wire [31:0] pyc_reg_571; // op=pyc.reg +wire [15:0] pyc_reg_579; // op=pyc.reg +wire pyc_reg_584; // op=pyc.reg +wire [18:0] pyc_reg_585; // op=pyc.reg wire [31:0] pyc_sext_108; // op=pyc.sext wire [31:0] pyc_sext_114; // op=pyc.sext wire [31:0] pyc_sext_117; // op=pyc.sext @@ -812,16 +814,24 @@ wire [31:0] pyc_sext_92; // op=pyc.sext wire [31:0] pyc_sext_95; // op=pyc.sext wire [31:0] pyc_sext_96; // op=pyc.sext wire [31:0] pyc_sext_97; // op=pyc.sext -wire [1:0] pyc_zext_521; // op=pyc.zext +wire [31:0] pyc_shli_534; // op=pyc.shli +wire [31:0] pyc_shli_535; // op=pyc.shli +wire [31:0] pyc_shli_540; // op=pyc.shli +wire [31:0] pyc_shli_541; // op=pyc.shli +wire [31:0] pyc_shli_553; // op=pyc.shli +wire [31:0] pyc_shli_554; // op=pyc.shli +wire [31:0] pyc_shli_559; // op=pyc.shli +wire [31:0] pyc_shli_560; // op=pyc.shli wire [1:0] pyc_zext_523; // op=pyc.zext -wire [1:0] pyc_zext_526; // op=pyc.zext +wire [1:0] pyc_zext_525; // op=pyc.zext wire [1:0] pyc_zext_528; // op=pyc.zext -wire [1:0] pyc_zext_544; // op=pyc.zext -wire [1:0] pyc_zext_547; // op=pyc.zext +wire [1:0] pyc_zext_530; // op=pyc.zext +wire [1:0] pyc_zext_546; // op=pyc.zext +wire [1:0] pyc_zext_549; // op=pyc.zext // --- Combinational (netlist) -assign pe_int_out0 = pyc_reg_578; -assign pe_int_out_vld = pyc_reg_577; +assign pe_int_out0 = pyc_reg_585; +assign pe_int_out_vld = pyc_reg_584; assign pe_int_s0_a = pyc_reg_44; assign pe_int_s0_b = pyc_reg_45; assign pe_int_s0_b1 = pyc_reg_46; @@ -900,22 +910,21 @@ assign pe_int_s1_p2d1_7 = pyc_reg_452; assign pe_int_s2_e1_a = pyc_reg_508; assign pe_int_s2_e1_b0 = pyc_reg_509; assign pe_int_s2_e1_b1 = pyc_reg_510; -assign pe_int_s2_s2a = pyc_reg_511; assign pe_int_s2_s2a__next = pyc_instance_485; -assign pe_int_s2_s2b0 = pyc_reg_512; +assign pe_int_s2_s2b0 = pyc_reg_514; assign pe_int_s2_s2b0__next = pyc_instance_486; -assign pe_int_s2_s2b1 = pyc_reg_513; +assign pe_int_s2_s2b1 = pyc_reg_515; assign pe_int_s2_s2b1__next = pyc_instance_487; -assign pe_int_s2_s2c0_hi = pyc_reg_517; +assign pe_int_s2_s2c0_hi = pyc_reg_519; assign pe_int_s2_s2c0_hi__next = pyc_instance_491; -assign pe_int_s2_s2c0_lo = pyc_reg_516; +assign pe_int_s2_s2c0_lo = pyc_reg_518; assign pe_int_s2_s2c0_lo__next = pyc_instance_490; assign pe_int_s2_s2c1_hi__next = pyc_instance_493; -assign pe_int_s2_s2c1_lo = pyc_reg_518; +assign pe_int_s2_s2c1_lo = pyc_reg_520; assign pe_int_s2_s2c1_lo__next = pyc_instance_492; -assign pe_int_s2_s2d0 = pyc_reg_514; +assign pe_int_s2_s2d0 = pyc_reg_516; assign pe_int_s2_s2d0__next = pyc_instance_488; -assign pe_int_s2_s2d1 = pyc_reg_515; +assign pe_int_s2_s2d1 = pyc_reg_517; assign pe_int_s2_s2d1__next = pyc_instance_489; assign pyc_constant_1 = 19'd0; assign pyc_constant_2 = 16'd0; @@ -1440,66 +1449,75 @@ assign pe_int_s2_is_2c = pyc_extract_504; assign pyc_comb_505 = pe_int_s2_is_2a; assign pyc_comb_506 = pe_int_s2_is_2b; assign pyc_comb_507 = pe_int_s2_is_2c; -assign pe_int_s2_s2c1_hi = pyc_reg_519; -assign pyc_extract_520 = pe_int_s2_e1_a[0]; -assign pyc_zext_521 = {{1{1'b0}}, pyc_extract_520}; -assign pyc_extract_522 = pe_int_s2_e1_b0[0]; +assign pe_int_s2_s2a = pyc_reg_511; +assign _v5_bal_1__next = pe_int_s2_s2a; +assign pyc_comb_512 = pe_int_s2_s2a; +assign pyc_comb_513 = _v5_bal_1__next; +assign pe_int_s2_s2c1_hi = pyc_reg_521; +assign pyc_extract_522 = pe_int_s2_e1_a[0]; assign pyc_zext_523 = {{1{1'b0}}, pyc_extract_522}; -assign pyc_add_524 = (pyc_zext_521 + pyc_zext_523); -assign pyc_extract_525 = pe_int_s2_e1_a[1]; -assign pyc_zext_526 = {{1{1'b0}}, pyc_extract_525}; -assign pyc_extract_527 = pe_int_s2_e1_b0[1]; +assign pyc_extract_524 = pe_int_s2_e1_b0[0]; +assign pyc_zext_525 = {{1{1'b0}}, pyc_extract_524}; +assign pyc_add_526 = (pyc_zext_523 + pyc_zext_525); +assign pyc_extract_527 = pe_int_s2_e1_a[1]; assign pyc_zext_528 = {{1{1'b0}}, pyc_extract_527}; -assign pyc_add_529 = (pyc_zext_526 + pyc_zext_528); -assign pyc_add_530 = (pe_int_s2_s2c0_lo + pe_int_s2_s2c0_lo); -assign pyc_add_531 = (pyc_add_530 + pyc_add_530); -assign pyc_eq_532 = (pyc_add_524 == pyc_comb_19); -assign pyc_eq_533 = (pyc_add_524 == pyc_comb_17); -assign pyc_mux_534 = (pyc_eq_533 ? pyc_add_530 : pyc_add_531); -assign pyc_mux_535 = (pyc_eq_532 ? pe_int_s2_s2c0_lo : pyc_mux_534); -assign pyc_add_536 = (pe_int_s2_s2c0_hi + pe_int_s2_s2c0_hi); -assign pyc_add_537 = (pyc_add_536 + pyc_add_536); -assign pyc_eq_538 = (pyc_add_529 == pyc_comb_19); -assign pyc_eq_539 = (pyc_add_529 == pyc_comb_17); -assign pyc_mux_540 = (pyc_eq_539 ? pyc_add_536 : pyc_add_537); -assign pyc_mux_541 = (pyc_eq_538 ? pe_int_s2_s2c0_hi : pyc_mux_540); -assign pyc_add_542 = (pyc_mux_535 + pyc_mux_541); -assign pyc_extract_543 = pe_int_s2_e1_b1[0]; -assign pyc_zext_544 = {{1{1'b0}}, pyc_extract_543}; -assign pyc_add_545 = (pyc_zext_521 + pyc_zext_544); -assign pyc_extract_546 = pe_int_s2_e1_b1[1]; -assign pyc_zext_547 = {{1{1'b0}}, pyc_extract_546}; -assign pyc_add_548 = (pyc_zext_526 + pyc_zext_547); -assign pyc_add_549 = (pe_int_s2_s2c1_lo + pe_int_s2_s2c1_lo); -assign pyc_add_550 = (pyc_add_549 + pyc_add_549); -assign pyc_eq_551 = (pyc_add_545 == pyc_comb_19); -assign pyc_eq_552 = (pyc_add_545 == pyc_comb_17); -assign pyc_mux_553 = (pyc_eq_552 ? pyc_add_549 : pyc_add_550); -assign pyc_mux_554 = (pyc_eq_551 ? pe_int_s2_s2c1_lo : pyc_mux_553); -assign pyc_add_555 = (pe_int_s2_s2c1_hi + pe_int_s2_s2c1_hi); -assign pyc_add_556 = (pyc_add_555 + pyc_add_555); -assign pyc_eq_557 = (pyc_add_548 == pyc_comb_19); -assign pyc_eq_558 = (pyc_add_548 == pyc_comb_17); -assign pyc_mux_559 = (pyc_eq_558 ? pyc_add_555 : pyc_add_556); -assign pyc_mux_560 = (pyc_eq_557 ? pe_int_s2_s2c1_hi : pyc_mux_559); -assign pyc_add_561 = (pyc_mux_554 + pyc_mux_560); -assign pyc_mux_562 = (pyc_comb_507 ? pyc_add_542 : pe_int_s2_s2d0); -assign pyc_mux_563 = (pyc_comb_506 ? pe_int_s2_s2b0 : pyc_mux_562); -assign pyc_mux_564 = (pyc_comb_505 ? pe_int_s2_s2a : pyc_mux_563); -assign pyc_mux_565 = (pyc_comb_507 ? pyc_add_561 : pe_int_s2_s2d1); -assign pyc_mux_566 = (pyc_comb_506 ? pe_int_s2_s2b1 : pyc_mux_565); -assign pyc_mux_567 = (pyc_comb_505 ? pe_int_s2_s2b1 : pyc_mux_566); -assign pyc_extract_568 = pyc_mux_564[18:0]; -assign pe_int_out0__next = pyc_extract_568; -assign pyc_extract_569 = pyc_mux_567[15:0]; -assign pyc_comb_570 = pe_int_out0__next; -assign pyc_comb_571 = pyc_extract_569; -assign pe_int_out1 = pyc_reg_572; -assign pyc_mux_573 = (pyc_comb_505 ? pe_int_out1 : pyc_comb_571); -assign pyc_mux_574 = (pyc_comb_497 ? pyc_mux_573 : pe_int_out1); -assign pyc_comb_575 = pe_int_out1; -assign pyc_comb_576 = pyc_mux_574; -assign pe_int_out1__next = pyc_comb_576; +assign pyc_extract_529 = pe_int_s2_e1_b0[1]; +assign pyc_zext_530 = {{1{1'b0}}, pyc_extract_529}; +assign pyc_add_531 = (pyc_zext_528 + pyc_zext_530); +assign pyc_eq_532 = (pyc_add_526 == pyc_comb_19); +assign pyc_eq_533 = (pyc_add_526 == pyc_comb_17); +assign pyc_shli_534 = (pe_int_s2_s2c0_lo << 1); +assign pyc_shli_535 = (pe_int_s2_s2c0_lo << 2); +assign pyc_mux_536 = (pyc_eq_533 ? pyc_shli_534 : pyc_shli_535); +assign pyc_mux_537 = (pyc_eq_532 ? pe_int_s2_s2c0_lo : pyc_mux_536); +assign pyc_eq_538 = (pyc_add_531 == pyc_comb_19); +assign pyc_eq_539 = (pyc_add_531 == pyc_comb_17); +assign pyc_shli_540 = (pe_int_s2_s2c0_hi << 1); +assign pyc_shli_541 = (pe_int_s2_s2c0_hi << 2); +assign pyc_mux_542 = (pyc_eq_539 ? pyc_shli_540 : pyc_shli_541); +assign pyc_mux_543 = (pyc_eq_538 ? pe_int_s2_s2c0_hi : pyc_mux_542); +assign pyc_add_544 = (pyc_mux_537 + pyc_mux_543); +assign pyc_extract_545 = pe_int_s2_e1_b1[0]; +assign pyc_zext_546 = {{1{1'b0}}, pyc_extract_545}; +assign pyc_add_547 = (pyc_zext_523 + pyc_zext_546); +assign pyc_extract_548 = pe_int_s2_e1_b1[1]; +assign pyc_zext_549 = {{1{1'b0}}, pyc_extract_548}; +assign pyc_add_550 = (pyc_zext_528 + pyc_zext_549); +assign pyc_eq_551 = (pyc_add_547 == pyc_comb_19); +assign pyc_eq_552 = (pyc_add_547 == pyc_comb_17); +assign pyc_shli_553 = (pe_int_s2_s2c1_lo << 1); +assign pyc_shli_554 = (pe_int_s2_s2c1_lo << 2); +assign pyc_mux_555 = (pyc_eq_552 ? pyc_shli_553 : pyc_shli_554); +assign pyc_mux_556 = (pyc_eq_551 ? pe_int_s2_s2c1_lo : pyc_mux_555); +assign pyc_eq_557 = (pyc_add_550 == pyc_comb_19); +assign pyc_eq_558 = (pyc_add_550 == pyc_comb_17); +assign pyc_shli_559 = (pe_int_s2_s2c1_hi << 1); +assign pyc_shli_560 = (pe_int_s2_s2c1_hi << 2); +assign pyc_mux_561 = (pyc_eq_558 ? pyc_shli_559 : pyc_shli_560); +assign pyc_mux_562 = (pyc_eq_557 ? pe_int_s2_s2c1_hi : pyc_mux_561); +assign pyc_add_563 = (pyc_mux_556 + pyc_mux_562); +assign pyc_mux_564 = (pyc_comb_507 ? pyc_add_544 : pe_int_s2_s2d0); +assign pyc_mux_565 = (pyc_comb_506 ? pe_int_s2_s2b0 : pyc_mux_564); +assign pyc_mux_566 = (pyc_comb_505 ? pyc_comb_512 : pyc_mux_565); +assign pyc_comb_567 = pyc_add_563; +assign pyc_comb_568 = pyc_mux_566; +assign _v5_bal_1 = pyc_reg_569; +assign _v5_bal_2__next = _v5_bal_1; +assign pyc_comb_570 = _v5_bal_2__next; +assign pyc_mux_572 = (pyc_comb_507 ? pyc_comb_567 : pe_int_s2_s2d1); +assign pyc_mux_573 = (pyc_comb_506 ? pe_int_s2_s2b1 : pyc_mux_572); +assign pyc_mux_574 = (pyc_comb_505 ? pyc_comb_18 : pyc_mux_573); +assign pyc_extract_575 = pyc_comb_568[18:0]; +assign pe_int_out0__next = pyc_extract_575; +assign pyc_extract_576 = pyc_mux_574[15:0]; +assign pyc_comb_577 = pe_int_out0__next; +assign pyc_comb_578 = pyc_extract_576; +assign pe_int_out1 = pyc_reg_579; +assign pyc_mux_580 = (pyc_comb_505 ? pe_int_out1 : pyc_comb_578); +assign pyc_mux_581 = (pyc_comb_497 ? pyc_mux_580 : pe_int_out1); +assign pyc_comb_582 = pe_int_out1; +assign pyc_comb_583 = pyc_mux_581; +assign pe_int_out1__next = pyc_comb_583; // --- Submodules PE_INT_WALLACE_DOT8_TREE pe_int_s2a_wallace ( @@ -2397,98 +2415,114 @@ PYC_REG #(.WIDTH(32)) pyc_reg_511_inst ( .init(pyc_comb_18), .q(pyc_reg_511) ); -PYC_REG #(.WIDTH(32)) pyc_reg_512_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_514_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pe_int_s2_s2b0__next), .init(pyc_comb_18), - .q(pyc_reg_512) + .q(pyc_reg_514) ); -PYC_REG #(.WIDTH(32)) pyc_reg_513_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_515_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pe_int_s2_s2b1__next), .init(pyc_comb_18), - .q(pyc_reg_513) + .q(pyc_reg_515) ); -PYC_REG #(.WIDTH(32)) pyc_reg_514_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_516_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pe_int_s2_s2d0__next), .init(pyc_comb_18), - .q(pyc_reg_514) + .q(pyc_reg_516) ); -PYC_REG #(.WIDTH(32)) pyc_reg_515_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_517_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pe_int_s2_s2d1__next), .init(pyc_comb_18), - .q(pyc_reg_515) + .q(pyc_reg_517) ); -PYC_REG #(.WIDTH(32)) pyc_reg_516_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_518_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pe_int_s2_s2c0_lo__next), .init(pyc_comb_18), - .q(pyc_reg_516) + .q(pyc_reg_518) ); -PYC_REG #(.WIDTH(32)) pyc_reg_517_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_519_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pe_int_s2_s2c0_hi__next), .init(pyc_comb_18), - .q(pyc_reg_517) + .q(pyc_reg_519) ); -PYC_REG #(.WIDTH(32)) pyc_reg_518_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_520_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pe_int_s2_s2c1_lo__next), .init(pyc_comb_18), - .q(pyc_reg_518) + .q(pyc_reg_520) ); -PYC_REG #(.WIDTH(32)) pyc_reg_519_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_521_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pe_int_s2_s2c1_hi__next), .init(pyc_comb_18), - .q(pyc_reg_519) + .q(pyc_reg_521) ); -PYC_REG #(.WIDTH(16)) pyc_reg_572_inst ( +PYC_REG #(.WIDTH(32)) pyc_reg_569_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_513), + .init(pyc_comb_18), + .q(pyc_reg_569) +); +PYC_REG #(.WIDTH(32)) pyc_reg_571_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_21), + .d(pyc_comb_570), + .init(pyc_comb_18), + .q(pyc_reg_571) +); +PYC_REG #(.WIDTH(16)) pyc_reg_579_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pe_int_out1__next), .init(pyc_comb_16), - .q(pyc_reg_572) + .q(pyc_reg_579) ); -PYC_REG #(.WIDTH(1)) pyc_reg_577_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_584_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), .d(pyc_comb_498), .init(pyc_comb_22), - .q(pyc_reg_577) + .q(pyc_reg_584) ); -PYC_REG #(.WIDTH(19)) pyc_reg_578_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_585_inst ( .clk(clk), .rst(rst), .en(pyc_comb_21), - .d(pyc_comb_570), + .d(pyc_comb_577), .init(pyc_comb_15), - .q(pyc_reg_578) + .q(pyc_reg_585) ); assign vld_out = pe_int_out_vld; assign out0 = pe_int_out0; -assign out1 = pyc_comb_575; +assign out1 = pyc_comb_582; endmodule diff --git a/designs/PE_INT/sim/README.md b/designs/PE_INT/sim/README.md index 947f8dc..3f1ec87 100644 --- a/designs/PE_INT/sim/README.md +++ b/designs/PE_INT/sim/README.md @@ -1,49 +1,49 @@ -# sim (One-Command Simulation) +# sim（一鍵仿真入口） -This directory provides an interactive one-command script: +本目錄提供互動式一鍵腳本： - `run_sim.sh` -## Features +## 功能 -Before execution, the script prompts for options (5-second timeout per prompt, then default is used): +執行前會詢問（每題等待 5 秒，逾時套用預設值）： -1. testcase vector seed (default: current timestamp) -2. simulator: `iverilog` / `verilator` (default: `iverilog`) -3. generate waveform or not (default: `No`) -4. waveform format: `vcd` / `fst` (default: `vcd`) +1. testcase 向量 seed（預設：當下時間戳） +2. 使用哪個 simulator：`iverilog` / `verilator`（預設 `iverilog`） +3. 是否產生波形（預設 `No`） +4. 波形格式：`vcd` / `fst`（預設 `vcd`） -The script first resolves and runs the model vector generator from `model/model.f`: +腳本會先透過 `model/model.f` 解析並執行： ```bash python3 --seed ``` -Then it runs all testcases in `tb_rtl/case` via filelists (`filelist/pe_int.f` + `tb_rtl/tb.f`). +再以 filelist（`filelist/pe_int.f` + `tb_rtl/tb.f`）跑 `tb_rtl/case` 下全部 testcase。 -## Reproducibility +## 可重現性 -- The same seed always generates identical `tc_mode_switch_random` vectors and expected values. -- The same seed also generates identical sanity vectors (`tc_mode2a/2b/2c/2d_sanity`); different seeds produce different vectors. -- Both `iverilog` and `verilator` use the same seed generation flow, so seed behavior is consistent across simulators. -- Each testcase has an independent log, and the seed is recorded at the beginning for replay. -- Log path: +- 同一個 seed 會生成完全一致的 `tc_mode_switch_random` 向量與 expected。 +- 同一個 seed 也會生成完全一致的 sanity vectors（`tc_mode2a/2b/2c/2d_sanity`）；不同 seed 會改變其向量。 +- `iverilog` 與 `verilator` 都使用同一份 seed 生成流程，因此兩者都保證上述 seed 行為一致。 +- 每個 testcase 都有獨立 log，且開頭會記錄該次 seed，便於下次還原。 +- log 位置： - `sim/logs//_run/seed__.log` -## Run +## 執行 ```bash bash sim/run_sim.sh ``` -## Waveform Output +## 波形輸出 -- When waveform output is enabled, files are written to: +- 啟用波形後，輸出位置為： - `sim/waves///wave.` -## Simulator Differences (Handled by Script) +## 參數差異（腳本已內建處理） -- `iverilog`: runs through `iverilog + vvp`; waveform via `$dumpfile/$dumpvars` (commonly VCD). -- `verilator`: automatically adds: +- `iverilog`：以 `iverilog + vvp` 路徑執行；波形以 `$dumpfile/$dumpvars` 生成（實務預設 VCD）。 +- `verilator`：依格式自動加： - `--trace`（VCD） - `--trace-fst`（FST） diff --git a/designs/PE_INT/sim/run_all_wsl.sh b/designs/PE_INT/sim/run_all_wsl.sh index d2302cd..0244ecd 100644 --- a/designs/PE_INT/sim/run_all_wsl.sh +++ b/designs/PE_INT/sim/run_all_wsl.sh @@ -35,64 +35,19 @@ CASES=( "tc_mode2b_sanity" "tc_mode2c_sanity" "tc_mode2d_sanity" - "tc_mode2a_sanity_rand_timing" - "tc_mode2b_sanity_rand_timing" - "tc_mode2c_sanity_rand_timing" - "tc_mode2d_sanity_rand_timing" "tc_mode_switch_random" ) -LOG_DIR="build/logs" -mkdir -p "$LOG_DIR" - -run_parallel_cases() { - local tool="$1" - local failures=0 - local -a pids=() - local -a names=() - - for c in "${CASES[@]}"; do - local log="$LOG_DIR/${tool}_${c}.log" - echo "[INFO] [$tool] launch $c (log: $log)" - if [[ "$tool" == "iverilog" ]]; then - ( - set -euo pipefail - iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" - vvp "build/${c}.iv.out" - ) >"$log" 2>&1 & - else - ( - set -euo pipefail - verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" - "./obj_dir/${c}.vlt.out" - ) >"$log" 2>&1 & - fi - pids+=("$!") - names+=("$c") - done - - for idx in "${!pids[@]}"; do - local pid="${pids[$idx]}" - local name="${names[$idx]}" - local log="$LOG_DIR/${tool}_${name}.log" - if wait "$pid"; then - echo "[PASS] [$tool] $name" - else - failures=$((failures + 1)) - echo "[FAIL] [$tool] $name (see $log)" - fi - done - - if (( failures > 0 )); then - echo "[ERR] [$tool] failed cases: $failures" - exit 1 - fi -} - -echo "[INFO] Running RTL cases with iverilog (parallel)..." -run_parallel_cases "iverilog" - -echo "[INFO] Running RTL cases with verilator (parallel)..." -run_parallel_cases "verilator" +echo "[INFO] Running RTL cases with iverilog..." +for c in "${CASES[@]}"; do + iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" + vvp "build/${c}.iv.out" +done + +echo "[INFO] Running RTL cases with verilator..." +for c in "${CASES[@]}"; do + verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + "./obj_dir/${c}.vlt.out" +done echo "[PASS] all tb_rtl cases passed on iverilog + verilator." diff --git a/designs/PE_INT/sim/run_sim.sh b/designs/PE_INT/sim/run_sim.sh index 725cfea..702ff7c 100644 --- a/designs/PE_INT/sim/run_sim.sh +++ b/designs/PE_INT/sim/run_sim.sh @@ -14,10 +14,6 @@ CASES=( "tc_mode2b_sanity" "tc_mode2c_sanity" "tc_mode2d_sanity" - "tc_mode2a_sanity_rand_timing" - "tc_mode2b_sanity_rand_timing" - "tc_mode2c_sanity_rand_timing" - "tc_mode2d_sanity_rand_timing" "tc_mode_switch_random" ) @@ -189,118 +185,6 @@ cleanup_pass_logs() { fi } -run_cases_parallel_iverilog() { - local seed="$1" - local log_root="$2" - local failures=0 - local -a pids=() - local -a names=() - - for c in "${CASES[@]}"; do - local case_log="${log_root}/seed_${seed}_${c}.log" - ( - set -euo pipefail - echo "[INFO] simulator=iverilog case=${c} seed=${seed}" - iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" - if [[ "$WAVE_ON" -eq 1 ]]; then - CASE_WAVE_DIR="${WAVE_ROOT}/${c}" - mkdir -p "$CASE_WAVE_DIR" - ( - cd "$CASE_WAVE_DIR" - vvp "${ROOT}/build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 - ) - else - vvp "build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" - fi - ) >"$case_log" 2>&1 & - pids+=("$!") - names+=("$c") - echo "[INFO] launch iverilog case=${c} (log=${case_log})" - done - - for idx in "${!pids[@]}"; do - local pid="${pids[$idx]}" - local case_name="${names[$idx]}" - local case_log="${log_root}/seed_${seed}_${case_name}.log" - if wait "$pid"; then - echo "[PASS] [iverilog] ${case_name}" - else - failures=$((failures + 1)) - echo "[FAIL] [iverilog] ${case_name} (see ${case_log})" - fi - done - - if (( failures > 0 )); then - echo "[ERR] [iverilog] failed cases: ${failures}" - return 1 - fi -} - -run_cases_parallel_verilator() { - local seed="$1" - local log_root="$2" - local failures=0 - local -a pids=() - local -a names=() - - if [[ "$seed_idx" -eq 0 ]]; then - echo "[INFO] build verilator binaries for all cases..." - for c in "${CASES[@]}"; do - if [[ "$WAVE_ON" -eq 1 && "$WAVE_FMT" == "fst" ]]; then - verilator --binary --timing -Wall -Wno-fatal --trace-fst -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" - elif [[ "$WAVE_ON" -eq 1 ]]; then - verilator --binary --timing -Wall -Wno-fatal --trace -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" - else - verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" - fi - done - else - echo "[INFO] reuse existing verilator binaries for all cases" - fi - - for c in "${CASES[@]}"; do - local case_log="${log_root}/seed_${seed}_${c}.log" - ( - set -euo pipefail - echo "[INFO] simulator=verilator case=${c} seed=${seed}" - if [[ "$WAVE_ON" -eq 1 ]]; then - CASE_WAVE_DIR="${WAVE_ROOT}/${c}" - mkdir -p "$CASE_WAVE_DIR" - ( - cd "$CASE_WAVE_DIR" - if [[ "$WAVE_FMT" == "fst" ]]; then - "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=1 - else - "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 - fi - ) - else - "./obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" - fi - ) >"$case_log" 2>&1 & - pids+=("$!") - names+=("$c") - echo "[INFO] launch verilator case=${c} (log=${case_log})" - done - - for idx in "${!pids[@]}"; do - local pid="${pids[$idx]}" - local case_name="${names[$idx]}" - local case_log="${log_root}/seed_${seed}_${case_name}.log" - if wait "$pid"; then - echo "[PASS] [verilator] ${case_name}" - else - failures=$((failures + 1)) - echo "[FAIL] [verilator] ${case_name} (see ${case_log})" - fi - done - - if (( failures > 0 )); then - echo "[ERR] [verilator] failed cases: ${failures}" - return 1 - fi -} - echo echo "[INFO] simulator=$SIM wave=$WAVE_ON format=$WAVE_FMT base_seed=$BASE_SEED seed_runs=$SEED_RUNS" @@ -324,9 +208,56 @@ for ((seed_idx = 0; seed_idx < SEED_RUNS; seed_idx++)); do echo "[INFO] testcase logs are under ${LOG_ROOT}" if [[ "$SIM" == "iverilog" ]]; then - run_cases_parallel_iverilog "$SEED" "$LOG_ROOT" + for c in "${CASES[@]}"; do + CASE_LOG="${LOG_ROOT}/seed_${SEED}_${c}.log" + { + echo "[INFO] simulator=iverilog case=${c} seed=${SEED}" + iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" + if [[ "$WAVE_ON" -eq 1 ]]; then + CASE_WAVE_DIR="${WAVE_ROOT}/${c}" + mkdir -p "$CASE_WAVE_DIR" + ( + cd "$CASE_WAVE_DIR" + vvp "${ROOT}/build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 + ) + else + vvp "build/${c}.iv.out" +GEN_DIR="${GEN_DIR}" + fi + } 2>&1 | tee "$CASE_LOG" + done else - run_cases_parallel_verilator "$SEED" "$LOG_ROOT" + for c in "${CASES[@]}"; do + CASE_LOG="${LOG_ROOT}/seed_${SEED}_${c}.log" + { + echo "[INFO] simulator=verilator case=${c} seed=${SEED}" + if [[ "$seed_idx" -eq 0 ]]; then + if [[ "$WAVE_ON" -eq 1 && "$WAVE_FMT" == "fst" ]]; then + verilator --binary --timing -Wall -Wno-fatal --trace-fst -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + elif [[ "$WAVE_ON" -eq 1 ]]; then + verilator --binary --timing -Wall -Wno-fatal --trace -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + else + verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + fi + else + echo "[INFO] reuse existing verilator binary for ${c}" + fi + + if [[ "$WAVE_ON" -eq 1 ]]; then + CASE_WAVE_DIR="${WAVE_ROOT}/${c}" + mkdir -p "$CASE_WAVE_DIR" + ( + cd "$CASE_WAVE_DIR" + if [[ "$WAVE_FMT" == "fst" ]]; then + "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=1 + else + "${ROOT}/obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" +WAVE=1 +WAVE_FST=0 + fi + ) + else + "./obj_dir/${c}.vlt.out" +GEN_DIR="${GEN_DIR}" + fi + } 2>&1 | tee "$CASE_LOG" + done fi done diff --git a/designs/PE_INT/tb/README.md b/designs/PE_INT/tb/README.md index 97f2e2b..f653713 100644 --- a/designs/PE_INT/tb/README.md +++ b/designs/PE_INT/tb/README.md @@ -1,14 +1,14 @@ -# tb (PyCircuit / Model-Oriented Testbench) +# tb（pyCircuit / 模型測試） -This directory only contains: +本目錄只放： -- PyCircuit testbenches (for example `tb_pe_int_pycircuit.py`) -- PyCircuit-related test flow files +- pyCircuit testbench（例如 `tb_pe_int_pycircuit.py`） +- pyCircuit 相關測試流程檔 -## Do Not Put Here +## 不放內容 -- Model implementation and model regression files (put in `model/`) -- RTL-specific Verilog testbenches -- RTL testcase datasets +- 模型本體與模型回歸（統一放 `model/`） +- RTL 專用 Verilog testbench +- RTL case 資料集 -Those artifacts belong in `model/` and `tb_rtl/` respectively. +上述內容分別統一放在 `model/` 與 `tb_rtl/`。 diff --git a/designs/PE_INT/tb/tb_pe_int_pycircuit.py b/designs/PE_INT/tb/tb_pe_int_pycircuit.py index 5397132..b56268c 100644 --- a/designs/PE_INT/tb/tb_pe_int_pycircuit.py +++ b/designs/PE_INT/tb/tb_pe_int_pycircuit.py @@ -1,103 +1,103 @@ -from __future__ import annotations - -import sys -from pathlib import Path - -from pycircuit import ( - CycleAwareCircuit, - CycleAwareDomain, - CycleAwareTb, - Tb, - compile_cycle_aware, - testbench, -) - -_THIS_DIR = Path(__file__).resolve().parent -_PY_DIR = _THIS_DIR.parent / "python" -_MODEL_DIR = _THIS_DIR.parent / "model" -if str(_PY_DIR) not in sys.path: - sys.path.insert(0, str(_PY_DIR)) -if str(_MODEL_DIR) not in sys.path: - sys.path.insert(0, str(_MODEL_DIR)) - -from pe_int_pycircuit import build # noqa: E402 -from ref_model import MODE_2A, MODE_2B, compute_transaction, pack_s4x8_to_40, pack_s8x8_to_laneword # noqa: E402 - -DEFAULT_PARAMS = {"latency": 3} - - -def _to_u(value: int, bits: int) -> int: - return value & ((1 << bits) - 1) - - -def _mode2b_vector(): - a = [1, -2, 3, -4, 5, -6, 7, -8] - b0 = [1, 2, -3, 4, -5, 6, -7, -8] - b1 = [-1, 2, 3, -4, 5, -6, 7, 0] - a80 = pack_s8x8_to_laneword(a) - b80 = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) - exp = compute_transaction(MODE_2B, a80, b80, 0, (0, 0), (0, 0), (0, 0)) - return a80, b80, exp - - -@testbench -def tb(t: Tb) -> None: - tb = CycleAwareTb(t) - tb.clock("clk") - tb.reset("rst_n", cycles_asserted=2, cycles_deasserted=1) - tb.timeout(200) - - a80, b80, exp2b = _mode2b_vector() - exp2a = compute_transaction( - MODE_2A, - pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), - pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), - 0, - (0, 0), - (0, 0), - (0, 0), - ) - - tb.drive("vld", 0) - tb.drive("mode", MODE_2A) - tb.drive("a", 0) - tb.drive("b", 0) - tb.drive("b1", 0) - tb.drive("e1_a", 0) - tb.drive("e1_b0", 0) - tb.drive("e1_b1", 0) - tb.expect("vld_out", 0) - - # cycle 0: inject 2b - tb.next() - tb.drive("vld", 1) - tb.drive("mode", MODE_2B) - tb.drive("a", _to_u(a80, 80)) - tb.drive("b", _to_u(b80, 80)) - tb.drive("b1", 0) - - # cycle 1: inject 2a - tb.next() - tb.drive("vld", 1) - tb.drive("mode", MODE_2A) - tb.drive("a", _to_u(pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), 80)) - tb.drive("b", _to_u(pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), 80)) - tb.drive("b1", 0) - - # drain and check outputs on target cycles. - for _ in range(20): - tb.next() - tb.drive("vld", 0) - if tb.cycle == 5: - tb.expect("vld_out", 1) - tb.expect("out0", _to_u(exp2b.out0_19, 19)) - tb.expect("out1", _to_u(exp2b.out1_16, 16)) - if tb.cycle == 6: - tb.expect("vld_out", 1) - tb.expect("out0", _to_u(exp2a.out0_19, 19)) - - tb.finish() - - -if __name__ == "__main__": - print(compile_cycle_aware(build, name="tb_pe_int_top", eager=True, **DEFAULT_PARAMS).emit_mlir()) +from __future__ import annotations + +import sys +from pathlib import Path + +from pycircuit import ( + CycleAwareCircuit, + CycleAwareDomain, + CycleAwareTb, + Tb, + compile_cycle_aware, + testbench, +) + +_THIS_DIR = Path(__file__).resolve().parent +_PY_DIR = _THIS_DIR.parent / "python" +_MODEL_DIR = _THIS_DIR.parent / "model" +if str(_PY_DIR) not in sys.path: + sys.path.insert(0, str(_PY_DIR)) +if str(_MODEL_DIR) not in sys.path: + sys.path.insert(0, str(_MODEL_DIR)) + +from pe_int_pycircuit import build # noqa: E402 +from ref_model import MODE_2A, MODE_2B, compute_transaction, pack_s4x8_to_40, pack_s8x8_to_laneword # noqa: E402 + +DEFAULT_PARAMS = {"latency": 4, "hierarchical": True} + + +def _to_u(value: int, bits: int) -> int: + return value & ((1 << bits) - 1) + + +def _mode2b_vector(): + a = [1, -2, 3, -4, 5, -6, 7, -8] + b0 = [1, 2, -3, 4, -5, 6, -7, -8] + b1 = [-1, 2, 3, -4, 5, -6, 7, 0] + a80 = pack_s8x8_to_laneword(a) + b80 = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) + exp = compute_transaction(MODE_2B, a80, b80, 0, (0, 0), (0, 0), (0, 0)) + return a80, b80, exp + + +@testbench +def tb(t: Tb) -> None: + tb = CycleAwareTb(t) + tb.clock("clk") + tb.reset("rst_n", cycles_asserted=2, cycles_deasserted=1) + tb.timeout(200) + + a80, b80, exp2b = _mode2b_vector() + exp2a = compute_transaction( + MODE_2A, + pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), + pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), + 0, + (0, 0), + (0, 0), + (0, 0), + ) + + tb.drive("vld", 0) + tb.drive("mode", MODE_2A) + tb.drive("a", 0) + tb.drive("b", 0) + tb.drive("b1", 0) + tb.drive("e1_a", 0) + tb.drive("e1_b0", 0) + tb.drive("e1_b1", 0) + tb.expect("vld_out", 0) + + # cycle 0: inject 2b + tb.next() + tb.drive("vld", 1) + tb.drive("mode", MODE_2B) + tb.drive("a", _to_u(a80, 80)) + tb.drive("b", _to_u(b80, 80)) + tb.drive("b1", 0) + + # cycle 1: inject 2a + tb.next() + tb.drive("vld", 1) + tb.drive("mode", MODE_2A) + tb.drive("a", _to_u(pack_s8x8_to_laneword([1, 2, 3, 4, 5, 6, 7, 8]), 80)) + tb.drive("b", _to_u(pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), 80)) + tb.drive("b1", 0) + + # drain and check outputs on target cycles. + for _ in range(20): + tb.next() + tb.drive("vld", 0) + if tb.cycle == 5: + tb.expect("vld_out", 1) + tb.expect("out0", _to_u(exp2b.out0_19, 19)) + tb.expect("out1", _to_u(exp2b.out1_16, 16)) + if tb.cycle == 6: + tb.expect("vld_out", 1) + tb.expect("out0", _to_u(exp2a.out0_19, 19)) + + tb.finish() + + +if __name__ == "__main__": + print(compile_cycle_aware(build, name="tb_pe_int_top", eager=True, **DEFAULT_PARAMS).emit_mlir()) diff --git a/designs/PE_INT/tb_rtl/README.md b/designs/PE_INT/tb_rtl/README.md index ffa8a77..add456b 100644 --- a/designs/PE_INT/tb_rtl/README.md +++ b/designs/PE_INT/tb_rtl/README.md @@ -1,31 +1,31 @@ -# RTL Test Environment (`tb_rtl`) +# RTL 測試環境（tb_rtl） -This directory stores files required for **RTL simulation**, separated from `tb/` (PyCircuit testbenches). +本目錄專門放 **RTL 仿真** 所需檔案，與 `tb/` 下的 pyCircuit testbench 分離。 -## Directory Layout +## 目錄說明 -- `case/`: RTL testcases (single-mode sanity + mode-switch random) -- `case/generated/`: testcase vectors and expected data generated by `model/gen_rtl_case_vectors.py` -- `tb.f`: testbench/case filelist (prefixed with absolute `$PE_INT`) -- `sim/run_all_wsl.sh`: batch-run `iverilog` / `verilator` in WSL +- `case/`: 各個 RTL testcase（單模式 sanity + 模式切換 random） +- `case/generated/`: 由 `model/gen_rtl_case_vectors.py` 自動產生的 testcase 向量與 expected +- `tb.f`: 驗證環境/用例 filelist（以 `$PE_INT` 絕對路徑為開頭） +- `sim/run_all_wsl.sh`: 在 WSL 內批次跑 `iverilog` / `verilator` -## Quick Run (WSL) +## 快速執行（WSL） -Run at repo root (e.g. `/mnt/d/git-repo/pycircuit/designs/PE_INT`): +在 repo root（`/mnt/d/src_code/PE_INT`）執行： ```bash bash sim/run_all_wsl.sh ``` -This script first resolves and runs: +此腳本會先透過 `model/model.f` 解析並執行： ```bash python3 ``` -Then it runs simulator regressions with filelists (`filelist/pe_int.f` + `tb_rtl/tb.f`). +再透過 filelist（`filelist/pe_int.f` + `tb_rtl/tb.f`）進行 simulator 回歸。 -## Single-Case Run Examples +## 單一用例執行範例 ### iverilog diff --git a/designs/PE_INT/tb_rtl/case/README.md b/designs/PE_INT/tb_rtl/case/README.md index 44838b1..446f1e9 100644 --- a/designs/PE_INT/tb_rtl/case/README.md +++ b/designs/PE_INT/tb_rtl/case/README.md @@ -1,39 +1,39 @@ -# RTL Testcases (`case`) +# RTL 測試案例（case） -Each `.v` file in this directory is an independent testcase and can be compiled/simulated alone. +本目錄每個 `.v` 檔是獨立 testcase（可單獨編譯/仿真）。 -## Case List and Purpose +## 案例清單與目的 - `tc_mode2a_sanity.v` - - Verifies mode 2a (`S8xS8`) math correctness. - - Verifies `out1` is not unnecessarily updated in 2a mode (holds previous dual-path value). + - 驗證 mode 2a（S8xS8）數學結果正確。 + - 驗證 2a 下 `out1` 不應被更新（保持前一個雙路模式值）。 - `tc_mode2b_sanity.v` - - Verifies mode 2b (`S8xS4`) dual outputs `out0/out1`. + - 驗證 mode 2b（S8xS4）雙路輸出 `out0/out1` 正確。 - `tc_mode2c_sanity.v` - - Verifies mode 2c (`S5xS5 + E1`) dual outputs. + - 驗證 mode 2c（S5xS5 + E1）雙路輸出正確。 - `tc_mode2d_sanity.v` - - Verifies mode 2d (`S8xS5`) dual outputs. + - 驗證 mode 2d（S8xS5）雙路輸出正確。 - `tc_mode_switch_random.v` - - Verifies `vld -> vld_out` alignment/order under back-to-back mode switching. - - Verifies output values under mixed traffic (including `vld=0` gaps). - - Expected data must be traceable to reference models in `model/`. + - 驗證 back-to-back 切 mode 時，`vld -> vld_out` 對齊與順序正確。 + - 驗證 mixed traffic（含 `vld=0` 空檔）下，輸出值與預期一致。 + - 預期值來源需可追溯到 `model/` 下的參考模型。 -## Naming Convention +## 命名規範 -- `tc_*`: directly usable as simulator top module names. -- Each case includes PASS/FAIL messages and `$fatal` for CI-friendly checks. +- `tc_*`：可直接做 simulator top module 使用。 +- 每個 case 內建 PASS/FAIL 訊息與 `$fatal`，方便 CI 直接判斷。 -## Automatic Expected Generation +## expected 自動生成 -- Generator: `gen_rtl_case_vectors.py` resolved from `model/model.f` -- Output: `tb_rtl/case/generated/*.vh` -- Testcases use these generated files via `` `include ``; do not handwrite expected values. +- 產生工具：`model/model.f` 內的 `gen_rtl_case_vectors.py` +- 產生輸出：`tb_rtl/case/generated/*.vh` +- testcase 透過 `` `include `` 使用這些自動檔案，不手抄 expected。 -Manual regenerate (resolved through filelist): +手動重生（透過 filelist 解析）： ```bash export PE_INT="$(pwd)" diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v index 85b92bc..9a15e9a 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity.v @@ -35,7 +35,7 @@ module tc_mode2a_sanity; localparam [1:0] MODE_2B = 2'b01; localparam string CASE_NAME = "2a"; - pe_int_l3 dut ( + PE_INT dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) ); diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v index 1706e65..fb2d901 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v @@ -38,7 +38,7 @@ module tc_mode2a_sanity_rand_timing; localparam [1:0] MODE_FIXED = 2'b00; localparam string CASE_NAME = "2a_rand"; - pe_int_l3 dut ( + PE_INT dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) ); diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v index c8008e0..8067800 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity.v @@ -29,7 +29,7 @@ module tc_mode2b_sanity; localparam [1:0] MODE_2B = 2'b01; localparam string CASE_NAME = "2b"; - pe_int_l3 dut ( + PE_INT dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) ); diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v index 72f2263..e875895 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v @@ -38,7 +38,7 @@ module tc_mode2b_sanity_rand_timing; localparam [1:0] MODE_FIXED = 2'b01; localparam string CASE_NAME = "2b_rand"; - pe_int_l3 dut ( + PE_INT dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) ); diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v index 0d6afa5..f618c51 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity.v @@ -33,7 +33,7 @@ module tc_mode2c_sanity; localparam [1:0] MODE_2C = 2'b10; localparam string CASE_NAME = "2c"; - pe_int_l3 dut ( + PE_INT dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) ); diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v index 8d62aae..fd008a3 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v @@ -38,7 +38,7 @@ module tc_mode2c_sanity_rand_timing; localparam [1:0] MODE_FIXED = 2'b10; localparam string CASE_NAME = "2c_rand"; - pe_int_l3 dut ( + PE_INT dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) ); diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v index faa7f4f..e31c750 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity.v @@ -29,7 +29,7 @@ module tc_mode2d_sanity; localparam [1:0] MODE_2D = 2'b11; localparam string CASE_NAME = "2d"; - pe_int_l3 dut ( + PE_INT dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) ); diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v index a7ac1f0..54be158 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v @@ -38,7 +38,7 @@ module tc_mode2d_sanity_rand_timing; localparam [1:0] MODE_FIXED = 2'b11; localparam string CASE_NAME = "2d_rand"; - pe_int_l3 dut ( + PE_INT dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) ); diff --git a/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v b/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v index 0fe3e66..4b7f2a8 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v @@ -1,110 +1,110 @@ -`timescale 1ns/1ps - -module tc_mode_switch_random; - reg clk; - reg rst_n; - reg vld; - reg [1:0] mode; - reg [79:0] a; - reg [79:0] b; - reg [79:0] b1; - reg [1:0] e1_a; - reg [1:0] e1_b0; - reg [1:0] e1_b1; - - wire signed [18:0] out0; - wire signed [15:0] out1; - wire vld_out; - - integer i; - integer got; - integer err; - integer exp_count; - localparam integer N_TX = 1000; - localparam integer N_EXP_MAX = 1000; - string gen_dir; - reg [31:0] meta [0:0]; - - reg tx_vld [0:N_TX-1]; - reg [1:0] tx_mode [0:N_TX-1]; - reg [79:0] tx_a [0:N_TX-1]; - reg [79:0] tx_b [0:N_TX-1]; - reg [79:0] tx_b1 [0:N_TX-1]; - reg [1:0] tx_e1a [0:N_TX-1]; - reg [1:0] tx_e1b0 [0:N_TX-1]; - reg [1:0] tx_e1b1 [0:N_TX-1]; - - reg [18:0] exp_o0 [0:N_EXP_MAX-1]; - reg [15:0] exp_o1 [0:N_EXP_MAX-1]; - localparam string CASE_NAME = "rand"; - - pe_int_l3 dut ( - .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), - .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) - ); - - `include "common_wave_dump.vh" - `include "common_exact_latency_scoreboard.vh" - - always #5 clk = ~clk; - - always @(posedge clk) begin - if (!rst_n) begin - sb_reset(); - end else begin - sb_tick(); - end - end - - initial begin - clk = 0; rst_n = 0; vld = 0; mode = 0; - a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; - exp_count = 0; sb_reset(); - - if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin - gen_dir = "tb_rtl/case/generated"; - end - $readmemh({gen_dir, "/tc_mode_switch_random_tx_vld.mem"}, tx_vld); - $readmemh({gen_dir, "/tc_mode_switch_random_tx_mode.mem"}, tx_mode); - $readmemh({gen_dir, "/tc_mode_switch_random_tx_a.mem"}, tx_a); - $readmemh({gen_dir, "/tc_mode_switch_random_tx_b.mem"}, tx_b); - $readmemh({gen_dir, "/tc_mode_switch_random_tx_b1.mem"}, tx_b1); - $readmemh({gen_dir, "/tc_mode_switch_random_tx_e1a.mem"}, tx_e1a); - $readmemh({gen_dir, "/tc_mode_switch_random_tx_e1b0.mem"}, tx_e1b0); - $readmemh({gen_dir, "/tc_mode_switch_random_tx_e1b1.mem"}, tx_e1b1); - $readmemh({gen_dir, "/tc_mode_switch_random_exp_o0.mem"}, exp_o0); - $readmemh({gen_dir, "/tc_mode_switch_random_exp_o1.mem"}, exp_o1); - $readmemh({gen_dir, "/tc_mode_switch_random_meta.mem"}, meta); - exp_count = meta[0]; - - repeat (3) @(posedge clk); - rst_n = 1; - repeat (3) @(posedge clk); - - for (i = 0; i < N_TX; i = i + 1) begin - @(negedge clk); - vld = tx_vld[i]; - mode = tx_mode[i]; - a = tx_a[i]; - b = tx_b[i]; - b1 = tx_b1[i]; - e1_a = tx_e1a[i]; - e1_b0 = tx_e1b0[i]; - e1_b1 = tx_e1b1[i]; - end - - @(negedge clk); - vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - - repeat (30) @(posedge clk); - sb_final_check(); - - if (err == 0) begin - $display("[PASS] tc_mode_switch_random"); - end else begin - $fatal(1, "[FAIL] tc_mode_switch_random err=%0d", err); - end - $finish; - end -endmodule +`timescale 1ns/1ps + +module tc_mode_switch_random; + reg clk; + reg rst_n; + reg vld; + reg [1:0] mode; + reg [79:0] a; + reg [79:0] b; + reg [79:0] b1; + reg [1:0] e1_a; + reg [1:0] e1_b0; + reg [1:0] e1_b1; + + wire signed [18:0] out0; + wire signed [15:0] out1; + wire vld_out; + + integer i; + integer got; + integer err; + integer exp_count; + localparam integer N_TX = 1000; + localparam integer N_EXP_MAX = 1000; + string gen_dir; + reg [31:0] meta [0:0]; + + reg tx_vld [0:N_TX-1]; + reg [1:0] tx_mode [0:N_TX-1]; + reg [79:0] tx_a [0:N_TX-1]; + reg [79:0] tx_b [0:N_TX-1]; + reg [79:0] tx_b1 [0:N_TX-1]; + reg [1:0] tx_e1a [0:N_TX-1]; + reg [1:0] tx_e1b0 [0:N_TX-1]; + reg [1:0] tx_e1b1 [0:N_TX-1]; + + reg [18:0] exp_o0 [0:N_EXP_MAX-1]; + reg [15:0] exp_o1 [0:N_EXP_MAX-1]; + localparam string CASE_NAME = "rand"; + + PE_INT dut ( + .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), + .e1_a(e1_a), .e1_b0(e1_b0), .e1_b1(e1_b1), .out0(out0), .out1(out1), .vld_out(vld_out) + ); + + `include "common_wave_dump.vh" + `include "common_exact_latency_scoreboard.vh" + + always #5 clk = ~clk; + + always @(posedge clk) begin + if (!rst_n) begin + sb_reset(); + end else begin + sb_tick(); + end + end + + initial begin + clk = 0; rst_n = 0; vld = 0; mode = 0; + a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + got = 0; err = 0; + exp_count = 0; sb_reset(); + + if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin + gen_dir = "tb_rtl/case/generated"; + end + $readmemh({gen_dir, "/tc_mode_switch_random_tx_vld.mem"}, tx_vld); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_mode.mem"}, tx_mode); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_a.mem"}, tx_a); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_b.mem"}, tx_b); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_b1.mem"}, tx_b1); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_e1a.mem"}, tx_e1a); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_e1b0.mem"}, tx_e1b0); + $readmemh({gen_dir, "/tc_mode_switch_random_tx_e1b1.mem"}, tx_e1b1); + $readmemh({gen_dir, "/tc_mode_switch_random_exp_o0.mem"}, exp_o0); + $readmemh({gen_dir, "/tc_mode_switch_random_exp_o1.mem"}, exp_o1); + $readmemh({gen_dir, "/tc_mode_switch_random_meta.mem"}, meta); + exp_count = meta[0]; + + repeat (3) @(posedge clk); + rst_n = 1; + repeat (3) @(posedge clk); + + for (i = 0; i < N_TX; i = i + 1) begin + @(negedge clk); + vld = tx_vld[i]; + mode = tx_mode[i]; + a = tx_a[i]; + b = tx_b[i]; + b1 = tx_b1[i]; + e1_a = tx_e1a[i]; + e1_b0 = tx_e1b0[i]; + e1_b1 = tx_e1b1[i]; + end + + @(negedge clk); + vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; + + repeat (30) @(posedge clk); + sb_final_check(); + + if (err == 0) begin + $display("[PASS] tc_mode_switch_random"); + end else begin + $fatal(1, "[FAIL] tc_mode_switch_random err=%0d", err); + end + $finish; + end +endmodule diff --git a/designs/PE_INT/tb_rtl/tb.f b/designs/PE_INT/tb_rtl/tb.f index cb33bfe..7311afc 100644 --- a/designs/PE_INT/tb_rtl/tb.f +++ b/designs/PE_INT/tb_rtl/tb.f @@ -3,8 +3,4 @@ $PE_INT/tb_rtl/case/tc_mode2b_sanity.v $PE_INT/tb_rtl/case/tc_mode2c_sanity.v $PE_INT/tb_rtl/case/tc_mode2d_sanity.v -$PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v -$PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v -$PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v -$PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v $PE_INT/tb_rtl/case/tc_mode_switch_random.v From f816e309728365b0a1386fcb79cba22e66cbaf52 Mon Sep 17 00:00:00 2001 From: HenryLee Date: Wed, 6 May 2026 10:56:40 +0800 Subject: [PATCH 06/10] fix(designs): address PE_INT review follow-ups --- agents/skill/pe_int/SKILL.md | 4 ++-- .../generated-rtl-contract-audit/SKILL.md | 6 ++++++ .../skills/pe-int-implementation/SKILL.md | 6 +++++- .../skills/pe-int-pycircuiteval-flow/SKILL.md | 6 +++++- .../spec-structural-intent-review/SKILL.md | 5 +++++ designs/PE_INT/README.md | 2 +- designs/PE_INT/model/README.md | 2 +- designs/PE_INT/model/pe_int_pycircuit_eval.py | 18 +++++++++++------- designs/PE_INT/model/test_pe_int.py | 8 ++++---- designs/PE_INT/python/pe_int/pipeline.py | 16 ---------------- designs/PE_INT/sim/run_all_wsl.sh | 9 ++++++++- designs/PE_INT/sim/run_sim.sh | 13 ++++++++++--- designs/PE_INT/tb_rtl/README.md | 3 ++- 13 files changed, 60 insertions(+), 38 deletions(-) delete mode 100644 designs/PE_INT/python/pe_int/pipeline.py diff --git a/agents/skill/pe_int/SKILL.md b/agents/skill/pe_int/SKILL.md index a996865..bc1cce1 100644 --- a/agents/skill/pe_int/SKILL.md +++ b/agents/skill/pe_int/SKILL.md @@ -36,13 +36,13 @@ Do this before implementation: Decision policy: - `<= 25`: within target, no action needed. -- `26 ~ 30`: acceptable as guideline overflow; must warn user and suggest optional repartition. +- `26..30`: acceptable as guideline overflow; must warn user and suggest optional repartition. - `> 30`: strong risk; propose repartition or structural optimization and request user decision. ## 6) Definition of Done (DoD) - [ ] Latency convention is explicitly documented. - [ ] Functional spec and design spec latency semantics are consistent. - [ ] Real RTL path register-count evidence is provided. -- [ ] Stage logic depth check is recorded (including warning if 26~30). +- [ ] Stage logic depth check is recorded (including warning if 26..30). - [ ] Regression/simulation passes. - [ ] No transaction reorder under continuous valid traffic. diff --git a/designs/PE_INT/.cursor/skills/generated-rtl-contract-audit/SKILL.md b/designs/PE_INT/.cursor/skills/generated-rtl-contract-audit/SKILL.md index 61855e7..f97401b 100644 --- a/designs/PE_INT/.cursor/skills/generated-rtl-contract-audit/SKILL.md +++ b/designs/PE_INT/.cursor/skills/generated-rtl-contract-audit/SKILL.md @@ -21,6 +21,8 @@ Do not treat source-level tests or model regressions as sufficient proof that de 6. Confirm stale generated modules/files are removed or excluded. 7. Confirm submodules instantiated by the top are present in the filelist. 8. Confirm generated RTL has no unexpected compatibility wrapper unless explicitly required. +9. Check simulator/lint warnings for unused signals, unused bits, and unused + ports. Treat `UNUSEDSIGNAL` as a review item even when functionality passes. ## Required Evidence @@ -29,6 +31,8 @@ When closing the task, report: - Which generated files were audited. - The key contract points checked. - The command or search used to prove there are no stale names/files. +- Any unused-signal warnings found, why they exist, and whether source changes + can remove them instead of suppressing them. - Regression status after the audit. ## Common Failure Patterns @@ -38,3 +42,5 @@ When closing the task, report: - Top module name is patched but submodule or primitive names are not. - Source module names are correct but deliverable filenames violate repo convention. - Old build directories leak stale modules into synced RTL. +- Generated RTL contains unused ports/signals/bits that come from stale + intermediates, over-wide expressions, or copied submodule interfaces. diff --git a/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md index f5b6b0e..9564961 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md @@ -64,7 +64,11 @@ If area and dynamic power conflict, prioritize dynamic power. 3. Keep each submodule core logic around 200 lines or less when possible. 4. Keep top-level focused on stage orchestration and alignment. 5. Control and datapath must advance at matching stage depth. - +6. Pure combinational submodules should not have `clk`/`rst` ports. If a + PyCircuit hierarchy API forces these ports on a combinational submodule, + treat that as a framework limitation to report, not as a normal coding + pattern to copy. + ## Mandatory Stage Coding Contract Top-level coding must be explicit: diff --git a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md index 659f610..480e484 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md @@ -71,7 +71,11 @@ Extract executable checks from `docs/spec.md`: 3. Keep submodule core logic around 200 lines or less when practical. 4. Keep top-level focused on stage connection/alignment. 5. Keep control-path and datapath depth-aligned. - +6. Pure combinational submodules should not expose or propagate `clk`/`rst`. + Only stateful submodules should carry clock/reset ports; if a PyCircuit API + forces clock/reset on a combinational hierarchy boundary, document it as a + framework limitation and avoid adding internal logic that depends on them. + ### Step B.2: Mandatory Stage Contract Top-level must be reviewable as: diff --git a/designs/PE_INT/.cursor/skills/spec-structural-intent-review/SKILL.md b/designs/PE_INT/.cursor/skills/spec-structural-intent-review/SKILL.md index c857c12..b394597 100644 --- a/designs/PE_INT/.cursor/skills/spec-structural-intent-review/SKILL.md +++ b/designs/PE_INT/.cursor/skills/spec-structural-intent-review/SKILL.md @@ -26,6 +26,9 @@ Passing functional tests is not enough when the spec requires a particular struc 4. For latency, count actual registers on the real signal path. 5. For arithmetic, verify the requested topology is present, not just functionally equivalent. 6. For width contracts, verify each operation's input/output width has no arbitrary margin and no overflow in covered scenarios. +7. Review generated RTL warnings for unused signals/bits/ports. Do not ignore + them only because simulation passes; unused logic increases later dead-code + cleanup cost and can hide source-structure mistakes. ## When To Warn @@ -36,6 +39,8 @@ Warn the user when: - Multiple comb blocks are merged without checking logic depth. - A generated design adds hidden balancing registers that change effective latency. - A datapath expression relies on implicit or private width behavior. +- Generated RTL exposes unused signals, unused high bits, or unused clock/reset + ports on combinational submodules. ## Required Evidence diff --git a/designs/PE_INT/README.md b/designs/PE_INT/README.md index dc9bef0..391a53f 100644 --- a/designs/PE_INT/README.md +++ b/designs/PE_INT/README.md @@ -22,7 +22,7 @@ ## 主要檔案 - `model/ref_model.py`: 四模式數學與打包/解包參考模型 -- `model/pe_int_pycircuit_eval.py`: cycle-accurate golden pipeline model（L=3） +- `model/pe_int_pycircuit_eval.py`: cycle-accurate golden pipeline model（L=4） - `model/test_pe_int.py`: 模型層隨機回歸（功能與時序對齊） - `model/gen_rtl_case_vectors.py`: 自動重生 `tb_rtl/case` 的 expected 向量 - `python/pe_int_pycircuit.py`: pyCircuit frontend 設計入口（source of RTL） diff --git a/designs/PE_INT/model/README.md b/designs/PE_INT/model/README.md index c65fb8b..9ce8e81 100644 --- a/designs/PE_INT/model/README.md +++ b/designs/PE_INT/model/README.md @@ -5,7 +5,7 @@ ## 內容 - `ref_model.py`: 四模式數學語義與打包/解包參考模型 -- `pe_int_pycircuit_eval.py`: cycle-accurate pipeline 模型（L=3） +- `pe_int_pycircuit_eval.py`: cycle-accurate pipeline 模型（L=4） - `test_pe_int.py`: 模型層回歸測試（不直接跑 RTL simulator） - `gen_rtl_case_vectors.py`: 依模型自動產生 `tb_rtl/case` 的 testcase 向量與 expected - `model.f`: model 檔案清單（以 `$PE_INT` 絕對路徑為開頭） diff --git a/designs/PE_INT/model/pe_int_pycircuit_eval.py b/designs/PE_INT/model/pe_int_pycircuit_eval.py index 00f4363..7a731a5 100644 --- a/designs/PE_INT/model/pe_int_pycircuit_eval.py +++ b/designs/PE_INT/model/pe_int_pycircuit_eval.py @@ -4,7 +4,7 @@ from ref_model import MODE_2A, MacResult, compute_transaction, to_signed -DEFAULT_PIPELINE_L = 3 +DEFAULT_PIPELINE_L = 4 @dataclass @@ -22,13 +22,14 @@ class StepResult: out1: int -class PEIntL3Model: +class PEIntModel: """Cycle-accurate PE_INT model for golden checking.""" def __init__(self) -> None: self.s0 = StagePayload() self.s1 = StagePayload() self.s2 = StagePayload() + self.s3 = StagePayload() self.out0 = 0 self.out1 = 0 self.vld_out = 0 @@ -39,6 +40,7 @@ def reset(self) -> None: self.s0 = StagePayload() self.s1 = StagePayload() self.s2 = StagePayload() + self.s3 = StagePayload() self.out0 = 0 self.out1 = 0 self.vld_out = 0 @@ -66,18 +68,19 @@ def step( self.s0 = StagePayload() self.s1 = StagePayload() self.s2 = StagePayload() + self.s3 = StagePayload() self.vld_out = 0 self.out0 = 0 self.out1 = 0 return StepResult(vld_out=0, out0=0, out1=0) - new_vld_out = self.s2.vld + new_vld_out = self.s3.vld new_out0 = self.out0 new_out1 = self.out1 - if self.s2.vld: - new_out0 = to_signed(self.s2.out0_19, 19) - if self.s2.mode != MODE_2A: - new_out1 = to_signed(self.s2.out1_16, 16) + if self.s3.vld: + new_out0 = to_signed(self.s3.out0_19, 19) + if self.s3.mode != MODE_2A: + new_out1 = to_signed(self.s3.out1_16, 16) if vld: mac: MacResult = compute_transaction(mode, a, b, b1, e1_a, e1_b0, e1_b1) @@ -90,6 +93,7 @@ def step( else: next_s0 = StagePayload(vld=0, mode=mode & 0x3, out0_19=0, out1_16=0) + self.s3 = StagePayload(self.s2.vld, self.s2.mode, self.s2.out0_19, self.s2.out1_16) self.s2 = StagePayload(self.s1.vld, self.s1.mode, self.s1.out0_19, self.s1.out1_16) self.s1 = StagePayload(self.s0.vld, self.s0.mode, self.s0.out0_19, self.s0.out1_16) self.s0 = next_s0 diff --git a/designs/PE_INT/model/test_pe_int.py b/designs/PE_INT/model/test_pe_int.py index 71cfdf3..9bcce9d 100644 --- a/designs/PE_INT/model/test_pe_int.py +++ b/designs/PE_INT/model/test_pe_int.py @@ -8,7 +8,7 @@ MODEL_DIR = Path(__file__).resolve().parent sys.path.insert(0, str(MODEL_DIR)) -from pe_int_pycircuit_eval import DEFAULT_PIPELINE_L, PEIntL3Model +from pe_int_pycircuit_eval import DEFAULT_PIPELINE_L, PEIntModel from ref_model import ( MODE_2A, MODE_2B, @@ -85,7 +85,7 @@ def test_mode_math_direct(self) -> None: self.assertLessEqual(got.out1_16, (1 << 15) - 1) def test_pipeline_alignment_and_mode_switch(self) -> None: - dut = PEIntL3Model() + dut = PEIntModel() expected: list[tuple[int, int, int, int]] = [] # cycle, mode, out0, out1 out_hits = 0 @@ -143,7 +143,7 @@ def test_pipeline_alignment_and_mode_switch(self) -> None: self.assertGreater(out_hits, 0) def test_mode2a_out1_no_toggle(self) -> None: - dut = PEIntL3Model() + dut = PEIntModel() # First, drive one non-2a sample to set out1 base. a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2B) @@ -159,7 +159,7 @@ def test_mode2a_out1_no_toggle(self) -> None: self.assertEqual(dut.out1, base_out1) def test_async_reset_clears_pipeline(self) -> None: - dut = PEIntL3Model() + dut = PEIntModel() # inject a valid sample a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2D) dut.step(rst_n=1, vld=1, mode=MODE_2D, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) diff --git a/designs/PE_INT/python/pe_int/pipeline.py b/designs/PE_INT/python/pe_int/pipeline.py deleted file mode 100644 index c014325..0000000 --- a/designs/PE_INT/python/pe_int/pipeline.py +++ /dev/null @@ -1,16 +0,0 @@ -from __future__ import annotations - -from pycircuit import mux - -from .constants import MODE_2A, MODE_2B, MODE_2C - - -def select_mode(mode, v2a, v2b, v2c, v2d): - return mux(mode == MODE_2A, v2a, mux(mode == MODE_2B, v2b, mux(mode == MODE_2C, v2c, v2d))) - - -def out1_hold_policy(domain, *, vld_aligned, out1_en_aligned, out1_aligned, prefix: str = "pe"): - out1_hold = domain.state(width=16, reset_value=0, name=f"{prefix}_out1_hold") - out1_next = mux(vld_aligned, mux(out1_en_aligned, out1_aligned, out1_hold), out1_hold) - out1_hold.set(out1_next) - return out1_next diff --git a/designs/PE_INT/sim/run_all_wsl.sh b/designs/PE_INT/sim/run_all_wsl.sh index 0244ecd..f47d39b 100644 --- a/designs/PE_INT/sim/run_all_wsl.sh +++ b/designs/PE_INT/sim/run_all_wsl.sh @@ -38,6 +38,13 @@ CASES=( "tc_mode_switch_random" ) +VERILATOR_WARNING_FLAGS=( + -Wno-DECLFILENAME + -Wno-TIMESCALEMOD + -Wno-UNUSEDSIGNAL + -Wno-BLKSEQ +) + echo "[INFO] Running RTL cases with iverilog..." for c in "${CASES[@]}"; do iverilog -g2012 -s "$c" -f "$RTL_FILELIST" -f "$TB_FILELIST" -o "build/${c}.iv.out" @@ -46,7 +53,7 @@ done echo "[INFO] Running RTL cases with verilator..." for c in "${CASES[@]}"; do - verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + verilator --binary --timing -Wall "${VERILATOR_WARNING_FLAGS[@]}" -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" "./obj_dir/${c}.vlt.out" done diff --git a/designs/PE_INT/sim/run_sim.sh b/designs/PE_INT/sim/run_sim.sh index 702ff7c..dc55a03 100644 --- a/designs/PE_INT/sim/run_sim.sh +++ b/designs/PE_INT/sim/run_sim.sh @@ -17,6 +17,13 @@ CASES=( "tc_mode_switch_random" ) +VERILATOR_WARNING_FLAGS=( + -Wno-DECLFILENAME + -Wno-TIMESCALEMOD + -Wno-UNUSEDSIGNAL + -Wno-BLKSEQ +) + mkdir -p build RTL_FILELIST_SRC="$ROOT/filelist/pe_int.f" @@ -232,11 +239,11 @@ for ((seed_idx = 0; seed_idx < SEED_RUNS; seed_idx++)); do echo "[INFO] simulator=verilator case=${c} seed=${SEED}" if [[ "$seed_idx" -eq 0 ]]; then if [[ "$WAVE_ON" -eq 1 && "$WAVE_FMT" == "fst" ]]; then - verilator --binary --timing -Wall -Wno-fatal --trace-fst -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + verilator --binary --timing -Wall "${VERILATOR_WARNING_FLAGS[@]}" --trace-fst -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" elif [[ "$WAVE_ON" -eq 1 ]]; then - verilator --binary --timing -Wall -Wno-fatal --trace -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + verilator --binary --timing -Wall "${VERILATOR_WARNING_FLAGS[@]}" --trace -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" else - verilator --binary --timing -Wall -Wno-fatal -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" + verilator --binary --timing -Wall "${VERILATOR_WARNING_FLAGS[@]}" -f "$RTL_FILELIST" -f "$TB_FILELIST" --top-module "$c" -o "${c}.vlt.out" fi else echo "[INFO] reuse existing verilator binary for ${c}" diff --git a/designs/PE_INT/tb_rtl/README.md b/designs/PE_INT/tb_rtl/README.md index add456b..7fc4c59 100644 --- a/designs/PE_INT/tb_rtl/README.md +++ b/designs/PE_INT/tb_rtl/README.md @@ -43,7 +43,8 @@ vvp build/tc_mode2b_sanity.out export PE_INT="$(pwd)" sed "s|\$PE_INT|${PE_INT}|g" filelist/pe_int.f > build/.pe_int.resolved.f sed "s|\$PE_INT|${PE_INT}|g" tb_rtl/tb.f > build/.tb.resolved.f -verilator --binary --timing -Wall -Wno-fatal \ +verilator --binary --timing -Wall \ + -Wno-DECLFILENAME -Wno-TIMESCALEMOD -Wno-UNUSEDSIGNAL -Wno-BLKSEQ \ -f build/.pe_int.resolved.f -f build/.tb.resolved.f \ --top-module tc_mode2b_sanity -o tc_mode2b_sanity ./obj_dir/tc_mode2b_sanity From 1372963d3727bad37f8c95f9f0352dc79a376645 Mon Sep 17 00:00:00 2001 From: HenryLee Date: Wed, 6 May 2026 11:54:45 +0800 Subject: [PATCH 07/10] fix(designs): eliminate PE_INT unused RTL warnings Regenerate PE_INT with width-specific Wallace reductions and remove unused-signal suppression so Verilator can catch real dead logic. --- .../skills/pe-int-implementation/SKILL.md | 160 +- .../skills/pe-int-pycircuiteval-flow/SKILL.md | 308 +- designs/PE_INT/.gitignore | 59 +- designs/PE_INT/filelist/pe_int.f | 3 +- designs/PE_INT/model/test_pe_int.py | 348 +- designs/PE_INT/python/build.py | 35 + designs/PE_INT/python/pe_int/decode.py | 20 +- designs/PE_INT/python/pe_int/lane_mac.py | 24 +- designs/PE_INT/python/pe_int/mac_modes.py | 87 +- designs/PE_INT/python/pe_int/top.py | 29 +- designs/PE_INT/rtl/build/pe_int.v | 4014 ++++++++--------- .../rtl/build/pe_int_wallace_dot8_tree.v | 3130 ------------- .../rtl/build/pe_int_wallace_dot8_tree_w16.v | 1528 +++++++ .../rtl/build/pe_int_wallace_dot8_tree_w19.v | 1828 ++++++++ designs/PE_INT/sim/run_all_wsl.sh | 1 - designs/PE_INT/sim/run_sim.sh | 1 - designs/PE_INT/tb/tb_pe_int_pycircuit.py | 7 +- designs/PE_INT/tb_rtl/README.md | 2 +- .../tb_rtl/case/tc_mode_switch_random.v | 30 +- 19 files changed, 5935 insertions(+), 5679 deletions(-) delete mode 100644 designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree.v create mode 100644 designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w16.v create mode 100644 designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w19.v diff --git a/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md index 9564961..d3df16b 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md @@ -1,85 +1,85 @@ ---- -name: pe-int-implementation -description: Project-level implementation guidance for PE_INT. Use for PE_INT coding choices, pipeline structure, latency alignment, power/area trade-offs, and debug order. ---- - -# PE_INT Implementation Guidance (Non-Formal) - -This is a project skill for implementation intent and practical trade-offs. -It does **not** override frozen rules in `docs/spec.md`. -If there is any conflict, `docs/spec.md` wins. - -## Hard Rule: RTL Source Ownership - -1. Deliverable RTL must be generated from PyCircuit source through `pycircuit.cli build` / `pycc`. -2. Do not accept model-generated RTL as deliverable output. -3. Do not hand-edit generated RTL for final delivery. -4. If spec is ambiguous, ask the user for clarification before changing behavior. - -## Fixed Debug SOP (Seed -> Model -> PyCircuit -> RTL) - -When any testcase fails, follow this order: - -1. Record failing seed, testcase, and simulator. -2. Reproduce with the same seed and regenerate vectors. -3. Run model checks first; if model fails, fix model/spec alignment first. -4. If model passes, run PyCircuit checks. -5. If PyCircuit fails, fix `python/` and rebuild RTL. -6. Only debug RTL-level issues after model and PyCircuit both pass. -7. Re-verify failing case first, then run full regression. - -Use `pass/fail` wording in reports. - -## Regression Notes - -- Sanity and random vectors are seed-dependent and reproducible. -- Runtime vector loading (`$readmemh` + `+GEN_DIR`) is preferred over compile-time baked expected data. -- Default output paths: - - logs: `sim/logs/` - - waves: `sim/waves/` - -## `vld` to `vld_out` and Pipeline Depth - -- Enforce one-to-one mapping from sampled `vld` to `vld_out`. -- Keep fixed latency `L` across all modes. -- Keep internal pipeline stage count identical across all modes. -- Use full pipeline datapath; no independent FIFOs for reordering. -- Latency must be measured by **actual register count on real paths** (control and data), - not by stage naming conventions. -- Always verify `vld_out` path and `out0/out1` paths separately, then check alignment. - -## Power and Area Priority - -After functionality and logic-depth constraints are satisfied: - -1. Reduce dynamic power as primary priority. -2. Reduce area as secondary priority. - -If area and dynamic power conflict, prioritize dynamic power. - -## PyCircuit Structure Requirements - -1. Stage boundaries must be explicit and reviewable. -2. Keep submodules split into separate files. -3. Keep each submodule core logic around 200 lines or less when possible. -4. Keep top-level focused on stage orchestration and alignment. -5. Control and datapath must advance at matching stage depth. +--- +name: pe-int-implementation +description: Project-level implementation guidance for PE_INT. Use for PE_INT coding choices, pipeline structure, latency alignment, power/area trade-offs, and debug order. +--- + +# PE_INT Implementation Guidance (Non-Formal) + +This is a project skill for implementation intent and practical trade-offs. +It does **not** override frozen rules in `docs/spec.md`. +If there is any conflict, `docs/spec.md` wins. + +## Hard Rule: RTL Source Ownership + +1. Deliverable RTL must be generated from PyCircuit source through `pycircuit.cli build` / `pycc`. +2. Do not accept model-generated RTL as deliverable output. +3. Do not hand-edit generated RTL for final delivery. +4. If spec is ambiguous, ask the user for clarification before changing behavior. + +## Fixed Debug SOP (Seed -> Model -> PyCircuit -> RTL) + +When any testcase fails, follow this order: + +1. Record failing seed, testcase, and simulator. +2. Reproduce with the same seed and regenerate vectors. +3. Run model checks first; if model fails, fix model/spec alignment first. +4. If model passes, run PyCircuit checks. +5. If PyCircuit fails, fix `python/` and rebuild RTL. +6. Only debug RTL-level issues after model and PyCircuit both pass. +7. Re-verify failing case first, then run full regression. + +Use `pass/fail` wording in reports. + +## Regression Notes + +- Sanity and random vectors are seed-dependent and reproducible. +- Runtime vector loading (`$readmemh` + `+GEN_DIR`) is preferred over compile-time baked expected data. +- Default output paths: + - logs: `sim/logs/` + - waves: `sim/waves/` + +## `vld` to `vld_out` and Pipeline Depth + +- Enforce one-to-one mapping from sampled `vld` to `vld_out`. +- Keep fixed latency `L` across all modes. +- Keep internal pipeline stage count identical across all modes. +- Use full pipeline datapath; no independent FIFOs for reordering. +- Latency must be measured by **actual register count on real paths** (control and data), + not by stage naming conventions. +- Always verify `vld_out` path and `out0/out1` paths separately, then check alignment. + +## Power and Area Priority + +After functionality and logic-depth constraints are satisfied: + +1. Reduce dynamic power as primary priority. +2. Reduce area as secondary priority. + +If area and dynamic power conflict, prioritize dynamic power. + +## PyCircuit Structure Requirements + +1. Stage boundaries must be explicit and reviewable. +2. Keep submodules split into separate files. +3. Keep each submodule core logic around 200 lines or less when possible. +4. Keep top-level focused on stage orchestration and alignment. +5. Control and datapath must advance at matching stage depth. 6. Pure combinational submodules should not have `clk`/`rst` ports. If a PyCircuit hierarchy API forces these ports on a combinational submodule, treat that as a framework limitation to report, not as a normal coding pattern to copy. -## Mandatory Stage Coding Contract - -Top-level coding must be explicit: - -`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> combN -> regN -> output` - -Rules: - -1. Stage boundaries must be visible at top-level. -2. Each stage must define combinational work before register transfer. -3. Datapath and control-path must both be reviewable per stage. -4. `vld/mode/enable/select` control signals must stay aligned with payload. -5. Do not hide full pipeline register chains inside opaque helper loops. - +## Mandatory Stage Coding Contract + +Top-level coding must be explicit: + +`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> combN -> regN -> output` + +Rules: + +1. Stage boundaries must be visible at top-level. +2. Each stage must define combinational work before register transfer. +3. Datapath and control-path must both be reviewable per stage. +4. `vld/mode/enable/select` control signals must stay aligned with payload. +5. Do not hide full pipeline register chains inside opaque helper loops. + diff --git a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md index 480e484..5e44d6b 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md @@ -1,159 +1,159 @@ ---- -name: pe-int-pycircuiteval-flow -description: Unified PE_INT flow using PyCircuitEval. Use when implementing PE_INT from spec, generating RTL from PyCircuit, and running model/tb/tb_rtl validation. ---- - -# PE_INT x PyCircuitEval Unified Flow - -This skill standardizes PE_INT flow across sessions and machines: - -- Single spec source: `docs/spec.md` -- Implementation language: PyCircuit frontend -- Deliverable RTL source: PyCircuit build (`pycircuit.cli build` / `pycc`) -- Verification layers: - - `model/`: golden/reference and model regressions - - `tb/`: PyCircuit test flow - - `tb_rtl/`: RTL-specific simulation flow - -## 0) When to Use - -Enable this skill when the user asks to: - -- implement PE_INT from `spec.md` -- generate RTL from PyCircuit source -- add testbench/regression coverage -- reproduce PE_INT flow on another machine - -## 1) Source-of-Truth and Forbidden Actions - -1. `docs/spec.md` is the only behavior contract. -2. Do not handwrite deliverable RTL. -3. Do not accept model-generated RTL as final deliverable. -4. If implementation conflicts with spec, fix implementation (do not silently rewrite spec). - -## 2) Fallback If Profile Is Missing - -If no existing PyCircuitEval profile is available on a fresh machine/session: - -1. Learn latest PyCircuit flow from `LinxISA/pyCircuit`. -2. Confirm understanding of: - - module/circuit structure - - `pycircuit.cli build` / `pycc` flow - - minimal device+tb compile/run pattern -3. Then start PE_INT implementation. - -## 3) Standard PE_INT Flow (Fixed Order) - -### Step A: Spec Checklist - -Extract executable checks from `docs/spec.md`: - -- top-level ports and widths -- mode 2a/2b/2c/2d math semantics -- fixed `vld -> vld_out` mapping and latency -- cross-mode stage consistency -- mode-2a `out1` stability policy - -### Step B: Implement in PyCircuit, Then Build RTL - -1. Implement in `python/`. -2. Build through `pycircuit.cli build` / `pycc`. -3. After each build, sync deliverable RTL artifacts from the build output tree into `rtl/build/`. -4. Refresh `filelist/pe_int.f` after each sync so simulations consume the latest deliverable set. -5. Do not manually patch final RTL deliverables. -6. Use uppercase Verilog/PyCircuit module identifiers for deliverable RTL modules (for example `PE_INT`). -7. Use lowercase snake_case filenames for RTL deliverables (for example `pe_int.v`). - -### Step B.1: PyCircuit Structure Rules - -1. Keep pipeline stage boundaries explicit (`*_s0/*_s1/...` style). -2. Keep submodules separated under `python/pe_int/`. -3. Keep submodule core logic around 200 lines or less when practical. -4. Keep top-level focused on stage connection/alignment. -5. Keep control-path and datapath depth-aligned. +--- +name: pe-int-pycircuiteval-flow +description: Unified PE_INT flow using PyCircuitEval. Use when implementing PE_INT from spec, generating RTL from PyCircuit, and running model/tb/tb_rtl validation. +--- + +# PE_INT x PyCircuitEval Unified Flow + +This skill standardizes PE_INT flow across sessions and machines: + +- Single spec source: `docs/spec.md` +- Implementation language: PyCircuit frontend +- Deliverable RTL source: PyCircuit build (`pycircuit.cli build` / `pycc`) +- Verification layers: + - `model/`: golden/reference and model regressions + - `tb/`: PyCircuit test flow + - `tb_rtl/`: RTL-specific simulation flow + +## 0) When to Use + +Enable this skill when the user asks to: + +- implement PE_INT from `spec.md` +- generate RTL from PyCircuit source +- add testbench/regression coverage +- reproduce PE_INT flow on another machine + +## 1) Source-of-Truth and Forbidden Actions + +1. `docs/spec.md` is the only behavior contract. +2. Do not handwrite deliverable RTL. +3. Do not accept model-generated RTL as final deliverable. +4. If implementation conflicts with spec, fix implementation (do not silently rewrite spec). + +## 2) Fallback If Profile Is Missing + +If no existing PyCircuitEval profile is available on a fresh machine/session: + +1. Learn latest PyCircuit flow from `LinxISA/pyCircuit`. +2. Confirm understanding of: + - module/circuit structure + - `pycircuit.cli build` / `pycc` flow + - minimal device+tb compile/run pattern +3. Then start PE_INT implementation. + +## 3) Standard PE_INT Flow (Fixed Order) + +### Step A: Spec Checklist + +Extract executable checks from `docs/spec.md`: + +- top-level ports and widths +- mode 2a/2b/2c/2d math semantics +- fixed `vld -> vld_out` mapping and latency +- cross-mode stage consistency +- mode-2a `out1` stability policy + +### Step B: Implement in PyCircuit, Then Build RTL + +1. Implement in `python/`. +2. Build through `pycircuit.cli build` / `pycc`. +3. After each build, sync deliverable RTL artifacts from the build output tree into `rtl/build/`. +4. Refresh `filelist/pe_int.f` after each sync so simulations consume the latest deliverable set. +5. Do not manually patch final RTL deliverables. +6. Use uppercase Verilog/PyCircuit module identifiers for deliverable RTL modules (for example `PE_INT`). +7. Use lowercase snake_case filenames for RTL deliverables (for example `pe_int.v`). + +### Step B.1: PyCircuit Structure Rules + +1. Keep pipeline stage boundaries explicit (`*_s0/*_s1/...` style). +2. Keep submodules separated under `python/pe_int/`. +3. Keep submodule core logic around 200 lines or less when practical. +4. Keep top-level focused on stage connection/alignment. +5. Keep control-path and datapath depth-aligned. 6. Pure combinational submodules should not expose or propagate `clk`/`rst`. Only stateful submodules should carry clock/reset ports; if a PyCircuit API forces clock/reset on a combinational hierarchy boundary, document it as a framework limitation and avoid adding internal logic that depends on them. -### Step B.2: Mandatory Stage Contract - -Top-level must be reviewable as: - -`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> output` - -No hidden full register-chain helper loops. - -### Step C: Build Verification Assets - -- `model/`: math + timing model regression -- `tb/`: PyCircuit testbench comparison flow -- Validate: - - one-to-one valid mapping - - fixed latency and cross-mode consistency - - no bubble under full-pipeline working window - -### Step C.1: Latency Counting Rule (Mandatory) - -When checking latency / stage counts, always count the **actual number of -registers on the real signal path** in generated RTL. - -Do **not** infer latency only from stage naming (`s0/s1/...`) or comment labels. - -Required checks: - -1. Count register depth separately for control (`vld_out`) and data (`out0/out1`). -2. Confirm control/data path depths are aligned at output boundary. -3. If mismatch exists, report effective latency based on register count. - -### Step D (Optional): RTL Simulator Validation - -Only run this step after user confirms explicitly: - -1. Build RTL from PyCircuit source. -2. Run `tb_rtl/` testcases on both `iverilog` and `verilator`. -3. Report pass/fail and key outputs. - -## 4) Current Vector Baseline - -Current project baseline: - -- `tc_mode2a_sanity`: 1000 -- `tc_mode2b_sanity`: 1000 -- `tc_mode2c_sanity`: 1000 -- `tc_mode2d_sanity`: 1000 -- `tc_mode_switch_random`: 1000 - -Simulation script baseline: - -- multi-seed runs supported (default 10) -- runtime vector loading via `+GEN_DIR` -- logs: `sim/logs//...` -- waves: `sim/waves//...` - -## 5) Acceptance Checklist - -All of the following must pass: - -1. PyCircuit source can reproducibly rebuild RTL. -2. Deliverable RTL is generated by PyCircuit/pycc, not handwritten. -3. `model/` and `tb/` regressions pass. -4. README documents: - - build commands - - test commands - - fixed latency/alignment behavior - -If optional Step D is approved: - -- `tb_rtl/` testcases run successfully -- `iverilog` passes -- `verilator` passes - -## 6) Fixed Debug SOP - -On fail, always use: - -`Seed -> Model -> PyCircuit -> RTL` - -No step skipping. - +### Step B.2: Mandatory Stage Contract + +Top-level must be reviewable as: + +`input -> comb0 -> reg0 -> comb1 -> reg1 -> ... -> output` + +No hidden full register-chain helper loops. + +### Step C: Build Verification Assets + +- `model/`: math + timing model regression +- `tb/`: PyCircuit testbench comparison flow +- Validate: + - one-to-one valid mapping + - fixed latency and cross-mode consistency + - no bubble under full-pipeline working window + +### Step C.1: Latency Counting Rule (Mandatory) + +When checking latency / stage counts, always count the **actual number of +registers on the real signal path** in generated RTL. + +Do **not** infer latency only from stage naming (`s0/s1/...`) or comment labels. + +Required checks: + +1. Count register depth separately for control (`vld_out`) and data (`out0/out1`). +2. Confirm control/data path depths are aligned at output boundary. +3. If mismatch exists, report effective latency based on register count. + +### Step D (Optional): RTL Simulator Validation + +Only run this step after user confirms explicitly: + +1. Build RTL from PyCircuit source. +2. Run `tb_rtl/` testcases on both `iverilog` and `verilator`. +3. Report pass/fail and key outputs. + +## 4) Current Vector Baseline + +Current project baseline: + +- `tc_mode2a_sanity`: 1000 +- `tc_mode2b_sanity`: 1000 +- `tc_mode2c_sanity`: 1000 +- `tc_mode2d_sanity`: 1000 +- `tc_mode_switch_random`: 1000 + +Simulation script baseline: + +- multi-seed runs supported (default 10) +- runtime vector loading via `+GEN_DIR` +- logs: `sim/logs//...` +- waves: `sim/waves//...` + +## 5) Acceptance Checklist + +All of the following must pass: + +1. PyCircuit source can reproducibly rebuild RTL. +2. Deliverable RTL is generated by PyCircuit/pycc, not handwritten. +3. `model/` and `tb/` regressions pass. +4. README documents: + - build commands + - test commands + - fixed latency/alignment behavior + +If optional Step D is approved: + +- `tb_rtl/` testcases run successfully +- `iverilog` passes +- `verilator` passes + +## 6) Fixed Debug SOP + +On fail, always use: + +`Seed -> Model -> PyCircuit -> RTL` + +No step skipping. + diff --git a/designs/PE_INT/.gitignore b/designs/PE_INT/.gitignore index 9ead86f..6bde6fe 100644 --- a/designs/PE_INT/.gitignore +++ b/designs/PE_INT/.gitignore @@ -1,27 +1,32 @@ -# Tool-generated outputs -build/ -obj_dir/ -sim/logs/ -sim/waves/ - -# Simulation artifacts -*.vcd -*.fst -*.vpd -*.wdb -*.log -*.out - -# Python cache / env -__pycache__/ -*.pyc -.venv/ -venv/ - -# Generated testcase vectors (runtime-loaded) -tb_rtl/case/generated/*.mem -tb_rtl/case/generated/*_sizes.vh - -# OS/editor noise -.DS_Store -Thumbs.db +# Tool-generated outputs +build/ +obj_dir/ +sim/logs/ +sim/waves/ + +# Deliverable RTL snapshots are generated but intentionally versioned. +!rtl/ +!rtl/build/ +!rtl/build/*.v + +# Simulation artifacts +*.vcd +*.fst +*.vpd +*.wdb +*.log +*.out + +# Python cache / env +__pycache__/ +*.pyc +.venv/ +venv/ + +# Generated testcase vectors (runtime-loaded) +tb_rtl/case/generated/*.mem +tb_rtl/case/generated/*_sizes.vh + +# OS/editor noise +.DS_Store +Thumbs.db diff --git a/designs/PE_INT/filelist/pe_int.f b/designs/PE_INT/filelist/pe_int.f index 3f1fe44..20c1ef2 100644 --- a/designs/PE_INT/filelist/pe_int.f +++ b/designs/PE_INT/filelist/pe_int.f @@ -1,3 +1,4 @@ $PE_INT/rtl/build/pyc_primitives.v -$PE_INT/rtl/build/pe_int_wallace_dot8_tree.v +$PE_INT/rtl/build/pe_int_wallace_dot8_tree_w16.v +$PE_INT/rtl/build/pe_int_wallace_dot8_tree_w19.v $PE_INT/rtl/build/pe_int.v diff --git a/designs/PE_INT/model/test_pe_int.py b/designs/PE_INT/model/test_pe_int.py index 9bcce9d..47498a0 100644 --- a/designs/PE_INT/model/test_pe_int.py +++ b/designs/PE_INT/model/test_pe_int.py @@ -1,178 +1,178 @@ -from __future__ import annotations - -import random -import sys -import unittest -from pathlib import Path - -MODEL_DIR = Path(__file__).resolve().parent -sys.path.insert(0, str(MODEL_DIR)) - +from __future__ import annotations + +import random +import sys +import unittest +from pathlib import Path + +MODEL_DIR = Path(__file__).resolve().parent +sys.path.insert(0, str(MODEL_DIR)) + from pe_int_pycircuit_eval import DEFAULT_PIPELINE_L, PEIntModel -from ref_model import ( - MODE_2A, - MODE_2B, - MODE_2C, - MODE_2D, - compute_transaction, - pack_s4x8_to_40, - pack_s5x8_to_40, - pack_s5x16_to_80, - pack_s8x8_to_laneword, -) - - -def _rand_s(width: int) -> int: - lo = -(1 << (width - 1)) - hi = (1 << (width - 1)) - 1 - return random.randint(lo, hi) - - -def _make_txn(mode: int) -> tuple[int, int, int, tuple[int, int], tuple[int, int], tuple[int, int]]: - if mode == MODE_2A: - a = [_rand_s(8) for _ in range(8)] - b = [_rand_s(8) for _ in range(8)] - return ( - pack_s8x8_to_laneword(a), - pack_s8x8_to_laneword(b), - 0, - (0, 0), - (0, 0), - (0, 0), - ) - if mode == MODE_2B: - a = [_rand_s(8) for _ in range(8)] - b0 = [_rand_s(4) for _ in range(8)] - b1 = [_rand_s(4) for _ in range(8)] - b = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) - return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) - if mode == MODE_2D: - a = [_rand_s(8) for _ in range(8)] - b0 = [_rand_s(5) for _ in range(8)] - b1 = [_rand_s(5) for _ in range(8)] - b = pack_s5x8_to_40(b0) | (pack_s5x8_to_40(b1) << 40) - return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) - # MODE_2C - a = [_rand_s(5) for _ in range(16)] - b0 = [_rand_s(5) for _ in range(16)] - b1 = [_rand_s(5) for _ in range(16)] - e1a = (random.randint(0, 1), random.randint(0, 1)) - e1b0 = (random.randint(0, 1), random.randint(0, 1)) - e1b1 = (random.randint(0, 1), random.randint(0, 1)) - return ( - pack_s5x16_to_80(a), - pack_s5x16_to_80(b0), - pack_s5x16_to_80(b1), - e1a, - e1b0, - e1b1, - ) - - -class TestPEIntModel(unittest.TestCase): - def setUp(self) -> None: - random.seed(11) - - def test_mode_math_direct(self) -> None: - for mode in (MODE_2A, MODE_2B, MODE_2C, MODE_2D): - for _ in range(40): - a, b, b1, e1a, e1b0, e1b1 = _make_txn(mode) - got = compute_transaction(mode, a, b, b1, e1a, e1b0, e1b1) - # smoke checks on bounded output widths - self.assertGreaterEqual(got.out0_19, -(1 << 18)) - self.assertLessEqual(got.out0_19, (1 << 18) - 1) - self.assertGreaterEqual(got.out1_16, -(1 << 15)) - self.assertLessEqual(got.out1_16, (1 << 15) - 1) - - def test_pipeline_alignment_and_mode_switch(self) -> None: +from ref_model import ( + MODE_2A, + MODE_2B, + MODE_2C, + MODE_2D, + compute_transaction, + pack_s4x8_to_40, + pack_s5x8_to_40, + pack_s5x16_to_80, + pack_s8x8_to_laneword, +) + + +def _rand_s(width: int) -> int: + lo = -(1 << (width - 1)) + hi = (1 << (width - 1)) - 1 + return random.randint(lo, hi) + + +def _make_txn(mode: int) -> tuple[int, int, int, tuple[int, int], tuple[int, int], tuple[int, int]]: + if mode == MODE_2A: + a = [_rand_s(8) for _ in range(8)] + b = [_rand_s(8) for _ in range(8)] + return ( + pack_s8x8_to_laneword(a), + pack_s8x8_to_laneword(b), + 0, + (0, 0), + (0, 0), + (0, 0), + ) + if mode == MODE_2B: + a = [_rand_s(8) for _ in range(8)] + b0 = [_rand_s(4) for _ in range(8)] + b1 = [_rand_s(4) for _ in range(8)] + b = pack_s4x8_to_40(b0) | (pack_s4x8_to_40(b1) << 40) + return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) + if mode == MODE_2D: + a = [_rand_s(8) for _ in range(8)] + b0 = [_rand_s(5) for _ in range(8)] + b1 = [_rand_s(5) for _ in range(8)] + b = pack_s5x8_to_40(b0) | (pack_s5x8_to_40(b1) << 40) + return (pack_s8x8_to_laneword(a), b, 0, (0, 0), (0, 0), (0, 0)) + # MODE_2C + a = [_rand_s(5) for _ in range(16)] + b0 = [_rand_s(5) for _ in range(16)] + b1 = [_rand_s(5) for _ in range(16)] + e1a = (random.randint(0, 1), random.randint(0, 1)) + e1b0 = (random.randint(0, 1), random.randint(0, 1)) + e1b1 = (random.randint(0, 1), random.randint(0, 1)) + return ( + pack_s5x16_to_80(a), + pack_s5x16_to_80(b0), + pack_s5x16_to_80(b1), + e1a, + e1b0, + e1b1, + ) + + +class TestPEIntModel(unittest.TestCase): + def setUp(self) -> None: + random.seed(11) + + def test_mode_math_direct(self) -> None: + for mode in (MODE_2A, MODE_2B, MODE_2C, MODE_2D): + for _ in range(40): + a, b, b1, e1a, e1b0, e1b1 = _make_txn(mode) + got = compute_transaction(mode, a, b, b1, e1a, e1b0, e1b1) + # smoke checks on bounded output widths + self.assertGreaterEqual(got.out0_19, -(1 << 18)) + self.assertLessEqual(got.out0_19, (1 << 18) - 1) + self.assertGreaterEqual(got.out1_16, -(1 << 15)) + self.assertLessEqual(got.out1_16, (1 << 15) - 1) + + def test_pipeline_alignment_and_mode_switch(self) -> None: dut = PEIntModel() - expected: list[tuple[int, int, int, int]] = [] # cycle, mode, out0, out1 - out_hits = 0 - - for cycle in range(120): - vld = random.randint(0, 1) - mode = random.choice((MODE_2A, MODE_2B, MODE_2C, MODE_2D)) - a, b, b1, e1a, e1b0, e1b1 = _make_txn(mode) - - if vld: - exp = compute_transaction(mode, a, b, b1, e1a, e1b0, e1b1) - expected.append((cycle + DEFAULT_PIPELINE_L, mode, exp.out0_19, exp.out1_16)) - - step = dut.step( - rst_n=1, - vld=vld, - mode=mode, - a=a, - b=b, - b1=b1, - e1_a=e1a, - e1_b0=e1b0, - e1_b1=e1b1, - ) - - if step.vld_out: - self.assertTrue(expected, "vld_out should map to one expected transaction") - due_cycle, due_mode, exp0, exp1 = expected.pop(0) - self.assertEqual(cycle, due_cycle) - self.assertEqual(step.out0, exp0) - if due_mode != MODE_2A: - self.assertEqual(step.out1, exp1) - out_hits += 1 - - # Drain pipeline - for cycle in range(120, 130): - step = dut.step( - rst_n=1, - vld=0, - mode=MODE_2A, - a=0, - b=0, - b1=0, - e1_a=(0, 0), - e1_b0=(0, 0), - e1_b1=(0, 0), - ) - if step.vld_out: - due_cycle, due_mode, exp0, exp1 = expected.pop(0) - self.assertEqual(cycle, due_cycle) - self.assertEqual(step.out0, exp0) - if due_mode != MODE_2A: - self.assertEqual(step.out1, exp1) - out_hits += 1 - self.assertEqual(len(expected), 0) - self.assertGreater(out_hits, 0) - - def test_mode2a_out1_no_toggle(self) -> None: + expected: list[tuple[int, int, int, int]] = [] # cycle, mode, out0, out1 + out_hits = 0 + + for cycle in range(120): + vld = random.randint(0, 1) + mode = random.choice((MODE_2A, MODE_2B, MODE_2C, MODE_2D)) + a, b, b1, e1a, e1b0, e1b1 = _make_txn(mode) + + if vld: + exp = compute_transaction(mode, a, b, b1, e1a, e1b0, e1b1) + expected.append((cycle + DEFAULT_PIPELINE_L, mode, exp.out0_19, exp.out1_16)) + + step = dut.step( + rst_n=1, + vld=vld, + mode=mode, + a=a, + b=b, + b1=b1, + e1_a=e1a, + e1_b0=e1b0, + e1_b1=e1b1, + ) + + if step.vld_out: + self.assertTrue(expected, "vld_out should map to one expected transaction") + due_cycle, due_mode, exp0, exp1 = expected.pop(0) + self.assertEqual(cycle, due_cycle) + self.assertEqual(step.out0, exp0) + if due_mode != MODE_2A: + self.assertEqual(step.out1, exp1) + out_hits += 1 + + # Drain pipeline + for cycle in range(120, 130): + step = dut.step( + rst_n=1, + vld=0, + mode=MODE_2A, + a=0, + b=0, + b1=0, + e1_a=(0, 0), + e1_b0=(0, 0), + e1_b1=(0, 0), + ) + if step.vld_out: + due_cycle, due_mode, exp0, exp1 = expected.pop(0) + self.assertEqual(cycle, due_cycle) + self.assertEqual(step.out0, exp0) + if due_mode != MODE_2A: + self.assertEqual(step.out1, exp1) + out_hits += 1 + self.assertEqual(len(expected), 0) + self.assertGreater(out_hits, 0) + + def test_mode2a_out1_no_toggle(self) -> None: dut = PEIntModel() - - # First, drive one non-2a sample to set out1 base. - a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2B) - dut.step(rst_n=1, vld=1, mode=MODE_2B, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) - for _ in range(DEFAULT_PIPELINE_L + 1): - dut.step(rst_n=1, vld=0, mode=MODE_2A, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) - base_out1 = dut.out1 - - # Then continuous mode2a valid traffic; out1 should hold. - for _ in range(30): - a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2A) - dut.step(rst_n=1, vld=1, mode=MODE_2A, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) - self.assertEqual(dut.out1, base_out1) - - def test_async_reset_clears_pipeline(self) -> None: + + # First, drive one non-2a sample to set out1 base. + a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2B) + dut.step(rst_n=1, vld=1, mode=MODE_2B, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) + for _ in range(DEFAULT_PIPELINE_L + 1): + dut.step(rst_n=1, vld=0, mode=MODE_2A, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) + base_out1 = dut.out1 + + # Then continuous mode2a valid traffic; out1 should hold. + for _ in range(30): + a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2A) + dut.step(rst_n=1, vld=1, mode=MODE_2A, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) + self.assertEqual(dut.out1, base_out1) + + def test_async_reset_clears_pipeline(self) -> None: dut = PEIntModel() - # inject a valid sample - a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2D) - dut.step(rst_n=1, vld=1, mode=MODE_2D, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) - # asynchronous reset assertion - res = dut.step(rst_n=0, vld=1, mode=MODE_2D, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) - self.assertEqual(res.vld_out, 0) - self.assertEqual(res.out0, 0) - self.assertEqual(res.out1, 0) - # release reset and keep idle, no stale output should appear - for _ in range(DEFAULT_PIPELINE_L + 2): - res = dut.step(rst_n=1, vld=0, mode=MODE_2A, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) - self.assertEqual(res.vld_out, 0) - - -if __name__ == "__main__": - unittest.main() + # inject a valid sample + a, b, b1, e1a, e1b0, e1b1 = _make_txn(MODE_2D) + dut.step(rst_n=1, vld=1, mode=MODE_2D, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) + # asynchronous reset assertion + res = dut.step(rst_n=0, vld=1, mode=MODE_2D, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) + self.assertEqual(res.vld_out, 0) + self.assertEqual(res.out0, 0) + self.assertEqual(res.out1, 0) + # release reset and keep idle, no stale output should appear + for _ in range(DEFAULT_PIPELINE_L + 2): + res = dut.step(rst_n=1, vld=0, mode=MODE_2A, a=0, b=0, b1=0, e1_a=(0, 0), e1_b0=(0, 0), e1_b1=(0, 0)) + self.assertEqual(res.vld_out, 0) + + +if __name__ == "__main__": + unittest.main() diff --git a/designs/PE_INT/python/build.py b/designs/PE_INT/python/build.py index ed5de26..0e3402a 100644 --- a/designs/PE_INT/python/build.py +++ b/designs/PE_INT/python/build.py @@ -19,6 +19,12 @@ "pyc_cdc_sync": "PYC_CDC_SYNC", } +_PURE_COMB_MODULES_WITH_FORCED_CLOCK_RESET = ( + "PE_INT_WALLACE_DOT8_TREE", + "PE_INT_WALLACE_DOT8_TREE_W16", + "PE_INT_WALLACE_DOT8_TREE_W19", +) + def _normalize_module_identifier_case(verilog_text: str) -> str: """Use uppercase module identifiers in deliverable RTL while keeping net names intact.""" @@ -132,6 +138,30 @@ def _insert_internal_reset_wire(top_text: str, module_name: str = "PE_INT") -> s return top_text[:insert_idx] + reset_decl + top_text[insert_idx:] +def _drop_pure_comb_clock_reset_ports(verilog_text: str, module_name: str) -> str: + """Remove forced hierarchy clk/rst ports from known pure combinational modules.""" + if re.search(rf"\bmodule\s+{re.escape(module_name)}\b", verilog_text): + verilog_text = re.sub( + r"^\s*input\s+clk,\s*\n\s*input\s+rst,\s*\n", + "", + verilog_text, + count=1, + flags=re.MULTILINE, + ) + + instance_re = re.compile( + rf"(\b{re.escape(module_name)}\s+\w+\s*\(\n)(.*?)(\n\);)", + flags=re.DOTALL, + ) + + def strip_instance_ports(match: re.Match[str]) -> str: + body = re.sub(r"^\s*\.clk\(clk\),\s*\n", "", match.group(2), flags=re.MULTILINE) + body = re.sub(r"^\s*\.rst\(rst\),\s*\n", "", body, flags=re.MULTILINE) + return match.group(1) + body + match.group(3) + + return instance_re.sub(strip_instance_ports, verilog_text) + + def _load_current_design_name(repo_root: Path) -> str: py_dir = repo_root / "python" if str(py_dir) not in sys.path: @@ -172,6 +202,8 @@ def _sync_generated_rtl(repo_root: Path, out_dir: Path, design_name: str) -> Non if re.search(r"^\s*input\s+rst,\s*$", top_text, flags=re.MULTILINE): top_text = re.sub(r"^\s*input\s+rst,\s*$\n?", "", top_text, count=1, flags=re.MULTILINE) top_text = _insert_internal_reset_wire(top_text) + for module_name in _PURE_COMB_MODULES_WITH_FORCED_CLOCK_RESET: + top_text = _drop_pure_comb_clock_reset_ports(top_text, module_name) dst_top.write_text(_normalize_module_identifier_case(top_text), encoding="utf-8") primitives_text = primitives_verilog.read_text(encoding="utf-8") @@ -186,6 +218,9 @@ def _sync_generated_rtl(repo_root: Path, out_dir: Path, design_name: str) -> Non continue dst_module = rtl_dir / f"{module_dir.name.lower()}.v" module_text = module_verilog.read_text(encoding="utf-8") + if module_dir.name in _PURE_COMB_MODULES_WITH_FORCED_CLOCK_RESET: + module_text = _drop_pure_comb_clock_reset_ports(module_text, "PE_INT_WALLACE_DOT8_TREE") + module_text = _drop_pure_comb_clock_reset_ports(module_text, module_dir.name) dst_module.write_text(_normalize_module_identifier_case(module_text), encoding="utf-8") dst_submodules.append(dst_module) diff --git a/designs/PE_INT/python/pe_int/decode.py b/designs/PE_INT/python/pe_int/decode.py index 32808d4..518379e 100644 --- a/designs/PE_INT/python/pe_int/decode.py +++ b/designs/PE_INT/python/pe_int/decode.py @@ -26,32 +26,32 @@ def lane5(word, idx: int): return wire_of(word)[lo : lo + 5] -def decode_s8_from_lane_word(word, idx: int): +def decode_s8_from_lane_word(word, idx: int, *, bits: int = 32): lo_lane = lane5(word, 2 * idx) hi_lane = lane5(word, 2 * idx + 1) lo4 = wire_of(lo_lane)[1:5] hi4 = wire_of(hi_lane)[1:5] raw8 = cat(hi4, lo4) - return sext(raw8, 32) + return sext(raw8, bits) -def decode_s4_from_40(word40, idx: int): +def decode_s4_from_40(word40, idx: int, *, bits: int = 32): lane = wire_of(word40)[5 * idx : 5 * idx + 5] raw4 = wire_of(lane)[1:5] - return sext(raw4, 32) + return sext(raw4, bits) -def decode_s4_hi_from_80(word80, idx: int): +def decode_s4_hi_from_80(word80, idx: int, *, bits: int = 32): lane = wire_of(word80)[40 + 5 * idx : 40 + 5 * idx + 5] raw4 = wire_of(lane)[1:5] - return sext(raw4, 32) + return sext(raw4, bits) -def decode_s5(word, idx: int): +def decode_s5(word, idx: int, *, bits: int = 32): raw = wire_of(word)[5 * idx : 5 * idx + 5] - return sext(raw, 32) + return sext(raw, bits) -def decode_s5_hi_from_80(word80, idx: int): +def decode_s5_hi_from_80(word80, idx: int, *, bits: int = 32): raw = wire_of(word80)[40 + 5 * idx : 40 + 5 * idx + 5] - return sext(raw, 32) + return sext(raw, bits) diff --git a/designs/PE_INT/python/pe_int/lane_mac.py b/designs/PE_INT/python/pe_int/lane_mac.py index 7e3402b..1ff12b1 100644 --- a/designs/PE_INT/python/pe_int/lane_mac.py +++ b/designs/PE_INT/python/pe_int/lane_mac.py @@ -4,6 +4,7 @@ from pycircuit import cas, cat, mux, wire_of +from .constants import OUT0_W, OUT1_W from .decode import zext @@ -101,6 +102,20 @@ def wallace_dot8_tree(m, domain, *, inputs: dict | None = None, width: int = RED wallace_dot8_tree.__pycircuit_name__ = "PE_INT_WALLACE_DOT8_TREE" +def wallace_dot8_tree_w19(m, domain, *, inputs: dict | None = None, prefix: str = "wallace_dot8_w19"): + return wallace_dot8_tree(m, domain, inputs=inputs, width=OUT0_W, prefix=prefix) + + +wallace_dot8_tree_w19.__pycircuit_name__ = "PE_INT_WALLACE_DOT8_TREE_W19" + + +def wallace_dot8_tree_w16(m, domain, *, inputs: dict | None = None, prefix: str = "wallace_dot8_w16"): + return wallace_dot8_tree(m, domain, inputs=inputs, width=OUT1_W, prefix=prefix) + + +wallace_dot8_tree_w16.__pycircuit_name__ = "PE_INT_WALLACE_DOT8_TREE_W16" + + def dot8_reduce(products: Sequence[object]): return _wallace_dot8_reduce(products) @@ -124,12 +139,11 @@ def shift_scale_x1_x2_x4(value, shift2b): ) -def select_one_hot4(sel0, sel1, sel2, sel3, cand0, cand1, cand2, cand3): +def select_one_hot4(sel0, sel1, sel2, cand0, cand1, cand2, cand3): """ One-hot mode selection. Use muxes instead of boolean-masked multiplication so PyCircuit does not insert balancing registers in comb3. """ - _ = sel3 return wire_of(sel0)._select_internal( wire_of(cand0), wire_of(sel1)._select_internal( @@ -139,9 +153,11 @@ def select_one_hot4(sel0, sel1, sel2, sel3, cand0, cand1, cand2, cand3): ) -def sum_shift_pair(lo, hi, e1_a, e1_b): +def sum_shift_pair(lo, hi, e1_a, e1_b, *, width: int = REDUCE_W): e1_a_w = wire_of(e1_a) e1_b_w = wire_of(e1_b) sh_lo = zext(e1_a_w[0:1], 2) + zext(e1_b_w[0:1], 2) sh_hi = zext(e1_a_w[1:2], 2) + zext(e1_b_w[1:2], 2) - return shift_scale_x1_x2_x4(lo, sh_lo) + shift_scale_x1_x2_x4(hi, sh_hi) + lo_scaled = wire_of(shift_scale_x1_x2_x4(wire_of(lo)[0:width], sh_lo))[0:width] + hi_scaled = wire_of(shift_scale_x1_x2_x4(wire_of(hi)[0:width], sh_hi))[0:width] + return lo_scaled + hi_scaled diff --git a/designs/PE_INT/python/pe_int/mac_modes.py b/designs/PE_INT/python/pe_int/mac_modes.py index 684a2eb..d8cd221 100644 --- a/designs/PE_INT/python/pe_int/mac_modes.py +++ b/designs/PE_INT/python/pe_int/mac_modes.py @@ -2,8 +2,9 @@ from pycircuit import wire_of +from .constants import OUT0_W, OUT1_W from .decode import decode_s4_from_40, decode_s4_hi_from_80, decode_s5, decode_s5_hi_from_80, decode_s8_from_lane_word -from .lane_mac import booth_mul_signed, select_one_hot4, sum_shift_pair, wallace_dot8_tree +from .lane_mac import booth_mul_signed, select_one_hot4, sum_shift_pair, wallace_dot8_tree_w16, wallace_dot8_tree_w19 def _mode_one_hot(mode): @@ -31,24 +32,26 @@ def comb1_generate_products(a, b, b1): p2c1 = [] for lane_idx in range(8): - a8_i = decode_s8_from_lane_word(a, lane_idx) - b8_i = decode_s8_from_lane_word(b, lane_idx) - b4_0_i = decode_s4_from_40(b_lo40, lane_idx) - b4_1_i = decode_s4_hi_from_80(b, lane_idx) - b5_0_i = decode_s5(b_lo40, lane_idx) - b5_1_i = decode_s5_hi_from_80(b, lane_idx) - p2a.append(booth_mul_signed(a8_i, b8_i)) - p2b0.append(booth_mul_signed(a8_i, b4_0_i)) - p2b1.append(booth_mul_signed(a8_i, b4_1_i)) - p2d0.append(booth_mul_signed(a8_i, b5_0_i)) - p2d1.append(booth_mul_signed(a8_i, b5_1_i)) + a8_o0_i = decode_s8_from_lane_word(a, lane_idx, bits=OUT0_W) + a8_o1_i = decode_s8_from_lane_word(a, lane_idx, bits=OUT1_W) + b8_i = decode_s8_from_lane_word(b, lane_idx, bits=OUT0_W) + b4_0_i = decode_s4_from_40(b_lo40, lane_idx, bits=OUT0_W) + b4_1_i = decode_s4_hi_from_80(b, lane_idx, bits=OUT1_W) + b5_0_i = decode_s5(b_lo40, lane_idx, bits=OUT0_W) + b5_1_i = decode_s5_hi_from_80(b, lane_idx, bits=OUT1_W) + p2a.append(booth_mul_signed(a8_o0_i, b8_i)) + p2b0.append(booth_mul_signed(a8_o0_i, b4_0_i)) + p2b1.append(booth_mul_signed(a8_o1_i, b4_1_i)) + p2d0.append(booth_mul_signed(a8_o0_i, b5_0_i)) + p2d1.append(booth_mul_signed(a8_o1_i, b5_1_i)) for lane_idx in range(16): - a5_i = decode_s5(a, lane_idx) - b0_5_i = decode_s5(b, lane_idx) - b1_5_i = decode_s5(b1, lane_idx) - p2c0.append(booth_mul_signed(a5_i, b0_5_i)) - p2c1.append(booth_mul_signed(a5_i, b1_5_i)) + a5_o0_i = decode_s5(a, lane_idx, bits=OUT0_W) + a5_o1_i = decode_s5(a, lane_idx, bits=OUT1_W) + b0_5_i = decode_s5(b, lane_idx, bits=OUT0_W) + b1_5_i = decode_s5(b1, lane_idx, bits=OUT1_W) + p2c0.append(booth_mul_signed(a5_o0_i, b0_5_i)) + p2c1.append(booth_mul_signed(a5_o1_i, b1_5_i)) return { "p2a": p2a, @@ -61,10 +64,11 @@ def comb1_generate_products(a, b, b1): } -def _wallace_dot8(domain, products, *, prefix: str): +def _wallace_dot8(domain, products, *, width: int, prefix: str): + module = wallace_dot8_tree_w19 if width == OUT0_W else wallace_dot8_tree_w16 return domain.call( - wallace_dot8_tree, - inputs={f"in{idx}": product for idx, product in enumerate(products)}, + module, + inputs={f"in{idx}": wire_of(product)[0:width] for idx, product in enumerate(products)}, prefix=prefix, )["sum"] @@ -83,15 +87,15 @@ def comb2_reduce_products(domain, products): p2c0 = products["p2c0"] p2c1 = products["p2c1"] - s2a = _wallace_dot8(domain, p2a, prefix="pe_int_s2a_wallace") - s2b0 = _wallace_dot8(domain, p2b0, prefix="pe_int_s2b0_wallace") - s2b1 = _wallace_dot8(domain, p2b1, prefix="pe_int_s2b1_wallace") - s2d0 = _wallace_dot8(domain, p2d0, prefix="pe_int_s2d0_wallace") - s2d1 = _wallace_dot8(domain, p2d1, prefix="pe_int_s2d1_wallace") - s2c0_lo = _wallace_dot8(domain, p2c0[0:8], prefix="pe_int_s2c0_lo_wallace") - s2c0_hi = _wallace_dot8(domain, p2c0[8:16], prefix="pe_int_s2c0_hi_wallace") - s2c1_lo = _wallace_dot8(domain, p2c1[0:8], prefix="pe_int_s2c1_lo_wallace") - s2c1_hi = _wallace_dot8(domain, p2c1[8:16], prefix="pe_int_s2c1_hi_wallace") + s2a = _wallace_dot8(domain, p2a, width=OUT0_W, prefix="pe_int_s2a_wallace") + s2b0 = _wallace_dot8(domain, p2b0, width=OUT0_W, prefix="pe_int_s2b0_wallace") + s2b1 = _wallace_dot8(domain, p2b1, width=OUT1_W, prefix="pe_int_s2b1_wallace") + s2d0 = _wallace_dot8(domain, p2d0, width=OUT0_W, prefix="pe_int_s2d0_wallace") + s2d1 = _wallace_dot8(domain, p2d1, width=OUT1_W, prefix="pe_int_s2d1_wallace") + s2c0_lo = _wallace_dot8(domain, p2c0[0:8], width=OUT0_W, prefix="pe_int_s2c0_lo_wallace") + s2c0_hi = _wallace_dot8(domain, p2c0[8:16], width=OUT0_W, prefix="pe_int_s2c0_hi_wallace") + s2c1_lo = _wallace_dot8(domain, p2c1[0:8], width=OUT1_W, prefix="pe_int_s2c1_lo_wallace") + s2c1_hi = _wallace_dot8(domain, p2c1[8:16], width=OUT1_W, prefix="pe_int_s2c1_hi_wallace") return { "s2a": s2a, "s2b0": s2b0, @@ -105,33 +109,32 @@ def comb2_reduce_products(domain, products): } -def comb3_mode_merge(reduced, e1_a, e1_b0, e1_b1, *, is_2a, is_2b, is_2c, is_2d): +def comb3_mode_merge(reduced, e1_a, e1_b0, e1_b1, *, is_2a, is_2b, is_2c): """ DS §5.7: - 2c post-scale x1/x2/x4 - one-hot mode merge for out0_raw/out1_raw """ - s2c0 = sum_shift_pair(reduced["s2c0_lo"], reduced["s2c0_hi"], e1_a, e1_b0) - s2c1 = sum_shift_pair(reduced["s2c1_lo"], reduced["s2c1_hi"], e1_a, e1_b1) + s2c0 = sum_shift_pair(reduced["s2c0_lo"], reduced["s2c0_hi"], e1_a, e1_b0, width=OUT0_W) + s2c1 = sum_shift_pair(reduced["s2c1_lo"], reduced["s2c1_hi"], e1_a, e1_b1, width=OUT1_W) out0_raw = select_one_hot4( is_2a, is_2b, is_2c, - is_2d, - reduced["s2a"], - reduced["s2b0"], - s2c0, - reduced["s2d0"], + wire_of(reduced["s2a"])[0:OUT0_W], + wire_of(reduced["s2b0"])[0:OUT0_W], + wire_of(s2c0)[0:OUT0_W], + wire_of(reduced["s2d0"])[0:OUT0_W], ) + out1_zero = wire_of(reduced["s2b1"])[0:OUT1_W] & 0 out1_raw = select_one_hot4( is_2a, is_2b, is_2c, - is_2d, - reduced["s2a"] * 0, - reduced["s2b1"], - s2c1, - reduced["s2d1"], + out1_zero, + wire_of(reduced["s2b1"])[0:OUT1_W], + wire_of(s2c1)[0:OUT1_W], + wire_of(reduced["s2d1"])[0:OUT1_W], ) return out0_raw, out1_raw diff --git a/designs/PE_INT/python/pe_int/top.py b/designs/PE_INT/python/pe_int/top.py index d54f261..a51356c 100644 --- a/designs/PE_INT/python/pe_int/top.py +++ b/designs/PE_INT/python/pe_int/top.py @@ -3,13 +3,12 @@ from pathlib import Path try: - from pycircuit import CycleAwareCircuit, CycleAwareDomain, cas, compile_cycle_aware, mux, wire_of + from pycircuit import CycleAwareCircuit, CycleAwareDomain, cas, compile_cycle_aware, wire_of except ImportError: # pragma: no cover - allows local tests without pyCircuit. CycleAwareCircuit = object # type: ignore[assignment] CycleAwareDomain = object # type: ignore[assignment] cas = None # type: ignore[assignment] compile_cycle_aware = None # type: ignore[assignment] - mux = None # type: ignore[assignment] wire_of = None # type: ignore[assignment] from .constants import DEFAULT_PIPELINE_L, OUT0_W, OUT1_W, SPEC_LATENCY_L @@ -17,7 +16,7 @@ def _require_pycircuit() -> None: - if cas is None or compile_cycle_aware is None or wire_of is None or mux is None: + if cas is None or compile_cycle_aware is None or wire_of is None: raise RuntimeError( "pyCircuit is not installed. Please set PYTHONPATH according to README, " "or install LinxISA/pyCircuit frontend." @@ -62,7 +61,6 @@ def build( c0_is_2a = in_mode == 0 c0_is_2b = in_mode == 1 c0_is_2c = in_mode == 2 - c0_is_2d = in_mode == 3 # reg0: input capture boundary (cycle-aware sampled transaction). domain.next() @@ -70,7 +68,6 @@ def build( s0_is_2a = _reg_sig(domain, c0_is_2a, "pe_int_s0_is_2a") s0_is_2b = _reg_sig(domain, c0_is_2b, "pe_int_s0_is_2b") s0_is_2c = _reg_sig(domain, c0_is_2c, "pe_int_s0_is_2c") - s0_is_2d = _reg_sig(domain, c0_is_2d, "pe_int_s0_is_2d") s0_a = _reg_sig(domain, in_a, "pe_int_s0_a") s0_b = _reg_sig(domain, in_b, "pe_int_s0_b") s0_b1 = _reg_sig(domain, in_b1, "pe_int_s0_b1") @@ -87,7 +84,6 @@ def build( s1_is_2a = _reg_sig(domain, s0_is_2a, "pe_int_s1_is_2a") s1_is_2b = _reg_sig(domain, s0_is_2b, "pe_int_s1_is_2b") s1_is_2c = _reg_sig(domain, s0_is_2c, "pe_int_s1_is_2c") - s1_is_2d = _reg_sig(domain, s0_is_2d, "pe_int_s1_is_2d") s1_e1_a = _reg_sig(domain, s0_e1_a, "pe_int_s1_e1_a") s1_e1_b0 = _reg_sig(domain, s0_e1_b0, "pe_int_s1_e1_b0") s1_e1_b1 = _reg_sig(domain, s0_e1_b1, "pe_int_s1_e1_b1") @@ -110,15 +106,14 @@ def build( s2_is_2a = _reg_sig(domain, s1_is_2a, "pe_int_s2_is_2a") s2_is_2b = _reg_sig(domain, s1_is_2b, "pe_int_s2_is_2b") s2_is_2c = _reg_sig(domain, s1_is_2c, "pe_int_s2_is_2c") - s2_is_2d = _reg_sig(domain, s1_is_2d, "pe_int_s2_is_2d") s2_e1_a = _reg_sig(domain, s1_e1_a, "pe_int_s2_e1_a") s2_e1_b0 = _reg_sig(domain, s1_e1_b0, "pe_int_s2_e1_b0") s2_e1_b1 = _reg_sig(domain, s1_e1_b1, "pe_int_s2_e1_b1") - s2_s2a = _reg_sig(domain, c2_reduced["s2a"], "pe_int_s2_s2a") - s2_s2b0 = _reg_sig(domain, c2_reduced["s2b0"], "pe_int_s2_s2b0") - s2_s2b1 = _reg_sig(domain, c2_reduced["s2b1"], "pe_int_s2_s2b1") - s2_s2d0 = _reg_sig(domain, c2_reduced["s2d0"], "pe_int_s2_s2d0") - s2_s2d1 = _reg_sig(domain, c2_reduced["s2d1"], "pe_int_s2_s2d1") + s2_s2a = _reg_sig(domain, wire_of(c2_reduced["s2a"])[0:OUT0_W], "pe_int_s2_s2a") + s2_s2b0 = _reg_sig(domain, wire_of(c2_reduced["s2b0"])[0:OUT0_W], "pe_int_s2_s2b0") + s2_s2b1 = _reg_sig(domain, wire_of(c2_reduced["s2b1"])[0:OUT1_W], "pe_int_s2_s2b1") + s2_s2d0 = _reg_sig(domain, wire_of(c2_reduced["s2d0"])[0:OUT0_W], "pe_int_s2_s2d0") + s2_s2d1 = _reg_sig(domain, wire_of(c2_reduced["s2d1"])[0:OUT1_W], "pe_int_s2_s2d1") s2_s2c0_lo = _reg_sig(domain, c2_reduced["s2c0_lo"], "pe_int_s2_s2c0_lo") s2_s2c0_hi = _reg_sig(domain, c2_reduced["s2c0_hi"], "pe_int_s2_s2c0_hi") s2_s2c1_lo = _reg_sig(domain, c2_reduced["s2c1_lo"], "pe_int_s2_s2c1_lo") @@ -144,18 +139,14 @@ def build( is_2a=s2_is_2a, is_2b=s2_is_2b, is_2c=s2_is_2c, - is_2d=s2_is_2d, ) - c3_out0_raw = cas(domain, wire_of(c3_out0_raw), cycle=0) - c3_out1_raw = cas(domain, wire_of(c3_out1_raw), cycle=0) - c3_out0 = wire_of(c3_out0_raw)[0:OUT0_W] + c3_out0 = cas(domain, wire_of(c3_out0_raw)[0:OUT0_W], cycle=0) c3_out1 = wire_of(c3_out1_raw)[0:OUT1_W] # reg3/output commit: vld_out/out0/out1 from the same commit boundary. out1 = domain.state(width=OUT1_W, reset_value=0, name="pe_int_out1") - out1_commit = mux( - wire_of(s2_vld), - mux(wire_of(s2_is_2a), wire_of(out1), c3_out1), + out1_commit = wire_of(s2_vld)._select_internal( + wire_of(s2_is_2a)._select_internal(wire_of(out1), wire_of(c3_out1)), wire_of(out1), ) out1.set(out1_commit) diff --git a/designs/PE_INT/rtl/build/pe_int.v b/designs/PE_INT/rtl/build/pe_int.v index b1e81aa..f60f84d 100644 --- a/designs/PE_INT/rtl/build/pe_int.v +++ b/designs/PE_INT/rtl/build/pe_int.v @@ -21,9 +21,6 @@ wire rst; assign rst = ~rst_n; -wire [31:0] _v5_bal_1; // pyc.name="_v5_bal_1" -wire [31:0] _v5_bal_1__next; // pyc.name="_v5_bal_1__next" -wire [31:0] _v5_bal_2__next; // pyc.name="_v5_bal_2__next" wire [18:0] pe_int_out0; // pyc.name="pe_int_out0" wire [18:0] pe_int_out0__next; // pyc.name="pe_int_out0__next" wire [15:0] pe_int_out1; // pyc.name="pe_int_out1" @@ -48,8 +45,6 @@ wire pe_int_s0_is_2b; // pyc.name="pe_int_s0_is_2b" wire pe_int_s0_is_2b__next; // pyc.name="pe_int_s0_is_2b__next" wire pe_int_s0_is_2c; // pyc.name="pe_int_s0_is_2c" wire pe_int_s0_is_2c__next; // pyc.name="pe_int_s0_is_2c__next" -wire pe_int_s0_is_2d; // pyc.name="pe_int_s0_is_2d" -wire pe_int_s0_is_2d__next; // pyc.name="pe_int_s0_is_2d__next" wire pe_int_s0_vld; // pyc.name="pe_int_s0_vld" wire pe_int_s0_vld__next; // pyc.name="pe_int_s0_vld__next" wire [1:0] pe_int_s1_e1_a; // pyc.name="pe_int_s1_e1_a" @@ -64,151 +59,150 @@ wire pe_int_s1_is_2b; // pyc.name="pe_int_s1_is_2b" wire pe_int_s1_is_2b__next; // pyc.name="pe_int_s1_is_2b__next" wire pe_int_s1_is_2c; // pyc.name="pe_int_s1_is_2c" wire pe_int_s1_is_2c__next; // pyc.name="pe_int_s1_is_2c__next" -wire pe_int_s1_is_2d__next; // pyc.name="pe_int_s1_is_2d__next" -wire [31:0] pe_int_s1_p2a_0; // pyc.name="pe_int_s1_p2a_0" -wire [31:0] pe_int_s1_p2a_0__next; // pyc.name="pe_int_s1_p2a_0__next" -wire [31:0] pe_int_s1_p2a_1; // pyc.name="pe_int_s1_p2a_1" -wire [31:0] pe_int_s1_p2a_1__next; // pyc.name="pe_int_s1_p2a_1__next" -wire [31:0] pe_int_s1_p2a_2; // pyc.name="pe_int_s1_p2a_2" -wire [31:0] pe_int_s1_p2a_2__next; // pyc.name="pe_int_s1_p2a_2__next" -wire [31:0] pe_int_s1_p2a_3; // pyc.name="pe_int_s1_p2a_3" -wire [31:0] pe_int_s1_p2a_3__next; // pyc.name="pe_int_s1_p2a_3__next" -wire [31:0] pe_int_s1_p2a_4; // pyc.name="pe_int_s1_p2a_4" -wire [31:0] pe_int_s1_p2a_4__next; // pyc.name="pe_int_s1_p2a_4__next" -wire [31:0] pe_int_s1_p2a_5; // pyc.name="pe_int_s1_p2a_5" -wire [31:0] pe_int_s1_p2a_5__next; // pyc.name="pe_int_s1_p2a_5__next" -wire [31:0] pe_int_s1_p2a_6; // pyc.name="pe_int_s1_p2a_6" -wire [31:0] pe_int_s1_p2a_6__next; // pyc.name="pe_int_s1_p2a_6__next" -wire [31:0] pe_int_s1_p2a_7; // pyc.name="pe_int_s1_p2a_7" -wire [31:0] pe_int_s1_p2a_7__next; // pyc.name="pe_int_s1_p2a_7__next" -wire [31:0] pe_int_s1_p2b0_0; // pyc.name="pe_int_s1_p2b0_0" -wire [31:0] pe_int_s1_p2b0_0__next; // pyc.name="pe_int_s1_p2b0_0__next" -wire [31:0] pe_int_s1_p2b0_1; // pyc.name="pe_int_s1_p2b0_1" -wire [31:0] pe_int_s1_p2b0_1__next; // pyc.name="pe_int_s1_p2b0_1__next" -wire [31:0] pe_int_s1_p2b0_2; // pyc.name="pe_int_s1_p2b0_2" -wire [31:0] pe_int_s1_p2b0_2__next; // pyc.name="pe_int_s1_p2b0_2__next" -wire [31:0] pe_int_s1_p2b0_3; // pyc.name="pe_int_s1_p2b0_3" -wire [31:0] pe_int_s1_p2b0_3__next; // pyc.name="pe_int_s1_p2b0_3__next" -wire [31:0] pe_int_s1_p2b0_4; // pyc.name="pe_int_s1_p2b0_4" -wire [31:0] pe_int_s1_p2b0_4__next; // pyc.name="pe_int_s1_p2b0_4__next" -wire [31:0] pe_int_s1_p2b0_5; // pyc.name="pe_int_s1_p2b0_5" -wire [31:0] pe_int_s1_p2b0_5__next; // pyc.name="pe_int_s1_p2b0_5__next" -wire [31:0] pe_int_s1_p2b0_6; // pyc.name="pe_int_s1_p2b0_6" -wire [31:0] pe_int_s1_p2b0_6__next; // pyc.name="pe_int_s1_p2b0_6__next" -wire [31:0] pe_int_s1_p2b0_7; // pyc.name="pe_int_s1_p2b0_7" -wire [31:0] pe_int_s1_p2b0_7__next; // pyc.name="pe_int_s1_p2b0_7__next" -wire [31:0] pe_int_s1_p2b1_0; // pyc.name="pe_int_s1_p2b1_0" -wire [31:0] pe_int_s1_p2b1_0__next; // pyc.name="pe_int_s1_p2b1_0__next" -wire [31:0] pe_int_s1_p2b1_1; // pyc.name="pe_int_s1_p2b1_1" -wire [31:0] pe_int_s1_p2b1_1__next; // pyc.name="pe_int_s1_p2b1_1__next" -wire [31:0] pe_int_s1_p2b1_2; // pyc.name="pe_int_s1_p2b1_2" -wire [31:0] pe_int_s1_p2b1_2__next; // pyc.name="pe_int_s1_p2b1_2__next" -wire [31:0] pe_int_s1_p2b1_3; // pyc.name="pe_int_s1_p2b1_3" -wire [31:0] pe_int_s1_p2b1_3__next; // pyc.name="pe_int_s1_p2b1_3__next" -wire [31:0] pe_int_s1_p2b1_4; // pyc.name="pe_int_s1_p2b1_4" -wire [31:0] pe_int_s1_p2b1_4__next; // pyc.name="pe_int_s1_p2b1_4__next" -wire [31:0] pe_int_s1_p2b1_5; // pyc.name="pe_int_s1_p2b1_5" -wire [31:0] pe_int_s1_p2b1_5__next; // pyc.name="pe_int_s1_p2b1_5__next" -wire [31:0] pe_int_s1_p2b1_6; // pyc.name="pe_int_s1_p2b1_6" -wire [31:0] pe_int_s1_p2b1_6__next; // pyc.name="pe_int_s1_p2b1_6__next" -wire [31:0] pe_int_s1_p2b1_7; // pyc.name="pe_int_s1_p2b1_7" -wire [31:0] pe_int_s1_p2b1_7__next; // pyc.name="pe_int_s1_p2b1_7__next" -wire [31:0] pe_int_s1_p2c0_0; // pyc.name="pe_int_s1_p2c0_0" -wire [31:0] pe_int_s1_p2c0_0__next; // pyc.name="pe_int_s1_p2c0_0__next" -wire [31:0] pe_int_s1_p2c0_1; // pyc.name="pe_int_s1_p2c0_1" -wire [31:0] pe_int_s1_p2c0_10; // pyc.name="pe_int_s1_p2c0_10" -wire [31:0] pe_int_s1_p2c0_10__next; // pyc.name="pe_int_s1_p2c0_10__next" -wire [31:0] pe_int_s1_p2c0_11; // pyc.name="pe_int_s1_p2c0_11" -wire [31:0] pe_int_s1_p2c0_11__next; // pyc.name="pe_int_s1_p2c0_11__next" -wire [31:0] pe_int_s1_p2c0_12; // pyc.name="pe_int_s1_p2c0_12" -wire [31:0] pe_int_s1_p2c0_12__next; // pyc.name="pe_int_s1_p2c0_12__next" -wire [31:0] pe_int_s1_p2c0_13; // pyc.name="pe_int_s1_p2c0_13" -wire [31:0] pe_int_s1_p2c0_13__next; // pyc.name="pe_int_s1_p2c0_13__next" -wire [31:0] pe_int_s1_p2c0_14; // pyc.name="pe_int_s1_p2c0_14" -wire [31:0] pe_int_s1_p2c0_14__next; // pyc.name="pe_int_s1_p2c0_14__next" -wire [31:0] pe_int_s1_p2c0_15; // pyc.name="pe_int_s1_p2c0_15" -wire [31:0] pe_int_s1_p2c0_15__next; // pyc.name="pe_int_s1_p2c0_15__next" -wire [31:0] pe_int_s1_p2c0_1__next; // pyc.name="pe_int_s1_p2c0_1__next" -wire [31:0] pe_int_s1_p2c0_2; // pyc.name="pe_int_s1_p2c0_2" -wire [31:0] pe_int_s1_p2c0_2__next; // pyc.name="pe_int_s1_p2c0_2__next" -wire [31:0] pe_int_s1_p2c0_3; // pyc.name="pe_int_s1_p2c0_3" -wire [31:0] pe_int_s1_p2c0_3__next; // pyc.name="pe_int_s1_p2c0_3__next" -wire [31:0] pe_int_s1_p2c0_4; // pyc.name="pe_int_s1_p2c0_4" -wire [31:0] pe_int_s1_p2c0_4__next; // pyc.name="pe_int_s1_p2c0_4__next" -wire [31:0] pe_int_s1_p2c0_5; // pyc.name="pe_int_s1_p2c0_5" -wire [31:0] pe_int_s1_p2c0_5__next; // pyc.name="pe_int_s1_p2c0_5__next" -wire [31:0] pe_int_s1_p2c0_6; // pyc.name="pe_int_s1_p2c0_6" -wire [31:0] pe_int_s1_p2c0_6__next; // pyc.name="pe_int_s1_p2c0_6__next" -wire [31:0] pe_int_s1_p2c0_7; // pyc.name="pe_int_s1_p2c0_7" -wire [31:0] pe_int_s1_p2c0_7__next; // pyc.name="pe_int_s1_p2c0_7__next" -wire [31:0] pe_int_s1_p2c0_8; // pyc.name="pe_int_s1_p2c0_8" -wire [31:0] pe_int_s1_p2c0_8__next; // pyc.name="pe_int_s1_p2c0_8__next" -wire [31:0] pe_int_s1_p2c0_9; // pyc.name="pe_int_s1_p2c0_9" -wire [31:0] pe_int_s1_p2c0_9__next; // pyc.name="pe_int_s1_p2c0_9__next" -wire [31:0] pe_int_s1_p2c1_0; // pyc.name="pe_int_s1_p2c1_0" -wire [31:0] pe_int_s1_p2c1_0__next; // pyc.name="pe_int_s1_p2c1_0__next" -wire [31:0] pe_int_s1_p2c1_1; // pyc.name="pe_int_s1_p2c1_1" -wire [31:0] pe_int_s1_p2c1_10; // pyc.name="pe_int_s1_p2c1_10" -wire [31:0] pe_int_s1_p2c1_10__next; // pyc.name="pe_int_s1_p2c1_10__next" -wire [31:0] pe_int_s1_p2c1_11; // pyc.name="pe_int_s1_p2c1_11" -wire [31:0] pe_int_s1_p2c1_11__next; // pyc.name="pe_int_s1_p2c1_11__next" -wire [31:0] pe_int_s1_p2c1_12; // pyc.name="pe_int_s1_p2c1_12" -wire [31:0] pe_int_s1_p2c1_12__next; // pyc.name="pe_int_s1_p2c1_12__next" -wire [31:0] pe_int_s1_p2c1_13; // pyc.name="pe_int_s1_p2c1_13" -wire [31:0] pe_int_s1_p2c1_13__next; // pyc.name="pe_int_s1_p2c1_13__next" -wire [31:0] pe_int_s1_p2c1_14; // pyc.name="pe_int_s1_p2c1_14" -wire [31:0] pe_int_s1_p2c1_14__next; // pyc.name="pe_int_s1_p2c1_14__next" -wire [31:0] pe_int_s1_p2c1_15; // pyc.name="pe_int_s1_p2c1_15" -wire [31:0] pe_int_s1_p2c1_15__next; // pyc.name="pe_int_s1_p2c1_15__next" -wire [31:0] pe_int_s1_p2c1_1__next; // pyc.name="pe_int_s1_p2c1_1__next" -wire [31:0] pe_int_s1_p2c1_2; // pyc.name="pe_int_s1_p2c1_2" -wire [31:0] pe_int_s1_p2c1_2__next; // pyc.name="pe_int_s1_p2c1_2__next" -wire [31:0] pe_int_s1_p2c1_3; // pyc.name="pe_int_s1_p2c1_3" -wire [31:0] pe_int_s1_p2c1_3__next; // pyc.name="pe_int_s1_p2c1_3__next" -wire [31:0] pe_int_s1_p2c1_4; // pyc.name="pe_int_s1_p2c1_4" -wire [31:0] pe_int_s1_p2c1_4__next; // pyc.name="pe_int_s1_p2c1_4__next" -wire [31:0] pe_int_s1_p2c1_5; // pyc.name="pe_int_s1_p2c1_5" -wire [31:0] pe_int_s1_p2c1_5__next; // pyc.name="pe_int_s1_p2c1_5__next" -wire [31:0] pe_int_s1_p2c1_6; // pyc.name="pe_int_s1_p2c1_6" -wire [31:0] pe_int_s1_p2c1_6__next; // pyc.name="pe_int_s1_p2c1_6__next" -wire [31:0] pe_int_s1_p2c1_7; // pyc.name="pe_int_s1_p2c1_7" -wire [31:0] pe_int_s1_p2c1_7__next; // pyc.name="pe_int_s1_p2c1_7__next" -wire [31:0] pe_int_s1_p2c1_8; // pyc.name="pe_int_s1_p2c1_8" -wire [31:0] pe_int_s1_p2c1_8__next; // pyc.name="pe_int_s1_p2c1_8__next" -wire [31:0] pe_int_s1_p2c1_9; // pyc.name="pe_int_s1_p2c1_9" -wire [31:0] pe_int_s1_p2c1_9__next; // pyc.name="pe_int_s1_p2c1_9__next" -wire [31:0] pe_int_s1_p2d0_0; // pyc.name="pe_int_s1_p2d0_0" -wire [31:0] pe_int_s1_p2d0_0__next; // pyc.name="pe_int_s1_p2d0_0__next" -wire [31:0] pe_int_s1_p2d0_1; // pyc.name="pe_int_s1_p2d0_1" -wire [31:0] pe_int_s1_p2d0_1__next; // pyc.name="pe_int_s1_p2d0_1__next" -wire [31:0] pe_int_s1_p2d0_2; // pyc.name="pe_int_s1_p2d0_2" -wire [31:0] pe_int_s1_p2d0_2__next; // pyc.name="pe_int_s1_p2d0_2__next" -wire [31:0] pe_int_s1_p2d0_3; // pyc.name="pe_int_s1_p2d0_3" -wire [31:0] pe_int_s1_p2d0_3__next; // pyc.name="pe_int_s1_p2d0_3__next" -wire [31:0] pe_int_s1_p2d0_4; // pyc.name="pe_int_s1_p2d0_4" -wire [31:0] pe_int_s1_p2d0_4__next; // pyc.name="pe_int_s1_p2d0_4__next" -wire [31:0] pe_int_s1_p2d0_5; // pyc.name="pe_int_s1_p2d0_5" -wire [31:0] pe_int_s1_p2d0_5__next; // pyc.name="pe_int_s1_p2d0_5__next" -wire [31:0] pe_int_s1_p2d0_6; // pyc.name="pe_int_s1_p2d0_6" -wire [31:0] pe_int_s1_p2d0_6__next; // pyc.name="pe_int_s1_p2d0_6__next" -wire [31:0] pe_int_s1_p2d0_7; // pyc.name="pe_int_s1_p2d0_7" -wire [31:0] pe_int_s1_p2d0_7__next; // pyc.name="pe_int_s1_p2d0_7__next" -wire [31:0] pe_int_s1_p2d1_0; // pyc.name="pe_int_s1_p2d1_0" -wire [31:0] pe_int_s1_p2d1_0__next; // pyc.name="pe_int_s1_p2d1_0__next" -wire [31:0] pe_int_s1_p2d1_1; // pyc.name="pe_int_s1_p2d1_1" -wire [31:0] pe_int_s1_p2d1_1__next; // pyc.name="pe_int_s1_p2d1_1__next" -wire [31:0] pe_int_s1_p2d1_2; // pyc.name="pe_int_s1_p2d1_2" -wire [31:0] pe_int_s1_p2d1_2__next; // pyc.name="pe_int_s1_p2d1_2__next" -wire [31:0] pe_int_s1_p2d1_3; // pyc.name="pe_int_s1_p2d1_3" -wire [31:0] pe_int_s1_p2d1_3__next; // pyc.name="pe_int_s1_p2d1_3__next" -wire [31:0] pe_int_s1_p2d1_4; // pyc.name="pe_int_s1_p2d1_4" -wire [31:0] pe_int_s1_p2d1_4__next; // pyc.name="pe_int_s1_p2d1_4__next" -wire [31:0] pe_int_s1_p2d1_5; // pyc.name="pe_int_s1_p2d1_5" -wire [31:0] pe_int_s1_p2d1_5__next; // pyc.name="pe_int_s1_p2d1_5__next" -wire [31:0] pe_int_s1_p2d1_6; // pyc.name="pe_int_s1_p2d1_6" -wire [31:0] pe_int_s1_p2d1_6__next; // pyc.name="pe_int_s1_p2d1_6__next" -wire [31:0] pe_int_s1_p2d1_7; // pyc.name="pe_int_s1_p2d1_7" -wire [31:0] pe_int_s1_p2d1_7__next; // pyc.name="pe_int_s1_p2d1_7__next" +wire [18:0] pe_int_s1_p2a_0; // pyc.name="pe_int_s1_p2a_0" +wire [18:0] pe_int_s1_p2a_0__next; // pyc.name="pe_int_s1_p2a_0__next" +wire [18:0] pe_int_s1_p2a_1; // pyc.name="pe_int_s1_p2a_1" +wire [18:0] pe_int_s1_p2a_1__next; // pyc.name="pe_int_s1_p2a_1__next" +wire [18:0] pe_int_s1_p2a_2; // pyc.name="pe_int_s1_p2a_2" +wire [18:0] pe_int_s1_p2a_2__next; // pyc.name="pe_int_s1_p2a_2__next" +wire [18:0] pe_int_s1_p2a_3; // pyc.name="pe_int_s1_p2a_3" +wire [18:0] pe_int_s1_p2a_3__next; // pyc.name="pe_int_s1_p2a_3__next" +wire [18:0] pe_int_s1_p2a_4; // pyc.name="pe_int_s1_p2a_4" +wire [18:0] pe_int_s1_p2a_4__next; // pyc.name="pe_int_s1_p2a_4__next" +wire [18:0] pe_int_s1_p2a_5; // pyc.name="pe_int_s1_p2a_5" +wire [18:0] pe_int_s1_p2a_5__next; // pyc.name="pe_int_s1_p2a_5__next" +wire [18:0] pe_int_s1_p2a_6; // pyc.name="pe_int_s1_p2a_6" +wire [18:0] pe_int_s1_p2a_6__next; // pyc.name="pe_int_s1_p2a_6__next" +wire [18:0] pe_int_s1_p2a_7; // pyc.name="pe_int_s1_p2a_7" +wire [18:0] pe_int_s1_p2a_7__next; // pyc.name="pe_int_s1_p2a_7__next" +wire [18:0] pe_int_s1_p2b0_0; // pyc.name="pe_int_s1_p2b0_0" +wire [18:0] pe_int_s1_p2b0_0__next; // pyc.name="pe_int_s1_p2b0_0__next" +wire [18:0] pe_int_s1_p2b0_1; // pyc.name="pe_int_s1_p2b0_1" +wire [18:0] pe_int_s1_p2b0_1__next; // pyc.name="pe_int_s1_p2b0_1__next" +wire [18:0] pe_int_s1_p2b0_2; // pyc.name="pe_int_s1_p2b0_2" +wire [18:0] pe_int_s1_p2b0_2__next; // pyc.name="pe_int_s1_p2b0_2__next" +wire [18:0] pe_int_s1_p2b0_3; // pyc.name="pe_int_s1_p2b0_3" +wire [18:0] pe_int_s1_p2b0_3__next; // pyc.name="pe_int_s1_p2b0_3__next" +wire [18:0] pe_int_s1_p2b0_4; // pyc.name="pe_int_s1_p2b0_4" +wire [18:0] pe_int_s1_p2b0_4__next; // pyc.name="pe_int_s1_p2b0_4__next" +wire [18:0] pe_int_s1_p2b0_5; // pyc.name="pe_int_s1_p2b0_5" +wire [18:0] pe_int_s1_p2b0_5__next; // pyc.name="pe_int_s1_p2b0_5__next" +wire [18:0] pe_int_s1_p2b0_6; // pyc.name="pe_int_s1_p2b0_6" +wire [18:0] pe_int_s1_p2b0_6__next; // pyc.name="pe_int_s1_p2b0_6__next" +wire [18:0] pe_int_s1_p2b0_7; // pyc.name="pe_int_s1_p2b0_7" +wire [18:0] pe_int_s1_p2b0_7__next; // pyc.name="pe_int_s1_p2b0_7__next" +wire [15:0] pe_int_s1_p2b1_0; // pyc.name="pe_int_s1_p2b1_0" +wire [15:0] pe_int_s1_p2b1_0__next; // pyc.name="pe_int_s1_p2b1_0__next" +wire [15:0] pe_int_s1_p2b1_1; // pyc.name="pe_int_s1_p2b1_1" +wire [15:0] pe_int_s1_p2b1_1__next; // pyc.name="pe_int_s1_p2b1_1__next" +wire [15:0] pe_int_s1_p2b1_2; // pyc.name="pe_int_s1_p2b1_2" +wire [15:0] pe_int_s1_p2b1_2__next; // pyc.name="pe_int_s1_p2b1_2__next" +wire [15:0] pe_int_s1_p2b1_3; // pyc.name="pe_int_s1_p2b1_3" +wire [15:0] pe_int_s1_p2b1_3__next; // pyc.name="pe_int_s1_p2b1_3__next" +wire [15:0] pe_int_s1_p2b1_4; // pyc.name="pe_int_s1_p2b1_4" +wire [15:0] pe_int_s1_p2b1_4__next; // pyc.name="pe_int_s1_p2b1_4__next" +wire [15:0] pe_int_s1_p2b1_5; // pyc.name="pe_int_s1_p2b1_5" +wire [15:0] pe_int_s1_p2b1_5__next; // pyc.name="pe_int_s1_p2b1_5__next" +wire [15:0] pe_int_s1_p2b1_6; // pyc.name="pe_int_s1_p2b1_6" +wire [15:0] pe_int_s1_p2b1_6__next; // pyc.name="pe_int_s1_p2b1_6__next" +wire [15:0] pe_int_s1_p2b1_7; // pyc.name="pe_int_s1_p2b1_7" +wire [15:0] pe_int_s1_p2b1_7__next; // pyc.name="pe_int_s1_p2b1_7__next" +wire [18:0] pe_int_s1_p2c0_0; // pyc.name="pe_int_s1_p2c0_0" +wire [18:0] pe_int_s1_p2c0_0__next; // pyc.name="pe_int_s1_p2c0_0__next" +wire [18:0] pe_int_s1_p2c0_1; // pyc.name="pe_int_s1_p2c0_1" +wire [18:0] pe_int_s1_p2c0_10; // pyc.name="pe_int_s1_p2c0_10" +wire [18:0] pe_int_s1_p2c0_10__next; // pyc.name="pe_int_s1_p2c0_10__next" +wire [18:0] pe_int_s1_p2c0_11; // pyc.name="pe_int_s1_p2c0_11" +wire [18:0] pe_int_s1_p2c0_11__next; // pyc.name="pe_int_s1_p2c0_11__next" +wire [18:0] pe_int_s1_p2c0_12; // pyc.name="pe_int_s1_p2c0_12" +wire [18:0] pe_int_s1_p2c0_12__next; // pyc.name="pe_int_s1_p2c0_12__next" +wire [18:0] pe_int_s1_p2c0_13; // pyc.name="pe_int_s1_p2c0_13" +wire [18:0] pe_int_s1_p2c0_13__next; // pyc.name="pe_int_s1_p2c0_13__next" +wire [18:0] pe_int_s1_p2c0_14; // pyc.name="pe_int_s1_p2c0_14" +wire [18:0] pe_int_s1_p2c0_14__next; // pyc.name="pe_int_s1_p2c0_14__next" +wire [18:0] pe_int_s1_p2c0_15; // pyc.name="pe_int_s1_p2c0_15" +wire [18:0] pe_int_s1_p2c0_15__next; // pyc.name="pe_int_s1_p2c0_15__next" +wire [18:0] pe_int_s1_p2c0_1__next; // pyc.name="pe_int_s1_p2c0_1__next" +wire [18:0] pe_int_s1_p2c0_2; // pyc.name="pe_int_s1_p2c0_2" +wire [18:0] pe_int_s1_p2c0_2__next; // pyc.name="pe_int_s1_p2c0_2__next" +wire [18:0] pe_int_s1_p2c0_3; // pyc.name="pe_int_s1_p2c0_3" +wire [18:0] pe_int_s1_p2c0_3__next; // pyc.name="pe_int_s1_p2c0_3__next" +wire [18:0] pe_int_s1_p2c0_4; // pyc.name="pe_int_s1_p2c0_4" +wire [18:0] pe_int_s1_p2c0_4__next; // pyc.name="pe_int_s1_p2c0_4__next" +wire [18:0] pe_int_s1_p2c0_5; // pyc.name="pe_int_s1_p2c0_5" +wire [18:0] pe_int_s1_p2c0_5__next; // pyc.name="pe_int_s1_p2c0_5__next" +wire [18:0] pe_int_s1_p2c0_6; // pyc.name="pe_int_s1_p2c0_6" +wire [18:0] pe_int_s1_p2c0_6__next; // pyc.name="pe_int_s1_p2c0_6__next" +wire [18:0] pe_int_s1_p2c0_7; // pyc.name="pe_int_s1_p2c0_7" +wire [18:0] pe_int_s1_p2c0_7__next; // pyc.name="pe_int_s1_p2c0_7__next" +wire [18:0] pe_int_s1_p2c0_8; // pyc.name="pe_int_s1_p2c0_8" +wire [18:0] pe_int_s1_p2c0_8__next; // pyc.name="pe_int_s1_p2c0_8__next" +wire [18:0] pe_int_s1_p2c0_9; // pyc.name="pe_int_s1_p2c0_9" +wire [18:0] pe_int_s1_p2c0_9__next; // pyc.name="pe_int_s1_p2c0_9__next" +wire [15:0] pe_int_s1_p2c1_0; // pyc.name="pe_int_s1_p2c1_0" +wire [15:0] pe_int_s1_p2c1_0__next; // pyc.name="pe_int_s1_p2c1_0__next" +wire [15:0] pe_int_s1_p2c1_1; // pyc.name="pe_int_s1_p2c1_1" +wire [15:0] pe_int_s1_p2c1_10; // pyc.name="pe_int_s1_p2c1_10" +wire [15:0] pe_int_s1_p2c1_10__next; // pyc.name="pe_int_s1_p2c1_10__next" +wire [15:0] pe_int_s1_p2c1_11; // pyc.name="pe_int_s1_p2c1_11" +wire [15:0] pe_int_s1_p2c1_11__next; // pyc.name="pe_int_s1_p2c1_11__next" +wire [15:0] pe_int_s1_p2c1_12; // pyc.name="pe_int_s1_p2c1_12" +wire [15:0] pe_int_s1_p2c1_12__next; // pyc.name="pe_int_s1_p2c1_12__next" +wire [15:0] pe_int_s1_p2c1_13; // pyc.name="pe_int_s1_p2c1_13" +wire [15:0] pe_int_s1_p2c1_13__next; // pyc.name="pe_int_s1_p2c1_13__next" +wire [15:0] pe_int_s1_p2c1_14; // pyc.name="pe_int_s1_p2c1_14" +wire [15:0] pe_int_s1_p2c1_14__next; // pyc.name="pe_int_s1_p2c1_14__next" +wire [15:0] pe_int_s1_p2c1_15; // pyc.name="pe_int_s1_p2c1_15" +wire [15:0] pe_int_s1_p2c1_15__next; // pyc.name="pe_int_s1_p2c1_15__next" +wire [15:0] pe_int_s1_p2c1_1__next; // pyc.name="pe_int_s1_p2c1_1__next" +wire [15:0] pe_int_s1_p2c1_2; // pyc.name="pe_int_s1_p2c1_2" +wire [15:0] pe_int_s1_p2c1_2__next; // pyc.name="pe_int_s1_p2c1_2__next" +wire [15:0] pe_int_s1_p2c1_3; // pyc.name="pe_int_s1_p2c1_3" +wire [15:0] pe_int_s1_p2c1_3__next; // pyc.name="pe_int_s1_p2c1_3__next" +wire [15:0] pe_int_s1_p2c1_4; // pyc.name="pe_int_s1_p2c1_4" +wire [15:0] pe_int_s1_p2c1_4__next; // pyc.name="pe_int_s1_p2c1_4__next" +wire [15:0] pe_int_s1_p2c1_5; // pyc.name="pe_int_s1_p2c1_5" +wire [15:0] pe_int_s1_p2c1_5__next; // pyc.name="pe_int_s1_p2c1_5__next" +wire [15:0] pe_int_s1_p2c1_6; // pyc.name="pe_int_s1_p2c1_6" +wire [15:0] pe_int_s1_p2c1_6__next; // pyc.name="pe_int_s1_p2c1_6__next" +wire [15:0] pe_int_s1_p2c1_7; // pyc.name="pe_int_s1_p2c1_7" +wire [15:0] pe_int_s1_p2c1_7__next; // pyc.name="pe_int_s1_p2c1_7__next" +wire [15:0] pe_int_s1_p2c1_8; // pyc.name="pe_int_s1_p2c1_8" +wire [15:0] pe_int_s1_p2c1_8__next; // pyc.name="pe_int_s1_p2c1_8__next" +wire [15:0] pe_int_s1_p2c1_9; // pyc.name="pe_int_s1_p2c1_9" +wire [15:0] pe_int_s1_p2c1_9__next; // pyc.name="pe_int_s1_p2c1_9__next" +wire [18:0] pe_int_s1_p2d0_0; // pyc.name="pe_int_s1_p2d0_0" +wire [18:0] pe_int_s1_p2d0_0__next; // pyc.name="pe_int_s1_p2d0_0__next" +wire [18:0] pe_int_s1_p2d0_1; // pyc.name="pe_int_s1_p2d0_1" +wire [18:0] pe_int_s1_p2d0_1__next; // pyc.name="pe_int_s1_p2d0_1__next" +wire [18:0] pe_int_s1_p2d0_2; // pyc.name="pe_int_s1_p2d0_2" +wire [18:0] pe_int_s1_p2d0_2__next; // pyc.name="pe_int_s1_p2d0_2__next" +wire [18:0] pe_int_s1_p2d0_3; // pyc.name="pe_int_s1_p2d0_3" +wire [18:0] pe_int_s1_p2d0_3__next; // pyc.name="pe_int_s1_p2d0_3__next" +wire [18:0] pe_int_s1_p2d0_4; // pyc.name="pe_int_s1_p2d0_4" +wire [18:0] pe_int_s1_p2d0_4__next; // pyc.name="pe_int_s1_p2d0_4__next" +wire [18:0] pe_int_s1_p2d0_5; // pyc.name="pe_int_s1_p2d0_5" +wire [18:0] pe_int_s1_p2d0_5__next; // pyc.name="pe_int_s1_p2d0_5__next" +wire [18:0] pe_int_s1_p2d0_6; // pyc.name="pe_int_s1_p2d0_6" +wire [18:0] pe_int_s1_p2d0_6__next; // pyc.name="pe_int_s1_p2d0_6__next" +wire [18:0] pe_int_s1_p2d0_7; // pyc.name="pe_int_s1_p2d0_7" +wire [18:0] pe_int_s1_p2d0_7__next; // pyc.name="pe_int_s1_p2d0_7__next" +wire [15:0] pe_int_s1_p2d1_0; // pyc.name="pe_int_s1_p2d1_0" +wire [15:0] pe_int_s1_p2d1_0__next; // pyc.name="pe_int_s1_p2d1_0__next" +wire [15:0] pe_int_s1_p2d1_1; // pyc.name="pe_int_s1_p2d1_1" +wire [15:0] pe_int_s1_p2d1_1__next; // pyc.name="pe_int_s1_p2d1_1__next" +wire [15:0] pe_int_s1_p2d1_2; // pyc.name="pe_int_s1_p2d1_2" +wire [15:0] pe_int_s1_p2d1_2__next; // pyc.name="pe_int_s1_p2d1_2__next" +wire [15:0] pe_int_s1_p2d1_3; // pyc.name="pe_int_s1_p2d1_3" +wire [15:0] pe_int_s1_p2d1_3__next; // pyc.name="pe_int_s1_p2d1_3__next" +wire [15:0] pe_int_s1_p2d1_4; // pyc.name="pe_int_s1_p2d1_4" +wire [15:0] pe_int_s1_p2d1_4__next; // pyc.name="pe_int_s1_p2d1_4__next" +wire [15:0] pe_int_s1_p2d1_5; // pyc.name="pe_int_s1_p2d1_5" +wire [15:0] pe_int_s1_p2d1_5__next; // pyc.name="pe_int_s1_p2d1_5__next" +wire [15:0] pe_int_s1_p2d1_6; // pyc.name="pe_int_s1_p2d1_6" +wire [15:0] pe_int_s1_p2d1_6__next; // pyc.name="pe_int_s1_p2d1_6__next" +wire [15:0] pe_int_s1_p2d1_7; // pyc.name="pe_int_s1_p2d1_7" +wire [15:0] pe_int_s1_p2d1_7__next; // pyc.name="pe_int_s1_p2d1_7__next" wire pe_int_s1_vld; // pyc.name="pe_int_s1_vld" wire pe_int_s1_vld__next; // pyc.name="pe_int_s1_vld__next" wire [1:0] pe_int_s2_e1_a; // pyc.name="pe_int_s2_e1_a" @@ -223,238 +217,225 @@ wire pe_int_s2_is_2b; // pyc.name="pe_int_s2_is_2b" wire pe_int_s2_is_2b__next; // pyc.name="pe_int_s2_is_2b__next" wire pe_int_s2_is_2c; // pyc.name="pe_int_s2_is_2c" wire pe_int_s2_is_2c__next; // pyc.name="pe_int_s2_is_2c__next" -wire [31:0] pe_int_s2_s2a; // pyc.name="pe_int_s2_s2a" -wire [31:0] pe_int_s2_s2a__next; // pyc.name="pe_int_s2_s2a__next" -wire [31:0] pe_int_s2_s2b0; // pyc.name="pe_int_s2_s2b0" -wire [31:0] pe_int_s2_s2b0__next; // pyc.name="pe_int_s2_s2b0__next" -wire [31:0] pe_int_s2_s2b1; // pyc.name="pe_int_s2_s2b1" -wire [31:0] pe_int_s2_s2b1__next; // pyc.name="pe_int_s2_s2b1__next" -wire [31:0] pe_int_s2_s2c0_hi; // pyc.name="pe_int_s2_s2c0_hi" -wire [31:0] pe_int_s2_s2c0_hi__next; // pyc.name="pe_int_s2_s2c0_hi__next" -wire [31:0] pe_int_s2_s2c0_lo; // pyc.name="pe_int_s2_s2c0_lo" -wire [31:0] pe_int_s2_s2c0_lo__next; // pyc.name="pe_int_s2_s2c0_lo__next" -wire [31:0] pe_int_s2_s2c1_hi; // pyc.name="pe_int_s2_s2c1_hi" -wire [31:0] pe_int_s2_s2c1_hi__next; // pyc.name="pe_int_s2_s2c1_hi__next" -wire [31:0] pe_int_s2_s2c1_lo; // pyc.name="pe_int_s2_s2c1_lo" -wire [31:0] pe_int_s2_s2c1_lo__next; // pyc.name="pe_int_s2_s2c1_lo__next" -wire [31:0] pe_int_s2_s2d0; // pyc.name="pe_int_s2_s2d0" -wire [31:0] pe_int_s2_s2d0__next; // pyc.name="pe_int_s2_s2d0__next" -wire [31:0] pe_int_s2_s2d1; // pyc.name="pe_int_s2_s2d1" -wire [31:0] pe_int_s2_s2d1__next; // pyc.name="pe_int_s2_s2d1__next" +wire [18:0] pe_int_s2_s2a; // pyc.name="pe_int_s2_s2a" +wire [18:0] pe_int_s2_s2a__next; // pyc.name="pe_int_s2_s2a__next" +wire [18:0] pe_int_s2_s2b0; // pyc.name="pe_int_s2_s2b0" +wire [18:0] pe_int_s2_s2b0__next; // pyc.name="pe_int_s2_s2b0__next" +wire [15:0] pe_int_s2_s2b1; // pyc.name="pe_int_s2_s2b1" +wire [15:0] pe_int_s2_s2b1__next; // pyc.name="pe_int_s2_s2b1__next" +wire [18:0] pe_int_s2_s2c0_hi; // pyc.name="pe_int_s2_s2c0_hi" +wire [18:0] pe_int_s2_s2c0_hi__next; // pyc.name="pe_int_s2_s2c0_hi__next" +wire [18:0] pe_int_s2_s2c0_lo; // pyc.name="pe_int_s2_s2c0_lo" +wire [18:0] pe_int_s2_s2c0_lo__next; // pyc.name="pe_int_s2_s2c0_lo__next" +wire [15:0] pe_int_s2_s2c1_hi; // pyc.name="pe_int_s2_s2c1_hi" +wire [15:0] pe_int_s2_s2c1_hi__next; // pyc.name="pe_int_s2_s2c1_hi__next" +wire [15:0] pe_int_s2_s2c1_lo; // pyc.name="pe_int_s2_s2c1_lo" +wire [15:0] pe_int_s2_s2c1_lo__next; // pyc.name="pe_int_s2_s2c1_lo__next" +wire [18:0] pe_int_s2_s2d0; // pyc.name="pe_int_s2_s2d0" +wire [18:0] pe_int_s2_s2d0__next; // pyc.name="pe_int_s2_s2d0__next" +wire [15:0] pe_int_s2_s2d1; // pyc.name="pe_int_s2_s2d1" +wire [15:0] pe_int_s2_s2d1__next; // pyc.name="pe_int_s2_s2d1__next" wire pe_int_s2_vld; // pyc.name="pe_int_s2_vld" wire pe_int_s2_vld__next; // pyc.name="pe_int_s2_vld__next" -wire [1:0] pyc_add_526; // op=pyc.add -wire [1:0] pyc_add_531; // op=pyc.add -wire [31:0] pyc_add_544; // op=pyc.add -wire [1:0] pyc_add_547; // op=pyc.add -wire [1:0] pyc_add_550; // op=pyc.add -wire [31:0] pyc_add_563; // op=pyc.add -wire [18:0] pyc_comb_15; // op=pyc.comb -wire [15:0] pyc_comb_16; // op=pyc.comb -wire [1:0] pyc_comb_17; // op=pyc.comb -wire [31:0] pyc_comb_18; // op=pyc.comb +wire [1:0] pyc_add_548; // op=pyc.add +wire [1:0] pyc_add_553; // op=pyc.add +wire [18:0] pyc_add_566; // op=pyc.add +wire [1:0] pyc_add_569; // op=pyc.add +wire [1:0] pyc_add_572; // op=pyc.add +wire [15:0] pyc_add_585; // op=pyc.add +wire [1:0] pyc_comb_12; // op=pyc.comb +wire [15:0] pyc_comb_13; // op=pyc.comb +wire [18:0] pyc_comb_14; // op=pyc.comb +wire [1:0] pyc_comb_15; // op=pyc.comb +wire [79:0] pyc_comb_16; // op=pyc.comb +wire pyc_comb_17; // op=pyc.comb +wire pyc_comb_18; // op=pyc.comb wire [1:0] pyc_comb_19; // op=pyc.comb -wire [79:0] pyc_comb_20; // op=pyc.comb -wire pyc_comb_21; // op=pyc.comb -wire pyc_comb_22; // op=pyc.comb -wire [1:0] pyc_comb_23; // op=pyc.comb -wire [1:0] pyc_comb_24; // op=pyc.comb -wire [1:0] pyc_comb_25; // op=pyc.comb -wire [79:0] pyc_comb_26; // op=pyc.comb -wire [79:0] pyc_comb_27; // op=pyc.comb -wire [79:0] pyc_comb_28; // op=pyc.comb -wire pyc_comb_29; // op=pyc.comb +wire [1:0] pyc_comb_20; // op=pyc.comb +wire [1:0] pyc_comb_21; // op=pyc.comb +wire [79:0] pyc_comb_22; // op=pyc.comb +wire [79:0] pyc_comb_23; // op=pyc.comb +wire [79:0] pyc_comb_24; // op=pyc.comb +wire pyc_comb_25; // op=pyc.comb +wire pyc_comb_26; // op=pyc.comb +wire pyc_comb_27; // op=pyc.comb +wire pyc_comb_28; // op=pyc.comb wire pyc_comb_30; // op=pyc.comb -wire pyc_comb_31; // op=pyc.comb wire pyc_comb_32; // op=pyc.comb -wire [1:0] pyc_comb_325; // op=pyc.comb -wire [31:0] pyc_comb_326; // op=pyc.comb -wire [31:0] pyc_comb_327; // op=pyc.comb -wire [31:0] pyc_comb_328; // op=pyc.comb -wire [31:0] pyc_comb_329; // op=pyc.comb -wire pyc_comb_33; // op=pyc.comb -wire [31:0] pyc_comb_330; // op=pyc.comb -wire [31:0] pyc_comb_331; // op=pyc.comb -wire [31:0] pyc_comb_332; // op=pyc.comb -wire [31:0] pyc_comb_333; // op=pyc.comb -wire [31:0] pyc_comb_334; // op=pyc.comb -wire [31:0] pyc_comb_335; // op=pyc.comb -wire [31:0] pyc_comb_336; // op=pyc.comb -wire [31:0] pyc_comb_337; // op=pyc.comb -wire [31:0] pyc_comb_338; // op=pyc.comb -wire [31:0] pyc_comb_339; // op=pyc.comb -wire [31:0] pyc_comb_340; // op=pyc.comb -wire [31:0] pyc_comb_341; // op=pyc.comb -wire [31:0] pyc_comb_342; // op=pyc.comb -wire [31:0] pyc_comb_343; // op=pyc.comb -wire [31:0] pyc_comb_344; // op=pyc.comb -wire [31:0] pyc_comb_345; // op=pyc.comb -wire [31:0] pyc_comb_346; // op=pyc.comb -wire [31:0] pyc_comb_347; // op=pyc.comb -wire [31:0] pyc_comb_348; // op=pyc.comb -wire [31:0] pyc_comb_349; // op=pyc.comb -wire pyc_comb_35; // op=pyc.comb -wire [31:0] pyc_comb_350; // op=pyc.comb -wire [31:0] pyc_comb_351; // op=pyc.comb -wire [31:0] pyc_comb_352; // op=pyc.comb -wire [31:0] pyc_comb_353; // op=pyc.comb -wire [31:0] pyc_comb_354; // op=pyc.comb -wire [31:0] pyc_comb_355; // op=pyc.comb -wire [31:0] pyc_comb_356; // op=pyc.comb -wire [31:0] pyc_comb_357; // op=pyc.comb -wire [31:0] pyc_comb_358; // op=pyc.comb -wire [31:0] pyc_comb_359; // op=pyc.comb -wire [31:0] pyc_comb_360; // op=pyc.comb -wire [31:0] pyc_comb_361; // op=pyc.comb -wire [31:0] pyc_comb_362; // op=pyc.comb -wire [31:0] pyc_comb_363; // op=pyc.comb -wire [31:0] pyc_comb_364; // op=pyc.comb -wire [31:0] pyc_comb_365; // op=pyc.comb -wire [31:0] pyc_comb_366; // op=pyc.comb -wire [31:0] pyc_comb_367; // op=pyc.comb -wire [31:0] pyc_comb_368; // op=pyc.comb -wire [31:0] pyc_comb_369; // op=pyc.comb -wire pyc_comb_37; // op=pyc.comb -wire [31:0] pyc_comb_370; // op=pyc.comb -wire [31:0] pyc_comb_371; // op=pyc.comb -wire [31:0] pyc_comb_372; // op=pyc.comb -wire [31:0] pyc_comb_373; // op=pyc.comb -wire [31:0] pyc_comb_374; // op=pyc.comb -wire [31:0] pyc_comb_375; // op=pyc.comb -wire [31:0] pyc_comb_376; // op=pyc.comb -wire [31:0] pyc_comb_377; // op=pyc.comb -wire [31:0] pyc_comb_378; // op=pyc.comb -wire [31:0] pyc_comb_379; // op=pyc.comb -wire [31:0] pyc_comb_380; // op=pyc.comb -wire [31:0] pyc_comb_381; // op=pyc.comb -wire [31:0] pyc_comb_382; // op=pyc.comb -wire [31:0] pyc_comb_383; // op=pyc.comb -wire [31:0] pyc_comb_384; // op=pyc.comb -wire [31:0] pyc_comb_385; // op=pyc.comb -wire [31:0] pyc_comb_386; // op=pyc.comb -wire [31:0] pyc_comb_387; // op=pyc.comb -wire [31:0] pyc_comb_388; // op=pyc.comb -wire [31:0] pyc_comb_389; // op=pyc.comb -wire pyc_comb_39; // op=pyc.comb -wire [31:0] pyc_comb_390; // op=pyc.comb -wire [31:0] pyc_comb_391; // op=pyc.comb -wire [31:0] pyc_comb_392; // op=pyc.comb -wire [31:0] pyc_comb_393; // op=pyc.comb -wire [31:0] pyc_comb_394; // op=pyc.comb -wire [31:0] pyc_comb_395; // op=pyc.comb -wire [31:0] pyc_comb_396; // op=pyc.comb -wire [31:0] pyc_comb_397; // op=pyc.comb -wire pyc_comb_399; // op=pyc.comb -wire pyc_comb_401; // op=pyc.comb -wire pyc_comb_403; // op=pyc.comb -wire pyc_comb_405; // op=pyc.comb -wire [1:0] pyc_comb_408; // op=pyc.comb -wire pyc_comb_41; // op=pyc.comb -wire [1:0] pyc_comb_410; // op=pyc.comb -wire [1:0] pyc_comb_412; // op=pyc.comb -wire pyc_comb_43; // op=pyc.comb -wire [1:0] pyc_comb_48; // op=pyc.comb -wire pyc_comb_497; // op=pyc.comb -wire pyc_comb_498; // op=pyc.comb -wire [2:0] pyc_comb_499; // op=pyc.comb -wire [1:0] pyc_comb_50; // op=pyc.comb -wire [2:0] pyc_comb_500; // op=pyc.comb -wire pyc_comb_505; // op=pyc.comb -wire pyc_comb_506; // op=pyc.comb -wire pyc_comb_507; // op=pyc.comb -wire [31:0] pyc_comb_512; // op=pyc.comb -wire [31:0] pyc_comb_513; // op=pyc.comb -wire [31:0] pyc_comb_567; // op=pyc.comb -wire [31:0] pyc_comb_568; // op=pyc.comb -wire [31:0] pyc_comb_570; // op=pyc.comb -wire [18:0] pyc_comb_577; // op=pyc.comb -wire [15:0] pyc_comb_578; // op=pyc.comb -wire [15:0] pyc_comb_582; // op=pyc.comb -wire [15:0] pyc_comb_583; // op=pyc.comb -wire [7:0] pyc_concat_107; // op=pyc.concat -wire [7:0] pyc_concat_113; // op=pyc.concat -wire [7:0] pyc_concat_132; // op=pyc.concat -wire [7:0] pyc_concat_138; // op=pyc.concat +wire pyc_comb_34; // op=pyc.comb +wire [1:0] pyc_comb_350; // op=pyc.comb +wire [18:0] pyc_comb_351; // op=pyc.comb +wire [18:0] pyc_comb_352; // op=pyc.comb +wire [15:0] pyc_comb_353; // op=pyc.comb +wire [18:0] pyc_comb_354; // op=pyc.comb +wire [15:0] pyc_comb_355; // op=pyc.comb +wire [18:0] pyc_comb_356; // op=pyc.comb +wire [18:0] pyc_comb_357; // op=pyc.comb +wire [15:0] pyc_comb_358; // op=pyc.comb +wire [18:0] pyc_comb_359; // op=pyc.comb +wire pyc_comb_36; // op=pyc.comb +wire [15:0] pyc_comb_360; // op=pyc.comb +wire [18:0] pyc_comb_361; // op=pyc.comb +wire [18:0] pyc_comb_362; // op=pyc.comb +wire [15:0] pyc_comb_363; // op=pyc.comb +wire [18:0] pyc_comb_364; // op=pyc.comb +wire [15:0] pyc_comb_365; // op=pyc.comb +wire [18:0] pyc_comb_366; // op=pyc.comb +wire [18:0] pyc_comb_367; // op=pyc.comb +wire [15:0] pyc_comb_368; // op=pyc.comb +wire [18:0] pyc_comb_369; // op=pyc.comb +wire [15:0] pyc_comb_370; // op=pyc.comb +wire [18:0] pyc_comb_371; // op=pyc.comb +wire [18:0] pyc_comb_372; // op=pyc.comb +wire [15:0] pyc_comb_373; // op=pyc.comb +wire [18:0] pyc_comb_374; // op=pyc.comb +wire [15:0] pyc_comb_375; // op=pyc.comb +wire [18:0] pyc_comb_376; // op=pyc.comb +wire [18:0] pyc_comb_377; // op=pyc.comb +wire [15:0] pyc_comb_378; // op=pyc.comb +wire [18:0] pyc_comb_379; // op=pyc.comb +wire [15:0] pyc_comb_380; // op=pyc.comb +wire [18:0] pyc_comb_381; // op=pyc.comb +wire [18:0] pyc_comb_382; // op=pyc.comb +wire [15:0] pyc_comb_383; // op=pyc.comb +wire [18:0] pyc_comb_384; // op=pyc.comb +wire [15:0] pyc_comb_385; // op=pyc.comb +wire [18:0] pyc_comb_386; // op=pyc.comb +wire [18:0] pyc_comb_387; // op=pyc.comb +wire [15:0] pyc_comb_388; // op=pyc.comb +wire [18:0] pyc_comb_389; // op=pyc.comb +wire [15:0] pyc_comb_390; // op=pyc.comb +wire [18:0] pyc_comb_391; // op=pyc.comb +wire [15:0] pyc_comb_392; // op=pyc.comb +wire [18:0] pyc_comb_393; // op=pyc.comb +wire [15:0] pyc_comb_394; // op=pyc.comb +wire [18:0] pyc_comb_395; // op=pyc.comb +wire [15:0] pyc_comb_396; // op=pyc.comb +wire [18:0] pyc_comb_397; // op=pyc.comb +wire [15:0] pyc_comb_398; // op=pyc.comb +wire [18:0] pyc_comb_399; // op=pyc.comb +wire [15:0] pyc_comb_400; // op=pyc.comb +wire [18:0] pyc_comb_401; // op=pyc.comb +wire [15:0] pyc_comb_402; // op=pyc.comb +wire [18:0] pyc_comb_403; // op=pyc.comb +wire [15:0] pyc_comb_404; // op=pyc.comb +wire [18:0] pyc_comb_405; // op=pyc.comb +wire [15:0] pyc_comb_406; // op=pyc.comb +wire [18:0] pyc_comb_407; // op=pyc.comb +wire [15:0] pyc_comb_408; // op=pyc.comb +wire [18:0] pyc_comb_409; // op=pyc.comb +wire [1:0] pyc_comb_41; // op=pyc.comb +wire [15:0] pyc_comb_410; // op=pyc.comb +wire [18:0] pyc_comb_411; // op=pyc.comb +wire [15:0] pyc_comb_412; // op=pyc.comb +wire [18:0] pyc_comb_413; // op=pyc.comb +wire [15:0] pyc_comb_414; // op=pyc.comb +wire [18:0] pyc_comb_415; // op=pyc.comb +wire [15:0] pyc_comb_416; // op=pyc.comb +wire [18:0] pyc_comb_417; // op=pyc.comb +wire [15:0] pyc_comb_418; // op=pyc.comb +wire [18:0] pyc_comb_419; // op=pyc.comb +wire [15:0] pyc_comb_420; // op=pyc.comb +wire [18:0] pyc_comb_421; // op=pyc.comb +wire [15:0] pyc_comb_422; // op=pyc.comb +wire pyc_comb_424; // op=pyc.comb +wire pyc_comb_426; // op=pyc.comb +wire pyc_comb_428; // op=pyc.comb +wire [1:0] pyc_comb_43; // op=pyc.comb +wire pyc_comb_430; // op=pyc.comb +wire [1:0] pyc_comb_432; // op=pyc.comb +wire [1:0] pyc_comb_434; // op=pyc.comb +wire [1:0] pyc_comb_436; // op=pyc.comb +wire pyc_comb_521; // op=pyc.comb +wire pyc_comb_522; // op=pyc.comb +wire [2:0] pyc_comb_523; // op=pyc.comb +wire [2:0] pyc_comb_524; // op=pyc.comb +wire pyc_comb_529; // op=pyc.comb +wire pyc_comb_530; // op=pyc.comb +wire pyc_comb_531; // op=pyc.comb +wire [18:0] pyc_comb_591; // op=pyc.comb +wire [15:0] pyc_comb_592; // op=pyc.comb +wire [15:0] pyc_comb_596; // op=pyc.comb +wire [15:0] pyc_comb_597; // op=pyc.comb +wire [7:0] pyc_concat_102; // op=pyc.concat +wire [7:0] pyc_concat_109; // op=pyc.concat +wire [7:0] pyc_concat_128; // op=pyc.concat +wire [7:0] pyc_concat_135; // op=pyc.concat +wire [7:0] pyc_concat_154; // op=pyc.concat wire [7:0] pyc_concat_157; // op=pyc.concat -wire [7:0] pyc_concat_159; // op=pyc.concat -wire [7:0] pyc_concat_178; // op=pyc.concat -wire [7:0] pyc_concat_180; // op=pyc.concat -wire [7:0] pyc_concat_199; // op=pyc.concat +wire [7:0] pyc_concat_176; // op=pyc.concat +wire [7:0] pyc_concat_179; // op=pyc.concat +wire [7:0] pyc_concat_198; // op=pyc.concat wire [7:0] pyc_concat_201; // op=pyc.concat wire [7:0] pyc_concat_220; // op=pyc.concat -wire [7:0] pyc_concat_224; // op=pyc.concat -wire [2:0] pyc_concat_495; // op=pyc.concat -wire [2:0] pyc_concat_496; // op=pyc.concat +wire [7:0] pyc_concat_225; // op=pyc.concat +wire [7:0] pyc_concat_50; // op=pyc.concat +wire [2:0] pyc_concat_519; // op=pyc.concat +wire [2:0] pyc_concat_520; // op=pyc.concat wire [7:0] pyc_concat_57; // op=pyc.concat -wire [7:0] pyc_concat_63; // op=pyc.concat -wire [7:0] pyc_concat_82; // op=pyc.concat -wire [7:0] pyc_concat_88; // op=pyc.concat -wire [18:0] pyc_constant_1; // op=pyc.constant -wire pyc_constant_10; // op=pyc.constant +wire [7:0] pyc_concat_76; // op=pyc.concat +wire [7:0] pyc_concat_83; // op=pyc.concat +wire [1:0] pyc_constant_1; // op=pyc.constant wire [15:0] pyc_constant_2; // op=pyc.constant -wire [1:0] pyc_constant_3; // op=pyc.constant -wire [31:0] pyc_constant_4; // op=pyc.constant -wire [1:0] pyc_constant_5; // op=pyc.constant -wire [79:0] pyc_constant_6; // op=pyc.constant -wire [1:0] pyc_constant_7; // op=pyc.constant -wire [1:0] pyc_constant_8; // op=pyc.constant -wire pyc_constant_9; // op=pyc.constant +wire [18:0] pyc_constant_3; // op=pyc.constant +wire [1:0] pyc_constant_4; // op=pyc.constant +wire [79:0] pyc_constant_5; // op=pyc.constant +wire [1:0] pyc_constant_6; // op=pyc.constant +wire pyc_constant_7; // op=pyc.constant +wire pyc_constant_8; // op=pyc.constant +wire pyc_eq_10; // op=pyc.eq wire pyc_eq_11; // op=pyc.eq -wire pyc_eq_12; // op=pyc.eq -wire pyc_eq_13; // op=pyc.eq -wire pyc_eq_14; // op=pyc.eq -wire pyc_eq_532; // op=pyc.eq -wire pyc_eq_533; // op=pyc.eq -wire pyc_eq_538; // op=pyc.eq -wire pyc_eq_539; // op=pyc.eq -wire pyc_eq_551; // op=pyc.eq -wire pyc_eq_552; // op=pyc.eq -wire pyc_eq_557; // op=pyc.eq -wire pyc_eq_558; // op=pyc.eq -wire [4:0] pyc_extract_103; // op=pyc.extract -wire [4:0] pyc_extract_104; // op=pyc.extract -wire [3:0] pyc_extract_105; // op=pyc.extract -wire [3:0] pyc_extract_106; // op=pyc.extract -wire [4:0] pyc_extract_109; // op=pyc.extract -wire [4:0] pyc_extract_110; // op=pyc.extract -wire [3:0] pyc_extract_111; // op=pyc.extract +wire pyc_eq_554; // op=pyc.eq +wire pyc_eq_555; // op=pyc.eq +wire pyc_eq_560; // op=pyc.eq +wire pyc_eq_561; // op=pyc.eq +wire pyc_eq_573; // op=pyc.eq +wire pyc_eq_574; // op=pyc.eq +wire pyc_eq_579; // op=pyc.eq +wire pyc_eq_580; // op=pyc.eq +wire pyc_eq_9; // op=pyc.eq +wire [3:0] pyc_extract_100; // op=pyc.extract +wire [3:0] pyc_extract_101; // op=pyc.extract +wire [4:0] pyc_extract_105; // op=pyc.extract +wire [4:0] pyc_extract_106; // op=pyc.extract +wire [3:0] pyc_extract_107; // op=pyc.extract +wire [3:0] pyc_extract_108; // op=pyc.extract +wire [4:0] pyc_extract_111; // op=pyc.extract wire [3:0] pyc_extract_112; // op=pyc.extract -wire [4:0] pyc_extract_115; // op=pyc.extract -wire [3:0] pyc_extract_116; // op=pyc.extract -wire [4:0] pyc_extract_118; // op=pyc.extract -wire [3:0] pyc_extract_119; // op=pyc.extract -wire [4:0] pyc_extract_128; // op=pyc.extract -wire [4:0] pyc_extract_129; // op=pyc.extract -wire [3:0] pyc_extract_130; // op=pyc.extract -wire [3:0] pyc_extract_131; // op=pyc.extract -wire [4:0] pyc_extract_134; // op=pyc.extract -wire [4:0] pyc_extract_135; // op=pyc.extract -wire [3:0] pyc_extract_136; // op=pyc.extract -wire [3:0] pyc_extract_137; // op=pyc.extract +wire [4:0] pyc_extract_114; // op=pyc.extract +wire [3:0] pyc_extract_115; // op=pyc.extract +wire [4:0] pyc_extract_124; // op=pyc.extract +wire [4:0] pyc_extract_125; // op=pyc.extract +wire [3:0] pyc_extract_126; // op=pyc.extract +wire [3:0] pyc_extract_127; // op=pyc.extract +wire [4:0] pyc_extract_131; // op=pyc.extract +wire [4:0] pyc_extract_132; // op=pyc.extract +wire [3:0] pyc_extract_133; // op=pyc.extract +wire [3:0] pyc_extract_134; // op=pyc.extract +wire [4:0] pyc_extract_137; // op=pyc.extract +wire [3:0] pyc_extract_138; // op=pyc.extract wire [4:0] pyc_extract_140; // op=pyc.extract wire [3:0] pyc_extract_141; // op=pyc.extract -wire [4:0] pyc_extract_143; // op=pyc.extract -wire [3:0] pyc_extract_144; // op=pyc.extract -wire [4:0] pyc_extract_153; // op=pyc.extract -wire [4:0] pyc_extract_154; // op=pyc.extract -wire [3:0] pyc_extract_155; // op=pyc.extract -wire [3:0] pyc_extract_156; // op=pyc.extract -wire [4:0] pyc_extract_161; // op=pyc.extract -wire [3:0] pyc_extract_162; // op=pyc.extract -wire [4:0] pyc_extract_164; // op=pyc.extract -wire [3:0] pyc_extract_165; // op=pyc.extract -wire [4:0] pyc_extract_174; // op=pyc.extract -wire [4:0] pyc_extract_175; // op=pyc.extract -wire [3:0] pyc_extract_176; // op=pyc.extract -wire [3:0] pyc_extract_177; // op=pyc.extract -wire [4:0] pyc_extract_182; // op=pyc.extract -wire [3:0] pyc_extract_183; // op=pyc.extract -wire [4:0] pyc_extract_185; // op=pyc.extract -wire [3:0] pyc_extract_186; // op=pyc.extract +wire [4:0] pyc_extract_150; // op=pyc.extract +wire [4:0] pyc_extract_151; // op=pyc.extract +wire [3:0] pyc_extract_152; // op=pyc.extract +wire [3:0] pyc_extract_153; // op=pyc.extract +wire [4:0] pyc_extract_159; // op=pyc.extract +wire [3:0] pyc_extract_160; // op=pyc.extract +wire [4:0] pyc_extract_162; // op=pyc.extract +wire [3:0] pyc_extract_163; // op=pyc.extract +wire [4:0] pyc_extract_172; // op=pyc.extract +wire [4:0] pyc_extract_173; // op=pyc.extract +wire [3:0] pyc_extract_174; // op=pyc.extract +wire [3:0] pyc_extract_175; // op=pyc.extract +wire [4:0] pyc_extract_181; // op=pyc.extract +wire [3:0] pyc_extract_182; // op=pyc.extract +wire [4:0] pyc_extract_184; // op=pyc.extract +wire [3:0] pyc_extract_185; // op=pyc.extract +wire [4:0] pyc_extract_194; // op=pyc.extract wire [4:0] pyc_extract_195; // op=pyc.extract -wire [4:0] pyc_extract_196; // op=pyc.extract +wire [3:0] pyc_extract_196; // op=pyc.extract wire [3:0] pyc_extract_197; // op=pyc.extract -wire [3:0] pyc_extract_198; // op=pyc.extract wire [4:0] pyc_extract_203; // op=pyc.extract wire [3:0] pyc_extract_204; // op=pyc.extract wire [4:0] pyc_extract_206; // op=pyc.extract @@ -463,479 +444,505 @@ wire [4:0] pyc_extract_216; // op=pyc.extract wire [4:0] pyc_extract_217; // op=pyc.extract wire [3:0] pyc_extract_218; // op=pyc.extract wire [3:0] pyc_extract_219; // op=pyc.extract -wire [4:0] pyc_extract_222; // op=pyc.extract -wire [3:0] pyc_extract_223; // op=pyc.extract -wire [4:0] pyc_extract_226; // op=pyc.extract -wire [3:0] pyc_extract_227; // op=pyc.extract -wire [4:0] pyc_extract_239; // op=pyc.extract -wire [4:0] pyc_extract_245; // op=pyc.extract -wire [4:0] pyc_extract_251; // op=pyc.extract -wire [4:0] pyc_extract_257; // op=pyc.extract -wire [4:0] pyc_extract_263; // op=pyc.extract +wire [4:0] pyc_extract_223; // op=pyc.extract +wire [3:0] pyc_extract_224; // op=pyc.extract +wire [4:0] pyc_extract_227; // op=pyc.extract +wire [3:0] pyc_extract_228; // op=pyc.extract +wire [4:0] pyc_extract_241; // op=pyc.extract +wire [4:0] pyc_extract_248; // op=pyc.extract +wire [4:0] pyc_extract_255; // op=pyc.extract +wire [4:0] pyc_extract_262; // op=pyc.extract wire [4:0] pyc_extract_269; // op=pyc.extract -wire [4:0] pyc_extract_275; // op=pyc.extract -wire [4:0] pyc_extract_281; // op=pyc.extract -wire [4:0] pyc_extract_286; // op=pyc.extract -wire [4:0] pyc_extract_291; // op=pyc.extract -wire [4:0] pyc_extract_296; // op=pyc.extract -wire [4:0] pyc_extract_301; // op=pyc.extract -wire [4:0] pyc_extract_306; // op=pyc.extract +wire [4:0] pyc_extract_276; // op=pyc.extract +wire [4:0] pyc_extract_283; // op=pyc.extract +wire [4:0] pyc_extract_290; // op=pyc.extract +wire [4:0] pyc_extract_297; // op=pyc.extract +wire [4:0] pyc_extract_304; // op=pyc.extract wire [4:0] pyc_extract_311; // op=pyc.extract -wire [4:0] pyc_extract_316; // op=pyc.extract -wire [4:0] pyc_extract_321; // op=pyc.extract -wire pyc_extract_502; // op=pyc.extract -wire pyc_extract_503; // op=pyc.extract -wire pyc_extract_504; // op=pyc.extract -wire [39:0] pyc_extract_52; // op=pyc.extract -wire pyc_extract_522; // op=pyc.extract -wire pyc_extract_524; // op=pyc.extract +wire [4:0] pyc_extract_318; // op=pyc.extract +wire [4:0] pyc_extract_325; // op=pyc.extract +wire [4:0] pyc_extract_332; // op=pyc.extract +wire [4:0] pyc_extract_339; // op=pyc.extract +wire [4:0] pyc_extract_346; // op=pyc.extract +wire [39:0] pyc_extract_45; // op=pyc.extract +wire [4:0] pyc_extract_46; // op=pyc.extract +wire [4:0] pyc_extract_47; // op=pyc.extract +wire [3:0] pyc_extract_48; // op=pyc.extract +wire [3:0] pyc_extract_49; // op=pyc.extract +wire pyc_extract_526; // op=pyc.extract wire pyc_extract_527; // op=pyc.extract -wire pyc_extract_529; // op=pyc.extract +wire pyc_extract_528; // op=pyc.extract wire [4:0] pyc_extract_53; // op=pyc.extract wire [4:0] pyc_extract_54; // op=pyc.extract -wire pyc_extract_545; // op=pyc.extract -wire pyc_extract_548; // op=pyc.extract +wire pyc_extract_544; // op=pyc.extract +wire pyc_extract_546; // op=pyc.extract +wire pyc_extract_549; // op=pyc.extract wire [3:0] pyc_extract_55; // op=pyc.extract +wire pyc_extract_551; // op=pyc.extract wire [3:0] pyc_extract_56; // op=pyc.extract -wire [18:0] pyc_extract_575; // op=pyc.extract -wire [15:0] pyc_extract_576; // op=pyc.extract +wire pyc_extract_567; // op=pyc.extract +wire pyc_extract_570; // op=pyc.extract wire [4:0] pyc_extract_59; // op=pyc.extract -wire [4:0] pyc_extract_60; // op=pyc.extract -wire [3:0] pyc_extract_61; // op=pyc.extract -wire [3:0] pyc_extract_62; // op=pyc.extract -wire [4:0] pyc_extract_65; // op=pyc.extract -wire [3:0] pyc_extract_66; // op=pyc.extract -wire [4:0] pyc_extract_68; // op=pyc.extract -wire [3:0] pyc_extract_69; // op=pyc.extract -wire [4:0] pyc_extract_78; // op=pyc.extract +wire [3:0] pyc_extract_60; // op=pyc.extract +wire [4:0] pyc_extract_62; // op=pyc.extract +wire [3:0] pyc_extract_63; // op=pyc.extract +wire [4:0] pyc_extract_72; // op=pyc.extract +wire [4:0] pyc_extract_73; // op=pyc.extract +wire [3:0] pyc_extract_74; // op=pyc.extract +wire [3:0] pyc_extract_75; // op=pyc.extract wire [4:0] pyc_extract_79; // op=pyc.extract -wire [3:0] pyc_extract_80; // op=pyc.extract +wire [4:0] pyc_extract_80; // op=pyc.extract wire [3:0] pyc_extract_81; // op=pyc.extract -wire [4:0] pyc_extract_84; // op=pyc.extract +wire [3:0] pyc_extract_82; // op=pyc.extract wire [4:0] pyc_extract_85; // op=pyc.extract wire [3:0] pyc_extract_86; // op=pyc.extract -wire [3:0] pyc_extract_87; // op=pyc.extract -wire [4:0] pyc_extract_90; // op=pyc.extract -wire [3:0] pyc_extract_91; // op=pyc.extract -wire [4:0] pyc_extract_93; // op=pyc.extract -wire [3:0] pyc_extract_94; // op=pyc.extract -wire [31:0] pyc_instance_485; // op=pyc.instance -wire [31:0] pyc_instance_486; // op=pyc.instance -wire [31:0] pyc_instance_487; // op=pyc.instance -wire [31:0] pyc_instance_488; // op=pyc.instance -wire [31:0] pyc_instance_489; // op=pyc.instance -wire [31:0] pyc_instance_490; // op=pyc.instance -wire [31:0] pyc_instance_491; // op=pyc.instance -wire [31:0] pyc_instance_492; // op=pyc.instance -wire [31:0] pyc_instance_493; // op=pyc.instance -wire [31:0] pyc_mul_100; // op=pyc.mul -wire [31:0] pyc_mul_101; // op=pyc.mul -wire [31:0] pyc_mul_102; // op=pyc.mul -wire [31:0] pyc_mul_123; // op=pyc.mul -wire [31:0] pyc_mul_124; // op=pyc.mul -wire [31:0] pyc_mul_125; // op=pyc.mul -wire [31:0] pyc_mul_126; // op=pyc.mul -wire [31:0] pyc_mul_127; // op=pyc.mul -wire [31:0] pyc_mul_148; // op=pyc.mul -wire [31:0] pyc_mul_149; // op=pyc.mul -wire [31:0] pyc_mul_150; // op=pyc.mul -wire [31:0] pyc_mul_151; // op=pyc.mul -wire [31:0] pyc_mul_152; // op=pyc.mul -wire [31:0] pyc_mul_169; // op=pyc.mul -wire [31:0] pyc_mul_170; // op=pyc.mul -wire [31:0] pyc_mul_171; // op=pyc.mul -wire [31:0] pyc_mul_172; // op=pyc.mul -wire [31:0] pyc_mul_173; // op=pyc.mul -wire [31:0] pyc_mul_190; // op=pyc.mul -wire [31:0] pyc_mul_191; // op=pyc.mul -wire [31:0] pyc_mul_192; // op=pyc.mul -wire [31:0] pyc_mul_193; // op=pyc.mul -wire [31:0] pyc_mul_194; // op=pyc.mul -wire [31:0] pyc_mul_211; // op=pyc.mul -wire [31:0] pyc_mul_212; // op=pyc.mul -wire [31:0] pyc_mul_213; // op=pyc.mul -wire [31:0] pyc_mul_214; // op=pyc.mul -wire [31:0] pyc_mul_215; // op=pyc.mul -wire [31:0] pyc_mul_232; // op=pyc.mul -wire [31:0] pyc_mul_233; // op=pyc.mul -wire [31:0] pyc_mul_234; // op=pyc.mul -wire [31:0] pyc_mul_235; // op=pyc.mul -wire [31:0] pyc_mul_236; // op=pyc.mul -wire [31:0] pyc_mul_241; // op=pyc.mul -wire [31:0] pyc_mul_242; // op=pyc.mul -wire [31:0] pyc_mul_247; // op=pyc.mul -wire [31:0] pyc_mul_248; // op=pyc.mul -wire [31:0] pyc_mul_253; // op=pyc.mul -wire [31:0] pyc_mul_254; // op=pyc.mul -wire [31:0] pyc_mul_259; // op=pyc.mul -wire [31:0] pyc_mul_260; // op=pyc.mul -wire [31:0] pyc_mul_265; // op=pyc.mul -wire [31:0] pyc_mul_266; // op=pyc.mul -wire [31:0] pyc_mul_271; // op=pyc.mul -wire [31:0] pyc_mul_272; // op=pyc.mul -wire [31:0] pyc_mul_277; // op=pyc.mul -wire [31:0] pyc_mul_278; // op=pyc.mul -wire [31:0] pyc_mul_283; // op=pyc.mul -wire [31:0] pyc_mul_284; // op=pyc.mul -wire [31:0] pyc_mul_288; // op=pyc.mul -wire [31:0] pyc_mul_289; // op=pyc.mul -wire [31:0] pyc_mul_293; // op=pyc.mul -wire [31:0] pyc_mul_294; // op=pyc.mul -wire [31:0] pyc_mul_298; // op=pyc.mul -wire [31:0] pyc_mul_299; // op=pyc.mul -wire [31:0] pyc_mul_303; // op=pyc.mul -wire [31:0] pyc_mul_304; // op=pyc.mul -wire [31:0] pyc_mul_308; // op=pyc.mul -wire [31:0] pyc_mul_309; // op=pyc.mul -wire [31:0] pyc_mul_313; // op=pyc.mul -wire [31:0] pyc_mul_314; // op=pyc.mul -wire [31:0] pyc_mul_318; // op=pyc.mul -wire [31:0] pyc_mul_319; // op=pyc.mul -wire [31:0] pyc_mul_323; // op=pyc.mul -wire [31:0] pyc_mul_324; // op=pyc.mul -wire [31:0] pyc_mul_73; // op=pyc.mul -wire [31:0] pyc_mul_74; // op=pyc.mul -wire [31:0] pyc_mul_75; // op=pyc.mul -wire [31:0] pyc_mul_76; // op=pyc.mul -wire [31:0] pyc_mul_77; // op=pyc.mul -wire [31:0] pyc_mul_98; // op=pyc.mul -wire [31:0] pyc_mul_99; // op=pyc.mul -wire [31:0] pyc_mux_536; // op=pyc.mux -wire [31:0] pyc_mux_537; // op=pyc.mux -wire [31:0] pyc_mux_542; // op=pyc.mux -wire [31:0] pyc_mux_543; // op=pyc.mux -wire [31:0] pyc_mux_555; // op=pyc.mux -wire [31:0] pyc_mux_556; // op=pyc.mux -wire [31:0] pyc_mux_561; // op=pyc.mux -wire [31:0] pyc_mux_562; // op=pyc.mux -wire [31:0] pyc_mux_564; // op=pyc.mux -wire [31:0] pyc_mux_565; // op=pyc.mux -wire [31:0] pyc_mux_566; // op=pyc.mux -wire [31:0] pyc_mux_572; // op=pyc.mux -wire [31:0] pyc_mux_573; // op=pyc.mux -wire [31:0] pyc_mux_574; // op=pyc.mux -wire [15:0] pyc_mux_580; // op=pyc.mux -wire [15:0] pyc_mux_581; // op=pyc.mux -wire pyc_reg_34; // op=pyc.reg -wire pyc_reg_36; // op=pyc.reg -wire pyc_reg_38; // op=pyc.reg -wire pyc_reg_398; // op=pyc.reg -wire pyc_reg_40; // op=pyc.reg -wire pyc_reg_400; // op=pyc.reg -wire pyc_reg_402; // op=pyc.reg -wire pyc_reg_404; // op=pyc.reg -wire pyc_reg_406; // op=pyc.reg -wire [1:0] pyc_reg_407; // op=pyc.reg -wire [1:0] pyc_reg_409; // op=pyc.reg -wire [1:0] pyc_reg_411; // op=pyc.reg -wire [31:0] pyc_reg_413; // op=pyc.reg -wire [31:0] pyc_reg_414; // op=pyc.reg -wire [31:0] pyc_reg_415; // op=pyc.reg -wire [31:0] pyc_reg_416; // op=pyc.reg -wire [31:0] pyc_reg_417; // op=pyc.reg -wire [31:0] pyc_reg_418; // op=pyc.reg -wire [31:0] pyc_reg_419; // op=pyc.reg -wire pyc_reg_42; // op=pyc.reg -wire [31:0] pyc_reg_420; // op=pyc.reg -wire [31:0] pyc_reg_421; // op=pyc.reg -wire [31:0] pyc_reg_422; // op=pyc.reg -wire [31:0] pyc_reg_423; // op=pyc.reg -wire [31:0] pyc_reg_424; // op=pyc.reg -wire [31:0] pyc_reg_425; // op=pyc.reg -wire [31:0] pyc_reg_426; // op=pyc.reg -wire [31:0] pyc_reg_427; // op=pyc.reg -wire [31:0] pyc_reg_428; // op=pyc.reg -wire [31:0] pyc_reg_429; // op=pyc.reg -wire [31:0] pyc_reg_430; // op=pyc.reg -wire [31:0] pyc_reg_431; // op=pyc.reg -wire [31:0] pyc_reg_432; // op=pyc.reg -wire [31:0] pyc_reg_433; // op=pyc.reg -wire [31:0] pyc_reg_434; // op=pyc.reg -wire [31:0] pyc_reg_435; // op=pyc.reg -wire [31:0] pyc_reg_436; // op=pyc.reg -wire [31:0] pyc_reg_437; // op=pyc.reg -wire [31:0] pyc_reg_438; // op=pyc.reg -wire [31:0] pyc_reg_439; // op=pyc.reg -wire [79:0] pyc_reg_44; // op=pyc.reg -wire [31:0] pyc_reg_440; // op=pyc.reg -wire [31:0] pyc_reg_441; // op=pyc.reg -wire [31:0] pyc_reg_442; // op=pyc.reg -wire [31:0] pyc_reg_443; // op=pyc.reg -wire [31:0] pyc_reg_444; // op=pyc.reg -wire [31:0] pyc_reg_445; // op=pyc.reg -wire [31:0] pyc_reg_446; // op=pyc.reg -wire [31:0] pyc_reg_447; // op=pyc.reg -wire [31:0] pyc_reg_448; // op=pyc.reg -wire [31:0] pyc_reg_449; // op=pyc.reg -wire [79:0] pyc_reg_45; // op=pyc.reg -wire [31:0] pyc_reg_450; // op=pyc.reg -wire [31:0] pyc_reg_451; // op=pyc.reg -wire [31:0] pyc_reg_452; // op=pyc.reg -wire [31:0] pyc_reg_453; // op=pyc.reg -wire [31:0] pyc_reg_454; // op=pyc.reg -wire [31:0] pyc_reg_455; // op=pyc.reg -wire [31:0] pyc_reg_456; // op=pyc.reg -wire [31:0] pyc_reg_457; // op=pyc.reg -wire [31:0] pyc_reg_458; // op=pyc.reg -wire [31:0] pyc_reg_459; // op=pyc.reg -wire [79:0] pyc_reg_46; // op=pyc.reg -wire [31:0] pyc_reg_460; // op=pyc.reg -wire [31:0] pyc_reg_461; // op=pyc.reg -wire [31:0] pyc_reg_462; // op=pyc.reg -wire [31:0] pyc_reg_463; // op=pyc.reg -wire [31:0] pyc_reg_464; // op=pyc.reg -wire [31:0] pyc_reg_465; // op=pyc.reg -wire [31:0] pyc_reg_466; // op=pyc.reg -wire [31:0] pyc_reg_467; // op=pyc.reg -wire [31:0] pyc_reg_468; // op=pyc.reg -wire [31:0] pyc_reg_469; // op=pyc.reg -wire [1:0] pyc_reg_47; // op=pyc.reg -wire [31:0] pyc_reg_470; // op=pyc.reg -wire [31:0] pyc_reg_471; // op=pyc.reg -wire [31:0] pyc_reg_472; // op=pyc.reg -wire [31:0] pyc_reg_473; // op=pyc.reg -wire [31:0] pyc_reg_474; // op=pyc.reg -wire [31:0] pyc_reg_475; // op=pyc.reg -wire [31:0] pyc_reg_476; // op=pyc.reg -wire [31:0] pyc_reg_477; // op=pyc.reg -wire [31:0] pyc_reg_478; // op=pyc.reg -wire [31:0] pyc_reg_479; // op=pyc.reg -wire [31:0] pyc_reg_480; // op=pyc.reg -wire [31:0] pyc_reg_481; // op=pyc.reg -wire [31:0] pyc_reg_482; // op=pyc.reg -wire [31:0] pyc_reg_483; // op=pyc.reg -wire [31:0] pyc_reg_484; // op=pyc.reg -wire [1:0] pyc_reg_49; // op=pyc.reg -wire pyc_reg_494; // op=pyc.reg -wire [2:0] pyc_reg_501; // op=pyc.reg -wire [1:0] pyc_reg_508; // op=pyc.reg -wire [1:0] pyc_reg_509; // op=pyc.reg -wire [1:0] pyc_reg_51; // op=pyc.reg -wire [1:0] pyc_reg_510; // op=pyc.reg -wire [31:0] pyc_reg_511; // op=pyc.reg -wire [31:0] pyc_reg_514; // op=pyc.reg -wire [31:0] pyc_reg_515; // op=pyc.reg -wire [31:0] pyc_reg_516; // op=pyc.reg -wire [31:0] pyc_reg_517; // op=pyc.reg -wire [31:0] pyc_reg_518; // op=pyc.reg -wire [31:0] pyc_reg_519; // op=pyc.reg -wire [31:0] pyc_reg_520; // op=pyc.reg -wire [31:0] pyc_reg_521; // op=pyc.reg -wire [31:0] pyc_reg_569; // op=pyc.reg -wire [31:0] pyc_reg_571; // op=pyc.reg -wire [15:0] pyc_reg_579; // op=pyc.reg -wire pyc_reg_584; // op=pyc.reg -wire [18:0] pyc_reg_585; // op=pyc.reg -wire [31:0] pyc_sext_108; // op=pyc.sext -wire [31:0] pyc_sext_114; // op=pyc.sext -wire [31:0] pyc_sext_117; // op=pyc.sext -wire [31:0] pyc_sext_120; // op=pyc.sext -wire [31:0] pyc_sext_121; // op=pyc.sext -wire [31:0] pyc_sext_122; // op=pyc.sext -wire [31:0] pyc_sext_133; // op=pyc.sext -wire [31:0] pyc_sext_139; // op=pyc.sext -wire [31:0] pyc_sext_142; // op=pyc.sext -wire [31:0] pyc_sext_145; // op=pyc.sext -wire [31:0] pyc_sext_146; // op=pyc.sext -wire [31:0] pyc_sext_147; // op=pyc.sext -wire [31:0] pyc_sext_158; // op=pyc.sext -wire [31:0] pyc_sext_160; // op=pyc.sext -wire [31:0] pyc_sext_163; // op=pyc.sext -wire [31:0] pyc_sext_166; // op=pyc.sext -wire [31:0] pyc_sext_167; // op=pyc.sext -wire [31:0] pyc_sext_168; // op=pyc.sext -wire [31:0] pyc_sext_179; // op=pyc.sext -wire [31:0] pyc_sext_181; // op=pyc.sext -wire [31:0] pyc_sext_184; // op=pyc.sext -wire [31:0] pyc_sext_187; // op=pyc.sext -wire [31:0] pyc_sext_188; // op=pyc.sext -wire [31:0] pyc_sext_189; // op=pyc.sext -wire [31:0] pyc_sext_200; // op=pyc.sext -wire [31:0] pyc_sext_202; // op=pyc.sext -wire [31:0] pyc_sext_205; // op=pyc.sext -wire [31:0] pyc_sext_208; // op=pyc.sext -wire [31:0] pyc_sext_209; // op=pyc.sext -wire [31:0] pyc_sext_210; // op=pyc.sext -wire [31:0] pyc_sext_221; // op=pyc.sext -wire [31:0] pyc_sext_225; // op=pyc.sext -wire [31:0] pyc_sext_228; // op=pyc.sext -wire [31:0] pyc_sext_229; // op=pyc.sext -wire [31:0] pyc_sext_230; // op=pyc.sext -wire [31:0] pyc_sext_231; // op=pyc.sext -wire [31:0] pyc_sext_237; // op=pyc.sext -wire [31:0] pyc_sext_238; // op=pyc.sext -wire [31:0] pyc_sext_240; // op=pyc.sext -wire [31:0] pyc_sext_243; // op=pyc.sext -wire [31:0] pyc_sext_244; // op=pyc.sext -wire [31:0] pyc_sext_246; // op=pyc.sext -wire [31:0] pyc_sext_249; // op=pyc.sext -wire [31:0] pyc_sext_250; // op=pyc.sext -wire [31:0] pyc_sext_252; // op=pyc.sext -wire [31:0] pyc_sext_255; // op=pyc.sext -wire [31:0] pyc_sext_256; // op=pyc.sext -wire [31:0] pyc_sext_258; // op=pyc.sext -wire [31:0] pyc_sext_261; // op=pyc.sext -wire [31:0] pyc_sext_262; // op=pyc.sext -wire [31:0] pyc_sext_264; // op=pyc.sext -wire [31:0] pyc_sext_267; // op=pyc.sext -wire [31:0] pyc_sext_268; // op=pyc.sext -wire [31:0] pyc_sext_270; // op=pyc.sext -wire [31:0] pyc_sext_273; // op=pyc.sext -wire [31:0] pyc_sext_274; // op=pyc.sext -wire [31:0] pyc_sext_276; // op=pyc.sext -wire [31:0] pyc_sext_279; // op=pyc.sext -wire [31:0] pyc_sext_280; // op=pyc.sext -wire [31:0] pyc_sext_282; // op=pyc.sext -wire [31:0] pyc_sext_285; // op=pyc.sext -wire [31:0] pyc_sext_287; // op=pyc.sext -wire [31:0] pyc_sext_290; // op=pyc.sext -wire [31:0] pyc_sext_292; // op=pyc.sext -wire [31:0] pyc_sext_295; // op=pyc.sext -wire [31:0] pyc_sext_297; // op=pyc.sext -wire [31:0] pyc_sext_300; // op=pyc.sext -wire [31:0] pyc_sext_302; // op=pyc.sext -wire [31:0] pyc_sext_305; // op=pyc.sext -wire [31:0] pyc_sext_307; // op=pyc.sext -wire [31:0] pyc_sext_310; // op=pyc.sext -wire [31:0] pyc_sext_312; // op=pyc.sext -wire [31:0] pyc_sext_315; // op=pyc.sext -wire [31:0] pyc_sext_317; // op=pyc.sext -wire [31:0] pyc_sext_320; // op=pyc.sext -wire [31:0] pyc_sext_322; // op=pyc.sext -wire [31:0] pyc_sext_58; // op=pyc.sext -wire [31:0] pyc_sext_64; // op=pyc.sext -wire [31:0] pyc_sext_67; // op=pyc.sext -wire [31:0] pyc_sext_70; // op=pyc.sext -wire [31:0] pyc_sext_71; // op=pyc.sext -wire [31:0] pyc_sext_72; // op=pyc.sext -wire [31:0] pyc_sext_83; // op=pyc.sext -wire [31:0] pyc_sext_89; // op=pyc.sext -wire [31:0] pyc_sext_92; // op=pyc.sext -wire [31:0] pyc_sext_95; // op=pyc.sext -wire [31:0] pyc_sext_96; // op=pyc.sext -wire [31:0] pyc_sext_97; // op=pyc.sext -wire [31:0] pyc_shli_534; // op=pyc.shli -wire [31:0] pyc_shli_535; // op=pyc.shli -wire [31:0] pyc_shli_540; // op=pyc.shli -wire [31:0] pyc_shli_541; // op=pyc.shli -wire [31:0] pyc_shli_553; // op=pyc.shli -wire [31:0] pyc_shli_554; // op=pyc.shli -wire [31:0] pyc_shli_559; // op=pyc.shli -wire [31:0] pyc_shli_560; // op=pyc.shli -wire [1:0] pyc_zext_523; // op=pyc.zext -wire [1:0] pyc_zext_525; // op=pyc.zext -wire [1:0] pyc_zext_528; // op=pyc.zext -wire [1:0] pyc_zext_530; // op=pyc.zext -wire [1:0] pyc_zext_546; // op=pyc.zext -wire [1:0] pyc_zext_549; // op=pyc.zext +wire [4:0] pyc_extract_88; // op=pyc.extract +wire [3:0] pyc_extract_89; // op=pyc.extract +wire [4:0] pyc_extract_98; // op=pyc.extract +wire [4:0] pyc_extract_99; // op=pyc.extract +wire [18:0] pyc_instance_509; // op=pyc.instance +wire [18:0] pyc_instance_510; // op=pyc.instance +wire [15:0] pyc_instance_511; // op=pyc.instance +wire [18:0] pyc_instance_512; // op=pyc.instance +wire [15:0] pyc_instance_513; // op=pyc.instance +wire [18:0] pyc_instance_514; // op=pyc.instance +wire [18:0] pyc_instance_515; // op=pyc.instance +wire [15:0] pyc_instance_516; // op=pyc.instance +wire [15:0] pyc_instance_517; // op=pyc.instance +wire [18:0] pyc_mul_119; // op=pyc.mul +wire [18:0] pyc_mul_120; // op=pyc.mul +wire [15:0] pyc_mul_121; // op=pyc.mul +wire [18:0] pyc_mul_122; // op=pyc.mul +wire [15:0] pyc_mul_123; // op=pyc.mul +wire [18:0] pyc_mul_145; // op=pyc.mul +wire [18:0] pyc_mul_146; // op=pyc.mul +wire [15:0] pyc_mul_147; // op=pyc.mul +wire [18:0] pyc_mul_148; // op=pyc.mul +wire [15:0] pyc_mul_149; // op=pyc.mul +wire [18:0] pyc_mul_167; // op=pyc.mul +wire [18:0] pyc_mul_168; // op=pyc.mul +wire [15:0] pyc_mul_169; // op=pyc.mul +wire [18:0] pyc_mul_170; // op=pyc.mul +wire [15:0] pyc_mul_171; // op=pyc.mul +wire [18:0] pyc_mul_189; // op=pyc.mul +wire [18:0] pyc_mul_190; // op=pyc.mul +wire [15:0] pyc_mul_191; // op=pyc.mul +wire [18:0] pyc_mul_192; // op=pyc.mul +wire [15:0] pyc_mul_193; // op=pyc.mul +wire [18:0] pyc_mul_211; // op=pyc.mul +wire [18:0] pyc_mul_212; // op=pyc.mul +wire [15:0] pyc_mul_213; // op=pyc.mul +wire [18:0] pyc_mul_214; // op=pyc.mul +wire [15:0] pyc_mul_215; // op=pyc.mul +wire [18:0] pyc_mul_233; // op=pyc.mul +wire [18:0] pyc_mul_234; // op=pyc.mul +wire [15:0] pyc_mul_235; // op=pyc.mul +wire [18:0] pyc_mul_236; // op=pyc.mul +wire [15:0] pyc_mul_237; // op=pyc.mul +wire [18:0] pyc_mul_243; // op=pyc.mul +wire [15:0] pyc_mul_244; // op=pyc.mul +wire [18:0] pyc_mul_250; // op=pyc.mul +wire [15:0] pyc_mul_251; // op=pyc.mul +wire [18:0] pyc_mul_257; // op=pyc.mul +wire [15:0] pyc_mul_258; // op=pyc.mul +wire [18:0] pyc_mul_264; // op=pyc.mul +wire [15:0] pyc_mul_265; // op=pyc.mul +wire [18:0] pyc_mul_271; // op=pyc.mul +wire [15:0] pyc_mul_272; // op=pyc.mul +wire [18:0] pyc_mul_278; // op=pyc.mul +wire [15:0] pyc_mul_279; // op=pyc.mul +wire [18:0] pyc_mul_285; // op=pyc.mul +wire [15:0] pyc_mul_286; // op=pyc.mul +wire [18:0] pyc_mul_292; // op=pyc.mul +wire [15:0] pyc_mul_293; // op=pyc.mul +wire [18:0] pyc_mul_299; // op=pyc.mul +wire [15:0] pyc_mul_300; // op=pyc.mul +wire [18:0] pyc_mul_306; // op=pyc.mul +wire [15:0] pyc_mul_307; // op=pyc.mul +wire [18:0] pyc_mul_313; // op=pyc.mul +wire [15:0] pyc_mul_314; // op=pyc.mul +wire [18:0] pyc_mul_320; // op=pyc.mul +wire [15:0] pyc_mul_321; // op=pyc.mul +wire [18:0] pyc_mul_327; // op=pyc.mul +wire [15:0] pyc_mul_328; // op=pyc.mul +wire [18:0] pyc_mul_334; // op=pyc.mul +wire [15:0] pyc_mul_335; // op=pyc.mul +wire [18:0] pyc_mul_341; // op=pyc.mul +wire [15:0] pyc_mul_342; // op=pyc.mul +wire [18:0] pyc_mul_348; // op=pyc.mul +wire [15:0] pyc_mul_349; // op=pyc.mul +wire [18:0] pyc_mul_67; // op=pyc.mul +wire [18:0] pyc_mul_68; // op=pyc.mul +wire [15:0] pyc_mul_69; // op=pyc.mul +wire [18:0] pyc_mul_70; // op=pyc.mul +wire [15:0] pyc_mul_71; // op=pyc.mul +wire [18:0] pyc_mul_93; // op=pyc.mul +wire [18:0] pyc_mul_94; // op=pyc.mul +wire [15:0] pyc_mul_95; // op=pyc.mul +wire [18:0] pyc_mul_96; // op=pyc.mul +wire [15:0] pyc_mul_97; // op=pyc.mul +wire [18:0] pyc_mux_558; // op=pyc.mux +wire [18:0] pyc_mux_559; // op=pyc.mux +wire [18:0] pyc_mux_564; // op=pyc.mux +wire [18:0] pyc_mux_565; // op=pyc.mux +wire [15:0] pyc_mux_577; // op=pyc.mux +wire [15:0] pyc_mux_578; // op=pyc.mux +wire [15:0] pyc_mux_583; // op=pyc.mux +wire [15:0] pyc_mux_584; // op=pyc.mux +wire [18:0] pyc_mux_586; // op=pyc.mux +wire [18:0] pyc_mux_587; // op=pyc.mux +wire [18:0] pyc_mux_588; // op=pyc.mux +wire [15:0] pyc_mux_589; // op=pyc.mux +wire [15:0] pyc_mux_590; // op=pyc.mux +wire [15:0] pyc_mux_594; // op=pyc.mux +wire [15:0] pyc_mux_595; // op=pyc.mux +wire pyc_reg_29; // op=pyc.reg +wire pyc_reg_31; // op=pyc.reg +wire pyc_reg_33; // op=pyc.reg +wire pyc_reg_35; // op=pyc.reg +wire [79:0] pyc_reg_37; // op=pyc.reg +wire [79:0] pyc_reg_38; // op=pyc.reg +wire [79:0] pyc_reg_39; // op=pyc.reg +wire [1:0] pyc_reg_40; // op=pyc.reg +wire [1:0] pyc_reg_42; // op=pyc.reg +wire pyc_reg_423; // op=pyc.reg +wire pyc_reg_425; // op=pyc.reg +wire pyc_reg_427; // op=pyc.reg +wire pyc_reg_429; // op=pyc.reg +wire [1:0] pyc_reg_431; // op=pyc.reg +wire [1:0] pyc_reg_433; // op=pyc.reg +wire [1:0] pyc_reg_435; // op=pyc.reg +wire [18:0] pyc_reg_437; // op=pyc.reg +wire [18:0] pyc_reg_438; // op=pyc.reg +wire [18:0] pyc_reg_439; // op=pyc.reg +wire [1:0] pyc_reg_44; // op=pyc.reg +wire [18:0] pyc_reg_440; // op=pyc.reg +wire [18:0] pyc_reg_441; // op=pyc.reg +wire [18:0] pyc_reg_442; // op=pyc.reg +wire [18:0] pyc_reg_443; // op=pyc.reg +wire [18:0] pyc_reg_444; // op=pyc.reg +wire [18:0] pyc_reg_445; // op=pyc.reg +wire [18:0] pyc_reg_446; // op=pyc.reg +wire [18:0] pyc_reg_447; // op=pyc.reg +wire [18:0] pyc_reg_448; // op=pyc.reg +wire [18:0] pyc_reg_449; // op=pyc.reg +wire [18:0] pyc_reg_450; // op=pyc.reg +wire [18:0] pyc_reg_451; // op=pyc.reg +wire [18:0] pyc_reg_452; // op=pyc.reg +wire [15:0] pyc_reg_453; // op=pyc.reg +wire [15:0] pyc_reg_454; // op=pyc.reg +wire [15:0] pyc_reg_455; // op=pyc.reg +wire [15:0] pyc_reg_456; // op=pyc.reg +wire [15:0] pyc_reg_457; // op=pyc.reg +wire [15:0] pyc_reg_458; // op=pyc.reg +wire [15:0] pyc_reg_459; // op=pyc.reg +wire [15:0] pyc_reg_460; // op=pyc.reg +wire [18:0] pyc_reg_461; // op=pyc.reg +wire [18:0] pyc_reg_462; // op=pyc.reg +wire [18:0] pyc_reg_463; // op=pyc.reg +wire [18:0] pyc_reg_464; // op=pyc.reg +wire [18:0] pyc_reg_465; // op=pyc.reg +wire [18:0] pyc_reg_466; // op=pyc.reg +wire [18:0] pyc_reg_467; // op=pyc.reg +wire [18:0] pyc_reg_468; // op=pyc.reg +wire [15:0] pyc_reg_469; // op=pyc.reg +wire [15:0] pyc_reg_470; // op=pyc.reg +wire [15:0] pyc_reg_471; // op=pyc.reg +wire [15:0] pyc_reg_472; // op=pyc.reg +wire [15:0] pyc_reg_473; // op=pyc.reg +wire [15:0] pyc_reg_474; // op=pyc.reg +wire [15:0] pyc_reg_475; // op=pyc.reg +wire [15:0] pyc_reg_476; // op=pyc.reg +wire [18:0] pyc_reg_477; // op=pyc.reg +wire [18:0] pyc_reg_478; // op=pyc.reg +wire [18:0] pyc_reg_479; // op=pyc.reg +wire [18:0] pyc_reg_480; // op=pyc.reg +wire [18:0] pyc_reg_481; // op=pyc.reg +wire [18:0] pyc_reg_482; // op=pyc.reg +wire [18:0] pyc_reg_483; // op=pyc.reg +wire [18:0] pyc_reg_484; // op=pyc.reg +wire [18:0] pyc_reg_485; // op=pyc.reg +wire [18:0] pyc_reg_486; // op=pyc.reg +wire [18:0] pyc_reg_487; // op=pyc.reg +wire [18:0] pyc_reg_488; // op=pyc.reg +wire [18:0] pyc_reg_489; // op=pyc.reg +wire [18:0] pyc_reg_490; // op=pyc.reg +wire [18:0] pyc_reg_491; // op=pyc.reg +wire [18:0] pyc_reg_492; // op=pyc.reg +wire [15:0] pyc_reg_493; // op=pyc.reg +wire [15:0] pyc_reg_494; // op=pyc.reg +wire [15:0] pyc_reg_495; // op=pyc.reg +wire [15:0] pyc_reg_496; // op=pyc.reg +wire [15:0] pyc_reg_497; // op=pyc.reg +wire [15:0] pyc_reg_498; // op=pyc.reg +wire [15:0] pyc_reg_499; // op=pyc.reg +wire [15:0] pyc_reg_500; // op=pyc.reg +wire [15:0] pyc_reg_501; // op=pyc.reg +wire [15:0] pyc_reg_502; // op=pyc.reg +wire [15:0] pyc_reg_503; // op=pyc.reg +wire [15:0] pyc_reg_504; // op=pyc.reg +wire [15:0] pyc_reg_505; // op=pyc.reg +wire [15:0] pyc_reg_506; // op=pyc.reg +wire [15:0] pyc_reg_507; // op=pyc.reg +wire [15:0] pyc_reg_508; // op=pyc.reg +wire pyc_reg_518; // op=pyc.reg +wire [2:0] pyc_reg_525; // op=pyc.reg +wire [1:0] pyc_reg_532; // op=pyc.reg +wire [1:0] pyc_reg_533; // op=pyc.reg +wire [1:0] pyc_reg_534; // op=pyc.reg +wire [18:0] pyc_reg_535; // op=pyc.reg +wire [18:0] pyc_reg_536; // op=pyc.reg +wire [15:0] pyc_reg_537; // op=pyc.reg +wire [18:0] pyc_reg_538; // op=pyc.reg +wire [15:0] pyc_reg_539; // op=pyc.reg +wire [18:0] pyc_reg_540; // op=pyc.reg +wire [18:0] pyc_reg_541; // op=pyc.reg +wire [15:0] pyc_reg_542; // op=pyc.reg +wire [15:0] pyc_reg_543; // op=pyc.reg +wire [15:0] pyc_reg_593; // op=pyc.reg +wire pyc_reg_598; // op=pyc.reg +wire [18:0] pyc_reg_599; // op=pyc.reg +wire [18:0] pyc_sext_103; // op=pyc.sext +wire [15:0] pyc_sext_104; // op=pyc.sext +wire [18:0] pyc_sext_110; // op=pyc.sext +wire [18:0] pyc_sext_113; // op=pyc.sext +wire [15:0] pyc_sext_116; // op=pyc.sext +wire [18:0] pyc_sext_117; // op=pyc.sext +wire [15:0] pyc_sext_118; // op=pyc.sext +wire [18:0] pyc_sext_129; // op=pyc.sext +wire [15:0] pyc_sext_130; // op=pyc.sext +wire [18:0] pyc_sext_136; // op=pyc.sext +wire [18:0] pyc_sext_139; // op=pyc.sext +wire [15:0] pyc_sext_142; // op=pyc.sext +wire [18:0] pyc_sext_143; // op=pyc.sext +wire [15:0] pyc_sext_144; // op=pyc.sext +wire [18:0] pyc_sext_155; // op=pyc.sext +wire [15:0] pyc_sext_156; // op=pyc.sext +wire [18:0] pyc_sext_158; // op=pyc.sext +wire [18:0] pyc_sext_161; // op=pyc.sext +wire [15:0] pyc_sext_164; // op=pyc.sext +wire [18:0] pyc_sext_165; // op=pyc.sext +wire [15:0] pyc_sext_166; // op=pyc.sext +wire [18:0] pyc_sext_177; // op=pyc.sext +wire [15:0] pyc_sext_178; // op=pyc.sext +wire [18:0] pyc_sext_180; // op=pyc.sext +wire [18:0] pyc_sext_183; // op=pyc.sext +wire [15:0] pyc_sext_186; // op=pyc.sext +wire [18:0] pyc_sext_187; // op=pyc.sext +wire [15:0] pyc_sext_188; // op=pyc.sext +wire [18:0] pyc_sext_199; // op=pyc.sext +wire [15:0] pyc_sext_200; // op=pyc.sext +wire [18:0] pyc_sext_202; // op=pyc.sext +wire [18:0] pyc_sext_205; // op=pyc.sext +wire [15:0] pyc_sext_208; // op=pyc.sext +wire [18:0] pyc_sext_209; // op=pyc.sext +wire [15:0] pyc_sext_210; // op=pyc.sext +wire [18:0] pyc_sext_221; // op=pyc.sext +wire [15:0] pyc_sext_222; // op=pyc.sext +wire [18:0] pyc_sext_226; // op=pyc.sext +wire [18:0] pyc_sext_229; // op=pyc.sext +wire [15:0] pyc_sext_230; // op=pyc.sext +wire [18:0] pyc_sext_231; // op=pyc.sext +wire [15:0] pyc_sext_232; // op=pyc.sext +wire [18:0] pyc_sext_238; // op=pyc.sext +wire [15:0] pyc_sext_239; // op=pyc.sext +wire [18:0] pyc_sext_240; // op=pyc.sext +wire [15:0] pyc_sext_242; // op=pyc.sext +wire [18:0] pyc_sext_245; // op=pyc.sext +wire [15:0] pyc_sext_246; // op=pyc.sext +wire [18:0] pyc_sext_247; // op=pyc.sext +wire [15:0] pyc_sext_249; // op=pyc.sext +wire [18:0] pyc_sext_252; // op=pyc.sext +wire [15:0] pyc_sext_253; // op=pyc.sext +wire [18:0] pyc_sext_254; // op=pyc.sext +wire [15:0] pyc_sext_256; // op=pyc.sext +wire [18:0] pyc_sext_259; // op=pyc.sext +wire [15:0] pyc_sext_260; // op=pyc.sext +wire [18:0] pyc_sext_261; // op=pyc.sext +wire [15:0] pyc_sext_263; // op=pyc.sext +wire [18:0] pyc_sext_266; // op=pyc.sext +wire [15:0] pyc_sext_267; // op=pyc.sext +wire [18:0] pyc_sext_268; // op=pyc.sext +wire [15:0] pyc_sext_270; // op=pyc.sext +wire [18:0] pyc_sext_273; // op=pyc.sext +wire [15:0] pyc_sext_274; // op=pyc.sext +wire [18:0] pyc_sext_275; // op=pyc.sext +wire [15:0] pyc_sext_277; // op=pyc.sext +wire [18:0] pyc_sext_280; // op=pyc.sext +wire [15:0] pyc_sext_281; // op=pyc.sext +wire [18:0] pyc_sext_282; // op=pyc.sext +wire [15:0] pyc_sext_284; // op=pyc.sext +wire [18:0] pyc_sext_287; // op=pyc.sext +wire [15:0] pyc_sext_288; // op=pyc.sext +wire [18:0] pyc_sext_289; // op=pyc.sext +wire [15:0] pyc_sext_291; // op=pyc.sext +wire [18:0] pyc_sext_294; // op=pyc.sext +wire [15:0] pyc_sext_295; // op=pyc.sext +wire [18:0] pyc_sext_296; // op=pyc.sext +wire [15:0] pyc_sext_298; // op=pyc.sext +wire [18:0] pyc_sext_301; // op=pyc.sext +wire [15:0] pyc_sext_302; // op=pyc.sext +wire [18:0] pyc_sext_303; // op=pyc.sext +wire [15:0] pyc_sext_305; // op=pyc.sext +wire [18:0] pyc_sext_308; // op=pyc.sext +wire [15:0] pyc_sext_309; // op=pyc.sext +wire [18:0] pyc_sext_310; // op=pyc.sext +wire [15:0] pyc_sext_312; // op=pyc.sext +wire [18:0] pyc_sext_315; // op=pyc.sext +wire [15:0] pyc_sext_316; // op=pyc.sext +wire [18:0] pyc_sext_317; // op=pyc.sext +wire [15:0] pyc_sext_319; // op=pyc.sext +wire [18:0] pyc_sext_322; // op=pyc.sext +wire [15:0] pyc_sext_323; // op=pyc.sext +wire [18:0] pyc_sext_324; // op=pyc.sext +wire [15:0] pyc_sext_326; // op=pyc.sext +wire [18:0] pyc_sext_329; // op=pyc.sext +wire [15:0] pyc_sext_330; // op=pyc.sext +wire [18:0] pyc_sext_331; // op=pyc.sext +wire [15:0] pyc_sext_333; // op=pyc.sext +wire [18:0] pyc_sext_336; // op=pyc.sext +wire [15:0] pyc_sext_337; // op=pyc.sext +wire [18:0] pyc_sext_338; // op=pyc.sext +wire [15:0] pyc_sext_340; // op=pyc.sext +wire [18:0] pyc_sext_343; // op=pyc.sext +wire [15:0] pyc_sext_344; // op=pyc.sext +wire [18:0] pyc_sext_345; // op=pyc.sext +wire [15:0] pyc_sext_347; // op=pyc.sext +wire [18:0] pyc_sext_51; // op=pyc.sext +wire [15:0] pyc_sext_52; // op=pyc.sext +wire [18:0] pyc_sext_58; // op=pyc.sext +wire [18:0] pyc_sext_61; // op=pyc.sext +wire [15:0] pyc_sext_64; // op=pyc.sext +wire [18:0] pyc_sext_65; // op=pyc.sext +wire [15:0] pyc_sext_66; // op=pyc.sext +wire [18:0] pyc_sext_77; // op=pyc.sext +wire [15:0] pyc_sext_78; // op=pyc.sext +wire [18:0] pyc_sext_84; // op=pyc.sext +wire [18:0] pyc_sext_87; // op=pyc.sext +wire [15:0] pyc_sext_90; // op=pyc.sext +wire [18:0] pyc_sext_91; // op=pyc.sext +wire [15:0] pyc_sext_92; // op=pyc.sext +wire [18:0] pyc_shli_556; // op=pyc.shli +wire [18:0] pyc_shli_557; // op=pyc.shli +wire [18:0] pyc_shli_562; // op=pyc.shli +wire [18:0] pyc_shli_563; // op=pyc.shli +wire [15:0] pyc_shli_575; // op=pyc.shli +wire [15:0] pyc_shli_576; // op=pyc.shli +wire [15:0] pyc_shli_581; // op=pyc.shli +wire [15:0] pyc_shli_582; // op=pyc.shli +wire [1:0] pyc_zext_545; // op=pyc.zext +wire [1:0] pyc_zext_547; // op=pyc.zext +wire [1:0] pyc_zext_550; // op=pyc.zext +wire [1:0] pyc_zext_552; // op=pyc.zext +wire [1:0] pyc_zext_568; // op=pyc.zext +wire [1:0] pyc_zext_571; // op=pyc.zext // --- Combinational (netlist) -assign pe_int_out0 = pyc_reg_585; -assign pe_int_out_vld = pyc_reg_584; -assign pe_int_s0_a = pyc_reg_44; -assign pe_int_s0_b = pyc_reg_45; -assign pe_int_s0_b1 = pyc_reg_46; -assign pe_int_s1_p2a_0 = pyc_reg_413; -assign pe_int_s1_p2a_1 = pyc_reg_414; -assign pe_int_s1_p2a_2 = pyc_reg_415; -assign pe_int_s1_p2a_3 = pyc_reg_416; -assign pe_int_s1_p2a_4 = pyc_reg_417; -assign pe_int_s1_p2a_5 = pyc_reg_418; -assign pe_int_s1_p2a_6 = pyc_reg_419; -assign pe_int_s1_p2a_7 = pyc_reg_420; -assign pe_int_s1_p2b0_0 = pyc_reg_421; -assign pe_int_s1_p2b0_1 = pyc_reg_422; -assign pe_int_s1_p2b0_2 = pyc_reg_423; -assign pe_int_s1_p2b0_3 = pyc_reg_424; -assign pe_int_s1_p2b0_4 = pyc_reg_425; -assign pe_int_s1_p2b0_5 = pyc_reg_426; -assign pe_int_s1_p2b0_6 = pyc_reg_427; -assign pe_int_s1_p2b0_7 = pyc_reg_428; -assign pe_int_s1_p2b1_0 = pyc_reg_429; -assign pe_int_s1_p2b1_1 = pyc_reg_430; -assign pe_int_s1_p2b1_2 = pyc_reg_431; -assign pe_int_s1_p2b1_3 = pyc_reg_432; -assign pe_int_s1_p2b1_4 = pyc_reg_433; -assign pe_int_s1_p2b1_5 = pyc_reg_434; -assign pe_int_s1_p2b1_6 = pyc_reg_435; -assign pe_int_s1_p2b1_7 = pyc_reg_436; -assign pe_int_s1_p2c0_0 = pyc_reg_453; -assign pe_int_s1_p2c0_1 = pyc_reg_454; -assign pe_int_s1_p2c0_10 = pyc_reg_463; -assign pe_int_s1_p2c0_11 = pyc_reg_464; -assign pe_int_s1_p2c0_12 = pyc_reg_465; -assign pe_int_s1_p2c0_13 = pyc_reg_466; -assign pe_int_s1_p2c0_14 = pyc_reg_467; -assign pe_int_s1_p2c0_15 = pyc_reg_468; -assign pe_int_s1_p2c0_2 = pyc_reg_455; -assign pe_int_s1_p2c0_3 = pyc_reg_456; -assign pe_int_s1_p2c0_4 = pyc_reg_457; -assign pe_int_s1_p2c0_5 = pyc_reg_458; -assign pe_int_s1_p2c0_6 = pyc_reg_459; -assign pe_int_s1_p2c0_7 = pyc_reg_460; -assign pe_int_s1_p2c0_8 = pyc_reg_461; -assign pe_int_s1_p2c0_9 = pyc_reg_462; -assign pe_int_s1_p2c1_0 = pyc_reg_469; -assign pe_int_s1_p2c1_1 = pyc_reg_470; -assign pe_int_s1_p2c1_10 = pyc_reg_479; -assign pe_int_s1_p2c1_11 = pyc_reg_480; -assign pe_int_s1_p2c1_12 = pyc_reg_481; -assign pe_int_s1_p2c1_13 = pyc_reg_482; -assign pe_int_s1_p2c1_14 = pyc_reg_483; -assign pe_int_s1_p2c1_15 = pyc_reg_484; -assign pe_int_s1_p2c1_2 = pyc_reg_471; -assign pe_int_s1_p2c1_3 = pyc_reg_472; -assign pe_int_s1_p2c1_4 = pyc_reg_473; -assign pe_int_s1_p2c1_5 = pyc_reg_474; -assign pe_int_s1_p2c1_6 = pyc_reg_475; -assign pe_int_s1_p2c1_7 = pyc_reg_476; -assign pe_int_s1_p2c1_8 = pyc_reg_477; -assign pe_int_s1_p2c1_9 = pyc_reg_478; -assign pe_int_s1_p2d0_0 = pyc_reg_437; -assign pe_int_s1_p2d0_1 = pyc_reg_438; -assign pe_int_s1_p2d0_2 = pyc_reg_439; -assign pe_int_s1_p2d0_3 = pyc_reg_440; -assign pe_int_s1_p2d0_4 = pyc_reg_441; -assign pe_int_s1_p2d0_5 = pyc_reg_442; -assign pe_int_s1_p2d0_6 = pyc_reg_443; -assign pe_int_s1_p2d0_7 = pyc_reg_444; -assign pe_int_s1_p2d1_0 = pyc_reg_445; -assign pe_int_s1_p2d1_1 = pyc_reg_446; -assign pe_int_s1_p2d1_2 = pyc_reg_447; -assign pe_int_s1_p2d1_3 = pyc_reg_448; -assign pe_int_s1_p2d1_4 = pyc_reg_449; -assign pe_int_s1_p2d1_5 = pyc_reg_450; -assign pe_int_s1_p2d1_6 = pyc_reg_451; -assign pe_int_s1_p2d1_7 = pyc_reg_452; -assign pe_int_s2_e1_a = pyc_reg_508; -assign pe_int_s2_e1_b0 = pyc_reg_509; -assign pe_int_s2_e1_b1 = pyc_reg_510; -assign pe_int_s2_s2a__next = pyc_instance_485; -assign pe_int_s2_s2b0 = pyc_reg_514; -assign pe_int_s2_s2b0__next = pyc_instance_486; -assign pe_int_s2_s2b1 = pyc_reg_515; -assign pe_int_s2_s2b1__next = pyc_instance_487; -assign pe_int_s2_s2c0_hi = pyc_reg_519; -assign pe_int_s2_s2c0_hi__next = pyc_instance_491; -assign pe_int_s2_s2c0_lo = pyc_reg_518; -assign pe_int_s2_s2c0_lo__next = pyc_instance_490; -assign pe_int_s2_s2c1_hi__next = pyc_instance_493; -assign pe_int_s2_s2c1_lo = pyc_reg_520; -assign pe_int_s2_s2c1_lo__next = pyc_instance_492; -assign pe_int_s2_s2d0 = pyc_reg_516; -assign pe_int_s2_s2d0__next = pyc_instance_488; -assign pe_int_s2_s2d1 = pyc_reg_517; -assign pe_int_s2_s2d1__next = pyc_instance_489; -assign pyc_constant_1 = 19'd0; +assign pe_int_out0 = pyc_reg_599; +assign pe_int_out_vld = pyc_reg_598; +assign pe_int_s0_a = pyc_reg_37; +assign pe_int_s0_b = pyc_reg_38; +assign pe_int_s0_b1 = pyc_reg_39; +assign pe_int_s1_p2a_0 = pyc_reg_437; +assign pe_int_s1_p2a_1 = pyc_reg_438; +assign pe_int_s1_p2a_2 = pyc_reg_439; +assign pe_int_s1_p2a_3 = pyc_reg_440; +assign pe_int_s1_p2a_4 = pyc_reg_441; +assign pe_int_s1_p2a_5 = pyc_reg_442; +assign pe_int_s1_p2a_6 = pyc_reg_443; +assign pe_int_s1_p2a_7 = pyc_reg_444; +assign pe_int_s1_p2b0_0 = pyc_reg_445; +assign pe_int_s1_p2b0_1 = pyc_reg_446; +assign pe_int_s1_p2b0_2 = pyc_reg_447; +assign pe_int_s1_p2b0_3 = pyc_reg_448; +assign pe_int_s1_p2b0_4 = pyc_reg_449; +assign pe_int_s1_p2b0_5 = pyc_reg_450; +assign pe_int_s1_p2b0_6 = pyc_reg_451; +assign pe_int_s1_p2b0_7 = pyc_reg_452; +assign pe_int_s1_p2b1_0 = pyc_reg_453; +assign pe_int_s1_p2b1_1 = pyc_reg_454; +assign pe_int_s1_p2b1_2 = pyc_reg_455; +assign pe_int_s1_p2b1_3 = pyc_reg_456; +assign pe_int_s1_p2b1_4 = pyc_reg_457; +assign pe_int_s1_p2b1_5 = pyc_reg_458; +assign pe_int_s1_p2b1_6 = pyc_reg_459; +assign pe_int_s1_p2b1_7 = pyc_reg_460; +assign pe_int_s1_p2c0_0 = pyc_reg_477; +assign pe_int_s1_p2c0_1 = pyc_reg_478; +assign pe_int_s1_p2c0_10 = pyc_reg_487; +assign pe_int_s1_p2c0_11 = pyc_reg_488; +assign pe_int_s1_p2c0_12 = pyc_reg_489; +assign pe_int_s1_p2c0_13 = pyc_reg_490; +assign pe_int_s1_p2c0_14 = pyc_reg_491; +assign pe_int_s1_p2c0_15 = pyc_reg_492; +assign pe_int_s1_p2c0_2 = pyc_reg_479; +assign pe_int_s1_p2c0_3 = pyc_reg_480; +assign pe_int_s1_p2c0_4 = pyc_reg_481; +assign pe_int_s1_p2c0_5 = pyc_reg_482; +assign pe_int_s1_p2c0_6 = pyc_reg_483; +assign pe_int_s1_p2c0_7 = pyc_reg_484; +assign pe_int_s1_p2c0_8 = pyc_reg_485; +assign pe_int_s1_p2c0_9 = pyc_reg_486; +assign pe_int_s1_p2c1_0 = pyc_reg_493; +assign pe_int_s1_p2c1_1 = pyc_reg_494; +assign pe_int_s1_p2c1_10 = pyc_reg_503; +assign pe_int_s1_p2c1_11 = pyc_reg_504; +assign pe_int_s1_p2c1_12 = pyc_reg_505; +assign pe_int_s1_p2c1_13 = pyc_reg_506; +assign pe_int_s1_p2c1_14 = pyc_reg_507; +assign pe_int_s1_p2c1_15 = pyc_reg_508; +assign pe_int_s1_p2c1_2 = pyc_reg_495; +assign pe_int_s1_p2c1_3 = pyc_reg_496; +assign pe_int_s1_p2c1_4 = pyc_reg_497; +assign pe_int_s1_p2c1_5 = pyc_reg_498; +assign pe_int_s1_p2c1_6 = pyc_reg_499; +assign pe_int_s1_p2c1_7 = pyc_reg_500; +assign pe_int_s1_p2c1_8 = pyc_reg_501; +assign pe_int_s1_p2c1_9 = pyc_reg_502; +assign pe_int_s1_p2d0_0 = pyc_reg_461; +assign pe_int_s1_p2d0_1 = pyc_reg_462; +assign pe_int_s1_p2d0_2 = pyc_reg_463; +assign pe_int_s1_p2d0_3 = pyc_reg_464; +assign pe_int_s1_p2d0_4 = pyc_reg_465; +assign pe_int_s1_p2d0_5 = pyc_reg_466; +assign pe_int_s1_p2d0_6 = pyc_reg_467; +assign pe_int_s1_p2d0_7 = pyc_reg_468; +assign pe_int_s1_p2d1_0 = pyc_reg_469; +assign pe_int_s1_p2d1_1 = pyc_reg_470; +assign pe_int_s1_p2d1_2 = pyc_reg_471; +assign pe_int_s1_p2d1_3 = pyc_reg_472; +assign pe_int_s1_p2d1_4 = pyc_reg_473; +assign pe_int_s1_p2d1_5 = pyc_reg_474; +assign pe_int_s1_p2d1_6 = pyc_reg_475; +assign pe_int_s1_p2d1_7 = pyc_reg_476; +assign pe_int_s2_e1_a = pyc_reg_532; +assign pe_int_s2_e1_b0 = pyc_reg_533; +assign pe_int_s2_e1_b1 = pyc_reg_534; +assign pe_int_s2_s2a = pyc_reg_535; +assign pe_int_s2_s2a__next = pyc_instance_509; +assign pe_int_s2_s2b0 = pyc_reg_536; +assign pe_int_s2_s2b0__next = pyc_instance_510; +assign pe_int_s2_s2b1 = pyc_reg_537; +assign pe_int_s2_s2b1__next = pyc_instance_511; +assign pe_int_s2_s2c0_hi = pyc_reg_541; +assign pe_int_s2_s2c0_hi__next = pyc_instance_515; +assign pe_int_s2_s2c0_lo = pyc_reg_540; +assign pe_int_s2_s2c0_lo__next = pyc_instance_514; +assign pe_int_s2_s2c1_hi__next = pyc_instance_517; +assign pe_int_s2_s2c1_lo = pyc_reg_542; +assign pe_int_s2_s2c1_lo__next = pyc_instance_516; +assign pe_int_s2_s2d0 = pyc_reg_538; +assign pe_int_s2_s2d0__next = pyc_instance_512; +assign pe_int_s2_s2d1 = pyc_reg_539; +assign pe_int_s2_s2d1__next = pyc_instance_513; +assign pyc_constant_1 = 2'd1; assign pyc_constant_2 = 16'd0; -assign pyc_constant_3 = 2'd1; -assign pyc_constant_4 = 32'd0; -assign pyc_constant_5 = 2'd0; -assign pyc_constant_6 = 80'd0; -assign pyc_constant_7 = 2'd3; -assign pyc_constant_8 = 2'd2; -assign pyc_constant_9 = 1'd1; -assign pyc_constant_10 = 1'd0; +assign pyc_constant_3 = 19'd0; +assign pyc_constant_4 = 2'd0; +assign pyc_constant_5 = 80'd0; +assign pyc_constant_6 = 2'd2; +assign pyc_constant_7 = 1'd1; +assign pyc_constant_8 = 1'd0; assign pe_int_s0_e1_b1__next = e1_b1; assign pe_int_s0_e1_b0__next = e1_b0; assign pe_int_s0_e1_a__next = e1_a; @@ -943,231 +950,243 @@ assign pe_int_s0_b1__next = b1; assign pe_int_s0_b__next = b; assign pe_int_s0_a__next = a; assign pe_int_s0_vld__next = vld; -assign pyc_eq_11 = (mode == pyc_constant_5); -assign pe_int_s0_is_2a__next = pyc_eq_11; -assign pyc_eq_12 = (mode == pyc_constant_3); -assign pe_int_s0_is_2b__next = pyc_eq_12; -assign pyc_eq_13 = (mode == pyc_constant_8); -assign pe_int_s0_is_2c__next = pyc_eq_13; -assign pyc_eq_14 = (mode == pyc_constant_7); -assign pe_int_s0_is_2d__next = pyc_eq_14; -assign pyc_comb_15 = pyc_constant_1; -assign pyc_comb_16 = pyc_constant_2; -assign pyc_comb_17 = pyc_constant_3; -assign pyc_comb_18 = pyc_constant_4; -assign pyc_comb_19 = pyc_constant_5; -assign pyc_comb_20 = pyc_constant_6; -assign pyc_comb_21 = pyc_constant_9; -assign pyc_comb_22 = pyc_constant_10; -assign pyc_comb_23 = pe_int_s0_e1_b1__next; -assign pyc_comb_24 = pe_int_s0_e1_b0__next; -assign pyc_comb_25 = pe_int_s0_e1_a__next; -assign pyc_comb_26 = pe_int_s0_b1__next; -assign pyc_comb_27 = pe_int_s0_b__next; -assign pyc_comb_28 = pe_int_s0_a__next; -assign pyc_comb_29 = pe_int_s0_vld__next; -assign pyc_comb_30 = pe_int_s0_is_2a__next; -assign pyc_comb_31 = pe_int_s0_is_2b__next; -assign pyc_comb_32 = pe_int_s0_is_2c__next; -assign pyc_comb_33 = pe_int_s0_is_2d__next; -assign pe_int_s0_e1_b1 = pyc_reg_51; +assign pyc_eq_9 = (mode == pyc_constant_4); +assign pe_int_s0_is_2a__next = pyc_eq_9; +assign pyc_eq_10 = (mode == pyc_constant_1); +assign pe_int_s0_is_2b__next = pyc_eq_10; +assign pyc_eq_11 = (mode == pyc_constant_6); +assign pe_int_s0_is_2c__next = pyc_eq_11; +assign pyc_comb_12 = pyc_constant_1; +assign pyc_comb_13 = pyc_constant_2; +assign pyc_comb_14 = pyc_constant_3; +assign pyc_comb_15 = pyc_constant_4; +assign pyc_comb_16 = pyc_constant_5; +assign pyc_comb_17 = pyc_constant_7; +assign pyc_comb_18 = pyc_constant_8; +assign pyc_comb_19 = pe_int_s0_e1_b1__next; +assign pyc_comb_20 = pe_int_s0_e1_b0__next; +assign pyc_comb_21 = pe_int_s0_e1_a__next; +assign pyc_comb_22 = pe_int_s0_b1__next; +assign pyc_comb_23 = pe_int_s0_b__next; +assign pyc_comb_24 = pe_int_s0_a__next; +assign pyc_comb_25 = pe_int_s0_vld__next; +assign pyc_comb_26 = pe_int_s0_is_2a__next; +assign pyc_comb_27 = pe_int_s0_is_2b__next; +assign pyc_comb_28 = pe_int_s0_is_2c__next; +assign pe_int_s0_vld = pyc_reg_29; +assign pe_int_s1_vld__next = pe_int_s0_vld; +assign pyc_comb_30 = pe_int_s1_vld__next; +assign pe_int_s0_is_2a = pyc_reg_31; +assign pe_int_s1_is_2a__next = pe_int_s0_is_2a; +assign pyc_comb_32 = pe_int_s1_is_2a__next; +assign pe_int_s0_is_2b = pyc_reg_33; +assign pe_int_s1_is_2b__next = pe_int_s0_is_2b; +assign pyc_comb_34 = pe_int_s1_is_2b__next; +assign pe_int_s0_e1_b1 = pyc_reg_44; assign pe_int_s1_e1_b1__next = pe_int_s0_e1_b1; -assign pyc_extract_52 = pe_int_s0_b[39:0]; -assign pyc_extract_53 = pe_int_s0_a[4:0]; -assign pyc_extract_54 = pe_int_s0_a[9:5]; +assign pyc_extract_45 = pe_int_s0_b[39:0]; +assign pyc_extract_46 = pe_int_s0_a[4:0]; +assign pyc_extract_47 = pe_int_s0_a[9:5]; +assign pyc_extract_48 = pyc_extract_46[4:1]; +assign pyc_extract_49 = pyc_extract_47[4:1]; +assign pyc_concat_50 = {pyc_extract_49, pyc_extract_48}; +assign pyc_sext_51 = {{11{pyc_concat_50[7]}}, pyc_concat_50}; +assign pyc_sext_52 = {{8{pyc_concat_50[7]}}, pyc_concat_50}; +assign pyc_extract_53 = pe_int_s0_b[4:0]; +assign pyc_extract_54 = pe_int_s0_b[9:5]; assign pyc_extract_55 = pyc_extract_53[4:1]; assign pyc_extract_56 = pyc_extract_54[4:1]; assign pyc_concat_57 = {pyc_extract_56, pyc_extract_55}; -assign pyc_sext_58 = {{24{pyc_concat_57[7]}}, pyc_concat_57}; -assign pyc_extract_59 = pe_int_s0_b[4:0]; -assign pyc_extract_60 = pe_int_s0_b[9:5]; -assign pyc_extract_61 = pyc_extract_59[4:1]; -assign pyc_extract_62 = pyc_extract_60[4:1]; -assign pyc_concat_63 = {pyc_extract_62, pyc_extract_61}; -assign pyc_sext_64 = {{24{pyc_concat_63[7]}}, pyc_concat_63}; -assign pyc_extract_65 = pyc_extract_52[4:0]; -assign pyc_extract_66 = pyc_extract_65[4:1]; -assign pyc_sext_67 = {{28{pyc_extract_66[3]}}, pyc_extract_66}; -assign pyc_extract_68 = pe_int_s0_b[44:40]; -assign pyc_extract_69 = pyc_extract_68[4:1]; -assign pyc_sext_70 = {{28{pyc_extract_69[3]}}, pyc_extract_69}; -assign pyc_sext_71 = {{27{pyc_extract_65[4]}}, pyc_extract_65}; -assign pyc_sext_72 = {{27{pyc_extract_68[4]}}, pyc_extract_68}; -assign pyc_mul_73 = (pyc_sext_58 * pyc_sext_64); -assign pe_int_s1_p2a_0__next = pyc_mul_73; -assign pyc_mul_74 = (pyc_sext_58 * pyc_sext_67); -assign pe_int_s1_p2b0_0__next = pyc_mul_74; -assign pyc_mul_75 = (pyc_sext_58 * pyc_sext_70); -assign pe_int_s1_p2b1_0__next = pyc_mul_75; -assign pyc_mul_76 = (pyc_sext_58 * pyc_sext_71); -assign pe_int_s1_p2d0_0__next = pyc_mul_76; -assign pyc_mul_77 = (pyc_sext_58 * pyc_sext_72); -assign pe_int_s1_p2d1_0__next = pyc_mul_77; -assign pyc_extract_78 = pe_int_s0_a[14:10]; -assign pyc_extract_79 = pe_int_s0_a[19:15]; -assign pyc_extract_80 = pyc_extract_78[4:1]; +assign pyc_sext_58 = {{11{pyc_concat_57[7]}}, pyc_concat_57}; +assign pyc_extract_59 = pyc_extract_45[4:0]; +assign pyc_extract_60 = pyc_extract_59[4:1]; +assign pyc_sext_61 = {{15{pyc_extract_60[3]}}, pyc_extract_60}; +assign pyc_extract_62 = pe_int_s0_b[44:40]; +assign pyc_extract_63 = pyc_extract_62[4:1]; +assign pyc_sext_64 = {{12{pyc_extract_63[3]}}, pyc_extract_63}; +assign pyc_sext_65 = {{14{pyc_extract_59[4]}}, pyc_extract_59}; +assign pyc_sext_66 = {{11{pyc_extract_62[4]}}, pyc_extract_62}; +assign pyc_mul_67 = (pyc_sext_51 * pyc_sext_58); +assign pe_int_s1_p2a_0__next = pyc_mul_67; +assign pyc_mul_68 = (pyc_sext_51 * pyc_sext_61); +assign pe_int_s1_p2b0_0__next = pyc_mul_68; +assign pyc_mul_69 = (pyc_sext_52 * pyc_sext_64); +assign pe_int_s1_p2b1_0__next = pyc_mul_69; +assign pyc_mul_70 = (pyc_sext_51 * pyc_sext_65); +assign pe_int_s1_p2d0_0__next = pyc_mul_70; +assign pyc_mul_71 = (pyc_sext_52 * pyc_sext_66); +assign pe_int_s1_p2d1_0__next = pyc_mul_71; +assign pyc_extract_72 = pe_int_s0_a[14:10]; +assign pyc_extract_73 = pe_int_s0_a[19:15]; +assign pyc_extract_74 = pyc_extract_72[4:1]; +assign pyc_extract_75 = pyc_extract_73[4:1]; +assign pyc_concat_76 = {pyc_extract_75, pyc_extract_74}; +assign pyc_sext_77 = {{11{pyc_concat_76[7]}}, pyc_concat_76}; +assign pyc_sext_78 = {{8{pyc_concat_76[7]}}, pyc_concat_76}; +assign pyc_extract_79 = pe_int_s0_b[14:10]; +assign pyc_extract_80 = pe_int_s0_b[19:15]; assign pyc_extract_81 = pyc_extract_79[4:1]; -assign pyc_concat_82 = {pyc_extract_81, pyc_extract_80}; -assign pyc_sext_83 = {{24{pyc_concat_82[7]}}, pyc_concat_82}; -assign pyc_extract_84 = pe_int_s0_b[14:10]; -assign pyc_extract_85 = pe_int_s0_b[19:15]; -assign pyc_extract_86 = pyc_extract_84[4:1]; -assign pyc_extract_87 = pyc_extract_85[4:1]; -assign pyc_concat_88 = {pyc_extract_87, pyc_extract_86}; -assign pyc_sext_89 = {{24{pyc_concat_88[7]}}, pyc_concat_88}; -assign pyc_extract_90 = pyc_extract_52[9:5]; -assign pyc_extract_91 = pyc_extract_90[4:1]; -assign pyc_sext_92 = {{28{pyc_extract_91[3]}}, pyc_extract_91}; -assign pyc_extract_93 = pe_int_s0_b[49:45]; -assign pyc_extract_94 = pyc_extract_93[4:1]; -assign pyc_sext_95 = {{28{pyc_extract_94[3]}}, pyc_extract_94}; -assign pyc_sext_96 = {{27{pyc_extract_90[4]}}, pyc_extract_90}; -assign pyc_sext_97 = {{27{pyc_extract_93[4]}}, pyc_extract_93}; -assign pyc_mul_98 = (pyc_sext_83 * pyc_sext_89); -assign pe_int_s1_p2a_1__next = pyc_mul_98; -assign pyc_mul_99 = (pyc_sext_83 * pyc_sext_92); -assign pe_int_s1_p2b0_1__next = pyc_mul_99; -assign pyc_mul_100 = (pyc_sext_83 * pyc_sext_95); -assign pe_int_s1_p2b1_1__next = pyc_mul_100; -assign pyc_mul_101 = (pyc_sext_83 * pyc_sext_96); -assign pe_int_s1_p2d0_1__next = pyc_mul_101; -assign pyc_mul_102 = (pyc_sext_83 * pyc_sext_97); -assign pe_int_s1_p2d1_1__next = pyc_mul_102; -assign pyc_extract_103 = pe_int_s0_a[24:20]; -assign pyc_extract_104 = pe_int_s0_a[29:25]; -assign pyc_extract_105 = pyc_extract_103[4:1]; -assign pyc_extract_106 = pyc_extract_104[4:1]; -assign pyc_concat_107 = {pyc_extract_106, pyc_extract_105}; -assign pyc_sext_108 = {{24{pyc_concat_107[7]}}, pyc_concat_107}; -assign pyc_extract_109 = pe_int_s0_b[24:20]; -assign pyc_extract_110 = pe_int_s0_b[29:25]; -assign pyc_extract_111 = pyc_extract_109[4:1]; -assign pyc_extract_112 = pyc_extract_110[4:1]; -assign pyc_concat_113 = {pyc_extract_112, pyc_extract_111}; -assign pyc_sext_114 = {{24{pyc_concat_113[7]}}, pyc_concat_113}; -assign pyc_extract_115 = pyc_extract_52[14:10]; -assign pyc_extract_116 = pyc_extract_115[4:1]; -assign pyc_sext_117 = {{28{pyc_extract_116[3]}}, pyc_extract_116}; -assign pyc_extract_118 = pe_int_s0_b[54:50]; -assign pyc_extract_119 = pyc_extract_118[4:1]; -assign pyc_sext_120 = {{28{pyc_extract_119[3]}}, pyc_extract_119}; -assign pyc_sext_121 = {{27{pyc_extract_115[4]}}, pyc_extract_115}; -assign pyc_sext_122 = {{27{pyc_extract_118[4]}}, pyc_extract_118}; -assign pyc_mul_123 = (pyc_sext_108 * pyc_sext_114); -assign pe_int_s1_p2a_2__next = pyc_mul_123; -assign pyc_mul_124 = (pyc_sext_108 * pyc_sext_117); -assign pe_int_s1_p2b0_2__next = pyc_mul_124; -assign pyc_mul_125 = (pyc_sext_108 * pyc_sext_120); -assign pe_int_s1_p2b1_2__next = pyc_mul_125; -assign pyc_mul_126 = (pyc_sext_108 * pyc_sext_121); -assign pe_int_s1_p2d0_2__next = pyc_mul_126; -assign pyc_mul_127 = (pyc_sext_108 * pyc_sext_122); -assign pe_int_s1_p2d1_2__next = pyc_mul_127; -assign pyc_extract_128 = pe_int_s0_a[34:30]; -assign pyc_extract_129 = pe_int_s0_a[39:35]; -assign pyc_extract_130 = pyc_extract_128[4:1]; -assign pyc_extract_131 = pyc_extract_129[4:1]; -assign pyc_concat_132 = {pyc_extract_131, pyc_extract_130}; -assign pyc_sext_133 = {{24{pyc_concat_132[7]}}, pyc_concat_132}; -assign pyc_extract_134 = pe_int_s0_b[34:30]; -assign pyc_extract_135 = pe_int_s0_b[39:35]; -assign pyc_extract_136 = pyc_extract_134[4:1]; -assign pyc_extract_137 = pyc_extract_135[4:1]; -assign pyc_concat_138 = {pyc_extract_137, pyc_extract_136}; -assign pyc_sext_139 = {{24{pyc_concat_138[7]}}, pyc_concat_138}; -assign pyc_extract_140 = pyc_extract_52[19:15]; +assign pyc_extract_82 = pyc_extract_80[4:1]; +assign pyc_concat_83 = {pyc_extract_82, pyc_extract_81}; +assign pyc_sext_84 = {{11{pyc_concat_83[7]}}, pyc_concat_83}; +assign pyc_extract_85 = pyc_extract_45[9:5]; +assign pyc_extract_86 = pyc_extract_85[4:1]; +assign pyc_sext_87 = {{15{pyc_extract_86[3]}}, pyc_extract_86}; +assign pyc_extract_88 = pe_int_s0_b[49:45]; +assign pyc_extract_89 = pyc_extract_88[4:1]; +assign pyc_sext_90 = {{12{pyc_extract_89[3]}}, pyc_extract_89}; +assign pyc_sext_91 = {{14{pyc_extract_85[4]}}, pyc_extract_85}; +assign pyc_sext_92 = {{11{pyc_extract_88[4]}}, pyc_extract_88}; +assign pyc_mul_93 = (pyc_sext_77 * pyc_sext_84); +assign pe_int_s1_p2a_1__next = pyc_mul_93; +assign pyc_mul_94 = (pyc_sext_77 * pyc_sext_87); +assign pe_int_s1_p2b0_1__next = pyc_mul_94; +assign pyc_mul_95 = (pyc_sext_78 * pyc_sext_90); +assign pe_int_s1_p2b1_1__next = pyc_mul_95; +assign pyc_mul_96 = (pyc_sext_77 * pyc_sext_91); +assign pe_int_s1_p2d0_1__next = pyc_mul_96; +assign pyc_mul_97 = (pyc_sext_78 * pyc_sext_92); +assign pe_int_s1_p2d1_1__next = pyc_mul_97; +assign pyc_extract_98 = pe_int_s0_a[24:20]; +assign pyc_extract_99 = pe_int_s0_a[29:25]; +assign pyc_extract_100 = pyc_extract_98[4:1]; +assign pyc_extract_101 = pyc_extract_99[4:1]; +assign pyc_concat_102 = {pyc_extract_101, pyc_extract_100}; +assign pyc_sext_103 = {{11{pyc_concat_102[7]}}, pyc_concat_102}; +assign pyc_sext_104 = {{8{pyc_concat_102[7]}}, pyc_concat_102}; +assign pyc_extract_105 = pe_int_s0_b[24:20]; +assign pyc_extract_106 = pe_int_s0_b[29:25]; +assign pyc_extract_107 = pyc_extract_105[4:1]; +assign pyc_extract_108 = pyc_extract_106[4:1]; +assign pyc_concat_109 = {pyc_extract_108, pyc_extract_107}; +assign pyc_sext_110 = {{11{pyc_concat_109[7]}}, pyc_concat_109}; +assign pyc_extract_111 = pyc_extract_45[14:10]; +assign pyc_extract_112 = pyc_extract_111[4:1]; +assign pyc_sext_113 = {{15{pyc_extract_112[3]}}, pyc_extract_112}; +assign pyc_extract_114 = pe_int_s0_b[54:50]; +assign pyc_extract_115 = pyc_extract_114[4:1]; +assign pyc_sext_116 = {{12{pyc_extract_115[3]}}, pyc_extract_115}; +assign pyc_sext_117 = {{14{pyc_extract_111[4]}}, pyc_extract_111}; +assign pyc_sext_118 = {{11{pyc_extract_114[4]}}, pyc_extract_114}; +assign pyc_mul_119 = (pyc_sext_103 * pyc_sext_110); +assign pe_int_s1_p2a_2__next = pyc_mul_119; +assign pyc_mul_120 = (pyc_sext_103 * pyc_sext_113); +assign pe_int_s1_p2b0_2__next = pyc_mul_120; +assign pyc_mul_121 = (pyc_sext_104 * pyc_sext_116); +assign pe_int_s1_p2b1_2__next = pyc_mul_121; +assign pyc_mul_122 = (pyc_sext_103 * pyc_sext_117); +assign pe_int_s1_p2d0_2__next = pyc_mul_122; +assign pyc_mul_123 = (pyc_sext_104 * pyc_sext_118); +assign pe_int_s1_p2d1_2__next = pyc_mul_123; +assign pyc_extract_124 = pe_int_s0_a[34:30]; +assign pyc_extract_125 = pe_int_s0_a[39:35]; +assign pyc_extract_126 = pyc_extract_124[4:1]; +assign pyc_extract_127 = pyc_extract_125[4:1]; +assign pyc_concat_128 = {pyc_extract_127, pyc_extract_126}; +assign pyc_sext_129 = {{11{pyc_concat_128[7]}}, pyc_concat_128}; +assign pyc_sext_130 = {{8{pyc_concat_128[7]}}, pyc_concat_128}; +assign pyc_extract_131 = pe_int_s0_b[34:30]; +assign pyc_extract_132 = pe_int_s0_b[39:35]; +assign pyc_extract_133 = pyc_extract_131[4:1]; +assign pyc_extract_134 = pyc_extract_132[4:1]; +assign pyc_concat_135 = {pyc_extract_134, pyc_extract_133}; +assign pyc_sext_136 = {{11{pyc_concat_135[7]}}, pyc_concat_135}; +assign pyc_extract_137 = pyc_extract_45[19:15]; +assign pyc_extract_138 = pyc_extract_137[4:1]; +assign pyc_sext_139 = {{15{pyc_extract_138[3]}}, pyc_extract_138}; +assign pyc_extract_140 = pe_int_s0_b[59:55]; assign pyc_extract_141 = pyc_extract_140[4:1]; -assign pyc_sext_142 = {{28{pyc_extract_141[3]}}, pyc_extract_141}; -assign pyc_extract_143 = pe_int_s0_b[59:55]; -assign pyc_extract_144 = pyc_extract_143[4:1]; -assign pyc_sext_145 = {{28{pyc_extract_144[3]}}, pyc_extract_144}; -assign pyc_sext_146 = {{27{pyc_extract_140[4]}}, pyc_extract_140}; -assign pyc_sext_147 = {{27{pyc_extract_143[4]}}, pyc_extract_143}; -assign pyc_mul_148 = (pyc_sext_133 * pyc_sext_139); -assign pe_int_s1_p2a_3__next = pyc_mul_148; -assign pyc_mul_149 = (pyc_sext_133 * pyc_sext_142); -assign pe_int_s1_p2b0_3__next = pyc_mul_149; -assign pyc_mul_150 = (pyc_sext_133 * pyc_sext_145); -assign pe_int_s1_p2b1_3__next = pyc_mul_150; -assign pyc_mul_151 = (pyc_sext_133 * pyc_sext_146); -assign pe_int_s1_p2d0_3__next = pyc_mul_151; -assign pyc_mul_152 = (pyc_sext_133 * pyc_sext_147); -assign pe_int_s1_p2d1_3__next = pyc_mul_152; -assign pyc_extract_153 = pe_int_s0_a[44:40]; -assign pyc_extract_154 = pe_int_s0_a[49:45]; -assign pyc_extract_155 = pyc_extract_153[4:1]; -assign pyc_extract_156 = pyc_extract_154[4:1]; -assign pyc_concat_157 = {pyc_extract_156, pyc_extract_155}; -assign pyc_sext_158 = {{24{pyc_concat_157[7]}}, pyc_concat_157}; -assign pyc_concat_159 = {pyc_extract_94, pyc_extract_69}; -assign pyc_sext_160 = {{24{pyc_concat_159[7]}}, pyc_concat_159}; -assign pyc_extract_161 = pyc_extract_52[24:20]; -assign pyc_extract_162 = pyc_extract_161[4:1]; -assign pyc_sext_163 = {{28{pyc_extract_162[3]}}, pyc_extract_162}; -assign pyc_extract_164 = pe_int_s0_b[64:60]; -assign pyc_extract_165 = pyc_extract_164[4:1]; -assign pyc_sext_166 = {{28{pyc_extract_165[3]}}, pyc_extract_165}; -assign pyc_sext_167 = {{27{pyc_extract_161[4]}}, pyc_extract_161}; -assign pyc_sext_168 = {{27{pyc_extract_164[4]}}, pyc_extract_164}; -assign pyc_mul_169 = (pyc_sext_158 * pyc_sext_160); -assign pe_int_s1_p2a_4__next = pyc_mul_169; -assign pyc_mul_170 = (pyc_sext_158 * pyc_sext_163); -assign pe_int_s1_p2b0_4__next = pyc_mul_170; -assign pyc_mul_171 = (pyc_sext_158 * pyc_sext_166); -assign pe_int_s1_p2b1_4__next = pyc_mul_171; -assign pyc_mul_172 = (pyc_sext_158 * pyc_sext_167); -assign pe_int_s1_p2d0_4__next = pyc_mul_172; -assign pyc_mul_173 = (pyc_sext_158 * pyc_sext_168); -assign pe_int_s1_p2d1_4__next = pyc_mul_173; -assign pyc_extract_174 = pe_int_s0_a[54:50]; -assign pyc_extract_175 = pe_int_s0_a[59:55]; -assign pyc_extract_176 = pyc_extract_174[4:1]; -assign pyc_extract_177 = pyc_extract_175[4:1]; -assign pyc_concat_178 = {pyc_extract_177, pyc_extract_176}; -assign pyc_sext_179 = {{24{pyc_concat_178[7]}}, pyc_concat_178}; -assign pyc_concat_180 = {pyc_extract_144, pyc_extract_119}; -assign pyc_sext_181 = {{24{pyc_concat_180[7]}}, pyc_concat_180}; -assign pyc_extract_182 = pyc_extract_52[29:25]; -assign pyc_extract_183 = pyc_extract_182[4:1]; -assign pyc_sext_184 = {{28{pyc_extract_183[3]}}, pyc_extract_183}; -assign pyc_extract_185 = pe_int_s0_b[69:65]; -assign pyc_extract_186 = pyc_extract_185[4:1]; -assign pyc_sext_187 = {{28{pyc_extract_186[3]}}, pyc_extract_186}; -assign pyc_sext_188 = {{27{pyc_extract_182[4]}}, pyc_extract_182}; -assign pyc_sext_189 = {{27{pyc_extract_185[4]}}, pyc_extract_185}; -assign pyc_mul_190 = (pyc_sext_179 * pyc_sext_181); -assign pe_int_s1_p2a_5__next = pyc_mul_190; -assign pyc_mul_191 = (pyc_sext_179 * pyc_sext_184); -assign pe_int_s1_p2b0_5__next = pyc_mul_191; -assign pyc_mul_192 = (pyc_sext_179 * pyc_sext_187); -assign pe_int_s1_p2b1_5__next = pyc_mul_192; -assign pyc_mul_193 = (pyc_sext_179 * pyc_sext_188); -assign pe_int_s1_p2d0_5__next = pyc_mul_193; -assign pyc_mul_194 = (pyc_sext_179 * pyc_sext_189); -assign pe_int_s1_p2d1_5__next = pyc_mul_194; -assign pyc_extract_195 = pe_int_s0_a[64:60]; -assign pyc_extract_196 = pe_int_s0_a[69:65]; +assign pyc_sext_142 = {{12{pyc_extract_141[3]}}, pyc_extract_141}; +assign pyc_sext_143 = {{14{pyc_extract_137[4]}}, pyc_extract_137}; +assign pyc_sext_144 = {{11{pyc_extract_140[4]}}, pyc_extract_140}; +assign pyc_mul_145 = (pyc_sext_129 * pyc_sext_136); +assign pe_int_s1_p2a_3__next = pyc_mul_145; +assign pyc_mul_146 = (pyc_sext_129 * pyc_sext_139); +assign pe_int_s1_p2b0_3__next = pyc_mul_146; +assign pyc_mul_147 = (pyc_sext_130 * pyc_sext_142); +assign pe_int_s1_p2b1_3__next = pyc_mul_147; +assign pyc_mul_148 = (pyc_sext_129 * pyc_sext_143); +assign pe_int_s1_p2d0_3__next = pyc_mul_148; +assign pyc_mul_149 = (pyc_sext_130 * pyc_sext_144); +assign pe_int_s1_p2d1_3__next = pyc_mul_149; +assign pyc_extract_150 = pe_int_s0_a[44:40]; +assign pyc_extract_151 = pe_int_s0_a[49:45]; +assign pyc_extract_152 = pyc_extract_150[4:1]; +assign pyc_extract_153 = pyc_extract_151[4:1]; +assign pyc_concat_154 = {pyc_extract_153, pyc_extract_152}; +assign pyc_sext_155 = {{11{pyc_concat_154[7]}}, pyc_concat_154}; +assign pyc_sext_156 = {{8{pyc_concat_154[7]}}, pyc_concat_154}; +assign pyc_concat_157 = {pyc_extract_89, pyc_extract_63}; +assign pyc_sext_158 = {{11{pyc_concat_157[7]}}, pyc_concat_157}; +assign pyc_extract_159 = pyc_extract_45[24:20]; +assign pyc_extract_160 = pyc_extract_159[4:1]; +assign pyc_sext_161 = {{15{pyc_extract_160[3]}}, pyc_extract_160}; +assign pyc_extract_162 = pe_int_s0_b[64:60]; +assign pyc_extract_163 = pyc_extract_162[4:1]; +assign pyc_sext_164 = {{12{pyc_extract_163[3]}}, pyc_extract_163}; +assign pyc_sext_165 = {{14{pyc_extract_159[4]}}, pyc_extract_159}; +assign pyc_sext_166 = {{11{pyc_extract_162[4]}}, pyc_extract_162}; +assign pyc_mul_167 = (pyc_sext_155 * pyc_sext_158); +assign pe_int_s1_p2a_4__next = pyc_mul_167; +assign pyc_mul_168 = (pyc_sext_155 * pyc_sext_161); +assign pe_int_s1_p2b0_4__next = pyc_mul_168; +assign pyc_mul_169 = (pyc_sext_156 * pyc_sext_164); +assign pe_int_s1_p2b1_4__next = pyc_mul_169; +assign pyc_mul_170 = (pyc_sext_155 * pyc_sext_165); +assign pe_int_s1_p2d0_4__next = pyc_mul_170; +assign pyc_mul_171 = (pyc_sext_156 * pyc_sext_166); +assign pe_int_s1_p2d1_4__next = pyc_mul_171; +assign pyc_extract_172 = pe_int_s0_a[54:50]; +assign pyc_extract_173 = pe_int_s0_a[59:55]; +assign pyc_extract_174 = pyc_extract_172[4:1]; +assign pyc_extract_175 = pyc_extract_173[4:1]; +assign pyc_concat_176 = {pyc_extract_175, pyc_extract_174}; +assign pyc_sext_177 = {{11{pyc_concat_176[7]}}, pyc_concat_176}; +assign pyc_sext_178 = {{8{pyc_concat_176[7]}}, pyc_concat_176}; +assign pyc_concat_179 = {pyc_extract_141, pyc_extract_115}; +assign pyc_sext_180 = {{11{pyc_concat_179[7]}}, pyc_concat_179}; +assign pyc_extract_181 = pyc_extract_45[29:25]; +assign pyc_extract_182 = pyc_extract_181[4:1]; +assign pyc_sext_183 = {{15{pyc_extract_182[3]}}, pyc_extract_182}; +assign pyc_extract_184 = pe_int_s0_b[69:65]; +assign pyc_extract_185 = pyc_extract_184[4:1]; +assign pyc_sext_186 = {{12{pyc_extract_185[3]}}, pyc_extract_185}; +assign pyc_sext_187 = {{14{pyc_extract_181[4]}}, pyc_extract_181}; +assign pyc_sext_188 = {{11{pyc_extract_184[4]}}, pyc_extract_184}; +assign pyc_mul_189 = (pyc_sext_177 * pyc_sext_180); +assign pe_int_s1_p2a_5__next = pyc_mul_189; +assign pyc_mul_190 = (pyc_sext_177 * pyc_sext_183); +assign pe_int_s1_p2b0_5__next = pyc_mul_190; +assign pyc_mul_191 = (pyc_sext_178 * pyc_sext_186); +assign pe_int_s1_p2b1_5__next = pyc_mul_191; +assign pyc_mul_192 = (pyc_sext_177 * pyc_sext_187); +assign pe_int_s1_p2d0_5__next = pyc_mul_192; +assign pyc_mul_193 = (pyc_sext_178 * pyc_sext_188); +assign pe_int_s1_p2d1_5__next = pyc_mul_193; +assign pyc_extract_194 = pe_int_s0_a[64:60]; +assign pyc_extract_195 = pe_int_s0_a[69:65]; +assign pyc_extract_196 = pyc_extract_194[4:1]; assign pyc_extract_197 = pyc_extract_195[4:1]; -assign pyc_extract_198 = pyc_extract_196[4:1]; -assign pyc_concat_199 = {pyc_extract_198, pyc_extract_197}; -assign pyc_sext_200 = {{24{pyc_concat_199[7]}}, pyc_concat_199}; -assign pyc_concat_201 = {pyc_extract_186, pyc_extract_165}; -assign pyc_sext_202 = {{24{pyc_concat_201[7]}}, pyc_concat_201}; -assign pyc_extract_203 = pyc_extract_52[34:30]; +assign pyc_concat_198 = {pyc_extract_197, pyc_extract_196}; +assign pyc_sext_199 = {{11{pyc_concat_198[7]}}, pyc_concat_198}; +assign pyc_sext_200 = {{8{pyc_concat_198[7]}}, pyc_concat_198}; +assign pyc_concat_201 = {pyc_extract_185, pyc_extract_163}; +assign pyc_sext_202 = {{11{pyc_concat_201[7]}}, pyc_concat_201}; +assign pyc_extract_203 = pyc_extract_45[34:30]; assign pyc_extract_204 = pyc_extract_203[4:1]; -assign pyc_sext_205 = {{28{pyc_extract_204[3]}}, pyc_extract_204}; +assign pyc_sext_205 = {{15{pyc_extract_204[3]}}, pyc_extract_204}; assign pyc_extract_206 = pe_int_s0_b[74:70]; assign pyc_extract_207 = pyc_extract_206[4:1]; -assign pyc_sext_208 = {{28{pyc_extract_207[3]}}, pyc_extract_207}; -assign pyc_sext_209 = {{27{pyc_extract_203[4]}}, pyc_extract_203}; -assign pyc_sext_210 = {{27{pyc_extract_206[4]}}, pyc_extract_206}; -assign pyc_mul_211 = (pyc_sext_200 * pyc_sext_202); +assign pyc_sext_208 = {{12{pyc_extract_207[3]}}, pyc_extract_207}; +assign pyc_sext_209 = {{14{pyc_extract_203[4]}}, pyc_extract_203}; +assign pyc_sext_210 = {{11{pyc_extract_206[4]}}, pyc_extract_206}; +assign pyc_mul_211 = (pyc_sext_199 * pyc_sext_202); assign pe_int_s1_p2a_6__next = pyc_mul_211; -assign pyc_mul_212 = (pyc_sext_200 * pyc_sext_205); +assign pyc_mul_212 = (pyc_sext_199 * pyc_sext_205); assign pe_int_s1_p2b0_6__next = pyc_mul_212; assign pyc_mul_213 = (pyc_sext_200 * pyc_sext_208); assign pe_int_s1_p2b1_6__next = pyc_mul_213; -assign pyc_mul_214 = (pyc_sext_200 * pyc_sext_209); +assign pyc_mul_214 = (pyc_sext_199 * pyc_sext_209); assign pe_int_s1_p2d0_6__next = pyc_mul_214; assign pyc_mul_215 = (pyc_sext_200 * pyc_sext_210); assign pe_int_s1_p2d1_6__next = pyc_mul_215; @@ -1176,1353 +1195,1304 @@ assign pyc_extract_217 = pe_int_s0_a[79:75]; assign pyc_extract_218 = pyc_extract_216[4:1]; assign pyc_extract_219 = pyc_extract_217[4:1]; assign pyc_concat_220 = {pyc_extract_219, pyc_extract_218}; -assign pyc_sext_221 = {{24{pyc_concat_220[7]}}, pyc_concat_220}; -assign pyc_extract_222 = pe_int_s0_b[79:75]; -assign pyc_extract_223 = pyc_extract_222[4:1]; -assign pyc_concat_224 = {pyc_extract_223, pyc_extract_207}; -assign pyc_sext_225 = {{24{pyc_concat_224[7]}}, pyc_concat_224}; -assign pyc_extract_226 = pyc_extract_52[39:35]; -assign pyc_extract_227 = pyc_extract_226[4:1]; -assign pyc_sext_228 = {{28{pyc_extract_227[3]}}, pyc_extract_227}; -assign pyc_sext_229 = {{28{pyc_extract_223[3]}}, pyc_extract_223}; -assign pyc_sext_230 = {{27{pyc_extract_226[4]}}, pyc_extract_226}; -assign pyc_sext_231 = {{27{pyc_extract_222[4]}}, pyc_extract_222}; -assign pyc_mul_232 = (pyc_sext_221 * pyc_sext_225); -assign pe_int_s1_p2a_7__next = pyc_mul_232; -assign pyc_mul_233 = (pyc_sext_221 * pyc_sext_228); -assign pe_int_s1_p2b0_7__next = pyc_mul_233; +assign pyc_sext_221 = {{11{pyc_concat_220[7]}}, pyc_concat_220}; +assign pyc_sext_222 = {{8{pyc_concat_220[7]}}, pyc_concat_220}; +assign pyc_extract_223 = pe_int_s0_b[79:75]; +assign pyc_extract_224 = pyc_extract_223[4:1]; +assign pyc_concat_225 = {pyc_extract_224, pyc_extract_207}; +assign pyc_sext_226 = {{11{pyc_concat_225[7]}}, pyc_concat_225}; +assign pyc_extract_227 = pyc_extract_45[39:35]; +assign pyc_extract_228 = pyc_extract_227[4:1]; +assign pyc_sext_229 = {{15{pyc_extract_228[3]}}, pyc_extract_228}; +assign pyc_sext_230 = {{12{pyc_extract_224[3]}}, pyc_extract_224}; +assign pyc_sext_231 = {{14{pyc_extract_227[4]}}, pyc_extract_227}; +assign pyc_sext_232 = {{11{pyc_extract_223[4]}}, pyc_extract_223}; +assign pyc_mul_233 = (pyc_sext_221 * pyc_sext_226); +assign pe_int_s1_p2a_7__next = pyc_mul_233; assign pyc_mul_234 = (pyc_sext_221 * pyc_sext_229); -assign pe_int_s1_p2b1_7__next = pyc_mul_234; -assign pyc_mul_235 = (pyc_sext_221 * pyc_sext_230); -assign pe_int_s1_p2d0_7__next = pyc_mul_235; +assign pe_int_s1_p2b0_7__next = pyc_mul_234; +assign pyc_mul_235 = (pyc_sext_222 * pyc_sext_230); +assign pe_int_s1_p2b1_7__next = pyc_mul_235; assign pyc_mul_236 = (pyc_sext_221 * pyc_sext_231); -assign pe_int_s1_p2d1_7__next = pyc_mul_236; -assign pyc_sext_237 = {{27{pyc_extract_53[4]}}, pyc_extract_53}; -assign pyc_sext_238 = {{27{pyc_extract_59[4]}}, pyc_extract_59}; -assign pyc_extract_239 = pe_int_s0_b1[4:0]; -assign pyc_sext_240 = {{27{pyc_extract_239[4]}}, pyc_extract_239}; -assign pyc_mul_241 = (pyc_sext_237 * pyc_sext_238); -assign pe_int_s1_p2c0_0__next = pyc_mul_241; -assign pyc_mul_242 = (pyc_sext_237 * pyc_sext_240); -assign pe_int_s1_p2c1_0__next = pyc_mul_242; -assign pyc_sext_243 = {{27{pyc_extract_54[4]}}, pyc_extract_54}; -assign pyc_sext_244 = {{27{pyc_extract_60[4]}}, pyc_extract_60}; -assign pyc_extract_245 = pe_int_s0_b1[9:5]; -assign pyc_sext_246 = {{27{pyc_extract_245[4]}}, pyc_extract_245}; -assign pyc_mul_247 = (pyc_sext_243 * pyc_sext_244); -assign pe_int_s1_p2c0_1__next = pyc_mul_247; -assign pyc_mul_248 = (pyc_sext_243 * pyc_sext_246); -assign pe_int_s1_p2c1_1__next = pyc_mul_248; -assign pyc_sext_249 = {{27{pyc_extract_78[4]}}, pyc_extract_78}; -assign pyc_sext_250 = {{27{pyc_extract_84[4]}}, pyc_extract_84}; -assign pyc_extract_251 = pe_int_s0_b1[14:10]; -assign pyc_sext_252 = {{27{pyc_extract_251[4]}}, pyc_extract_251}; -assign pyc_mul_253 = (pyc_sext_249 * pyc_sext_250); -assign pe_int_s1_p2c0_2__next = pyc_mul_253; -assign pyc_mul_254 = (pyc_sext_249 * pyc_sext_252); -assign pe_int_s1_p2c1_2__next = pyc_mul_254; -assign pyc_sext_255 = {{27{pyc_extract_79[4]}}, pyc_extract_79}; -assign pyc_sext_256 = {{27{pyc_extract_85[4]}}, pyc_extract_85}; -assign pyc_extract_257 = pe_int_s0_b1[19:15]; -assign pyc_sext_258 = {{27{pyc_extract_257[4]}}, pyc_extract_257}; -assign pyc_mul_259 = (pyc_sext_255 * pyc_sext_256); -assign pe_int_s1_p2c0_3__next = pyc_mul_259; -assign pyc_mul_260 = (pyc_sext_255 * pyc_sext_258); -assign pe_int_s1_p2c1_3__next = pyc_mul_260; -assign pyc_sext_261 = {{27{pyc_extract_103[4]}}, pyc_extract_103}; -assign pyc_sext_262 = {{27{pyc_extract_109[4]}}, pyc_extract_109}; -assign pyc_extract_263 = pe_int_s0_b1[24:20]; -assign pyc_sext_264 = {{27{pyc_extract_263[4]}}, pyc_extract_263}; -assign pyc_mul_265 = (pyc_sext_261 * pyc_sext_262); -assign pe_int_s1_p2c0_4__next = pyc_mul_265; -assign pyc_mul_266 = (pyc_sext_261 * pyc_sext_264); -assign pe_int_s1_p2c1_4__next = pyc_mul_266; -assign pyc_sext_267 = {{27{pyc_extract_104[4]}}, pyc_extract_104}; -assign pyc_sext_268 = {{27{pyc_extract_110[4]}}, pyc_extract_110}; -assign pyc_extract_269 = pe_int_s0_b1[29:25]; -assign pyc_sext_270 = {{27{pyc_extract_269[4]}}, pyc_extract_269}; -assign pyc_mul_271 = (pyc_sext_267 * pyc_sext_268); -assign pe_int_s1_p2c0_5__next = pyc_mul_271; +assign pe_int_s1_p2d0_7__next = pyc_mul_236; +assign pyc_mul_237 = (pyc_sext_222 * pyc_sext_232); +assign pe_int_s1_p2d1_7__next = pyc_mul_237; +assign pyc_sext_238 = {{14{pyc_extract_46[4]}}, pyc_extract_46}; +assign pyc_sext_239 = {{11{pyc_extract_46[4]}}, pyc_extract_46}; +assign pyc_sext_240 = {{14{pyc_extract_53[4]}}, pyc_extract_53}; +assign pyc_extract_241 = pe_int_s0_b1[4:0]; +assign pyc_sext_242 = {{11{pyc_extract_241[4]}}, pyc_extract_241}; +assign pyc_mul_243 = (pyc_sext_238 * pyc_sext_240); +assign pe_int_s1_p2c0_0__next = pyc_mul_243; +assign pyc_mul_244 = (pyc_sext_239 * pyc_sext_242); +assign pe_int_s1_p2c1_0__next = pyc_mul_244; +assign pyc_sext_245 = {{14{pyc_extract_47[4]}}, pyc_extract_47}; +assign pyc_sext_246 = {{11{pyc_extract_47[4]}}, pyc_extract_47}; +assign pyc_sext_247 = {{14{pyc_extract_54[4]}}, pyc_extract_54}; +assign pyc_extract_248 = pe_int_s0_b1[9:5]; +assign pyc_sext_249 = {{11{pyc_extract_248[4]}}, pyc_extract_248}; +assign pyc_mul_250 = (pyc_sext_245 * pyc_sext_247); +assign pe_int_s1_p2c0_1__next = pyc_mul_250; +assign pyc_mul_251 = (pyc_sext_246 * pyc_sext_249); +assign pe_int_s1_p2c1_1__next = pyc_mul_251; +assign pyc_sext_252 = {{14{pyc_extract_72[4]}}, pyc_extract_72}; +assign pyc_sext_253 = {{11{pyc_extract_72[4]}}, pyc_extract_72}; +assign pyc_sext_254 = {{14{pyc_extract_79[4]}}, pyc_extract_79}; +assign pyc_extract_255 = pe_int_s0_b1[14:10]; +assign pyc_sext_256 = {{11{pyc_extract_255[4]}}, pyc_extract_255}; +assign pyc_mul_257 = (pyc_sext_252 * pyc_sext_254); +assign pe_int_s1_p2c0_2__next = pyc_mul_257; +assign pyc_mul_258 = (pyc_sext_253 * pyc_sext_256); +assign pe_int_s1_p2c1_2__next = pyc_mul_258; +assign pyc_sext_259 = {{14{pyc_extract_73[4]}}, pyc_extract_73}; +assign pyc_sext_260 = {{11{pyc_extract_73[4]}}, pyc_extract_73}; +assign pyc_sext_261 = {{14{pyc_extract_80[4]}}, pyc_extract_80}; +assign pyc_extract_262 = pe_int_s0_b1[19:15]; +assign pyc_sext_263 = {{11{pyc_extract_262[4]}}, pyc_extract_262}; +assign pyc_mul_264 = (pyc_sext_259 * pyc_sext_261); +assign pe_int_s1_p2c0_3__next = pyc_mul_264; +assign pyc_mul_265 = (pyc_sext_260 * pyc_sext_263); +assign pe_int_s1_p2c1_3__next = pyc_mul_265; +assign pyc_sext_266 = {{14{pyc_extract_98[4]}}, pyc_extract_98}; +assign pyc_sext_267 = {{11{pyc_extract_98[4]}}, pyc_extract_98}; +assign pyc_sext_268 = {{14{pyc_extract_105[4]}}, pyc_extract_105}; +assign pyc_extract_269 = pe_int_s0_b1[24:20]; +assign pyc_sext_270 = {{11{pyc_extract_269[4]}}, pyc_extract_269}; +assign pyc_mul_271 = (pyc_sext_266 * pyc_sext_268); +assign pe_int_s1_p2c0_4__next = pyc_mul_271; assign pyc_mul_272 = (pyc_sext_267 * pyc_sext_270); -assign pe_int_s1_p2c1_5__next = pyc_mul_272; -assign pyc_sext_273 = {{27{pyc_extract_128[4]}}, pyc_extract_128}; -assign pyc_sext_274 = {{27{pyc_extract_134[4]}}, pyc_extract_134}; -assign pyc_extract_275 = pe_int_s0_b1[34:30]; -assign pyc_sext_276 = {{27{pyc_extract_275[4]}}, pyc_extract_275}; -assign pyc_mul_277 = (pyc_sext_273 * pyc_sext_274); -assign pe_int_s1_p2c0_6__next = pyc_mul_277; -assign pyc_mul_278 = (pyc_sext_273 * pyc_sext_276); -assign pe_int_s1_p2c1_6__next = pyc_mul_278; -assign pyc_sext_279 = {{27{pyc_extract_129[4]}}, pyc_extract_129}; -assign pyc_sext_280 = {{27{pyc_extract_135[4]}}, pyc_extract_135}; -assign pyc_extract_281 = pe_int_s0_b1[39:35]; -assign pyc_sext_282 = {{27{pyc_extract_281[4]}}, pyc_extract_281}; -assign pyc_mul_283 = (pyc_sext_279 * pyc_sext_280); -assign pe_int_s1_p2c0_7__next = pyc_mul_283; -assign pyc_mul_284 = (pyc_sext_279 * pyc_sext_282); -assign pe_int_s1_p2c1_7__next = pyc_mul_284; -assign pyc_sext_285 = {{27{pyc_extract_153[4]}}, pyc_extract_153}; -assign pyc_extract_286 = pe_int_s0_b1[44:40]; -assign pyc_sext_287 = {{27{pyc_extract_286[4]}}, pyc_extract_286}; -assign pyc_mul_288 = (pyc_sext_285 * pyc_sext_72); -assign pe_int_s1_p2c0_8__next = pyc_mul_288; -assign pyc_mul_289 = (pyc_sext_285 * pyc_sext_287); -assign pe_int_s1_p2c1_8__next = pyc_mul_289; -assign pyc_sext_290 = {{27{pyc_extract_154[4]}}, pyc_extract_154}; -assign pyc_extract_291 = pe_int_s0_b1[49:45]; -assign pyc_sext_292 = {{27{pyc_extract_291[4]}}, pyc_extract_291}; -assign pyc_mul_293 = (pyc_sext_290 * pyc_sext_97); -assign pe_int_s1_p2c0_9__next = pyc_mul_293; -assign pyc_mul_294 = (pyc_sext_290 * pyc_sext_292); -assign pe_int_s1_p2c1_9__next = pyc_mul_294; -assign pyc_sext_295 = {{27{pyc_extract_174[4]}}, pyc_extract_174}; -assign pyc_extract_296 = pe_int_s0_b1[54:50]; -assign pyc_sext_297 = {{27{pyc_extract_296[4]}}, pyc_extract_296}; -assign pyc_mul_298 = (pyc_sext_295 * pyc_sext_122); -assign pe_int_s1_p2c0_10__next = pyc_mul_298; -assign pyc_mul_299 = (pyc_sext_295 * pyc_sext_297); -assign pe_int_s1_p2c1_10__next = pyc_mul_299; -assign pyc_sext_300 = {{27{pyc_extract_175[4]}}, pyc_extract_175}; -assign pyc_extract_301 = pe_int_s0_b1[59:55]; -assign pyc_sext_302 = {{27{pyc_extract_301[4]}}, pyc_extract_301}; -assign pyc_mul_303 = (pyc_sext_300 * pyc_sext_147); -assign pe_int_s1_p2c0_11__next = pyc_mul_303; -assign pyc_mul_304 = (pyc_sext_300 * pyc_sext_302); -assign pe_int_s1_p2c1_11__next = pyc_mul_304; -assign pyc_sext_305 = {{27{pyc_extract_195[4]}}, pyc_extract_195}; -assign pyc_extract_306 = pe_int_s0_b1[64:60]; -assign pyc_sext_307 = {{27{pyc_extract_306[4]}}, pyc_extract_306}; -assign pyc_mul_308 = (pyc_sext_305 * pyc_sext_168); -assign pe_int_s1_p2c0_12__next = pyc_mul_308; -assign pyc_mul_309 = (pyc_sext_305 * pyc_sext_307); -assign pe_int_s1_p2c1_12__next = pyc_mul_309; -assign pyc_sext_310 = {{27{pyc_extract_196[4]}}, pyc_extract_196}; -assign pyc_extract_311 = pe_int_s0_b1[69:65]; -assign pyc_sext_312 = {{27{pyc_extract_311[4]}}, pyc_extract_311}; -assign pyc_mul_313 = (pyc_sext_310 * pyc_sext_189); -assign pe_int_s1_p2c0_13__next = pyc_mul_313; -assign pyc_mul_314 = (pyc_sext_310 * pyc_sext_312); -assign pe_int_s1_p2c1_13__next = pyc_mul_314; -assign pyc_sext_315 = {{27{pyc_extract_216[4]}}, pyc_extract_216}; -assign pyc_extract_316 = pe_int_s0_b1[74:70]; -assign pyc_sext_317 = {{27{pyc_extract_316[4]}}, pyc_extract_316}; -assign pyc_mul_318 = (pyc_sext_315 * pyc_sext_210); -assign pe_int_s1_p2c0_14__next = pyc_mul_318; -assign pyc_mul_319 = (pyc_sext_315 * pyc_sext_317); -assign pe_int_s1_p2c1_14__next = pyc_mul_319; -assign pyc_sext_320 = {{27{pyc_extract_217[4]}}, pyc_extract_217}; -assign pyc_extract_321 = pe_int_s0_b1[79:75]; -assign pyc_sext_322 = {{27{pyc_extract_321[4]}}, pyc_extract_321}; -assign pyc_mul_323 = (pyc_sext_320 * pyc_sext_231); -assign pe_int_s1_p2c0_15__next = pyc_mul_323; -assign pyc_mul_324 = (pyc_sext_320 * pyc_sext_322); -assign pe_int_s1_p2c1_15__next = pyc_mul_324; -assign pyc_comb_325 = pe_int_s1_e1_b1__next; -assign pyc_comb_326 = pe_int_s1_p2a_0__next; -assign pyc_comb_327 = pe_int_s1_p2b0_0__next; -assign pyc_comb_328 = pe_int_s1_p2b1_0__next; -assign pyc_comb_329 = pe_int_s1_p2d0_0__next; -assign pyc_comb_330 = pe_int_s1_p2d1_0__next; -assign pyc_comb_331 = pe_int_s1_p2a_1__next; -assign pyc_comb_332 = pe_int_s1_p2b0_1__next; -assign pyc_comb_333 = pe_int_s1_p2b1_1__next; -assign pyc_comb_334 = pe_int_s1_p2d0_1__next; -assign pyc_comb_335 = pe_int_s1_p2d1_1__next; -assign pyc_comb_336 = pe_int_s1_p2a_2__next; -assign pyc_comb_337 = pe_int_s1_p2b0_2__next; -assign pyc_comb_338 = pe_int_s1_p2b1_2__next; -assign pyc_comb_339 = pe_int_s1_p2d0_2__next; -assign pyc_comb_340 = pe_int_s1_p2d1_2__next; -assign pyc_comb_341 = pe_int_s1_p2a_3__next; -assign pyc_comb_342 = pe_int_s1_p2b0_3__next; -assign pyc_comb_343 = pe_int_s1_p2b1_3__next; -assign pyc_comb_344 = pe_int_s1_p2d0_3__next; -assign pyc_comb_345 = pe_int_s1_p2d1_3__next; -assign pyc_comb_346 = pe_int_s1_p2a_4__next; -assign pyc_comb_347 = pe_int_s1_p2b0_4__next; -assign pyc_comb_348 = pe_int_s1_p2b1_4__next; -assign pyc_comb_349 = pe_int_s1_p2d0_4__next; -assign pyc_comb_350 = pe_int_s1_p2d1_4__next; -assign pyc_comb_351 = pe_int_s1_p2a_5__next; -assign pyc_comb_352 = pe_int_s1_p2b0_5__next; -assign pyc_comb_353 = pe_int_s1_p2b1_5__next; -assign pyc_comb_354 = pe_int_s1_p2d0_5__next; -assign pyc_comb_355 = pe_int_s1_p2d1_5__next; -assign pyc_comb_356 = pe_int_s1_p2a_6__next; -assign pyc_comb_357 = pe_int_s1_p2b0_6__next; -assign pyc_comb_358 = pe_int_s1_p2b1_6__next; -assign pyc_comb_359 = pe_int_s1_p2d0_6__next; -assign pyc_comb_360 = pe_int_s1_p2d1_6__next; -assign pyc_comb_361 = pe_int_s1_p2a_7__next; -assign pyc_comb_362 = pe_int_s1_p2b0_7__next; -assign pyc_comb_363 = pe_int_s1_p2b1_7__next; -assign pyc_comb_364 = pe_int_s1_p2d0_7__next; -assign pyc_comb_365 = pe_int_s1_p2d1_7__next; -assign pyc_comb_366 = pe_int_s1_p2c0_0__next; -assign pyc_comb_367 = pe_int_s1_p2c1_0__next; -assign pyc_comb_368 = pe_int_s1_p2c0_1__next; -assign pyc_comb_369 = pe_int_s1_p2c1_1__next; -assign pyc_comb_370 = pe_int_s1_p2c0_2__next; -assign pyc_comb_371 = pe_int_s1_p2c1_2__next; -assign pyc_comb_372 = pe_int_s1_p2c0_3__next; -assign pyc_comb_373 = pe_int_s1_p2c1_3__next; -assign pyc_comb_374 = pe_int_s1_p2c0_4__next; -assign pyc_comb_375 = pe_int_s1_p2c1_4__next; -assign pyc_comb_376 = pe_int_s1_p2c0_5__next; -assign pyc_comb_377 = pe_int_s1_p2c1_5__next; -assign pyc_comb_378 = pe_int_s1_p2c0_6__next; -assign pyc_comb_379 = pe_int_s1_p2c1_6__next; -assign pyc_comb_380 = pe_int_s1_p2c0_7__next; -assign pyc_comb_381 = pe_int_s1_p2c1_7__next; -assign pyc_comb_382 = pe_int_s1_p2c0_8__next; -assign pyc_comb_383 = pe_int_s1_p2c1_8__next; -assign pyc_comb_384 = pe_int_s1_p2c0_9__next; -assign pyc_comb_385 = pe_int_s1_p2c1_9__next; -assign pyc_comb_386 = pe_int_s1_p2c0_10__next; -assign pyc_comb_387 = pe_int_s1_p2c1_10__next; -assign pyc_comb_388 = pe_int_s1_p2c0_11__next; -assign pyc_comb_389 = pe_int_s1_p2c1_11__next; -assign pyc_comb_390 = pe_int_s1_p2c0_12__next; -assign pyc_comb_391 = pe_int_s1_p2c1_12__next; -assign pyc_comb_392 = pe_int_s1_p2c0_13__next; -assign pyc_comb_393 = pe_int_s1_p2c1_13__next; -assign pyc_comb_394 = pe_int_s1_p2c0_14__next; -assign pyc_comb_395 = pe_int_s1_p2c1_14__next; -assign pyc_comb_396 = pe_int_s1_p2c0_15__next; -assign pyc_comb_397 = pe_int_s1_p2c1_15__next; -assign pe_int_s0_vld = pyc_reg_34; -assign pe_int_s1_vld__next = pe_int_s0_vld; -assign pyc_comb_35 = pe_int_s1_vld__next; -assign pe_int_s0_is_2a = pyc_reg_36; -assign pe_int_s1_is_2a__next = pe_int_s0_is_2a; -assign pyc_comb_37 = pe_int_s1_is_2a__next; -assign pe_int_s0_is_2b = pyc_reg_38; -assign pe_int_s1_is_2b__next = pe_int_s0_is_2b; -assign pyc_comb_39 = pe_int_s1_is_2b__next; -assign pe_int_s1_vld = pyc_reg_398; +assign pe_int_s1_p2c1_4__next = pyc_mul_272; +assign pyc_sext_273 = {{14{pyc_extract_99[4]}}, pyc_extract_99}; +assign pyc_sext_274 = {{11{pyc_extract_99[4]}}, pyc_extract_99}; +assign pyc_sext_275 = {{14{pyc_extract_106[4]}}, pyc_extract_106}; +assign pyc_extract_276 = pe_int_s0_b1[29:25]; +assign pyc_sext_277 = {{11{pyc_extract_276[4]}}, pyc_extract_276}; +assign pyc_mul_278 = (pyc_sext_273 * pyc_sext_275); +assign pe_int_s1_p2c0_5__next = pyc_mul_278; +assign pyc_mul_279 = (pyc_sext_274 * pyc_sext_277); +assign pe_int_s1_p2c1_5__next = pyc_mul_279; +assign pyc_sext_280 = {{14{pyc_extract_124[4]}}, pyc_extract_124}; +assign pyc_sext_281 = {{11{pyc_extract_124[4]}}, pyc_extract_124}; +assign pyc_sext_282 = {{14{pyc_extract_131[4]}}, pyc_extract_131}; +assign pyc_extract_283 = pe_int_s0_b1[34:30]; +assign pyc_sext_284 = {{11{pyc_extract_283[4]}}, pyc_extract_283}; +assign pyc_mul_285 = (pyc_sext_280 * pyc_sext_282); +assign pe_int_s1_p2c0_6__next = pyc_mul_285; +assign pyc_mul_286 = (pyc_sext_281 * pyc_sext_284); +assign pe_int_s1_p2c1_6__next = pyc_mul_286; +assign pyc_sext_287 = {{14{pyc_extract_125[4]}}, pyc_extract_125}; +assign pyc_sext_288 = {{11{pyc_extract_125[4]}}, pyc_extract_125}; +assign pyc_sext_289 = {{14{pyc_extract_132[4]}}, pyc_extract_132}; +assign pyc_extract_290 = pe_int_s0_b1[39:35]; +assign pyc_sext_291 = {{11{pyc_extract_290[4]}}, pyc_extract_290}; +assign pyc_mul_292 = (pyc_sext_287 * pyc_sext_289); +assign pe_int_s1_p2c0_7__next = pyc_mul_292; +assign pyc_mul_293 = (pyc_sext_288 * pyc_sext_291); +assign pe_int_s1_p2c1_7__next = pyc_mul_293; +assign pyc_sext_294 = {{14{pyc_extract_150[4]}}, pyc_extract_150}; +assign pyc_sext_295 = {{11{pyc_extract_150[4]}}, pyc_extract_150}; +assign pyc_sext_296 = {{14{pyc_extract_62[4]}}, pyc_extract_62}; +assign pyc_extract_297 = pe_int_s0_b1[44:40]; +assign pyc_sext_298 = {{11{pyc_extract_297[4]}}, pyc_extract_297}; +assign pyc_mul_299 = (pyc_sext_294 * pyc_sext_296); +assign pe_int_s1_p2c0_8__next = pyc_mul_299; +assign pyc_mul_300 = (pyc_sext_295 * pyc_sext_298); +assign pe_int_s1_p2c1_8__next = pyc_mul_300; +assign pyc_sext_301 = {{14{pyc_extract_151[4]}}, pyc_extract_151}; +assign pyc_sext_302 = {{11{pyc_extract_151[4]}}, pyc_extract_151}; +assign pyc_sext_303 = {{14{pyc_extract_88[4]}}, pyc_extract_88}; +assign pyc_extract_304 = pe_int_s0_b1[49:45]; +assign pyc_sext_305 = {{11{pyc_extract_304[4]}}, pyc_extract_304}; +assign pyc_mul_306 = (pyc_sext_301 * pyc_sext_303); +assign pe_int_s1_p2c0_9__next = pyc_mul_306; +assign pyc_mul_307 = (pyc_sext_302 * pyc_sext_305); +assign pe_int_s1_p2c1_9__next = pyc_mul_307; +assign pyc_sext_308 = {{14{pyc_extract_172[4]}}, pyc_extract_172}; +assign pyc_sext_309 = {{11{pyc_extract_172[4]}}, pyc_extract_172}; +assign pyc_sext_310 = {{14{pyc_extract_114[4]}}, pyc_extract_114}; +assign pyc_extract_311 = pe_int_s0_b1[54:50]; +assign pyc_sext_312 = {{11{pyc_extract_311[4]}}, pyc_extract_311}; +assign pyc_mul_313 = (pyc_sext_308 * pyc_sext_310); +assign pe_int_s1_p2c0_10__next = pyc_mul_313; +assign pyc_mul_314 = (pyc_sext_309 * pyc_sext_312); +assign pe_int_s1_p2c1_10__next = pyc_mul_314; +assign pyc_sext_315 = {{14{pyc_extract_173[4]}}, pyc_extract_173}; +assign pyc_sext_316 = {{11{pyc_extract_173[4]}}, pyc_extract_173}; +assign pyc_sext_317 = {{14{pyc_extract_140[4]}}, pyc_extract_140}; +assign pyc_extract_318 = pe_int_s0_b1[59:55]; +assign pyc_sext_319 = {{11{pyc_extract_318[4]}}, pyc_extract_318}; +assign pyc_mul_320 = (pyc_sext_315 * pyc_sext_317); +assign pe_int_s1_p2c0_11__next = pyc_mul_320; +assign pyc_mul_321 = (pyc_sext_316 * pyc_sext_319); +assign pe_int_s1_p2c1_11__next = pyc_mul_321; +assign pyc_sext_322 = {{14{pyc_extract_194[4]}}, pyc_extract_194}; +assign pyc_sext_323 = {{11{pyc_extract_194[4]}}, pyc_extract_194}; +assign pyc_sext_324 = {{14{pyc_extract_162[4]}}, pyc_extract_162}; +assign pyc_extract_325 = pe_int_s0_b1[64:60]; +assign pyc_sext_326 = {{11{pyc_extract_325[4]}}, pyc_extract_325}; +assign pyc_mul_327 = (pyc_sext_322 * pyc_sext_324); +assign pe_int_s1_p2c0_12__next = pyc_mul_327; +assign pyc_mul_328 = (pyc_sext_323 * pyc_sext_326); +assign pe_int_s1_p2c1_12__next = pyc_mul_328; +assign pyc_sext_329 = {{14{pyc_extract_195[4]}}, pyc_extract_195}; +assign pyc_sext_330 = {{11{pyc_extract_195[4]}}, pyc_extract_195}; +assign pyc_sext_331 = {{14{pyc_extract_184[4]}}, pyc_extract_184}; +assign pyc_extract_332 = pe_int_s0_b1[69:65]; +assign pyc_sext_333 = {{11{pyc_extract_332[4]}}, pyc_extract_332}; +assign pyc_mul_334 = (pyc_sext_329 * pyc_sext_331); +assign pe_int_s1_p2c0_13__next = pyc_mul_334; +assign pyc_mul_335 = (pyc_sext_330 * pyc_sext_333); +assign pe_int_s1_p2c1_13__next = pyc_mul_335; +assign pyc_sext_336 = {{14{pyc_extract_216[4]}}, pyc_extract_216}; +assign pyc_sext_337 = {{11{pyc_extract_216[4]}}, pyc_extract_216}; +assign pyc_sext_338 = {{14{pyc_extract_206[4]}}, pyc_extract_206}; +assign pyc_extract_339 = pe_int_s0_b1[74:70]; +assign pyc_sext_340 = {{11{pyc_extract_339[4]}}, pyc_extract_339}; +assign pyc_mul_341 = (pyc_sext_336 * pyc_sext_338); +assign pe_int_s1_p2c0_14__next = pyc_mul_341; +assign pyc_mul_342 = (pyc_sext_337 * pyc_sext_340); +assign pe_int_s1_p2c1_14__next = pyc_mul_342; +assign pyc_sext_343 = {{14{pyc_extract_217[4]}}, pyc_extract_217}; +assign pyc_sext_344 = {{11{pyc_extract_217[4]}}, pyc_extract_217}; +assign pyc_sext_345 = {{14{pyc_extract_223[4]}}, pyc_extract_223}; +assign pyc_extract_346 = pe_int_s0_b1[79:75]; +assign pyc_sext_347 = {{11{pyc_extract_346[4]}}, pyc_extract_346}; +assign pyc_mul_348 = (pyc_sext_343 * pyc_sext_345); +assign pe_int_s1_p2c0_15__next = pyc_mul_348; +assign pyc_mul_349 = (pyc_sext_344 * pyc_sext_347); +assign pe_int_s1_p2c1_15__next = pyc_mul_349; +assign pyc_comb_350 = pe_int_s1_e1_b1__next; +assign pyc_comb_351 = pe_int_s1_p2a_0__next; +assign pyc_comb_352 = pe_int_s1_p2b0_0__next; +assign pyc_comb_353 = pe_int_s1_p2b1_0__next; +assign pyc_comb_354 = pe_int_s1_p2d0_0__next; +assign pyc_comb_355 = pe_int_s1_p2d1_0__next; +assign pyc_comb_356 = pe_int_s1_p2a_1__next; +assign pyc_comb_357 = pe_int_s1_p2b0_1__next; +assign pyc_comb_358 = pe_int_s1_p2b1_1__next; +assign pyc_comb_359 = pe_int_s1_p2d0_1__next; +assign pyc_comb_360 = pe_int_s1_p2d1_1__next; +assign pyc_comb_361 = pe_int_s1_p2a_2__next; +assign pyc_comb_362 = pe_int_s1_p2b0_2__next; +assign pyc_comb_363 = pe_int_s1_p2b1_2__next; +assign pyc_comb_364 = pe_int_s1_p2d0_2__next; +assign pyc_comb_365 = pe_int_s1_p2d1_2__next; +assign pyc_comb_366 = pe_int_s1_p2a_3__next; +assign pyc_comb_367 = pe_int_s1_p2b0_3__next; +assign pyc_comb_368 = pe_int_s1_p2b1_3__next; +assign pyc_comb_369 = pe_int_s1_p2d0_3__next; +assign pyc_comb_370 = pe_int_s1_p2d1_3__next; +assign pyc_comb_371 = pe_int_s1_p2a_4__next; +assign pyc_comb_372 = pe_int_s1_p2b0_4__next; +assign pyc_comb_373 = pe_int_s1_p2b1_4__next; +assign pyc_comb_374 = pe_int_s1_p2d0_4__next; +assign pyc_comb_375 = pe_int_s1_p2d1_4__next; +assign pyc_comb_376 = pe_int_s1_p2a_5__next; +assign pyc_comb_377 = pe_int_s1_p2b0_5__next; +assign pyc_comb_378 = pe_int_s1_p2b1_5__next; +assign pyc_comb_379 = pe_int_s1_p2d0_5__next; +assign pyc_comb_380 = pe_int_s1_p2d1_5__next; +assign pyc_comb_381 = pe_int_s1_p2a_6__next; +assign pyc_comb_382 = pe_int_s1_p2b0_6__next; +assign pyc_comb_383 = pe_int_s1_p2b1_6__next; +assign pyc_comb_384 = pe_int_s1_p2d0_6__next; +assign pyc_comb_385 = pe_int_s1_p2d1_6__next; +assign pyc_comb_386 = pe_int_s1_p2a_7__next; +assign pyc_comb_387 = pe_int_s1_p2b0_7__next; +assign pyc_comb_388 = pe_int_s1_p2b1_7__next; +assign pyc_comb_389 = pe_int_s1_p2d0_7__next; +assign pyc_comb_390 = pe_int_s1_p2d1_7__next; +assign pyc_comb_391 = pe_int_s1_p2c0_0__next; +assign pyc_comb_392 = pe_int_s1_p2c1_0__next; +assign pyc_comb_393 = pe_int_s1_p2c0_1__next; +assign pyc_comb_394 = pe_int_s1_p2c1_1__next; +assign pyc_comb_395 = pe_int_s1_p2c0_2__next; +assign pyc_comb_396 = pe_int_s1_p2c1_2__next; +assign pyc_comb_397 = pe_int_s1_p2c0_3__next; +assign pyc_comb_398 = pe_int_s1_p2c1_3__next; +assign pyc_comb_399 = pe_int_s1_p2c0_4__next; +assign pyc_comb_400 = pe_int_s1_p2c1_4__next; +assign pyc_comb_401 = pe_int_s1_p2c0_5__next; +assign pyc_comb_402 = pe_int_s1_p2c1_5__next; +assign pyc_comb_403 = pe_int_s1_p2c0_6__next; +assign pyc_comb_404 = pe_int_s1_p2c1_6__next; +assign pyc_comb_405 = pe_int_s1_p2c0_7__next; +assign pyc_comb_406 = pe_int_s1_p2c1_7__next; +assign pyc_comb_407 = pe_int_s1_p2c0_8__next; +assign pyc_comb_408 = pe_int_s1_p2c1_8__next; +assign pyc_comb_409 = pe_int_s1_p2c0_9__next; +assign pyc_comb_410 = pe_int_s1_p2c1_9__next; +assign pyc_comb_411 = pe_int_s1_p2c0_10__next; +assign pyc_comb_412 = pe_int_s1_p2c1_10__next; +assign pyc_comb_413 = pe_int_s1_p2c0_11__next; +assign pyc_comb_414 = pe_int_s1_p2c1_11__next; +assign pyc_comb_415 = pe_int_s1_p2c0_12__next; +assign pyc_comb_416 = pe_int_s1_p2c1_12__next; +assign pyc_comb_417 = pe_int_s1_p2c0_13__next; +assign pyc_comb_418 = pe_int_s1_p2c1_13__next; +assign pyc_comb_419 = pe_int_s1_p2c0_14__next; +assign pyc_comb_420 = pe_int_s1_p2c1_14__next; +assign pyc_comb_421 = pe_int_s1_p2c0_15__next; +assign pyc_comb_422 = pe_int_s1_p2c1_15__next; +assign pe_int_s0_is_2c = pyc_reg_35; +assign pe_int_s1_is_2c__next = pe_int_s0_is_2c; +assign pyc_comb_36 = pe_int_s1_is_2c__next; +assign pe_int_s0_e1_a = pyc_reg_40; +assign pe_int_s1_e1_a__next = pe_int_s0_e1_a; +assign pyc_comb_41 = pe_int_s1_e1_a__next; +assign pe_int_s1_vld = pyc_reg_423; assign pe_int_s2_vld__next = pe_int_s1_vld; -assign pyc_comb_399 = pe_int_s2_vld__next; -assign pe_int_s1_is_2a = pyc_reg_400; +assign pyc_comb_424 = pe_int_s2_vld__next; +assign pe_int_s1_is_2a = pyc_reg_425; assign pe_int_s2_is_2a__next = pe_int_s1_is_2a; -assign pyc_comb_401 = pe_int_s2_is_2a__next; -assign pe_int_s1_is_2b = pyc_reg_402; +assign pyc_comb_426 = pe_int_s2_is_2a__next; +assign pe_int_s1_is_2b = pyc_reg_427; assign pe_int_s2_is_2b__next = pe_int_s1_is_2b; -assign pyc_comb_403 = pe_int_s2_is_2b__next; -assign pe_int_s1_is_2c = pyc_reg_404; +assign pyc_comb_428 = pe_int_s2_is_2b__next; +assign pe_int_s0_e1_b0 = pyc_reg_42; +assign pe_int_s1_e1_b0__next = pe_int_s0_e1_b0; +assign pyc_comb_43 = pe_int_s1_e1_b0__next; +assign pe_int_s1_is_2c = pyc_reg_429; assign pe_int_s2_is_2c__next = pe_int_s1_is_2c; -assign pyc_comb_405 = pe_int_s2_is_2c__next; -assign pe_int_s1_e1_a = pyc_reg_407; +assign pyc_comb_430 = pe_int_s2_is_2c__next; +assign pe_int_s1_e1_a = pyc_reg_431; assign pe_int_s2_e1_a__next = pe_int_s1_e1_a; -assign pyc_comb_408 = pe_int_s2_e1_a__next; -assign pe_int_s0_is_2c = pyc_reg_40; -assign pe_int_s1_is_2c__next = pe_int_s0_is_2c; -assign pyc_comb_41 = pe_int_s1_is_2c__next; -assign pe_int_s1_e1_b0 = pyc_reg_409; +assign pyc_comb_432 = pe_int_s2_e1_a__next; +assign pe_int_s1_e1_b0 = pyc_reg_433; assign pe_int_s2_e1_b0__next = pe_int_s1_e1_b0; -assign pyc_comb_410 = pe_int_s2_e1_b0__next; -assign pe_int_s1_e1_b1 = pyc_reg_411; +assign pyc_comb_434 = pe_int_s2_e1_b0__next; +assign pe_int_s1_e1_b1 = pyc_reg_435; assign pe_int_s2_e1_b1__next = pe_int_s1_e1_b1; -assign pyc_comb_412 = pe_int_s2_e1_b1__next; -assign pe_int_s0_is_2d = pyc_reg_42; -assign pe_int_s1_is_2d__next = pe_int_s0_is_2d; -assign pyc_comb_43 = pe_int_s1_is_2d__next; -assign pe_int_s0_e1_a = pyc_reg_47; -assign pe_int_s1_e1_a__next = pe_int_s0_e1_a; -assign pyc_comb_48 = pe_int_s1_e1_a__next; -assign pe_int_s2_vld = pyc_reg_494; +assign pyc_comb_436 = pe_int_s2_e1_b1__next; +assign pe_int_s2_vld = pyc_reg_518; assign pe_int_out_vld__next = pe_int_s2_vld; -assign pyc_concat_495 = {pyc_comb_405, pyc_comb_403, pyc_comb_401}; -assign pyc_concat_496 = {pyc_comb_22, pyc_comb_22, pyc_comb_22}; -assign pyc_comb_497 = pe_int_s2_vld; -assign pyc_comb_498 = pe_int_out_vld__next; -assign pyc_comb_499 = pyc_concat_495; -assign pyc_comb_500 = pyc_concat_496; -assign pe_int_s0_e1_b0 = pyc_reg_49; -assign pe_int_s1_e1_b0__next = pe_int_s0_e1_b0; -assign pyc_comb_50 = pe_int_s1_e1_b0__next; -assign pyc_extract_502 = pyc_reg_501[0]; -assign pyc_extract_503 = pyc_reg_501[1]; -assign pyc_extract_504 = pyc_reg_501[2]; -assign pe_int_s2_is_2a = pyc_extract_502; -assign pe_int_s2_is_2b = pyc_extract_503; -assign pe_int_s2_is_2c = pyc_extract_504; -assign pyc_comb_505 = pe_int_s2_is_2a; -assign pyc_comb_506 = pe_int_s2_is_2b; -assign pyc_comb_507 = pe_int_s2_is_2c; -assign pe_int_s2_s2a = pyc_reg_511; -assign _v5_bal_1__next = pe_int_s2_s2a; -assign pyc_comb_512 = pe_int_s2_s2a; -assign pyc_comb_513 = _v5_bal_1__next; -assign pe_int_s2_s2c1_hi = pyc_reg_521; -assign pyc_extract_522 = pe_int_s2_e1_a[0]; -assign pyc_zext_523 = {{1{1'b0}}, pyc_extract_522}; -assign pyc_extract_524 = pe_int_s2_e1_b0[0]; -assign pyc_zext_525 = {{1{1'b0}}, pyc_extract_524}; -assign pyc_add_526 = (pyc_zext_523 + pyc_zext_525); -assign pyc_extract_527 = pe_int_s2_e1_a[1]; -assign pyc_zext_528 = {{1{1'b0}}, pyc_extract_527}; -assign pyc_extract_529 = pe_int_s2_e1_b0[1]; -assign pyc_zext_530 = {{1{1'b0}}, pyc_extract_529}; -assign pyc_add_531 = (pyc_zext_528 + pyc_zext_530); -assign pyc_eq_532 = (pyc_add_526 == pyc_comb_19); -assign pyc_eq_533 = (pyc_add_526 == pyc_comb_17); -assign pyc_shli_534 = (pe_int_s2_s2c0_lo << 1); -assign pyc_shli_535 = (pe_int_s2_s2c0_lo << 2); -assign pyc_mux_536 = (pyc_eq_533 ? pyc_shli_534 : pyc_shli_535); -assign pyc_mux_537 = (pyc_eq_532 ? pe_int_s2_s2c0_lo : pyc_mux_536); -assign pyc_eq_538 = (pyc_add_531 == pyc_comb_19); -assign pyc_eq_539 = (pyc_add_531 == pyc_comb_17); -assign pyc_shli_540 = (pe_int_s2_s2c0_hi << 1); -assign pyc_shli_541 = (pe_int_s2_s2c0_hi << 2); -assign pyc_mux_542 = (pyc_eq_539 ? pyc_shli_540 : pyc_shli_541); -assign pyc_mux_543 = (pyc_eq_538 ? pe_int_s2_s2c0_hi : pyc_mux_542); -assign pyc_add_544 = (pyc_mux_537 + pyc_mux_543); -assign pyc_extract_545 = pe_int_s2_e1_b1[0]; -assign pyc_zext_546 = {{1{1'b0}}, pyc_extract_545}; -assign pyc_add_547 = (pyc_zext_523 + pyc_zext_546); -assign pyc_extract_548 = pe_int_s2_e1_b1[1]; -assign pyc_zext_549 = {{1{1'b0}}, pyc_extract_548}; -assign pyc_add_550 = (pyc_zext_528 + pyc_zext_549); -assign pyc_eq_551 = (pyc_add_547 == pyc_comb_19); -assign pyc_eq_552 = (pyc_add_547 == pyc_comb_17); -assign pyc_shli_553 = (pe_int_s2_s2c1_lo << 1); -assign pyc_shli_554 = (pe_int_s2_s2c1_lo << 2); -assign pyc_mux_555 = (pyc_eq_552 ? pyc_shli_553 : pyc_shli_554); -assign pyc_mux_556 = (pyc_eq_551 ? pe_int_s2_s2c1_lo : pyc_mux_555); -assign pyc_eq_557 = (pyc_add_550 == pyc_comb_19); -assign pyc_eq_558 = (pyc_add_550 == pyc_comb_17); -assign pyc_shli_559 = (pe_int_s2_s2c1_hi << 1); -assign pyc_shli_560 = (pe_int_s2_s2c1_hi << 2); -assign pyc_mux_561 = (pyc_eq_558 ? pyc_shli_559 : pyc_shli_560); -assign pyc_mux_562 = (pyc_eq_557 ? pe_int_s2_s2c1_hi : pyc_mux_561); -assign pyc_add_563 = (pyc_mux_556 + pyc_mux_562); -assign pyc_mux_564 = (pyc_comb_507 ? pyc_add_544 : pe_int_s2_s2d0); -assign pyc_mux_565 = (pyc_comb_506 ? pe_int_s2_s2b0 : pyc_mux_564); -assign pyc_mux_566 = (pyc_comb_505 ? pyc_comb_512 : pyc_mux_565); -assign pyc_comb_567 = pyc_add_563; -assign pyc_comb_568 = pyc_mux_566; -assign _v5_bal_1 = pyc_reg_569; -assign _v5_bal_2__next = _v5_bal_1; -assign pyc_comb_570 = _v5_bal_2__next; -assign pyc_mux_572 = (pyc_comb_507 ? pyc_comb_567 : pe_int_s2_s2d1); -assign pyc_mux_573 = (pyc_comb_506 ? pe_int_s2_s2b1 : pyc_mux_572); -assign pyc_mux_574 = (pyc_comb_505 ? pyc_comb_18 : pyc_mux_573); -assign pyc_extract_575 = pyc_comb_568[18:0]; -assign pe_int_out0__next = pyc_extract_575; -assign pyc_extract_576 = pyc_mux_574[15:0]; -assign pyc_comb_577 = pe_int_out0__next; -assign pyc_comb_578 = pyc_extract_576; -assign pe_int_out1 = pyc_reg_579; -assign pyc_mux_580 = (pyc_comb_505 ? pe_int_out1 : pyc_comb_578); -assign pyc_mux_581 = (pyc_comb_497 ? pyc_mux_580 : pe_int_out1); -assign pyc_comb_582 = pe_int_out1; -assign pyc_comb_583 = pyc_mux_581; -assign pe_int_out1__next = pyc_comb_583; +assign pyc_concat_519 = {pyc_comb_430, pyc_comb_428, pyc_comb_426}; +assign pyc_concat_520 = {pyc_comb_18, pyc_comb_18, pyc_comb_18}; +assign pyc_comb_521 = pe_int_s2_vld; +assign pyc_comb_522 = pe_int_out_vld__next; +assign pyc_comb_523 = pyc_concat_519; +assign pyc_comb_524 = pyc_concat_520; +assign pyc_extract_526 = pyc_reg_525[0]; +assign pyc_extract_527 = pyc_reg_525[1]; +assign pyc_extract_528 = pyc_reg_525[2]; +assign pe_int_s2_is_2a = pyc_extract_526; +assign pe_int_s2_is_2b = pyc_extract_527; +assign pe_int_s2_is_2c = pyc_extract_528; +assign pyc_comb_529 = pe_int_s2_is_2a; +assign pyc_comb_530 = pe_int_s2_is_2b; +assign pyc_comb_531 = pe_int_s2_is_2c; +assign pe_int_s2_s2c1_hi = pyc_reg_543; +assign pyc_extract_544 = pe_int_s2_e1_a[0]; +assign pyc_zext_545 = {{1{1'b0}}, pyc_extract_544}; +assign pyc_extract_546 = pe_int_s2_e1_b0[0]; +assign pyc_zext_547 = {{1{1'b0}}, pyc_extract_546}; +assign pyc_add_548 = (pyc_zext_545 + pyc_zext_547); +assign pyc_extract_549 = pe_int_s2_e1_a[1]; +assign pyc_zext_550 = {{1{1'b0}}, pyc_extract_549}; +assign pyc_extract_551 = pe_int_s2_e1_b0[1]; +assign pyc_zext_552 = {{1{1'b0}}, pyc_extract_551}; +assign pyc_add_553 = (pyc_zext_550 + pyc_zext_552); +assign pyc_eq_554 = (pyc_add_548 == pyc_comb_15); +assign pyc_eq_555 = (pyc_add_548 == pyc_comb_12); +assign pyc_shli_556 = (pe_int_s2_s2c0_lo << 1); +assign pyc_shli_557 = (pe_int_s2_s2c0_lo << 2); +assign pyc_mux_558 = (pyc_eq_555 ? pyc_shli_556 : pyc_shli_557); +assign pyc_mux_559 = (pyc_eq_554 ? pe_int_s2_s2c0_lo : pyc_mux_558); +assign pyc_eq_560 = (pyc_add_553 == pyc_comb_15); +assign pyc_eq_561 = (pyc_add_553 == pyc_comb_12); +assign pyc_shli_562 = (pe_int_s2_s2c0_hi << 1); +assign pyc_shli_563 = (pe_int_s2_s2c0_hi << 2); +assign pyc_mux_564 = (pyc_eq_561 ? pyc_shli_562 : pyc_shli_563); +assign pyc_mux_565 = (pyc_eq_560 ? pe_int_s2_s2c0_hi : pyc_mux_564); +assign pyc_add_566 = (pyc_mux_559 + pyc_mux_565); +assign pyc_extract_567 = pe_int_s2_e1_b1[0]; +assign pyc_zext_568 = {{1{1'b0}}, pyc_extract_567}; +assign pyc_add_569 = (pyc_zext_545 + pyc_zext_568); +assign pyc_extract_570 = pe_int_s2_e1_b1[1]; +assign pyc_zext_571 = {{1{1'b0}}, pyc_extract_570}; +assign pyc_add_572 = (pyc_zext_550 + pyc_zext_571); +assign pyc_eq_573 = (pyc_add_569 == pyc_comb_15); +assign pyc_eq_574 = (pyc_add_569 == pyc_comb_12); +assign pyc_shli_575 = (pe_int_s2_s2c1_lo << 1); +assign pyc_shli_576 = (pe_int_s2_s2c1_lo << 2); +assign pyc_mux_577 = (pyc_eq_574 ? pyc_shli_575 : pyc_shli_576); +assign pyc_mux_578 = (pyc_eq_573 ? pe_int_s2_s2c1_lo : pyc_mux_577); +assign pyc_eq_579 = (pyc_add_572 == pyc_comb_15); +assign pyc_eq_580 = (pyc_add_572 == pyc_comb_12); +assign pyc_shli_581 = (pe_int_s2_s2c1_hi << 1); +assign pyc_shli_582 = (pe_int_s2_s2c1_hi << 2); +assign pyc_mux_583 = (pyc_eq_580 ? pyc_shli_581 : pyc_shli_582); +assign pyc_mux_584 = (pyc_eq_579 ? pe_int_s2_s2c1_hi : pyc_mux_583); +assign pyc_add_585 = (pyc_mux_578 + pyc_mux_584); +assign pyc_mux_586 = (pyc_comb_531 ? pyc_add_566 : pe_int_s2_s2d0); +assign pyc_mux_587 = (pyc_comb_530 ? pe_int_s2_s2b0 : pyc_mux_586); +assign pyc_mux_588 = (pyc_comb_529 ? pe_int_s2_s2a : pyc_mux_587); +assign pe_int_out0__next = pyc_mux_588; +assign pyc_mux_589 = (pyc_comb_531 ? pyc_add_585 : pe_int_s2_s2d1); +assign pyc_mux_590 = (pyc_comb_530 ? pe_int_s2_s2b1 : pyc_mux_589); +assign pyc_comb_591 = pe_int_out0__next; +assign pyc_comb_592 = pyc_mux_590; +assign pe_int_out1 = pyc_reg_593; +assign pyc_mux_594 = (pyc_comb_529 ? pe_int_out1 : pyc_comb_592); +assign pyc_mux_595 = (pyc_comb_521 ? pyc_mux_594 : pe_int_out1); +assign pyc_comb_596 = pe_int_out1; +assign pyc_comb_597 = pyc_mux_595; +assign pe_int_out1__next = pyc_comb_597; // --- Submodules -PE_INT_WALLACE_DOT8_TREE pe_int_s2a_wallace ( - .clk(clk), - .rst(rst), - .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2a_0), - .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2a_1), - .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2a_2), - .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2a_3), - .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2a_4), - .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2a_5), - .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2a_6), - .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2a_7), - .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_485) -); -PE_INT_WALLACE_DOT8_TREE pe_int_s2b0_wallace ( - .clk(clk), - .rst(rst), - .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2b0_0), - .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2b0_1), - .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2b0_2), - .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2b0_3), - .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2b0_4), - .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2b0_5), - .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2b0_6), - .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2b0_7), - .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_486) -); -PE_INT_WALLACE_DOT8_TREE pe_int_s2b1_wallace ( - .clk(clk), - .rst(rst), - .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2b1_0), - .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2b1_1), - .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2b1_2), - .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2b1_3), - .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2b1_4), - .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2b1_5), - .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2b1_6), - .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2b1_7), - .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_487) -); -PE_INT_WALLACE_DOT8_TREE pe_int_s2d0_wallace ( - .clk(clk), - .rst(rst), - .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2d0_0), - .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2d0_1), - .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2d0_2), - .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2d0_3), - .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2d0_4), - .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2d0_5), - .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2d0_6), - .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2d0_7), - .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_488) -); -PE_INT_WALLACE_DOT8_TREE pe_int_s2d1_wallace ( - .clk(clk), - .rst(rst), - .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2d1_0), - .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2d1_1), - .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2d1_2), - .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2d1_3), - .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2d1_4), - .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2d1_5), - .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2d1_6), - .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2d1_7), - .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_489) -); -PE_INT_WALLACE_DOT8_TREE pe_int_s2c0_lo_wallace ( - .clk(clk), - .rst(rst), - .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2c0_0), - .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2c0_1), - .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2c0_2), - .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2c0_3), - .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2c0_4), - .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2c0_5), - .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2c0_6), - .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2c0_7), - .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_490) -); -PE_INT_WALLACE_DOT8_TREE pe_int_s2c0_hi_wallace ( - .clk(clk), - .rst(rst), - .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2c0_8), - .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2c0_9), - .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2c0_10), - .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2c0_11), - .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2c0_12), - .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2c0_13), - .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2c0_14), - .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2c0_15), - .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_491) -); -PE_INT_WALLACE_DOT8_TREE pe_int_s2c1_lo_wallace ( - .clk(clk), - .rst(rst), - .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2c1_0), - .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2c1_1), - .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2c1_2), - .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2c1_3), - .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2c1_4), - .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2c1_5), - .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2c1_6), - .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2c1_7), - .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_492) -); -PE_INT_WALLACE_DOT8_TREE pe_int_s2c1_hi_wallace ( - .clk(clk), - .rst(rst), - .PE_INT_WALLACE_DOT8_TREE_in0(pe_int_s1_p2c1_8), - .PE_INT_WALLACE_DOT8_TREE_in1(pe_int_s1_p2c1_9), - .PE_INT_WALLACE_DOT8_TREE_in2(pe_int_s1_p2c1_10), - .PE_INT_WALLACE_DOT8_TREE_in3(pe_int_s1_p2c1_11), - .PE_INT_WALLACE_DOT8_TREE_in4(pe_int_s1_p2c1_12), - .PE_INT_WALLACE_DOT8_TREE_in5(pe_int_s1_p2c1_13), - .PE_INT_WALLACE_DOT8_TREE_in6(pe_int_s1_p2c1_14), - .PE_INT_WALLACE_DOT8_TREE_in7(pe_int_s1_p2c1_15), - .PE_INT_WALLACE_DOT8_TREE_sum(pyc_instance_493) +PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2a_wallace ( + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2a_0), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2a_1), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2a_2), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2a_3), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2a_4), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2a_5), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2a_6), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2a_7), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_509) +); +PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2b0_wallace ( + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2b0_0), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2b0_1), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2b0_2), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2b0_3), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2b0_4), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2b0_5), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2b0_6), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2b0_7), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_510) +); +PE_INT_WALLACE_DOT8_TREE_W16 pe_int_s2b1_wallace ( + .PE_INT_WALLACE_DOT8_TREE_W16_in0(pe_int_s1_p2b1_0), + .PE_INT_WALLACE_DOT8_TREE_W16_in1(pe_int_s1_p2b1_1), + .PE_INT_WALLACE_DOT8_TREE_W16_in2(pe_int_s1_p2b1_2), + .PE_INT_WALLACE_DOT8_TREE_W16_in3(pe_int_s1_p2b1_3), + .PE_INT_WALLACE_DOT8_TREE_W16_in4(pe_int_s1_p2b1_4), + .PE_INT_WALLACE_DOT8_TREE_W16_in5(pe_int_s1_p2b1_5), + .PE_INT_WALLACE_DOT8_TREE_W16_in6(pe_int_s1_p2b1_6), + .PE_INT_WALLACE_DOT8_TREE_W16_in7(pe_int_s1_p2b1_7), + .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_511) +); +PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2d0_wallace ( + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2d0_0), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2d0_1), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2d0_2), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2d0_3), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2d0_4), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2d0_5), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2d0_6), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2d0_7), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_512) +); +PE_INT_WALLACE_DOT8_TREE_W16 pe_int_s2d1_wallace ( + .PE_INT_WALLACE_DOT8_TREE_W16_in0(pe_int_s1_p2d1_0), + .PE_INT_WALLACE_DOT8_TREE_W16_in1(pe_int_s1_p2d1_1), + .PE_INT_WALLACE_DOT8_TREE_W16_in2(pe_int_s1_p2d1_2), + .PE_INT_WALLACE_DOT8_TREE_W16_in3(pe_int_s1_p2d1_3), + .PE_INT_WALLACE_DOT8_TREE_W16_in4(pe_int_s1_p2d1_4), + .PE_INT_WALLACE_DOT8_TREE_W16_in5(pe_int_s1_p2d1_5), + .PE_INT_WALLACE_DOT8_TREE_W16_in6(pe_int_s1_p2d1_6), + .PE_INT_WALLACE_DOT8_TREE_W16_in7(pe_int_s1_p2d1_7), + .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_513) +); +PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2c0_lo_wallace ( + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2c0_0), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2c0_1), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2c0_2), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2c0_3), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2c0_4), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2c0_5), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2c0_6), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2c0_7), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_514) +); +PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2c0_hi_wallace ( + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2c0_8), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2c0_9), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2c0_10), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2c0_11), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2c0_12), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2c0_13), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2c0_14), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2c0_15), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_515) +); +PE_INT_WALLACE_DOT8_TREE_W16 pe_int_s2c1_lo_wallace ( + .PE_INT_WALLACE_DOT8_TREE_W16_in0(pe_int_s1_p2c1_0), + .PE_INT_WALLACE_DOT8_TREE_W16_in1(pe_int_s1_p2c1_1), + .PE_INT_WALLACE_DOT8_TREE_W16_in2(pe_int_s1_p2c1_2), + .PE_INT_WALLACE_DOT8_TREE_W16_in3(pe_int_s1_p2c1_3), + .PE_INT_WALLACE_DOT8_TREE_W16_in4(pe_int_s1_p2c1_4), + .PE_INT_WALLACE_DOT8_TREE_W16_in5(pe_int_s1_p2c1_5), + .PE_INT_WALLACE_DOT8_TREE_W16_in6(pe_int_s1_p2c1_6), + .PE_INT_WALLACE_DOT8_TREE_W16_in7(pe_int_s1_p2c1_7), + .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_516) +); +PE_INT_WALLACE_DOT8_TREE_W16 pe_int_s2c1_hi_wallace ( + .PE_INT_WALLACE_DOT8_TREE_W16_in0(pe_int_s1_p2c1_8), + .PE_INT_WALLACE_DOT8_TREE_W16_in1(pe_int_s1_p2c1_9), + .PE_INT_WALLACE_DOT8_TREE_W16_in2(pe_int_s1_p2c1_10), + .PE_INT_WALLACE_DOT8_TREE_W16_in3(pe_int_s1_p2c1_11), + .PE_INT_WALLACE_DOT8_TREE_W16_in4(pe_int_s1_p2c1_12), + .PE_INT_WALLACE_DOT8_TREE_W16_in5(pe_int_s1_p2c1_13), + .PE_INT_WALLACE_DOT8_TREE_W16_in6(pe_int_s1_p2c1_14), + .PE_INT_WALLACE_DOT8_TREE_W16_in7(pe_int_s1_p2c1_15), + .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_517) ); // --- Sequential primitives -PYC_REG #(.WIDTH(1)) pyc_reg_34_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_29_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_29), - .init(pyc_comb_22), - .q(pyc_reg_34) -); -PYC_REG #(.WIDTH(1)) pyc_reg_36_inst ( - .clk(clk), - .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_30), - .init(pyc_comb_22), - .q(pyc_reg_36) + .en(pyc_comb_17), + .d(pyc_comb_25), + .init(pyc_comb_18), + .q(pyc_reg_29) ); -PYC_REG #(.WIDTH(1)) pyc_reg_38_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_31_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_31), - .init(pyc_comb_22), - .q(pyc_reg_38) + .en(pyc_comb_17), + .d(pyc_comb_26), + .init(pyc_comb_18), + .q(pyc_reg_31) ); -PYC_REG #(.WIDTH(1)) pyc_reg_398_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_33_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_35), - .init(pyc_comb_22), - .q(pyc_reg_398) + .en(pyc_comb_17), + .d(pyc_comb_27), + .init(pyc_comb_18), + .q(pyc_reg_33) ); -PYC_REG #(.WIDTH(1)) pyc_reg_40_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_35_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_32), - .init(pyc_comb_22), - .q(pyc_reg_40) + .en(pyc_comb_17), + .d(pyc_comb_28), + .init(pyc_comb_18), + .q(pyc_reg_35) ); -PYC_REG #(.WIDTH(1)) pyc_reg_400_inst ( +PYC_REG #(.WIDTH(80)) pyc_reg_37_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_37), - .init(pyc_comb_22), - .q(pyc_reg_400) + .en(pyc_comb_17), + .d(pyc_comb_24), + .init(pyc_comb_16), + .q(pyc_reg_37) ); -PYC_REG #(.WIDTH(1)) pyc_reg_402_inst ( +PYC_REG #(.WIDTH(80)) pyc_reg_38_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_39), - .init(pyc_comb_22), - .q(pyc_reg_402) + .en(pyc_comb_17), + .d(pyc_comb_23), + .init(pyc_comb_16), + .q(pyc_reg_38) ); -PYC_REG #(.WIDTH(1)) pyc_reg_404_inst ( +PYC_REG #(.WIDTH(80)) pyc_reg_39_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_41), - .init(pyc_comb_22), - .q(pyc_reg_404) + .en(pyc_comb_17), + .d(pyc_comb_22), + .init(pyc_comb_16), + .q(pyc_reg_39) ); -PYC_REG #(.WIDTH(1)) pyc_reg_406_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_40_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_43), - .init(pyc_comb_22), - .q(pyc_reg_406) + .en(pyc_comb_17), + .d(pyc_comb_21), + .init(pyc_comb_15), + .q(pyc_reg_40) ); -PYC_REG #(.WIDTH(2)) pyc_reg_407_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_42_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_48), - .init(pyc_comb_19), - .q(pyc_reg_407) + .en(pyc_comb_17), + .d(pyc_comb_20), + .init(pyc_comb_15), + .q(pyc_reg_42) ); -PYC_REG #(.WIDTH(2)) pyc_reg_409_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_423_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_50), - .init(pyc_comb_19), - .q(pyc_reg_409) + .en(pyc_comb_17), + .d(pyc_comb_30), + .init(pyc_comb_18), + .q(pyc_reg_423) ); -PYC_REG #(.WIDTH(2)) pyc_reg_411_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_425_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_325), - .init(pyc_comb_19), - .q(pyc_reg_411) + .en(pyc_comb_17), + .d(pyc_comb_32), + .init(pyc_comb_18), + .q(pyc_reg_425) ); -PYC_REG #(.WIDTH(32)) pyc_reg_413_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_427_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_326), + .en(pyc_comb_17), + .d(pyc_comb_34), .init(pyc_comb_18), - .q(pyc_reg_413) + .q(pyc_reg_427) ); -PYC_REG #(.WIDTH(32)) pyc_reg_414_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_429_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_331), + .en(pyc_comb_17), + .d(pyc_comb_36), .init(pyc_comb_18), - .q(pyc_reg_414) + .q(pyc_reg_429) ); -PYC_REG #(.WIDTH(32)) pyc_reg_415_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_431_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_336), - .init(pyc_comb_18), - .q(pyc_reg_415) + .en(pyc_comb_17), + .d(pyc_comb_41), + .init(pyc_comb_15), + .q(pyc_reg_431) ); -PYC_REG #(.WIDTH(32)) pyc_reg_416_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_433_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_341), - .init(pyc_comb_18), - .q(pyc_reg_416) + .en(pyc_comb_17), + .d(pyc_comb_43), + .init(pyc_comb_15), + .q(pyc_reg_433) ); -PYC_REG #(.WIDTH(32)) pyc_reg_417_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_435_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_346), - .init(pyc_comb_18), - .q(pyc_reg_417) + .en(pyc_comb_17), + .d(pyc_comb_350), + .init(pyc_comb_15), + .q(pyc_reg_435) ); -PYC_REG #(.WIDTH(32)) pyc_reg_418_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_437_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_351), - .init(pyc_comb_18), - .q(pyc_reg_418) + .init(pyc_comb_14), + .q(pyc_reg_437) ); -PYC_REG #(.WIDTH(32)) pyc_reg_419_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_438_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_356), - .init(pyc_comb_18), - .q(pyc_reg_419) + .init(pyc_comb_14), + .q(pyc_reg_438) ); -PYC_REG #(.WIDTH(1)) pyc_reg_42_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_439_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_33), - .init(pyc_comb_22), - .q(pyc_reg_42) + .en(pyc_comb_17), + .d(pyc_comb_361), + .init(pyc_comb_14), + .q(pyc_reg_439) ); -PYC_REG #(.WIDTH(32)) pyc_reg_420_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_44_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_361), - .init(pyc_comb_18), - .q(pyc_reg_420) + .en(pyc_comb_17), + .d(pyc_comb_19), + .init(pyc_comb_15), + .q(pyc_reg_44) ); -PYC_REG #(.WIDTH(32)) pyc_reg_421_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_440_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_327), - .init(pyc_comb_18), - .q(pyc_reg_421) + .en(pyc_comb_17), + .d(pyc_comb_366), + .init(pyc_comb_14), + .q(pyc_reg_440) ); -PYC_REG #(.WIDTH(32)) pyc_reg_422_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_441_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_332), - .init(pyc_comb_18), - .q(pyc_reg_422) + .en(pyc_comb_17), + .d(pyc_comb_371), + .init(pyc_comb_14), + .q(pyc_reg_441) ); -PYC_REG #(.WIDTH(32)) pyc_reg_423_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_442_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_337), - .init(pyc_comb_18), - .q(pyc_reg_423) + .en(pyc_comb_17), + .d(pyc_comb_376), + .init(pyc_comb_14), + .q(pyc_reg_442) ); -PYC_REG #(.WIDTH(32)) pyc_reg_424_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_443_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_342), - .init(pyc_comb_18), - .q(pyc_reg_424) + .en(pyc_comb_17), + .d(pyc_comb_381), + .init(pyc_comb_14), + .q(pyc_reg_443) ); -PYC_REG #(.WIDTH(32)) pyc_reg_425_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_444_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_347), - .init(pyc_comb_18), - .q(pyc_reg_425) + .en(pyc_comb_17), + .d(pyc_comb_386), + .init(pyc_comb_14), + .q(pyc_reg_444) ); -PYC_REG #(.WIDTH(32)) pyc_reg_426_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_445_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_352), - .init(pyc_comb_18), - .q(pyc_reg_426) + .init(pyc_comb_14), + .q(pyc_reg_445) ); -PYC_REG #(.WIDTH(32)) pyc_reg_427_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_446_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_357), - .init(pyc_comb_18), - .q(pyc_reg_427) + .init(pyc_comb_14), + .q(pyc_reg_446) ); -PYC_REG #(.WIDTH(32)) pyc_reg_428_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_447_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_362), - .init(pyc_comb_18), - .q(pyc_reg_428) + .init(pyc_comb_14), + .q(pyc_reg_447) ); -PYC_REG #(.WIDTH(32)) pyc_reg_429_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_448_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_328), - .init(pyc_comb_18), - .q(pyc_reg_429) + .en(pyc_comb_17), + .d(pyc_comb_367), + .init(pyc_comb_14), + .q(pyc_reg_448) ); -PYC_REG #(.WIDTH(32)) pyc_reg_430_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_449_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_333), - .init(pyc_comb_18), - .q(pyc_reg_430) + .en(pyc_comb_17), + .d(pyc_comb_372), + .init(pyc_comb_14), + .q(pyc_reg_449) ); -PYC_REG #(.WIDTH(32)) pyc_reg_431_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_450_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_338), - .init(pyc_comb_18), - .q(pyc_reg_431) + .en(pyc_comb_17), + .d(pyc_comb_377), + .init(pyc_comb_14), + .q(pyc_reg_450) ); -PYC_REG #(.WIDTH(32)) pyc_reg_432_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_451_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_343), - .init(pyc_comb_18), - .q(pyc_reg_432) + .en(pyc_comb_17), + .d(pyc_comb_382), + .init(pyc_comb_14), + .q(pyc_reg_451) ); -PYC_REG #(.WIDTH(32)) pyc_reg_433_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_452_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_348), - .init(pyc_comb_18), - .q(pyc_reg_433) + .en(pyc_comb_17), + .d(pyc_comb_387), + .init(pyc_comb_14), + .q(pyc_reg_452) ); -PYC_REG #(.WIDTH(32)) pyc_reg_434_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_453_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_353), - .init(pyc_comb_18), - .q(pyc_reg_434) + .init(pyc_comb_13), + .q(pyc_reg_453) ); -PYC_REG #(.WIDTH(32)) pyc_reg_435_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_454_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_358), - .init(pyc_comb_18), - .q(pyc_reg_435) + .init(pyc_comb_13), + .q(pyc_reg_454) ); -PYC_REG #(.WIDTH(32)) pyc_reg_436_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_455_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_363), - .init(pyc_comb_18), - .q(pyc_reg_436) -); -PYC_REG #(.WIDTH(32)) pyc_reg_437_inst ( - .clk(clk), - .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_329), - .init(pyc_comb_18), - .q(pyc_reg_437) + .init(pyc_comb_13), + .q(pyc_reg_455) ); -PYC_REG #(.WIDTH(32)) pyc_reg_438_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_456_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_334), - .init(pyc_comb_18), - .q(pyc_reg_438) + .en(pyc_comb_17), + .d(pyc_comb_368), + .init(pyc_comb_13), + .q(pyc_reg_456) ); -PYC_REG #(.WIDTH(32)) pyc_reg_439_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_457_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_339), - .init(pyc_comb_18), - .q(pyc_reg_439) + .en(pyc_comb_17), + .d(pyc_comb_373), + .init(pyc_comb_13), + .q(pyc_reg_457) ); -PYC_REG #(.WIDTH(80)) pyc_reg_44_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_458_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_28), - .init(pyc_comb_20), - .q(pyc_reg_44) + .en(pyc_comb_17), + .d(pyc_comb_378), + .init(pyc_comb_13), + .q(pyc_reg_458) ); -PYC_REG #(.WIDTH(32)) pyc_reg_440_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_459_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_344), - .init(pyc_comb_18), - .q(pyc_reg_440) + .en(pyc_comb_17), + .d(pyc_comb_383), + .init(pyc_comb_13), + .q(pyc_reg_459) ); -PYC_REG #(.WIDTH(32)) pyc_reg_441_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_460_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_349), - .init(pyc_comb_18), - .q(pyc_reg_441) + .en(pyc_comb_17), + .d(pyc_comb_388), + .init(pyc_comb_13), + .q(pyc_reg_460) ); -PYC_REG #(.WIDTH(32)) pyc_reg_442_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_461_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_354), - .init(pyc_comb_18), - .q(pyc_reg_442) + .init(pyc_comb_14), + .q(pyc_reg_461) ); -PYC_REG #(.WIDTH(32)) pyc_reg_443_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_462_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_359), - .init(pyc_comb_18), - .q(pyc_reg_443) + .init(pyc_comb_14), + .q(pyc_reg_462) ); -PYC_REG #(.WIDTH(32)) pyc_reg_444_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_463_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_364), - .init(pyc_comb_18), - .q(pyc_reg_444) -); -PYC_REG #(.WIDTH(32)) pyc_reg_445_inst ( - .clk(clk), - .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_330), - .init(pyc_comb_18), - .q(pyc_reg_445) + .init(pyc_comb_14), + .q(pyc_reg_463) ); -PYC_REG #(.WIDTH(32)) pyc_reg_446_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_464_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_335), - .init(pyc_comb_18), - .q(pyc_reg_446) + .en(pyc_comb_17), + .d(pyc_comb_369), + .init(pyc_comb_14), + .q(pyc_reg_464) ); -PYC_REG #(.WIDTH(32)) pyc_reg_447_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_465_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_340), - .init(pyc_comb_18), - .q(pyc_reg_447) + .en(pyc_comb_17), + .d(pyc_comb_374), + .init(pyc_comb_14), + .q(pyc_reg_465) ); -PYC_REG #(.WIDTH(32)) pyc_reg_448_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_466_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_345), - .init(pyc_comb_18), - .q(pyc_reg_448) + .en(pyc_comb_17), + .d(pyc_comb_379), + .init(pyc_comb_14), + .q(pyc_reg_466) ); -PYC_REG #(.WIDTH(32)) pyc_reg_449_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_467_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_350), - .init(pyc_comb_18), - .q(pyc_reg_449) + .en(pyc_comb_17), + .d(pyc_comb_384), + .init(pyc_comb_14), + .q(pyc_reg_467) ); -PYC_REG #(.WIDTH(80)) pyc_reg_45_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_468_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_27), - .init(pyc_comb_20), - .q(pyc_reg_45) + .en(pyc_comb_17), + .d(pyc_comb_389), + .init(pyc_comb_14), + .q(pyc_reg_468) ); -PYC_REG #(.WIDTH(32)) pyc_reg_450_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_469_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_355), - .init(pyc_comb_18), - .q(pyc_reg_450) + .init(pyc_comb_13), + .q(pyc_reg_469) ); -PYC_REG #(.WIDTH(32)) pyc_reg_451_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_470_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_360), - .init(pyc_comb_18), - .q(pyc_reg_451) + .init(pyc_comb_13), + .q(pyc_reg_470) ); -PYC_REG #(.WIDTH(32)) pyc_reg_452_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_471_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pyc_comb_365), - .init(pyc_comb_18), - .q(pyc_reg_452) + .init(pyc_comb_13), + .q(pyc_reg_471) ); -PYC_REG #(.WIDTH(32)) pyc_reg_453_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_472_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_366), - .init(pyc_comb_18), - .q(pyc_reg_453) + .en(pyc_comb_17), + .d(pyc_comb_370), + .init(pyc_comb_13), + .q(pyc_reg_472) ); -PYC_REG #(.WIDTH(32)) pyc_reg_454_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_473_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_368), - .init(pyc_comb_18), - .q(pyc_reg_454) + .en(pyc_comb_17), + .d(pyc_comb_375), + .init(pyc_comb_13), + .q(pyc_reg_473) ); -PYC_REG #(.WIDTH(32)) pyc_reg_455_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_474_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_370), - .init(pyc_comb_18), - .q(pyc_reg_455) + .en(pyc_comb_17), + .d(pyc_comb_380), + .init(pyc_comb_13), + .q(pyc_reg_474) ); -PYC_REG #(.WIDTH(32)) pyc_reg_456_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_475_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_372), - .init(pyc_comb_18), - .q(pyc_reg_456) + .en(pyc_comb_17), + .d(pyc_comb_385), + .init(pyc_comb_13), + .q(pyc_reg_475) ); -PYC_REG #(.WIDTH(32)) pyc_reg_457_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_476_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_374), - .init(pyc_comb_18), - .q(pyc_reg_457) + .en(pyc_comb_17), + .d(pyc_comb_390), + .init(pyc_comb_13), + .q(pyc_reg_476) ); -PYC_REG #(.WIDTH(32)) pyc_reg_458_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_477_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_376), - .init(pyc_comb_18), - .q(pyc_reg_458) + .en(pyc_comb_17), + .d(pyc_comb_391), + .init(pyc_comb_14), + .q(pyc_reg_477) ); -PYC_REG #(.WIDTH(32)) pyc_reg_459_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_478_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_378), - .init(pyc_comb_18), - .q(pyc_reg_459) + .en(pyc_comb_17), + .d(pyc_comb_393), + .init(pyc_comb_14), + .q(pyc_reg_478) ); -PYC_REG #(.WIDTH(80)) pyc_reg_46_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_479_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_26), - .init(pyc_comb_20), - .q(pyc_reg_46) + .en(pyc_comb_17), + .d(pyc_comb_395), + .init(pyc_comb_14), + .q(pyc_reg_479) ); -PYC_REG #(.WIDTH(32)) pyc_reg_460_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_480_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_380), - .init(pyc_comb_18), - .q(pyc_reg_460) + .en(pyc_comb_17), + .d(pyc_comb_397), + .init(pyc_comb_14), + .q(pyc_reg_480) ); -PYC_REG #(.WIDTH(32)) pyc_reg_461_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_481_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_382), - .init(pyc_comb_18), - .q(pyc_reg_461) + .en(pyc_comb_17), + .d(pyc_comb_399), + .init(pyc_comb_14), + .q(pyc_reg_481) ); -PYC_REG #(.WIDTH(32)) pyc_reg_462_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_482_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_384), - .init(pyc_comb_18), - .q(pyc_reg_462) + .en(pyc_comb_17), + .d(pyc_comb_401), + .init(pyc_comb_14), + .q(pyc_reg_482) ); -PYC_REG #(.WIDTH(32)) pyc_reg_463_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_483_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_386), - .init(pyc_comb_18), - .q(pyc_reg_463) + .en(pyc_comb_17), + .d(pyc_comb_403), + .init(pyc_comb_14), + .q(pyc_reg_483) ); -PYC_REG #(.WIDTH(32)) pyc_reg_464_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_484_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_388), - .init(pyc_comb_18), - .q(pyc_reg_464) + .en(pyc_comb_17), + .d(pyc_comb_405), + .init(pyc_comb_14), + .q(pyc_reg_484) ); -PYC_REG #(.WIDTH(32)) pyc_reg_465_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_485_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_390), - .init(pyc_comb_18), - .q(pyc_reg_465) + .en(pyc_comb_17), + .d(pyc_comb_407), + .init(pyc_comb_14), + .q(pyc_reg_485) ); -PYC_REG #(.WIDTH(32)) pyc_reg_466_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_486_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_392), - .init(pyc_comb_18), - .q(pyc_reg_466) + .en(pyc_comb_17), + .d(pyc_comb_409), + .init(pyc_comb_14), + .q(pyc_reg_486) ); -PYC_REG #(.WIDTH(32)) pyc_reg_467_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_487_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_394), - .init(pyc_comb_18), - .q(pyc_reg_467) + .en(pyc_comb_17), + .d(pyc_comb_411), + .init(pyc_comb_14), + .q(pyc_reg_487) ); -PYC_REG #(.WIDTH(32)) pyc_reg_468_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_488_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_396), - .init(pyc_comb_18), - .q(pyc_reg_468) + .en(pyc_comb_17), + .d(pyc_comb_413), + .init(pyc_comb_14), + .q(pyc_reg_488) ); -PYC_REG #(.WIDTH(32)) pyc_reg_469_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_489_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_367), - .init(pyc_comb_18), - .q(pyc_reg_469) + .en(pyc_comb_17), + .d(pyc_comb_415), + .init(pyc_comb_14), + .q(pyc_reg_489) ); -PYC_REG #(.WIDTH(2)) pyc_reg_47_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_490_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_25), - .init(pyc_comb_19), - .q(pyc_reg_47) + .en(pyc_comb_17), + .d(pyc_comb_417), + .init(pyc_comb_14), + .q(pyc_reg_490) ); -PYC_REG #(.WIDTH(32)) pyc_reg_470_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_491_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_369), - .init(pyc_comb_18), - .q(pyc_reg_470) + .en(pyc_comb_17), + .d(pyc_comb_419), + .init(pyc_comb_14), + .q(pyc_reg_491) ); -PYC_REG #(.WIDTH(32)) pyc_reg_471_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_492_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_371), - .init(pyc_comb_18), - .q(pyc_reg_471) + .en(pyc_comb_17), + .d(pyc_comb_421), + .init(pyc_comb_14), + .q(pyc_reg_492) ); -PYC_REG #(.WIDTH(32)) pyc_reg_472_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_493_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_373), - .init(pyc_comb_18), - .q(pyc_reg_472) + .en(pyc_comb_17), + .d(pyc_comb_392), + .init(pyc_comb_13), + .q(pyc_reg_493) ); -PYC_REG #(.WIDTH(32)) pyc_reg_473_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_494_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_375), - .init(pyc_comb_18), - .q(pyc_reg_473) + .en(pyc_comb_17), + .d(pyc_comb_394), + .init(pyc_comb_13), + .q(pyc_reg_494) ); -PYC_REG #(.WIDTH(32)) pyc_reg_474_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_495_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_377), - .init(pyc_comb_18), - .q(pyc_reg_474) + .en(pyc_comb_17), + .d(pyc_comb_396), + .init(pyc_comb_13), + .q(pyc_reg_495) ); -PYC_REG #(.WIDTH(32)) pyc_reg_475_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_496_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_379), - .init(pyc_comb_18), - .q(pyc_reg_475) + .en(pyc_comb_17), + .d(pyc_comb_398), + .init(pyc_comb_13), + .q(pyc_reg_496) ); -PYC_REG #(.WIDTH(32)) pyc_reg_476_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_497_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_381), - .init(pyc_comb_18), - .q(pyc_reg_476) + .en(pyc_comb_17), + .d(pyc_comb_400), + .init(pyc_comb_13), + .q(pyc_reg_497) ); -PYC_REG #(.WIDTH(32)) pyc_reg_477_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_498_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_383), - .init(pyc_comb_18), - .q(pyc_reg_477) + .en(pyc_comb_17), + .d(pyc_comb_402), + .init(pyc_comb_13), + .q(pyc_reg_498) ); -PYC_REG #(.WIDTH(32)) pyc_reg_478_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_499_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_385), - .init(pyc_comb_18), - .q(pyc_reg_478) + .en(pyc_comb_17), + .d(pyc_comb_404), + .init(pyc_comb_13), + .q(pyc_reg_499) ); -PYC_REG #(.WIDTH(32)) pyc_reg_479_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_500_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_387), - .init(pyc_comb_18), - .q(pyc_reg_479) + .en(pyc_comb_17), + .d(pyc_comb_406), + .init(pyc_comb_13), + .q(pyc_reg_500) ); -PYC_REG #(.WIDTH(32)) pyc_reg_480_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_501_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_389), - .init(pyc_comb_18), - .q(pyc_reg_480) + .en(pyc_comb_17), + .d(pyc_comb_408), + .init(pyc_comb_13), + .q(pyc_reg_501) ); -PYC_REG #(.WIDTH(32)) pyc_reg_481_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_502_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_391), - .init(pyc_comb_18), - .q(pyc_reg_481) + .en(pyc_comb_17), + .d(pyc_comb_410), + .init(pyc_comb_13), + .q(pyc_reg_502) ); -PYC_REG #(.WIDTH(32)) pyc_reg_482_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_503_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_393), - .init(pyc_comb_18), - .q(pyc_reg_482) + .en(pyc_comb_17), + .d(pyc_comb_412), + .init(pyc_comb_13), + .q(pyc_reg_503) ); -PYC_REG #(.WIDTH(32)) pyc_reg_483_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_504_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_395), - .init(pyc_comb_18), - .q(pyc_reg_483) + .en(pyc_comb_17), + .d(pyc_comb_414), + .init(pyc_comb_13), + .q(pyc_reg_504) ); -PYC_REG #(.WIDTH(32)) pyc_reg_484_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_505_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_397), - .init(pyc_comb_18), - .q(pyc_reg_484) + .en(pyc_comb_17), + .d(pyc_comb_416), + .init(pyc_comb_13), + .q(pyc_reg_505) ); -PYC_REG #(.WIDTH(2)) pyc_reg_49_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_506_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_24), - .init(pyc_comb_19), - .q(pyc_reg_49) + .en(pyc_comb_17), + .d(pyc_comb_418), + .init(pyc_comb_13), + .q(pyc_reg_506) ); -PYC_REG #(.WIDTH(1)) pyc_reg_494_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_507_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_399), - .init(pyc_comb_22), - .q(pyc_reg_494) + .en(pyc_comb_17), + .d(pyc_comb_420), + .init(pyc_comb_13), + .q(pyc_reg_507) ); -PYC_REG #(.WIDTH(3)) pyc_reg_501_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_508_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_499), - .init(pyc_comb_500), - .q(pyc_reg_501) + .en(pyc_comb_17), + .d(pyc_comb_422), + .init(pyc_comb_13), + .q(pyc_reg_508) ); -PYC_REG #(.WIDTH(2)) pyc_reg_508_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_518_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_408), - .init(pyc_comb_19), - .q(pyc_reg_508) + .en(pyc_comb_17), + .d(pyc_comb_424), + .init(pyc_comb_18), + .q(pyc_reg_518) ); -PYC_REG #(.WIDTH(2)) pyc_reg_509_inst ( +PYC_REG #(.WIDTH(3)) pyc_reg_525_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_410), - .init(pyc_comb_19), - .q(pyc_reg_509) + .en(pyc_comb_17), + .d(pyc_comb_523), + .init(pyc_comb_524), + .q(pyc_reg_525) ); -PYC_REG #(.WIDTH(2)) pyc_reg_51_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_532_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_23), - .init(pyc_comb_19), - .q(pyc_reg_51) + .en(pyc_comb_17), + .d(pyc_comb_432), + .init(pyc_comb_15), + .q(pyc_reg_532) ); -PYC_REG #(.WIDTH(2)) pyc_reg_510_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_533_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_412), - .init(pyc_comb_19), - .q(pyc_reg_510) + .en(pyc_comb_17), + .d(pyc_comb_434), + .init(pyc_comb_15), + .q(pyc_reg_533) +); +PYC_REG #(.WIDTH(2)) pyc_reg_534_inst ( + .clk(clk), + .rst(rst), + .en(pyc_comb_17), + .d(pyc_comb_436), + .init(pyc_comb_15), + .q(pyc_reg_534) ); -PYC_REG #(.WIDTH(32)) pyc_reg_511_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_535_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_s2_s2a__next), - .init(pyc_comb_18), - .q(pyc_reg_511) + .init(pyc_comb_14), + .q(pyc_reg_535) ); -PYC_REG #(.WIDTH(32)) pyc_reg_514_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_536_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_s2_s2b0__next), - .init(pyc_comb_18), - .q(pyc_reg_514) + .init(pyc_comb_14), + .q(pyc_reg_536) ); -PYC_REG #(.WIDTH(32)) pyc_reg_515_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_537_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_s2_s2b1__next), - .init(pyc_comb_18), - .q(pyc_reg_515) + .init(pyc_comb_13), + .q(pyc_reg_537) ); -PYC_REG #(.WIDTH(32)) pyc_reg_516_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_538_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_s2_s2d0__next), - .init(pyc_comb_18), - .q(pyc_reg_516) + .init(pyc_comb_14), + .q(pyc_reg_538) ); -PYC_REG #(.WIDTH(32)) pyc_reg_517_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_539_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_s2_s2d1__next), - .init(pyc_comb_18), - .q(pyc_reg_517) + .init(pyc_comb_13), + .q(pyc_reg_539) ); -PYC_REG #(.WIDTH(32)) pyc_reg_518_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_540_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_s2_s2c0_lo__next), - .init(pyc_comb_18), - .q(pyc_reg_518) + .init(pyc_comb_14), + .q(pyc_reg_540) ); -PYC_REG #(.WIDTH(32)) pyc_reg_519_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_541_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_s2_s2c0_hi__next), - .init(pyc_comb_18), - .q(pyc_reg_519) + .init(pyc_comb_14), + .q(pyc_reg_541) ); -PYC_REG #(.WIDTH(32)) pyc_reg_520_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_542_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_s2_s2c1_lo__next), - .init(pyc_comb_18), - .q(pyc_reg_520) + .init(pyc_comb_13), + .q(pyc_reg_542) ); -PYC_REG #(.WIDTH(32)) pyc_reg_521_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_543_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_s2_s2c1_hi__next), - .init(pyc_comb_18), - .q(pyc_reg_521) + .init(pyc_comb_13), + .q(pyc_reg_543) ); -PYC_REG #(.WIDTH(32)) pyc_reg_569_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_593_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_513), - .init(pyc_comb_18), - .q(pyc_reg_569) -); -PYC_REG #(.WIDTH(32)) pyc_reg_571_inst ( - .clk(clk), - .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_570), - .init(pyc_comb_18), - .q(pyc_reg_571) -); -PYC_REG #(.WIDTH(16)) pyc_reg_579_inst ( - .clk(clk), - .rst(rst), - .en(pyc_comb_21), + .en(pyc_comb_17), .d(pe_int_out1__next), - .init(pyc_comb_16), - .q(pyc_reg_579) + .init(pyc_comb_13), + .q(pyc_reg_593) ); -PYC_REG #(.WIDTH(1)) pyc_reg_584_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_598_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_498), - .init(pyc_comb_22), - .q(pyc_reg_584) + .en(pyc_comb_17), + .d(pyc_comb_522), + .init(pyc_comb_18), + .q(pyc_reg_598) ); -PYC_REG #(.WIDTH(19)) pyc_reg_585_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_599_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_21), - .d(pyc_comb_577), - .init(pyc_comb_15), - .q(pyc_reg_585) + .en(pyc_comb_17), + .d(pyc_comb_591), + .init(pyc_comb_14), + .q(pyc_reg_599) ); assign vld_out = pe_int_out_vld; assign out0 = pe_int_out0; -assign out1 = pyc_comb_582; +assign out1 = pyc_comb_596; endmodule diff --git a/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree.v b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree.v deleted file mode 100644 index 7f8e2b3..0000000 --- a/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree.v +++ /dev/null @@ -1,3130 +0,0 @@ -// Generated by pycc (pyCircuit) -// Module: PE_INT_WALLACE_DOT8_TREE - -module PE_INT_WALLACE_DOT8_TREE ( - input clk, - input rst, - input [31:0] PE_INT_WALLACE_DOT8_TREE_in0, - input [31:0] PE_INT_WALLACE_DOT8_TREE_in1, - input [31:0] PE_INT_WALLACE_DOT8_TREE_in2, - input [31:0] PE_INT_WALLACE_DOT8_TREE_in3, - input [31:0] PE_INT_WALLACE_DOT8_TREE_in4, - input [31:0] PE_INT_WALLACE_DOT8_TREE_in5, - input [31:0] PE_INT_WALLACE_DOT8_TREE_in6, - input [31:0] PE_INT_WALLACE_DOT8_TREE_in7, - output [31:0] PE_INT_WALLACE_DOT8_TREE_sum -); - -wire [31:0] pyc_add_1552; // op=pyc.add -wire pyc_and_10; // op=pyc.and -wire pyc_and_100; // op=pyc.and -wire pyc_and_1003; // op=pyc.and -wire pyc_and_1004; // op=pyc.and -wire pyc_and_1006; // op=pyc.and -wire pyc_and_101; // op=pyc.and -wire pyc_and_1013; // op=pyc.and -wire pyc_and_1014; // op=pyc.and -wire pyc_and_1016; // op=pyc.and -wire pyc_and_1021; // op=pyc.and -wire pyc_and_1022; // op=pyc.and -wire pyc_and_1024; // op=pyc.and -wire pyc_and_103; // op=pyc.and -wire pyc_and_1031; // op=pyc.and -wire pyc_and_1032; // op=pyc.and -wire pyc_and_1034; // op=pyc.and -wire pyc_and_1039; // op=pyc.and -wire pyc_and_1040; // op=pyc.and -wire pyc_and_1042; // op=pyc.and -wire pyc_and_1049; // op=pyc.and -wire pyc_and_1050; // op=pyc.and -wire pyc_and_1052; // op=pyc.and -wire pyc_and_1057; // op=pyc.and -wire pyc_and_1058; // op=pyc.and -wire pyc_and_1060; // op=pyc.and -wire pyc_and_1067; // op=pyc.and -wire pyc_and_1068; // op=pyc.and -wire pyc_and_1070; // op=pyc.and -wire pyc_and_1075; // op=pyc.and -wire pyc_and_1076; // op=pyc.and -wire pyc_and_1078; // op=pyc.and -wire pyc_and_1085; // op=pyc.and -wire pyc_and_1086; // op=pyc.and -wire pyc_and_1088; // op=pyc.and -wire pyc_and_1093; // op=pyc.and -wire pyc_and_1094; // op=pyc.and -wire pyc_and_1096; // op=pyc.and -wire pyc_and_110; // op=pyc.and -wire pyc_and_1103; // op=pyc.and -wire pyc_and_1104; // op=pyc.and -wire pyc_and_1106; // op=pyc.and -wire pyc_and_111; // op=pyc.and -wire pyc_and_1111; // op=pyc.and -wire pyc_and_1112; // op=pyc.and -wire pyc_and_1114; // op=pyc.and -wire pyc_and_1125; // op=pyc.and -wire pyc_and_1128; // op=pyc.and -wire pyc_and_1129; // op=pyc.and -wire pyc_and_113; // op=pyc.and -wire pyc_and_1131; // op=pyc.and -wire pyc_and_1135; // op=pyc.and -wire pyc_and_1136; // op=pyc.and -wire pyc_and_1138; // op=pyc.and -wire pyc_and_1142; // op=pyc.and -wire pyc_and_1143; // op=pyc.and -wire pyc_and_1145; // op=pyc.and -wire pyc_and_1149; // op=pyc.and -wire pyc_and_1150; // op=pyc.and -wire pyc_and_1152; // op=pyc.and -wire pyc_and_1156; // op=pyc.and -wire pyc_and_1157; // op=pyc.and -wire pyc_and_1159; // op=pyc.and -wire pyc_and_1163; // op=pyc.and -wire pyc_and_1164; // op=pyc.and -wire pyc_and_1166; // op=pyc.and -wire pyc_and_1170; // op=pyc.and -wire pyc_and_1171; // op=pyc.and -wire pyc_and_1173; // op=pyc.and -wire pyc_and_1177; // op=pyc.and -wire pyc_and_1178; // op=pyc.and -wire pyc_and_118; // op=pyc.and -wire pyc_and_1180; // op=pyc.and -wire pyc_and_1184; // op=pyc.and -wire pyc_and_1185; // op=pyc.and -wire pyc_and_1187; // op=pyc.and -wire pyc_and_119; // op=pyc.and -wire pyc_and_1191; // op=pyc.and -wire pyc_and_1192; // op=pyc.and -wire pyc_and_1194; // op=pyc.and -wire pyc_and_1198; // op=pyc.and -wire pyc_and_1199; // op=pyc.and -wire pyc_and_1201; // op=pyc.and -wire pyc_and_1205; // op=pyc.and -wire pyc_and_1206; // op=pyc.and -wire pyc_and_1208; // op=pyc.and -wire pyc_and_121; // op=pyc.and -wire pyc_and_1212; // op=pyc.and -wire pyc_and_1213; // op=pyc.and -wire pyc_and_1215; // op=pyc.and -wire pyc_and_1219; // op=pyc.and -wire pyc_and_1220; // op=pyc.and -wire pyc_and_1222; // op=pyc.and -wire pyc_and_1226; // op=pyc.and -wire pyc_and_1227; // op=pyc.and -wire pyc_and_1229; // op=pyc.and -wire pyc_and_1233; // op=pyc.and -wire pyc_and_1234; // op=pyc.and -wire pyc_and_1236; // op=pyc.and -wire pyc_and_1240; // op=pyc.and -wire pyc_and_1241; // op=pyc.and -wire pyc_and_1243; // op=pyc.and -wire pyc_and_1247; // op=pyc.and -wire pyc_and_1248; // op=pyc.and -wire pyc_and_1250; // op=pyc.and -wire pyc_and_1254; // op=pyc.and -wire pyc_and_1255; // op=pyc.and -wire pyc_and_1257; // op=pyc.and -wire pyc_and_1261; // op=pyc.and -wire pyc_and_1262; // op=pyc.and -wire pyc_and_1264; // op=pyc.and -wire pyc_and_1268; // op=pyc.and -wire pyc_and_1269; // op=pyc.and -wire pyc_and_1271; // op=pyc.and -wire pyc_and_1275; // op=pyc.and -wire pyc_and_1276; // op=pyc.and -wire pyc_and_1278; // op=pyc.and -wire pyc_and_128; // op=pyc.and -wire pyc_and_1282; // op=pyc.and -wire pyc_and_1283; // op=pyc.and -wire pyc_and_1285; // op=pyc.and -wire pyc_and_1289; // op=pyc.and -wire pyc_and_129; // op=pyc.and -wire pyc_and_1290; // op=pyc.and -wire pyc_and_1292; // op=pyc.and -wire pyc_and_1296; // op=pyc.and -wire pyc_and_1297; // op=pyc.and -wire pyc_and_1299; // op=pyc.and -wire pyc_and_1303; // op=pyc.and -wire pyc_and_1304; // op=pyc.and -wire pyc_and_1306; // op=pyc.and -wire pyc_and_131; // op=pyc.and -wire pyc_and_1310; // op=pyc.and -wire pyc_and_1311; // op=pyc.and -wire pyc_and_1313; // op=pyc.and -wire pyc_and_1317; // op=pyc.and -wire pyc_and_1318; // op=pyc.and -wire pyc_and_1320; // op=pyc.and -wire pyc_and_1324; // op=pyc.and -wire pyc_and_1325; // op=pyc.and -wire pyc_and_1327; // op=pyc.and -wire pyc_and_1331; // op=pyc.and -wire pyc_and_1332; // op=pyc.and -wire pyc_and_1334; // op=pyc.and -wire pyc_and_1338; // op=pyc.and -wire pyc_and_1339; // op=pyc.and -wire pyc_and_1341; // op=pyc.and -wire pyc_and_1345; // op=pyc.and -wire pyc_and_1346; // op=pyc.and -wire pyc_and_1348; // op=pyc.and -wire pyc_and_1352; // op=pyc.and -wire pyc_and_1353; // op=pyc.and -wire pyc_and_1355; // op=pyc.and -wire pyc_and_1359; // op=pyc.and -wire pyc_and_136; // op=pyc.and -wire pyc_and_1360; // op=pyc.and -wire pyc_and_1362; // op=pyc.and -wire pyc_and_1366; // op=pyc.and -wire pyc_and_1367; // op=pyc.and -wire pyc_and_1369; // op=pyc.and -wire pyc_and_137; // op=pyc.and -wire pyc_and_1373; // op=pyc.and -wire pyc_and_1374; // op=pyc.and -wire pyc_and_1376; // op=pyc.and -wire pyc_and_1380; // op=pyc.and -wire pyc_and_1381; // op=pyc.and -wire pyc_and_1383; // op=pyc.and -wire pyc_and_1387; // op=pyc.and -wire pyc_and_1388; // op=pyc.and -wire pyc_and_139; // op=pyc.and -wire pyc_and_1390; // op=pyc.and -wire pyc_and_1394; // op=pyc.and -wire pyc_and_1395; // op=pyc.and -wire pyc_and_1397; // op=pyc.and -wire pyc_and_14; // op=pyc.and -wire pyc_and_1401; // op=pyc.and -wire pyc_and_1402; // op=pyc.and -wire pyc_and_1404; // op=pyc.and -wire pyc_and_1408; // op=pyc.and -wire pyc_and_1409; // op=pyc.and -wire pyc_and_1411; // op=pyc.and -wire pyc_and_1415; // op=pyc.and -wire pyc_and_1416; // op=pyc.and -wire pyc_and_1418; // op=pyc.and -wire pyc_and_1422; // op=pyc.and -wire pyc_and_1423; // op=pyc.and -wire pyc_and_1425; // op=pyc.and -wire pyc_and_1429; // op=pyc.and -wire pyc_and_1430; // op=pyc.and -wire pyc_and_1432; // op=pyc.and -wire pyc_and_1436; // op=pyc.and -wire pyc_and_1437; // op=pyc.and -wire pyc_and_1439; // op=pyc.and -wire pyc_and_1443; // op=pyc.and -wire pyc_and_1444; // op=pyc.and -wire pyc_and_1446; // op=pyc.and -wire pyc_and_1450; // op=pyc.and -wire pyc_and_1451; // op=pyc.and -wire pyc_and_1453; // op=pyc.and -wire pyc_and_1457; // op=pyc.and -wire pyc_and_1458; // op=pyc.and -wire pyc_and_146; // op=pyc.and -wire pyc_and_1460; // op=pyc.and -wire pyc_and_1464; // op=pyc.and -wire pyc_and_1465; // op=pyc.and -wire pyc_and_1467; // op=pyc.and -wire pyc_and_147; // op=pyc.and -wire pyc_and_1471; // op=pyc.and -wire pyc_and_1472; // op=pyc.and -wire pyc_and_1474; // op=pyc.and -wire pyc_and_1478; // op=pyc.and -wire pyc_and_1479; // op=pyc.and -wire pyc_and_1481; // op=pyc.and -wire pyc_and_1485; // op=pyc.and -wire pyc_and_1486; // op=pyc.and -wire pyc_and_1488; // op=pyc.and -wire pyc_and_149; // op=pyc.and -wire pyc_and_1492; // op=pyc.and -wire pyc_and_1493; // op=pyc.and -wire pyc_and_1495; // op=pyc.and -wire pyc_and_1499; // op=pyc.and -wire pyc_and_1500; // op=pyc.and -wire pyc_and_1502; // op=pyc.and -wire pyc_and_1506; // op=pyc.and -wire pyc_and_1507; // op=pyc.and -wire pyc_and_1509; // op=pyc.and -wire pyc_and_1513; // op=pyc.and -wire pyc_and_1514; // op=pyc.and -wire pyc_and_1516; // op=pyc.and -wire pyc_and_1520; // op=pyc.and -wire pyc_and_1521; // op=pyc.and -wire pyc_and_1523; // op=pyc.and -wire pyc_and_1527; // op=pyc.and -wire pyc_and_1528; // op=pyc.and -wire pyc_and_1530; // op=pyc.and -wire pyc_and_1534; // op=pyc.and -wire pyc_and_1535; // op=pyc.and -wire pyc_and_1537; // op=pyc.and -wire pyc_and_154; // op=pyc.and -wire pyc_and_1541; // op=pyc.and -wire pyc_and_1542; // op=pyc.and -wire pyc_and_1544; // op=pyc.and -wire pyc_and_155; // op=pyc.and -wire pyc_and_157; // op=pyc.and -wire pyc_and_164; // op=pyc.and -wire pyc_and_165; // op=pyc.and -wire pyc_and_167; // op=pyc.and -wire pyc_and_172; // op=pyc.and -wire pyc_and_173; // op=pyc.and -wire pyc_and_175; // op=pyc.and -wire pyc_and_182; // op=pyc.and -wire pyc_and_183; // op=pyc.and -wire pyc_and_185; // op=pyc.and -wire pyc_and_190; // op=pyc.and -wire pyc_and_191; // op=pyc.and -wire pyc_and_193; // op=pyc.and -wire pyc_and_20; // op=pyc.and -wire pyc_and_200; // op=pyc.and -wire pyc_and_201; // op=pyc.and -wire pyc_and_203; // op=pyc.and -wire pyc_and_208; // op=pyc.and -wire pyc_and_209; // op=pyc.and -wire pyc_and_21; // op=pyc.and -wire pyc_and_211; // op=pyc.and -wire pyc_and_218; // op=pyc.and -wire pyc_and_219; // op=pyc.and -wire pyc_and_221; // op=pyc.and -wire pyc_and_226; // op=pyc.and -wire pyc_and_227; // op=pyc.and -wire pyc_and_229; // op=pyc.and -wire pyc_and_23; // op=pyc.and -wire pyc_and_236; // op=pyc.and -wire pyc_and_237; // op=pyc.and -wire pyc_and_239; // op=pyc.and -wire pyc_and_244; // op=pyc.and -wire pyc_and_245; // op=pyc.and -wire pyc_and_247; // op=pyc.and -wire pyc_and_254; // op=pyc.and -wire pyc_and_255; // op=pyc.and -wire pyc_and_257; // op=pyc.and -wire pyc_and_262; // op=pyc.and -wire pyc_and_263; // op=pyc.and -wire pyc_and_265; // op=pyc.and -wire pyc_and_272; // op=pyc.and -wire pyc_and_273; // op=pyc.and -wire pyc_and_275; // op=pyc.and -wire pyc_and_28; // op=pyc.and -wire pyc_and_280; // op=pyc.and -wire pyc_and_281; // op=pyc.and -wire pyc_and_283; // op=pyc.and -wire pyc_and_29; // op=pyc.and -wire pyc_and_290; // op=pyc.and -wire pyc_and_291; // op=pyc.and -wire pyc_and_293; // op=pyc.and -wire pyc_and_298; // op=pyc.and -wire pyc_and_299; // op=pyc.and -wire pyc_and_301; // op=pyc.and -wire pyc_and_308; // op=pyc.and -wire pyc_and_309; // op=pyc.and -wire pyc_and_31; // op=pyc.and -wire pyc_and_311; // op=pyc.and -wire pyc_and_316; // op=pyc.and -wire pyc_and_317; // op=pyc.and -wire pyc_and_319; // op=pyc.and -wire pyc_and_326; // op=pyc.and -wire pyc_and_327; // op=pyc.and -wire pyc_and_329; // op=pyc.and -wire pyc_and_334; // op=pyc.and -wire pyc_and_335; // op=pyc.and -wire pyc_and_337; // op=pyc.and -wire pyc_and_344; // op=pyc.and -wire pyc_and_345; // op=pyc.and -wire pyc_and_347; // op=pyc.and -wire pyc_and_352; // op=pyc.and -wire pyc_and_353; // op=pyc.and -wire pyc_and_355; // op=pyc.and -wire pyc_and_362; // op=pyc.and -wire pyc_and_363; // op=pyc.and -wire pyc_and_365; // op=pyc.and -wire pyc_and_370; // op=pyc.and -wire pyc_and_371; // op=pyc.and -wire pyc_and_373; // op=pyc.and -wire pyc_and_38; // op=pyc.and -wire pyc_and_380; // op=pyc.and -wire pyc_and_381; // op=pyc.and -wire pyc_and_383; // op=pyc.and -wire pyc_and_388; // op=pyc.and -wire pyc_and_389; // op=pyc.and -wire pyc_and_39; // op=pyc.and -wire pyc_and_391; // op=pyc.and -wire pyc_and_398; // op=pyc.and -wire pyc_and_399; // op=pyc.and -wire pyc_and_401; // op=pyc.and -wire pyc_and_406; // op=pyc.and -wire pyc_and_407; // op=pyc.and -wire pyc_and_409; // op=pyc.and -wire pyc_and_41; // op=pyc.and -wire pyc_and_416; // op=pyc.and -wire pyc_and_417; // op=pyc.and -wire pyc_and_419; // op=pyc.and -wire pyc_and_424; // op=pyc.and -wire pyc_and_425; // op=pyc.and -wire pyc_and_427; // op=pyc.and -wire pyc_and_434; // op=pyc.and -wire pyc_and_435; // op=pyc.and -wire pyc_and_437; // op=pyc.and -wire pyc_and_442; // op=pyc.and -wire pyc_and_443; // op=pyc.and -wire pyc_and_445; // op=pyc.and -wire pyc_and_452; // op=pyc.and -wire pyc_and_453; // op=pyc.and -wire pyc_and_455; // op=pyc.and -wire pyc_and_46; // op=pyc.and -wire pyc_and_460; // op=pyc.and -wire pyc_and_461; // op=pyc.and -wire pyc_and_463; // op=pyc.and -wire pyc_and_47; // op=pyc.and -wire pyc_and_470; // op=pyc.and -wire pyc_and_471; // op=pyc.and -wire pyc_and_473; // op=pyc.and -wire pyc_and_478; // op=pyc.and -wire pyc_and_479; // op=pyc.and -wire pyc_and_481; // op=pyc.and -wire pyc_and_488; // op=pyc.and -wire pyc_and_489; // op=pyc.and -wire pyc_and_49; // op=pyc.and -wire pyc_and_491; // op=pyc.and -wire pyc_and_496; // op=pyc.and -wire pyc_and_497; // op=pyc.and -wire pyc_and_499; // op=pyc.and -wire pyc_and_506; // op=pyc.and -wire pyc_and_507; // op=pyc.and -wire pyc_and_509; // op=pyc.and -wire pyc_and_514; // op=pyc.and -wire pyc_and_515; // op=pyc.and -wire pyc_and_517; // op=pyc.and -wire pyc_and_524; // op=pyc.and -wire pyc_and_525; // op=pyc.and -wire pyc_and_527; // op=pyc.and -wire pyc_and_532; // op=pyc.and -wire pyc_and_533; // op=pyc.and -wire pyc_and_535; // op=pyc.and -wire pyc_and_542; // op=pyc.and -wire pyc_and_543; // op=pyc.and -wire pyc_and_545; // op=pyc.and -wire pyc_and_550; // op=pyc.and -wire pyc_and_551; // op=pyc.and -wire pyc_and_553; // op=pyc.and -wire pyc_and_56; // op=pyc.and -wire pyc_and_568; // op=pyc.and -wire pyc_and_569; // op=pyc.and -wire pyc_and_57; // op=pyc.and -wire pyc_and_571; // op=pyc.and -wire pyc_and_575; // op=pyc.and -wire pyc_and_581; // op=pyc.and -wire pyc_and_582; // op=pyc.and -wire pyc_and_584; // op=pyc.and -wire pyc_and_589; // op=pyc.and -wire pyc_and_59; // op=pyc.and -wire pyc_and_590; // op=pyc.and -wire pyc_and_592; // op=pyc.and -wire pyc_and_599; // op=pyc.and -wire pyc_and_600; // op=pyc.and -wire pyc_and_602; // op=pyc.and -wire pyc_and_607; // op=pyc.and -wire pyc_and_608; // op=pyc.and -wire pyc_and_610; // op=pyc.and -wire pyc_and_617; // op=pyc.and -wire pyc_and_618; // op=pyc.and -wire pyc_and_620; // op=pyc.and -wire pyc_and_625; // op=pyc.and -wire pyc_and_626; // op=pyc.and -wire pyc_and_628; // op=pyc.and -wire pyc_and_635; // op=pyc.and -wire pyc_and_636; // op=pyc.and -wire pyc_and_638; // op=pyc.and -wire pyc_and_64; // op=pyc.and -wire pyc_and_643; // op=pyc.and -wire pyc_and_644; // op=pyc.and -wire pyc_and_646; // op=pyc.and -wire pyc_and_65; // op=pyc.and -wire pyc_and_653; // op=pyc.and -wire pyc_and_654; // op=pyc.and -wire pyc_and_656; // op=pyc.and -wire pyc_and_661; // op=pyc.and -wire pyc_and_662; // op=pyc.and -wire pyc_and_664; // op=pyc.and -wire pyc_and_67; // op=pyc.and -wire pyc_and_671; // op=pyc.and -wire pyc_and_672; // op=pyc.and -wire pyc_and_674; // op=pyc.and -wire pyc_and_679; // op=pyc.and -wire pyc_and_680; // op=pyc.and -wire pyc_and_682; // op=pyc.and -wire pyc_and_689; // op=pyc.and -wire pyc_and_690; // op=pyc.and -wire pyc_and_692; // op=pyc.and -wire pyc_and_697; // op=pyc.and -wire pyc_and_698; // op=pyc.and -wire pyc_and_7; // op=pyc.and -wire pyc_and_700; // op=pyc.and -wire pyc_and_707; // op=pyc.and -wire pyc_and_708; // op=pyc.and -wire pyc_and_710; // op=pyc.and -wire pyc_and_715; // op=pyc.and -wire pyc_and_716; // op=pyc.and -wire pyc_and_718; // op=pyc.and -wire pyc_and_725; // op=pyc.and -wire pyc_and_726; // op=pyc.and -wire pyc_and_728; // op=pyc.and -wire pyc_and_733; // op=pyc.and -wire pyc_and_734; // op=pyc.and -wire pyc_and_736; // op=pyc.and -wire pyc_and_74; // op=pyc.and -wire pyc_and_743; // op=pyc.and -wire pyc_and_744; // op=pyc.and -wire pyc_and_746; // op=pyc.and -wire pyc_and_75; // op=pyc.and -wire pyc_and_751; // op=pyc.and -wire pyc_and_752; // op=pyc.and -wire pyc_and_754; // op=pyc.and -wire pyc_and_761; // op=pyc.and -wire pyc_and_762; // op=pyc.and -wire pyc_and_764; // op=pyc.and -wire pyc_and_769; // op=pyc.and -wire pyc_and_77; // op=pyc.and -wire pyc_and_770; // op=pyc.and -wire pyc_and_772; // op=pyc.and -wire pyc_and_779; // op=pyc.and -wire pyc_and_780; // op=pyc.and -wire pyc_and_782; // op=pyc.and -wire pyc_and_787; // op=pyc.and -wire pyc_and_788; // op=pyc.and -wire pyc_and_790; // op=pyc.and -wire pyc_and_797; // op=pyc.and -wire pyc_and_798; // op=pyc.and -wire pyc_and_8; // op=pyc.and -wire pyc_and_800; // op=pyc.and -wire pyc_and_805; // op=pyc.and -wire pyc_and_806; // op=pyc.and -wire pyc_and_808; // op=pyc.and -wire pyc_and_815; // op=pyc.and -wire pyc_and_816; // op=pyc.and -wire pyc_and_818; // op=pyc.and -wire pyc_and_82; // op=pyc.and -wire pyc_and_823; // op=pyc.and -wire pyc_and_824; // op=pyc.and -wire pyc_and_826; // op=pyc.and -wire pyc_and_83; // op=pyc.and -wire pyc_and_833; // op=pyc.and -wire pyc_and_834; // op=pyc.and -wire pyc_and_836; // op=pyc.and -wire pyc_and_841; // op=pyc.and -wire pyc_and_842; // op=pyc.and -wire pyc_and_844; // op=pyc.and -wire pyc_and_85; // op=pyc.and -wire pyc_and_851; // op=pyc.and -wire pyc_and_852; // op=pyc.and -wire pyc_and_854; // op=pyc.and -wire pyc_and_859; // op=pyc.and -wire pyc_and_860; // op=pyc.and -wire pyc_and_862; // op=pyc.and -wire pyc_and_869; // op=pyc.and -wire pyc_and_870; // op=pyc.and -wire pyc_and_872; // op=pyc.and -wire pyc_and_877; // op=pyc.and -wire pyc_and_878; // op=pyc.and -wire pyc_and_880; // op=pyc.and -wire pyc_and_887; // op=pyc.and -wire pyc_and_888; // op=pyc.and -wire pyc_and_890; // op=pyc.and -wire pyc_and_895; // op=pyc.and -wire pyc_and_896; // op=pyc.and -wire pyc_and_898; // op=pyc.and -wire pyc_and_905; // op=pyc.and -wire pyc_and_906; // op=pyc.and -wire pyc_and_908; // op=pyc.and -wire pyc_and_913; // op=pyc.and -wire pyc_and_914; // op=pyc.and -wire pyc_and_916; // op=pyc.and -wire pyc_and_92; // op=pyc.and -wire pyc_and_923; // op=pyc.and -wire pyc_and_924; // op=pyc.and -wire pyc_and_926; // op=pyc.and -wire pyc_and_93; // op=pyc.and -wire pyc_and_931; // op=pyc.and -wire pyc_and_932; // op=pyc.and -wire pyc_and_934; // op=pyc.and -wire pyc_and_941; // op=pyc.and -wire pyc_and_942; // op=pyc.and -wire pyc_and_944; // op=pyc.and -wire pyc_and_949; // op=pyc.and -wire pyc_and_95; // op=pyc.and -wire pyc_and_950; // op=pyc.and -wire pyc_and_952; // op=pyc.and -wire pyc_and_959; // op=pyc.and -wire pyc_and_960; // op=pyc.and -wire pyc_and_962; // op=pyc.and -wire pyc_and_967; // op=pyc.and -wire pyc_and_968; // op=pyc.and -wire pyc_and_970; // op=pyc.and -wire pyc_and_977; // op=pyc.and -wire pyc_and_978; // op=pyc.and -wire pyc_and_980; // op=pyc.and -wire pyc_and_985; // op=pyc.and -wire pyc_and_986; // op=pyc.and -wire pyc_and_988; // op=pyc.and -wire pyc_and_995; // op=pyc.and -wire pyc_and_996; // op=pyc.and -wire pyc_and_998; // op=pyc.and -wire [31:0] pyc_comb_1553; // op=pyc.comb -wire [31:0] pyc_concat_1550; // op=pyc.concat -wire [31:0] pyc_concat_1551; // op=pyc.concat -wire pyc_constant_1; // op=pyc.constant -wire pyc_extract_1000; // op=pyc.extract -wire pyc_extract_1008; // op=pyc.extract -wire pyc_extract_1009; // op=pyc.extract -wire pyc_extract_1010; // op=pyc.extract -wire pyc_extract_1018; // op=pyc.extract -wire pyc_extract_1026; // op=pyc.extract -wire pyc_extract_1027; // op=pyc.extract -wire pyc_extract_1028; // op=pyc.extract -wire pyc_extract_1036; // op=pyc.extract -wire pyc_extract_1044; // op=pyc.extract -wire pyc_extract_1045; // op=pyc.extract -wire pyc_extract_1046; // op=pyc.extract -wire pyc_extract_105; // op=pyc.extract -wire pyc_extract_1054; // op=pyc.extract -wire pyc_extract_106; // op=pyc.extract -wire pyc_extract_1062; // op=pyc.extract -wire pyc_extract_1063; // op=pyc.extract -wire pyc_extract_1064; // op=pyc.extract -wire pyc_extract_107; // op=pyc.extract -wire pyc_extract_1072; // op=pyc.extract -wire pyc_extract_1080; // op=pyc.extract -wire pyc_extract_1081; // op=pyc.extract -wire pyc_extract_1082; // op=pyc.extract -wire pyc_extract_1090; // op=pyc.extract -wire pyc_extract_1098; // op=pyc.extract -wire pyc_extract_1099; // op=pyc.extract -wire pyc_extract_1100; // op=pyc.extract -wire pyc_extract_1108; // op=pyc.extract -wire pyc_extract_1116; // op=pyc.extract -wire pyc_extract_1117; // op=pyc.extract -wire pyc_extract_1118; // op=pyc.extract -wire pyc_extract_1121; // op=pyc.extract -wire pyc_extract_115; // op=pyc.extract -wire pyc_extract_12; // op=pyc.extract -wire pyc_extract_123; // op=pyc.extract -wire pyc_extract_124; // op=pyc.extract -wire pyc_extract_125; // op=pyc.extract -wire pyc_extract_133; // op=pyc.extract -wire pyc_extract_141; // op=pyc.extract -wire pyc_extract_142; // op=pyc.extract -wire pyc_extract_143; // op=pyc.extract -wire pyc_extract_15; // op=pyc.extract -wire pyc_extract_151; // op=pyc.extract -wire pyc_extract_159; // op=pyc.extract -wire pyc_extract_16; // op=pyc.extract -wire pyc_extract_160; // op=pyc.extract -wire pyc_extract_161; // op=pyc.extract -wire pyc_extract_169; // op=pyc.extract -wire pyc_extract_17; // op=pyc.extract -wire pyc_extract_177; // op=pyc.extract -wire pyc_extract_178; // op=pyc.extract -wire pyc_extract_179; // op=pyc.extract -wire pyc_extract_187; // op=pyc.extract -wire pyc_extract_195; // op=pyc.extract -wire pyc_extract_196; // op=pyc.extract -wire pyc_extract_197; // op=pyc.extract -wire pyc_extract_2; // op=pyc.extract -wire pyc_extract_205; // op=pyc.extract -wire pyc_extract_213; // op=pyc.extract -wire pyc_extract_214; // op=pyc.extract -wire pyc_extract_215; // op=pyc.extract -wire pyc_extract_223; // op=pyc.extract -wire pyc_extract_231; // op=pyc.extract -wire pyc_extract_232; // op=pyc.extract -wire pyc_extract_233; // op=pyc.extract -wire pyc_extract_241; // op=pyc.extract -wire pyc_extract_249; // op=pyc.extract -wire pyc_extract_25; // op=pyc.extract -wire pyc_extract_250; // op=pyc.extract -wire pyc_extract_251; // op=pyc.extract -wire pyc_extract_259; // op=pyc.extract -wire pyc_extract_267; // op=pyc.extract -wire pyc_extract_268; // op=pyc.extract -wire pyc_extract_269; // op=pyc.extract -wire pyc_extract_277; // op=pyc.extract -wire pyc_extract_285; // op=pyc.extract -wire pyc_extract_286; // op=pyc.extract -wire pyc_extract_287; // op=pyc.extract -wire pyc_extract_295; // op=pyc.extract -wire pyc_extract_3; // op=pyc.extract -wire pyc_extract_303; // op=pyc.extract -wire pyc_extract_304; // op=pyc.extract -wire pyc_extract_305; // op=pyc.extract -wire pyc_extract_313; // op=pyc.extract -wire pyc_extract_321; // op=pyc.extract -wire pyc_extract_322; // op=pyc.extract -wire pyc_extract_323; // op=pyc.extract -wire pyc_extract_33; // op=pyc.extract -wire pyc_extract_331; // op=pyc.extract -wire pyc_extract_339; // op=pyc.extract -wire pyc_extract_34; // op=pyc.extract -wire pyc_extract_340; // op=pyc.extract -wire pyc_extract_341; // op=pyc.extract -wire pyc_extract_349; // op=pyc.extract -wire pyc_extract_35; // op=pyc.extract -wire pyc_extract_357; // op=pyc.extract -wire pyc_extract_358; // op=pyc.extract -wire pyc_extract_359; // op=pyc.extract -wire pyc_extract_367; // op=pyc.extract -wire pyc_extract_375; // op=pyc.extract -wire pyc_extract_376; // op=pyc.extract -wire pyc_extract_377; // op=pyc.extract -wire pyc_extract_385; // op=pyc.extract -wire pyc_extract_393; // op=pyc.extract -wire pyc_extract_394; // op=pyc.extract -wire pyc_extract_395; // op=pyc.extract -wire pyc_extract_4; // op=pyc.extract -wire pyc_extract_403; // op=pyc.extract -wire pyc_extract_411; // op=pyc.extract -wire pyc_extract_412; // op=pyc.extract -wire pyc_extract_413; // op=pyc.extract -wire pyc_extract_421; // op=pyc.extract -wire pyc_extract_429; // op=pyc.extract -wire pyc_extract_43; // op=pyc.extract -wire pyc_extract_430; // op=pyc.extract -wire pyc_extract_431; // op=pyc.extract -wire pyc_extract_439; // op=pyc.extract -wire pyc_extract_447; // op=pyc.extract -wire pyc_extract_448; // op=pyc.extract -wire pyc_extract_449; // op=pyc.extract -wire pyc_extract_457; // op=pyc.extract -wire pyc_extract_465; // op=pyc.extract -wire pyc_extract_466; // op=pyc.extract -wire pyc_extract_467; // op=pyc.extract -wire pyc_extract_475; // op=pyc.extract -wire pyc_extract_483; // op=pyc.extract -wire pyc_extract_484; // op=pyc.extract -wire pyc_extract_485; // op=pyc.extract -wire pyc_extract_493; // op=pyc.extract -wire pyc_extract_501; // op=pyc.extract -wire pyc_extract_502; // op=pyc.extract -wire pyc_extract_503; // op=pyc.extract -wire pyc_extract_51; // op=pyc.extract -wire pyc_extract_511; // op=pyc.extract -wire pyc_extract_519; // op=pyc.extract -wire pyc_extract_52; // op=pyc.extract -wire pyc_extract_520; // op=pyc.extract -wire pyc_extract_521; // op=pyc.extract -wire pyc_extract_529; // op=pyc.extract -wire pyc_extract_53; // op=pyc.extract -wire pyc_extract_537; // op=pyc.extract -wire pyc_extract_538; // op=pyc.extract -wire pyc_extract_539; // op=pyc.extract -wire pyc_extract_547; // op=pyc.extract -wire pyc_extract_555; // op=pyc.extract -wire pyc_extract_556; // op=pyc.extract -wire pyc_extract_557; // op=pyc.extract -wire pyc_extract_560; // op=pyc.extract -wire pyc_extract_563; // op=pyc.extract -wire pyc_extract_564; // op=pyc.extract -wire pyc_extract_565; // op=pyc.extract -wire pyc_extract_573; // op=pyc.extract -wire pyc_extract_576; // op=pyc.extract -wire pyc_extract_577; // op=pyc.extract -wire pyc_extract_578; // op=pyc.extract -wire pyc_extract_586; // op=pyc.extract -wire pyc_extract_594; // op=pyc.extract -wire pyc_extract_595; // op=pyc.extract -wire pyc_extract_596; // op=pyc.extract -wire pyc_extract_604; // op=pyc.extract -wire pyc_extract_61; // op=pyc.extract -wire pyc_extract_612; // op=pyc.extract -wire pyc_extract_613; // op=pyc.extract -wire pyc_extract_614; // op=pyc.extract -wire pyc_extract_622; // op=pyc.extract -wire pyc_extract_630; // op=pyc.extract -wire pyc_extract_631; // op=pyc.extract -wire pyc_extract_632; // op=pyc.extract -wire pyc_extract_640; // op=pyc.extract -wire pyc_extract_648; // op=pyc.extract -wire pyc_extract_649; // op=pyc.extract -wire pyc_extract_650; // op=pyc.extract -wire pyc_extract_658; // op=pyc.extract -wire pyc_extract_666; // op=pyc.extract -wire pyc_extract_667; // op=pyc.extract -wire pyc_extract_668; // op=pyc.extract -wire pyc_extract_676; // op=pyc.extract -wire pyc_extract_684; // op=pyc.extract -wire pyc_extract_685; // op=pyc.extract -wire pyc_extract_686; // op=pyc.extract -wire pyc_extract_69; // op=pyc.extract -wire pyc_extract_694; // op=pyc.extract -wire pyc_extract_70; // op=pyc.extract -wire pyc_extract_702; // op=pyc.extract -wire pyc_extract_703; // op=pyc.extract -wire pyc_extract_704; // op=pyc.extract -wire pyc_extract_71; // op=pyc.extract -wire pyc_extract_712; // op=pyc.extract -wire pyc_extract_720; // op=pyc.extract -wire pyc_extract_721; // op=pyc.extract -wire pyc_extract_722; // op=pyc.extract -wire pyc_extract_730; // op=pyc.extract -wire pyc_extract_738; // op=pyc.extract -wire pyc_extract_739; // op=pyc.extract -wire pyc_extract_740; // op=pyc.extract -wire pyc_extract_748; // op=pyc.extract -wire pyc_extract_756; // op=pyc.extract -wire pyc_extract_757; // op=pyc.extract -wire pyc_extract_758; // op=pyc.extract -wire pyc_extract_766; // op=pyc.extract -wire pyc_extract_774; // op=pyc.extract -wire pyc_extract_775; // op=pyc.extract -wire pyc_extract_776; // op=pyc.extract -wire pyc_extract_784; // op=pyc.extract -wire pyc_extract_79; // op=pyc.extract -wire pyc_extract_792; // op=pyc.extract -wire pyc_extract_793; // op=pyc.extract -wire pyc_extract_794; // op=pyc.extract -wire pyc_extract_802; // op=pyc.extract -wire pyc_extract_810; // op=pyc.extract -wire pyc_extract_811; // op=pyc.extract -wire pyc_extract_812; // op=pyc.extract -wire pyc_extract_820; // op=pyc.extract -wire pyc_extract_828; // op=pyc.extract -wire pyc_extract_829; // op=pyc.extract -wire pyc_extract_830; // op=pyc.extract -wire pyc_extract_838; // op=pyc.extract -wire pyc_extract_846; // op=pyc.extract -wire pyc_extract_847; // op=pyc.extract -wire pyc_extract_848; // op=pyc.extract -wire pyc_extract_856; // op=pyc.extract -wire pyc_extract_864; // op=pyc.extract -wire pyc_extract_865; // op=pyc.extract -wire pyc_extract_866; // op=pyc.extract -wire pyc_extract_87; // op=pyc.extract -wire pyc_extract_874; // op=pyc.extract -wire pyc_extract_88; // op=pyc.extract -wire pyc_extract_882; // op=pyc.extract -wire pyc_extract_883; // op=pyc.extract -wire pyc_extract_884; // op=pyc.extract -wire pyc_extract_89; // op=pyc.extract -wire pyc_extract_892; // op=pyc.extract -wire pyc_extract_900; // op=pyc.extract -wire pyc_extract_901; // op=pyc.extract -wire pyc_extract_902; // op=pyc.extract -wire pyc_extract_910; // op=pyc.extract -wire pyc_extract_918; // op=pyc.extract -wire pyc_extract_919; // op=pyc.extract -wire pyc_extract_920; // op=pyc.extract -wire pyc_extract_928; // op=pyc.extract -wire pyc_extract_936; // op=pyc.extract -wire pyc_extract_937; // op=pyc.extract -wire pyc_extract_938; // op=pyc.extract -wire pyc_extract_946; // op=pyc.extract -wire pyc_extract_954; // op=pyc.extract -wire pyc_extract_955; // op=pyc.extract -wire pyc_extract_956; // op=pyc.extract -wire pyc_extract_964; // op=pyc.extract -wire pyc_extract_97; // op=pyc.extract -wire pyc_extract_972; // op=pyc.extract -wire pyc_extract_973; // op=pyc.extract -wire pyc_extract_974; // op=pyc.extract -wire pyc_extract_982; // op=pyc.extract -wire pyc_extract_990; // op=pyc.extract -wire pyc_extract_991; // op=pyc.extract -wire pyc_extract_992; // op=pyc.extract -wire pyc_or_1005; // op=pyc.or -wire pyc_or_1007; // op=pyc.or -wire pyc_or_1015; // op=pyc.or -wire pyc_or_1017; // op=pyc.or -wire pyc_or_102; // op=pyc.or -wire pyc_or_1023; // op=pyc.or -wire pyc_or_1025; // op=pyc.or -wire pyc_or_1033; // op=pyc.or -wire pyc_or_1035; // op=pyc.or -wire pyc_or_104; // op=pyc.or -wire pyc_or_1041; // op=pyc.or -wire pyc_or_1043; // op=pyc.or -wire pyc_or_1051; // op=pyc.or -wire pyc_or_1053; // op=pyc.or -wire pyc_or_1059; // op=pyc.or -wire pyc_or_1061; // op=pyc.or -wire pyc_or_1069; // op=pyc.or -wire pyc_or_1071; // op=pyc.or -wire pyc_or_1077; // op=pyc.or -wire pyc_or_1079; // op=pyc.or -wire pyc_or_1087; // op=pyc.or -wire pyc_or_1089; // op=pyc.or -wire pyc_or_1095; // op=pyc.or -wire pyc_or_1097; // op=pyc.or -wire pyc_or_11; // op=pyc.or -wire pyc_or_1105; // op=pyc.or -wire pyc_or_1107; // op=pyc.or -wire pyc_or_1113; // op=pyc.or -wire pyc_or_1115; // op=pyc.or -wire pyc_or_112; // op=pyc.or -wire pyc_or_1130; // op=pyc.or -wire pyc_or_1132; // op=pyc.or -wire pyc_or_1137; // op=pyc.or -wire pyc_or_1139; // op=pyc.or -wire pyc_or_114; // op=pyc.or -wire pyc_or_1144; // op=pyc.or -wire pyc_or_1146; // op=pyc.or -wire pyc_or_1151; // op=pyc.or -wire pyc_or_1153; // op=pyc.or -wire pyc_or_1158; // op=pyc.or -wire pyc_or_1160; // op=pyc.or -wire pyc_or_1165; // op=pyc.or -wire pyc_or_1167; // op=pyc.or -wire pyc_or_1172; // op=pyc.or -wire pyc_or_1174; // op=pyc.or -wire pyc_or_1179; // op=pyc.or -wire pyc_or_1181; // op=pyc.or -wire pyc_or_1186; // op=pyc.or -wire pyc_or_1188; // op=pyc.or -wire pyc_or_1193; // op=pyc.or -wire pyc_or_1195; // op=pyc.or -wire pyc_or_120; // op=pyc.or -wire pyc_or_1200; // op=pyc.or -wire pyc_or_1202; // op=pyc.or -wire pyc_or_1207; // op=pyc.or -wire pyc_or_1209; // op=pyc.or -wire pyc_or_1214; // op=pyc.or -wire pyc_or_1216; // op=pyc.or -wire pyc_or_122; // op=pyc.or -wire pyc_or_1221; // op=pyc.or -wire pyc_or_1223; // op=pyc.or -wire pyc_or_1228; // op=pyc.or -wire pyc_or_1230; // op=pyc.or -wire pyc_or_1235; // op=pyc.or -wire pyc_or_1237; // op=pyc.or -wire pyc_or_1242; // op=pyc.or -wire pyc_or_1244; // op=pyc.or -wire pyc_or_1249; // op=pyc.or -wire pyc_or_1251; // op=pyc.or -wire pyc_or_1256; // op=pyc.or -wire pyc_or_1258; // op=pyc.or -wire pyc_or_1263; // op=pyc.or -wire pyc_or_1265; // op=pyc.or -wire pyc_or_1270; // op=pyc.or -wire pyc_or_1272; // op=pyc.or -wire pyc_or_1277; // op=pyc.or -wire pyc_or_1279; // op=pyc.or -wire pyc_or_1284; // op=pyc.or -wire pyc_or_1286; // op=pyc.or -wire pyc_or_1291; // op=pyc.or -wire pyc_or_1293; // op=pyc.or -wire pyc_or_1298; // op=pyc.or -wire pyc_or_130; // op=pyc.or -wire pyc_or_1300; // op=pyc.or -wire pyc_or_1305; // op=pyc.or -wire pyc_or_1307; // op=pyc.or -wire pyc_or_1312; // op=pyc.or -wire pyc_or_1314; // op=pyc.or -wire pyc_or_1319; // op=pyc.or -wire pyc_or_132; // op=pyc.or -wire pyc_or_1321; // op=pyc.or -wire pyc_or_1326; // op=pyc.or -wire pyc_or_1328; // op=pyc.or -wire pyc_or_1333; // op=pyc.or -wire pyc_or_1335; // op=pyc.or -wire pyc_or_1340; // op=pyc.or -wire pyc_or_1342; // op=pyc.or -wire pyc_or_1347; // op=pyc.or -wire pyc_or_1349; // op=pyc.or -wire pyc_or_1354; // op=pyc.or -wire pyc_or_1356; // op=pyc.or -wire pyc_or_1361; // op=pyc.or -wire pyc_or_1363; // op=pyc.or -wire pyc_or_1368; // op=pyc.or -wire pyc_or_1370; // op=pyc.or -wire pyc_or_1375; // op=pyc.or -wire pyc_or_1377; // op=pyc.or -wire pyc_or_138; // op=pyc.or -wire pyc_or_1382; // op=pyc.or -wire pyc_or_1384; // op=pyc.or -wire pyc_or_1389; // op=pyc.or -wire pyc_or_1391; // op=pyc.or -wire pyc_or_1396; // op=pyc.or -wire pyc_or_1398; // op=pyc.or -wire pyc_or_140; // op=pyc.or -wire pyc_or_1403; // op=pyc.or -wire pyc_or_1405; // op=pyc.or -wire pyc_or_1410; // op=pyc.or -wire pyc_or_1412; // op=pyc.or -wire pyc_or_1417; // op=pyc.or -wire pyc_or_1419; // op=pyc.or -wire pyc_or_1424; // op=pyc.or -wire pyc_or_1426; // op=pyc.or -wire pyc_or_1431; // op=pyc.or -wire pyc_or_1433; // op=pyc.or -wire pyc_or_1438; // op=pyc.or -wire pyc_or_1440; // op=pyc.or -wire pyc_or_1445; // op=pyc.or -wire pyc_or_1447; // op=pyc.or -wire pyc_or_1452; // op=pyc.or -wire pyc_or_1454; // op=pyc.or -wire pyc_or_1459; // op=pyc.or -wire pyc_or_1461; // op=pyc.or -wire pyc_or_1466; // op=pyc.or -wire pyc_or_1468; // op=pyc.or -wire pyc_or_1473; // op=pyc.or -wire pyc_or_1475; // op=pyc.or -wire pyc_or_148; // op=pyc.or -wire pyc_or_1480; // op=pyc.or -wire pyc_or_1482; // op=pyc.or -wire pyc_or_1487; // op=pyc.or -wire pyc_or_1489; // op=pyc.or -wire pyc_or_1494; // op=pyc.or -wire pyc_or_1496; // op=pyc.or -wire pyc_or_150; // op=pyc.or -wire pyc_or_1501; // op=pyc.or -wire pyc_or_1503; // op=pyc.or -wire pyc_or_1508; // op=pyc.or -wire pyc_or_1510; // op=pyc.or -wire pyc_or_1515; // op=pyc.or -wire pyc_or_1517; // op=pyc.or -wire pyc_or_1522; // op=pyc.or -wire pyc_or_1524; // op=pyc.or -wire pyc_or_1529; // op=pyc.or -wire pyc_or_1531; // op=pyc.or -wire pyc_or_1536; // op=pyc.or -wire pyc_or_1538; // op=pyc.or -wire pyc_or_1543; // op=pyc.or -wire pyc_or_1545; // op=pyc.or -wire pyc_or_156; // op=pyc.or -wire pyc_or_158; // op=pyc.or -wire pyc_or_166; // op=pyc.or -wire pyc_or_168; // op=pyc.or -wire pyc_or_174; // op=pyc.or -wire pyc_or_176; // op=pyc.or -wire pyc_or_184; // op=pyc.or -wire pyc_or_186; // op=pyc.or -wire pyc_or_192; // op=pyc.or -wire pyc_or_194; // op=pyc.or -wire pyc_or_202; // op=pyc.or -wire pyc_or_204; // op=pyc.or -wire pyc_or_210; // op=pyc.or -wire pyc_or_212; // op=pyc.or -wire pyc_or_22; // op=pyc.or -wire pyc_or_220; // op=pyc.or -wire pyc_or_222; // op=pyc.or -wire pyc_or_228; // op=pyc.or -wire pyc_or_230; // op=pyc.or -wire pyc_or_238; // op=pyc.or -wire pyc_or_24; // op=pyc.or -wire pyc_or_240; // op=pyc.or -wire pyc_or_246; // op=pyc.or -wire pyc_or_248; // op=pyc.or -wire pyc_or_256; // op=pyc.or -wire pyc_or_258; // op=pyc.or -wire pyc_or_264; // op=pyc.or -wire pyc_or_266; // op=pyc.or -wire pyc_or_274; // op=pyc.or -wire pyc_or_276; // op=pyc.or -wire pyc_or_282; // op=pyc.or -wire pyc_or_284; // op=pyc.or -wire pyc_or_292; // op=pyc.or -wire pyc_or_294; // op=pyc.or -wire pyc_or_30; // op=pyc.or -wire pyc_or_300; // op=pyc.or -wire pyc_or_302; // op=pyc.or -wire pyc_or_310; // op=pyc.or -wire pyc_or_312; // op=pyc.or -wire pyc_or_318; // op=pyc.or -wire pyc_or_32; // op=pyc.or -wire pyc_or_320; // op=pyc.or -wire pyc_or_328; // op=pyc.or -wire pyc_or_330; // op=pyc.or -wire pyc_or_336; // op=pyc.or -wire pyc_or_338; // op=pyc.or -wire pyc_or_346; // op=pyc.or -wire pyc_or_348; // op=pyc.or -wire pyc_or_354; // op=pyc.or -wire pyc_or_356; // op=pyc.or -wire pyc_or_364; // op=pyc.or -wire pyc_or_366; // op=pyc.or -wire pyc_or_372; // op=pyc.or -wire pyc_or_374; // op=pyc.or -wire pyc_or_382; // op=pyc.or -wire pyc_or_384; // op=pyc.or -wire pyc_or_390; // op=pyc.or -wire pyc_or_392; // op=pyc.or -wire pyc_or_40; // op=pyc.or -wire pyc_or_400; // op=pyc.or -wire pyc_or_402; // op=pyc.or -wire pyc_or_408; // op=pyc.or -wire pyc_or_410; // op=pyc.or -wire pyc_or_418; // op=pyc.or -wire pyc_or_42; // op=pyc.or -wire pyc_or_420; // op=pyc.or -wire pyc_or_426; // op=pyc.or -wire pyc_or_428; // op=pyc.or -wire pyc_or_436; // op=pyc.or -wire pyc_or_438; // op=pyc.or -wire pyc_or_444; // op=pyc.or -wire pyc_or_446; // op=pyc.or -wire pyc_or_454; // op=pyc.or -wire pyc_or_456; // op=pyc.or -wire pyc_or_462; // op=pyc.or -wire pyc_or_464; // op=pyc.or -wire pyc_or_472; // op=pyc.or -wire pyc_or_474; // op=pyc.or -wire pyc_or_48; // op=pyc.or -wire pyc_or_480; // op=pyc.or -wire pyc_or_482; // op=pyc.or -wire pyc_or_490; // op=pyc.or -wire pyc_or_492; // op=pyc.or -wire pyc_or_498; // op=pyc.or -wire pyc_or_50; // op=pyc.or -wire pyc_or_500; // op=pyc.or -wire pyc_or_508; // op=pyc.or -wire pyc_or_510; // op=pyc.or -wire pyc_or_516; // op=pyc.or -wire pyc_or_518; // op=pyc.or -wire pyc_or_526; // op=pyc.or -wire pyc_or_528; // op=pyc.or -wire pyc_or_534; // op=pyc.or -wire pyc_or_536; // op=pyc.or -wire pyc_or_544; // op=pyc.or -wire pyc_or_546; // op=pyc.or -wire pyc_or_552; // op=pyc.or -wire pyc_or_554; // op=pyc.or -wire pyc_or_570; // op=pyc.or -wire pyc_or_572; // op=pyc.or -wire pyc_or_58; // op=pyc.or -wire pyc_or_583; // op=pyc.or -wire pyc_or_585; // op=pyc.or -wire pyc_or_591; // op=pyc.or -wire pyc_or_593; // op=pyc.or -wire pyc_or_60; // op=pyc.or -wire pyc_or_601; // op=pyc.or -wire pyc_or_603; // op=pyc.or -wire pyc_or_609; // op=pyc.or -wire pyc_or_611; // op=pyc.or -wire pyc_or_619; // op=pyc.or -wire pyc_or_621; // op=pyc.or -wire pyc_or_627; // op=pyc.or -wire pyc_or_629; // op=pyc.or -wire pyc_or_637; // op=pyc.or -wire pyc_or_639; // op=pyc.or -wire pyc_or_645; // op=pyc.or -wire pyc_or_647; // op=pyc.or -wire pyc_or_655; // op=pyc.or -wire pyc_or_657; // op=pyc.or -wire pyc_or_66; // op=pyc.or -wire pyc_or_663; // op=pyc.or -wire pyc_or_665; // op=pyc.or -wire pyc_or_673; // op=pyc.or -wire pyc_or_675; // op=pyc.or -wire pyc_or_68; // op=pyc.or -wire pyc_or_681; // op=pyc.or -wire pyc_or_683; // op=pyc.or -wire pyc_or_691; // op=pyc.or -wire pyc_or_693; // op=pyc.or -wire pyc_or_699; // op=pyc.or -wire pyc_or_701; // op=pyc.or -wire pyc_or_709; // op=pyc.or -wire pyc_or_711; // op=pyc.or -wire pyc_or_717; // op=pyc.or -wire pyc_or_719; // op=pyc.or -wire pyc_or_727; // op=pyc.or -wire pyc_or_729; // op=pyc.or -wire pyc_or_735; // op=pyc.or -wire pyc_or_737; // op=pyc.or -wire pyc_or_745; // op=pyc.or -wire pyc_or_747; // op=pyc.or -wire pyc_or_753; // op=pyc.or -wire pyc_or_755; // op=pyc.or -wire pyc_or_76; // op=pyc.or -wire pyc_or_763; // op=pyc.or -wire pyc_or_765; // op=pyc.or -wire pyc_or_771; // op=pyc.or -wire pyc_or_773; // op=pyc.or -wire pyc_or_78; // op=pyc.or -wire pyc_or_781; // op=pyc.or -wire pyc_or_783; // op=pyc.or -wire pyc_or_789; // op=pyc.or -wire pyc_or_791; // op=pyc.or -wire pyc_or_799; // op=pyc.or -wire pyc_or_801; // op=pyc.or -wire pyc_or_807; // op=pyc.or -wire pyc_or_809; // op=pyc.or -wire pyc_or_817; // op=pyc.or -wire pyc_or_819; // op=pyc.or -wire pyc_or_825; // op=pyc.or -wire pyc_or_827; // op=pyc.or -wire pyc_or_835; // op=pyc.or -wire pyc_or_837; // op=pyc.or -wire pyc_or_84; // op=pyc.or -wire pyc_or_843; // op=pyc.or -wire pyc_or_845; // op=pyc.or -wire pyc_or_853; // op=pyc.or -wire pyc_or_855; // op=pyc.or -wire pyc_or_86; // op=pyc.or -wire pyc_or_861; // op=pyc.or -wire pyc_or_863; // op=pyc.or -wire pyc_or_871; // op=pyc.or -wire pyc_or_873; // op=pyc.or -wire pyc_or_879; // op=pyc.or -wire pyc_or_881; // op=pyc.or -wire pyc_or_889; // op=pyc.or -wire pyc_or_891; // op=pyc.or -wire pyc_or_897; // op=pyc.or -wire pyc_or_899; // op=pyc.or -wire pyc_or_9; // op=pyc.or -wire pyc_or_907; // op=pyc.or -wire pyc_or_909; // op=pyc.or -wire pyc_or_915; // op=pyc.or -wire pyc_or_917; // op=pyc.or -wire pyc_or_925; // op=pyc.or -wire pyc_or_927; // op=pyc.or -wire pyc_or_933; // op=pyc.or -wire pyc_or_935; // op=pyc.or -wire pyc_or_94; // op=pyc.or -wire pyc_or_943; // op=pyc.or -wire pyc_or_945; // op=pyc.or -wire pyc_or_951; // op=pyc.or -wire pyc_or_953; // op=pyc.or -wire pyc_or_96; // op=pyc.or -wire pyc_or_961; // op=pyc.or -wire pyc_or_963; // op=pyc.or -wire pyc_or_969; // op=pyc.or -wire pyc_or_971; // op=pyc.or -wire pyc_or_979; // op=pyc.or -wire pyc_or_981; // op=pyc.or -wire pyc_or_987; // op=pyc.or -wire pyc_or_989; // op=pyc.or -wire pyc_or_997; // op=pyc.or -wire pyc_or_999; // op=pyc.or -wire pyc_xor_1001; // op=pyc.xor -wire pyc_xor_1002; // op=pyc.xor -wire pyc_xor_1011; // op=pyc.xor -wire pyc_xor_1012; // op=pyc.xor -wire pyc_xor_1019; // op=pyc.xor -wire pyc_xor_1020; // op=pyc.xor -wire pyc_xor_1029; // op=pyc.xor -wire pyc_xor_1030; // op=pyc.xor -wire pyc_xor_1037; // op=pyc.xor -wire pyc_xor_1038; // op=pyc.xor -wire pyc_xor_1047; // op=pyc.xor -wire pyc_xor_1048; // op=pyc.xor -wire pyc_xor_1055; // op=pyc.xor -wire pyc_xor_1056; // op=pyc.xor -wire pyc_xor_1065; // op=pyc.xor -wire pyc_xor_1066; // op=pyc.xor -wire pyc_xor_1073; // op=pyc.xor -wire pyc_xor_1074; // op=pyc.xor -wire pyc_xor_108; // op=pyc.xor -wire pyc_xor_1083; // op=pyc.xor -wire pyc_xor_1084; // op=pyc.xor -wire pyc_xor_109; // op=pyc.xor -wire pyc_xor_1091; // op=pyc.xor -wire pyc_xor_1092; // op=pyc.xor -wire pyc_xor_1101; // op=pyc.xor -wire pyc_xor_1102; // op=pyc.xor -wire pyc_xor_1109; // op=pyc.xor -wire pyc_xor_1110; // op=pyc.xor -wire pyc_xor_1119; // op=pyc.xor -wire pyc_xor_1120; // op=pyc.xor -wire pyc_xor_1122; // op=pyc.xor -wire pyc_xor_1123; // op=pyc.xor -wire pyc_xor_1124; // op=pyc.xor -wire pyc_xor_1126; // op=pyc.xor -wire pyc_xor_1127; // op=pyc.xor -wire pyc_xor_1133; // op=pyc.xor -wire pyc_xor_1134; // op=pyc.xor -wire pyc_xor_1140; // op=pyc.xor -wire pyc_xor_1141; // op=pyc.xor -wire pyc_xor_1147; // op=pyc.xor -wire pyc_xor_1148; // op=pyc.xor -wire pyc_xor_1154; // op=pyc.xor -wire pyc_xor_1155; // op=pyc.xor -wire pyc_xor_116; // op=pyc.xor -wire pyc_xor_1161; // op=pyc.xor -wire pyc_xor_1162; // op=pyc.xor -wire pyc_xor_1168; // op=pyc.xor -wire pyc_xor_1169; // op=pyc.xor -wire pyc_xor_117; // op=pyc.xor -wire pyc_xor_1175; // op=pyc.xor -wire pyc_xor_1176; // op=pyc.xor -wire pyc_xor_1182; // op=pyc.xor -wire pyc_xor_1183; // op=pyc.xor -wire pyc_xor_1189; // op=pyc.xor -wire pyc_xor_1190; // op=pyc.xor -wire pyc_xor_1196; // op=pyc.xor -wire pyc_xor_1197; // op=pyc.xor -wire pyc_xor_1203; // op=pyc.xor -wire pyc_xor_1204; // op=pyc.xor -wire pyc_xor_1210; // op=pyc.xor -wire pyc_xor_1211; // op=pyc.xor -wire pyc_xor_1217; // op=pyc.xor -wire pyc_xor_1218; // op=pyc.xor -wire pyc_xor_1224; // op=pyc.xor -wire pyc_xor_1225; // op=pyc.xor -wire pyc_xor_1231; // op=pyc.xor -wire pyc_xor_1232; // op=pyc.xor -wire pyc_xor_1238; // op=pyc.xor -wire pyc_xor_1239; // op=pyc.xor -wire pyc_xor_1245; // op=pyc.xor -wire pyc_xor_1246; // op=pyc.xor -wire pyc_xor_1252; // op=pyc.xor -wire pyc_xor_1253; // op=pyc.xor -wire pyc_xor_1259; // op=pyc.xor -wire pyc_xor_126; // op=pyc.xor -wire pyc_xor_1260; // op=pyc.xor -wire pyc_xor_1266; // op=pyc.xor -wire pyc_xor_1267; // op=pyc.xor -wire pyc_xor_127; // op=pyc.xor -wire pyc_xor_1273; // op=pyc.xor -wire pyc_xor_1274; // op=pyc.xor -wire pyc_xor_1280; // op=pyc.xor -wire pyc_xor_1281; // op=pyc.xor -wire pyc_xor_1287; // op=pyc.xor -wire pyc_xor_1288; // op=pyc.xor -wire pyc_xor_1294; // op=pyc.xor -wire pyc_xor_1295; // op=pyc.xor -wire pyc_xor_13; // op=pyc.xor -wire pyc_xor_1301; // op=pyc.xor -wire pyc_xor_1302; // op=pyc.xor -wire pyc_xor_1308; // op=pyc.xor -wire pyc_xor_1309; // op=pyc.xor -wire pyc_xor_1315; // op=pyc.xor -wire pyc_xor_1316; // op=pyc.xor -wire pyc_xor_1322; // op=pyc.xor -wire pyc_xor_1323; // op=pyc.xor -wire pyc_xor_1329; // op=pyc.xor -wire pyc_xor_1330; // op=pyc.xor -wire pyc_xor_1336; // op=pyc.xor -wire pyc_xor_1337; // op=pyc.xor -wire pyc_xor_134; // op=pyc.xor -wire pyc_xor_1343; // op=pyc.xor -wire pyc_xor_1344; // op=pyc.xor -wire pyc_xor_135; // op=pyc.xor -wire pyc_xor_1350; // op=pyc.xor -wire pyc_xor_1351; // op=pyc.xor -wire pyc_xor_1357; // op=pyc.xor -wire pyc_xor_1358; // op=pyc.xor -wire pyc_xor_1364; // op=pyc.xor -wire pyc_xor_1365; // op=pyc.xor -wire pyc_xor_1371; // op=pyc.xor -wire pyc_xor_1372; // op=pyc.xor -wire pyc_xor_1378; // op=pyc.xor -wire pyc_xor_1379; // op=pyc.xor -wire pyc_xor_1385; // op=pyc.xor -wire pyc_xor_1386; // op=pyc.xor -wire pyc_xor_1392; // op=pyc.xor -wire pyc_xor_1393; // op=pyc.xor -wire pyc_xor_1399; // op=pyc.xor -wire pyc_xor_1400; // op=pyc.xor -wire pyc_xor_1406; // op=pyc.xor -wire pyc_xor_1407; // op=pyc.xor -wire pyc_xor_1413; // op=pyc.xor -wire pyc_xor_1414; // op=pyc.xor -wire pyc_xor_1420; // op=pyc.xor -wire pyc_xor_1421; // op=pyc.xor -wire pyc_xor_1427; // op=pyc.xor -wire pyc_xor_1428; // op=pyc.xor -wire pyc_xor_1434; // op=pyc.xor -wire pyc_xor_1435; // op=pyc.xor -wire pyc_xor_144; // op=pyc.xor -wire pyc_xor_1441; // op=pyc.xor -wire pyc_xor_1442; // op=pyc.xor -wire pyc_xor_1448; // op=pyc.xor -wire pyc_xor_1449; // op=pyc.xor -wire pyc_xor_145; // op=pyc.xor -wire pyc_xor_1455; // op=pyc.xor -wire pyc_xor_1456; // op=pyc.xor -wire pyc_xor_1462; // op=pyc.xor -wire pyc_xor_1463; // op=pyc.xor -wire pyc_xor_1469; // op=pyc.xor -wire pyc_xor_1470; // op=pyc.xor -wire pyc_xor_1476; // op=pyc.xor -wire pyc_xor_1477; // op=pyc.xor -wire pyc_xor_1483; // op=pyc.xor -wire pyc_xor_1484; // op=pyc.xor -wire pyc_xor_1490; // op=pyc.xor -wire pyc_xor_1491; // op=pyc.xor -wire pyc_xor_1497; // op=pyc.xor -wire pyc_xor_1498; // op=pyc.xor -wire pyc_xor_1504; // op=pyc.xor -wire pyc_xor_1505; // op=pyc.xor -wire pyc_xor_1511; // op=pyc.xor -wire pyc_xor_1512; // op=pyc.xor -wire pyc_xor_1518; // op=pyc.xor -wire pyc_xor_1519; // op=pyc.xor -wire pyc_xor_152; // op=pyc.xor -wire pyc_xor_1525; // op=pyc.xor -wire pyc_xor_1526; // op=pyc.xor -wire pyc_xor_153; // op=pyc.xor -wire pyc_xor_1532; // op=pyc.xor -wire pyc_xor_1533; // op=pyc.xor -wire pyc_xor_1539; // op=pyc.xor -wire pyc_xor_1540; // op=pyc.xor -wire pyc_xor_1546; // op=pyc.xor -wire pyc_xor_1547; // op=pyc.xor -wire pyc_xor_1548; // op=pyc.xor -wire pyc_xor_1549; // op=pyc.xor -wire pyc_xor_162; // op=pyc.xor -wire pyc_xor_163; // op=pyc.xor -wire pyc_xor_170; // op=pyc.xor -wire pyc_xor_171; // op=pyc.xor -wire pyc_xor_18; // op=pyc.xor -wire pyc_xor_180; // op=pyc.xor -wire pyc_xor_181; // op=pyc.xor -wire pyc_xor_188; // op=pyc.xor -wire pyc_xor_189; // op=pyc.xor -wire pyc_xor_19; // op=pyc.xor -wire pyc_xor_198; // op=pyc.xor -wire pyc_xor_199; // op=pyc.xor -wire pyc_xor_206; // op=pyc.xor -wire pyc_xor_207; // op=pyc.xor -wire pyc_xor_216; // op=pyc.xor -wire pyc_xor_217; // op=pyc.xor -wire pyc_xor_224; // op=pyc.xor -wire pyc_xor_225; // op=pyc.xor -wire pyc_xor_234; // op=pyc.xor -wire pyc_xor_235; // op=pyc.xor -wire pyc_xor_242; // op=pyc.xor -wire pyc_xor_243; // op=pyc.xor -wire pyc_xor_252; // op=pyc.xor -wire pyc_xor_253; // op=pyc.xor -wire pyc_xor_26; // op=pyc.xor -wire pyc_xor_260; // op=pyc.xor -wire pyc_xor_261; // op=pyc.xor -wire pyc_xor_27; // op=pyc.xor -wire pyc_xor_270; // op=pyc.xor -wire pyc_xor_271; // op=pyc.xor -wire pyc_xor_278; // op=pyc.xor -wire pyc_xor_279; // op=pyc.xor -wire pyc_xor_288; // op=pyc.xor -wire pyc_xor_289; // op=pyc.xor -wire pyc_xor_296; // op=pyc.xor -wire pyc_xor_297; // op=pyc.xor -wire pyc_xor_306; // op=pyc.xor -wire pyc_xor_307; // op=pyc.xor -wire pyc_xor_314; // op=pyc.xor -wire pyc_xor_315; // op=pyc.xor -wire pyc_xor_324; // op=pyc.xor -wire pyc_xor_325; // op=pyc.xor -wire pyc_xor_332; // op=pyc.xor -wire pyc_xor_333; // op=pyc.xor -wire pyc_xor_342; // op=pyc.xor -wire pyc_xor_343; // op=pyc.xor -wire pyc_xor_350; // op=pyc.xor -wire pyc_xor_351; // op=pyc.xor -wire pyc_xor_36; // op=pyc.xor -wire pyc_xor_360; // op=pyc.xor -wire pyc_xor_361; // op=pyc.xor -wire pyc_xor_368; // op=pyc.xor -wire pyc_xor_369; // op=pyc.xor -wire pyc_xor_37; // op=pyc.xor -wire pyc_xor_378; // op=pyc.xor -wire pyc_xor_379; // op=pyc.xor -wire pyc_xor_386; // op=pyc.xor -wire pyc_xor_387; // op=pyc.xor -wire pyc_xor_396; // op=pyc.xor -wire pyc_xor_397; // op=pyc.xor -wire pyc_xor_404; // op=pyc.xor -wire pyc_xor_405; // op=pyc.xor -wire pyc_xor_414; // op=pyc.xor -wire pyc_xor_415; // op=pyc.xor -wire pyc_xor_422; // op=pyc.xor -wire pyc_xor_423; // op=pyc.xor -wire pyc_xor_432; // op=pyc.xor -wire pyc_xor_433; // op=pyc.xor -wire pyc_xor_44; // op=pyc.xor -wire pyc_xor_440; // op=pyc.xor -wire pyc_xor_441; // op=pyc.xor -wire pyc_xor_45; // op=pyc.xor -wire pyc_xor_450; // op=pyc.xor -wire pyc_xor_451; // op=pyc.xor -wire pyc_xor_458; // op=pyc.xor -wire pyc_xor_459; // op=pyc.xor -wire pyc_xor_468; // op=pyc.xor -wire pyc_xor_469; // op=pyc.xor -wire pyc_xor_476; // op=pyc.xor -wire pyc_xor_477; // op=pyc.xor -wire pyc_xor_486; // op=pyc.xor -wire pyc_xor_487; // op=pyc.xor -wire pyc_xor_494; // op=pyc.xor -wire pyc_xor_495; // op=pyc.xor -wire pyc_xor_5; // op=pyc.xor -wire pyc_xor_504; // op=pyc.xor -wire pyc_xor_505; // op=pyc.xor -wire pyc_xor_512; // op=pyc.xor -wire pyc_xor_513; // op=pyc.xor -wire pyc_xor_522; // op=pyc.xor -wire pyc_xor_523; // op=pyc.xor -wire pyc_xor_530; // op=pyc.xor -wire pyc_xor_531; // op=pyc.xor -wire pyc_xor_54; // op=pyc.xor -wire pyc_xor_540; // op=pyc.xor -wire pyc_xor_541; // op=pyc.xor -wire pyc_xor_548; // op=pyc.xor -wire pyc_xor_549; // op=pyc.xor -wire pyc_xor_55; // op=pyc.xor -wire pyc_xor_558; // op=pyc.xor -wire pyc_xor_559; // op=pyc.xor -wire pyc_xor_561; // op=pyc.xor -wire pyc_xor_562; // op=pyc.xor -wire pyc_xor_566; // op=pyc.xor -wire pyc_xor_567; // op=pyc.xor -wire pyc_xor_574; // op=pyc.xor -wire pyc_xor_579; // op=pyc.xor -wire pyc_xor_580; // op=pyc.xor -wire pyc_xor_587; // op=pyc.xor -wire pyc_xor_588; // op=pyc.xor -wire pyc_xor_597; // op=pyc.xor -wire pyc_xor_598; // op=pyc.xor -wire pyc_xor_6; // op=pyc.xor -wire pyc_xor_605; // op=pyc.xor -wire pyc_xor_606; // op=pyc.xor -wire pyc_xor_615; // op=pyc.xor -wire pyc_xor_616; // op=pyc.xor -wire pyc_xor_62; // op=pyc.xor -wire pyc_xor_623; // op=pyc.xor -wire pyc_xor_624; // op=pyc.xor -wire pyc_xor_63; // op=pyc.xor -wire pyc_xor_633; // op=pyc.xor -wire pyc_xor_634; // op=pyc.xor -wire pyc_xor_641; // op=pyc.xor -wire pyc_xor_642; // op=pyc.xor -wire pyc_xor_651; // op=pyc.xor -wire pyc_xor_652; // op=pyc.xor -wire pyc_xor_659; // op=pyc.xor -wire pyc_xor_660; // op=pyc.xor -wire pyc_xor_669; // op=pyc.xor -wire pyc_xor_670; // op=pyc.xor -wire pyc_xor_677; // op=pyc.xor -wire pyc_xor_678; // op=pyc.xor -wire pyc_xor_687; // op=pyc.xor -wire pyc_xor_688; // op=pyc.xor -wire pyc_xor_695; // op=pyc.xor -wire pyc_xor_696; // op=pyc.xor -wire pyc_xor_705; // op=pyc.xor -wire pyc_xor_706; // op=pyc.xor -wire pyc_xor_713; // op=pyc.xor -wire pyc_xor_714; // op=pyc.xor -wire pyc_xor_72; // op=pyc.xor -wire pyc_xor_723; // op=pyc.xor -wire pyc_xor_724; // op=pyc.xor -wire pyc_xor_73; // op=pyc.xor -wire pyc_xor_731; // op=pyc.xor -wire pyc_xor_732; // op=pyc.xor -wire pyc_xor_741; // op=pyc.xor -wire pyc_xor_742; // op=pyc.xor -wire pyc_xor_749; // op=pyc.xor -wire pyc_xor_750; // op=pyc.xor -wire pyc_xor_759; // op=pyc.xor -wire pyc_xor_760; // op=pyc.xor -wire pyc_xor_767; // op=pyc.xor -wire pyc_xor_768; // op=pyc.xor -wire pyc_xor_777; // op=pyc.xor -wire pyc_xor_778; // op=pyc.xor -wire pyc_xor_785; // op=pyc.xor -wire pyc_xor_786; // op=pyc.xor -wire pyc_xor_795; // op=pyc.xor -wire pyc_xor_796; // op=pyc.xor -wire pyc_xor_80; // op=pyc.xor -wire pyc_xor_803; // op=pyc.xor -wire pyc_xor_804; // op=pyc.xor -wire pyc_xor_81; // op=pyc.xor -wire pyc_xor_813; // op=pyc.xor -wire pyc_xor_814; // op=pyc.xor -wire pyc_xor_821; // op=pyc.xor -wire pyc_xor_822; // op=pyc.xor -wire pyc_xor_831; // op=pyc.xor -wire pyc_xor_832; // op=pyc.xor -wire pyc_xor_839; // op=pyc.xor -wire pyc_xor_840; // op=pyc.xor -wire pyc_xor_849; // op=pyc.xor -wire pyc_xor_850; // op=pyc.xor -wire pyc_xor_857; // op=pyc.xor -wire pyc_xor_858; // op=pyc.xor -wire pyc_xor_867; // op=pyc.xor -wire pyc_xor_868; // op=pyc.xor -wire pyc_xor_875; // op=pyc.xor -wire pyc_xor_876; // op=pyc.xor -wire pyc_xor_885; // op=pyc.xor -wire pyc_xor_886; // op=pyc.xor -wire pyc_xor_893; // op=pyc.xor -wire pyc_xor_894; // op=pyc.xor -wire pyc_xor_90; // op=pyc.xor -wire pyc_xor_903; // op=pyc.xor -wire pyc_xor_904; // op=pyc.xor -wire pyc_xor_91; // op=pyc.xor -wire pyc_xor_911; // op=pyc.xor -wire pyc_xor_912; // op=pyc.xor -wire pyc_xor_921; // op=pyc.xor -wire pyc_xor_922; // op=pyc.xor -wire pyc_xor_929; // op=pyc.xor -wire pyc_xor_930; // op=pyc.xor -wire pyc_xor_939; // op=pyc.xor -wire pyc_xor_940; // op=pyc.xor -wire pyc_xor_947; // op=pyc.xor -wire pyc_xor_948; // op=pyc.xor -wire pyc_xor_957; // op=pyc.xor -wire pyc_xor_958; // op=pyc.xor -wire pyc_xor_965; // op=pyc.xor -wire pyc_xor_966; // op=pyc.xor -wire pyc_xor_975; // op=pyc.xor -wire pyc_xor_976; // op=pyc.xor -wire pyc_xor_98; // op=pyc.xor -wire pyc_xor_983; // op=pyc.xor -wire pyc_xor_984; // op=pyc.xor -wire pyc_xor_99; // op=pyc.xor -wire pyc_xor_993; // op=pyc.xor -wire pyc_xor_994; // op=pyc.xor - -// --- Combinational (netlist) -assign pyc_constant_1 = 1'd0; -assign pyc_extract_2 = PE_INT_WALLACE_DOT8_TREE_in0[0]; -assign pyc_extract_3 = PE_INT_WALLACE_DOT8_TREE_in1[0]; -assign pyc_extract_4 = PE_INT_WALLACE_DOT8_TREE_in2[0]; -assign pyc_xor_5 = (pyc_extract_2 ^ pyc_extract_3); -assign pyc_xor_6 = (pyc_xor_5 ^ pyc_extract_4); -assign pyc_and_7 = (pyc_extract_2 & pyc_extract_3); -assign pyc_and_8 = (pyc_extract_2 & pyc_extract_4); -assign pyc_or_9 = (pyc_and_7 | pyc_and_8); -assign pyc_and_10 = (pyc_extract_3 & pyc_extract_4); -assign pyc_or_11 = (pyc_or_9 | pyc_and_10); -assign pyc_extract_12 = PE_INT_WALLACE_DOT8_TREE_in3[0]; -assign pyc_xor_13 = (pyc_xor_6 ^ pyc_extract_12); -assign pyc_and_14 = (pyc_xor_6 & pyc_extract_12); -assign pyc_extract_15 = PE_INT_WALLACE_DOT8_TREE_in0[1]; -assign pyc_extract_16 = PE_INT_WALLACE_DOT8_TREE_in1[1]; -assign pyc_extract_17 = PE_INT_WALLACE_DOT8_TREE_in2[1]; -assign pyc_xor_18 = (pyc_extract_15 ^ pyc_extract_16); -assign pyc_xor_19 = (pyc_xor_18 ^ pyc_extract_17); -assign pyc_and_20 = (pyc_extract_15 & pyc_extract_16); -assign pyc_and_21 = (pyc_extract_15 & pyc_extract_17); -assign pyc_or_22 = (pyc_and_20 | pyc_and_21); -assign pyc_and_23 = (pyc_extract_16 & pyc_extract_17); -assign pyc_or_24 = (pyc_or_22 | pyc_and_23); -assign pyc_extract_25 = PE_INT_WALLACE_DOT8_TREE_in3[1]; -assign pyc_xor_26 = (pyc_xor_19 ^ pyc_extract_25); -assign pyc_xor_27 = (pyc_xor_26 ^ pyc_or_11); -assign pyc_and_28 = (pyc_xor_19 & pyc_extract_25); -assign pyc_and_29 = (pyc_xor_19 & pyc_or_11); -assign pyc_or_30 = (pyc_and_28 | pyc_and_29); -assign pyc_and_31 = (pyc_extract_25 & pyc_or_11); -assign pyc_or_32 = (pyc_or_30 | pyc_and_31); -assign pyc_extract_33 = PE_INT_WALLACE_DOT8_TREE_in0[2]; -assign pyc_extract_34 = PE_INT_WALLACE_DOT8_TREE_in1[2]; -assign pyc_extract_35 = PE_INT_WALLACE_DOT8_TREE_in2[2]; -assign pyc_xor_36 = (pyc_extract_33 ^ pyc_extract_34); -assign pyc_xor_37 = (pyc_xor_36 ^ pyc_extract_35); -assign pyc_and_38 = (pyc_extract_33 & pyc_extract_34); -assign pyc_and_39 = (pyc_extract_33 & pyc_extract_35); -assign pyc_or_40 = (pyc_and_38 | pyc_and_39); -assign pyc_and_41 = (pyc_extract_34 & pyc_extract_35); -assign pyc_or_42 = (pyc_or_40 | pyc_and_41); -assign pyc_extract_43 = PE_INT_WALLACE_DOT8_TREE_in3[2]; -assign pyc_xor_44 = (pyc_xor_37 ^ pyc_extract_43); -assign pyc_xor_45 = (pyc_xor_44 ^ pyc_or_24); -assign pyc_and_46 = (pyc_xor_37 & pyc_extract_43); -assign pyc_and_47 = (pyc_xor_37 & pyc_or_24); -assign pyc_or_48 = (pyc_and_46 | pyc_and_47); -assign pyc_and_49 = (pyc_extract_43 & pyc_or_24); -assign pyc_or_50 = (pyc_or_48 | pyc_and_49); -assign pyc_extract_51 = PE_INT_WALLACE_DOT8_TREE_in0[3]; -assign pyc_extract_52 = PE_INT_WALLACE_DOT8_TREE_in1[3]; -assign pyc_extract_53 = PE_INT_WALLACE_DOT8_TREE_in2[3]; -assign pyc_xor_54 = (pyc_extract_51 ^ pyc_extract_52); -assign pyc_xor_55 = (pyc_xor_54 ^ pyc_extract_53); -assign pyc_and_56 = (pyc_extract_51 & pyc_extract_52); -assign pyc_and_57 = (pyc_extract_51 & pyc_extract_53); -assign pyc_or_58 = (pyc_and_56 | pyc_and_57); -assign pyc_and_59 = (pyc_extract_52 & pyc_extract_53); -assign pyc_or_60 = (pyc_or_58 | pyc_and_59); -assign pyc_extract_61 = PE_INT_WALLACE_DOT8_TREE_in3[3]; -assign pyc_xor_62 = (pyc_xor_55 ^ pyc_extract_61); -assign pyc_xor_63 = (pyc_xor_62 ^ pyc_or_42); -assign pyc_and_64 = (pyc_xor_55 & pyc_extract_61); -assign pyc_and_65 = (pyc_xor_55 & pyc_or_42); -assign pyc_or_66 = (pyc_and_64 | pyc_and_65); -assign pyc_and_67 = (pyc_extract_61 & pyc_or_42); -assign pyc_or_68 = (pyc_or_66 | pyc_and_67); -assign pyc_extract_69 = PE_INT_WALLACE_DOT8_TREE_in0[4]; -assign pyc_extract_70 = PE_INT_WALLACE_DOT8_TREE_in1[4]; -assign pyc_extract_71 = PE_INT_WALLACE_DOT8_TREE_in2[4]; -assign pyc_xor_72 = (pyc_extract_69 ^ pyc_extract_70); -assign pyc_xor_73 = (pyc_xor_72 ^ pyc_extract_71); -assign pyc_and_74 = (pyc_extract_69 & pyc_extract_70); -assign pyc_and_75 = (pyc_extract_69 & pyc_extract_71); -assign pyc_or_76 = (pyc_and_74 | pyc_and_75); -assign pyc_and_77 = (pyc_extract_70 & pyc_extract_71); -assign pyc_or_78 = (pyc_or_76 | pyc_and_77); -assign pyc_extract_79 = PE_INT_WALLACE_DOT8_TREE_in3[4]; -assign pyc_xor_80 = (pyc_xor_73 ^ pyc_extract_79); -assign pyc_xor_81 = (pyc_xor_80 ^ pyc_or_60); -assign pyc_and_82 = (pyc_xor_73 & pyc_extract_79); -assign pyc_and_83 = (pyc_xor_73 & pyc_or_60); -assign pyc_or_84 = (pyc_and_82 | pyc_and_83); -assign pyc_and_85 = (pyc_extract_79 & pyc_or_60); -assign pyc_or_86 = (pyc_or_84 | pyc_and_85); -assign pyc_extract_87 = PE_INT_WALLACE_DOT8_TREE_in0[5]; -assign pyc_extract_88 = PE_INT_WALLACE_DOT8_TREE_in1[5]; -assign pyc_extract_89 = PE_INT_WALLACE_DOT8_TREE_in2[5]; -assign pyc_xor_90 = (pyc_extract_87 ^ pyc_extract_88); -assign pyc_xor_91 = (pyc_xor_90 ^ pyc_extract_89); -assign pyc_and_92 = (pyc_extract_87 & pyc_extract_88); -assign pyc_and_93 = (pyc_extract_87 & pyc_extract_89); -assign pyc_or_94 = (pyc_and_92 | pyc_and_93); -assign pyc_and_95 = (pyc_extract_88 & pyc_extract_89); -assign pyc_or_96 = (pyc_or_94 | pyc_and_95); -assign pyc_extract_97 = PE_INT_WALLACE_DOT8_TREE_in3[5]; -assign pyc_xor_98 = (pyc_xor_91 ^ pyc_extract_97); -assign pyc_xor_99 = (pyc_xor_98 ^ pyc_or_78); -assign pyc_and_100 = (pyc_xor_91 & pyc_extract_97); -assign pyc_and_101 = (pyc_xor_91 & pyc_or_78); -assign pyc_or_102 = (pyc_and_100 | pyc_and_101); -assign pyc_and_103 = (pyc_extract_97 & pyc_or_78); -assign pyc_or_104 = (pyc_or_102 | pyc_and_103); -assign pyc_extract_105 = PE_INT_WALLACE_DOT8_TREE_in0[6]; -assign pyc_extract_106 = PE_INT_WALLACE_DOT8_TREE_in1[6]; -assign pyc_extract_107 = PE_INT_WALLACE_DOT8_TREE_in2[6]; -assign pyc_xor_108 = (pyc_extract_105 ^ pyc_extract_106); -assign pyc_xor_109 = (pyc_xor_108 ^ pyc_extract_107); -assign pyc_and_110 = (pyc_extract_105 & pyc_extract_106); -assign pyc_and_111 = (pyc_extract_105 & pyc_extract_107); -assign pyc_or_112 = (pyc_and_110 | pyc_and_111); -assign pyc_and_113 = (pyc_extract_106 & pyc_extract_107); -assign pyc_or_114 = (pyc_or_112 | pyc_and_113); -assign pyc_extract_115 = PE_INT_WALLACE_DOT8_TREE_in3[6]; -assign pyc_xor_116 = (pyc_xor_109 ^ pyc_extract_115); -assign pyc_xor_117 = (pyc_xor_116 ^ pyc_or_96); -assign pyc_and_118 = (pyc_xor_109 & pyc_extract_115); -assign pyc_and_119 = (pyc_xor_109 & pyc_or_96); -assign pyc_or_120 = (pyc_and_118 | pyc_and_119); -assign pyc_and_121 = (pyc_extract_115 & pyc_or_96); -assign pyc_or_122 = (pyc_or_120 | pyc_and_121); -assign pyc_extract_123 = PE_INT_WALLACE_DOT8_TREE_in0[7]; -assign pyc_extract_124 = PE_INT_WALLACE_DOT8_TREE_in1[7]; -assign pyc_extract_125 = PE_INT_WALLACE_DOT8_TREE_in2[7]; -assign pyc_xor_126 = (pyc_extract_123 ^ pyc_extract_124); -assign pyc_xor_127 = (pyc_xor_126 ^ pyc_extract_125); -assign pyc_and_128 = (pyc_extract_123 & pyc_extract_124); -assign pyc_and_129 = (pyc_extract_123 & pyc_extract_125); -assign pyc_or_130 = (pyc_and_128 | pyc_and_129); -assign pyc_and_131 = (pyc_extract_124 & pyc_extract_125); -assign pyc_or_132 = (pyc_or_130 | pyc_and_131); -assign pyc_extract_133 = PE_INT_WALLACE_DOT8_TREE_in3[7]; -assign pyc_xor_134 = (pyc_xor_127 ^ pyc_extract_133); -assign pyc_xor_135 = (pyc_xor_134 ^ pyc_or_114); -assign pyc_and_136 = (pyc_xor_127 & pyc_extract_133); -assign pyc_and_137 = (pyc_xor_127 & pyc_or_114); -assign pyc_or_138 = (pyc_and_136 | pyc_and_137); -assign pyc_and_139 = (pyc_extract_133 & pyc_or_114); -assign pyc_or_140 = (pyc_or_138 | pyc_and_139); -assign pyc_extract_141 = PE_INT_WALLACE_DOT8_TREE_in0[8]; -assign pyc_extract_142 = PE_INT_WALLACE_DOT8_TREE_in1[8]; -assign pyc_extract_143 = PE_INT_WALLACE_DOT8_TREE_in2[8]; -assign pyc_xor_144 = (pyc_extract_141 ^ pyc_extract_142); -assign pyc_xor_145 = (pyc_xor_144 ^ pyc_extract_143); -assign pyc_and_146 = (pyc_extract_141 & pyc_extract_142); -assign pyc_and_147 = (pyc_extract_141 & pyc_extract_143); -assign pyc_or_148 = (pyc_and_146 | pyc_and_147); -assign pyc_and_149 = (pyc_extract_142 & pyc_extract_143); -assign pyc_or_150 = (pyc_or_148 | pyc_and_149); -assign pyc_extract_151 = PE_INT_WALLACE_DOT8_TREE_in3[8]; -assign pyc_xor_152 = (pyc_xor_145 ^ pyc_extract_151); -assign pyc_xor_153 = (pyc_xor_152 ^ pyc_or_132); -assign pyc_and_154 = (pyc_xor_145 & pyc_extract_151); -assign pyc_and_155 = (pyc_xor_145 & pyc_or_132); -assign pyc_or_156 = (pyc_and_154 | pyc_and_155); -assign pyc_and_157 = (pyc_extract_151 & pyc_or_132); -assign pyc_or_158 = (pyc_or_156 | pyc_and_157); -assign pyc_extract_159 = PE_INT_WALLACE_DOT8_TREE_in0[9]; -assign pyc_extract_160 = PE_INT_WALLACE_DOT8_TREE_in1[9]; -assign pyc_extract_161 = PE_INT_WALLACE_DOT8_TREE_in2[9]; -assign pyc_xor_162 = (pyc_extract_159 ^ pyc_extract_160); -assign pyc_xor_163 = (pyc_xor_162 ^ pyc_extract_161); -assign pyc_and_164 = (pyc_extract_159 & pyc_extract_160); -assign pyc_and_165 = (pyc_extract_159 & pyc_extract_161); -assign pyc_or_166 = (pyc_and_164 | pyc_and_165); -assign pyc_and_167 = (pyc_extract_160 & pyc_extract_161); -assign pyc_or_168 = (pyc_or_166 | pyc_and_167); -assign pyc_extract_169 = PE_INT_WALLACE_DOT8_TREE_in3[9]; -assign pyc_xor_170 = (pyc_xor_163 ^ pyc_extract_169); -assign pyc_xor_171 = (pyc_xor_170 ^ pyc_or_150); -assign pyc_and_172 = (pyc_xor_163 & pyc_extract_169); -assign pyc_and_173 = (pyc_xor_163 & pyc_or_150); -assign pyc_or_174 = (pyc_and_172 | pyc_and_173); -assign pyc_and_175 = (pyc_extract_169 & pyc_or_150); -assign pyc_or_176 = (pyc_or_174 | pyc_and_175); -assign pyc_extract_177 = PE_INT_WALLACE_DOT8_TREE_in0[10]; -assign pyc_extract_178 = PE_INT_WALLACE_DOT8_TREE_in1[10]; -assign pyc_extract_179 = PE_INT_WALLACE_DOT8_TREE_in2[10]; -assign pyc_xor_180 = (pyc_extract_177 ^ pyc_extract_178); -assign pyc_xor_181 = (pyc_xor_180 ^ pyc_extract_179); -assign pyc_and_182 = (pyc_extract_177 & pyc_extract_178); -assign pyc_and_183 = (pyc_extract_177 & pyc_extract_179); -assign pyc_or_184 = (pyc_and_182 | pyc_and_183); -assign pyc_and_185 = (pyc_extract_178 & pyc_extract_179); -assign pyc_or_186 = (pyc_or_184 | pyc_and_185); -assign pyc_extract_187 = PE_INT_WALLACE_DOT8_TREE_in3[10]; -assign pyc_xor_188 = (pyc_xor_181 ^ pyc_extract_187); -assign pyc_xor_189 = (pyc_xor_188 ^ pyc_or_168); -assign pyc_and_190 = (pyc_xor_181 & pyc_extract_187); -assign pyc_and_191 = (pyc_xor_181 & pyc_or_168); -assign pyc_or_192 = (pyc_and_190 | pyc_and_191); -assign pyc_and_193 = (pyc_extract_187 & pyc_or_168); -assign pyc_or_194 = (pyc_or_192 | pyc_and_193); -assign pyc_extract_195 = PE_INT_WALLACE_DOT8_TREE_in0[11]; -assign pyc_extract_196 = PE_INT_WALLACE_DOT8_TREE_in1[11]; -assign pyc_extract_197 = PE_INT_WALLACE_DOT8_TREE_in2[11]; -assign pyc_xor_198 = (pyc_extract_195 ^ pyc_extract_196); -assign pyc_xor_199 = (pyc_xor_198 ^ pyc_extract_197); -assign pyc_and_200 = (pyc_extract_195 & pyc_extract_196); -assign pyc_and_201 = (pyc_extract_195 & pyc_extract_197); -assign pyc_or_202 = (pyc_and_200 | pyc_and_201); -assign pyc_and_203 = (pyc_extract_196 & pyc_extract_197); -assign pyc_or_204 = (pyc_or_202 | pyc_and_203); -assign pyc_extract_205 = PE_INT_WALLACE_DOT8_TREE_in3[11]; -assign pyc_xor_206 = (pyc_xor_199 ^ pyc_extract_205); -assign pyc_xor_207 = (pyc_xor_206 ^ pyc_or_186); -assign pyc_and_208 = (pyc_xor_199 & pyc_extract_205); -assign pyc_and_209 = (pyc_xor_199 & pyc_or_186); -assign pyc_or_210 = (pyc_and_208 | pyc_and_209); -assign pyc_and_211 = (pyc_extract_205 & pyc_or_186); -assign pyc_or_212 = (pyc_or_210 | pyc_and_211); -assign pyc_extract_213 = PE_INT_WALLACE_DOT8_TREE_in0[12]; -assign pyc_extract_214 = PE_INT_WALLACE_DOT8_TREE_in1[12]; -assign pyc_extract_215 = PE_INT_WALLACE_DOT8_TREE_in2[12]; -assign pyc_xor_216 = (pyc_extract_213 ^ pyc_extract_214); -assign pyc_xor_217 = (pyc_xor_216 ^ pyc_extract_215); -assign pyc_and_218 = (pyc_extract_213 & pyc_extract_214); -assign pyc_and_219 = (pyc_extract_213 & pyc_extract_215); -assign pyc_or_220 = (pyc_and_218 | pyc_and_219); -assign pyc_and_221 = (pyc_extract_214 & pyc_extract_215); -assign pyc_or_222 = (pyc_or_220 | pyc_and_221); -assign pyc_extract_223 = PE_INT_WALLACE_DOT8_TREE_in3[12]; -assign pyc_xor_224 = (pyc_xor_217 ^ pyc_extract_223); -assign pyc_xor_225 = (pyc_xor_224 ^ pyc_or_204); -assign pyc_and_226 = (pyc_xor_217 & pyc_extract_223); -assign pyc_and_227 = (pyc_xor_217 & pyc_or_204); -assign pyc_or_228 = (pyc_and_226 | pyc_and_227); -assign pyc_and_229 = (pyc_extract_223 & pyc_or_204); -assign pyc_or_230 = (pyc_or_228 | pyc_and_229); -assign pyc_extract_231 = PE_INT_WALLACE_DOT8_TREE_in0[13]; -assign pyc_extract_232 = PE_INT_WALLACE_DOT8_TREE_in1[13]; -assign pyc_extract_233 = PE_INT_WALLACE_DOT8_TREE_in2[13]; -assign pyc_xor_234 = (pyc_extract_231 ^ pyc_extract_232); -assign pyc_xor_235 = (pyc_xor_234 ^ pyc_extract_233); -assign pyc_and_236 = (pyc_extract_231 & pyc_extract_232); -assign pyc_and_237 = (pyc_extract_231 & pyc_extract_233); -assign pyc_or_238 = (pyc_and_236 | pyc_and_237); -assign pyc_and_239 = (pyc_extract_232 & pyc_extract_233); -assign pyc_or_240 = (pyc_or_238 | pyc_and_239); -assign pyc_extract_241 = PE_INT_WALLACE_DOT8_TREE_in3[13]; -assign pyc_xor_242 = (pyc_xor_235 ^ pyc_extract_241); -assign pyc_xor_243 = (pyc_xor_242 ^ pyc_or_222); -assign pyc_and_244 = (pyc_xor_235 & pyc_extract_241); -assign pyc_and_245 = (pyc_xor_235 & pyc_or_222); -assign pyc_or_246 = (pyc_and_244 | pyc_and_245); -assign pyc_and_247 = (pyc_extract_241 & pyc_or_222); -assign pyc_or_248 = (pyc_or_246 | pyc_and_247); -assign pyc_extract_249 = PE_INT_WALLACE_DOT8_TREE_in0[14]; -assign pyc_extract_250 = PE_INT_WALLACE_DOT8_TREE_in1[14]; -assign pyc_extract_251 = PE_INT_WALLACE_DOT8_TREE_in2[14]; -assign pyc_xor_252 = (pyc_extract_249 ^ pyc_extract_250); -assign pyc_xor_253 = (pyc_xor_252 ^ pyc_extract_251); -assign pyc_and_254 = (pyc_extract_249 & pyc_extract_250); -assign pyc_and_255 = (pyc_extract_249 & pyc_extract_251); -assign pyc_or_256 = (pyc_and_254 | pyc_and_255); -assign pyc_and_257 = (pyc_extract_250 & pyc_extract_251); -assign pyc_or_258 = (pyc_or_256 | pyc_and_257); -assign pyc_extract_259 = PE_INT_WALLACE_DOT8_TREE_in3[14]; -assign pyc_xor_260 = (pyc_xor_253 ^ pyc_extract_259); -assign pyc_xor_261 = (pyc_xor_260 ^ pyc_or_240); -assign pyc_and_262 = (pyc_xor_253 & pyc_extract_259); -assign pyc_and_263 = (pyc_xor_253 & pyc_or_240); -assign pyc_or_264 = (pyc_and_262 | pyc_and_263); -assign pyc_and_265 = (pyc_extract_259 & pyc_or_240); -assign pyc_or_266 = (pyc_or_264 | pyc_and_265); -assign pyc_extract_267 = PE_INT_WALLACE_DOT8_TREE_in0[15]; -assign pyc_extract_268 = PE_INT_WALLACE_DOT8_TREE_in1[15]; -assign pyc_extract_269 = PE_INT_WALLACE_DOT8_TREE_in2[15]; -assign pyc_xor_270 = (pyc_extract_267 ^ pyc_extract_268); -assign pyc_xor_271 = (pyc_xor_270 ^ pyc_extract_269); -assign pyc_and_272 = (pyc_extract_267 & pyc_extract_268); -assign pyc_and_273 = (pyc_extract_267 & pyc_extract_269); -assign pyc_or_274 = (pyc_and_272 | pyc_and_273); -assign pyc_and_275 = (pyc_extract_268 & pyc_extract_269); -assign pyc_or_276 = (pyc_or_274 | pyc_and_275); -assign pyc_extract_277 = PE_INT_WALLACE_DOT8_TREE_in3[15]; -assign pyc_xor_278 = (pyc_xor_271 ^ pyc_extract_277); -assign pyc_xor_279 = (pyc_xor_278 ^ pyc_or_258); -assign pyc_and_280 = (pyc_xor_271 & pyc_extract_277); -assign pyc_and_281 = (pyc_xor_271 & pyc_or_258); -assign pyc_or_282 = (pyc_and_280 | pyc_and_281); -assign pyc_and_283 = (pyc_extract_277 & pyc_or_258); -assign pyc_or_284 = (pyc_or_282 | pyc_and_283); -assign pyc_extract_285 = PE_INT_WALLACE_DOT8_TREE_in0[16]; -assign pyc_extract_286 = PE_INT_WALLACE_DOT8_TREE_in1[16]; -assign pyc_extract_287 = PE_INT_WALLACE_DOT8_TREE_in2[16]; -assign pyc_xor_288 = (pyc_extract_285 ^ pyc_extract_286); -assign pyc_xor_289 = (pyc_xor_288 ^ pyc_extract_287); -assign pyc_and_290 = (pyc_extract_285 & pyc_extract_286); -assign pyc_and_291 = (pyc_extract_285 & pyc_extract_287); -assign pyc_or_292 = (pyc_and_290 | pyc_and_291); -assign pyc_and_293 = (pyc_extract_286 & pyc_extract_287); -assign pyc_or_294 = (pyc_or_292 | pyc_and_293); -assign pyc_extract_295 = PE_INT_WALLACE_DOT8_TREE_in3[16]; -assign pyc_xor_296 = (pyc_xor_289 ^ pyc_extract_295); -assign pyc_xor_297 = (pyc_xor_296 ^ pyc_or_276); -assign pyc_and_298 = (pyc_xor_289 & pyc_extract_295); -assign pyc_and_299 = (pyc_xor_289 & pyc_or_276); -assign pyc_or_300 = (pyc_and_298 | pyc_and_299); -assign pyc_and_301 = (pyc_extract_295 & pyc_or_276); -assign pyc_or_302 = (pyc_or_300 | pyc_and_301); -assign pyc_extract_303 = PE_INT_WALLACE_DOT8_TREE_in0[17]; -assign pyc_extract_304 = PE_INT_WALLACE_DOT8_TREE_in1[17]; -assign pyc_extract_305 = PE_INT_WALLACE_DOT8_TREE_in2[17]; -assign pyc_xor_306 = (pyc_extract_303 ^ pyc_extract_304); -assign pyc_xor_307 = (pyc_xor_306 ^ pyc_extract_305); -assign pyc_and_308 = (pyc_extract_303 & pyc_extract_304); -assign pyc_and_309 = (pyc_extract_303 & pyc_extract_305); -assign pyc_or_310 = (pyc_and_308 | pyc_and_309); -assign pyc_and_311 = (pyc_extract_304 & pyc_extract_305); -assign pyc_or_312 = (pyc_or_310 | pyc_and_311); -assign pyc_extract_313 = PE_INT_WALLACE_DOT8_TREE_in3[17]; -assign pyc_xor_314 = (pyc_xor_307 ^ pyc_extract_313); -assign pyc_xor_315 = (pyc_xor_314 ^ pyc_or_294); -assign pyc_and_316 = (pyc_xor_307 & pyc_extract_313); -assign pyc_and_317 = (pyc_xor_307 & pyc_or_294); -assign pyc_or_318 = (pyc_and_316 | pyc_and_317); -assign pyc_and_319 = (pyc_extract_313 & pyc_or_294); -assign pyc_or_320 = (pyc_or_318 | pyc_and_319); -assign pyc_extract_321 = PE_INT_WALLACE_DOT8_TREE_in0[18]; -assign pyc_extract_322 = PE_INT_WALLACE_DOT8_TREE_in1[18]; -assign pyc_extract_323 = PE_INT_WALLACE_DOT8_TREE_in2[18]; -assign pyc_xor_324 = (pyc_extract_321 ^ pyc_extract_322); -assign pyc_xor_325 = (pyc_xor_324 ^ pyc_extract_323); -assign pyc_and_326 = (pyc_extract_321 & pyc_extract_322); -assign pyc_and_327 = (pyc_extract_321 & pyc_extract_323); -assign pyc_or_328 = (pyc_and_326 | pyc_and_327); -assign pyc_and_329 = (pyc_extract_322 & pyc_extract_323); -assign pyc_or_330 = (pyc_or_328 | pyc_and_329); -assign pyc_extract_331 = PE_INT_WALLACE_DOT8_TREE_in3[18]; -assign pyc_xor_332 = (pyc_xor_325 ^ pyc_extract_331); -assign pyc_xor_333 = (pyc_xor_332 ^ pyc_or_312); -assign pyc_and_334 = (pyc_xor_325 & pyc_extract_331); -assign pyc_and_335 = (pyc_xor_325 & pyc_or_312); -assign pyc_or_336 = (pyc_and_334 | pyc_and_335); -assign pyc_and_337 = (pyc_extract_331 & pyc_or_312); -assign pyc_or_338 = (pyc_or_336 | pyc_and_337); -assign pyc_extract_339 = PE_INT_WALLACE_DOT8_TREE_in0[19]; -assign pyc_extract_340 = PE_INT_WALLACE_DOT8_TREE_in1[19]; -assign pyc_extract_341 = PE_INT_WALLACE_DOT8_TREE_in2[19]; -assign pyc_xor_342 = (pyc_extract_339 ^ pyc_extract_340); -assign pyc_xor_343 = (pyc_xor_342 ^ pyc_extract_341); -assign pyc_and_344 = (pyc_extract_339 & pyc_extract_340); -assign pyc_and_345 = (pyc_extract_339 & pyc_extract_341); -assign pyc_or_346 = (pyc_and_344 | pyc_and_345); -assign pyc_and_347 = (pyc_extract_340 & pyc_extract_341); -assign pyc_or_348 = (pyc_or_346 | pyc_and_347); -assign pyc_extract_349 = PE_INT_WALLACE_DOT8_TREE_in3[19]; -assign pyc_xor_350 = (pyc_xor_343 ^ pyc_extract_349); -assign pyc_xor_351 = (pyc_xor_350 ^ pyc_or_330); -assign pyc_and_352 = (pyc_xor_343 & pyc_extract_349); -assign pyc_and_353 = (pyc_xor_343 & pyc_or_330); -assign pyc_or_354 = (pyc_and_352 | pyc_and_353); -assign pyc_and_355 = (pyc_extract_349 & pyc_or_330); -assign pyc_or_356 = (pyc_or_354 | pyc_and_355); -assign pyc_extract_357 = PE_INT_WALLACE_DOT8_TREE_in0[20]; -assign pyc_extract_358 = PE_INT_WALLACE_DOT8_TREE_in1[20]; -assign pyc_extract_359 = PE_INT_WALLACE_DOT8_TREE_in2[20]; -assign pyc_xor_360 = (pyc_extract_357 ^ pyc_extract_358); -assign pyc_xor_361 = (pyc_xor_360 ^ pyc_extract_359); -assign pyc_and_362 = (pyc_extract_357 & pyc_extract_358); -assign pyc_and_363 = (pyc_extract_357 & pyc_extract_359); -assign pyc_or_364 = (pyc_and_362 | pyc_and_363); -assign pyc_and_365 = (pyc_extract_358 & pyc_extract_359); -assign pyc_or_366 = (pyc_or_364 | pyc_and_365); -assign pyc_extract_367 = PE_INT_WALLACE_DOT8_TREE_in3[20]; -assign pyc_xor_368 = (pyc_xor_361 ^ pyc_extract_367); -assign pyc_xor_369 = (pyc_xor_368 ^ pyc_or_348); -assign pyc_and_370 = (pyc_xor_361 & pyc_extract_367); -assign pyc_and_371 = (pyc_xor_361 & pyc_or_348); -assign pyc_or_372 = (pyc_and_370 | pyc_and_371); -assign pyc_and_373 = (pyc_extract_367 & pyc_or_348); -assign pyc_or_374 = (pyc_or_372 | pyc_and_373); -assign pyc_extract_375 = PE_INT_WALLACE_DOT8_TREE_in0[21]; -assign pyc_extract_376 = PE_INT_WALLACE_DOT8_TREE_in1[21]; -assign pyc_extract_377 = PE_INT_WALLACE_DOT8_TREE_in2[21]; -assign pyc_xor_378 = (pyc_extract_375 ^ pyc_extract_376); -assign pyc_xor_379 = (pyc_xor_378 ^ pyc_extract_377); -assign pyc_and_380 = (pyc_extract_375 & pyc_extract_376); -assign pyc_and_381 = (pyc_extract_375 & pyc_extract_377); -assign pyc_or_382 = (pyc_and_380 | pyc_and_381); -assign pyc_and_383 = (pyc_extract_376 & pyc_extract_377); -assign pyc_or_384 = (pyc_or_382 | pyc_and_383); -assign pyc_extract_385 = PE_INT_WALLACE_DOT8_TREE_in3[21]; -assign pyc_xor_386 = (pyc_xor_379 ^ pyc_extract_385); -assign pyc_xor_387 = (pyc_xor_386 ^ pyc_or_366); -assign pyc_and_388 = (pyc_xor_379 & pyc_extract_385); -assign pyc_and_389 = (pyc_xor_379 & pyc_or_366); -assign pyc_or_390 = (pyc_and_388 | pyc_and_389); -assign pyc_and_391 = (pyc_extract_385 & pyc_or_366); -assign pyc_or_392 = (pyc_or_390 | pyc_and_391); -assign pyc_extract_393 = PE_INT_WALLACE_DOT8_TREE_in0[22]; -assign pyc_extract_394 = PE_INT_WALLACE_DOT8_TREE_in1[22]; -assign pyc_extract_395 = PE_INT_WALLACE_DOT8_TREE_in2[22]; -assign pyc_xor_396 = (pyc_extract_393 ^ pyc_extract_394); -assign pyc_xor_397 = (pyc_xor_396 ^ pyc_extract_395); -assign pyc_and_398 = (pyc_extract_393 & pyc_extract_394); -assign pyc_and_399 = (pyc_extract_393 & pyc_extract_395); -assign pyc_or_400 = (pyc_and_398 | pyc_and_399); -assign pyc_and_401 = (pyc_extract_394 & pyc_extract_395); -assign pyc_or_402 = (pyc_or_400 | pyc_and_401); -assign pyc_extract_403 = PE_INT_WALLACE_DOT8_TREE_in3[22]; -assign pyc_xor_404 = (pyc_xor_397 ^ pyc_extract_403); -assign pyc_xor_405 = (pyc_xor_404 ^ pyc_or_384); -assign pyc_and_406 = (pyc_xor_397 & pyc_extract_403); -assign pyc_and_407 = (pyc_xor_397 & pyc_or_384); -assign pyc_or_408 = (pyc_and_406 | pyc_and_407); -assign pyc_and_409 = (pyc_extract_403 & pyc_or_384); -assign pyc_or_410 = (pyc_or_408 | pyc_and_409); -assign pyc_extract_411 = PE_INT_WALLACE_DOT8_TREE_in0[23]; -assign pyc_extract_412 = PE_INT_WALLACE_DOT8_TREE_in1[23]; -assign pyc_extract_413 = PE_INT_WALLACE_DOT8_TREE_in2[23]; -assign pyc_xor_414 = (pyc_extract_411 ^ pyc_extract_412); -assign pyc_xor_415 = (pyc_xor_414 ^ pyc_extract_413); -assign pyc_and_416 = (pyc_extract_411 & pyc_extract_412); -assign pyc_and_417 = (pyc_extract_411 & pyc_extract_413); -assign pyc_or_418 = (pyc_and_416 | pyc_and_417); -assign pyc_and_419 = (pyc_extract_412 & pyc_extract_413); -assign pyc_or_420 = (pyc_or_418 | pyc_and_419); -assign pyc_extract_421 = PE_INT_WALLACE_DOT8_TREE_in3[23]; -assign pyc_xor_422 = (pyc_xor_415 ^ pyc_extract_421); -assign pyc_xor_423 = (pyc_xor_422 ^ pyc_or_402); -assign pyc_and_424 = (pyc_xor_415 & pyc_extract_421); -assign pyc_and_425 = (pyc_xor_415 & pyc_or_402); -assign pyc_or_426 = (pyc_and_424 | pyc_and_425); -assign pyc_and_427 = (pyc_extract_421 & pyc_or_402); -assign pyc_or_428 = (pyc_or_426 | pyc_and_427); -assign pyc_extract_429 = PE_INT_WALLACE_DOT8_TREE_in0[24]; -assign pyc_extract_430 = PE_INT_WALLACE_DOT8_TREE_in1[24]; -assign pyc_extract_431 = PE_INT_WALLACE_DOT8_TREE_in2[24]; -assign pyc_xor_432 = (pyc_extract_429 ^ pyc_extract_430); -assign pyc_xor_433 = (pyc_xor_432 ^ pyc_extract_431); -assign pyc_and_434 = (pyc_extract_429 & pyc_extract_430); -assign pyc_and_435 = (pyc_extract_429 & pyc_extract_431); -assign pyc_or_436 = (pyc_and_434 | pyc_and_435); -assign pyc_and_437 = (pyc_extract_430 & pyc_extract_431); -assign pyc_or_438 = (pyc_or_436 | pyc_and_437); -assign pyc_extract_439 = PE_INT_WALLACE_DOT8_TREE_in3[24]; -assign pyc_xor_440 = (pyc_xor_433 ^ pyc_extract_439); -assign pyc_xor_441 = (pyc_xor_440 ^ pyc_or_420); -assign pyc_and_442 = (pyc_xor_433 & pyc_extract_439); -assign pyc_and_443 = (pyc_xor_433 & pyc_or_420); -assign pyc_or_444 = (pyc_and_442 | pyc_and_443); -assign pyc_and_445 = (pyc_extract_439 & pyc_or_420); -assign pyc_or_446 = (pyc_or_444 | pyc_and_445); -assign pyc_extract_447 = PE_INT_WALLACE_DOT8_TREE_in0[25]; -assign pyc_extract_448 = PE_INT_WALLACE_DOT8_TREE_in1[25]; -assign pyc_extract_449 = PE_INT_WALLACE_DOT8_TREE_in2[25]; -assign pyc_xor_450 = (pyc_extract_447 ^ pyc_extract_448); -assign pyc_xor_451 = (pyc_xor_450 ^ pyc_extract_449); -assign pyc_and_452 = (pyc_extract_447 & pyc_extract_448); -assign pyc_and_453 = (pyc_extract_447 & pyc_extract_449); -assign pyc_or_454 = (pyc_and_452 | pyc_and_453); -assign pyc_and_455 = (pyc_extract_448 & pyc_extract_449); -assign pyc_or_456 = (pyc_or_454 | pyc_and_455); -assign pyc_extract_457 = PE_INT_WALLACE_DOT8_TREE_in3[25]; -assign pyc_xor_458 = (pyc_xor_451 ^ pyc_extract_457); -assign pyc_xor_459 = (pyc_xor_458 ^ pyc_or_438); -assign pyc_and_460 = (pyc_xor_451 & pyc_extract_457); -assign pyc_and_461 = (pyc_xor_451 & pyc_or_438); -assign pyc_or_462 = (pyc_and_460 | pyc_and_461); -assign pyc_and_463 = (pyc_extract_457 & pyc_or_438); -assign pyc_or_464 = (pyc_or_462 | pyc_and_463); -assign pyc_extract_465 = PE_INT_WALLACE_DOT8_TREE_in0[26]; -assign pyc_extract_466 = PE_INT_WALLACE_DOT8_TREE_in1[26]; -assign pyc_extract_467 = PE_INT_WALLACE_DOT8_TREE_in2[26]; -assign pyc_xor_468 = (pyc_extract_465 ^ pyc_extract_466); -assign pyc_xor_469 = (pyc_xor_468 ^ pyc_extract_467); -assign pyc_and_470 = (pyc_extract_465 & pyc_extract_466); -assign pyc_and_471 = (pyc_extract_465 & pyc_extract_467); -assign pyc_or_472 = (pyc_and_470 | pyc_and_471); -assign pyc_and_473 = (pyc_extract_466 & pyc_extract_467); -assign pyc_or_474 = (pyc_or_472 | pyc_and_473); -assign pyc_extract_475 = PE_INT_WALLACE_DOT8_TREE_in3[26]; -assign pyc_xor_476 = (pyc_xor_469 ^ pyc_extract_475); -assign pyc_xor_477 = (pyc_xor_476 ^ pyc_or_456); -assign pyc_and_478 = (pyc_xor_469 & pyc_extract_475); -assign pyc_and_479 = (pyc_xor_469 & pyc_or_456); -assign pyc_or_480 = (pyc_and_478 | pyc_and_479); -assign pyc_and_481 = (pyc_extract_475 & pyc_or_456); -assign pyc_or_482 = (pyc_or_480 | pyc_and_481); -assign pyc_extract_483 = PE_INT_WALLACE_DOT8_TREE_in0[27]; -assign pyc_extract_484 = PE_INT_WALLACE_DOT8_TREE_in1[27]; -assign pyc_extract_485 = PE_INT_WALLACE_DOT8_TREE_in2[27]; -assign pyc_xor_486 = (pyc_extract_483 ^ pyc_extract_484); -assign pyc_xor_487 = (pyc_xor_486 ^ pyc_extract_485); -assign pyc_and_488 = (pyc_extract_483 & pyc_extract_484); -assign pyc_and_489 = (pyc_extract_483 & pyc_extract_485); -assign pyc_or_490 = (pyc_and_488 | pyc_and_489); -assign pyc_and_491 = (pyc_extract_484 & pyc_extract_485); -assign pyc_or_492 = (pyc_or_490 | pyc_and_491); -assign pyc_extract_493 = PE_INT_WALLACE_DOT8_TREE_in3[27]; -assign pyc_xor_494 = (pyc_xor_487 ^ pyc_extract_493); -assign pyc_xor_495 = (pyc_xor_494 ^ pyc_or_474); -assign pyc_and_496 = (pyc_xor_487 & pyc_extract_493); -assign pyc_and_497 = (pyc_xor_487 & pyc_or_474); -assign pyc_or_498 = (pyc_and_496 | pyc_and_497); -assign pyc_and_499 = (pyc_extract_493 & pyc_or_474); -assign pyc_or_500 = (pyc_or_498 | pyc_and_499); -assign pyc_extract_501 = PE_INT_WALLACE_DOT8_TREE_in0[28]; -assign pyc_extract_502 = PE_INT_WALLACE_DOT8_TREE_in1[28]; -assign pyc_extract_503 = PE_INT_WALLACE_DOT8_TREE_in2[28]; -assign pyc_xor_504 = (pyc_extract_501 ^ pyc_extract_502); -assign pyc_xor_505 = (pyc_xor_504 ^ pyc_extract_503); -assign pyc_and_506 = (pyc_extract_501 & pyc_extract_502); -assign pyc_and_507 = (pyc_extract_501 & pyc_extract_503); -assign pyc_or_508 = (pyc_and_506 | pyc_and_507); -assign pyc_and_509 = (pyc_extract_502 & pyc_extract_503); -assign pyc_or_510 = (pyc_or_508 | pyc_and_509); -assign pyc_extract_511 = PE_INT_WALLACE_DOT8_TREE_in3[28]; -assign pyc_xor_512 = (pyc_xor_505 ^ pyc_extract_511); -assign pyc_xor_513 = (pyc_xor_512 ^ pyc_or_492); -assign pyc_and_514 = (pyc_xor_505 & pyc_extract_511); -assign pyc_and_515 = (pyc_xor_505 & pyc_or_492); -assign pyc_or_516 = (pyc_and_514 | pyc_and_515); -assign pyc_and_517 = (pyc_extract_511 & pyc_or_492); -assign pyc_or_518 = (pyc_or_516 | pyc_and_517); -assign pyc_extract_519 = PE_INT_WALLACE_DOT8_TREE_in0[29]; -assign pyc_extract_520 = PE_INT_WALLACE_DOT8_TREE_in1[29]; -assign pyc_extract_521 = PE_INT_WALLACE_DOT8_TREE_in2[29]; -assign pyc_xor_522 = (pyc_extract_519 ^ pyc_extract_520); -assign pyc_xor_523 = (pyc_xor_522 ^ pyc_extract_521); -assign pyc_and_524 = (pyc_extract_519 & pyc_extract_520); -assign pyc_and_525 = (pyc_extract_519 & pyc_extract_521); -assign pyc_or_526 = (pyc_and_524 | pyc_and_525); -assign pyc_and_527 = (pyc_extract_520 & pyc_extract_521); -assign pyc_or_528 = (pyc_or_526 | pyc_and_527); -assign pyc_extract_529 = PE_INT_WALLACE_DOT8_TREE_in3[29]; -assign pyc_xor_530 = (pyc_xor_523 ^ pyc_extract_529); -assign pyc_xor_531 = (pyc_xor_530 ^ pyc_or_510); -assign pyc_and_532 = (pyc_xor_523 & pyc_extract_529); -assign pyc_and_533 = (pyc_xor_523 & pyc_or_510); -assign pyc_or_534 = (pyc_and_532 | pyc_and_533); -assign pyc_and_535 = (pyc_extract_529 & pyc_or_510); -assign pyc_or_536 = (pyc_or_534 | pyc_and_535); -assign pyc_extract_537 = PE_INT_WALLACE_DOT8_TREE_in0[30]; -assign pyc_extract_538 = PE_INT_WALLACE_DOT8_TREE_in1[30]; -assign pyc_extract_539 = PE_INT_WALLACE_DOT8_TREE_in2[30]; -assign pyc_xor_540 = (pyc_extract_537 ^ pyc_extract_538); -assign pyc_xor_541 = (pyc_xor_540 ^ pyc_extract_539); -assign pyc_and_542 = (pyc_extract_537 & pyc_extract_538); -assign pyc_and_543 = (pyc_extract_537 & pyc_extract_539); -assign pyc_or_544 = (pyc_and_542 | pyc_and_543); -assign pyc_and_545 = (pyc_extract_538 & pyc_extract_539); -assign pyc_or_546 = (pyc_or_544 | pyc_and_545); -assign pyc_extract_547 = PE_INT_WALLACE_DOT8_TREE_in3[30]; -assign pyc_xor_548 = (pyc_xor_541 ^ pyc_extract_547); -assign pyc_xor_549 = (pyc_xor_548 ^ pyc_or_528); -assign pyc_and_550 = (pyc_xor_541 & pyc_extract_547); -assign pyc_and_551 = (pyc_xor_541 & pyc_or_528); -assign pyc_or_552 = (pyc_and_550 | pyc_and_551); -assign pyc_and_553 = (pyc_extract_547 & pyc_or_528); -assign pyc_or_554 = (pyc_or_552 | pyc_and_553); -assign pyc_extract_555 = PE_INT_WALLACE_DOT8_TREE_in0[31]; -assign pyc_extract_556 = PE_INT_WALLACE_DOT8_TREE_in1[31]; -assign pyc_extract_557 = PE_INT_WALLACE_DOT8_TREE_in2[31]; -assign pyc_xor_558 = (pyc_extract_555 ^ pyc_extract_556); -assign pyc_xor_559 = (pyc_xor_558 ^ pyc_extract_557); -assign pyc_extract_560 = PE_INT_WALLACE_DOT8_TREE_in3[31]; -assign pyc_xor_561 = (pyc_xor_559 ^ pyc_extract_560); -assign pyc_xor_562 = (pyc_xor_561 ^ pyc_or_546); -assign pyc_extract_563 = PE_INT_WALLACE_DOT8_TREE_in4[0]; -assign pyc_extract_564 = PE_INT_WALLACE_DOT8_TREE_in5[0]; -assign pyc_extract_565 = PE_INT_WALLACE_DOT8_TREE_in6[0]; -assign pyc_xor_566 = (pyc_extract_563 ^ pyc_extract_564); -assign pyc_xor_567 = (pyc_xor_566 ^ pyc_extract_565); -assign pyc_and_568 = (pyc_extract_563 & pyc_extract_564); -assign pyc_and_569 = (pyc_extract_563 & pyc_extract_565); -assign pyc_or_570 = (pyc_and_568 | pyc_and_569); -assign pyc_and_571 = (pyc_extract_564 & pyc_extract_565); -assign pyc_or_572 = (pyc_or_570 | pyc_and_571); -assign pyc_extract_573 = PE_INT_WALLACE_DOT8_TREE_in7[0]; -assign pyc_xor_574 = (pyc_xor_567 ^ pyc_extract_573); -assign pyc_and_575 = (pyc_xor_567 & pyc_extract_573); -assign pyc_extract_576 = PE_INT_WALLACE_DOT8_TREE_in4[1]; -assign pyc_extract_577 = PE_INT_WALLACE_DOT8_TREE_in5[1]; -assign pyc_extract_578 = PE_INT_WALLACE_DOT8_TREE_in6[1]; -assign pyc_xor_579 = (pyc_extract_576 ^ pyc_extract_577); -assign pyc_xor_580 = (pyc_xor_579 ^ pyc_extract_578); -assign pyc_and_581 = (pyc_extract_576 & pyc_extract_577); -assign pyc_and_582 = (pyc_extract_576 & pyc_extract_578); -assign pyc_or_583 = (pyc_and_581 | pyc_and_582); -assign pyc_and_584 = (pyc_extract_577 & pyc_extract_578); -assign pyc_or_585 = (pyc_or_583 | pyc_and_584); -assign pyc_extract_586 = PE_INT_WALLACE_DOT8_TREE_in7[1]; -assign pyc_xor_587 = (pyc_xor_580 ^ pyc_extract_586); -assign pyc_xor_588 = (pyc_xor_587 ^ pyc_or_572); -assign pyc_and_589 = (pyc_xor_580 & pyc_extract_586); -assign pyc_and_590 = (pyc_xor_580 & pyc_or_572); -assign pyc_or_591 = (pyc_and_589 | pyc_and_590); -assign pyc_and_592 = (pyc_extract_586 & pyc_or_572); -assign pyc_or_593 = (pyc_or_591 | pyc_and_592); -assign pyc_extract_594 = PE_INT_WALLACE_DOT8_TREE_in4[2]; -assign pyc_extract_595 = PE_INT_WALLACE_DOT8_TREE_in5[2]; -assign pyc_extract_596 = PE_INT_WALLACE_DOT8_TREE_in6[2]; -assign pyc_xor_597 = (pyc_extract_594 ^ pyc_extract_595); -assign pyc_xor_598 = (pyc_xor_597 ^ pyc_extract_596); -assign pyc_and_599 = (pyc_extract_594 & pyc_extract_595); -assign pyc_and_600 = (pyc_extract_594 & pyc_extract_596); -assign pyc_or_601 = (pyc_and_599 | pyc_and_600); -assign pyc_and_602 = (pyc_extract_595 & pyc_extract_596); -assign pyc_or_603 = (pyc_or_601 | pyc_and_602); -assign pyc_extract_604 = PE_INT_WALLACE_DOT8_TREE_in7[2]; -assign pyc_xor_605 = (pyc_xor_598 ^ pyc_extract_604); -assign pyc_xor_606 = (pyc_xor_605 ^ pyc_or_585); -assign pyc_and_607 = (pyc_xor_598 & pyc_extract_604); -assign pyc_and_608 = (pyc_xor_598 & pyc_or_585); -assign pyc_or_609 = (pyc_and_607 | pyc_and_608); -assign pyc_and_610 = (pyc_extract_604 & pyc_or_585); -assign pyc_or_611 = (pyc_or_609 | pyc_and_610); -assign pyc_extract_612 = PE_INT_WALLACE_DOT8_TREE_in4[3]; -assign pyc_extract_613 = PE_INT_WALLACE_DOT8_TREE_in5[3]; -assign pyc_extract_614 = PE_INT_WALLACE_DOT8_TREE_in6[3]; -assign pyc_xor_615 = (pyc_extract_612 ^ pyc_extract_613); -assign pyc_xor_616 = (pyc_xor_615 ^ pyc_extract_614); -assign pyc_and_617 = (pyc_extract_612 & pyc_extract_613); -assign pyc_and_618 = (pyc_extract_612 & pyc_extract_614); -assign pyc_or_619 = (pyc_and_617 | pyc_and_618); -assign pyc_and_620 = (pyc_extract_613 & pyc_extract_614); -assign pyc_or_621 = (pyc_or_619 | pyc_and_620); -assign pyc_extract_622 = PE_INT_WALLACE_DOT8_TREE_in7[3]; -assign pyc_xor_623 = (pyc_xor_616 ^ pyc_extract_622); -assign pyc_xor_624 = (pyc_xor_623 ^ pyc_or_603); -assign pyc_and_625 = (pyc_xor_616 & pyc_extract_622); -assign pyc_and_626 = (pyc_xor_616 & pyc_or_603); -assign pyc_or_627 = (pyc_and_625 | pyc_and_626); -assign pyc_and_628 = (pyc_extract_622 & pyc_or_603); -assign pyc_or_629 = (pyc_or_627 | pyc_and_628); -assign pyc_extract_630 = PE_INT_WALLACE_DOT8_TREE_in4[4]; -assign pyc_extract_631 = PE_INT_WALLACE_DOT8_TREE_in5[4]; -assign pyc_extract_632 = PE_INT_WALLACE_DOT8_TREE_in6[4]; -assign pyc_xor_633 = (pyc_extract_630 ^ pyc_extract_631); -assign pyc_xor_634 = (pyc_xor_633 ^ pyc_extract_632); -assign pyc_and_635 = (pyc_extract_630 & pyc_extract_631); -assign pyc_and_636 = (pyc_extract_630 & pyc_extract_632); -assign pyc_or_637 = (pyc_and_635 | pyc_and_636); -assign pyc_and_638 = (pyc_extract_631 & pyc_extract_632); -assign pyc_or_639 = (pyc_or_637 | pyc_and_638); -assign pyc_extract_640 = PE_INT_WALLACE_DOT8_TREE_in7[4]; -assign pyc_xor_641 = (pyc_xor_634 ^ pyc_extract_640); -assign pyc_xor_642 = (pyc_xor_641 ^ pyc_or_621); -assign pyc_and_643 = (pyc_xor_634 & pyc_extract_640); -assign pyc_and_644 = (pyc_xor_634 & pyc_or_621); -assign pyc_or_645 = (pyc_and_643 | pyc_and_644); -assign pyc_and_646 = (pyc_extract_640 & pyc_or_621); -assign pyc_or_647 = (pyc_or_645 | pyc_and_646); -assign pyc_extract_648 = PE_INT_WALLACE_DOT8_TREE_in4[5]; -assign pyc_extract_649 = PE_INT_WALLACE_DOT8_TREE_in5[5]; -assign pyc_extract_650 = PE_INT_WALLACE_DOT8_TREE_in6[5]; -assign pyc_xor_651 = (pyc_extract_648 ^ pyc_extract_649); -assign pyc_xor_652 = (pyc_xor_651 ^ pyc_extract_650); -assign pyc_and_653 = (pyc_extract_648 & pyc_extract_649); -assign pyc_and_654 = (pyc_extract_648 & pyc_extract_650); -assign pyc_or_655 = (pyc_and_653 | pyc_and_654); -assign pyc_and_656 = (pyc_extract_649 & pyc_extract_650); -assign pyc_or_657 = (pyc_or_655 | pyc_and_656); -assign pyc_extract_658 = PE_INT_WALLACE_DOT8_TREE_in7[5]; -assign pyc_xor_659 = (pyc_xor_652 ^ pyc_extract_658); -assign pyc_xor_660 = (pyc_xor_659 ^ pyc_or_639); -assign pyc_and_661 = (pyc_xor_652 & pyc_extract_658); -assign pyc_and_662 = (pyc_xor_652 & pyc_or_639); -assign pyc_or_663 = (pyc_and_661 | pyc_and_662); -assign pyc_and_664 = (pyc_extract_658 & pyc_or_639); -assign pyc_or_665 = (pyc_or_663 | pyc_and_664); -assign pyc_extract_666 = PE_INT_WALLACE_DOT8_TREE_in4[6]; -assign pyc_extract_667 = PE_INT_WALLACE_DOT8_TREE_in5[6]; -assign pyc_extract_668 = PE_INT_WALLACE_DOT8_TREE_in6[6]; -assign pyc_xor_669 = (pyc_extract_666 ^ pyc_extract_667); -assign pyc_xor_670 = (pyc_xor_669 ^ pyc_extract_668); -assign pyc_and_671 = (pyc_extract_666 & pyc_extract_667); -assign pyc_and_672 = (pyc_extract_666 & pyc_extract_668); -assign pyc_or_673 = (pyc_and_671 | pyc_and_672); -assign pyc_and_674 = (pyc_extract_667 & pyc_extract_668); -assign pyc_or_675 = (pyc_or_673 | pyc_and_674); -assign pyc_extract_676 = PE_INT_WALLACE_DOT8_TREE_in7[6]; -assign pyc_xor_677 = (pyc_xor_670 ^ pyc_extract_676); -assign pyc_xor_678 = (pyc_xor_677 ^ pyc_or_657); -assign pyc_and_679 = (pyc_xor_670 & pyc_extract_676); -assign pyc_and_680 = (pyc_xor_670 & pyc_or_657); -assign pyc_or_681 = (pyc_and_679 | pyc_and_680); -assign pyc_and_682 = (pyc_extract_676 & pyc_or_657); -assign pyc_or_683 = (pyc_or_681 | pyc_and_682); -assign pyc_extract_684 = PE_INT_WALLACE_DOT8_TREE_in4[7]; -assign pyc_extract_685 = PE_INT_WALLACE_DOT8_TREE_in5[7]; -assign pyc_extract_686 = PE_INT_WALLACE_DOT8_TREE_in6[7]; -assign pyc_xor_687 = (pyc_extract_684 ^ pyc_extract_685); -assign pyc_xor_688 = (pyc_xor_687 ^ pyc_extract_686); -assign pyc_and_689 = (pyc_extract_684 & pyc_extract_685); -assign pyc_and_690 = (pyc_extract_684 & pyc_extract_686); -assign pyc_or_691 = (pyc_and_689 | pyc_and_690); -assign pyc_and_692 = (pyc_extract_685 & pyc_extract_686); -assign pyc_or_693 = (pyc_or_691 | pyc_and_692); -assign pyc_extract_694 = PE_INT_WALLACE_DOT8_TREE_in7[7]; -assign pyc_xor_695 = (pyc_xor_688 ^ pyc_extract_694); -assign pyc_xor_696 = (pyc_xor_695 ^ pyc_or_675); -assign pyc_and_697 = (pyc_xor_688 & pyc_extract_694); -assign pyc_and_698 = (pyc_xor_688 & pyc_or_675); -assign pyc_or_699 = (pyc_and_697 | pyc_and_698); -assign pyc_and_700 = (pyc_extract_694 & pyc_or_675); -assign pyc_or_701 = (pyc_or_699 | pyc_and_700); -assign pyc_extract_702 = PE_INT_WALLACE_DOT8_TREE_in4[8]; -assign pyc_extract_703 = PE_INT_WALLACE_DOT8_TREE_in5[8]; -assign pyc_extract_704 = PE_INT_WALLACE_DOT8_TREE_in6[8]; -assign pyc_xor_705 = (pyc_extract_702 ^ pyc_extract_703); -assign pyc_xor_706 = (pyc_xor_705 ^ pyc_extract_704); -assign pyc_and_707 = (pyc_extract_702 & pyc_extract_703); -assign pyc_and_708 = (pyc_extract_702 & pyc_extract_704); -assign pyc_or_709 = (pyc_and_707 | pyc_and_708); -assign pyc_and_710 = (pyc_extract_703 & pyc_extract_704); -assign pyc_or_711 = (pyc_or_709 | pyc_and_710); -assign pyc_extract_712 = PE_INT_WALLACE_DOT8_TREE_in7[8]; -assign pyc_xor_713 = (pyc_xor_706 ^ pyc_extract_712); -assign pyc_xor_714 = (pyc_xor_713 ^ pyc_or_693); -assign pyc_and_715 = (pyc_xor_706 & pyc_extract_712); -assign pyc_and_716 = (pyc_xor_706 & pyc_or_693); -assign pyc_or_717 = (pyc_and_715 | pyc_and_716); -assign pyc_and_718 = (pyc_extract_712 & pyc_or_693); -assign pyc_or_719 = (pyc_or_717 | pyc_and_718); -assign pyc_extract_720 = PE_INT_WALLACE_DOT8_TREE_in4[9]; -assign pyc_extract_721 = PE_INT_WALLACE_DOT8_TREE_in5[9]; -assign pyc_extract_722 = PE_INT_WALLACE_DOT8_TREE_in6[9]; -assign pyc_xor_723 = (pyc_extract_720 ^ pyc_extract_721); -assign pyc_xor_724 = (pyc_xor_723 ^ pyc_extract_722); -assign pyc_and_725 = (pyc_extract_720 & pyc_extract_721); -assign pyc_and_726 = (pyc_extract_720 & pyc_extract_722); -assign pyc_or_727 = (pyc_and_725 | pyc_and_726); -assign pyc_and_728 = (pyc_extract_721 & pyc_extract_722); -assign pyc_or_729 = (pyc_or_727 | pyc_and_728); -assign pyc_extract_730 = PE_INT_WALLACE_DOT8_TREE_in7[9]; -assign pyc_xor_731 = (pyc_xor_724 ^ pyc_extract_730); -assign pyc_xor_732 = (pyc_xor_731 ^ pyc_or_711); -assign pyc_and_733 = (pyc_xor_724 & pyc_extract_730); -assign pyc_and_734 = (pyc_xor_724 & pyc_or_711); -assign pyc_or_735 = (pyc_and_733 | pyc_and_734); -assign pyc_and_736 = (pyc_extract_730 & pyc_or_711); -assign pyc_or_737 = (pyc_or_735 | pyc_and_736); -assign pyc_extract_738 = PE_INT_WALLACE_DOT8_TREE_in4[10]; -assign pyc_extract_739 = PE_INT_WALLACE_DOT8_TREE_in5[10]; -assign pyc_extract_740 = PE_INT_WALLACE_DOT8_TREE_in6[10]; -assign pyc_xor_741 = (pyc_extract_738 ^ pyc_extract_739); -assign pyc_xor_742 = (pyc_xor_741 ^ pyc_extract_740); -assign pyc_and_743 = (pyc_extract_738 & pyc_extract_739); -assign pyc_and_744 = (pyc_extract_738 & pyc_extract_740); -assign pyc_or_745 = (pyc_and_743 | pyc_and_744); -assign pyc_and_746 = (pyc_extract_739 & pyc_extract_740); -assign pyc_or_747 = (pyc_or_745 | pyc_and_746); -assign pyc_extract_748 = PE_INT_WALLACE_DOT8_TREE_in7[10]; -assign pyc_xor_749 = (pyc_xor_742 ^ pyc_extract_748); -assign pyc_xor_750 = (pyc_xor_749 ^ pyc_or_729); -assign pyc_and_751 = (pyc_xor_742 & pyc_extract_748); -assign pyc_and_752 = (pyc_xor_742 & pyc_or_729); -assign pyc_or_753 = (pyc_and_751 | pyc_and_752); -assign pyc_and_754 = (pyc_extract_748 & pyc_or_729); -assign pyc_or_755 = (pyc_or_753 | pyc_and_754); -assign pyc_extract_756 = PE_INT_WALLACE_DOT8_TREE_in4[11]; -assign pyc_extract_757 = PE_INT_WALLACE_DOT8_TREE_in5[11]; -assign pyc_extract_758 = PE_INT_WALLACE_DOT8_TREE_in6[11]; -assign pyc_xor_759 = (pyc_extract_756 ^ pyc_extract_757); -assign pyc_xor_760 = (pyc_xor_759 ^ pyc_extract_758); -assign pyc_and_761 = (pyc_extract_756 & pyc_extract_757); -assign pyc_and_762 = (pyc_extract_756 & pyc_extract_758); -assign pyc_or_763 = (pyc_and_761 | pyc_and_762); -assign pyc_and_764 = (pyc_extract_757 & pyc_extract_758); -assign pyc_or_765 = (pyc_or_763 | pyc_and_764); -assign pyc_extract_766 = PE_INT_WALLACE_DOT8_TREE_in7[11]; -assign pyc_xor_767 = (pyc_xor_760 ^ pyc_extract_766); -assign pyc_xor_768 = (pyc_xor_767 ^ pyc_or_747); -assign pyc_and_769 = (pyc_xor_760 & pyc_extract_766); -assign pyc_and_770 = (pyc_xor_760 & pyc_or_747); -assign pyc_or_771 = (pyc_and_769 | pyc_and_770); -assign pyc_and_772 = (pyc_extract_766 & pyc_or_747); -assign pyc_or_773 = (pyc_or_771 | pyc_and_772); -assign pyc_extract_774 = PE_INT_WALLACE_DOT8_TREE_in4[12]; -assign pyc_extract_775 = PE_INT_WALLACE_DOT8_TREE_in5[12]; -assign pyc_extract_776 = PE_INT_WALLACE_DOT8_TREE_in6[12]; -assign pyc_xor_777 = (pyc_extract_774 ^ pyc_extract_775); -assign pyc_xor_778 = (pyc_xor_777 ^ pyc_extract_776); -assign pyc_and_779 = (pyc_extract_774 & pyc_extract_775); -assign pyc_and_780 = (pyc_extract_774 & pyc_extract_776); -assign pyc_or_781 = (pyc_and_779 | pyc_and_780); -assign pyc_and_782 = (pyc_extract_775 & pyc_extract_776); -assign pyc_or_783 = (pyc_or_781 | pyc_and_782); -assign pyc_extract_784 = PE_INT_WALLACE_DOT8_TREE_in7[12]; -assign pyc_xor_785 = (pyc_xor_778 ^ pyc_extract_784); -assign pyc_xor_786 = (pyc_xor_785 ^ pyc_or_765); -assign pyc_and_787 = (pyc_xor_778 & pyc_extract_784); -assign pyc_and_788 = (pyc_xor_778 & pyc_or_765); -assign pyc_or_789 = (pyc_and_787 | pyc_and_788); -assign pyc_and_790 = (pyc_extract_784 & pyc_or_765); -assign pyc_or_791 = (pyc_or_789 | pyc_and_790); -assign pyc_extract_792 = PE_INT_WALLACE_DOT8_TREE_in4[13]; -assign pyc_extract_793 = PE_INT_WALLACE_DOT8_TREE_in5[13]; -assign pyc_extract_794 = PE_INT_WALLACE_DOT8_TREE_in6[13]; -assign pyc_xor_795 = (pyc_extract_792 ^ pyc_extract_793); -assign pyc_xor_796 = (pyc_xor_795 ^ pyc_extract_794); -assign pyc_and_797 = (pyc_extract_792 & pyc_extract_793); -assign pyc_and_798 = (pyc_extract_792 & pyc_extract_794); -assign pyc_or_799 = (pyc_and_797 | pyc_and_798); -assign pyc_and_800 = (pyc_extract_793 & pyc_extract_794); -assign pyc_or_801 = (pyc_or_799 | pyc_and_800); -assign pyc_extract_802 = PE_INT_WALLACE_DOT8_TREE_in7[13]; -assign pyc_xor_803 = (pyc_xor_796 ^ pyc_extract_802); -assign pyc_xor_804 = (pyc_xor_803 ^ pyc_or_783); -assign pyc_and_805 = (pyc_xor_796 & pyc_extract_802); -assign pyc_and_806 = (pyc_xor_796 & pyc_or_783); -assign pyc_or_807 = (pyc_and_805 | pyc_and_806); -assign pyc_and_808 = (pyc_extract_802 & pyc_or_783); -assign pyc_or_809 = (pyc_or_807 | pyc_and_808); -assign pyc_extract_810 = PE_INT_WALLACE_DOT8_TREE_in4[14]; -assign pyc_extract_811 = PE_INT_WALLACE_DOT8_TREE_in5[14]; -assign pyc_extract_812 = PE_INT_WALLACE_DOT8_TREE_in6[14]; -assign pyc_xor_813 = (pyc_extract_810 ^ pyc_extract_811); -assign pyc_xor_814 = (pyc_xor_813 ^ pyc_extract_812); -assign pyc_and_815 = (pyc_extract_810 & pyc_extract_811); -assign pyc_and_816 = (pyc_extract_810 & pyc_extract_812); -assign pyc_or_817 = (pyc_and_815 | pyc_and_816); -assign pyc_and_818 = (pyc_extract_811 & pyc_extract_812); -assign pyc_or_819 = (pyc_or_817 | pyc_and_818); -assign pyc_extract_820 = PE_INT_WALLACE_DOT8_TREE_in7[14]; -assign pyc_xor_821 = (pyc_xor_814 ^ pyc_extract_820); -assign pyc_xor_822 = (pyc_xor_821 ^ pyc_or_801); -assign pyc_and_823 = (pyc_xor_814 & pyc_extract_820); -assign pyc_and_824 = (pyc_xor_814 & pyc_or_801); -assign pyc_or_825 = (pyc_and_823 | pyc_and_824); -assign pyc_and_826 = (pyc_extract_820 & pyc_or_801); -assign pyc_or_827 = (pyc_or_825 | pyc_and_826); -assign pyc_extract_828 = PE_INT_WALLACE_DOT8_TREE_in4[15]; -assign pyc_extract_829 = PE_INT_WALLACE_DOT8_TREE_in5[15]; -assign pyc_extract_830 = PE_INT_WALLACE_DOT8_TREE_in6[15]; -assign pyc_xor_831 = (pyc_extract_828 ^ pyc_extract_829); -assign pyc_xor_832 = (pyc_xor_831 ^ pyc_extract_830); -assign pyc_and_833 = (pyc_extract_828 & pyc_extract_829); -assign pyc_and_834 = (pyc_extract_828 & pyc_extract_830); -assign pyc_or_835 = (pyc_and_833 | pyc_and_834); -assign pyc_and_836 = (pyc_extract_829 & pyc_extract_830); -assign pyc_or_837 = (pyc_or_835 | pyc_and_836); -assign pyc_extract_838 = PE_INT_WALLACE_DOT8_TREE_in7[15]; -assign pyc_xor_839 = (pyc_xor_832 ^ pyc_extract_838); -assign pyc_xor_840 = (pyc_xor_839 ^ pyc_or_819); -assign pyc_and_841 = (pyc_xor_832 & pyc_extract_838); -assign pyc_and_842 = (pyc_xor_832 & pyc_or_819); -assign pyc_or_843 = (pyc_and_841 | pyc_and_842); -assign pyc_and_844 = (pyc_extract_838 & pyc_or_819); -assign pyc_or_845 = (pyc_or_843 | pyc_and_844); -assign pyc_extract_846 = PE_INT_WALLACE_DOT8_TREE_in4[16]; -assign pyc_extract_847 = PE_INT_WALLACE_DOT8_TREE_in5[16]; -assign pyc_extract_848 = PE_INT_WALLACE_DOT8_TREE_in6[16]; -assign pyc_xor_849 = (pyc_extract_846 ^ pyc_extract_847); -assign pyc_xor_850 = (pyc_xor_849 ^ pyc_extract_848); -assign pyc_and_851 = (pyc_extract_846 & pyc_extract_847); -assign pyc_and_852 = (pyc_extract_846 & pyc_extract_848); -assign pyc_or_853 = (pyc_and_851 | pyc_and_852); -assign pyc_and_854 = (pyc_extract_847 & pyc_extract_848); -assign pyc_or_855 = (pyc_or_853 | pyc_and_854); -assign pyc_extract_856 = PE_INT_WALLACE_DOT8_TREE_in7[16]; -assign pyc_xor_857 = (pyc_xor_850 ^ pyc_extract_856); -assign pyc_xor_858 = (pyc_xor_857 ^ pyc_or_837); -assign pyc_and_859 = (pyc_xor_850 & pyc_extract_856); -assign pyc_and_860 = (pyc_xor_850 & pyc_or_837); -assign pyc_or_861 = (pyc_and_859 | pyc_and_860); -assign pyc_and_862 = (pyc_extract_856 & pyc_or_837); -assign pyc_or_863 = (pyc_or_861 | pyc_and_862); -assign pyc_extract_864 = PE_INT_WALLACE_DOT8_TREE_in4[17]; -assign pyc_extract_865 = PE_INT_WALLACE_DOT8_TREE_in5[17]; -assign pyc_extract_866 = PE_INT_WALLACE_DOT8_TREE_in6[17]; -assign pyc_xor_867 = (pyc_extract_864 ^ pyc_extract_865); -assign pyc_xor_868 = (pyc_xor_867 ^ pyc_extract_866); -assign pyc_and_869 = (pyc_extract_864 & pyc_extract_865); -assign pyc_and_870 = (pyc_extract_864 & pyc_extract_866); -assign pyc_or_871 = (pyc_and_869 | pyc_and_870); -assign pyc_and_872 = (pyc_extract_865 & pyc_extract_866); -assign pyc_or_873 = (pyc_or_871 | pyc_and_872); -assign pyc_extract_874 = PE_INT_WALLACE_DOT8_TREE_in7[17]; -assign pyc_xor_875 = (pyc_xor_868 ^ pyc_extract_874); -assign pyc_xor_876 = (pyc_xor_875 ^ pyc_or_855); -assign pyc_and_877 = (pyc_xor_868 & pyc_extract_874); -assign pyc_and_878 = (pyc_xor_868 & pyc_or_855); -assign pyc_or_879 = (pyc_and_877 | pyc_and_878); -assign pyc_and_880 = (pyc_extract_874 & pyc_or_855); -assign pyc_or_881 = (pyc_or_879 | pyc_and_880); -assign pyc_extract_882 = PE_INT_WALLACE_DOT8_TREE_in4[18]; -assign pyc_extract_883 = PE_INT_WALLACE_DOT8_TREE_in5[18]; -assign pyc_extract_884 = PE_INT_WALLACE_DOT8_TREE_in6[18]; -assign pyc_xor_885 = (pyc_extract_882 ^ pyc_extract_883); -assign pyc_xor_886 = (pyc_xor_885 ^ pyc_extract_884); -assign pyc_and_887 = (pyc_extract_882 & pyc_extract_883); -assign pyc_and_888 = (pyc_extract_882 & pyc_extract_884); -assign pyc_or_889 = (pyc_and_887 | pyc_and_888); -assign pyc_and_890 = (pyc_extract_883 & pyc_extract_884); -assign pyc_or_891 = (pyc_or_889 | pyc_and_890); -assign pyc_extract_892 = PE_INT_WALLACE_DOT8_TREE_in7[18]; -assign pyc_xor_893 = (pyc_xor_886 ^ pyc_extract_892); -assign pyc_xor_894 = (pyc_xor_893 ^ pyc_or_873); -assign pyc_and_895 = (pyc_xor_886 & pyc_extract_892); -assign pyc_and_896 = (pyc_xor_886 & pyc_or_873); -assign pyc_or_897 = (pyc_and_895 | pyc_and_896); -assign pyc_and_898 = (pyc_extract_892 & pyc_or_873); -assign pyc_or_899 = (pyc_or_897 | pyc_and_898); -assign pyc_extract_900 = PE_INT_WALLACE_DOT8_TREE_in4[19]; -assign pyc_extract_901 = PE_INT_WALLACE_DOT8_TREE_in5[19]; -assign pyc_extract_902 = PE_INT_WALLACE_DOT8_TREE_in6[19]; -assign pyc_xor_903 = (pyc_extract_900 ^ pyc_extract_901); -assign pyc_xor_904 = (pyc_xor_903 ^ pyc_extract_902); -assign pyc_and_905 = (pyc_extract_900 & pyc_extract_901); -assign pyc_and_906 = (pyc_extract_900 & pyc_extract_902); -assign pyc_or_907 = (pyc_and_905 | pyc_and_906); -assign pyc_and_908 = (pyc_extract_901 & pyc_extract_902); -assign pyc_or_909 = (pyc_or_907 | pyc_and_908); -assign pyc_extract_910 = PE_INT_WALLACE_DOT8_TREE_in7[19]; -assign pyc_xor_911 = (pyc_xor_904 ^ pyc_extract_910); -assign pyc_xor_912 = (pyc_xor_911 ^ pyc_or_891); -assign pyc_and_913 = (pyc_xor_904 & pyc_extract_910); -assign pyc_and_914 = (pyc_xor_904 & pyc_or_891); -assign pyc_or_915 = (pyc_and_913 | pyc_and_914); -assign pyc_and_916 = (pyc_extract_910 & pyc_or_891); -assign pyc_or_917 = (pyc_or_915 | pyc_and_916); -assign pyc_extract_918 = PE_INT_WALLACE_DOT8_TREE_in4[20]; -assign pyc_extract_919 = PE_INT_WALLACE_DOT8_TREE_in5[20]; -assign pyc_extract_920 = PE_INT_WALLACE_DOT8_TREE_in6[20]; -assign pyc_xor_921 = (pyc_extract_918 ^ pyc_extract_919); -assign pyc_xor_922 = (pyc_xor_921 ^ pyc_extract_920); -assign pyc_and_923 = (pyc_extract_918 & pyc_extract_919); -assign pyc_and_924 = (pyc_extract_918 & pyc_extract_920); -assign pyc_or_925 = (pyc_and_923 | pyc_and_924); -assign pyc_and_926 = (pyc_extract_919 & pyc_extract_920); -assign pyc_or_927 = (pyc_or_925 | pyc_and_926); -assign pyc_extract_928 = PE_INT_WALLACE_DOT8_TREE_in7[20]; -assign pyc_xor_929 = (pyc_xor_922 ^ pyc_extract_928); -assign pyc_xor_930 = (pyc_xor_929 ^ pyc_or_909); -assign pyc_and_931 = (pyc_xor_922 & pyc_extract_928); -assign pyc_and_932 = (pyc_xor_922 & pyc_or_909); -assign pyc_or_933 = (pyc_and_931 | pyc_and_932); -assign pyc_and_934 = (pyc_extract_928 & pyc_or_909); -assign pyc_or_935 = (pyc_or_933 | pyc_and_934); -assign pyc_extract_936 = PE_INT_WALLACE_DOT8_TREE_in4[21]; -assign pyc_extract_937 = PE_INT_WALLACE_DOT8_TREE_in5[21]; -assign pyc_extract_938 = PE_INT_WALLACE_DOT8_TREE_in6[21]; -assign pyc_xor_939 = (pyc_extract_936 ^ pyc_extract_937); -assign pyc_xor_940 = (pyc_xor_939 ^ pyc_extract_938); -assign pyc_and_941 = (pyc_extract_936 & pyc_extract_937); -assign pyc_and_942 = (pyc_extract_936 & pyc_extract_938); -assign pyc_or_943 = (pyc_and_941 | pyc_and_942); -assign pyc_and_944 = (pyc_extract_937 & pyc_extract_938); -assign pyc_or_945 = (pyc_or_943 | pyc_and_944); -assign pyc_extract_946 = PE_INT_WALLACE_DOT8_TREE_in7[21]; -assign pyc_xor_947 = (pyc_xor_940 ^ pyc_extract_946); -assign pyc_xor_948 = (pyc_xor_947 ^ pyc_or_927); -assign pyc_and_949 = (pyc_xor_940 & pyc_extract_946); -assign pyc_and_950 = (pyc_xor_940 & pyc_or_927); -assign pyc_or_951 = (pyc_and_949 | pyc_and_950); -assign pyc_and_952 = (pyc_extract_946 & pyc_or_927); -assign pyc_or_953 = (pyc_or_951 | pyc_and_952); -assign pyc_extract_954 = PE_INT_WALLACE_DOT8_TREE_in4[22]; -assign pyc_extract_955 = PE_INT_WALLACE_DOT8_TREE_in5[22]; -assign pyc_extract_956 = PE_INT_WALLACE_DOT8_TREE_in6[22]; -assign pyc_xor_957 = (pyc_extract_954 ^ pyc_extract_955); -assign pyc_xor_958 = (pyc_xor_957 ^ pyc_extract_956); -assign pyc_and_959 = (pyc_extract_954 & pyc_extract_955); -assign pyc_and_960 = (pyc_extract_954 & pyc_extract_956); -assign pyc_or_961 = (pyc_and_959 | pyc_and_960); -assign pyc_and_962 = (pyc_extract_955 & pyc_extract_956); -assign pyc_or_963 = (pyc_or_961 | pyc_and_962); -assign pyc_extract_964 = PE_INT_WALLACE_DOT8_TREE_in7[22]; -assign pyc_xor_965 = (pyc_xor_958 ^ pyc_extract_964); -assign pyc_xor_966 = (pyc_xor_965 ^ pyc_or_945); -assign pyc_and_967 = (pyc_xor_958 & pyc_extract_964); -assign pyc_and_968 = (pyc_xor_958 & pyc_or_945); -assign pyc_or_969 = (pyc_and_967 | pyc_and_968); -assign pyc_and_970 = (pyc_extract_964 & pyc_or_945); -assign pyc_or_971 = (pyc_or_969 | pyc_and_970); -assign pyc_extract_972 = PE_INT_WALLACE_DOT8_TREE_in4[23]; -assign pyc_extract_973 = PE_INT_WALLACE_DOT8_TREE_in5[23]; -assign pyc_extract_974 = PE_INT_WALLACE_DOT8_TREE_in6[23]; -assign pyc_xor_975 = (pyc_extract_972 ^ pyc_extract_973); -assign pyc_xor_976 = (pyc_xor_975 ^ pyc_extract_974); -assign pyc_and_977 = (pyc_extract_972 & pyc_extract_973); -assign pyc_and_978 = (pyc_extract_972 & pyc_extract_974); -assign pyc_or_979 = (pyc_and_977 | pyc_and_978); -assign pyc_and_980 = (pyc_extract_973 & pyc_extract_974); -assign pyc_or_981 = (pyc_or_979 | pyc_and_980); -assign pyc_extract_982 = PE_INT_WALLACE_DOT8_TREE_in7[23]; -assign pyc_xor_983 = (pyc_xor_976 ^ pyc_extract_982); -assign pyc_xor_984 = (pyc_xor_983 ^ pyc_or_963); -assign pyc_and_985 = (pyc_xor_976 & pyc_extract_982); -assign pyc_and_986 = (pyc_xor_976 & pyc_or_963); -assign pyc_or_987 = (pyc_and_985 | pyc_and_986); -assign pyc_and_988 = (pyc_extract_982 & pyc_or_963); -assign pyc_or_989 = (pyc_or_987 | pyc_and_988); -assign pyc_extract_990 = PE_INT_WALLACE_DOT8_TREE_in4[24]; -assign pyc_extract_991 = PE_INT_WALLACE_DOT8_TREE_in5[24]; -assign pyc_extract_992 = PE_INT_WALLACE_DOT8_TREE_in6[24]; -assign pyc_xor_993 = (pyc_extract_990 ^ pyc_extract_991); -assign pyc_xor_994 = (pyc_xor_993 ^ pyc_extract_992); -assign pyc_and_995 = (pyc_extract_990 & pyc_extract_991); -assign pyc_and_996 = (pyc_extract_990 & pyc_extract_992); -assign pyc_or_997 = (pyc_and_995 | pyc_and_996); -assign pyc_and_998 = (pyc_extract_991 & pyc_extract_992); -assign pyc_or_999 = (pyc_or_997 | pyc_and_998); -assign pyc_extract_1000 = PE_INT_WALLACE_DOT8_TREE_in7[24]; -assign pyc_xor_1001 = (pyc_xor_994 ^ pyc_extract_1000); -assign pyc_xor_1002 = (pyc_xor_1001 ^ pyc_or_981); -assign pyc_and_1003 = (pyc_xor_994 & pyc_extract_1000); -assign pyc_and_1004 = (pyc_xor_994 & pyc_or_981); -assign pyc_or_1005 = (pyc_and_1003 | pyc_and_1004); -assign pyc_and_1006 = (pyc_extract_1000 & pyc_or_981); -assign pyc_or_1007 = (pyc_or_1005 | pyc_and_1006); -assign pyc_extract_1008 = PE_INT_WALLACE_DOT8_TREE_in4[25]; -assign pyc_extract_1009 = PE_INT_WALLACE_DOT8_TREE_in5[25]; -assign pyc_extract_1010 = PE_INT_WALLACE_DOT8_TREE_in6[25]; -assign pyc_xor_1011 = (pyc_extract_1008 ^ pyc_extract_1009); -assign pyc_xor_1012 = (pyc_xor_1011 ^ pyc_extract_1010); -assign pyc_and_1013 = (pyc_extract_1008 & pyc_extract_1009); -assign pyc_and_1014 = (pyc_extract_1008 & pyc_extract_1010); -assign pyc_or_1015 = (pyc_and_1013 | pyc_and_1014); -assign pyc_and_1016 = (pyc_extract_1009 & pyc_extract_1010); -assign pyc_or_1017 = (pyc_or_1015 | pyc_and_1016); -assign pyc_extract_1018 = PE_INT_WALLACE_DOT8_TREE_in7[25]; -assign pyc_xor_1019 = (pyc_xor_1012 ^ pyc_extract_1018); -assign pyc_xor_1020 = (pyc_xor_1019 ^ pyc_or_999); -assign pyc_and_1021 = (pyc_xor_1012 & pyc_extract_1018); -assign pyc_and_1022 = (pyc_xor_1012 & pyc_or_999); -assign pyc_or_1023 = (pyc_and_1021 | pyc_and_1022); -assign pyc_and_1024 = (pyc_extract_1018 & pyc_or_999); -assign pyc_or_1025 = (pyc_or_1023 | pyc_and_1024); -assign pyc_extract_1026 = PE_INT_WALLACE_DOT8_TREE_in4[26]; -assign pyc_extract_1027 = PE_INT_WALLACE_DOT8_TREE_in5[26]; -assign pyc_extract_1028 = PE_INT_WALLACE_DOT8_TREE_in6[26]; -assign pyc_xor_1029 = (pyc_extract_1026 ^ pyc_extract_1027); -assign pyc_xor_1030 = (pyc_xor_1029 ^ pyc_extract_1028); -assign pyc_and_1031 = (pyc_extract_1026 & pyc_extract_1027); -assign pyc_and_1032 = (pyc_extract_1026 & pyc_extract_1028); -assign pyc_or_1033 = (pyc_and_1031 | pyc_and_1032); -assign pyc_and_1034 = (pyc_extract_1027 & pyc_extract_1028); -assign pyc_or_1035 = (pyc_or_1033 | pyc_and_1034); -assign pyc_extract_1036 = PE_INT_WALLACE_DOT8_TREE_in7[26]; -assign pyc_xor_1037 = (pyc_xor_1030 ^ pyc_extract_1036); -assign pyc_xor_1038 = (pyc_xor_1037 ^ pyc_or_1017); -assign pyc_and_1039 = (pyc_xor_1030 & pyc_extract_1036); -assign pyc_and_1040 = (pyc_xor_1030 & pyc_or_1017); -assign pyc_or_1041 = (pyc_and_1039 | pyc_and_1040); -assign pyc_and_1042 = (pyc_extract_1036 & pyc_or_1017); -assign pyc_or_1043 = (pyc_or_1041 | pyc_and_1042); -assign pyc_extract_1044 = PE_INT_WALLACE_DOT8_TREE_in4[27]; -assign pyc_extract_1045 = PE_INT_WALLACE_DOT8_TREE_in5[27]; -assign pyc_extract_1046 = PE_INT_WALLACE_DOT8_TREE_in6[27]; -assign pyc_xor_1047 = (pyc_extract_1044 ^ pyc_extract_1045); -assign pyc_xor_1048 = (pyc_xor_1047 ^ pyc_extract_1046); -assign pyc_and_1049 = (pyc_extract_1044 & pyc_extract_1045); -assign pyc_and_1050 = (pyc_extract_1044 & pyc_extract_1046); -assign pyc_or_1051 = (pyc_and_1049 | pyc_and_1050); -assign pyc_and_1052 = (pyc_extract_1045 & pyc_extract_1046); -assign pyc_or_1053 = (pyc_or_1051 | pyc_and_1052); -assign pyc_extract_1054 = PE_INT_WALLACE_DOT8_TREE_in7[27]; -assign pyc_xor_1055 = (pyc_xor_1048 ^ pyc_extract_1054); -assign pyc_xor_1056 = (pyc_xor_1055 ^ pyc_or_1035); -assign pyc_and_1057 = (pyc_xor_1048 & pyc_extract_1054); -assign pyc_and_1058 = (pyc_xor_1048 & pyc_or_1035); -assign pyc_or_1059 = (pyc_and_1057 | pyc_and_1058); -assign pyc_and_1060 = (pyc_extract_1054 & pyc_or_1035); -assign pyc_or_1061 = (pyc_or_1059 | pyc_and_1060); -assign pyc_extract_1062 = PE_INT_WALLACE_DOT8_TREE_in4[28]; -assign pyc_extract_1063 = PE_INT_WALLACE_DOT8_TREE_in5[28]; -assign pyc_extract_1064 = PE_INT_WALLACE_DOT8_TREE_in6[28]; -assign pyc_xor_1065 = (pyc_extract_1062 ^ pyc_extract_1063); -assign pyc_xor_1066 = (pyc_xor_1065 ^ pyc_extract_1064); -assign pyc_and_1067 = (pyc_extract_1062 & pyc_extract_1063); -assign pyc_and_1068 = (pyc_extract_1062 & pyc_extract_1064); -assign pyc_or_1069 = (pyc_and_1067 | pyc_and_1068); -assign pyc_and_1070 = (pyc_extract_1063 & pyc_extract_1064); -assign pyc_or_1071 = (pyc_or_1069 | pyc_and_1070); -assign pyc_extract_1072 = PE_INT_WALLACE_DOT8_TREE_in7[28]; -assign pyc_xor_1073 = (pyc_xor_1066 ^ pyc_extract_1072); -assign pyc_xor_1074 = (pyc_xor_1073 ^ pyc_or_1053); -assign pyc_and_1075 = (pyc_xor_1066 & pyc_extract_1072); -assign pyc_and_1076 = (pyc_xor_1066 & pyc_or_1053); -assign pyc_or_1077 = (pyc_and_1075 | pyc_and_1076); -assign pyc_and_1078 = (pyc_extract_1072 & pyc_or_1053); -assign pyc_or_1079 = (pyc_or_1077 | pyc_and_1078); -assign pyc_extract_1080 = PE_INT_WALLACE_DOT8_TREE_in4[29]; -assign pyc_extract_1081 = PE_INT_WALLACE_DOT8_TREE_in5[29]; -assign pyc_extract_1082 = PE_INT_WALLACE_DOT8_TREE_in6[29]; -assign pyc_xor_1083 = (pyc_extract_1080 ^ pyc_extract_1081); -assign pyc_xor_1084 = (pyc_xor_1083 ^ pyc_extract_1082); -assign pyc_and_1085 = (pyc_extract_1080 & pyc_extract_1081); -assign pyc_and_1086 = (pyc_extract_1080 & pyc_extract_1082); -assign pyc_or_1087 = (pyc_and_1085 | pyc_and_1086); -assign pyc_and_1088 = (pyc_extract_1081 & pyc_extract_1082); -assign pyc_or_1089 = (pyc_or_1087 | pyc_and_1088); -assign pyc_extract_1090 = PE_INT_WALLACE_DOT8_TREE_in7[29]; -assign pyc_xor_1091 = (pyc_xor_1084 ^ pyc_extract_1090); -assign pyc_xor_1092 = (pyc_xor_1091 ^ pyc_or_1071); -assign pyc_and_1093 = (pyc_xor_1084 & pyc_extract_1090); -assign pyc_and_1094 = (pyc_xor_1084 & pyc_or_1071); -assign pyc_or_1095 = (pyc_and_1093 | pyc_and_1094); -assign pyc_and_1096 = (pyc_extract_1090 & pyc_or_1071); -assign pyc_or_1097 = (pyc_or_1095 | pyc_and_1096); -assign pyc_extract_1098 = PE_INT_WALLACE_DOT8_TREE_in4[30]; -assign pyc_extract_1099 = PE_INT_WALLACE_DOT8_TREE_in5[30]; -assign pyc_extract_1100 = PE_INT_WALLACE_DOT8_TREE_in6[30]; -assign pyc_xor_1101 = (pyc_extract_1098 ^ pyc_extract_1099); -assign pyc_xor_1102 = (pyc_xor_1101 ^ pyc_extract_1100); -assign pyc_and_1103 = (pyc_extract_1098 & pyc_extract_1099); -assign pyc_and_1104 = (pyc_extract_1098 & pyc_extract_1100); -assign pyc_or_1105 = (pyc_and_1103 | pyc_and_1104); -assign pyc_and_1106 = (pyc_extract_1099 & pyc_extract_1100); -assign pyc_or_1107 = (pyc_or_1105 | pyc_and_1106); -assign pyc_extract_1108 = PE_INT_WALLACE_DOT8_TREE_in7[30]; -assign pyc_xor_1109 = (pyc_xor_1102 ^ pyc_extract_1108); -assign pyc_xor_1110 = (pyc_xor_1109 ^ pyc_or_1089); -assign pyc_and_1111 = (pyc_xor_1102 & pyc_extract_1108); -assign pyc_and_1112 = (pyc_xor_1102 & pyc_or_1089); -assign pyc_or_1113 = (pyc_and_1111 | pyc_and_1112); -assign pyc_and_1114 = (pyc_extract_1108 & pyc_or_1089); -assign pyc_or_1115 = (pyc_or_1113 | pyc_and_1114); -assign pyc_extract_1116 = PE_INT_WALLACE_DOT8_TREE_in4[31]; -assign pyc_extract_1117 = PE_INT_WALLACE_DOT8_TREE_in5[31]; -assign pyc_extract_1118 = PE_INT_WALLACE_DOT8_TREE_in6[31]; -assign pyc_xor_1119 = (pyc_extract_1116 ^ pyc_extract_1117); -assign pyc_xor_1120 = (pyc_xor_1119 ^ pyc_extract_1118); -assign pyc_extract_1121 = PE_INT_WALLACE_DOT8_TREE_in7[31]; -assign pyc_xor_1122 = (pyc_xor_1120 ^ pyc_extract_1121); -assign pyc_xor_1123 = (pyc_xor_1122 ^ pyc_or_1107); -assign pyc_xor_1124 = (pyc_xor_13 ^ pyc_xor_574); -assign pyc_and_1125 = (pyc_xor_13 & pyc_xor_574); -assign pyc_xor_1126 = (pyc_xor_27 ^ pyc_and_14); -assign pyc_xor_1127 = (pyc_xor_1126 ^ pyc_xor_588); -assign pyc_and_1128 = (pyc_xor_27 & pyc_and_14); -assign pyc_and_1129 = (pyc_xor_27 & pyc_xor_588); -assign pyc_or_1130 = (pyc_and_1128 | pyc_and_1129); -assign pyc_and_1131 = (pyc_and_14 & pyc_xor_588); -assign pyc_or_1132 = (pyc_or_1130 | pyc_and_1131); -assign pyc_xor_1133 = (pyc_xor_1127 ^ pyc_and_575); -assign pyc_xor_1134 = (pyc_xor_1133 ^ pyc_and_1125); -assign pyc_and_1135 = (pyc_xor_1127 & pyc_and_575); -assign pyc_and_1136 = (pyc_xor_1127 & pyc_and_1125); -assign pyc_or_1137 = (pyc_and_1135 | pyc_and_1136); -assign pyc_and_1138 = (pyc_and_575 & pyc_and_1125); -assign pyc_or_1139 = (pyc_or_1137 | pyc_and_1138); -assign pyc_xor_1140 = (pyc_xor_45 ^ pyc_or_32); -assign pyc_xor_1141 = (pyc_xor_1140 ^ pyc_xor_606); -assign pyc_and_1142 = (pyc_xor_45 & pyc_or_32); -assign pyc_and_1143 = (pyc_xor_45 & pyc_xor_606); -assign pyc_or_1144 = (pyc_and_1142 | pyc_and_1143); -assign pyc_and_1145 = (pyc_or_32 & pyc_xor_606); -assign pyc_or_1146 = (pyc_or_1144 | pyc_and_1145); -assign pyc_xor_1147 = (pyc_xor_1141 ^ pyc_or_593); -assign pyc_xor_1148 = (pyc_xor_1147 ^ pyc_or_1132); -assign pyc_and_1149 = (pyc_xor_1141 & pyc_or_593); -assign pyc_and_1150 = (pyc_xor_1141 & pyc_or_1132); -assign pyc_or_1151 = (pyc_and_1149 | pyc_and_1150); -assign pyc_and_1152 = (pyc_or_593 & pyc_or_1132); -assign pyc_or_1153 = (pyc_or_1151 | pyc_and_1152); -assign pyc_xor_1154 = (pyc_xor_63 ^ pyc_or_50); -assign pyc_xor_1155 = (pyc_xor_1154 ^ pyc_xor_624); -assign pyc_and_1156 = (pyc_xor_63 & pyc_or_50); -assign pyc_and_1157 = (pyc_xor_63 & pyc_xor_624); -assign pyc_or_1158 = (pyc_and_1156 | pyc_and_1157); -assign pyc_and_1159 = (pyc_or_50 & pyc_xor_624); -assign pyc_or_1160 = (pyc_or_1158 | pyc_and_1159); -assign pyc_xor_1161 = (pyc_xor_1155 ^ pyc_or_611); -assign pyc_xor_1162 = (pyc_xor_1161 ^ pyc_or_1146); -assign pyc_and_1163 = (pyc_xor_1155 & pyc_or_611); -assign pyc_and_1164 = (pyc_xor_1155 & pyc_or_1146); -assign pyc_or_1165 = (pyc_and_1163 | pyc_and_1164); -assign pyc_and_1166 = (pyc_or_611 & pyc_or_1146); -assign pyc_or_1167 = (pyc_or_1165 | pyc_and_1166); -assign pyc_xor_1168 = (pyc_xor_81 ^ pyc_or_68); -assign pyc_xor_1169 = (pyc_xor_1168 ^ pyc_xor_642); -assign pyc_and_1170 = (pyc_xor_81 & pyc_or_68); -assign pyc_and_1171 = (pyc_xor_81 & pyc_xor_642); -assign pyc_or_1172 = (pyc_and_1170 | pyc_and_1171); -assign pyc_and_1173 = (pyc_or_68 & pyc_xor_642); -assign pyc_or_1174 = (pyc_or_1172 | pyc_and_1173); -assign pyc_xor_1175 = (pyc_xor_1169 ^ pyc_or_629); -assign pyc_xor_1176 = (pyc_xor_1175 ^ pyc_or_1160); -assign pyc_and_1177 = (pyc_xor_1169 & pyc_or_629); -assign pyc_and_1178 = (pyc_xor_1169 & pyc_or_1160); -assign pyc_or_1179 = (pyc_and_1177 | pyc_and_1178); -assign pyc_and_1180 = (pyc_or_629 & pyc_or_1160); -assign pyc_or_1181 = (pyc_or_1179 | pyc_and_1180); -assign pyc_xor_1182 = (pyc_xor_99 ^ pyc_or_86); -assign pyc_xor_1183 = (pyc_xor_1182 ^ pyc_xor_660); -assign pyc_and_1184 = (pyc_xor_99 & pyc_or_86); -assign pyc_and_1185 = (pyc_xor_99 & pyc_xor_660); -assign pyc_or_1186 = (pyc_and_1184 | pyc_and_1185); -assign pyc_and_1187 = (pyc_or_86 & pyc_xor_660); -assign pyc_or_1188 = (pyc_or_1186 | pyc_and_1187); -assign pyc_xor_1189 = (pyc_xor_1183 ^ pyc_or_647); -assign pyc_xor_1190 = (pyc_xor_1189 ^ pyc_or_1174); -assign pyc_and_1191 = (pyc_xor_1183 & pyc_or_647); -assign pyc_and_1192 = (pyc_xor_1183 & pyc_or_1174); -assign pyc_or_1193 = (pyc_and_1191 | pyc_and_1192); -assign pyc_and_1194 = (pyc_or_647 & pyc_or_1174); -assign pyc_or_1195 = (pyc_or_1193 | pyc_and_1194); -assign pyc_xor_1196 = (pyc_xor_117 ^ pyc_or_104); -assign pyc_xor_1197 = (pyc_xor_1196 ^ pyc_xor_678); -assign pyc_and_1198 = (pyc_xor_117 & pyc_or_104); -assign pyc_and_1199 = (pyc_xor_117 & pyc_xor_678); -assign pyc_or_1200 = (pyc_and_1198 | pyc_and_1199); -assign pyc_and_1201 = (pyc_or_104 & pyc_xor_678); -assign pyc_or_1202 = (pyc_or_1200 | pyc_and_1201); -assign pyc_xor_1203 = (pyc_xor_1197 ^ pyc_or_665); -assign pyc_xor_1204 = (pyc_xor_1203 ^ pyc_or_1188); -assign pyc_and_1205 = (pyc_xor_1197 & pyc_or_665); -assign pyc_and_1206 = (pyc_xor_1197 & pyc_or_1188); -assign pyc_or_1207 = (pyc_and_1205 | pyc_and_1206); -assign pyc_and_1208 = (pyc_or_665 & pyc_or_1188); -assign pyc_or_1209 = (pyc_or_1207 | pyc_and_1208); -assign pyc_xor_1210 = (pyc_xor_135 ^ pyc_or_122); -assign pyc_xor_1211 = (pyc_xor_1210 ^ pyc_xor_696); -assign pyc_and_1212 = (pyc_xor_135 & pyc_or_122); -assign pyc_and_1213 = (pyc_xor_135 & pyc_xor_696); -assign pyc_or_1214 = (pyc_and_1212 | pyc_and_1213); -assign pyc_and_1215 = (pyc_or_122 & pyc_xor_696); -assign pyc_or_1216 = (pyc_or_1214 | pyc_and_1215); -assign pyc_xor_1217 = (pyc_xor_1211 ^ pyc_or_683); -assign pyc_xor_1218 = (pyc_xor_1217 ^ pyc_or_1202); -assign pyc_and_1219 = (pyc_xor_1211 & pyc_or_683); -assign pyc_and_1220 = (pyc_xor_1211 & pyc_or_1202); -assign pyc_or_1221 = (pyc_and_1219 | pyc_and_1220); -assign pyc_and_1222 = (pyc_or_683 & pyc_or_1202); -assign pyc_or_1223 = (pyc_or_1221 | pyc_and_1222); -assign pyc_xor_1224 = (pyc_xor_153 ^ pyc_or_140); -assign pyc_xor_1225 = (pyc_xor_1224 ^ pyc_xor_714); -assign pyc_and_1226 = (pyc_xor_153 & pyc_or_140); -assign pyc_and_1227 = (pyc_xor_153 & pyc_xor_714); -assign pyc_or_1228 = (pyc_and_1226 | pyc_and_1227); -assign pyc_and_1229 = (pyc_or_140 & pyc_xor_714); -assign pyc_or_1230 = (pyc_or_1228 | pyc_and_1229); -assign pyc_xor_1231 = (pyc_xor_1225 ^ pyc_or_701); -assign pyc_xor_1232 = (pyc_xor_1231 ^ pyc_or_1216); -assign pyc_and_1233 = (pyc_xor_1225 & pyc_or_701); -assign pyc_and_1234 = (pyc_xor_1225 & pyc_or_1216); -assign pyc_or_1235 = (pyc_and_1233 | pyc_and_1234); -assign pyc_and_1236 = (pyc_or_701 & pyc_or_1216); -assign pyc_or_1237 = (pyc_or_1235 | pyc_and_1236); -assign pyc_xor_1238 = (pyc_xor_171 ^ pyc_or_158); -assign pyc_xor_1239 = (pyc_xor_1238 ^ pyc_xor_732); -assign pyc_and_1240 = (pyc_xor_171 & pyc_or_158); -assign pyc_and_1241 = (pyc_xor_171 & pyc_xor_732); -assign pyc_or_1242 = (pyc_and_1240 | pyc_and_1241); -assign pyc_and_1243 = (pyc_or_158 & pyc_xor_732); -assign pyc_or_1244 = (pyc_or_1242 | pyc_and_1243); -assign pyc_xor_1245 = (pyc_xor_1239 ^ pyc_or_719); -assign pyc_xor_1246 = (pyc_xor_1245 ^ pyc_or_1230); -assign pyc_and_1247 = (pyc_xor_1239 & pyc_or_719); -assign pyc_and_1248 = (pyc_xor_1239 & pyc_or_1230); -assign pyc_or_1249 = (pyc_and_1247 | pyc_and_1248); -assign pyc_and_1250 = (pyc_or_719 & pyc_or_1230); -assign pyc_or_1251 = (pyc_or_1249 | pyc_and_1250); -assign pyc_xor_1252 = (pyc_xor_189 ^ pyc_or_176); -assign pyc_xor_1253 = (pyc_xor_1252 ^ pyc_xor_750); -assign pyc_and_1254 = (pyc_xor_189 & pyc_or_176); -assign pyc_and_1255 = (pyc_xor_189 & pyc_xor_750); -assign pyc_or_1256 = (pyc_and_1254 | pyc_and_1255); -assign pyc_and_1257 = (pyc_or_176 & pyc_xor_750); -assign pyc_or_1258 = (pyc_or_1256 | pyc_and_1257); -assign pyc_xor_1259 = (pyc_xor_1253 ^ pyc_or_737); -assign pyc_xor_1260 = (pyc_xor_1259 ^ pyc_or_1244); -assign pyc_and_1261 = (pyc_xor_1253 & pyc_or_737); -assign pyc_and_1262 = (pyc_xor_1253 & pyc_or_1244); -assign pyc_or_1263 = (pyc_and_1261 | pyc_and_1262); -assign pyc_and_1264 = (pyc_or_737 & pyc_or_1244); -assign pyc_or_1265 = (pyc_or_1263 | pyc_and_1264); -assign pyc_xor_1266 = (pyc_xor_207 ^ pyc_or_194); -assign pyc_xor_1267 = (pyc_xor_1266 ^ pyc_xor_768); -assign pyc_and_1268 = (pyc_xor_207 & pyc_or_194); -assign pyc_and_1269 = (pyc_xor_207 & pyc_xor_768); -assign pyc_or_1270 = (pyc_and_1268 | pyc_and_1269); -assign pyc_and_1271 = (pyc_or_194 & pyc_xor_768); -assign pyc_or_1272 = (pyc_or_1270 | pyc_and_1271); -assign pyc_xor_1273 = (pyc_xor_1267 ^ pyc_or_755); -assign pyc_xor_1274 = (pyc_xor_1273 ^ pyc_or_1258); -assign pyc_and_1275 = (pyc_xor_1267 & pyc_or_755); -assign pyc_and_1276 = (pyc_xor_1267 & pyc_or_1258); -assign pyc_or_1277 = (pyc_and_1275 | pyc_and_1276); -assign pyc_and_1278 = (pyc_or_755 & pyc_or_1258); -assign pyc_or_1279 = (pyc_or_1277 | pyc_and_1278); -assign pyc_xor_1280 = (pyc_xor_225 ^ pyc_or_212); -assign pyc_xor_1281 = (pyc_xor_1280 ^ pyc_xor_786); -assign pyc_and_1282 = (pyc_xor_225 & pyc_or_212); -assign pyc_and_1283 = (pyc_xor_225 & pyc_xor_786); -assign pyc_or_1284 = (pyc_and_1282 | pyc_and_1283); -assign pyc_and_1285 = (pyc_or_212 & pyc_xor_786); -assign pyc_or_1286 = (pyc_or_1284 | pyc_and_1285); -assign pyc_xor_1287 = (pyc_xor_1281 ^ pyc_or_773); -assign pyc_xor_1288 = (pyc_xor_1287 ^ pyc_or_1272); -assign pyc_and_1289 = (pyc_xor_1281 & pyc_or_773); -assign pyc_and_1290 = (pyc_xor_1281 & pyc_or_1272); -assign pyc_or_1291 = (pyc_and_1289 | pyc_and_1290); -assign pyc_and_1292 = (pyc_or_773 & pyc_or_1272); -assign pyc_or_1293 = (pyc_or_1291 | pyc_and_1292); -assign pyc_xor_1294 = (pyc_xor_243 ^ pyc_or_230); -assign pyc_xor_1295 = (pyc_xor_1294 ^ pyc_xor_804); -assign pyc_and_1296 = (pyc_xor_243 & pyc_or_230); -assign pyc_and_1297 = (pyc_xor_243 & pyc_xor_804); -assign pyc_or_1298 = (pyc_and_1296 | pyc_and_1297); -assign pyc_and_1299 = (pyc_or_230 & pyc_xor_804); -assign pyc_or_1300 = (pyc_or_1298 | pyc_and_1299); -assign pyc_xor_1301 = (pyc_xor_1295 ^ pyc_or_791); -assign pyc_xor_1302 = (pyc_xor_1301 ^ pyc_or_1286); -assign pyc_and_1303 = (pyc_xor_1295 & pyc_or_791); -assign pyc_and_1304 = (pyc_xor_1295 & pyc_or_1286); -assign pyc_or_1305 = (pyc_and_1303 | pyc_and_1304); -assign pyc_and_1306 = (pyc_or_791 & pyc_or_1286); -assign pyc_or_1307 = (pyc_or_1305 | pyc_and_1306); -assign pyc_xor_1308 = (pyc_xor_261 ^ pyc_or_248); -assign pyc_xor_1309 = (pyc_xor_1308 ^ pyc_xor_822); -assign pyc_and_1310 = (pyc_xor_261 & pyc_or_248); -assign pyc_and_1311 = (pyc_xor_261 & pyc_xor_822); -assign pyc_or_1312 = (pyc_and_1310 | pyc_and_1311); -assign pyc_and_1313 = (pyc_or_248 & pyc_xor_822); -assign pyc_or_1314 = (pyc_or_1312 | pyc_and_1313); -assign pyc_xor_1315 = (pyc_xor_1309 ^ pyc_or_809); -assign pyc_xor_1316 = (pyc_xor_1315 ^ pyc_or_1300); -assign pyc_and_1317 = (pyc_xor_1309 & pyc_or_809); -assign pyc_and_1318 = (pyc_xor_1309 & pyc_or_1300); -assign pyc_or_1319 = (pyc_and_1317 | pyc_and_1318); -assign pyc_and_1320 = (pyc_or_809 & pyc_or_1300); -assign pyc_or_1321 = (pyc_or_1319 | pyc_and_1320); -assign pyc_xor_1322 = (pyc_xor_279 ^ pyc_or_266); -assign pyc_xor_1323 = (pyc_xor_1322 ^ pyc_xor_840); -assign pyc_and_1324 = (pyc_xor_279 & pyc_or_266); -assign pyc_and_1325 = (pyc_xor_279 & pyc_xor_840); -assign pyc_or_1326 = (pyc_and_1324 | pyc_and_1325); -assign pyc_and_1327 = (pyc_or_266 & pyc_xor_840); -assign pyc_or_1328 = (pyc_or_1326 | pyc_and_1327); -assign pyc_xor_1329 = (pyc_xor_1323 ^ pyc_or_827); -assign pyc_xor_1330 = (pyc_xor_1329 ^ pyc_or_1314); -assign pyc_and_1331 = (pyc_xor_1323 & pyc_or_827); -assign pyc_and_1332 = (pyc_xor_1323 & pyc_or_1314); -assign pyc_or_1333 = (pyc_and_1331 | pyc_and_1332); -assign pyc_and_1334 = (pyc_or_827 & pyc_or_1314); -assign pyc_or_1335 = (pyc_or_1333 | pyc_and_1334); -assign pyc_xor_1336 = (pyc_xor_297 ^ pyc_or_284); -assign pyc_xor_1337 = (pyc_xor_1336 ^ pyc_xor_858); -assign pyc_and_1338 = (pyc_xor_297 & pyc_or_284); -assign pyc_and_1339 = (pyc_xor_297 & pyc_xor_858); -assign pyc_or_1340 = (pyc_and_1338 | pyc_and_1339); -assign pyc_and_1341 = (pyc_or_284 & pyc_xor_858); -assign pyc_or_1342 = (pyc_or_1340 | pyc_and_1341); -assign pyc_xor_1343 = (pyc_xor_1337 ^ pyc_or_845); -assign pyc_xor_1344 = (pyc_xor_1343 ^ pyc_or_1328); -assign pyc_and_1345 = (pyc_xor_1337 & pyc_or_845); -assign pyc_and_1346 = (pyc_xor_1337 & pyc_or_1328); -assign pyc_or_1347 = (pyc_and_1345 | pyc_and_1346); -assign pyc_and_1348 = (pyc_or_845 & pyc_or_1328); -assign pyc_or_1349 = (pyc_or_1347 | pyc_and_1348); -assign pyc_xor_1350 = (pyc_xor_315 ^ pyc_or_302); -assign pyc_xor_1351 = (pyc_xor_1350 ^ pyc_xor_876); -assign pyc_and_1352 = (pyc_xor_315 & pyc_or_302); -assign pyc_and_1353 = (pyc_xor_315 & pyc_xor_876); -assign pyc_or_1354 = (pyc_and_1352 | pyc_and_1353); -assign pyc_and_1355 = (pyc_or_302 & pyc_xor_876); -assign pyc_or_1356 = (pyc_or_1354 | pyc_and_1355); -assign pyc_xor_1357 = (pyc_xor_1351 ^ pyc_or_863); -assign pyc_xor_1358 = (pyc_xor_1357 ^ pyc_or_1342); -assign pyc_and_1359 = (pyc_xor_1351 & pyc_or_863); -assign pyc_and_1360 = (pyc_xor_1351 & pyc_or_1342); -assign pyc_or_1361 = (pyc_and_1359 | pyc_and_1360); -assign pyc_and_1362 = (pyc_or_863 & pyc_or_1342); -assign pyc_or_1363 = (pyc_or_1361 | pyc_and_1362); -assign pyc_xor_1364 = (pyc_xor_333 ^ pyc_or_320); -assign pyc_xor_1365 = (pyc_xor_1364 ^ pyc_xor_894); -assign pyc_and_1366 = (pyc_xor_333 & pyc_or_320); -assign pyc_and_1367 = (pyc_xor_333 & pyc_xor_894); -assign pyc_or_1368 = (pyc_and_1366 | pyc_and_1367); -assign pyc_and_1369 = (pyc_or_320 & pyc_xor_894); -assign pyc_or_1370 = (pyc_or_1368 | pyc_and_1369); -assign pyc_xor_1371 = (pyc_xor_1365 ^ pyc_or_881); -assign pyc_xor_1372 = (pyc_xor_1371 ^ pyc_or_1356); -assign pyc_and_1373 = (pyc_xor_1365 & pyc_or_881); -assign pyc_and_1374 = (pyc_xor_1365 & pyc_or_1356); -assign pyc_or_1375 = (pyc_and_1373 | pyc_and_1374); -assign pyc_and_1376 = (pyc_or_881 & pyc_or_1356); -assign pyc_or_1377 = (pyc_or_1375 | pyc_and_1376); -assign pyc_xor_1378 = (pyc_xor_351 ^ pyc_or_338); -assign pyc_xor_1379 = (pyc_xor_1378 ^ pyc_xor_912); -assign pyc_and_1380 = (pyc_xor_351 & pyc_or_338); -assign pyc_and_1381 = (pyc_xor_351 & pyc_xor_912); -assign pyc_or_1382 = (pyc_and_1380 | pyc_and_1381); -assign pyc_and_1383 = (pyc_or_338 & pyc_xor_912); -assign pyc_or_1384 = (pyc_or_1382 | pyc_and_1383); -assign pyc_xor_1385 = (pyc_xor_1379 ^ pyc_or_899); -assign pyc_xor_1386 = (pyc_xor_1385 ^ pyc_or_1370); -assign pyc_and_1387 = (pyc_xor_1379 & pyc_or_899); -assign pyc_and_1388 = (pyc_xor_1379 & pyc_or_1370); -assign pyc_or_1389 = (pyc_and_1387 | pyc_and_1388); -assign pyc_and_1390 = (pyc_or_899 & pyc_or_1370); -assign pyc_or_1391 = (pyc_or_1389 | pyc_and_1390); -assign pyc_xor_1392 = (pyc_xor_369 ^ pyc_or_356); -assign pyc_xor_1393 = (pyc_xor_1392 ^ pyc_xor_930); -assign pyc_and_1394 = (pyc_xor_369 & pyc_or_356); -assign pyc_and_1395 = (pyc_xor_369 & pyc_xor_930); -assign pyc_or_1396 = (pyc_and_1394 | pyc_and_1395); -assign pyc_and_1397 = (pyc_or_356 & pyc_xor_930); -assign pyc_or_1398 = (pyc_or_1396 | pyc_and_1397); -assign pyc_xor_1399 = (pyc_xor_1393 ^ pyc_or_917); -assign pyc_xor_1400 = (pyc_xor_1399 ^ pyc_or_1384); -assign pyc_and_1401 = (pyc_xor_1393 & pyc_or_917); -assign pyc_and_1402 = (pyc_xor_1393 & pyc_or_1384); -assign pyc_or_1403 = (pyc_and_1401 | pyc_and_1402); -assign pyc_and_1404 = (pyc_or_917 & pyc_or_1384); -assign pyc_or_1405 = (pyc_or_1403 | pyc_and_1404); -assign pyc_xor_1406 = (pyc_xor_387 ^ pyc_or_374); -assign pyc_xor_1407 = (pyc_xor_1406 ^ pyc_xor_948); -assign pyc_and_1408 = (pyc_xor_387 & pyc_or_374); -assign pyc_and_1409 = (pyc_xor_387 & pyc_xor_948); -assign pyc_or_1410 = (pyc_and_1408 | pyc_and_1409); -assign pyc_and_1411 = (pyc_or_374 & pyc_xor_948); -assign pyc_or_1412 = (pyc_or_1410 | pyc_and_1411); -assign pyc_xor_1413 = (pyc_xor_1407 ^ pyc_or_935); -assign pyc_xor_1414 = (pyc_xor_1413 ^ pyc_or_1398); -assign pyc_and_1415 = (pyc_xor_1407 & pyc_or_935); -assign pyc_and_1416 = (pyc_xor_1407 & pyc_or_1398); -assign pyc_or_1417 = (pyc_and_1415 | pyc_and_1416); -assign pyc_and_1418 = (pyc_or_935 & pyc_or_1398); -assign pyc_or_1419 = (pyc_or_1417 | pyc_and_1418); -assign pyc_xor_1420 = (pyc_xor_405 ^ pyc_or_392); -assign pyc_xor_1421 = (pyc_xor_1420 ^ pyc_xor_966); -assign pyc_and_1422 = (pyc_xor_405 & pyc_or_392); -assign pyc_and_1423 = (pyc_xor_405 & pyc_xor_966); -assign pyc_or_1424 = (pyc_and_1422 | pyc_and_1423); -assign pyc_and_1425 = (pyc_or_392 & pyc_xor_966); -assign pyc_or_1426 = (pyc_or_1424 | pyc_and_1425); -assign pyc_xor_1427 = (pyc_xor_1421 ^ pyc_or_953); -assign pyc_xor_1428 = (pyc_xor_1427 ^ pyc_or_1412); -assign pyc_and_1429 = (pyc_xor_1421 & pyc_or_953); -assign pyc_and_1430 = (pyc_xor_1421 & pyc_or_1412); -assign pyc_or_1431 = (pyc_and_1429 | pyc_and_1430); -assign pyc_and_1432 = (pyc_or_953 & pyc_or_1412); -assign pyc_or_1433 = (pyc_or_1431 | pyc_and_1432); -assign pyc_xor_1434 = (pyc_xor_423 ^ pyc_or_410); -assign pyc_xor_1435 = (pyc_xor_1434 ^ pyc_xor_984); -assign pyc_and_1436 = (pyc_xor_423 & pyc_or_410); -assign pyc_and_1437 = (pyc_xor_423 & pyc_xor_984); -assign pyc_or_1438 = (pyc_and_1436 | pyc_and_1437); -assign pyc_and_1439 = (pyc_or_410 & pyc_xor_984); -assign pyc_or_1440 = (pyc_or_1438 | pyc_and_1439); -assign pyc_xor_1441 = (pyc_xor_1435 ^ pyc_or_971); -assign pyc_xor_1442 = (pyc_xor_1441 ^ pyc_or_1426); -assign pyc_and_1443 = (pyc_xor_1435 & pyc_or_971); -assign pyc_and_1444 = (pyc_xor_1435 & pyc_or_1426); -assign pyc_or_1445 = (pyc_and_1443 | pyc_and_1444); -assign pyc_and_1446 = (pyc_or_971 & pyc_or_1426); -assign pyc_or_1447 = (pyc_or_1445 | pyc_and_1446); -assign pyc_xor_1448 = (pyc_xor_441 ^ pyc_or_428); -assign pyc_xor_1449 = (pyc_xor_1448 ^ pyc_xor_1002); -assign pyc_and_1450 = (pyc_xor_441 & pyc_or_428); -assign pyc_and_1451 = (pyc_xor_441 & pyc_xor_1002); -assign pyc_or_1452 = (pyc_and_1450 | pyc_and_1451); -assign pyc_and_1453 = (pyc_or_428 & pyc_xor_1002); -assign pyc_or_1454 = (pyc_or_1452 | pyc_and_1453); -assign pyc_xor_1455 = (pyc_xor_1449 ^ pyc_or_989); -assign pyc_xor_1456 = (pyc_xor_1455 ^ pyc_or_1440); -assign pyc_and_1457 = (pyc_xor_1449 & pyc_or_989); -assign pyc_and_1458 = (pyc_xor_1449 & pyc_or_1440); -assign pyc_or_1459 = (pyc_and_1457 | pyc_and_1458); -assign pyc_and_1460 = (pyc_or_989 & pyc_or_1440); -assign pyc_or_1461 = (pyc_or_1459 | pyc_and_1460); -assign pyc_xor_1462 = (pyc_xor_459 ^ pyc_or_446); -assign pyc_xor_1463 = (pyc_xor_1462 ^ pyc_xor_1020); -assign pyc_and_1464 = (pyc_xor_459 & pyc_or_446); -assign pyc_and_1465 = (pyc_xor_459 & pyc_xor_1020); -assign pyc_or_1466 = (pyc_and_1464 | pyc_and_1465); -assign pyc_and_1467 = (pyc_or_446 & pyc_xor_1020); -assign pyc_or_1468 = (pyc_or_1466 | pyc_and_1467); -assign pyc_xor_1469 = (pyc_xor_1463 ^ pyc_or_1007); -assign pyc_xor_1470 = (pyc_xor_1469 ^ pyc_or_1454); -assign pyc_and_1471 = (pyc_xor_1463 & pyc_or_1007); -assign pyc_and_1472 = (pyc_xor_1463 & pyc_or_1454); -assign pyc_or_1473 = (pyc_and_1471 | pyc_and_1472); -assign pyc_and_1474 = (pyc_or_1007 & pyc_or_1454); -assign pyc_or_1475 = (pyc_or_1473 | pyc_and_1474); -assign pyc_xor_1476 = (pyc_xor_477 ^ pyc_or_464); -assign pyc_xor_1477 = (pyc_xor_1476 ^ pyc_xor_1038); -assign pyc_and_1478 = (pyc_xor_477 & pyc_or_464); -assign pyc_and_1479 = (pyc_xor_477 & pyc_xor_1038); -assign pyc_or_1480 = (pyc_and_1478 | pyc_and_1479); -assign pyc_and_1481 = (pyc_or_464 & pyc_xor_1038); -assign pyc_or_1482 = (pyc_or_1480 | pyc_and_1481); -assign pyc_xor_1483 = (pyc_xor_1477 ^ pyc_or_1025); -assign pyc_xor_1484 = (pyc_xor_1483 ^ pyc_or_1468); -assign pyc_and_1485 = (pyc_xor_1477 & pyc_or_1025); -assign pyc_and_1486 = (pyc_xor_1477 & pyc_or_1468); -assign pyc_or_1487 = (pyc_and_1485 | pyc_and_1486); -assign pyc_and_1488 = (pyc_or_1025 & pyc_or_1468); -assign pyc_or_1489 = (pyc_or_1487 | pyc_and_1488); -assign pyc_xor_1490 = (pyc_xor_495 ^ pyc_or_482); -assign pyc_xor_1491 = (pyc_xor_1490 ^ pyc_xor_1056); -assign pyc_and_1492 = (pyc_xor_495 & pyc_or_482); -assign pyc_and_1493 = (pyc_xor_495 & pyc_xor_1056); -assign pyc_or_1494 = (pyc_and_1492 | pyc_and_1493); -assign pyc_and_1495 = (pyc_or_482 & pyc_xor_1056); -assign pyc_or_1496 = (pyc_or_1494 | pyc_and_1495); -assign pyc_xor_1497 = (pyc_xor_1491 ^ pyc_or_1043); -assign pyc_xor_1498 = (pyc_xor_1497 ^ pyc_or_1482); -assign pyc_and_1499 = (pyc_xor_1491 & pyc_or_1043); -assign pyc_and_1500 = (pyc_xor_1491 & pyc_or_1482); -assign pyc_or_1501 = (pyc_and_1499 | pyc_and_1500); -assign pyc_and_1502 = (pyc_or_1043 & pyc_or_1482); -assign pyc_or_1503 = (pyc_or_1501 | pyc_and_1502); -assign pyc_xor_1504 = (pyc_xor_513 ^ pyc_or_500); -assign pyc_xor_1505 = (pyc_xor_1504 ^ pyc_xor_1074); -assign pyc_and_1506 = (pyc_xor_513 & pyc_or_500); -assign pyc_and_1507 = (pyc_xor_513 & pyc_xor_1074); -assign pyc_or_1508 = (pyc_and_1506 | pyc_and_1507); -assign pyc_and_1509 = (pyc_or_500 & pyc_xor_1074); -assign pyc_or_1510 = (pyc_or_1508 | pyc_and_1509); -assign pyc_xor_1511 = (pyc_xor_1505 ^ pyc_or_1061); -assign pyc_xor_1512 = (pyc_xor_1511 ^ pyc_or_1496); -assign pyc_and_1513 = (pyc_xor_1505 & pyc_or_1061); -assign pyc_and_1514 = (pyc_xor_1505 & pyc_or_1496); -assign pyc_or_1515 = (pyc_and_1513 | pyc_and_1514); -assign pyc_and_1516 = (pyc_or_1061 & pyc_or_1496); -assign pyc_or_1517 = (pyc_or_1515 | pyc_and_1516); -assign pyc_xor_1518 = (pyc_xor_531 ^ pyc_or_518); -assign pyc_xor_1519 = (pyc_xor_1518 ^ pyc_xor_1092); -assign pyc_and_1520 = (pyc_xor_531 & pyc_or_518); -assign pyc_and_1521 = (pyc_xor_531 & pyc_xor_1092); -assign pyc_or_1522 = (pyc_and_1520 | pyc_and_1521); -assign pyc_and_1523 = (pyc_or_518 & pyc_xor_1092); -assign pyc_or_1524 = (pyc_or_1522 | pyc_and_1523); -assign pyc_xor_1525 = (pyc_xor_1519 ^ pyc_or_1079); -assign pyc_xor_1526 = (pyc_xor_1525 ^ pyc_or_1510); -assign pyc_and_1527 = (pyc_xor_1519 & pyc_or_1079); -assign pyc_and_1528 = (pyc_xor_1519 & pyc_or_1510); -assign pyc_or_1529 = (pyc_and_1527 | pyc_and_1528); -assign pyc_and_1530 = (pyc_or_1079 & pyc_or_1510); -assign pyc_or_1531 = (pyc_or_1529 | pyc_and_1530); -assign pyc_xor_1532 = (pyc_xor_549 ^ pyc_or_536); -assign pyc_xor_1533 = (pyc_xor_1532 ^ pyc_xor_1110); -assign pyc_and_1534 = (pyc_xor_549 & pyc_or_536); -assign pyc_and_1535 = (pyc_xor_549 & pyc_xor_1110); -assign pyc_or_1536 = (pyc_and_1534 | pyc_and_1535); -assign pyc_and_1537 = (pyc_or_536 & pyc_xor_1110); -assign pyc_or_1538 = (pyc_or_1536 | pyc_and_1537); -assign pyc_xor_1539 = (pyc_xor_1533 ^ pyc_or_1097); -assign pyc_xor_1540 = (pyc_xor_1539 ^ pyc_or_1524); -assign pyc_and_1541 = (pyc_xor_1533 & pyc_or_1097); -assign pyc_and_1542 = (pyc_xor_1533 & pyc_or_1524); -assign pyc_or_1543 = (pyc_and_1541 | pyc_and_1542); -assign pyc_and_1544 = (pyc_or_1097 & pyc_or_1524); -assign pyc_or_1545 = (pyc_or_1543 | pyc_and_1544); -assign pyc_xor_1546 = (pyc_xor_562 ^ pyc_or_554); -assign pyc_xor_1547 = (pyc_xor_1546 ^ pyc_xor_1123); -assign pyc_xor_1548 = (pyc_xor_1547 ^ pyc_or_1115); -assign pyc_xor_1549 = (pyc_xor_1548 ^ pyc_or_1538); -assign pyc_concat_1550 = {pyc_xor_1549, pyc_xor_1540, pyc_xor_1526, pyc_xor_1512, pyc_xor_1498, pyc_xor_1484, pyc_xor_1470, pyc_xor_1456, pyc_xor_1442, pyc_xor_1428, pyc_xor_1414, pyc_xor_1400, pyc_xor_1386, pyc_xor_1372, pyc_xor_1358, pyc_xor_1344, pyc_xor_1330, pyc_xor_1316, pyc_xor_1302, pyc_xor_1288, pyc_xor_1274, pyc_xor_1260, pyc_xor_1246, pyc_xor_1232, pyc_xor_1218, pyc_xor_1204, pyc_xor_1190, pyc_xor_1176, pyc_xor_1162, pyc_xor_1148, pyc_xor_1134, pyc_xor_1124}; -assign pyc_concat_1551 = {pyc_or_1545, pyc_or_1531, pyc_or_1517, pyc_or_1503, pyc_or_1489, pyc_or_1475, pyc_or_1461, pyc_or_1447, pyc_or_1433, pyc_or_1419, pyc_or_1405, pyc_or_1391, pyc_or_1377, pyc_or_1363, pyc_or_1349, pyc_or_1335, pyc_or_1321, pyc_or_1307, pyc_or_1293, pyc_or_1279, pyc_or_1265, pyc_or_1251, pyc_or_1237, pyc_or_1223, pyc_or_1209, pyc_or_1195, pyc_or_1181, pyc_or_1167, pyc_or_1153, pyc_or_1139, pyc_constant_1, pyc_constant_1}; -assign pyc_add_1552 = (pyc_concat_1550 + pyc_concat_1551); -assign pyc_comb_1553 = pyc_add_1552; - -assign PE_INT_WALLACE_DOT8_TREE_sum = pyc_comb_1553; - -endmodule - diff --git a/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w16.v b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w16.v new file mode 100644 index 0000000..40eb07e --- /dev/null +++ b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w16.v @@ -0,0 +1,1528 @@ +// Generated by pycc (pyCircuit) +// Module: PE_INT_WALLACE_DOT8_TREE_W16 + +module PE_INT_WALLACE_DOT8_TREE_W16 ( + input [15:0] PE_INT_WALLACE_DOT8_TREE_W16_in0, + input [15:0] PE_INT_WALLACE_DOT8_TREE_W16_in1, + input [15:0] PE_INT_WALLACE_DOT8_TREE_W16_in2, + input [15:0] PE_INT_WALLACE_DOT8_TREE_W16_in3, + input [15:0] PE_INT_WALLACE_DOT8_TREE_W16_in4, + input [15:0] PE_INT_WALLACE_DOT8_TREE_W16_in5, + input [15:0] PE_INT_WALLACE_DOT8_TREE_W16_in6, + input [15:0] PE_INT_WALLACE_DOT8_TREE_W16_in7, + output [15:0] PE_INT_WALLACE_DOT8_TREE_W16_sum +); + +wire [15:0] pyc_add_752; // op=pyc.add +wire pyc_and_10; // op=pyc.and +wire pyc_and_100; // op=pyc.and +wire pyc_and_101; // op=pyc.and +wire pyc_and_103; // op=pyc.and +wire pyc_and_110; // op=pyc.and +wire pyc_and_111; // op=pyc.and +wire pyc_and_113; // op=pyc.and +wire pyc_and_118; // op=pyc.and +wire pyc_and_119; // op=pyc.and +wire pyc_and_121; // op=pyc.and +wire pyc_and_128; // op=pyc.and +wire pyc_and_129; // op=pyc.and +wire pyc_and_131; // op=pyc.and +wire pyc_and_136; // op=pyc.and +wire pyc_and_137; // op=pyc.and +wire pyc_and_139; // op=pyc.and +wire pyc_and_14; // op=pyc.and +wire pyc_and_146; // op=pyc.and +wire pyc_and_147; // op=pyc.and +wire pyc_and_149; // op=pyc.and +wire pyc_and_154; // op=pyc.and +wire pyc_and_155; // op=pyc.and +wire pyc_and_157; // op=pyc.and +wire pyc_and_164; // op=pyc.and +wire pyc_and_165; // op=pyc.and +wire pyc_and_167; // op=pyc.and +wire pyc_and_172; // op=pyc.and +wire pyc_and_173; // op=pyc.and +wire pyc_and_175; // op=pyc.and +wire pyc_and_182; // op=pyc.and +wire pyc_and_183; // op=pyc.and +wire pyc_and_185; // op=pyc.and +wire pyc_and_190; // op=pyc.and +wire pyc_and_191; // op=pyc.and +wire pyc_and_193; // op=pyc.and +wire pyc_and_20; // op=pyc.and +wire pyc_and_200; // op=pyc.and +wire pyc_and_201; // op=pyc.and +wire pyc_and_203; // op=pyc.and +wire pyc_and_208; // op=pyc.and +wire pyc_and_209; // op=pyc.and +wire pyc_and_21; // op=pyc.and +wire pyc_and_211; // op=pyc.and +wire pyc_and_218; // op=pyc.and +wire pyc_and_219; // op=pyc.and +wire pyc_and_221; // op=pyc.and +wire pyc_and_226; // op=pyc.and +wire pyc_and_227; // op=pyc.and +wire pyc_and_229; // op=pyc.and +wire pyc_and_23; // op=pyc.and +wire pyc_and_236; // op=pyc.and +wire pyc_and_237; // op=pyc.and +wire pyc_and_239; // op=pyc.and +wire pyc_and_244; // op=pyc.and +wire pyc_and_245; // op=pyc.and +wire pyc_and_247; // op=pyc.and +wire pyc_and_254; // op=pyc.and +wire pyc_and_255; // op=pyc.and +wire pyc_and_257; // op=pyc.and +wire pyc_and_262; // op=pyc.and +wire pyc_and_263; // op=pyc.and +wire pyc_and_265; // op=pyc.and +wire pyc_and_28; // op=pyc.and +wire pyc_and_280; // op=pyc.and +wire pyc_and_281; // op=pyc.and +wire pyc_and_283; // op=pyc.and +wire pyc_and_287; // op=pyc.and +wire pyc_and_29; // op=pyc.and +wire pyc_and_293; // op=pyc.and +wire pyc_and_294; // op=pyc.and +wire pyc_and_296; // op=pyc.and +wire pyc_and_301; // op=pyc.and +wire pyc_and_302; // op=pyc.and +wire pyc_and_304; // op=pyc.and +wire pyc_and_31; // op=pyc.and +wire pyc_and_311; // op=pyc.and +wire pyc_and_312; // op=pyc.and +wire pyc_and_314; // op=pyc.and +wire pyc_and_319; // op=pyc.and +wire pyc_and_320; // op=pyc.and +wire pyc_and_322; // op=pyc.and +wire pyc_and_329; // op=pyc.and +wire pyc_and_330; // op=pyc.and +wire pyc_and_332; // op=pyc.and +wire pyc_and_337; // op=pyc.and +wire pyc_and_338; // op=pyc.and +wire pyc_and_340; // op=pyc.and +wire pyc_and_347; // op=pyc.and +wire pyc_and_348; // op=pyc.and +wire pyc_and_350; // op=pyc.and +wire pyc_and_355; // op=pyc.and +wire pyc_and_356; // op=pyc.and +wire pyc_and_358; // op=pyc.and +wire pyc_and_365; // op=pyc.and +wire pyc_and_366; // op=pyc.and +wire pyc_and_368; // op=pyc.and +wire pyc_and_373; // op=pyc.and +wire pyc_and_374; // op=pyc.and +wire pyc_and_376; // op=pyc.and +wire pyc_and_38; // op=pyc.and +wire pyc_and_383; // op=pyc.and +wire pyc_and_384; // op=pyc.and +wire pyc_and_386; // op=pyc.and +wire pyc_and_39; // op=pyc.and +wire pyc_and_391; // op=pyc.and +wire pyc_and_392; // op=pyc.and +wire pyc_and_394; // op=pyc.and +wire pyc_and_401; // op=pyc.and +wire pyc_and_402; // op=pyc.and +wire pyc_and_404; // op=pyc.and +wire pyc_and_409; // op=pyc.and +wire pyc_and_41; // op=pyc.and +wire pyc_and_410; // op=pyc.and +wire pyc_and_412; // op=pyc.and +wire pyc_and_419; // op=pyc.and +wire pyc_and_420; // op=pyc.and +wire pyc_and_422; // op=pyc.and +wire pyc_and_427; // op=pyc.and +wire pyc_and_428; // op=pyc.and +wire pyc_and_430; // op=pyc.and +wire pyc_and_437; // op=pyc.and +wire pyc_and_438; // op=pyc.and +wire pyc_and_440; // op=pyc.and +wire pyc_and_445; // op=pyc.and +wire pyc_and_446; // op=pyc.and +wire pyc_and_448; // op=pyc.and +wire pyc_and_455; // op=pyc.and +wire pyc_and_456; // op=pyc.and +wire pyc_and_458; // op=pyc.and +wire pyc_and_46; // op=pyc.and +wire pyc_and_463; // op=pyc.and +wire pyc_and_464; // op=pyc.and +wire pyc_and_466; // op=pyc.and +wire pyc_and_47; // op=pyc.and +wire pyc_and_473; // op=pyc.and +wire pyc_and_474; // op=pyc.and +wire pyc_and_476; // op=pyc.and +wire pyc_and_481; // op=pyc.and +wire pyc_and_482; // op=pyc.and +wire pyc_and_484; // op=pyc.and +wire pyc_and_49; // op=pyc.and +wire pyc_and_491; // op=pyc.and +wire pyc_and_492; // op=pyc.and +wire pyc_and_494; // op=pyc.and +wire pyc_and_499; // op=pyc.and +wire pyc_and_500; // op=pyc.and +wire pyc_and_502; // op=pyc.and +wire pyc_and_509; // op=pyc.and +wire pyc_and_510; // op=pyc.and +wire pyc_and_512; // op=pyc.and +wire pyc_and_517; // op=pyc.and +wire pyc_and_518; // op=pyc.and +wire pyc_and_520; // op=pyc.and +wire pyc_and_527; // op=pyc.and +wire pyc_and_528; // op=pyc.and +wire pyc_and_530; // op=pyc.and +wire pyc_and_535; // op=pyc.and +wire pyc_and_536; // op=pyc.and +wire pyc_and_538; // op=pyc.and +wire pyc_and_549; // op=pyc.and +wire pyc_and_552; // op=pyc.and +wire pyc_and_553; // op=pyc.and +wire pyc_and_555; // op=pyc.and +wire pyc_and_559; // op=pyc.and +wire pyc_and_56; // op=pyc.and +wire pyc_and_560; // op=pyc.and +wire pyc_and_562; // op=pyc.and +wire pyc_and_566; // op=pyc.and +wire pyc_and_567; // op=pyc.and +wire pyc_and_569; // op=pyc.and +wire pyc_and_57; // op=pyc.and +wire pyc_and_573; // op=pyc.and +wire pyc_and_574; // op=pyc.and +wire pyc_and_576; // op=pyc.and +wire pyc_and_580; // op=pyc.and +wire pyc_and_581; // op=pyc.and +wire pyc_and_583; // op=pyc.and +wire pyc_and_587; // op=pyc.and +wire pyc_and_588; // op=pyc.and +wire pyc_and_59; // op=pyc.and +wire pyc_and_590; // op=pyc.and +wire pyc_and_594; // op=pyc.and +wire pyc_and_595; // op=pyc.and +wire pyc_and_597; // op=pyc.and +wire pyc_and_601; // op=pyc.and +wire pyc_and_602; // op=pyc.and +wire pyc_and_604; // op=pyc.and +wire pyc_and_608; // op=pyc.and +wire pyc_and_609; // op=pyc.and +wire pyc_and_611; // op=pyc.and +wire pyc_and_615; // op=pyc.and +wire pyc_and_616; // op=pyc.and +wire pyc_and_618; // op=pyc.and +wire pyc_and_622; // op=pyc.and +wire pyc_and_623; // op=pyc.and +wire pyc_and_625; // op=pyc.and +wire pyc_and_629; // op=pyc.and +wire pyc_and_630; // op=pyc.and +wire pyc_and_632; // op=pyc.and +wire pyc_and_636; // op=pyc.and +wire pyc_and_637; // op=pyc.and +wire pyc_and_639; // op=pyc.and +wire pyc_and_64; // op=pyc.and +wire pyc_and_643; // op=pyc.and +wire pyc_and_644; // op=pyc.and +wire pyc_and_646; // op=pyc.and +wire pyc_and_65; // op=pyc.and +wire pyc_and_650; // op=pyc.and +wire pyc_and_651; // op=pyc.and +wire pyc_and_653; // op=pyc.and +wire pyc_and_657; // op=pyc.and +wire pyc_and_658; // op=pyc.and +wire pyc_and_660; // op=pyc.and +wire pyc_and_664; // op=pyc.and +wire pyc_and_665; // op=pyc.and +wire pyc_and_667; // op=pyc.and +wire pyc_and_67; // op=pyc.and +wire pyc_and_671; // op=pyc.and +wire pyc_and_672; // op=pyc.and +wire pyc_and_674; // op=pyc.and +wire pyc_and_678; // op=pyc.and +wire pyc_and_679; // op=pyc.and +wire pyc_and_681; // op=pyc.and +wire pyc_and_685; // op=pyc.and +wire pyc_and_686; // op=pyc.and +wire pyc_and_688; // op=pyc.and +wire pyc_and_692; // op=pyc.and +wire pyc_and_693; // op=pyc.and +wire pyc_and_695; // op=pyc.and +wire pyc_and_699; // op=pyc.and +wire pyc_and_7; // op=pyc.and +wire pyc_and_700; // op=pyc.and +wire pyc_and_702; // op=pyc.and +wire pyc_and_706; // op=pyc.and +wire pyc_and_707; // op=pyc.and +wire pyc_and_709; // op=pyc.and +wire pyc_and_713; // op=pyc.and +wire pyc_and_714; // op=pyc.and +wire pyc_and_716; // op=pyc.and +wire pyc_and_720; // op=pyc.and +wire pyc_and_721; // op=pyc.and +wire pyc_and_723; // op=pyc.and +wire pyc_and_727; // op=pyc.and +wire pyc_and_728; // op=pyc.and +wire pyc_and_730; // op=pyc.and +wire pyc_and_734; // op=pyc.and +wire pyc_and_735; // op=pyc.and +wire pyc_and_737; // op=pyc.and +wire pyc_and_74; // op=pyc.and +wire pyc_and_741; // op=pyc.and +wire pyc_and_742; // op=pyc.and +wire pyc_and_744; // op=pyc.and +wire pyc_and_75; // op=pyc.and +wire pyc_and_77; // op=pyc.and +wire pyc_and_8; // op=pyc.and +wire pyc_and_82; // op=pyc.and +wire pyc_and_83; // op=pyc.and +wire pyc_and_85; // op=pyc.and +wire pyc_and_92; // op=pyc.and +wire pyc_and_93; // op=pyc.and +wire pyc_and_95; // op=pyc.and +wire [15:0] pyc_comb_753; // op=pyc.comb +wire [15:0] pyc_concat_750; // op=pyc.concat +wire [15:0] pyc_concat_751; // op=pyc.concat +wire pyc_constant_1; // op=pyc.constant +wire pyc_extract_105; // op=pyc.extract +wire pyc_extract_106; // op=pyc.extract +wire pyc_extract_107; // op=pyc.extract +wire pyc_extract_115; // op=pyc.extract +wire pyc_extract_12; // op=pyc.extract +wire pyc_extract_123; // op=pyc.extract +wire pyc_extract_124; // op=pyc.extract +wire pyc_extract_125; // op=pyc.extract +wire pyc_extract_133; // op=pyc.extract +wire pyc_extract_141; // op=pyc.extract +wire pyc_extract_142; // op=pyc.extract +wire pyc_extract_143; // op=pyc.extract +wire pyc_extract_15; // op=pyc.extract +wire pyc_extract_151; // op=pyc.extract +wire pyc_extract_159; // op=pyc.extract +wire pyc_extract_16; // op=pyc.extract +wire pyc_extract_160; // op=pyc.extract +wire pyc_extract_161; // op=pyc.extract +wire pyc_extract_169; // op=pyc.extract +wire pyc_extract_17; // op=pyc.extract +wire pyc_extract_177; // op=pyc.extract +wire pyc_extract_178; // op=pyc.extract +wire pyc_extract_179; // op=pyc.extract +wire pyc_extract_187; // op=pyc.extract +wire pyc_extract_195; // op=pyc.extract +wire pyc_extract_196; // op=pyc.extract +wire pyc_extract_197; // op=pyc.extract +wire pyc_extract_2; // op=pyc.extract +wire pyc_extract_205; // op=pyc.extract +wire pyc_extract_213; // op=pyc.extract +wire pyc_extract_214; // op=pyc.extract +wire pyc_extract_215; // op=pyc.extract +wire pyc_extract_223; // op=pyc.extract +wire pyc_extract_231; // op=pyc.extract +wire pyc_extract_232; // op=pyc.extract +wire pyc_extract_233; // op=pyc.extract +wire pyc_extract_241; // op=pyc.extract +wire pyc_extract_249; // op=pyc.extract +wire pyc_extract_25; // op=pyc.extract +wire pyc_extract_250; // op=pyc.extract +wire pyc_extract_251; // op=pyc.extract +wire pyc_extract_259; // op=pyc.extract +wire pyc_extract_267; // op=pyc.extract +wire pyc_extract_268; // op=pyc.extract +wire pyc_extract_269; // op=pyc.extract +wire pyc_extract_272; // op=pyc.extract +wire pyc_extract_275; // op=pyc.extract +wire pyc_extract_276; // op=pyc.extract +wire pyc_extract_277; // op=pyc.extract +wire pyc_extract_285; // op=pyc.extract +wire pyc_extract_288; // op=pyc.extract +wire pyc_extract_289; // op=pyc.extract +wire pyc_extract_290; // op=pyc.extract +wire pyc_extract_298; // op=pyc.extract +wire pyc_extract_3; // op=pyc.extract +wire pyc_extract_306; // op=pyc.extract +wire pyc_extract_307; // op=pyc.extract +wire pyc_extract_308; // op=pyc.extract +wire pyc_extract_316; // op=pyc.extract +wire pyc_extract_324; // op=pyc.extract +wire pyc_extract_325; // op=pyc.extract +wire pyc_extract_326; // op=pyc.extract +wire pyc_extract_33; // op=pyc.extract +wire pyc_extract_334; // op=pyc.extract +wire pyc_extract_34; // op=pyc.extract +wire pyc_extract_342; // op=pyc.extract +wire pyc_extract_343; // op=pyc.extract +wire pyc_extract_344; // op=pyc.extract +wire pyc_extract_35; // op=pyc.extract +wire pyc_extract_352; // op=pyc.extract +wire pyc_extract_360; // op=pyc.extract +wire pyc_extract_361; // op=pyc.extract +wire pyc_extract_362; // op=pyc.extract +wire pyc_extract_370; // op=pyc.extract +wire pyc_extract_378; // op=pyc.extract +wire pyc_extract_379; // op=pyc.extract +wire pyc_extract_380; // op=pyc.extract +wire pyc_extract_388; // op=pyc.extract +wire pyc_extract_396; // op=pyc.extract +wire pyc_extract_397; // op=pyc.extract +wire pyc_extract_398; // op=pyc.extract +wire pyc_extract_4; // op=pyc.extract +wire pyc_extract_406; // op=pyc.extract +wire pyc_extract_414; // op=pyc.extract +wire pyc_extract_415; // op=pyc.extract +wire pyc_extract_416; // op=pyc.extract +wire pyc_extract_424; // op=pyc.extract +wire pyc_extract_43; // op=pyc.extract +wire pyc_extract_432; // op=pyc.extract +wire pyc_extract_433; // op=pyc.extract +wire pyc_extract_434; // op=pyc.extract +wire pyc_extract_442; // op=pyc.extract +wire pyc_extract_450; // op=pyc.extract +wire pyc_extract_451; // op=pyc.extract +wire pyc_extract_452; // op=pyc.extract +wire pyc_extract_460; // op=pyc.extract +wire pyc_extract_468; // op=pyc.extract +wire pyc_extract_469; // op=pyc.extract +wire pyc_extract_470; // op=pyc.extract +wire pyc_extract_478; // op=pyc.extract +wire pyc_extract_486; // op=pyc.extract +wire pyc_extract_487; // op=pyc.extract +wire pyc_extract_488; // op=pyc.extract +wire pyc_extract_496; // op=pyc.extract +wire pyc_extract_504; // op=pyc.extract +wire pyc_extract_505; // op=pyc.extract +wire pyc_extract_506; // op=pyc.extract +wire pyc_extract_51; // op=pyc.extract +wire pyc_extract_514; // op=pyc.extract +wire pyc_extract_52; // op=pyc.extract +wire pyc_extract_522; // op=pyc.extract +wire pyc_extract_523; // op=pyc.extract +wire pyc_extract_524; // op=pyc.extract +wire pyc_extract_53; // op=pyc.extract +wire pyc_extract_532; // op=pyc.extract +wire pyc_extract_540; // op=pyc.extract +wire pyc_extract_541; // op=pyc.extract +wire pyc_extract_542; // op=pyc.extract +wire pyc_extract_545; // op=pyc.extract +wire pyc_extract_61; // op=pyc.extract +wire pyc_extract_69; // op=pyc.extract +wire pyc_extract_70; // op=pyc.extract +wire pyc_extract_71; // op=pyc.extract +wire pyc_extract_79; // op=pyc.extract +wire pyc_extract_87; // op=pyc.extract +wire pyc_extract_88; // op=pyc.extract +wire pyc_extract_89; // op=pyc.extract +wire pyc_extract_97; // op=pyc.extract +wire pyc_or_102; // op=pyc.or +wire pyc_or_104; // op=pyc.or +wire pyc_or_11; // op=pyc.or +wire pyc_or_112; // op=pyc.or +wire pyc_or_114; // op=pyc.or +wire pyc_or_120; // op=pyc.or +wire pyc_or_122; // op=pyc.or +wire pyc_or_130; // op=pyc.or +wire pyc_or_132; // op=pyc.or +wire pyc_or_138; // op=pyc.or +wire pyc_or_140; // op=pyc.or +wire pyc_or_148; // op=pyc.or +wire pyc_or_150; // op=pyc.or +wire pyc_or_156; // op=pyc.or +wire pyc_or_158; // op=pyc.or +wire pyc_or_166; // op=pyc.or +wire pyc_or_168; // op=pyc.or +wire pyc_or_174; // op=pyc.or +wire pyc_or_176; // op=pyc.or +wire pyc_or_184; // op=pyc.or +wire pyc_or_186; // op=pyc.or +wire pyc_or_192; // op=pyc.or +wire pyc_or_194; // op=pyc.or +wire pyc_or_202; // op=pyc.or +wire pyc_or_204; // op=pyc.or +wire pyc_or_210; // op=pyc.or +wire pyc_or_212; // op=pyc.or +wire pyc_or_22; // op=pyc.or +wire pyc_or_220; // op=pyc.or +wire pyc_or_222; // op=pyc.or +wire pyc_or_228; // op=pyc.or +wire pyc_or_230; // op=pyc.or +wire pyc_or_238; // op=pyc.or +wire pyc_or_24; // op=pyc.or +wire pyc_or_240; // op=pyc.or +wire pyc_or_246; // op=pyc.or +wire pyc_or_248; // op=pyc.or +wire pyc_or_256; // op=pyc.or +wire pyc_or_258; // op=pyc.or +wire pyc_or_264; // op=pyc.or +wire pyc_or_266; // op=pyc.or +wire pyc_or_282; // op=pyc.or +wire pyc_or_284; // op=pyc.or +wire pyc_or_295; // op=pyc.or +wire pyc_or_297; // op=pyc.or +wire pyc_or_30; // op=pyc.or +wire pyc_or_303; // op=pyc.or +wire pyc_or_305; // op=pyc.or +wire pyc_or_313; // op=pyc.or +wire pyc_or_315; // op=pyc.or +wire pyc_or_32; // op=pyc.or +wire pyc_or_321; // op=pyc.or +wire pyc_or_323; // op=pyc.or +wire pyc_or_331; // op=pyc.or +wire pyc_or_333; // op=pyc.or +wire pyc_or_339; // op=pyc.or +wire pyc_or_341; // op=pyc.or +wire pyc_or_349; // op=pyc.or +wire pyc_or_351; // op=pyc.or +wire pyc_or_357; // op=pyc.or +wire pyc_or_359; // op=pyc.or +wire pyc_or_367; // op=pyc.or +wire pyc_or_369; // op=pyc.or +wire pyc_or_375; // op=pyc.or +wire pyc_or_377; // op=pyc.or +wire pyc_or_385; // op=pyc.or +wire pyc_or_387; // op=pyc.or +wire pyc_or_393; // op=pyc.or +wire pyc_or_395; // op=pyc.or +wire pyc_or_40; // op=pyc.or +wire pyc_or_403; // op=pyc.or +wire pyc_or_405; // op=pyc.or +wire pyc_or_411; // op=pyc.or +wire pyc_or_413; // op=pyc.or +wire pyc_or_42; // op=pyc.or +wire pyc_or_421; // op=pyc.or +wire pyc_or_423; // op=pyc.or +wire pyc_or_429; // op=pyc.or +wire pyc_or_431; // op=pyc.or +wire pyc_or_439; // op=pyc.or +wire pyc_or_441; // op=pyc.or +wire pyc_or_447; // op=pyc.or +wire pyc_or_449; // op=pyc.or +wire pyc_or_457; // op=pyc.or +wire pyc_or_459; // op=pyc.or +wire pyc_or_465; // op=pyc.or +wire pyc_or_467; // op=pyc.or +wire pyc_or_475; // op=pyc.or +wire pyc_or_477; // op=pyc.or +wire pyc_or_48; // op=pyc.or +wire pyc_or_483; // op=pyc.or +wire pyc_or_485; // op=pyc.or +wire pyc_or_493; // op=pyc.or +wire pyc_or_495; // op=pyc.or +wire pyc_or_50; // op=pyc.or +wire pyc_or_501; // op=pyc.or +wire pyc_or_503; // op=pyc.or +wire pyc_or_511; // op=pyc.or +wire pyc_or_513; // op=pyc.or +wire pyc_or_519; // op=pyc.or +wire pyc_or_521; // op=pyc.or +wire pyc_or_529; // op=pyc.or +wire pyc_or_531; // op=pyc.or +wire pyc_or_537; // op=pyc.or +wire pyc_or_539; // op=pyc.or +wire pyc_or_554; // op=pyc.or +wire pyc_or_556; // op=pyc.or +wire pyc_or_561; // op=pyc.or +wire pyc_or_563; // op=pyc.or +wire pyc_or_568; // op=pyc.or +wire pyc_or_570; // op=pyc.or +wire pyc_or_575; // op=pyc.or +wire pyc_or_577; // op=pyc.or +wire pyc_or_58; // op=pyc.or +wire pyc_or_582; // op=pyc.or +wire pyc_or_584; // op=pyc.or +wire pyc_or_589; // op=pyc.or +wire pyc_or_591; // op=pyc.or +wire pyc_or_596; // op=pyc.or +wire pyc_or_598; // op=pyc.or +wire pyc_or_60; // op=pyc.or +wire pyc_or_603; // op=pyc.or +wire pyc_or_605; // op=pyc.or +wire pyc_or_610; // op=pyc.or +wire pyc_or_612; // op=pyc.or +wire pyc_or_617; // op=pyc.or +wire pyc_or_619; // op=pyc.or +wire pyc_or_624; // op=pyc.or +wire pyc_or_626; // op=pyc.or +wire pyc_or_631; // op=pyc.or +wire pyc_or_633; // op=pyc.or +wire pyc_or_638; // op=pyc.or +wire pyc_or_640; // op=pyc.or +wire pyc_or_645; // op=pyc.or +wire pyc_or_647; // op=pyc.or +wire pyc_or_652; // op=pyc.or +wire pyc_or_654; // op=pyc.or +wire pyc_or_659; // op=pyc.or +wire pyc_or_66; // op=pyc.or +wire pyc_or_661; // op=pyc.or +wire pyc_or_666; // op=pyc.or +wire pyc_or_668; // op=pyc.or +wire pyc_or_673; // op=pyc.or +wire pyc_or_675; // op=pyc.or +wire pyc_or_68; // op=pyc.or +wire pyc_or_680; // op=pyc.or +wire pyc_or_682; // op=pyc.or +wire pyc_or_687; // op=pyc.or +wire pyc_or_689; // op=pyc.or +wire pyc_or_694; // op=pyc.or +wire pyc_or_696; // op=pyc.or +wire pyc_or_701; // op=pyc.or +wire pyc_or_703; // op=pyc.or +wire pyc_or_708; // op=pyc.or +wire pyc_or_710; // op=pyc.or +wire pyc_or_715; // op=pyc.or +wire pyc_or_717; // op=pyc.or +wire pyc_or_722; // op=pyc.or +wire pyc_or_724; // op=pyc.or +wire pyc_or_729; // op=pyc.or +wire pyc_or_731; // op=pyc.or +wire pyc_or_736; // op=pyc.or +wire pyc_or_738; // op=pyc.or +wire pyc_or_743; // op=pyc.or +wire pyc_or_745; // op=pyc.or +wire pyc_or_76; // op=pyc.or +wire pyc_or_78; // op=pyc.or +wire pyc_or_84; // op=pyc.or +wire pyc_or_86; // op=pyc.or +wire pyc_or_9; // op=pyc.or +wire pyc_or_94; // op=pyc.or +wire pyc_or_96; // op=pyc.or +wire pyc_xor_108; // op=pyc.xor +wire pyc_xor_109; // op=pyc.xor +wire pyc_xor_116; // op=pyc.xor +wire pyc_xor_117; // op=pyc.xor +wire pyc_xor_126; // op=pyc.xor +wire pyc_xor_127; // op=pyc.xor +wire pyc_xor_13; // op=pyc.xor +wire pyc_xor_134; // op=pyc.xor +wire pyc_xor_135; // op=pyc.xor +wire pyc_xor_144; // op=pyc.xor +wire pyc_xor_145; // op=pyc.xor +wire pyc_xor_152; // op=pyc.xor +wire pyc_xor_153; // op=pyc.xor +wire pyc_xor_162; // op=pyc.xor +wire pyc_xor_163; // op=pyc.xor +wire pyc_xor_170; // op=pyc.xor +wire pyc_xor_171; // op=pyc.xor +wire pyc_xor_18; // op=pyc.xor +wire pyc_xor_180; // op=pyc.xor +wire pyc_xor_181; // op=pyc.xor +wire pyc_xor_188; // op=pyc.xor +wire pyc_xor_189; // op=pyc.xor +wire pyc_xor_19; // op=pyc.xor +wire pyc_xor_198; // op=pyc.xor +wire pyc_xor_199; // op=pyc.xor +wire pyc_xor_206; // op=pyc.xor +wire pyc_xor_207; // op=pyc.xor +wire pyc_xor_216; // op=pyc.xor +wire pyc_xor_217; // op=pyc.xor +wire pyc_xor_224; // op=pyc.xor +wire pyc_xor_225; // op=pyc.xor +wire pyc_xor_234; // op=pyc.xor +wire pyc_xor_235; // op=pyc.xor +wire pyc_xor_242; // op=pyc.xor +wire pyc_xor_243; // op=pyc.xor +wire pyc_xor_252; // op=pyc.xor +wire pyc_xor_253; // op=pyc.xor +wire pyc_xor_26; // op=pyc.xor +wire pyc_xor_260; // op=pyc.xor +wire pyc_xor_261; // op=pyc.xor +wire pyc_xor_27; // op=pyc.xor +wire pyc_xor_270; // op=pyc.xor +wire pyc_xor_271; // op=pyc.xor +wire pyc_xor_273; // op=pyc.xor +wire pyc_xor_274; // op=pyc.xor +wire pyc_xor_278; // op=pyc.xor +wire pyc_xor_279; // op=pyc.xor +wire pyc_xor_286; // op=pyc.xor +wire pyc_xor_291; // op=pyc.xor +wire pyc_xor_292; // op=pyc.xor +wire pyc_xor_299; // op=pyc.xor +wire pyc_xor_300; // op=pyc.xor +wire pyc_xor_309; // op=pyc.xor +wire pyc_xor_310; // op=pyc.xor +wire pyc_xor_317; // op=pyc.xor +wire pyc_xor_318; // op=pyc.xor +wire pyc_xor_327; // op=pyc.xor +wire pyc_xor_328; // op=pyc.xor +wire pyc_xor_335; // op=pyc.xor +wire pyc_xor_336; // op=pyc.xor +wire pyc_xor_345; // op=pyc.xor +wire pyc_xor_346; // op=pyc.xor +wire pyc_xor_353; // op=pyc.xor +wire pyc_xor_354; // op=pyc.xor +wire pyc_xor_36; // op=pyc.xor +wire pyc_xor_363; // op=pyc.xor +wire pyc_xor_364; // op=pyc.xor +wire pyc_xor_37; // op=pyc.xor +wire pyc_xor_371; // op=pyc.xor +wire pyc_xor_372; // op=pyc.xor +wire pyc_xor_381; // op=pyc.xor +wire pyc_xor_382; // op=pyc.xor +wire pyc_xor_389; // op=pyc.xor +wire pyc_xor_390; // op=pyc.xor +wire pyc_xor_399; // op=pyc.xor +wire pyc_xor_400; // op=pyc.xor +wire pyc_xor_407; // op=pyc.xor +wire pyc_xor_408; // op=pyc.xor +wire pyc_xor_417; // op=pyc.xor +wire pyc_xor_418; // op=pyc.xor +wire pyc_xor_425; // op=pyc.xor +wire pyc_xor_426; // op=pyc.xor +wire pyc_xor_435; // op=pyc.xor +wire pyc_xor_436; // op=pyc.xor +wire pyc_xor_44; // op=pyc.xor +wire pyc_xor_443; // op=pyc.xor +wire pyc_xor_444; // op=pyc.xor +wire pyc_xor_45; // op=pyc.xor +wire pyc_xor_453; // op=pyc.xor +wire pyc_xor_454; // op=pyc.xor +wire pyc_xor_461; // op=pyc.xor +wire pyc_xor_462; // op=pyc.xor +wire pyc_xor_471; // op=pyc.xor +wire pyc_xor_472; // op=pyc.xor +wire pyc_xor_479; // op=pyc.xor +wire pyc_xor_480; // op=pyc.xor +wire pyc_xor_489; // op=pyc.xor +wire pyc_xor_490; // op=pyc.xor +wire pyc_xor_497; // op=pyc.xor +wire pyc_xor_498; // op=pyc.xor +wire pyc_xor_5; // op=pyc.xor +wire pyc_xor_507; // op=pyc.xor +wire pyc_xor_508; // op=pyc.xor +wire pyc_xor_515; // op=pyc.xor +wire pyc_xor_516; // op=pyc.xor +wire pyc_xor_525; // op=pyc.xor +wire pyc_xor_526; // op=pyc.xor +wire pyc_xor_533; // op=pyc.xor +wire pyc_xor_534; // op=pyc.xor +wire pyc_xor_54; // op=pyc.xor +wire pyc_xor_543; // op=pyc.xor +wire pyc_xor_544; // op=pyc.xor +wire pyc_xor_546; // op=pyc.xor +wire pyc_xor_547; // op=pyc.xor +wire pyc_xor_548; // op=pyc.xor +wire pyc_xor_55; // op=pyc.xor +wire pyc_xor_550; // op=pyc.xor +wire pyc_xor_551; // op=pyc.xor +wire pyc_xor_557; // op=pyc.xor +wire pyc_xor_558; // op=pyc.xor +wire pyc_xor_564; // op=pyc.xor +wire pyc_xor_565; // op=pyc.xor +wire pyc_xor_571; // op=pyc.xor +wire pyc_xor_572; // op=pyc.xor +wire pyc_xor_578; // op=pyc.xor +wire pyc_xor_579; // op=pyc.xor +wire pyc_xor_585; // op=pyc.xor +wire pyc_xor_586; // op=pyc.xor +wire pyc_xor_592; // op=pyc.xor +wire pyc_xor_593; // op=pyc.xor +wire pyc_xor_599; // op=pyc.xor +wire pyc_xor_6; // op=pyc.xor +wire pyc_xor_600; // op=pyc.xor +wire pyc_xor_606; // op=pyc.xor +wire pyc_xor_607; // op=pyc.xor +wire pyc_xor_613; // op=pyc.xor +wire pyc_xor_614; // op=pyc.xor +wire pyc_xor_62; // op=pyc.xor +wire pyc_xor_620; // op=pyc.xor +wire pyc_xor_621; // op=pyc.xor +wire pyc_xor_627; // op=pyc.xor +wire pyc_xor_628; // op=pyc.xor +wire pyc_xor_63; // op=pyc.xor +wire pyc_xor_634; // op=pyc.xor +wire pyc_xor_635; // op=pyc.xor +wire pyc_xor_641; // op=pyc.xor +wire pyc_xor_642; // op=pyc.xor +wire pyc_xor_648; // op=pyc.xor +wire pyc_xor_649; // op=pyc.xor +wire pyc_xor_655; // op=pyc.xor +wire pyc_xor_656; // op=pyc.xor +wire pyc_xor_662; // op=pyc.xor +wire pyc_xor_663; // op=pyc.xor +wire pyc_xor_669; // op=pyc.xor +wire pyc_xor_670; // op=pyc.xor +wire pyc_xor_676; // op=pyc.xor +wire pyc_xor_677; // op=pyc.xor +wire pyc_xor_683; // op=pyc.xor +wire pyc_xor_684; // op=pyc.xor +wire pyc_xor_690; // op=pyc.xor +wire pyc_xor_691; // op=pyc.xor +wire pyc_xor_697; // op=pyc.xor +wire pyc_xor_698; // op=pyc.xor +wire pyc_xor_704; // op=pyc.xor +wire pyc_xor_705; // op=pyc.xor +wire pyc_xor_711; // op=pyc.xor +wire pyc_xor_712; // op=pyc.xor +wire pyc_xor_718; // op=pyc.xor +wire pyc_xor_719; // op=pyc.xor +wire pyc_xor_72; // op=pyc.xor +wire pyc_xor_725; // op=pyc.xor +wire pyc_xor_726; // op=pyc.xor +wire pyc_xor_73; // op=pyc.xor +wire pyc_xor_732; // op=pyc.xor +wire pyc_xor_733; // op=pyc.xor +wire pyc_xor_739; // op=pyc.xor +wire pyc_xor_740; // op=pyc.xor +wire pyc_xor_746; // op=pyc.xor +wire pyc_xor_747; // op=pyc.xor +wire pyc_xor_748; // op=pyc.xor +wire pyc_xor_749; // op=pyc.xor +wire pyc_xor_80; // op=pyc.xor +wire pyc_xor_81; // op=pyc.xor +wire pyc_xor_90; // op=pyc.xor +wire pyc_xor_91; // op=pyc.xor +wire pyc_xor_98; // op=pyc.xor +wire pyc_xor_99; // op=pyc.xor + +// --- Combinational (netlist) +assign pyc_constant_1 = 1'd0; +assign pyc_extract_2 = PE_INT_WALLACE_DOT8_TREE_W16_in0[0]; +assign pyc_extract_3 = PE_INT_WALLACE_DOT8_TREE_W16_in1[0]; +assign pyc_extract_4 = PE_INT_WALLACE_DOT8_TREE_W16_in2[0]; +assign pyc_xor_5 = (pyc_extract_2 ^ pyc_extract_3); +assign pyc_xor_6 = (pyc_xor_5 ^ pyc_extract_4); +assign pyc_and_7 = (pyc_extract_2 & pyc_extract_3); +assign pyc_and_8 = (pyc_extract_2 & pyc_extract_4); +assign pyc_or_9 = (pyc_and_7 | pyc_and_8); +assign pyc_and_10 = (pyc_extract_3 & pyc_extract_4); +assign pyc_or_11 = (pyc_or_9 | pyc_and_10); +assign pyc_extract_12 = PE_INT_WALLACE_DOT8_TREE_W16_in3[0]; +assign pyc_xor_13 = (pyc_xor_6 ^ pyc_extract_12); +assign pyc_and_14 = (pyc_xor_6 & pyc_extract_12); +assign pyc_extract_15 = PE_INT_WALLACE_DOT8_TREE_W16_in0[1]; +assign pyc_extract_16 = PE_INT_WALLACE_DOT8_TREE_W16_in1[1]; +assign pyc_extract_17 = PE_INT_WALLACE_DOT8_TREE_W16_in2[1]; +assign pyc_xor_18 = (pyc_extract_15 ^ pyc_extract_16); +assign pyc_xor_19 = (pyc_xor_18 ^ pyc_extract_17); +assign pyc_and_20 = (pyc_extract_15 & pyc_extract_16); +assign pyc_and_21 = (pyc_extract_15 & pyc_extract_17); +assign pyc_or_22 = (pyc_and_20 | pyc_and_21); +assign pyc_and_23 = (pyc_extract_16 & pyc_extract_17); +assign pyc_or_24 = (pyc_or_22 | pyc_and_23); +assign pyc_extract_25 = PE_INT_WALLACE_DOT8_TREE_W16_in3[1]; +assign pyc_xor_26 = (pyc_xor_19 ^ pyc_extract_25); +assign pyc_xor_27 = (pyc_xor_26 ^ pyc_or_11); +assign pyc_and_28 = (pyc_xor_19 & pyc_extract_25); +assign pyc_and_29 = (pyc_xor_19 & pyc_or_11); +assign pyc_or_30 = (pyc_and_28 | pyc_and_29); +assign pyc_and_31 = (pyc_extract_25 & pyc_or_11); +assign pyc_or_32 = (pyc_or_30 | pyc_and_31); +assign pyc_extract_33 = PE_INT_WALLACE_DOT8_TREE_W16_in0[2]; +assign pyc_extract_34 = PE_INT_WALLACE_DOT8_TREE_W16_in1[2]; +assign pyc_extract_35 = PE_INT_WALLACE_DOT8_TREE_W16_in2[2]; +assign pyc_xor_36 = (pyc_extract_33 ^ pyc_extract_34); +assign pyc_xor_37 = (pyc_xor_36 ^ pyc_extract_35); +assign pyc_and_38 = (pyc_extract_33 & pyc_extract_34); +assign pyc_and_39 = (pyc_extract_33 & pyc_extract_35); +assign pyc_or_40 = (pyc_and_38 | pyc_and_39); +assign pyc_and_41 = (pyc_extract_34 & pyc_extract_35); +assign pyc_or_42 = (pyc_or_40 | pyc_and_41); +assign pyc_extract_43 = PE_INT_WALLACE_DOT8_TREE_W16_in3[2]; +assign pyc_xor_44 = (pyc_xor_37 ^ pyc_extract_43); +assign pyc_xor_45 = (pyc_xor_44 ^ pyc_or_24); +assign pyc_and_46 = (pyc_xor_37 & pyc_extract_43); +assign pyc_and_47 = (pyc_xor_37 & pyc_or_24); +assign pyc_or_48 = (pyc_and_46 | pyc_and_47); +assign pyc_and_49 = (pyc_extract_43 & pyc_or_24); +assign pyc_or_50 = (pyc_or_48 | pyc_and_49); +assign pyc_extract_51 = PE_INT_WALLACE_DOT8_TREE_W16_in0[3]; +assign pyc_extract_52 = PE_INT_WALLACE_DOT8_TREE_W16_in1[3]; +assign pyc_extract_53 = PE_INT_WALLACE_DOT8_TREE_W16_in2[3]; +assign pyc_xor_54 = (pyc_extract_51 ^ pyc_extract_52); +assign pyc_xor_55 = (pyc_xor_54 ^ pyc_extract_53); +assign pyc_and_56 = (pyc_extract_51 & pyc_extract_52); +assign pyc_and_57 = (pyc_extract_51 & pyc_extract_53); +assign pyc_or_58 = (pyc_and_56 | pyc_and_57); +assign pyc_and_59 = (pyc_extract_52 & pyc_extract_53); +assign pyc_or_60 = (pyc_or_58 | pyc_and_59); +assign pyc_extract_61 = PE_INT_WALLACE_DOT8_TREE_W16_in3[3]; +assign pyc_xor_62 = (pyc_xor_55 ^ pyc_extract_61); +assign pyc_xor_63 = (pyc_xor_62 ^ pyc_or_42); +assign pyc_and_64 = (pyc_xor_55 & pyc_extract_61); +assign pyc_and_65 = (pyc_xor_55 & pyc_or_42); +assign pyc_or_66 = (pyc_and_64 | pyc_and_65); +assign pyc_and_67 = (pyc_extract_61 & pyc_or_42); +assign pyc_or_68 = (pyc_or_66 | pyc_and_67); +assign pyc_extract_69 = PE_INT_WALLACE_DOT8_TREE_W16_in0[4]; +assign pyc_extract_70 = PE_INT_WALLACE_DOT8_TREE_W16_in1[4]; +assign pyc_extract_71 = PE_INT_WALLACE_DOT8_TREE_W16_in2[4]; +assign pyc_xor_72 = (pyc_extract_69 ^ pyc_extract_70); +assign pyc_xor_73 = (pyc_xor_72 ^ pyc_extract_71); +assign pyc_and_74 = (pyc_extract_69 & pyc_extract_70); +assign pyc_and_75 = (pyc_extract_69 & pyc_extract_71); +assign pyc_or_76 = (pyc_and_74 | pyc_and_75); +assign pyc_and_77 = (pyc_extract_70 & pyc_extract_71); +assign pyc_or_78 = (pyc_or_76 | pyc_and_77); +assign pyc_extract_79 = PE_INT_WALLACE_DOT8_TREE_W16_in3[4]; +assign pyc_xor_80 = (pyc_xor_73 ^ pyc_extract_79); +assign pyc_xor_81 = (pyc_xor_80 ^ pyc_or_60); +assign pyc_and_82 = (pyc_xor_73 & pyc_extract_79); +assign pyc_and_83 = (pyc_xor_73 & pyc_or_60); +assign pyc_or_84 = (pyc_and_82 | pyc_and_83); +assign pyc_and_85 = (pyc_extract_79 & pyc_or_60); +assign pyc_or_86 = (pyc_or_84 | pyc_and_85); +assign pyc_extract_87 = PE_INT_WALLACE_DOT8_TREE_W16_in0[5]; +assign pyc_extract_88 = PE_INT_WALLACE_DOT8_TREE_W16_in1[5]; +assign pyc_extract_89 = PE_INT_WALLACE_DOT8_TREE_W16_in2[5]; +assign pyc_xor_90 = (pyc_extract_87 ^ pyc_extract_88); +assign pyc_xor_91 = (pyc_xor_90 ^ pyc_extract_89); +assign pyc_and_92 = (pyc_extract_87 & pyc_extract_88); +assign pyc_and_93 = (pyc_extract_87 & pyc_extract_89); +assign pyc_or_94 = (pyc_and_92 | pyc_and_93); +assign pyc_and_95 = (pyc_extract_88 & pyc_extract_89); +assign pyc_or_96 = (pyc_or_94 | pyc_and_95); +assign pyc_extract_97 = PE_INT_WALLACE_DOT8_TREE_W16_in3[5]; +assign pyc_xor_98 = (pyc_xor_91 ^ pyc_extract_97); +assign pyc_xor_99 = (pyc_xor_98 ^ pyc_or_78); +assign pyc_and_100 = (pyc_xor_91 & pyc_extract_97); +assign pyc_and_101 = (pyc_xor_91 & pyc_or_78); +assign pyc_or_102 = (pyc_and_100 | pyc_and_101); +assign pyc_and_103 = (pyc_extract_97 & pyc_or_78); +assign pyc_or_104 = (pyc_or_102 | pyc_and_103); +assign pyc_extract_105 = PE_INT_WALLACE_DOT8_TREE_W16_in0[6]; +assign pyc_extract_106 = PE_INT_WALLACE_DOT8_TREE_W16_in1[6]; +assign pyc_extract_107 = PE_INT_WALLACE_DOT8_TREE_W16_in2[6]; +assign pyc_xor_108 = (pyc_extract_105 ^ pyc_extract_106); +assign pyc_xor_109 = (pyc_xor_108 ^ pyc_extract_107); +assign pyc_and_110 = (pyc_extract_105 & pyc_extract_106); +assign pyc_and_111 = (pyc_extract_105 & pyc_extract_107); +assign pyc_or_112 = (pyc_and_110 | pyc_and_111); +assign pyc_and_113 = (pyc_extract_106 & pyc_extract_107); +assign pyc_or_114 = (pyc_or_112 | pyc_and_113); +assign pyc_extract_115 = PE_INT_WALLACE_DOT8_TREE_W16_in3[6]; +assign pyc_xor_116 = (pyc_xor_109 ^ pyc_extract_115); +assign pyc_xor_117 = (pyc_xor_116 ^ pyc_or_96); +assign pyc_and_118 = (pyc_xor_109 & pyc_extract_115); +assign pyc_and_119 = (pyc_xor_109 & pyc_or_96); +assign pyc_or_120 = (pyc_and_118 | pyc_and_119); +assign pyc_and_121 = (pyc_extract_115 & pyc_or_96); +assign pyc_or_122 = (pyc_or_120 | pyc_and_121); +assign pyc_extract_123 = PE_INT_WALLACE_DOT8_TREE_W16_in0[7]; +assign pyc_extract_124 = PE_INT_WALLACE_DOT8_TREE_W16_in1[7]; +assign pyc_extract_125 = PE_INT_WALLACE_DOT8_TREE_W16_in2[7]; +assign pyc_xor_126 = (pyc_extract_123 ^ pyc_extract_124); +assign pyc_xor_127 = (pyc_xor_126 ^ pyc_extract_125); +assign pyc_and_128 = (pyc_extract_123 & pyc_extract_124); +assign pyc_and_129 = (pyc_extract_123 & pyc_extract_125); +assign pyc_or_130 = (pyc_and_128 | pyc_and_129); +assign pyc_and_131 = (pyc_extract_124 & pyc_extract_125); +assign pyc_or_132 = (pyc_or_130 | pyc_and_131); +assign pyc_extract_133 = PE_INT_WALLACE_DOT8_TREE_W16_in3[7]; +assign pyc_xor_134 = (pyc_xor_127 ^ pyc_extract_133); +assign pyc_xor_135 = (pyc_xor_134 ^ pyc_or_114); +assign pyc_and_136 = (pyc_xor_127 & pyc_extract_133); +assign pyc_and_137 = (pyc_xor_127 & pyc_or_114); +assign pyc_or_138 = (pyc_and_136 | pyc_and_137); +assign pyc_and_139 = (pyc_extract_133 & pyc_or_114); +assign pyc_or_140 = (pyc_or_138 | pyc_and_139); +assign pyc_extract_141 = PE_INT_WALLACE_DOT8_TREE_W16_in0[8]; +assign pyc_extract_142 = PE_INT_WALLACE_DOT8_TREE_W16_in1[8]; +assign pyc_extract_143 = PE_INT_WALLACE_DOT8_TREE_W16_in2[8]; +assign pyc_xor_144 = (pyc_extract_141 ^ pyc_extract_142); +assign pyc_xor_145 = (pyc_xor_144 ^ pyc_extract_143); +assign pyc_and_146 = (pyc_extract_141 & pyc_extract_142); +assign pyc_and_147 = (pyc_extract_141 & pyc_extract_143); +assign pyc_or_148 = (pyc_and_146 | pyc_and_147); +assign pyc_and_149 = (pyc_extract_142 & pyc_extract_143); +assign pyc_or_150 = (pyc_or_148 | pyc_and_149); +assign pyc_extract_151 = PE_INT_WALLACE_DOT8_TREE_W16_in3[8]; +assign pyc_xor_152 = (pyc_xor_145 ^ pyc_extract_151); +assign pyc_xor_153 = (pyc_xor_152 ^ pyc_or_132); +assign pyc_and_154 = (pyc_xor_145 & pyc_extract_151); +assign pyc_and_155 = (pyc_xor_145 & pyc_or_132); +assign pyc_or_156 = (pyc_and_154 | pyc_and_155); +assign pyc_and_157 = (pyc_extract_151 & pyc_or_132); +assign pyc_or_158 = (pyc_or_156 | pyc_and_157); +assign pyc_extract_159 = PE_INT_WALLACE_DOT8_TREE_W16_in0[9]; +assign pyc_extract_160 = PE_INT_WALLACE_DOT8_TREE_W16_in1[9]; +assign pyc_extract_161 = PE_INT_WALLACE_DOT8_TREE_W16_in2[9]; +assign pyc_xor_162 = (pyc_extract_159 ^ pyc_extract_160); +assign pyc_xor_163 = (pyc_xor_162 ^ pyc_extract_161); +assign pyc_and_164 = (pyc_extract_159 & pyc_extract_160); +assign pyc_and_165 = (pyc_extract_159 & pyc_extract_161); +assign pyc_or_166 = (pyc_and_164 | pyc_and_165); +assign pyc_and_167 = (pyc_extract_160 & pyc_extract_161); +assign pyc_or_168 = (pyc_or_166 | pyc_and_167); +assign pyc_extract_169 = PE_INT_WALLACE_DOT8_TREE_W16_in3[9]; +assign pyc_xor_170 = (pyc_xor_163 ^ pyc_extract_169); +assign pyc_xor_171 = (pyc_xor_170 ^ pyc_or_150); +assign pyc_and_172 = (pyc_xor_163 & pyc_extract_169); +assign pyc_and_173 = (pyc_xor_163 & pyc_or_150); +assign pyc_or_174 = (pyc_and_172 | pyc_and_173); +assign pyc_and_175 = (pyc_extract_169 & pyc_or_150); +assign pyc_or_176 = (pyc_or_174 | pyc_and_175); +assign pyc_extract_177 = PE_INT_WALLACE_DOT8_TREE_W16_in0[10]; +assign pyc_extract_178 = PE_INT_WALLACE_DOT8_TREE_W16_in1[10]; +assign pyc_extract_179 = PE_INT_WALLACE_DOT8_TREE_W16_in2[10]; +assign pyc_xor_180 = (pyc_extract_177 ^ pyc_extract_178); +assign pyc_xor_181 = (pyc_xor_180 ^ pyc_extract_179); +assign pyc_and_182 = (pyc_extract_177 & pyc_extract_178); +assign pyc_and_183 = (pyc_extract_177 & pyc_extract_179); +assign pyc_or_184 = (pyc_and_182 | pyc_and_183); +assign pyc_and_185 = (pyc_extract_178 & pyc_extract_179); +assign pyc_or_186 = (pyc_or_184 | pyc_and_185); +assign pyc_extract_187 = PE_INT_WALLACE_DOT8_TREE_W16_in3[10]; +assign pyc_xor_188 = (pyc_xor_181 ^ pyc_extract_187); +assign pyc_xor_189 = (pyc_xor_188 ^ pyc_or_168); +assign pyc_and_190 = (pyc_xor_181 & pyc_extract_187); +assign pyc_and_191 = (pyc_xor_181 & pyc_or_168); +assign pyc_or_192 = (pyc_and_190 | pyc_and_191); +assign pyc_and_193 = (pyc_extract_187 & pyc_or_168); +assign pyc_or_194 = (pyc_or_192 | pyc_and_193); +assign pyc_extract_195 = PE_INT_WALLACE_DOT8_TREE_W16_in0[11]; +assign pyc_extract_196 = PE_INT_WALLACE_DOT8_TREE_W16_in1[11]; +assign pyc_extract_197 = PE_INT_WALLACE_DOT8_TREE_W16_in2[11]; +assign pyc_xor_198 = (pyc_extract_195 ^ pyc_extract_196); +assign pyc_xor_199 = (pyc_xor_198 ^ pyc_extract_197); +assign pyc_and_200 = (pyc_extract_195 & pyc_extract_196); +assign pyc_and_201 = (pyc_extract_195 & pyc_extract_197); +assign pyc_or_202 = (pyc_and_200 | pyc_and_201); +assign pyc_and_203 = (pyc_extract_196 & pyc_extract_197); +assign pyc_or_204 = (pyc_or_202 | pyc_and_203); +assign pyc_extract_205 = PE_INT_WALLACE_DOT8_TREE_W16_in3[11]; +assign pyc_xor_206 = (pyc_xor_199 ^ pyc_extract_205); +assign pyc_xor_207 = (pyc_xor_206 ^ pyc_or_186); +assign pyc_and_208 = (pyc_xor_199 & pyc_extract_205); +assign pyc_and_209 = (pyc_xor_199 & pyc_or_186); +assign pyc_or_210 = (pyc_and_208 | pyc_and_209); +assign pyc_and_211 = (pyc_extract_205 & pyc_or_186); +assign pyc_or_212 = (pyc_or_210 | pyc_and_211); +assign pyc_extract_213 = PE_INT_WALLACE_DOT8_TREE_W16_in0[12]; +assign pyc_extract_214 = PE_INT_WALLACE_DOT8_TREE_W16_in1[12]; +assign pyc_extract_215 = PE_INT_WALLACE_DOT8_TREE_W16_in2[12]; +assign pyc_xor_216 = (pyc_extract_213 ^ pyc_extract_214); +assign pyc_xor_217 = (pyc_xor_216 ^ pyc_extract_215); +assign pyc_and_218 = (pyc_extract_213 & pyc_extract_214); +assign pyc_and_219 = (pyc_extract_213 & pyc_extract_215); +assign pyc_or_220 = (pyc_and_218 | pyc_and_219); +assign pyc_and_221 = (pyc_extract_214 & pyc_extract_215); +assign pyc_or_222 = (pyc_or_220 | pyc_and_221); +assign pyc_extract_223 = PE_INT_WALLACE_DOT8_TREE_W16_in3[12]; +assign pyc_xor_224 = (pyc_xor_217 ^ pyc_extract_223); +assign pyc_xor_225 = (pyc_xor_224 ^ pyc_or_204); +assign pyc_and_226 = (pyc_xor_217 & pyc_extract_223); +assign pyc_and_227 = (pyc_xor_217 & pyc_or_204); +assign pyc_or_228 = (pyc_and_226 | pyc_and_227); +assign pyc_and_229 = (pyc_extract_223 & pyc_or_204); +assign pyc_or_230 = (pyc_or_228 | pyc_and_229); +assign pyc_extract_231 = PE_INT_WALLACE_DOT8_TREE_W16_in0[13]; +assign pyc_extract_232 = PE_INT_WALLACE_DOT8_TREE_W16_in1[13]; +assign pyc_extract_233 = PE_INT_WALLACE_DOT8_TREE_W16_in2[13]; +assign pyc_xor_234 = (pyc_extract_231 ^ pyc_extract_232); +assign pyc_xor_235 = (pyc_xor_234 ^ pyc_extract_233); +assign pyc_and_236 = (pyc_extract_231 & pyc_extract_232); +assign pyc_and_237 = (pyc_extract_231 & pyc_extract_233); +assign pyc_or_238 = (pyc_and_236 | pyc_and_237); +assign pyc_and_239 = (pyc_extract_232 & pyc_extract_233); +assign pyc_or_240 = (pyc_or_238 | pyc_and_239); +assign pyc_extract_241 = PE_INT_WALLACE_DOT8_TREE_W16_in3[13]; +assign pyc_xor_242 = (pyc_xor_235 ^ pyc_extract_241); +assign pyc_xor_243 = (pyc_xor_242 ^ pyc_or_222); +assign pyc_and_244 = (pyc_xor_235 & pyc_extract_241); +assign pyc_and_245 = (pyc_xor_235 & pyc_or_222); +assign pyc_or_246 = (pyc_and_244 | pyc_and_245); +assign pyc_and_247 = (pyc_extract_241 & pyc_or_222); +assign pyc_or_248 = (pyc_or_246 | pyc_and_247); +assign pyc_extract_249 = PE_INT_WALLACE_DOT8_TREE_W16_in0[14]; +assign pyc_extract_250 = PE_INT_WALLACE_DOT8_TREE_W16_in1[14]; +assign pyc_extract_251 = PE_INT_WALLACE_DOT8_TREE_W16_in2[14]; +assign pyc_xor_252 = (pyc_extract_249 ^ pyc_extract_250); +assign pyc_xor_253 = (pyc_xor_252 ^ pyc_extract_251); +assign pyc_and_254 = (pyc_extract_249 & pyc_extract_250); +assign pyc_and_255 = (pyc_extract_249 & pyc_extract_251); +assign pyc_or_256 = (pyc_and_254 | pyc_and_255); +assign pyc_and_257 = (pyc_extract_250 & pyc_extract_251); +assign pyc_or_258 = (pyc_or_256 | pyc_and_257); +assign pyc_extract_259 = PE_INT_WALLACE_DOT8_TREE_W16_in3[14]; +assign pyc_xor_260 = (pyc_xor_253 ^ pyc_extract_259); +assign pyc_xor_261 = (pyc_xor_260 ^ pyc_or_240); +assign pyc_and_262 = (pyc_xor_253 & pyc_extract_259); +assign pyc_and_263 = (pyc_xor_253 & pyc_or_240); +assign pyc_or_264 = (pyc_and_262 | pyc_and_263); +assign pyc_and_265 = (pyc_extract_259 & pyc_or_240); +assign pyc_or_266 = (pyc_or_264 | pyc_and_265); +assign pyc_extract_267 = PE_INT_WALLACE_DOT8_TREE_W16_in0[15]; +assign pyc_extract_268 = PE_INT_WALLACE_DOT8_TREE_W16_in1[15]; +assign pyc_extract_269 = PE_INT_WALLACE_DOT8_TREE_W16_in2[15]; +assign pyc_xor_270 = (pyc_extract_267 ^ pyc_extract_268); +assign pyc_xor_271 = (pyc_xor_270 ^ pyc_extract_269); +assign pyc_extract_272 = PE_INT_WALLACE_DOT8_TREE_W16_in3[15]; +assign pyc_xor_273 = (pyc_xor_271 ^ pyc_extract_272); +assign pyc_xor_274 = (pyc_xor_273 ^ pyc_or_258); +assign pyc_extract_275 = PE_INT_WALLACE_DOT8_TREE_W16_in4[0]; +assign pyc_extract_276 = PE_INT_WALLACE_DOT8_TREE_W16_in5[0]; +assign pyc_extract_277 = PE_INT_WALLACE_DOT8_TREE_W16_in6[0]; +assign pyc_xor_278 = (pyc_extract_275 ^ pyc_extract_276); +assign pyc_xor_279 = (pyc_xor_278 ^ pyc_extract_277); +assign pyc_and_280 = (pyc_extract_275 & pyc_extract_276); +assign pyc_and_281 = (pyc_extract_275 & pyc_extract_277); +assign pyc_or_282 = (pyc_and_280 | pyc_and_281); +assign pyc_and_283 = (pyc_extract_276 & pyc_extract_277); +assign pyc_or_284 = (pyc_or_282 | pyc_and_283); +assign pyc_extract_285 = PE_INT_WALLACE_DOT8_TREE_W16_in7[0]; +assign pyc_xor_286 = (pyc_xor_279 ^ pyc_extract_285); +assign pyc_and_287 = (pyc_xor_279 & pyc_extract_285); +assign pyc_extract_288 = PE_INT_WALLACE_DOT8_TREE_W16_in4[1]; +assign pyc_extract_289 = PE_INT_WALLACE_DOT8_TREE_W16_in5[1]; +assign pyc_extract_290 = PE_INT_WALLACE_DOT8_TREE_W16_in6[1]; +assign pyc_xor_291 = (pyc_extract_288 ^ pyc_extract_289); +assign pyc_xor_292 = (pyc_xor_291 ^ pyc_extract_290); +assign pyc_and_293 = (pyc_extract_288 & pyc_extract_289); +assign pyc_and_294 = (pyc_extract_288 & pyc_extract_290); +assign pyc_or_295 = (pyc_and_293 | pyc_and_294); +assign pyc_and_296 = (pyc_extract_289 & pyc_extract_290); +assign pyc_or_297 = (pyc_or_295 | pyc_and_296); +assign pyc_extract_298 = PE_INT_WALLACE_DOT8_TREE_W16_in7[1]; +assign pyc_xor_299 = (pyc_xor_292 ^ pyc_extract_298); +assign pyc_xor_300 = (pyc_xor_299 ^ pyc_or_284); +assign pyc_and_301 = (pyc_xor_292 & pyc_extract_298); +assign pyc_and_302 = (pyc_xor_292 & pyc_or_284); +assign pyc_or_303 = (pyc_and_301 | pyc_and_302); +assign pyc_and_304 = (pyc_extract_298 & pyc_or_284); +assign pyc_or_305 = (pyc_or_303 | pyc_and_304); +assign pyc_extract_306 = PE_INT_WALLACE_DOT8_TREE_W16_in4[2]; +assign pyc_extract_307 = PE_INT_WALLACE_DOT8_TREE_W16_in5[2]; +assign pyc_extract_308 = PE_INT_WALLACE_DOT8_TREE_W16_in6[2]; +assign pyc_xor_309 = (pyc_extract_306 ^ pyc_extract_307); +assign pyc_xor_310 = (pyc_xor_309 ^ pyc_extract_308); +assign pyc_and_311 = (pyc_extract_306 & pyc_extract_307); +assign pyc_and_312 = (pyc_extract_306 & pyc_extract_308); +assign pyc_or_313 = (pyc_and_311 | pyc_and_312); +assign pyc_and_314 = (pyc_extract_307 & pyc_extract_308); +assign pyc_or_315 = (pyc_or_313 | pyc_and_314); +assign pyc_extract_316 = PE_INT_WALLACE_DOT8_TREE_W16_in7[2]; +assign pyc_xor_317 = (pyc_xor_310 ^ pyc_extract_316); +assign pyc_xor_318 = (pyc_xor_317 ^ pyc_or_297); +assign pyc_and_319 = (pyc_xor_310 & pyc_extract_316); +assign pyc_and_320 = (pyc_xor_310 & pyc_or_297); +assign pyc_or_321 = (pyc_and_319 | pyc_and_320); +assign pyc_and_322 = (pyc_extract_316 & pyc_or_297); +assign pyc_or_323 = (pyc_or_321 | pyc_and_322); +assign pyc_extract_324 = PE_INT_WALLACE_DOT8_TREE_W16_in4[3]; +assign pyc_extract_325 = PE_INT_WALLACE_DOT8_TREE_W16_in5[3]; +assign pyc_extract_326 = PE_INT_WALLACE_DOT8_TREE_W16_in6[3]; +assign pyc_xor_327 = (pyc_extract_324 ^ pyc_extract_325); +assign pyc_xor_328 = (pyc_xor_327 ^ pyc_extract_326); +assign pyc_and_329 = (pyc_extract_324 & pyc_extract_325); +assign pyc_and_330 = (pyc_extract_324 & pyc_extract_326); +assign pyc_or_331 = (pyc_and_329 | pyc_and_330); +assign pyc_and_332 = (pyc_extract_325 & pyc_extract_326); +assign pyc_or_333 = (pyc_or_331 | pyc_and_332); +assign pyc_extract_334 = PE_INT_WALLACE_DOT8_TREE_W16_in7[3]; +assign pyc_xor_335 = (pyc_xor_328 ^ pyc_extract_334); +assign pyc_xor_336 = (pyc_xor_335 ^ pyc_or_315); +assign pyc_and_337 = (pyc_xor_328 & pyc_extract_334); +assign pyc_and_338 = (pyc_xor_328 & pyc_or_315); +assign pyc_or_339 = (pyc_and_337 | pyc_and_338); +assign pyc_and_340 = (pyc_extract_334 & pyc_or_315); +assign pyc_or_341 = (pyc_or_339 | pyc_and_340); +assign pyc_extract_342 = PE_INT_WALLACE_DOT8_TREE_W16_in4[4]; +assign pyc_extract_343 = PE_INT_WALLACE_DOT8_TREE_W16_in5[4]; +assign pyc_extract_344 = PE_INT_WALLACE_DOT8_TREE_W16_in6[4]; +assign pyc_xor_345 = (pyc_extract_342 ^ pyc_extract_343); +assign pyc_xor_346 = (pyc_xor_345 ^ pyc_extract_344); +assign pyc_and_347 = (pyc_extract_342 & pyc_extract_343); +assign pyc_and_348 = (pyc_extract_342 & pyc_extract_344); +assign pyc_or_349 = (pyc_and_347 | pyc_and_348); +assign pyc_and_350 = (pyc_extract_343 & pyc_extract_344); +assign pyc_or_351 = (pyc_or_349 | pyc_and_350); +assign pyc_extract_352 = PE_INT_WALLACE_DOT8_TREE_W16_in7[4]; +assign pyc_xor_353 = (pyc_xor_346 ^ pyc_extract_352); +assign pyc_xor_354 = (pyc_xor_353 ^ pyc_or_333); +assign pyc_and_355 = (pyc_xor_346 & pyc_extract_352); +assign pyc_and_356 = (pyc_xor_346 & pyc_or_333); +assign pyc_or_357 = (pyc_and_355 | pyc_and_356); +assign pyc_and_358 = (pyc_extract_352 & pyc_or_333); +assign pyc_or_359 = (pyc_or_357 | pyc_and_358); +assign pyc_extract_360 = PE_INT_WALLACE_DOT8_TREE_W16_in4[5]; +assign pyc_extract_361 = PE_INT_WALLACE_DOT8_TREE_W16_in5[5]; +assign pyc_extract_362 = PE_INT_WALLACE_DOT8_TREE_W16_in6[5]; +assign pyc_xor_363 = (pyc_extract_360 ^ pyc_extract_361); +assign pyc_xor_364 = (pyc_xor_363 ^ pyc_extract_362); +assign pyc_and_365 = (pyc_extract_360 & pyc_extract_361); +assign pyc_and_366 = (pyc_extract_360 & pyc_extract_362); +assign pyc_or_367 = (pyc_and_365 | pyc_and_366); +assign pyc_and_368 = (pyc_extract_361 & pyc_extract_362); +assign pyc_or_369 = (pyc_or_367 | pyc_and_368); +assign pyc_extract_370 = PE_INT_WALLACE_DOT8_TREE_W16_in7[5]; +assign pyc_xor_371 = (pyc_xor_364 ^ pyc_extract_370); +assign pyc_xor_372 = (pyc_xor_371 ^ pyc_or_351); +assign pyc_and_373 = (pyc_xor_364 & pyc_extract_370); +assign pyc_and_374 = (pyc_xor_364 & pyc_or_351); +assign pyc_or_375 = (pyc_and_373 | pyc_and_374); +assign pyc_and_376 = (pyc_extract_370 & pyc_or_351); +assign pyc_or_377 = (pyc_or_375 | pyc_and_376); +assign pyc_extract_378 = PE_INT_WALLACE_DOT8_TREE_W16_in4[6]; +assign pyc_extract_379 = PE_INT_WALLACE_DOT8_TREE_W16_in5[6]; +assign pyc_extract_380 = PE_INT_WALLACE_DOT8_TREE_W16_in6[6]; +assign pyc_xor_381 = (pyc_extract_378 ^ pyc_extract_379); +assign pyc_xor_382 = (pyc_xor_381 ^ pyc_extract_380); +assign pyc_and_383 = (pyc_extract_378 & pyc_extract_379); +assign pyc_and_384 = (pyc_extract_378 & pyc_extract_380); +assign pyc_or_385 = (pyc_and_383 | pyc_and_384); +assign pyc_and_386 = (pyc_extract_379 & pyc_extract_380); +assign pyc_or_387 = (pyc_or_385 | pyc_and_386); +assign pyc_extract_388 = PE_INT_WALLACE_DOT8_TREE_W16_in7[6]; +assign pyc_xor_389 = (pyc_xor_382 ^ pyc_extract_388); +assign pyc_xor_390 = (pyc_xor_389 ^ pyc_or_369); +assign pyc_and_391 = (pyc_xor_382 & pyc_extract_388); +assign pyc_and_392 = (pyc_xor_382 & pyc_or_369); +assign pyc_or_393 = (pyc_and_391 | pyc_and_392); +assign pyc_and_394 = (pyc_extract_388 & pyc_or_369); +assign pyc_or_395 = (pyc_or_393 | pyc_and_394); +assign pyc_extract_396 = PE_INT_WALLACE_DOT8_TREE_W16_in4[7]; +assign pyc_extract_397 = PE_INT_WALLACE_DOT8_TREE_W16_in5[7]; +assign pyc_extract_398 = PE_INT_WALLACE_DOT8_TREE_W16_in6[7]; +assign pyc_xor_399 = (pyc_extract_396 ^ pyc_extract_397); +assign pyc_xor_400 = (pyc_xor_399 ^ pyc_extract_398); +assign pyc_and_401 = (pyc_extract_396 & pyc_extract_397); +assign pyc_and_402 = (pyc_extract_396 & pyc_extract_398); +assign pyc_or_403 = (pyc_and_401 | pyc_and_402); +assign pyc_and_404 = (pyc_extract_397 & pyc_extract_398); +assign pyc_or_405 = (pyc_or_403 | pyc_and_404); +assign pyc_extract_406 = PE_INT_WALLACE_DOT8_TREE_W16_in7[7]; +assign pyc_xor_407 = (pyc_xor_400 ^ pyc_extract_406); +assign pyc_xor_408 = (pyc_xor_407 ^ pyc_or_387); +assign pyc_and_409 = (pyc_xor_400 & pyc_extract_406); +assign pyc_and_410 = (pyc_xor_400 & pyc_or_387); +assign pyc_or_411 = (pyc_and_409 | pyc_and_410); +assign pyc_and_412 = (pyc_extract_406 & pyc_or_387); +assign pyc_or_413 = (pyc_or_411 | pyc_and_412); +assign pyc_extract_414 = PE_INT_WALLACE_DOT8_TREE_W16_in4[8]; +assign pyc_extract_415 = PE_INT_WALLACE_DOT8_TREE_W16_in5[8]; +assign pyc_extract_416 = PE_INT_WALLACE_DOT8_TREE_W16_in6[8]; +assign pyc_xor_417 = (pyc_extract_414 ^ pyc_extract_415); +assign pyc_xor_418 = (pyc_xor_417 ^ pyc_extract_416); +assign pyc_and_419 = (pyc_extract_414 & pyc_extract_415); +assign pyc_and_420 = (pyc_extract_414 & pyc_extract_416); +assign pyc_or_421 = (pyc_and_419 | pyc_and_420); +assign pyc_and_422 = (pyc_extract_415 & pyc_extract_416); +assign pyc_or_423 = (pyc_or_421 | pyc_and_422); +assign pyc_extract_424 = PE_INT_WALLACE_DOT8_TREE_W16_in7[8]; +assign pyc_xor_425 = (pyc_xor_418 ^ pyc_extract_424); +assign pyc_xor_426 = (pyc_xor_425 ^ pyc_or_405); +assign pyc_and_427 = (pyc_xor_418 & pyc_extract_424); +assign pyc_and_428 = (pyc_xor_418 & pyc_or_405); +assign pyc_or_429 = (pyc_and_427 | pyc_and_428); +assign pyc_and_430 = (pyc_extract_424 & pyc_or_405); +assign pyc_or_431 = (pyc_or_429 | pyc_and_430); +assign pyc_extract_432 = PE_INT_WALLACE_DOT8_TREE_W16_in4[9]; +assign pyc_extract_433 = PE_INT_WALLACE_DOT8_TREE_W16_in5[9]; +assign pyc_extract_434 = PE_INT_WALLACE_DOT8_TREE_W16_in6[9]; +assign pyc_xor_435 = (pyc_extract_432 ^ pyc_extract_433); +assign pyc_xor_436 = (pyc_xor_435 ^ pyc_extract_434); +assign pyc_and_437 = (pyc_extract_432 & pyc_extract_433); +assign pyc_and_438 = (pyc_extract_432 & pyc_extract_434); +assign pyc_or_439 = (pyc_and_437 | pyc_and_438); +assign pyc_and_440 = (pyc_extract_433 & pyc_extract_434); +assign pyc_or_441 = (pyc_or_439 | pyc_and_440); +assign pyc_extract_442 = PE_INT_WALLACE_DOT8_TREE_W16_in7[9]; +assign pyc_xor_443 = (pyc_xor_436 ^ pyc_extract_442); +assign pyc_xor_444 = (pyc_xor_443 ^ pyc_or_423); +assign pyc_and_445 = (pyc_xor_436 & pyc_extract_442); +assign pyc_and_446 = (pyc_xor_436 & pyc_or_423); +assign pyc_or_447 = (pyc_and_445 | pyc_and_446); +assign pyc_and_448 = (pyc_extract_442 & pyc_or_423); +assign pyc_or_449 = (pyc_or_447 | pyc_and_448); +assign pyc_extract_450 = PE_INT_WALLACE_DOT8_TREE_W16_in4[10]; +assign pyc_extract_451 = PE_INT_WALLACE_DOT8_TREE_W16_in5[10]; +assign pyc_extract_452 = PE_INT_WALLACE_DOT8_TREE_W16_in6[10]; +assign pyc_xor_453 = (pyc_extract_450 ^ pyc_extract_451); +assign pyc_xor_454 = (pyc_xor_453 ^ pyc_extract_452); +assign pyc_and_455 = (pyc_extract_450 & pyc_extract_451); +assign pyc_and_456 = (pyc_extract_450 & pyc_extract_452); +assign pyc_or_457 = (pyc_and_455 | pyc_and_456); +assign pyc_and_458 = (pyc_extract_451 & pyc_extract_452); +assign pyc_or_459 = (pyc_or_457 | pyc_and_458); +assign pyc_extract_460 = PE_INT_WALLACE_DOT8_TREE_W16_in7[10]; +assign pyc_xor_461 = (pyc_xor_454 ^ pyc_extract_460); +assign pyc_xor_462 = (pyc_xor_461 ^ pyc_or_441); +assign pyc_and_463 = (pyc_xor_454 & pyc_extract_460); +assign pyc_and_464 = (pyc_xor_454 & pyc_or_441); +assign pyc_or_465 = (pyc_and_463 | pyc_and_464); +assign pyc_and_466 = (pyc_extract_460 & pyc_or_441); +assign pyc_or_467 = (pyc_or_465 | pyc_and_466); +assign pyc_extract_468 = PE_INT_WALLACE_DOT8_TREE_W16_in4[11]; +assign pyc_extract_469 = PE_INT_WALLACE_DOT8_TREE_W16_in5[11]; +assign pyc_extract_470 = PE_INT_WALLACE_DOT8_TREE_W16_in6[11]; +assign pyc_xor_471 = (pyc_extract_468 ^ pyc_extract_469); +assign pyc_xor_472 = (pyc_xor_471 ^ pyc_extract_470); +assign pyc_and_473 = (pyc_extract_468 & pyc_extract_469); +assign pyc_and_474 = (pyc_extract_468 & pyc_extract_470); +assign pyc_or_475 = (pyc_and_473 | pyc_and_474); +assign pyc_and_476 = (pyc_extract_469 & pyc_extract_470); +assign pyc_or_477 = (pyc_or_475 | pyc_and_476); +assign pyc_extract_478 = PE_INT_WALLACE_DOT8_TREE_W16_in7[11]; +assign pyc_xor_479 = (pyc_xor_472 ^ pyc_extract_478); +assign pyc_xor_480 = (pyc_xor_479 ^ pyc_or_459); +assign pyc_and_481 = (pyc_xor_472 & pyc_extract_478); +assign pyc_and_482 = (pyc_xor_472 & pyc_or_459); +assign pyc_or_483 = (pyc_and_481 | pyc_and_482); +assign pyc_and_484 = (pyc_extract_478 & pyc_or_459); +assign pyc_or_485 = (pyc_or_483 | pyc_and_484); +assign pyc_extract_486 = PE_INT_WALLACE_DOT8_TREE_W16_in4[12]; +assign pyc_extract_487 = PE_INT_WALLACE_DOT8_TREE_W16_in5[12]; +assign pyc_extract_488 = PE_INT_WALLACE_DOT8_TREE_W16_in6[12]; +assign pyc_xor_489 = (pyc_extract_486 ^ pyc_extract_487); +assign pyc_xor_490 = (pyc_xor_489 ^ pyc_extract_488); +assign pyc_and_491 = (pyc_extract_486 & pyc_extract_487); +assign pyc_and_492 = (pyc_extract_486 & pyc_extract_488); +assign pyc_or_493 = (pyc_and_491 | pyc_and_492); +assign pyc_and_494 = (pyc_extract_487 & pyc_extract_488); +assign pyc_or_495 = (pyc_or_493 | pyc_and_494); +assign pyc_extract_496 = PE_INT_WALLACE_DOT8_TREE_W16_in7[12]; +assign pyc_xor_497 = (pyc_xor_490 ^ pyc_extract_496); +assign pyc_xor_498 = (pyc_xor_497 ^ pyc_or_477); +assign pyc_and_499 = (pyc_xor_490 & pyc_extract_496); +assign pyc_and_500 = (pyc_xor_490 & pyc_or_477); +assign pyc_or_501 = (pyc_and_499 | pyc_and_500); +assign pyc_and_502 = (pyc_extract_496 & pyc_or_477); +assign pyc_or_503 = (pyc_or_501 | pyc_and_502); +assign pyc_extract_504 = PE_INT_WALLACE_DOT8_TREE_W16_in4[13]; +assign pyc_extract_505 = PE_INT_WALLACE_DOT8_TREE_W16_in5[13]; +assign pyc_extract_506 = PE_INT_WALLACE_DOT8_TREE_W16_in6[13]; +assign pyc_xor_507 = (pyc_extract_504 ^ pyc_extract_505); +assign pyc_xor_508 = (pyc_xor_507 ^ pyc_extract_506); +assign pyc_and_509 = (pyc_extract_504 & pyc_extract_505); +assign pyc_and_510 = (pyc_extract_504 & pyc_extract_506); +assign pyc_or_511 = (pyc_and_509 | pyc_and_510); +assign pyc_and_512 = (pyc_extract_505 & pyc_extract_506); +assign pyc_or_513 = (pyc_or_511 | pyc_and_512); +assign pyc_extract_514 = PE_INT_WALLACE_DOT8_TREE_W16_in7[13]; +assign pyc_xor_515 = (pyc_xor_508 ^ pyc_extract_514); +assign pyc_xor_516 = (pyc_xor_515 ^ pyc_or_495); +assign pyc_and_517 = (pyc_xor_508 & pyc_extract_514); +assign pyc_and_518 = (pyc_xor_508 & pyc_or_495); +assign pyc_or_519 = (pyc_and_517 | pyc_and_518); +assign pyc_and_520 = (pyc_extract_514 & pyc_or_495); +assign pyc_or_521 = (pyc_or_519 | pyc_and_520); +assign pyc_extract_522 = PE_INT_WALLACE_DOT8_TREE_W16_in4[14]; +assign pyc_extract_523 = PE_INT_WALLACE_DOT8_TREE_W16_in5[14]; +assign pyc_extract_524 = PE_INT_WALLACE_DOT8_TREE_W16_in6[14]; +assign pyc_xor_525 = (pyc_extract_522 ^ pyc_extract_523); +assign pyc_xor_526 = (pyc_xor_525 ^ pyc_extract_524); +assign pyc_and_527 = (pyc_extract_522 & pyc_extract_523); +assign pyc_and_528 = (pyc_extract_522 & pyc_extract_524); +assign pyc_or_529 = (pyc_and_527 | pyc_and_528); +assign pyc_and_530 = (pyc_extract_523 & pyc_extract_524); +assign pyc_or_531 = (pyc_or_529 | pyc_and_530); +assign pyc_extract_532 = PE_INT_WALLACE_DOT8_TREE_W16_in7[14]; +assign pyc_xor_533 = (pyc_xor_526 ^ pyc_extract_532); +assign pyc_xor_534 = (pyc_xor_533 ^ pyc_or_513); +assign pyc_and_535 = (pyc_xor_526 & pyc_extract_532); +assign pyc_and_536 = (pyc_xor_526 & pyc_or_513); +assign pyc_or_537 = (pyc_and_535 | pyc_and_536); +assign pyc_and_538 = (pyc_extract_532 & pyc_or_513); +assign pyc_or_539 = (pyc_or_537 | pyc_and_538); +assign pyc_extract_540 = PE_INT_WALLACE_DOT8_TREE_W16_in4[15]; +assign pyc_extract_541 = PE_INT_WALLACE_DOT8_TREE_W16_in5[15]; +assign pyc_extract_542 = PE_INT_WALLACE_DOT8_TREE_W16_in6[15]; +assign pyc_xor_543 = (pyc_extract_540 ^ pyc_extract_541); +assign pyc_xor_544 = (pyc_xor_543 ^ pyc_extract_542); +assign pyc_extract_545 = PE_INT_WALLACE_DOT8_TREE_W16_in7[15]; +assign pyc_xor_546 = (pyc_xor_544 ^ pyc_extract_545); +assign pyc_xor_547 = (pyc_xor_546 ^ pyc_or_531); +assign pyc_xor_548 = (pyc_xor_13 ^ pyc_xor_286); +assign pyc_and_549 = (pyc_xor_13 & pyc_xor_286); +assign pyc_xor_550 = (pyc_xor_27 ^ pyc_and_14); +assign pyc_xor_551 = (pyc_xor_550 ^ pyc_xor_300); +assign pyc_and_552 = (pyc_xor_27 & pyc_and_14); +assign pyc_and_553 = (pyc_xor_27 & pyc_xor_300); +assign pyc_or_554 = (pyc_and_552 | pyc_and_553); +assign pyc_and_555 = (pyc_and_14 & pyc_xor_300); +assign pyc_or_556 = (pyc_or_554 | pyc_and_555); +assign pyc_xor_557 = (pyc_xor_551 ^ pyc_and_287); +assign pyc_xor_558 = (pyc_xor_557 ^ pyc_and_549); +assign pyc_and_559 = (pyc_xor_551 & pyc_and_287); +assign pyc_and_560 = (pyc_xor_551 & pyc_and_549); +assign pyc_or_561 = (pyc_and_559 | pyc_and_560); +assign pyc_and_562 = (pyc_and_287 & pyc_and_549); +assign pyc_or_563 = (pyc_or_561 | pyc_and_562); +assign pyc_xor_564 = (pyc_xor_45 ^ pyc_or_32); +assign pyc_xor_565 = (pyc_xor_564 ^ pyc_xor_318); +assign pyc_and_566 = (pyc_xor_45 & pyc_or_32); +assign pyc_and_567 = (pyc_xor_45 & pyc_xor_318); +assign pyc_or_568 = (pyc_and_566 | pyc_and_567); +assign pyc_and_569 = (pyc_or_32 & pyc_xor_318); +assign pyc_or_570 = (pyc_or_568 | pyc_and_569); +assign pyc_xor_571 = (pyc_xor_565 ^ pyc_or_305); +assign pyc_xor_572 = (pyc_xor_571 ^ pyc_or_556); +assign pyc_and_573 = (pyc_xor_565 & pyc_or_305); +assign pyc_and_574 = (pyc_xor_565 & pyc_or_556); +assign pyc_or_575 = (pyc_and_573 | pyc_and_574); +assign pyc_and_576 = (pyc_or_305 & pyc_or_556); +assign pyc_or_577 = (pyc_or_575 | pyc_and_576); +assign pyc_xor_578 = (pyc_xor_63 ^ pyc_or_50); +assign pyc_xor_579 = (pyc_xor_578 ^ pyc_xor_336); +assign pyc_and_580 = (pyc_xor_63 & pyc_or_50); +assign pyc_and_581 = (pyc_xor_63 & pyc_xor_336); +assign pyc_or_582 = (pyc_and_580 | pyc_and_581); +assign pyc_and_583 = (pyc_or_50 & pyc_xor_336); +assign pyc_or_584 = (pyc_or_582 | pyc_and_583); +assign pyc_xor_585 = (pyc_xor_579 ^ pyc_or_323); +assign pyc_xor_586 = (pyc_xor_585 ^ pyc_or_570); +assign pyc_and_587 = (pyc_xor_579 & pyc_or_323); +assign pyc_and_588 = (pyc_xor_579 & pyc_or_570); +assign pyc_or_589 = (pyc_and_587 | pyc_and_588); +assign pyc_and_590 = (pyc_or_323 & pyc_or_570); +assign pyc_or_591 = (pyc_or_589 | pyc_and_590); +assign pyc_xor_592 = (pyc_xor_81 ^ pyc_or_68); +assign pyc_xor_593 = (pyc_xor_592 ^ pyc_xor_354); +assign pyc_and_594 = (pyc_xor_81 & pyc_or_68); +assign pyc_and_595 = (pyc_xor_81 & pyc_xor_354); +assign pyc_or_596 = (pyc_and_594 | pyc_and_595); +assign pyc_and_597 = (pyc_or_68 & pyc_xor_354); +assign pyc_or_598 = (pyc_or_596 | pyc_and_597); +assign pyc_xor_599 = (pyc_xor_593 ^ pyc_or_341); +assign pyc_xor_600 = (pyc_xor_599 ^ pyc_or_584); +assign pyc_and_601 = (pyc_xor_593 & pyc_or_341); +assign pyc_and_602 = (pyc_xor_593 & pyc_or_584); +assign pyc_or_603 = (pyc_and_601 | pyc_and_602); +assign pyc_and_604 = (pyc_or_341 & pyc_or_584); +assign pyc_or_605 = (pyc_or_603 | pyc_and_604); +assign pyc_xor_606 = (pyc_xor_99 ^ pyc_or_86); +assign pyc_xor_607 = (pyc_xor_606 ^ pyc_xor_372); +assign pyc_and_608 = (pyc_xor_99 & pyc_or_86); +assign pyc_and_609 = (pyc_xor_99 & pyc_xor_372); +assign pyc_or_610 = (pyc_and_608 | pyc_and_609); +assign pyc_and_611 = (pyc_or_86 & pyc_xor_372); +assign pyc_or_612 = (pyc_or_610 | pyc_and_611); +assign pyc_xor_613 = (pyc_xor_607 ^ pyc_or_359); +assign pyc_xor_614 = (pyc_xor_613 ^ pyc_or_598); +assign pyc_and_615 = (pyc_xor_607 & pyc_or_359); +assign pyc_and_616 = (pyc_xor_607 & pyc_or_598); +assign pyc_or_617 = (pyc_and_615 | pyc_and_616); +assign pyc_and_618 = (pyc_or_359 & pyc_or_598); +assign pyc_or_619 = (pyc_or_617 | pyc_and_618); +assign pyc_xor_620 = (pyc_xor_117 ^ pyc_or_104); +assign pyc_xor_621 = (pyc_xor_620 ^ pyc_xor_390); +assign pyc_and_622 = (pyc_xor_117 & pyc_or_104); +assign pyc_and_623 = (pyc_xor_117 & pyc_xor_390); +assign pyc_or_624 = (pyc_and_622 | pyc_and_623); +assign pyc_and_625 = (pyc_or_104 & pyc_xor_390); +assign pyc_or_626 = (pyc_or_624 | pyc_and_625); +assign pyc_xor_627 = (pyc_xor_621 ^ pyc_or_377); +assign pyc_xor_628 = (pyc_xor_627 ^ pyc_or_612); +assign pyc_and_629 = (pyc_xor_621 & pyc_or_377); +assign pyc_and_630 = (pyc_xor_621 & pyc_or_612); +assign pyc_or_631 = (pyc_and_629 | pyc_and_630); +assign pyc_and_632 = (pyc_or_377 & pyc_or_612); +assign pyc_or_633 = (pyc_or_631 | pyc_and_632); +assign pyc_xor_634 = (pyc_xor_135 ^ pyc_or_122); +assign pyc_xor_635 = (pyc_xor_634 ^ pyc_xor_408); +assign pyc_and_636 = (pyc_xor_135 & pyc_or_122); +assign pyc_and_637 = (pyc_xor_135 & pyc_xor_408); +assign pyc_or_638 = (pyc_and_636 | pyc_and_637); +assign pyc_and_639 = (pyc_or_122 & pyc_xor_408); +assign pyc_or_640 = (pyc_or_638 | pyc_and_639); +assign pyc_xor_641 = (pyc_xor_635 ^ pyc_or_395); +assign pyc_xor_642 = (pyc_xor_641 ^ pyc_or_626); +assign pyc_and_643 = (pyc_xor_635 & pyc_or_395); +assign pyc_and_644 = (pyc_xor_635 & pyc_or_626); +assign pyc_or_645 = (pyc_and_643 | pyc_and_644); +assign pyc_and_646 = (pyc_or_395 & pyc_or_626); +assign pyc_or_647 = (pyc_or_645 | pyc_and_646); +assign pyc_xor_648 = (pyc_xor_153 ^ pyc_or_140); +assign pyc_xor_649 = (pyc_xor_648 ^ pyc_xor_426); +assign pyc_and_650 = (pyc_xor_153 & pyc_or_140); +assign pyc_and_651 = (pyc_xor_153 & pyc_xor_426); +assign pyc_or_652 = (pyc_and_650 | pyc_and_651); +assign pyc_and_653 = (pyc_or_140 & pyc_xor_426); +assign pyc_or_654 = (pyc_or_652 | pyc_and_653); +assign pyc_xor_655 = (pyc_xor_649 ^ pyc_or_413); +assign pyc_xor_656 = (pyc_xor_655 ^ pyc_or_640); +assign pyc_and_657 = (pyc_xor_649 & pyc_or_413); +assign pyc_and_658 = (pyc_xor_649 & pyc_or_640); +assign pyc_or_659 = (pyc_and_657 | pyc_and_658); +assign pyc_and_660 = (pyc_or_413 & pyc_or_640); +assign pyc_or_661 = (pyc_or_659 | pyc_and_660); +assign pyc_xor_662 = (pyc_xor_171 ^ pyc_or_158); +assign pyc_xor_663 = (pyc_xor_662 ^ pyc_xor_444); +assign pyc_and_664 = (pyc_xor_171 & pyc_or_158); +assign pyc_and_665 = (pyc_xor_171 & pyc_xor_444); +assign pyc_or_666 = (pyc_and_664 | pyc_and_665); +assign pyc_and_667 = (pyc_or_158 & pyc_xor_444); +assign pyc_or_668 = (pyc_or_666 | pyc_and_667); +assign pyc_xor_669 = (pyc_xor_663 ^ pyc_or_431); +assign pyc_xor_670 = (pyc_xor_669 ^ pyc_or_654); +assign pyc_and_671 = (pyc_xor_663 & pyc_or_431); +assign pyc_and_672 = (pyc_xor_663 & pyc_or_654); +assign pyc_or_673 = (pyc_and_671 | pyc_and_672); +assign pyc_and_674 = (pyc_or_431 & pyc_or_654); +assign pyc_or_675 = (pyc_or_673 | pyc_and_674); +assign pyc_xor_676 = (pyc_xor_189 ^ pyc_or_176); +assign pyc_xor_677 = (pyc_xor_676 ^ pyc_xor_462); +assign pyc_and_678 = (pyc_xor_189 & pyc_or_176); +assign pyc_and_679 = (pyc_xor_189 & pyc_xor_462); +assign pyc_or_680 = (pyc_and_678 | pyc_and_679); +assign pyc_and_681 = (pyc_or_176 & pyc_xor_462); +assign pyc_or_682 = (pyc_or_680 | pyc_and_681); +assign pyc_xor_683 = (pyc_xor_677 ^ pyc_or_449); +assign pyc_xor_684 = (pyc_xor_683 ^ pyc_or_668); +assign pyc_and_685 = (pyc_xor_677 & pyc_or_449); +assign pyc_and_686 = (pyc_xor_677 & pyc_or_668); +assign pyc_or_687 = (pyc_and_685 | pyc_and_686); +assign pyc_and_688 = (pyc_or_449 & pyc_or_668); +assign pyc_or_689 = (pyc_or_687 | pyc_and_688); +assign pyc_xor_690 = (pyc_xor_207 ^ pyc_or_194); +assign pyc_xor_691 = (pyc_xor_690 ^ pyc_xor_480); +assign pyc_and_692 = (pyc_xor_207 & pyc_or_194); +assign pyc_and_693 = (pyc_xor_207 & pyc_xor_480); +assign pyc_or_694 = (pyc_and_692 | pyc_and_693); +assign pyc_and_695 = (pyc_or_194 & pyc_xor_480); +assign pyc_or_696 = (pyc_or_694 | pyc_and_695); +assign pyc_xor_697 = (pyc_xor_691 ^ pyc_or_467); +assign pyc_xor_698 = (pyc_xor_697 ^ pyc_or_682); +assign pyc_and_699 = (pyc_xor_691 & pyc_or_467); +assign pyc_and_700 = (pyc_xor_691 & pyc_or_682); +assign pyc_or_701 = (pyc_and_699 | pyc_and_700); +assign pyc_and_702 = (pyc_or_467 & pyc_or_682); +assign pyc_or_703 = (pyc_or_701 | pyc_and_702); +assign pyc_xor_704 = (pyc_xor_225 ^ pyc_or_212); +assign pyc_xor_705 = (pyc_xor_704 ^ pyc_xor_498); +assign pyc_and_706 = (pyc_xor_225 & pyc_or_212); +assign pyc_and_707 = (pyc_xor_225 & pyc_xor_498); +assign pyc_or_708 = (pyc_and_706 | pyc_and_707); +assign pyc_and_709 = (pyc_or_212 & pyc_xor_498); +assign pyc_or_710 = (pyc_or_708 | pyc_and_709); +assign pyc_xor_711 = (pyc_xor_705 ^ pyc_or_485); +assign pyc_xor_712 = (pyc_xor_711 ^ pyc_or_696); +assign pyc_and_713 = (pyc_xor_705 & pyc_or_485); +assign pyc_and_714 = (pyc_xor_705 & pyc_or_696); +assign pyc_or_715 = (pyc_and_713 | pyc_and_714); +assign pyc_and_716 = (pyc_or_485 & pyc_or_696); +assign pyc_or_717 = (pyc_or_715 | pyc_and_716); +assign pyc_xor_718 = (pyc_xor_243 ^ pyc_or_230); +assign pyc_xor_719 = (pyc_xor_718 ^ pyc_xor_516); +assign pyc_and_720 = (pyc_xor_243 & pyc_or_230); +assign pyc_and_721 = (pyc_xor_243 & pyc_xor_516); +assign pyc_or_722 = (pyc_and_720 | pyc_and_721); +assign pyc_and_723 = (pyc_or_230 & pyc_xor_516); +assign pyc_or_724 = (pyc_or_722 | pyc_and_723); +assign pyc_xor_725 = (pyc_xor_719 ^ pyc_or_503); +assign pyc_xor_726 = (pyc_xor_725 ^ pyc_or_710); +assign pyc_and_727 = (pyc_xor_719 & pyc_or_503); +assign pyc_and_728 = (pyc_xor_719 & pyc_or_710); +assign pyc_or_729 = (pyc_and_727 | pyc_and_728); +assign pyc_and_730 = (pyc_or_503 & pyc_or_710); +assign pyc_or_731 = (pyc_or_729 | pyc_and_730); +assign pyc_xor_732 = (pyc_xor_261 ^ pyc_or_248); +assign pyc_xor_733 = (pyc_xor_732 ^ pyc_xor_534); +assign pyc_and_734 = (pyc_xor_261 & pyc_or_248); +assign pyc_and_735 = (pyc_xor_261 & pyc_xor_534); +assign pyc_or_736 = (pyc_and_734 | pyc_and_735); +assign pyc_and_737 = (pyc_or_248 & pyc_xor_534); +assign pyc_or_738 = (pyc_or_736 | pyc_and_737); +assign pyc_xor_739 = (pyc_xor_733 ^ pyc_or_521); +assign pyc_xor_740 = (pyc_xor_739 ^ pyc_or_724); +assign pyc_and_741 = (pyc_xor_733 & pyc_or_521); +assign pyc_and_742 = (pyc_xor_733 & pyc_or_724); +assign pyc_or_743 = (pyc_and_741 | pyc_and_742); +assign pyc_and_744 = (pyc_or_521 & pyc_or_724); +assign pyc_or_745 = (pyc_or_743 | pyc_and_744); +assign pyc_xor_746 = (pyc_xor_274 ^ pyc_or_266); +assign pyc_xor_747 = (pyc_xor_746 ^ pyc_xor_547); +assign pyc_xor_748 = (pyc_xor_747 ^ pyc_or_539); +assign pyc_xor_749 = (pyc_xor_748 ^ pyc_or_738); +assign pyc_concat_750 = {pyc_xor_749, pyc_xor_740, pyc_xor_726, pyc_xor_712, pyc_xor_698, pyc_xor_684, pyc_xor_670, pyc_xor_656, pyc_xor_642, pyc_xor_628, pyc_xor_614, pyc_xor_600, pyc_xor_586, pyc_xor_572, pyc_xor_558, pyc_xor_548}; +assign pyc_concat_751 = {pyc_or_745, pyc_or_731, pyc_or_717, pyc_or_703, pyc_or_689, pyc_or_675, pyc_or_661, pyc_or_647, pyc_or_633, pyc_or_619, pyc_or_605, pyc_or_591, pyc_or_577, pyc_or_563, pyc_constant_1, pyc_constant_1}; +assign pyc_add_752 = (pyc_concat_750 + pyc_concat_751); +assign pyc_comb_753 = pyc_add_752; + +assign PE_INT_WALLACE_DOT8_TREE_W16_sum = pyc_comb_753; + +endmodule + diff --git a/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w19.v b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w19.v new file mode 100644 index 0000000..cde85bd --- /dev/null +++ b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w19.v @@ -0,0 +1,1828 @@ +// Generated by pycc (pyCircuit) +// Module: PE_INT_WALLACE_DOT8_TREE_W19 + +module PE_INT_WALLACE_DOT8_TREE_W19 ( + input [18:0] PE_INT_WALLACE_DOT8_TREE_W19_in0, + input [18:0] PE_INT_WALLACE_DOT8_TREE_W19_in1, + input [18:0] PE_INT_WALLACE_DOT8_TREE_W19_in2, + input [18:0] PE_INT_WALLACE_DOT8_TREE_W19_in3, + input [18:0] PE_INT_WALLACE_DOT8_TREE_W19_in4, + input [18:0] PE_INT_WALLACE_DOT8_TREE_W19_in5, + input [18:0] PE_INT_WALLACE_DOT8_TREE_W19_in6, + input [18:0] PE_INT_WALLACE_DOT8_TREE_W19_in7, + output [18:0] PE_INT_WALLACE_DOT8_TREE_W19_sum +); + +wire [18:0] pyc_add_902; // op=pyc.add +wire pyc_and_10; // op=pyc.and +wire pyc_and_100; // op=pyc.and +wire pyc_and_101; // op=pyc.and +wire pyc_and_103; // op=pyc.and +wire pyc_and_110; // op=pyc.and +wire pyc_and_111; // op=pyc.and +wire pyc_and_113; // op=pyc.and +wire pyc_and_118; // op=pyc.and +wire pyc_and_119; // op=pyc.and +wire pyc_and_121; // op=pyc.and +wire pyc_and_128; // op=pyc.and +wire pyc_and_129; // op=pyc.and +wire pyc_and_131; // op=pyc.and +wire pyc_and_136; // op=pyc.and +wire pyc_and_137; // op=pyc.and +wire pyc_and_139; // op=pyc.and +wire pyc_and_14; // op=pyc.and +wire pyc_and_146; // op=pyc.and +wire pyc_and_147; // op=pyc.and +wire pyc_and_149; // op=pyc.and +wire pyc_and_154; // op=pyc.and +wire pyc_and_155; // op=pyc.and +wire pyc_and_157; // op=pyc.and +wire pyc_and_164; // op=pyc.and +wire pyc_and_165; // op=pyc.and +wire pyc_and_167; // op=pyc.and +wire pyc_and_172; // op=pyc.and +wire pyc_and_173; // op=pyc.and +wire pyc_and_175; // op=pyc.and +wire pyc_and_182; // op=pyc.and +wire pyc_and_183; // op=pyc.and +wire pyc_and_185; // op=pyc.and +wire pyc_and_190; // op=pyc.and +wire pyc_and_191; // op=pyc.and +wire pyc_and_193; // op=pyc.and +wire pyc_and_20; // op=pyc.and +wire pyc_and_200; // op=pyc.and +wire pyc_and_201; // op=pyc.and +wire pyc_and_203; // op=pyc.and +wire pyc_and_208; // op=pyc.and +wire pyc_and_209; // op=pyc.and +wire pyc_and_21; // op=pyc.and +wire pyc_and_211; // op=pyc.and +wire pyc_and_218; // op=pyc.and +wire pyc_and_219; // op=pyc.and +wire pyc_and_221; // op=pyc.and +wire pyc_and_226; // op=pyc.and +wire pyc_and_227; // op=pyc.and +wire pyc_and_229; // op=pyc.and +wire pyc_and_23; // op=pyc.and +wire pyc_and_236; // op=pyc.and +wire pyc_and_237; // op=pyc.and +wire pyc_and_239; // op=pyc.and +wire pyc_and_244; // op=pyc.and +wire pyc_and_245; // op=pyc.and +wire pyc_and_247; // op=pyc.and +wire pyc_and_254; // op=pyc.and +wire pyc_and_255; // op=pyc.and +wire pyc_and_257; // op=pyc.and +wire pyc_and_262; // op=pyc.and +wire pyc_and_263; // op=pyc.and +wire pyc_and_265; // op=pyc.and +wire pyc_and_272; // op=pyc.and +wire pyc_and_273; // op=pyc.and +wire pyc_and_275; // op=pyc.and +wire pyc_and_28; // op=pyc.and +wire pyc_and_280; // op=pyc.and +wire pyc_and_281; // op=pyc.and +wire pyc_and_283; // op=pyc.and +wire pyc_and_29; // op=pyc.and +wire pyc_and_290; // op=pyc.and +wire pyc_and_291; // op=pyc.and +wire pyc_and_293; // op=pyc.and +wire pyc_and_298; // op=pyc.and +wire pyc_and_299; // op=pyc.and +wire pyc_and_301; // op=pyc.and +wire pyc_and_308; // op=pyc.and +wire pyc_and_309; // op=pyc.and +wire pyc_and_31; // op=pyc.and +wire pyc_and_311; // op=pyc.and +wire pyc_and_316; // op=pyc.and +wire pyc_and_317; // op=pyc.and +wire pyc_and_319; // op=pyc.and +wire pyc_and_334; // op=pyc.and +wire pyc_and_335; // op=pyc.and +wire pyc_and_337; // op=pyc.and +wire pyc_and_341; // op=pyc.and +wire pyc_and_347; // op=pyc.and +wire pyc_and_348; // op=pyc.and +wire pyc_and_350; // op=pyc.and +wire pyc_and_355; // op=pyc.and +wire pyc_and_356; // op=pyc.and +wire pyc_and_358; // op=pyc.and +wire pyc_and_365; // op=pyc.and +wire pyc_and_366; // op=pyc.and +wire pyc_and_368; // op=pyc.and +wire pyc_and_373; // op=pyc.and +wire pyc_and_374; // op=pyc.and +wire pyc_and_376; // op=pyc.and +wire pyc_and_38; // op=pyc.and +wire pyc_and_383; // op=pyc.and +wire pyc_and_384; // op=pyc.and +wire pyc_and_386; // op=pyc.and +wire pyc_and_39; // op=pyc.and +wire pyc_and_391; // op=pyc.and +wire pyc_and_392; // op=pyc.and +wire pyc_and_394; // op=pyc.and +wire pyc_and_401; // op=pyc.and +wire pyc_and_402; // op=pyc.and +wire pyc_and_404; // op=pyc.and +wire pyc_and_409; // op=pyc.and +wire pyc_and_41; // op=pyc.and +wire pyc_and_410; // op=pyc.and +wire pyc_and_412; // op=pyc.and +wire pyc_and_419; // op=pyc.and +wire pyc_and_420; // op=pyc.and +wire pyc_and_422; // op=pyc.and +wire pyc_and_427; // op=pyc.and +wire pyc_and_428; // op=pyc.and +wire pyc_and_430; // op=pyc.and +wire pyc_and_437; // op=pyc.and +wire pyc_and_438; // op=pyc.and +wire pyc_and_440; // op=pyc.and +wire pyc_and_445; // op=pyc.and +wire pyc_and_446; // op=pyc.and +wire pyc_and_448; // op=pyc.and +wire pyc_and_455; // op=pyc.and +wire pyc_and_456; // op=pyc.and +wire pyc_and_458; // op=pyc.and +wire pyc_and_46; // op=pyc.and +wire pyc_and_463; // op=pyc.and +wire pyc_and_464; // op=pyc.and +wire pyc_and_466; // op=pyc.and +wire pyc_and_47; // op=pyc.and +wire pyc_and_473; // op=pyc.and +wire pyc_and_474; // op=pyc.and +wire pyc_and_476; // op=pyc.and +wire pyc_and_481; // op=pyc.and +wire pyc_and_482; // op=pyc.and +wire pyc_and_484; // op=pyc.and +wire pyc_and_49; // op=pyc.and +wire pyc_and_491; // op=pyc.and +wire pyc_and_492; // op=pyc.and +wire pyc_and_494; // op=pyc.and +wire pyc_and_499; // op=pyc.and +wire pyc_and_500; // op=pyc.and +wire pyc_and_502; // op=pyc.and +wire pyc_and_509; // op=pyc.and +wire pyc_and_510; // op=pyc.and +wire pyc_and_512; // op=pyc.and +wire pyc_and_517; // op=pyc.and +wire pyc_and_518; // op=pyc.and +wire pyc_and_520; // op=pyc.and +wire pyc_and_527; // op=pyc.and +wire pyc_and_528; // op=pyc.and +wire pyc_and_530; // op=pyc.and +wire pyc_and_535; // op=pyc.and +wire pyc_and_536; // op=pyc.and +wire pyc_and_538; // op=pyc.and +wire pyc_and_545; // op=pyc.and +wire pyc_and_546; // op=pyc.and +wire pyc_and_548; // op=pyc.and +wire pyc_and_553; // op=pyc.and +wire pyc_and_554; // op=pyc.and +wire pyc_and_556; // op=pyc.and +wire pyc_and_56; // op=pyc.and +wire pyc_and_563; // op=pyc.and +wire pyc_and_564; // op=pyc.and +wire pyc_and_566; // op=pyc.and +wire pyc_and_57; // op=pyc.and +wire pyc_and_571; // op=pyc.and +wire pyc_and_572; // op=pyc.and +wire pyc_and_574; // op=pyc.and +wire pyc_and_581; // op=pyc.and +wire pyc_and_582; // op=pyc.and +wire pyc_and_584; // op=pyc.and +wire pyc_and_589; // op=pyc.and +wire pyc_and_59; // op=pyc.and +wire pyc_and_590; // op=pyc.and +wire pyc_and_592; // op=pyc.and +wire pyc_and_599; // op=pyc.and +wire pyc_and_600; // op=pyc.and +wire pyc_and_602; // op=pyc.and +wire pyc_and_607; // op=pyc.and +wire pyc_and_608; // op=pyc.and +wire pyc_and_610; // op=pyc.and +wire pyc_and_617; // op=pyc.and +wire pyc_and_618; // op=pyc.and +wire pyc_and_620; // op=pyc.and +wire pyc_and_625; // op=pyc.and +wire pyc_and_626; // op=pyc.and +wire pyc_and_628; // op=pyc.and +wire pyc_and_635; // op=pyc.and +wire pyc_and_636; // op=pyc.and +wire pyc_and_638; // op=pyc.and +wire pyc_and_64; // op=pyc.and +wire pyc_and_643; // op=pyc.and +wire pyc_and_644; // op=pyc.and +wire pyc_and_646; // op=pyc.and +wire pyc_and_65; // op=pyc.and +wire pyc_and_657; // op=pyc.and +wire pyc_and_660; // op=pyc.and +wire pyc_and_661; // op=pyc.and +wire pyc_and_663; // op=pyc.and +wire pyc_and_667; // op=pyc.and +wire pyc_and_668; // op=pyc.and +wire pyc_and_67; // op=pyc.and +wire pyc_and_670; // op=pyc.and +wire pyc_and_674; // op=pyc.and +wire pyc_and_675; // op=pyc.and +wire pyc_and_677; // op=pyc.and +wire pyc_and_681; // op=pyc.and +wire pyc_and_682; // op=pyc.and +wire pyc_and_684; // op=pyc.and +wire pyc_and_688; // op=pyc.and +wire pyc_and_689; // op=pyc.and +wire pyc_and_691; // op=pyc.and +wire pyc_and_695; // op=pyc.and +wire pyc_and_696; // op=pyc.and +wire pyc_and_698; // op=pyc.and +wire pyc_and_7; // op=pyc.and +wire pyc_and_702; // op=pyc.and +wire pyc_and_703; // op=pyc.and +wire pyc_and_705; // op=pyc.and +wire pyc_and_709; // op=pyc.and +wire pyc_and_710; // op=pyc.and +wire pyc_and_712; // op=pyc.and +wire pyc_and_716; // op=pyc.and +wire pyc_and_717; // op=pyc.and +wire pyc_and_719; // op=pyc.and +wire pyc_and_723; // op=pyc.and +wire pyc_and_724; // op=pyc.and +wire pyc_and_726; // op=pyc.and +wire pyc_and_730; // op=pyc.and +wire pyc_and_731; // op=pyc.and +wire pyc_and_733; // op=pyc.and +wire pyc_and_737; // op=pyc.and +wire pyc_and_738; // op=pyc.and +wire pyc_and_74; // op=pyc.and +wire pyc_and_740; // op=pyc.and +wire pyc_and_744; // op=pyc.and +wire pyc_and_745; // op=pyc.and +wire pyc_and_747; // op=pyc.and +wire pyc_and_75; // op=pyc.and +wire pyc_and_751; // op=pyc.and +wire pyc_and_752; // op=pyc.and +wire pyc_and_754; // op=pyc.and +wire pyc_and_758; // op=pyc.and +wire pyc_and_759; // op=pyc.and +wire pyc_and_761; // op=pyc.and +wire pyc_and_765; // op=pyc.and +wire pyc_and_766; // op=pyc.and +wire pyc_and_768; // op=pyc.and +wire pyc_and_77; // op=pyc.and +wire pyc_and_772; // op=pyc.and +wire pyc_and_773; // op=pyc.and +wire pyc_and_775; // op=pyc.and +wire pyc_and_779; // op=pyc.and +wire pyc_and_780; // op=pyc.and +wire pyc_and_782; // op=pyc.and +wire pyc_and_786; // op=pyc.and +wire pyc_and_787; // op=pyc.and +wire pyc_and_789; // op=pyc.and +wire pyc_and_793; // op=pyc.and +wire pyc_and_794; // op=pyc.and +wire pyc_and_796; // op=pyc.and +wire pyc_and_8; // op=pyc.and +wire pyc_and_800; // op=pyc.and +wire pyc_and_801; // op=pyc.and +wire pyc_and_803; // op=pyc.and +wire pyc_and_807; // op=pyc.and +wire pyc_and_808; // op=pyc.and +wire pyc_and_810; // op=pyc.and +wire pyc_and_814; // op=pyc.and +wire pyc_and_815; // op=pyc.and +wire pyc_and_817; // op=pyc.and +wire pyc_and_82; // op=pyc.and +wire pyc_and_821; // op=pyc.and +wire pyc_and_822; // op=pyc.and +wire pyc_and_824; // op=pyc.and +wire pyc_and_828; // op=pyc.and +wire pyc_and_829; // op=pyc.and +wire pyc_and_83; // op=pyc.and +wire pyc_and_831; // op=pyc.and +wire pyc_and_835; // op=pyc.and +wire pyc_and_836; // op=pyc.and +wire pyc_and_838; // op=pyc.and +wire pyc_and_842; // op=pyc.and +wire pyc_and_843; // op=pyc.and +wire pyc_and_845; // op=pyc.and +wire pyc_and_849; // op=pyc.and +wire pyc_and_85; // op=pyc.and +wire pyc_and_850; // op=pyc.and +wire pyc_and_852; // op=pyc.and +wire pyc_and_856; // op=pyc.and +wire pyc_and_857; // op=pyc.and +wire pyc_and_859; // op=pyc.and +wire pyc_and_863; // op=pyc.and +wire pyc_and_864; // op=pyc.and +wire pyc_and_866; // op=pyc.and +wire pyc_and_870; // op=pyc.and +wire pyc_and_871; // op=pyc.and +wire pyc_and_873; // op=pyc.and +wire pyc_and_877; // op=pyc.and +wire pyc_and_878; // op=pyc.and +wire pyc_and_880; // op=pyc.and +wire pyc_and_884; // op=pyc.and +wire pyc_and_885; // op=pyc.and +wire pyc_and_887; // op=pyc.and +wire pyc_and_891; // op=pyc.and +wire pyc_and_892; // op=pyc.and +wire pyc_and_894; // op=pyc.and +wire pyc_and_92; // op=pyc.and +wire pyc_and_93; // op=pyc.and +wire pyc_and_95; // op=pyc.and +wire [18:0] pyc_comb_903; // op=pyc.comb +wire [18:0] pyc_concat_900; // op=pyc.concat +wire [18:0] pyc_concat_901; // op=pyc.concat +wire pyc_constant_1; // op=pyc.constant +wire pyc_extract_105; // op=pyc.extract +wire pyc_extract_106; // op=pyc.extract +wire pyc_extract_107; // op=pyc.extract +wire pyc_extract_115; // op=pyc.extract +wire pyc_extract_12; // op=pyc.extract +wire pyc_extract_123; // op=pyc.extract +wire pyc_extract_124; // op=pyc.extract +wire pyc_extract_125; // op=pyc.extract +wire pyc_extract_133; // op=pyc.extract +wire pyc_extract_141; // op=pyc.extract +wire pyc_extract_142; // op=pyc.extract +wire pyc_extract_143; // op=pyc.extract +wire pyc_extract_15; // op=pyc.extract +wire pyc_extract_151; // op=pyc.extract +wire pyc_extract_159; // op=pyc.extract +wire pyc_extract_16; // op=pyc.extract +wire pyc_extract_160; // op=pyc.extract +wire pyc_extract_161; // op=pyc.extract +wire pyc_extract_169; // op=pyc.extract +wire pyc_extract_17; // op=pyc.extract +wire pyc_extract_177; // op=pyc.extract +wire pyc_extract_178; // op=pyc.extract +wire pyc_extract_179; // op=pyc.extract +wire pyc_extract_187; // op=pyc.extract +wire pyc_extract_195; // op=pyc.extract +wire pyc_extract_196; // op=pyc.extract +wire pyc_extract_197; // op=pyc.extract +wire pyc_extract_2; // op=pyc.extract +wire pyc_extract_205; // op=pyc.extract +wire pyc_extract_213; // op=pyc.extract +wire pyc_extract_214; // op=pyc.extract +wire pyc_extract_215; // op=pyc.extract +wire pyc_extract_223; // op=pyc.extract +wire pyc_extract_231; // op=pyc.extract +wire pyc_extract_232; // op=pyc.extract +wire pyc_extract_233; // op=pyc.extract +wire pyc_extract_241; // op=pyc.extract +wire pyc_extract_249; // op=pyc.extract +wire pyc_extract_25; // op=pyc.extract +wire pyc_extract_250; // op=pyc.extract +wire pyc_extract_251; // op=pyc.extract +wire pyc_extract_259; // op=pyc.extract +wire pyc_extract_267; // op=pyc.extract +wire pyc_extract_268; // op=pyc.extract +wire pyc_extract_269; // op=pyc.extract +wire pyc_extract_277; // op=pyc.extract +wire pyc_extract_285; // op=pyc.extract +wire pyc_extract_286; // op=pyc.extract +wire pyc_extract_287; // op=pyc.extract +wire pyc_extract_295; // op=pyc.extract +wire pyc_extract_3; // op=pyc.extract +wire pyc_extract_303; // op=pyc.extract +wire pyc_extract_304; // op=pyc.extract +wire pyc_extract_305; // op=pyc.extract +wire pyc_extract_313; // op=pyc.extract +wire pyc_extract_321; // op=pyc.extract +wire pyc_extract_322; // op=pyc.extract +wire pyc_extract_323; // op=pyc.extract +wire pyc_extract_326; // op=pyc.extract +wire pyc_extract_329; // op=pyc.extract +wire pyc_extract_33; // op=pyc.extract +wire pyc_extract_330; // op=pyc.extract +wire pyc_extract_331; // op=pyc.extract +wire pyc_extract_339; // op=pyc.extract +wire pyc_extract_34; // op=pyc.extract +wire pyc_extract_342; // op=pyc.extract +wire pyc_extract_343; // op=pyc.extract +wire pyc_extract_344; // op=pyc.extract +wire pyc_extract_35; // op=pyc.extract +wire pyc_extract_352; // op=pyc.extract +wire pyc_extract_360; // op=pyc.extract +wire pyc_extract_361; // op=pyc.extract +wire pyc_extract_362; // op=pyc.extract +wire pyc_extract_370; // op=pyc.extract +wire pyc_extract_378; // op=pyc.extract +wire pyc_extract_379; // op=pyc.extract +wire pyc_extract_380; // op=pyc.extract +wire pyc_extract_388; // op=pyc.extract +wire pyc_extract_396; // op=pyc.extract +wire pyc_extract_397; // op=pyc.extract +wire pyc_extract_398; // op=pyc.extract +wire pyc_extract_4; // op=pyc.extract +wire pyc_extract_406; // op=pyc.extract +wire pyc_extract_414; // op=pyc.extract +wire pyc_extract_415; // op=pyc.extract +wire pyc_extract_416; // op=pyc.extract +wire pyc_extract_424; // op=pyc.extract +wire pyc_extract_43; // op=pyc.extract +wire pyc_extract_432; // op=pyc.extract +wire pyc_extract_433; // op=pyc.extract +wire pyc_extract_434; // op=pyc.extract +wire pyc_extract_442; // op=pyc.extract +wire pyc_extract_450; // op=pyc.extract +wire pyc_extract_451; // op=pyc.extract +wire pyc_extract_452; // op=pyc.extract +wire pyc_extract_460; // op=pyc.extract +wire pyc_extract_468; // op=pyc.extract +wire pyc_extract_469; // op=pyc.extract +wire pyc_extract_470; // op=pyc.extract +wire pyc_extract_478; // op=pyc.extract +wire pyc_extract_486; // op=pyc.extract +wire pyc_extract_487; // op=pyc.extract +wire pyc_extract_488; // op=pyc.extract +wire pyc_extract_496; // op=pyc.extract +wire pyc_extract_504; // op=pyc.extract +wire pyc_extract_505; // op=pyc.extract +wire pyc_extract_506; // op=pyc.extract +wire pyc_extract_51; // op=pyc.extract +wire pyc_extract_514; // op=pyc.extract +wire pyc_extract_52; // op=pyc.extract +wire pyc_extract_522; // op=pyc.extract +wire pyc_extract_523; // op=pyc.extract +wire pyc_extract_524; // op=pyc.extract +wire pyc_extract_53; // op=pyc.extract +wire pyc_extract_532; // op=pyc.extract +wire pyc_extract_540; // op=pyc.extract +wire pyc_extract_541; // op=pyc.extract +wire pyc_extract_542; // op=pyc.extract +wire pyc_extract_550; // op=pyc.extract +wire pyc_extract_558; // op=pyc.extract +wire pyc_extract_559; // op=pyc.extract +wire pyc_extract_560; // op=pyc.extract +wire pyc_extract_568; // op=pyc.extract +wire pyc_extract_576; // op=pyc.extract +wire pyc_extract_577; // op=pyc.extract +wire pyc_extract_578; // op=pyc.extract +wire pyc_extract_586; // op=pyc.extract +wire pyc_extract_594; // op=pyc.extract +wire pyc_extract_595; // op=pyc.extract +wire pyc_extract_596; // op=pyc.extract +wire pyc_extract_604; // op=pyc.extract +wire pyc_extract_61; // op=pyc.extract +wire pyc_extract_612; // op=pyc.extract +wire pyc_extract_613; // op=pyc.extract +wire pyc_extract_614; // op=pyc.extract +wire pyc_extract_622; // op=pyc.extract +wire pyc_extract_630; // op=pyc.extract +wire pyc_extract_631; // op=pyc.extract +wire pyc_extract_632; // op=pyc.extract +wire pyc_extract_640; // op=pyc.extract +wire pyc_extract_648; // op=pyc.extract +wire pyc_extract_649; // op=pyc.extract +wire pyc_extract_650; // op=pyc.extract +wire pyc_extract_653; // op=pyc.extract +wire pyc_extract_69; // op=pyc.extract +wire pyc_extract_70; // op=pyc.extract +wire pyc_extract_71; // op=pyc.extract +wire pyc_extract_79; // op=pyc.extract +wire pyc_extract_87; // op=pyc.extract +wire pyc_extract_88; // op=pyc.extract +wire pyc_extract_89; // op=pyc.extract +wire pyc_extract_97; // op=pyc.extract +wire pyc_or_102; // op=pyc.or +wire pyc_or_104; // op=pyc.or +wire pyc_or_11; // op=pyc.or +wire pyc_or_112; // op=pyc.or +wire pyc_or_114; // op=pyc.or +wire pyc_or_120; // op=pyc.or +wire pyc_or_122; // op=pyc.or +wire pyc_or_130; // op=pyc.or +wire pyc_or_132; // op=pyc.or +wire pyc_or_138; // op=pyc.or +wire pyc_or_140; // op=pyc.or +wire pyc_or_148; // op=pyc.or +wire pyc_or_150; // op=pyc.or +wire pyc_or_156; // op=pyc.or +wire pyc_or_158; // op=pyc.or +wire pyc_or_166; // op=pyc.or +wire pyc_or_168; // op=pyc.or +wire pyc_or_174; // op=pyc.or +wire pyc_or_176; // op=pyc.or +wire pyc_or_184; // op=pyc.or +wire pyc_or_186; // op=pyc.or +wire pyc_or_192; // op=pyc.or +wire pyc_or_194; // op=pyc.or +wire pyc_or_202; // op=pyc.or +wire pyc_or_204; // op=pyc.or +wire pyc_or_210; // op=pyc.or +wire pyc_or_212; // op=pyc.or +wire pyc_or_22; // op=pyc.or +wire pyc_or_220; // op=pyc.or +wire pyc_or_222; // op=pyc.or +wire pyc_or_228; // op=pyc.or +wire pyc_or_230; // op=pyc.or +wire pyc_or_238; // op=pyc.or +wire pyc_or_24; // op=pyc.or +wire pyc_or_240; // op=pyc.or +wire pyc_or_246; // op=pyc.or +wire pyc_or_248; // op=pyc.or +wire pyc_or_256; // op=pyc.or +wire pyc_or_258; // op=pyc.or +wire pyc_or_264; // op=pyc.or +wire pyc_or_266; // op=pyc.or +wire pyc_or_274; // op=pyc.or +wire pyc_or_276; // op=pyc.or +wire pyc_or_282; // op=pyc.or +wire pyc_or_284; // op=pyc.or +wire pyc_or_292; // op=pyc.or +wire pyc_or_294; // op=pyc.or +wire pyc_or_30; // op=pyc.or +wire pyc_or_300; // op=pyc.or +wire pyc_or_302; // op=pyc.or +wire pyc_or_310; // op=pyc.or +wire pyc_or_312; // op=pyc.or +wire pyc_or_318; // op=pyc.or +wire pyc_or_32; // op=pyc.or +wire pyc_or_320; // op=pyc.or +wire pyc_or_336; // op=pyc.or +wire pyc_or_338; // op=pyc.or +wire pyc_or_349; // op=pyc.or +wire pyc_or_351; // op=pyc.or +wire pyc_or_357; // op=pyc.or +wire pyc_or_359; // op=pyc.or +wire pyc_or_367; // op=pyc.or +wire pyc_or_369; // op=pyc.or +wire pyc_or_375; // op=pyc.or +wire pyc_or_377; // op=pyc.or +wire pyc_or_385; // op=pyc.or +wire pyc_or_387; // op=pyc.or +wire pyc_or_393; // op=pyc.or +wire pyc_or_395; // op=pyc.or +wire pyc_or_40; // op=pyc.or +wire pyc_or_403; // op=pyc.or +wire pyc_or_405; // op=pyc.or +wire pyc_or_411; // op=pyc.or +wire pyc_or_413; // op=pyc.or +wire pyc_or_42; // op=pyc.or +wire pyc_or_421; // op=pyc.or +wire pyc_or_423; // op=pyc.or +wire pyc_or_429; // op=pyc.or +wire pyc_or_431; // op=pyc.or +wire pyc_or_439; // op=pyc.or +wire pyc_or_441; // op=pyc.or +wire pyc_or_447; // op=pyc.or +wire pyc_or_449; // op=pyc.or +wire pyc_or_457; // op=pyc.or +wire pyc_or_459; // op=pyc.or +wire pyc_or_465; // op=pyc.or +wire pyc_or_467; // op=pyc.or +wire pyc_or_475; // op=pyc.or +wire pyc_or_477; // op=pyc.or +wire pyc_or_48; // op=pyc.or +wire pyc_or_483; // op=pyc.or +wire pyc_or_485; // op=pyc.or +wire pyc_or_493; // op=pyc.or +wire pyc_or_495; // op=pyc.or +wire pyc_or_50; // op=pyc.or +wire pyc_or_501; // op=pyc.or +wire pyc_or_503; // op=pyc.or +wire pyc_or_511; // op=pyc.or +wire pyc_or_513; // op=pyc.or +wire pyc_or_519; // op=pyc.or +wire pyc_or_521; // op=pyc.or +wire pyc_or_529; // op=pyc.or +wire pyc_or_531; // op=pyc.or +wire pyc_or_537; // op=pyc.or +wire pyc_or_539; // op=pyc.or +wire pyc_or_547; // op=pyc.or +wire pyc_or_549; // op=pyc.or +wire pyc_or_555; // op=pyc.or +wire pyc_or_557; // op=pyc.or +wire pyc_or_565; // op=pyc.or +wire pyc_or_567; // op=pyc.or +wire pyc_or_573; // op=pyc.or +wire pyc_or_575; // op=pyc.or +wire pyc_or_58; // op=pyc.or +wire pyc_or_583; // op=pyc.or +wire pyc_or_585; // op=pyc.or +wire pyc_or_591; // op=pyc.or +wire pyc_or_593; // op=pyc.or +wire pyc_or_60; // op=pyc.or +wire pyc_or_601; // op=pyc.or +wire pyc_or_603; // op=pyc.or +wire pyc_or_609; // op=pyc.or +wire pyc_or_611; // op=pyc.or +wire pyc_or_619; // op=pyc.or +wire pyc_or_621; // op=pyc.or +wire pyc_or_627; // op=pyc.or +wire pyc_or_629; // op=pyc.or +wire pyc_or_637; // op=pyc.or +wire pyc_or_639; // op=pyc.or +wire pyc_or_645; // op=pyc.or +wire pyc_or_647; // op=pyc.or +wire pyc_or_66; // op=pyc.or +wire pyc_or_662; // op=pyc.or +wire pyc_or_664; // op=pyc.or +wire pyc_or_669; // op=pyc.or +wire pyc_or_671; // op=pyc.or +wire pyc_or_676; // op=pyc.or +wire pyc_or_678; // op=pyc.or +wire pyc_or_68; // op=pyc.or +wire pyc_or_683; // op=pyc.or +wire pyc_or_685; // op=pyc.or +wire pyc_or_690; // op=pyc.or +wire pyc_or_692; // op=pyc.or +wire pyc_or_697; // op=pyc.or +wire pyc_or_699; // op=pyc.or +wire pyc_or_704; // op=pyc.or +wire pyc_or_706; // op=pyc.or +wire pyc_or_711; // op=pyc.or +wire pyc_or_713; // op=pyc.or +wire pyc_or_718; // op=pyc.or +wire pyc_or_720; // op=pyc.or +wire pyc_or_725; // op=pyc.or +wire pyc_or_727; // op=pyc.or +wire pyc_or_732; // op=pyc.or +wire pyc_or_734; // op=pyc.or +wire pyc_or_739; // op=pyc.or +wire pyc_or_741; // op=pyc.or +wire pyc_or_746; // op=pyc.or +wire pyc_or_748; // op=pyc.or +wire pyc_or_753; // op=pyc.or +wire pyc_or_755; // op=pyc.or +wire pyc_or_76; // op=pyc.or +wire pyc_or_760; // op=pyc.or +wire pyc_or_762; // op=pyc.or +wire pyc_or_767; // op=pyc.or +wire pyc_or_769; // op=pyc.or +wire pyc_or_774; // op=pyc.or +wire pyc_or_776; // op=pyc.or +wire pyc_or_78; // op=pyc.or +wire pyc_or_781; // op=pyc.or +wire pyc_or_783; // op=pyc.or +wire pyc_or_788; // op=pyc.or +wire pyc_or_790; // op=pyc.or +wire pyc_or_795; // op=pyc.or +wire pyc_or_797; // op=pyc.or +wire pyc_or_802; // op=pyc.or +wire pyc_or_804; // op=pyc.or +wire pyc_or_809; // op=pyc.or +wire pyc_or_811; // op=pyc.or +wire pyc_or_816; // op=pyc.or +wire pyc_or_818; // op=pyc.or +wire pyc_or_823; // op=pyc.or +wire pyc_or_825; // op=pyc.or +wire pyc_or_830; // op=pyc.or +wire pyc_or_832; // op=pyc.or +wire pyc_or_837; // op=pyc.or +wire pyc_or_839; // op=pyc.or +wire pyc_or_84; // op=pyc.or +wire pyc_or_844; // op=pyc.or +wire pyc_or_846; // op=pyc.or +wire pyc_or_851; // op=pyc.or +wire pyc_or_853; // op=pyc.or +wire pyc_or_858; // op=pyc.or +wire pyc_or_86; // op=pyc.or +wire pyc_or_860; // op=pyc.or +wire pyc_or_865; // op=pyc.or +wire pyc_or_867; // op=pyc.or +wire pyc_or_872; // op=pyc.or +wire pyc_or_874; // op=pyc.or +wire pyc_or_879; // op=pyc.or +wire pyc_or_881; // op=pyc.or +wire pyc_or_886; // op=pyc.or +wire pyc_or_888; // op=pyc.or +wire pyc_or_893; // op=pyc.or +wire pyc_or_895; // op=pyc.or +wire pyc_or_9; // op=pyc.or +wire pyc_or_94; // op=pyc.or +wire pyc_or_96; // op=pyc.or +wire pyc_xor_108; // op=pyc.xor +wire pyc_xor_109; // op=pyc.xor +wire pyc_xor_116; // op=pyc.xor +wire pyc_xor_117; // op=pyc.xor +wire pyc_xor_126; // op=pyc.xor +wire pyc_xor_127; // op=pyc.xor +wire pyc_xor_13; // op=pyc.xor +wire pyc_xor_134; // op=pyc.xor +wire pyc_xor_135; // op=pyc.xor +wire pyc_xor_144; // op=pyc.xor +wire pyc_xor_145; // op=pyc.xor +wire pyc_xor_152; // op=pyc.xor +wire pyc_xor_153; // op=pyc.xor +wire pyc_xor_162; // op=pyc.xor +wire pyc_xor_163; // op=pyc.xor +wire pyc_xor_170; // op=pyc.xor +wire pyc_xor_171; // op=pyc.xor +wire pyc_xor_18; // op=pyc.xor +wire pyc_xor_180; // op=pyc.xor +wire pyc_xor_181; // op=pyc.xor +wire pyc_xor_188; // op=pyc.xor +wire pyc_xor_189; // op=pyc.xor +wire pyc_xor_19; // op=pyc.xor +wire pyc_xor_198; // op=pyc.xor +wire pyc_xor_199; // op=pyc.xor +wire pyc_xor_206; // op=pyc.xor +wire pyc_xor_207; // op=pyc.xor +wire pyc_xor_216; // op=pyc.xor +wire pyc_xor_217; // op=pyc.xor +wire pyc_xor_224; // op=pyc.xor +wire pyc_xor_225; // op=pyc.xor +wire pyc_xor_234; // op=pyc.xor +wire pyc_xor_235; // op=pyc.xor +wire pyc_xor_242; // op=pyc.xor +wire pyc_xor_243; // op=pyc.xor +wire pyc_xor_252; // op=pyc.xor +wire pyc_xor_253; // op=pyc.xor +wire pyc_xor_26; // op=pyc.xor +wire pyc_xor_260; // op=pyc.xor +wire pyc_xor_261; // op=pyc.xor +wire pyc_xor_27; // op=pyc.xor +wire pyc_xor_270; // op=pyc.xor +wire pyc_xor_271; // op=pyc.xor +wire pyc_xor_278; // op=pyc.xor +wire pyc_xor_279; // op=pyc.xor +wire pyc_xor_288; // op=pyc.xor +wire pyc_xor_289; // op=pyc.xor +wire pyc_xor_296; // op=pyc.xor +wire pyc_xor_297; // op=pyc.xor +wire pyc_xor_306; // op=pyc.xor +wire pyc_xor_307; // op=pyc.xor +wire pyc_xor_314; // op=pyc.xor +wire pyc_xor_315; // op=pyc.xor +wire pyc_xor_324; // op=pyc.xor +wire pyc_xor_325; // op=pyc.xor +wire pyc_xor_327; // op=pyc.xor +wire pyc_xor_328; // op=pyc.xor +wire pyc_xor_332; // op=pyc.xor +wire pyc_xor_333; // op=pyc.xor +wire pyc_xor_340; // op=pyc.xor +wire pyc_xor_345; // op=pyc.xor +wire pyc_xor_346; // op=pyc.xor +wire pyc_xor_353; // op=pyc.xor +wire pyc_xor_354; // op=pyc.xor +wire pyc_xor_36; // op=pyc.xor +wire pyc_xor_363; // op=pyc.xor +wire pyc_xor_364; // op=pyc.xor +wire pyc_xor_37; // op=pyc.xor +wire pyc_xor_371; // op=pyc.xor +wire pyc_xor_372; // op=pyc.xor +wire pyc_xor_381; // op=pyc.xor +wire pyc_xor_382; // op=pyc.xor +wire pyc_xor_389; // op=pyc.xor +wire pyc_xor_390; // op=pyc.xor +wire pyc_xor_399; // op=pyc.xor +wire pyc_xor_400; // op=pyc.xor +wire pyc_xor_407; // op=pyc.xor +wire pyc_xor_408; // op=pyc.xor +wire pyc_xor_417; // op=pyc.xor +wire pyc_xor_418; // op=pyc.xor +wire pyc_xor_425; // op=pyc.xor +wire pyc_xor_426; // op=pyc.xor +wire pyc_xor_435; // op=pyc.xor +wire pyc_xor_436; // op=pyc.xor +wire pyc_xor_44; // op=pyc.xor +wire pyc_xor_443; // op=pyc.xor +wire pyc_xor_444; // op=pyc.xor +wire pyc_xor_45; // op=pyc.xor +wire pyc_xor_453; // op=pyc.xor +wire pyc_xor_454; // op=pyc.xor +wire pyc_xor_461; // op=pyc.xor +wire pyc_xor_462; // op=pyc.xor +wire pyc_xor_471; // op=pyc.xor +wire pyc_xor_472; // op=pyc.xor +wire pyc_xor_479; // op=pyc.xor +wire pyc_xor_480; // op=pyc.xor +wire pyc_xor_489; // op=pyc.xor +wire pyc_xor_490; // op=pyc.xor +wire pyc_xor_497; // op=pyc.xor +wire pyc_xor_498; // op=pyc.xor +wire pyc_xor_5; // op=pyc.xor +wire pyc_xor_507; // op=pyc.xor +wire pyc_xor_508; // op=pyc.xor +wire pyc_xor_515; // op=pyc.xor +wire pyc_xor_516; // op=pyc.xor +wire pyc_xor_525; // op=pyc.xor +wire pyc_xor_526; // op=pyc.xor +wire pyc_xor_533; // op=pyc.xor +wire pyc_xor_534; // op=pyc.xor +wire pyc_xor_54; // op=pyc.xor +wire pyc_xor_543; // op=pyc.xor +wire pyc_xor_544; // op=pyc.xor +wire pyc_xor_55; // op=pyc.xor +wire pyc_xor_551; // op=pyc.xor +wire pyc_xor_552; // op=pyc.xor +wire pyc_xor_561; // op=pyc.xor +wire pyc_xor_562; // op=pyc.xor +wire pyc_xor_569; // op=pyc.xor +wire pyc_xor_570; // op=pyc.xor +wire pyc_xor_579; // op=pyc.xor +wire pyc_xor_580; // op=pyc.xor +wire pyc_xor_587; // op=pyc.xor +wire pyc_xor_588; // op=pyc.xor +wire pyc_xor_597; // op=pyc.xor +wire pyc_xor_598; // op=pyc.xor +wire pyc_xor_6; // op=pyc.xor +wire pyc_xor_605; // op=pyc.xor +wire pyc_xor_606; // op=pyc.xor +wire pyc_xor_615; // op=pyc.xor +wire pyc_xor_616; // op=pyc.xor +wire pyc_xor_62; // op=pyc.xor +wire pyc_xor_623; // op=pyc.xor +wire pyc_xor_624; // op=pyc.xor +wire pyc_xor_63; // op=pyc.xor +wire pyc_xor_633; // op=pyc.xor +wire pyc_xor_634; // op=pyc.xor +wire pyc_xor_641; // op=pyc.xor +wire pyc_xor_642; // op=pyc.xor +wire pyc_xor_651; // op=pyc.xor +wire pyc_xor_652; // op=pyc.xor +wire pyc_xor_654; // op=pyc.xor +wire pyc_xor_655; // op=pyc.xor +wire pyc_xor_656; // op=pyc.xor +wire pyc_xor_658; // op=pyc.xor +wire pyc_xor_659; // op=pyc.xor +wire pyc_xor_665; // op=pyc.xor +wire pyc_xor_666; // op=pyc.xor +wire pyc_xor_672; // op=pyc.xor +wire pyc_xor_673; // op=pyc.xor +wire pyc_xor_679; // op=pyc.xor +wire pyc_xor_680; // op=pyc.xor +wire pyc_xor_686; // op=pyc.xor +wire pyc_xor_687; // op=pyc.xor +wire pyc_xor_693; // op=pyc.xor +wire pyc_xor_694; // op=pyc.xor +wire pyc_xor_700; // op=pyc.xor +wire pyc_xor_701; // op=pyc.xor +wire pyc_xor_707; // op=pyc.xor +wire pyc_xor_708; // op=pyc.xor +wire pyc_xor_714; // op=pyc.xor +wire pyc_xor_715; // op=pyc.xor +wire pyc_xor_72; // op=pyc.xor +wire pyc_xor_721; // op=pyc.xor +wire pyc_xor_722; // op=pyc.xor +wire pyc_xor_728; // op=pyc.xor +wire pyc_xor_729; // op=pyc.xor +wire pyc_xor_73; // op=pyc.xor +wire pyc_xor_735; // op=pyc.xor +wire pyc_xor_736; // op=pyc.xor +wire pyc_xor_742; // op=pyc.xor +wire pyc_xor_743; // op=pyc.xor +wire pyc_xor_749; // op=pyc.xor +wire pyc_xor_750; // op=pyc.xor +wire pyc_xor_756; // op=pyc.xor +wire pyc_xor_757; // op=pyc.xor +wire pyc_xor_763; // op=pyc.xor +wire pyc_xor_764; // op=pyc.xor +wire pyc_xor_770; // op=pyc.xor +wire pyc_xor_771; // op=pyc.xor +wire pyc_xor_777; // op=pyc.xor +wire pyc_xor_778; // op=pyc.xor +wire pyc_xor_784; // op=pyc.xor +wire pyc_xor_785; // op=pyc.xor +wire pyc_xor_791; // op=pyc.xor +wire pyc_xor_792; // op=pyc.xor +wire pyc_xor_798; // op=pyc.xor +wire pyc_xor_799; // op=pyc.xor +wire pyc_xor_80; // op=pyc.xor +wire pyc_xor_805; // op=pyc.xor +wire pyc_xor_806; // op=pyc.xor +wire pyc_xor_81; // op=pyc.xor +wire pyc_xor_812; // op=pyc.xor +wire pyc_xor_813; // op=pyc.xor +wire pyc_xor_819; // op=pyc.xor +wire pyc_xor_820; // op=pyc.xor +wire pyc_xor_826; // op=pyc.xor +wire pyc_xor_827; // op=pyc.xor +wire pyc_xor_833; // op=pyc.xor +wire pyc_xor_834; // op=pyc.xor +wire pyc_xor_840; // op=pyc.xor +wire pyc_xor_841; // op=pyc.xor +wire pyc_xor_847; // op=pyc.xor +wire pyc_xor_848; // op=pyc.xor +wire pyc_xor_854; // op=pyc.xor +wire pyc_xor_855; // op=pyc.xor +wire pyc_xor_861; // op=pyc.xor +wire pyc_xor_862; // op=pyc.xor +wire pyc_xor_868; // op=pyc.xor +wire pyc_xor_869; // op=pyc.xor +wire pyc_xor_875; // op=pyc.xor +wire pyc_xor_876; // op=pyc.xor +wire pyc_xor_882; // op=pyc.xor +wire pyc_xor_883; // op=pyc.xor +wire pyc_xor_889; // op=pyc.xor +wire pyc_xor_890; // op=pyc.xor +wire pyc_xor_896; // op=pyc.xor +wire pyc_xor_897; // op=pyc.xor +wire pyc_xor_898; // op=pyc.xor +wire pyc_xor_899; // op=pyc.xor +wire pyc_xor_90; // op=pyc.xor +wire pyc_xor_91; // op=pyc.xor +wire pyc_xor_98; // op=pyc.xor +wire pyc_xor_99; // op=pyc.xor + +// --- Combinational (netlist) +assign pyc_constant_1 = 1'd0; +assign pyc_extract_2 = PE_INT_WALLACE_DOT8_TREE_W19_in0[0]; +assign pyc_extract_3 = PE_INT_WALLACE_DOT8_TREE_W19_in1[0]; +assign pyc_extract_4 = PE_INT_WALLACE_DOT8_TREE_W19_in2[0]; +assign pyc_xor_5 = (pyc_extract_2 ^ pyc_extract_3); +assign pyc_xor_6 = (pyc_xor_5 ^ pyc_extract_4); +assign pyc_and_7 = (pyc_extract_2 & pyc_extract_3); +assign pyc_and_8 = (pyc_extract_2 & pyc_extract_4); +assign pyc_or_9 = (pyc_and_7 | pyc_and_8); +assign pyc_and_10 = (pyc_extract_3 & pyc_extract_4); +assign pyc_or_11 = (pyc_or_9 | pyc_and_10); +assign pyc_extract_12 = PE_INT_WALLACE_DOT8_TREE_W19_in3[0]; +assign pyc_xor_13 = (pyc_xor_6 ^ pyc_extract_12); +assign pyc_and_14 = (pyc_xor_6 & pyc_extract_12); +assign pyc_extract_15 = PE_INT_WALLACE_DOT8_TREE_W19_in0[1]; +assign pyc_extract_16 = PE_INT_WALLACE_DOT8_TREE_W19_in1[1]; +assign pyc_extract_17 = PE_INT_WALLACE_DOT8_TREE_W19_in2[1]; +assign pyc_xor_18 = (pyc_extract_15 ^ pyc_extract_16); +assign pyc_xor_19 = (pyc_xor_18 ^ pyc_extract_17); +assign pyc_and_20 = (pyc_extract_15 & pyc_extract_16); +assign pyc_and_21 = (pyc_extract_15 & pyc_extract_17); +assign pyc_or_22 = (pyc_and_20 | pyc_and_21); +assign pyc_and_23 = (pyc_extract_16 & pyc_extract_17); +assign pyc_or_24 = (pyc_or_22 | pyc_and_23); +assign pyc_extract_25 = PE_INT_WALLACE_DOT8_TREE_W19_in3[1]; +assign pyc_xor_26 = (pyc_xor_19 ^ pyc_extract_25); +assign pyc_xor_27 = (pyc_xor_26 ^ pyc_or_11); +assign pyc_and_28 = (pyc_xor_19 & pyc_extract_25); +assign pyc_and_29 = (pyc_xor_19 & pyc_or_11); +assign pyc_or_30 = (pyc_and_28 | pyc_and_29); +assign pyc_and_31 = (pyc_extract_25 & pyc_or_11); +assign pyc_or_32 = (pyc_or_30 | pyc_and_31); +assign pyc_extract_33 = PE_INT_WALLACE_DOT8_TREE_W19_in0[2]; +assign pyc_extract_34 = PE_INT_WALLACE_DOT8_TREE_W19_in1[2]; +assign pyc_extract_35 = PE_INT_WALLACE_DOT8_TREE_W19_in2[2]; +assign pyc_xor_36 = (pyc_extract_33 ^ pyc_extract_34); +assign pyc_xor_37 = (pyc_xor_36 ^ pyc_extract_35); +assign pyc_and_38 = (pyc_extract_33 & pyc_extract_34); +assign pyc_and_39 = (pyc_extract_33 & pyc_extract_35); +assign pyc_or_40 = (pyc_and_38 | pyc_and_39); +assign pyc_and_41 = (pyc_extract_34 & pyc_extract_35); +assign pyc_or_42 = (pyc_or_40 | pyc_and_41); +assign pyc_extract_43 = PE_INT_WALLACE_DOT8_TREE_W19_in3[2]; +assign pyc_xor_44 = (pyc_xor_37 ^ pyc_extract_43); +assign pyc_xor_45 = (pyc_xor_44 ^ pyc_or_24); +assign pyc_and_46 = (pyc_xor_37 & pyc_extract_43); +assign pyc_and_47 = (pyc_xor_37 & pyc_or_24); +assign pyc_or_48 = (pyc_and_46 | pyc_and_47); +assign pyc_and_49 = (pyc_extract_43 & pyc_or_24); +assign pyc_or_50 = (pyc_or_48 | pyc_and_49); +assign pyc_extract_51 = PE_INT_WALLACE_DOT8_TREE_W19_in0[3]; +assign pyc_extract_52 = PE_INT_WALLACE_DOT8_TREE_W19_in1[3]; +assign pyc_extract_53 = PE_INT_WALLACE_DOT8_TREE_W19_in2[3]; +assign pyc_xor_54 = (pyc_extract_51 ^ pyc_extract_52); +assign pyc_xor_55 = (pyc_xor_54 ^ pyc_extract_53); +assign pyc_and_56 = (pyc_extract_51 & pyc_extract_52); +assign pyc_and_57 = (pyc_extract_51 & pyc_extract_53); +assign pyc_or_58 = (pyc_and_56 | pyc_and_57); +assign pyc_and_59 = (pyc_extract_52 & pyc_extract_53); +assign pyc_or_60 = (pyc_or_58 | pyc_and_59); +assign pyc_extract_61 = PE_INT_WALLACE_DOT8_TREE_W19_in3[3]; +assign pyc_xor_62 = (pyc_xor_55 ^ pyc_extract_61); +assign pyc_xor_63 = (pyc_xor_62 ^ pyc_or_42); +assign pyc_and_64 = (pyc_xor_55 & pyc_extract_61); +assign pyc_and_65 = (pyc_xor_55 & pyc_or_42); +assign pyc_or_66 = (pyc_and_64 | pyc_and_65); +assign pyc_and_67 = (pyc_extract_61 & pyc_or_42); +assign pyc_or_68 = (pyc_or_66 | pyc_and_67); +assign pyc_extract_69 = PE_INT_WALLACE_DOT8_TREE_W19_in0[4]; +assign pyc_extract_70 = PE_INT_WALLACE_DOT8_TREE_W19_in1[4]; +assign pyc_extract_71 = PE_INT_WALLACE_DOT8_TREE_W19_in2[4]; +assign pyc_xor_72 = (pyc_extract_69 ^ pyc_extract_70); +assign pyc_xor_73 = (pyc_xor_72 ^ pyc_extract_71); +assign pyc_and_74 = (pyc_extract_69 & pyc_extract_70); +assign pyc_and_75 = (pyc_extract_69 & pyc_extract_71); +assign pyc_or_76 = (pyc_and_74 | pyc_and_75); +assign pyc_and_77 = (pyc_extract_70 & pyc_extract_71); +assign pyc_or_78 = (pyc_or_76 | pyc_and_77); +assign pyc_extract_79 = PE_INT_WALLACE_DOT8_TREE_W19_in3[4]; +assign pyc_xor_80 = (pyc_xor_73 ^ pyc_extract_79); +assign pyc_xor_81 = (pyc_xor_80 ^ pyc_or_60); +assign pyc_and_82 = (pyc_xor_73 & pyc_extract_79); +assign pyc_and_83 = (pyc_xor_73 & pyc_or_60); +assign pyc_or_84 = (pyc_and_82 | pyc_and_83); +assign pyc_and_85 = (pyc_extract_79 & pyc_or_60); +assign pyc_or_86 = (pyc_or_84 | pyc_and_85); +assign pyc_extract_87 = PE_INT_WALLACE_DOT8_TREE_W19_in0[5]; +assign pyc_extract_88 = PE_INT_WALLACE_DOT8_TREE_W19_in1[5]; +assign pyc_extract_89 = PE_INT_WALLACE_DOT8_TREE_W19_in2[5]; +assign pyc_xor_90 = (pyc_extract_87 ^ pyc_extract_88); +assign pyc_xor_91 = (pyc_xor_90 ^ pyc_extract_89); +assign pyc_and_92 = (pyc_extract_87 & pyc_extract_88); +assign pyc_and_93 = (pyc_extract_87 & pyc_extract_89); +assign pyc_or_94 = (pyc_and_92 | pyc_and_93); +assign pyc_and_95 = (pyc_extract_88 & pyc_extract_89); +assign pyc_or_96 = (pyc_or_94 | pyc_and_95); +assign pyc_extract_97 = PE_INT_WALLACE_DOT8_TREE_W19_in3[5]; +assign pyc_xor_98 = (pyc_xor_91 ^ pyc_extract_97); +assign pyc_xor_99 = (pyc_xor_98 ^ pyc_or_78); +assign pyc_and_100 = (pyc_xor_91 & pyc_extract_97); +assign pyc_and_101 = (pyc_xor_91 & pyc_or_78); +assign pyc_or_102 = (pyc_and_100 | pyc_and_101); +assign pyc_and_103 = (pyc_extract_97 & pyc_or_78); +assign pyc_or_104 = (pyc_or_102 | pyc_and_103); +assign pyc_extract_105 = PE_INT_WALLACE_DOT8_TREE_W19_in0[6]; +assign pyc_extract_106 = PE_INT_WALLACE_DOT8_TREE_W19_in1[6]; +assign pyc_extract_107 = PE_INT_WALLACE_DOT8_TREE_W19_in2[6]; +assign pyc_xor_108 = (pyc_extract_105 ^ pyc_extract_106); +assign pyc_xor_109 = (pyc_xor_108 ^ pyc_extract_107); +assign pyc_and_110 = (pyc_extract_105 & pyc_extract_106); +assign pyc_and_111 = (pyc_extract_105 & pyc_extract_107); +assign pyc_or_112 = (pyc_and_110 | pyc_and_111); +assign pyc_and_113 = (pyc_extract_106 & pyc_extract_107); +assign pyc_or_114 = (pyc_or_112 | pyc_and_113); +assign pyc_extract_115 = PE_INT_WALLACE_DOT8_TREE_W19_in3[6]; +assign pyc_xor_116 = (pyc_xor_109 ^ pyc_extract_115); +assign pyc_xor_117 = (pyc_xor_116 ^ pyc_or_96); +assign pyc_and_118 = (pyc_xor_109 & pyc_extract_115); +assign pyc_and_119 = (pyc_xor_109 & pyc_or_96); +assign pyc_or_120 = (pyc_and_118 | pyc_and_119); +assign pyc_and_121 = (pyc_extract_115 & pyc_or_96); +assign pyc_or_122 = (pyc_or_120 | pyc_and_121); +assign pyc_extract_123 = PE_INT_WALLACE_DOT8_TREE_W19_in0[7]; +assign pyc_extract_124 = PE_INT_WALLACE_DOT8_TREE_W19_in1[7]; +assign pyc_extract_125 = PE_INT_WALLACE_DOT8_TREE_W19_in2[7]; +assign pyc_xor_126 = (pyc_extract_123 ^ pyc_extract_124); +assign pyc_xor_127 = (pyc_xor_126 ^ pyc_extract_125); +assign pyc_and_128 = (pyc_extract_123 & pyc_extract_124); +assign pyc_and_129 = (pyc_extract_123 & pyc_extract_125); +assign pyc_or_130 = (pyc_and_128 | pyc_and_129); +assign pyc_and_131 = (pyc_extract_124 & pyc_extract_125); +assign pyc_or_132 = (pyc_or_130 | pyc_and_131); +assign pyc_extract_133 = PE_INT_WALLACE_DOT8_TREE_W19_in3[7]; +assign pyc_xor_134 = (pyc_xor_127 ^ pyc_extract_133); +assign pyc_xor_135 = (pyc_xor_134 ^ pyc_or_114); +assign pyc_and_136 = (pyc_xor_127 & pyc_extract_133); +assign pyc_and_137 = (pyc_xor_127 & pyc_or_114); +assign pyc_or_138 = (pyc_and_136 | pyc_and_137); +assign pyc_and_139 = (pyc_extract_133 & pyc_or_114); +assign pyc_or_140 = (pyc_or_138 | pyc_and_139); +assign pyc_extract_141 = PE_INT_WALLACE_DOT8_TREE_W19_in0[8]; +assign pyc_extract_142 = PE_INT_WALLACE_DOT8_TREE_W19_in1[8]; +assign pyc_extract_143 = PE_INT_WALLACE_DOT8_TREE_W19_in2[8]; +assign pyc_xor_144 = (pyc_extract_141 ^ pyc_extract_142); +assign pyc_xor_145 = (pyc_xor_144 ^ pyc_extract_143); +assign pyc_and_146 = (pyc_extract_141 & pyc_extract_142); +assign pyc_and_147 = (pyc_extract_141 & pyc_extract_143); +assign pyc_or_148 = (pyc_and_146 | pyc_and_147); +assign pyc_and_149 = (pyc_extract_142 & pyc_extract_143); +assign pyc_or_150 = (pyc_or_148 | pyc_and_149); +assign pyc_extract_151 = PE_INT_WALLACE_DOT8_TREE_W19_in3[8]; +assign pyc_xor_152 = (pyc_xor_145 ^ pyc_extract_151); +assign pyc_xor_153 = (pyc_xor_152 ^ pyc_or_132); +assign pyc_and_154 = (pyc_xor_145 & pyc_extract_151); +assign pyc_and_155 = (pyc_xor_145 & pyc_or_132); +assign pyc_or_156 = (pyc_and_154 | pyc_and_155); +assign pyc_and_157 = (pyc_extract_151 & pyc_or_132); +assign pyc_or_158 = (pyc_or_156 | pyc_and_157); +assign pyc_extract_159 = PE_INT_WALLACE_DOT8_TREE_W19_in0[9]; +assign pyc_extract_160 = PE_INT_WALLACE_DOT8_TREE_W19_in1[9]; +assign pyc_extract_161 = PE_INT_WALLACE_DOT8_TREE_W19_in2[9]; +assign pyc_xor_162 = (pyc_extract_159 ^ pyc_extract_160); +assign pyc_xor_163 = (pyc_xor_162 ^ pyc_extract_161); +assign pyc_and_164 = (pyc_extract_159 & pyc_extract_160); +assign pyc_and_165 = (pyc_extract_159 & pyc_extract_161); +assign pyc_or_166 = (pyc_and_164 | pyc_and_165); +assign pyc_and_167 = (pyc_extract_160 & pyc_extract_161); +assign pyc_or_168 = (pyc_or_166 | pyc_and_167); +assign pyc_extract_169 = PE_INT_WALLACE_DOT8_TREE_W19_in3[9]; +assign pyc_xor_170 = (pyc_xor_163 ^ pyc_extract_169); +assign pyc_xor_171 = (pyc_xor_170 ^ pyc_or_150); +assign pyc_and_172 = (pyc_xor_163 & pyc_extract_169); +assign pyc_and_173 = (pyc_xor_163 & pyc_or_150); +assign pyc_or_174 = (pyc_and_172 | pyc_and_173); +assign pyc_and_175 = (pyc_extract_169 & pyc_or_150); +assign pyc_or_176 = (pyc_or_174 | pyc_and_175); +assign pyc_extract_177 = PE_INT_WALLACE_DOT8_TREE_W19_in0[10]; +assign pyc_extract_178 = PE_INT_WALLACE_DOT8_TREE_W19_in1[10]; +assign pyc_extract_179 = PE_INT_WALLACE_DOT8_TREE_W19_in2[10]; +assign pyc_xor_180 = (pyc_extract_177 ^ pyc_extract_178); +assign pyc_xor_181 = (pyc_xor_180 ^ pyc_extract_179); +assign pyc_and_182 = (pyc_extract_177 & pyc_extract_178); +assign pyc_and_183 = (pyc_extract_177 & pyc_extract_179); +assign pyc_or_184 = (pyc_and_182 | pyc_and_183); +assign pyc_and_185 = (pyc_extract_178 & pyc_extract_179); +assign pyc_or_186 = (pyc_or_184 | pyc_and_185); +assign pyc_extract_187 = PE_INT_WALLACE_DOT8_TREE_W19_in3[10]; +assign pyc_xor_188 = (pyc_xor_181 ^ pyc_extract_187); +assign pyc_xor_189 = (pyc_xor_188 ^ pyc_or_168); +assign pyc_and_190 = (pyc_xor_181 & pyc_extract_187); +assign pyc_and_191 = (pyc_xor_181 & pyc_or_168); +assign pyc_or_192 = (pyc_and_190 | pyc_and_191); +assign pyc_and_193 = (pyc_extract_187 & pyc_or_168); +assign pyc_or_194 = (pyc_or_192 | pyc_and_193); +assign pyc_extract_195 = PE_INT_WALLACE_DOT8_TREE_W19_in0[11]; +assign pyc_extract_196 = PE_INT_WALLACE_DOT8_TREE_W19_in1[11]; +assign pyc_extract_197 = PE_INT_WALLACE_DOT8_TREE_W19_in2[11]; +assign pyc_xor_198 = (pyc_extract_195 ^ pyc_extract_196); +assign pyc_xor_199 = (pyc_xor_198 ^ pyc_extract_197); +assign pyc_and_200 = (pyc_extract_195 & pyc_extract_196); +assign pyc_and_201 = (pyc_extract_195 & pyc_extract_197); +assign pyc_or_202 = (pyc_and_200 | pyc_and_201); +assign pyc_and_203 = (pyc_extract_196 & pyc_extract_197); +assign pyc_or_204 = (pyc_or_202 | pyc_and_203); +assign pyc_extract_205 = PE_INT_WALLACE_DOT8_TREE_W19_in3[11]; +assign pyc_xor_206 = (pyc_xor_199 ^ pyc_extract_205); +assign pyc_xor_207 = (pyc_xor_206 ^ pyc_or_186); +assign pyc_and_208 = (pyc_xor_199 & pyc_extract_205); +assign pyc_and_209 = (pyc_xor_199 & pyc_or_186); +assign pyc_or_210 = (pyc_and_208 | pyc_and_209); +assign pyc_and_211 = (pyc_extract_205 & pyc_or_186); +assign pyc_or_212 = (pyc_or_210 | pyc_and_211); +assign pyc_extract_213 = PE_INT_WALLACE_DOT8_TREE_W19_in0[12]; +assign pyc_extract_214 = PE_INT_WALLACE_DOT8_TREE_W19_in1[12]; +assign pyc_extract_215 = PE_INT_WALLACE_DOT8_TREE_W19_in2[12]; +assign pyc_xor_216 = (pyc_extract_213 ^ pyc_extract_214); +assign pyc_xor_217 = (pyc_xor_216 ^ pyc_extract_215); +assign pyc_and_218 = (pyc_extract_213 & pyc_extract_214); +assign pyc_and_219 = (pyc_extract_213 & pyc_extract_215); +assign pyc_or_220 = (pyc_and_218 | pyc_and_219); +assign pyc_and_221 = (pyc_extract_214 & pyc_extract_215); +assign pyc_or_222 = (pyc_or_220 | pyc_and_221); +assign pyc_extract_223 = PE_INT_WALLACE_DOT8_TREE_W19_in3[12]; +assign pyc_xor_224 = (pyc_xor_217 ^ pyc_extract_223); +assign pyc_xor_225 = (pyc_xor_224 ^ pyc_or_204); +assign pyc_and_226 = (pyc_xor_217 & pyc_extract_223); +assign pyc_and_227 = (pyc_xor_217 & pyc_or_204); +assign pyc_or_228 = (pyc_and_226 | pyc_and_227); +assign pyc_and_229 = (pyc_extract_223 & pyc_or_204); +assign pyc_or_230 = (pyc_or_228 | pyc_and_229); +assign pyc_extract_231 = PE_INT_WALLACE_DOT8_TREE_W19_in0[13]; +assign pyc_extract_232 = PE_INT_WALLACE_DOT8_TREE_W19_in1[13]; +assign pyc_extract_233 = PE_INT_WALLACE_DOT8_TREE_W19_in2[13]; +assign pyc_xor_234 = (pyc_extract_231 ^ pyc_extract_232); +assign pyc_xor_235 = (pyc_xor_234 ^ pyc_extract_233); +assign pyc_and_236 = (pyc_extract_231 & pyc_extract_232); +assign pyc_and_237 = (pyc_extract_231 & pyc_extract_233); +assign pyc_or_238 = (pyc_and_236 | pyc_and_237); +assign pyc_and_239 = (pyc_extract_232 & pyc_extract_233); +assign pyc_or_240 = (pyc_or_238 | pyc_and_239); +assign pyc_extract_241 = PE_INT_WALLACE_DOT8_TREE_W19_in3[13]; +assign pyc_xor_242 = (pyc_xor_235 ^ pyc_extract_241); +assign pyc_xor_243 = (pyc_xor_242 ^ pyc_or_222); +assign pyc_and_244 = (pyc_xor_235 & pyc_extract_241); +assign pyc_and_245 = (pyc_xor_235 & pyc_or_222); +assign pyc_or_246 = (pyc_and_244 | pyc_and_245); +assign pyc_and_247 = (pyc_extract_241 & pyc_or_222); +assign pyc_or_248 = (pyc_or_246 | pyc_and_247); +assign pyc_extract_249 = PE_INT_WALLACE_DOT8_TREE_W19_in0[14]; +assign pyc_extract_250 = PE_INT_WALLACE_DOT8_TREE_W19_in1[14]; +assign pyc_extract_251 = PE_INT_WALLACE_DOT8_TREE_W19_in2[14]; +assign pyc_xor_252 = (pyc_extract_249 ^ pyc_extract_250); +assign pyc_xor_253 = (pyc_xor_252 ^ pyc_extract_251); +assign pyc_and_254 = (pyc_extract_249 & pyc_extract_250); +assign pyc_and_255 = (pyc_extract_249 & pyc_extract_251); +assign pyc_or_256 = (pyc_and_254 | pyc_and_255); +assign pyc_and_257 = (pyc_extract_250 & pyc_extract_251); +assign pyc_or_258 = (pyc_or_256 | pyc_and_257); +assign pyc_extract_259 = PE_INT_WALLACE_DOT8_TREE_W19_in3[14]; +assign pyc_xor_260 = (pyc_xor_253 ^ pyc_extract_259); +assign pyc_xor_261 = (pyc_xor_260 ^ pyc_or_240); +assign pyc_and_262 = (pyc_xor_253 & pyc_extract_259); +assign pyc_and_263 = (pyc_xor_253 & pyc_or_240); +assign pyc_or_264 = (pyc_and_262 | pyc_and_263); +assign pyc_and_265 = (pyc_extract_259 & pyc_or_240); +assign pyc_or_266 = (pyc_or_264 | pyc_and_265); +assign pyc_extract_267 = PE_INT_WALLACE_DOT8_TREE_W19_in0[15]; +assign pyc_extract_268 = PE_INT_WALLACE_DOT8_TREE_W19_in1[15]; +assign pyc_extract_269 = PE_INT_WALLACE_DOT8_TREE_W19_in2[15]; +assign pyc_xor_270 = (pyc_extract_267 ^ pyc_extract_268); +assign pyc_xor_271 = (pyc_xor_270 ^ pyc_extract_269); +assign pyc_and_272 = (pyc_extract_267 & pyc_extract_268); +assign pyc_and_273 = (pyc_extract_267 & pyc_extract_269); +assign pyc_or_274 = (pyc_and_272 | pyc_and_273); +assign pyc_and_275 = (pyc_extract_268 & pyc_extract_269); +assign pyc_or_276 = (pyc_or_274 | pyc_and_275); +assign pyc_extract_277 = PE_INT_WALLACE_DOT8_TREE_W19_in3[15]; +assign pyc_xor_278 = (pyc_xor_271 ^ pyc_extract_277); +assign pyc_xor_279 = (pyc_xor_278 ^ pyc_or_258); +assign pyc_and_280 = (pyc_xor_271 & pyc_extract_277); +assign pyc_and_281 = (pyc_xor_271 & pyc_or_258); +assign pyc_or_282 = (pyc_and_280 | pyc_and_281); +assign pyc_and_283 = (pyc_extract_277 & pyc_or_258); +assign pyc_or_284 = (pyc_or_282 | pyc_and_283); +assign pyc_extract_285 = PE_INT_WALLACE_DOT8_TREE_W19_in0[16]; +assign pyc_extract_286 = PE_INT_WALLACE_DOT8_TREE_W19_in1[16]; +assign pyc_extract_287 = PE_INT_WALLACE_DOT8_TREE_W19_in2[16]; +assign pyc_xor_288 = (pyc_extract_285 ^ pyc_extract_286); +assign pyc_xor_289 = (pyc_xor_288 ^ pyc_extract_287); +assign pyc_and_290 = (pyc_extract_285 & pyc_extract_286); +assign pyc_and_291 = (pyc_extract_285 & pyc_extract_287); +assign pyc_or_292 = (pyc_and_290 | pyc_and_291); +assign pyc_and_293 = (pyc_extract_286 & pyc_extract_287); +assign pyc_or_294 = (pyc_or_292 | pyc_and_293); +assign pyc_extract_295 = PE_INT_WALLACE_DOT8_TREE_W19_in3[16]; +assign pyc_xor_296 = (pyc_xor_289 ^ pyc_extract_295); +assign pyc_xor_297 = (pyc_xor_296 ^ pyc_or_276); +assign pyc_and_298 = (pyc_xor_289 & pyc_extract_295); +assign pyc_and_299 = (pyc_xor_289 & pyc_or_276); +assign pyc_or_300 = (pyc_and_298 | pyc_and_299); +assign pyc_and_301 = (pyc_extract_295 & pyc_or_276); +assign pyc_or_302 = (pyc_or_300 | pyc_and_301); +assign pyc_extract_303 = PE_INT_WALLACE_DOT8_TREE_W19_in0[17]; +assign pyc_extract_304 = PE_INT_WALLACE_DOT8_TREE_W19_in1[17]; +assign pyc_extract_305 = PE_INT_WALLACE_DOT8_TREE_W19_in2[17]; +assign pyc_xor_306 = (pyc_extract_303 ^ pyc_extract_304); +assign pyc_xor_307 = (pyc_xor_306 ^ pyc_extract_305); +assign pyc_and_308 = (pyc_extract_303 & pyc_extract_304); +assign pyc_and_309 = (pyc_extract_303 & pyc_extract_305); +assign pyc_or_310 = (pyc_and_308 | pyc_and_309); +assign pyc_and_311 = (pyc_extract_304 & pyc_extract_305); +assign pyc_or_312 = (pyc_or_310 | pyc_and_311); +assign pyc_extract_313 = PE_INT_WALLACE_DOT8_TREE_W19_in3[17]; +assign pyc_xor_314 = (pyc_xor_307 ^ pyc_extract_313); +assign pyc_xor_315 = (pyc_xor_314 ^ pyc_or_294); +assign pyc_and_316 = (pyc_xor_307 & pyc_extract_313); +assign pyc_and_317 = (pyc_xor_307 & pyc_or_294); +assign pyc_or_318 = (pyc_and_316 | pyc_and_317); +assign pyc_and_319 = (pyc_extract_313 & pyc_or_294); +assign pyc_or_320 = (pyc_or_318 | pyc_and_319); +assign pyc_extract_321 = PE_INT_WALLACE_DOT8_TREE_W19_in0[18]; +assign pyc_extract_322 = PE_INT_WALLACE_DOT8_TREE_W19_in1[18]; +assign pyc_extract_323 = PE_INT_WALLACE_DOT8_TREE_W19_in2[18]; +assign pyc_xor_324 = (pyc_extract_321 ^ pyc_extract_322); +assign pyc_xor_325 = (pyc_xor_324 ^ pyc_extract_323); +assign pyc_extract_326 = PE_INT_WALLACE_DOT8_TREE_W19_in3[18]; +assign pyc_xor_327 = (pyc_xor_325 ^ pyc_extract_326); +assign pyc_xor_328 = (pyc_xor_327 ^ pyc_or_312); +assign pyc_extract_329 = PE_INT_WALLACE_DOT8_TREE_W19_in4[0]; +assign pyc_extract_330 = PE_INT_WALLACE_DOT8_TREE_W19_in5[0]; +assign pyc_extract_331 = PE_INT_WALLACE_DOT8_TREE_W19_in6[0]; +assign pyc_xor_332 = (pyc_extract_329 ^ pyc_extract_330); +assign pyc_xor_333 = (pyc_xor_332 ^ pyc_extract_331); +assign pyc_and_334 = (pyc_extract_329 & pyc_extract_330); +assign pyc_and_335 = (pyc_extract_329 & pyc_extract_331); +assign pyc_or_336 = (pyc_and_334 | pyc_and_335); +assign pyc_and_337 = (pyc_extract_330 & pyc_extract_331); +assign pyc_or_338 = (pyc_or_336 | pyc_and_337); +assign pyc_extract_339 = PE_INT_WALLACE_DOT8_TREE_W19_in7[0]; +assign pyc_xor_340 = (pyc_xor_333 ^ pyc_extract_339); +assign pyc_and_341 = (pyc_xor_333 & pyc_extract_339); +assign pyc_extract_342 = PE_INT_WALLACE_DOT8_TREE_W19_in4[1]; +assign pyc_extract_343 = PE_INT_WALLACE_DOT8_TREE_W19_in5[1]; +assign pyc_extract_344 = PE_INT_WALLACE_DOT8_TREE_W19_in6[1]; +assign pyc_xor_345 = (pyc_extract_342 ^ pyc_extract_343); +assign pyc_xor_346 = (pyc_xor_345 ^ pyc_extract_344); +assign pyc_and_347 = (pyc_extract_342 & pyc_extract_343); +assign pyc_and_348 = (pyc_extract_342 & pyc_extract_344); +assign pyc_or_349 = (pyc_and_347 | pyc_and_348); +assign pyc_and_350 = (pyc_extract_343 & pyc_extract_344); +assign pyc_or_351 = (pyc_or_349 | pyc_and_350); +assign pyc_extract_352 = PE_INT_WALLACE_DOT8_TREE_W19_in7[1]; +assign pyc_xor_353 = (pyc_xor_346 ^ pyc_extract_352); +assign pyc_xor_354 = (pyc_xor_353 ^ pyc_or_338); +assign pyc_and_355 = (pyc_xor_346 & pyc_extract_352); +assign pyc_and_356 = (pyc_xor_346 & pyc_or_338); +assign pyc_or_357 = (pyc_and_355 | pyc_and_356); +assign pyc_and_358 = (pyc_extract_352 & pyc_or_338); +assign pyc_or_359 = (pyc_or_357 | pyc_and_358); +assign pyc_extract_360 = PE_INT_WALLACE_DOT8_TREE_W19_in4[2]; +assign pyc_extract_361 = PE_INT_WALLACE_DOT8_TREE_W19_in5[2]; +assign pyc_extract_362 = PE_INT_WALLACE_DOT8_TREE_W19_in6[2]; +assign pyc_xor_363 = (pyc_extract_360 ^ pyc_extract_361); +assign pyc_xor_364 = (pyc_xor_363 ^ pyc_extract_362); +assign pyc_and_365 = (pyc_extract_360 & pyc_extract_361); +assign pyc_and_366 = (pyc_extract_360 & pyc_extract_362); +assign pyc_or_367 = (pyc_and_365 | pyc_and_366); +assign pyc_and_368 = (pyc_extract_361 & pyc_extract_362); +assign pyc_or_369 = (pyc_or_367 | pyc_and_368); +assign pyc_extract_370 = PE_INT_WALLACE_DOT8_TREE_W19_in7[2]; +assign pyc_xor_371 = (pyc_xor_364 ^ pyc_extract_370); +assign pyc_xor_372 = (pyc_xor_371 ^ pyc_or_351); +assign pyc_and_373 = (pyc_xor_364 & pyc_extract_370); +assign pyc_and_374 = (pyc_xor_364 & pyc_or_351); +assign pyc_or_375 = (pyc_and_373 | pyc_and_374); +assign pyc_and_376 = (pyc_extract_370 & pyc_or_351); +assign pyc_or_377 = (pyc_or_375 | pyc_and_376); +assign pyc_extract_378 = PE_INT_WALLACE_DOT8_TREE_W19_in4[3]; +assign pyc_extract_379 = PE_INT_WALLACE_DOT8_TREE_W19_in5[3]; +assign pyc_extract_380 = PE_INT_WALLACE_DOT8_TREE_W19_in6[3]; +assign pyc_xor_381 = (pyc_extract_378 ^ pyc_extract_379); +assign pyc_xor_382 = (pyc_xor_381 ^ pyc_extract_380); +assign pyc_and_383 = (pyc_extract_378 & pyc_extract_379); +assign pyc_and_384 = (pyc_extract_378 & pyc_extract_380); +assign pyc_or_385 = (pyc_and_383 | pyc_and_384); +assign pyc_and_386 = (pyc_extract_379 & pyc_extract_380); +assign pyc_or_387 = (pyc_or_385 | pyc_and_386); +assign pyc_extract_388 = PE_INT_WALLACE_DOT8_TREE_W19_in7[3]; +assign pyc_xor_389 = (pyc_xor_382 ^ pyc_extract_388); +assign pyc_xor_390 = (pyc_xor_389 ^ pyc_or_369); +assign pyc_and_391 = (pyc_xor_382 & pyc_extract_388); +assign pyc_and_392 = (pyc_xor_382 & pyc_or_369); +assign pyc_or_393 = (pyc_and_391 | pyc_and_392); +assign pyc_and_394 = (pyc_extract_388 & pyc_or_369); +assign pyc_or_395 = (pyc_or_393 | pyc_and_394); +assign pyc_extract_396 = PE_INT_WALLACE_DOT8_TREE_W19_in4[4]; +assign pyc_extract_397 = PE_INT_WALLACE_DOT8_TREE_W19_in5[4]; +assign pyc_extract_398 = PE_INT_WALLACE_DOT8_TREE_W19_in6[4]; +assign pyc_xor_399 = (pyc_extract_396 ^ pyc_extract_397); +assign pyc_xor_400 = (pyc_xor_399 ^ pyc_extract_398); +assign pyc_and_401 = (pyc_extract_396 & pyc_extract_397); +assign pyc_and_402 = (pyc_extract_396 & pyc_extract_398); +assign pyc_or_403 = (pyc_and_401 | pyc_and_402); +assign pyc_and_404 = (pyc_extract_397 & pyc_extract_398); +assign pyc_or_405 = (pyc_or_403 | pyc_and_404); +assign pyc_extract_406 = PE_INT_WALLACE_DOT8_TREE_W19_in7[4]; +assign pyc_xor_407 = (pyc_xor_400 ^ pyc_extract_406); +assign pyc_xor_408 = (pyc_xor_407 ^ pyc_or_387); +assign pyc_and_409 = (pyc_xor_400 & pyc_extract_406); +assign pyc_and_410 = (pyc_xor_400 & pyc_or_387); +assign pyc_or_411 = (pyc_and_409 | pyc_and_410); +assign pyc_and_412 = (pyc_extract_406 & pyc_or_387); +assign pyc_or_413 = (pyc_or_411 | pyc_and_412); +assign pyc_extract_414 = PE_INT_WALLACE_DOT8_TREE_W19_in4[5]; +assign pyc_extract_415 = PE_INT_WALLACE_DOT8_TREE_W19_in5[5]; +assign pyc_extract_416 = PE_INT_WALLACE_DOT8_TREE_W19_in6[5]; +assign pyc_xor_417 = (pyc_extract_414 ^ pyc_extract_415); +assign pyc_xor_418 = (pyc_xor_417 ^ pyc_extract_416); +assign pyc_and_419 = (pyc_extract_414 & pyc_extract_415); +assign pyc_and_420 = (pyc_extract_414 & pyc_extract_416); +assign pyc_or_421 = (pyc_and_419 | pyc_and_420); +assign pyc_and_422 = (pyc_extract_415 & pyc_extract_416); +assign pyc_or_423 = (pyc_or_421 | pyc_and_422); +assign pyc_extract_424 = PE_INT_WALLACE_DOT8_TREE_W19_in7[5]; +assign pyc_xor_425 = (pyc_xor_418 ^ pyc_extract_424); +assign pyc_xor_426 = (pyc_xor_425 ^ pyc_or_405); +assign pyc_and_427 = (pyc_xor_418 & pyc_extract_424); +assign pyc_and_428 = (pyc_xor_418 & pyc_or_405); +assign pyc_or_429 = (pyc_and_427 | pyc_and_428); +assign pyc_and_430 = (pyc_extract_424 & pyc_or_405); +assign pyc_or_431 = (pyc_or_429 | pyc_and_430); +assign pyc_extract_432 = PE_INT_WALLACE_DOT8_TREE_W19_in4[6]; +assign pyc_extract_433 = PE_INT_WALLACE_DOT8_TREE_W19_in5[6]; +assign pyc_extract_434 = PE_INT_WALLACE_DOT8_TREE_W19_in6[6]; +assign pyc_xor_435 = (pyc_extract_432 ^ pyc_extract_433); +assign pyc_xor_436 = (pyc_xor_435 ^ pyc_extract_434); +assign pyc_and_437 = (pyc_extract_432 & pyc_extract_433); +assign pyc_and_438 = (pyc_extract_432 & pyc_extract_434); +assign pyc_or_439 = (pyc_and_437 | pyc_and_438); +assign pyc_and_440 = (pyc_extract_433 & pyc_extract_434); +assign pyc_or_441 = (pyc_or_439 | pyc_and_440); +assign pyc_extract_442 = PE_INT_WALLACE_DOT8_TREE_W19_in7[6]; +assign pyc_xor_443 = (pyc_xor_436 ^ pyc_extract_442); +assign pyc_xor_444 = (pyc_xor_443 ^ pyc_or_423); +assign pyc_and_445 = (pyc_xor_436 & pyc_extract_442); +assign pyc_and_446 = (pyc_xor_436 & pyc_or_423); +assign pyc_or_447 = (pyc_and_445 | pyc_and_446); +assign pyc_and_448 = (pyc_extract_442 & pyc_or_423); +assign pyc_or_449 = (pyc_or_447 | pyc_and_448); +assign pyc_extract_450 = PE_INT_WALLACE_DOT8_TREE_W19_in4[7]; +assign pyc_extract_451 = PE_INT_WALLACE_DOT8_TREE_W19_in5[7]; +assign pyc_extract_452 = PE_INT_WALLACE_DOT8_TREE_W19_in6[7]; +assign pyc_xor_453 = (pyc_extract_450 ^ pyc_extract_451); +assign pyc_xor_454 = (pyc_xor_453 ^ pyc_extract_452); +assign pyc_and_455 = (pyc_extract_450 & pyc_extract_451); +assign pyc_and_456 = (pyc_extract_450 & pyc_extract_452); +assign pyc_or_457 = (pyc_and_455 | pyc_and_456); +assign pyc_and_458 = (pyc_extract_451 & pyc_extract_452); +assign pyc_or_459 = (pyc_or_457 | pyc_and_458); +assign pyc_extract_460 = PE_INT_WALLACE_DOT8_TREE_W19_in7[7]; +assign pyc_xor_461 = (pyc_xor_454 ^ pyc_extract_460); +assign pyc_xor_462 = (pyc_xor_461 ^ pyc_or_441); +assign pyc_and_463 = (pyc_xor_454 & pyc_extract_460); +assign pyc_and_464 = (pyc_xor_454 & pyc_or_441); +assign pyc_or_465 = (pyc_and_463 | pyc_and_464); +assign pyc_and_466 = (pyc_extract_460 & pyc_or_441); +assign pyc_or_467 = (pyc_or_465 | pyc_and_466); +assign pyc_extract_468 = PE_INT_WALLACE_DOT8_TREE_W19_in4[8]; +assign pyc_extract_469 = PE_INT_WALLACE_DOT8_TREE_W19_in5[8]; +assign pyc_extract_470 = PE_INT_WALLACE_DOT8_TREE_W19_in6[8]; +assign pyc_xor_471 = (pyc_extract_468 ^ pyc_extract_469); +assign pyc_xor_472 = (pyc_xor_471 ^ pyc_extract_470); +assign pyc_and_473 = (pyc_extract_468 & pyc_extract_469); +assign pyc_and_474 = (pyc_extract_468 & pyc_extract_470); +assign pyc_or_475 = (pyc_and_473 | pyc_and_474); +assign pyc_and_476 = (pyc_extract_469 & pyc_extract_470); +assign pyc_or_477 = (pyc_or_475 | pyc_and_476); +assign pyc_extract_478 = PE_INT_WALLACE_DOT8_TREE_W19_in7[8]; +assign pyc_xor_479 = (pyc_xor_472 ^ pyc_extract_478); +assign pyc_xor_480 = (pyc_xor_479 ^ pyc_or_459); +assign pyc_and_481 = (pyc_xor_472 & pyc_extract_478); +assign pyc_and_482 = (pyc_xor_472 & pyc_or_459); +assign pyc_or_483 = (pyc_and_481 | pyc_and_482); +assign pyc_and_484 = (pyc_extract_478 & pyc_or_459); +assign pyc_or_485 = (pyc_or_483 | pyc_and_484); +assign pyc_extract_486 = PE_INT_WALLACE_DOT8_TREE_W19_in4[9]; +assign pyc_extract_487 = PE_INT_WALLACE_DOT8_TREE_W19_in5[9]; +assign pyc_extract_488 = PE_INT_WALLACE_DOT8_TREE_W19_in6[9]; +assign pyc_xor_489 = (pyc_extract_486 ^ pyc_extract_487); +assign pyc_xor_490 = (pyc_xor_489 ^ pyc_extract_488); +assign pyc_and_491 = (pyc_extract_486 & pyc_extract_487); +assign pyc_and_492 = (pyc_extract_486 & pyc_extract_488); +assign pyc_or_493 = (pyc_and_491 | pyc_and_492); +assign pyc_and_494 = (pyc_extract_487 & pyc_extract_488); +assign pyc_or_495 = (pyc_or_493 | pyc_and_494); +assign pyc_extract_496 = PE_INT_WALLACE_DOT8_TREE_W19_in7[9]; +assign pyc_xor_497 = (pyc_xor_490 ^ pyc_extract_496); +assign pyc_xor_498 = (pyc_xor_497 ^ pyc_or_477); +assign pyc_and_499 = (pyc_xor_490 & pyc_extract_496); +assign pyc_and_500 = (pyc_xor_490 & pyc_or_477); +assign pyc_or_501 = (pyc_and_499 | pyc_and_500); +assign pyc_and_502 = (pyc_extract_496 & pyc_or_477); +assign pyc_or_503 = (pyc_or_501 | pyc_and_502); +assign pyc_extract_504 = PE_INT_WALLACE_DOT8_TREE_W19_in4[10]; +assign pyc_extract_505 = PE_INT_WALLACE_DOT8_TREE_W19_in5[10]; +assign pyc_extract_506 = PE_INT_WALLACE_DOT8_TREE_W19_in6[10]; +assign pyc_xor_507 = (pyc_extract_504 ^ pyc_extract_505); +assign pyc_xor_508 = (pyc_xor_507 ^ pyc_extract_506); +assign pyc_and_509 = (pyc_extract_504 & pyc_extract_505); +assign pyc_and_510 = (pyc_extract_504 & pyc_extract_506); +assign pyc_or_511 = (pyc_and_509 | pyc_and_510); +assign pyc_and_512 = (pyc_extract_505 & pyc_extract_506); +assign pyc_or_513 = (pyc_or_511 | pyc_and_512); +assign pyc_extract_514 = PE_INT_WALLACE_DOT8_TREE_W19_in7[10]; +assign pyc_xor_515 = (pyc_xor_508 ^ pyc_extract_514); +assign pyc_xor_516 = (pyc_xor_515 ^ pyc_or_495); +assign pyc_and_517 = (pyc_xor_508 & pyc_extract_514); +assign pyc_and_518 = (pyc_xor_508 & pyc_or_495); +assign pyc_or_519 = (pyc_and_517 | pyc_and_518); +assign pyc_and_520 = (pyc_extract_514 & pyc_or_495); +assign pyc_or_521 = (pyc_or_519 | pyc_and_520); +assign pyc_extract_522 = PE_INT_WALLACE_DOT8_TREE_W19_in4[11]; +assign pyc_extract_523 = PE_INT_WALLACE_DOT8_TREE_W19_in5[11]; +assign pyc_extract_524 = PE_INT_WALLACE_DOT8_TREE_W19_in6[11]; +assign pyc_xor_525 = (pyc_extract_522 ^ pyc_extract_523); +assign pyc_xor_526 = (pyc_xor_525 ^ pyc_extract_524); +assign pyc_and_527 = (pyc_extract_522 & pyc_extract_523); +assign pyc_and_528 = (pyc_extract_522 & pyc_extract_524); +assign pyc_or_529 = (pyc_and_527 | pyc_and_528); +assign pyc_and_530 = (pyc_extract_523 & pyc_extract_524); +assign pyc_or_531 = (pyc_or_529 | pyc_and_530); +assign pyc_extract_532 = PE_INT_WALLACE_DOT8_TREE_W19_in7[11]; +assign pyc_xor_533 = (pyc_xor_526 ^ pyc_extract_532); +assign pyc_xor_534 = (pyc_xor_533 ^ pyc_or_513); +assign pyc_and_535 = (pyc_xor_526 & pyc_extract_532); +assign pyc_and_536 = (pyc_xor_526 & pyc_or_513); +assign pyc_or_537 = (pyc_and_535 | pyc_and_536); +assign pyc_and_538 = (pyc_extract_532 & pyc_or_513); +assign pyc_or_539 = (pyc_or_537 | pyc_and_538); +assign pyc_extract_540 = PE_INT_WALLACE_DOT8_TREE_W19_in4[12]; +assign pyc_extract_541 = PE_INT_WALLACE_DOT8_TREE_W19_in5[12]; +assign pyc_extract_542 = PE_INT_WALLACE_DOT8_TREE_W19_in6[12]; +assign pyc_xor_543 = (pyc_extract_540 ^ pyc_extract_541); +assign pyc_xor_544 = (pyc_xor_543 ^ pyc_extract_542); +assign pyc_and_545 = (pyc_extract_540 & pyc_extract_541); +assign pyc_and_546 = (pyc_extract_540 & pyc_extract_542); +assign pyc_or_547 = (pyc_and_545 | pyc_and_546); +assign pyc_and_548 = (pyc_extract_541 & pyc_extract_542); +assign pyc_or_549 = (pyc_or_547 | pyc_and_548); +assign pyc_extract_550 = PE_INT_WALLACE_DOT8_TREE_W19_in7[12]; +assign pyc_xor_551 = (pyc_xor_544 ^ pyc_extract_550); +assign pyc_xor_552 = (pyc_xor_551 ^ pyc_or_531); +assign pyc_and_553 = (pyc_xor_544 & pyc_extract_550); +assign pyc_and_554 = (pyc_xor_544 & pyc_or_531); +assign pyc_or_555 = (pyc_and_553 | pyc_and_554); +assign pyc_and_556 = (pyc_extract_550 & pyc_or_531); +assign pyc_or_557 = (pyc_or_555 | pyc_and_556); +assign pyc_extract_558 = PE_INT_WALLACE_DOT8_TREE_W19_in4[13]; +assign pyc_extract_559 = PE_INT_WALLACE_DOT8_TREE_W19_in5[13]; +assign pyc_extract_560 = PE_INT_WALLACE_DOT8_TREE_W19_in6[13]; +assign pyc_xor_561 = (pyc_extract_558 ^ pyc_extract_559); +assign pyc_xor_562 = (pyc_xor_561 ^ pyc_extract_560); +assign pyc_and_563 = (pyc_extract_558 & pyc_extract_559); +assign pyc_and_564 = (pyc_extract_558 & pyc_extract_560); +assign pyc_or_565 = (pyc_and_563 | pyc_and_564); +assign pyc_and_566 = (pyc_extract_559 & pyc_extract_560); +assign pyc_or_567 = (pyc_or_565 | pyc_and_566); +assign pyc_extract_568 = PE_INT_WALLACE_DOT8_TREE_W19_in7[13]; +assign pyc_xor_569 = (pyc_xor_562 ^ pyc_extract_568); +assign pyc_xor_570 = (pyc_xor_569 ^ pyc_or_549); +assign pyc_and_571 = (pyc_xor_562 & pyc_extract_568); +assign pyc_and_572 = (pyc_xor_562 & pyc_or_549); +assign pyc_or_573 = (pyc_and_571 | pyc_and_572); +assign pyc_and_574 = (pyc_extract_568 & pyc_or_549); +assign pyc_or_575 = (pyc_or_573 | pyc_and_574); +assign pyc_extract_576 = PE_INT_WALLACE_DOT8_TREE_W19_in4[14]; +assign pyc_extract_577 = PE_INT_WALLACE_DOT8_TREE_W19_in5[14]; +assign pyc_extract_578 = PE_INT_WALLACE_DOT8_TREE_W19_in6[14]; +assign pyc_xor_579 = (pyc_extract_576 ^ pyc_extract_577); +assign pyc_xor_580 = (pyc_xor_579 ^ pyc_extract_578); +assign pyc_and_581 = (pyc_extract_576 & pyc_extract_577); +assign pyc_and_582 = (pyc_extract_576 & pyc_extract_578); +assign pyc_or_583 = (pyc_and_581 | pyc_and_582); +assign pyc_and_584 = (pyc_extract_577 & pyc_extract_578); +assign pyc_or_585 = (pyc_or_583 | pyc_and_584); +assign pyc_extract_586 = PE_INT_WALLACE_DOT8_TREE_W19_in7[14]; +assign pyc_xor_587 = (pyc_xor_580 ^ pyc_extract_586); +assign pyc_xor_588 = (pyc_xor_587 ^ pyc_or_567); +assign pyc_and_589 = (pyc_xor_580 & pyc_extract_586); +assign pyc_and_590 = (pyc_xor_580 & pyc_or_567); +assign pyc_or_591 = (pyc_and_589 | pyc_and_590); +assign pyc_and_592 = (pyc_extract_586 & pyc_or_567); +assign pyc_or_593 = (pyc_or_591 | pyc_and_592); +assign pyc_extract_594 = PE_INT_WALLACE_DOT8_TREE_W19_in4[15]; +assign pyc_extract_595 = PE_INT_WALLACE_DOT8_TREE_W19_in5[15]; +assign pyc_extract_596 = PE_INT_WALLACE_DOT8_TREE_W19_in6[15]; +assign pyc_xor_597 = (pyc_extract_594 ^ pyc_extract_595); +assign pyc_xor_598 = (pyc_xor_597 ^ pyc_extract_596); +assign pyc_and_599 = (pyc_extract_594 & pyc_extract_595); +assign pyc_and_600 = (pyc_extract_594 & pyc_extract_596); +assign pyc_or_601 = (pyc_and_599 | pyc_and_600); +assign pyc_and_602 = (pyc_extract_595 & pyc_extract_596); +assign pyc_or_603 = (pyc_or_601 | pyc_and_602); +assign pyc_extract_604 = PE_INT_WALLACE_DOT8_TREE_W19_in7[15]; +assign pyc_xor_605 = (pyc_xor_598 ^ pyc_extract_604); +assign pyc_xor_606 = (pyc_xor_605 ^ pyc_or_585); +assign pyc_and_607 = (pyc_xor_598 & pyc_extract_604); +assign pyc_and_608 = (pyc_xor_598 & pyc_or_585); +assign pyc_or_609 = (pyc_and_607 | pyc_and_608); +assign pyc_and_610 = (pyc_extract_604 & pyc_or_585); +assign pyc_or_611 = (pyc_or_609 | pyc_and_610); +assign pyc_extract_612 = PE_INT_WALLACE_DOT8_TREE_W19_in4[16]; +assign pyc_extract_613 = PE_INT_WALLACE_DOT8_TREE_W19_in5[16]; +assign pyc_extract_614 = PE_INT_WALLACE_DOT8_TREE_W19_in6[16]; +assign pyc_xor_615 = (pyc_extract_612 ^ pyc_extract_613); +assign pyc_xor_616 = (pyc_xor_615 ^ pyc_extract_614); +assign pyc_and_617 = (pyc_extract_612 & pyc_extract_613); +assign pyc_and_618 = (pyc_extract_612 & pyc_extract_614); +assign pyc_or_619 = (pyc_and_617 | pyc_and_618); +assign pyc_and_620 = (pyc_extract_613 & pyc_extract_614); +assign pyc_or_621 = (pyc_or_619 | pyc_and_620); +assign pyc_extract_622 = PE_INT_WALLACE_DOT8_TREE_W19_in7[16]; +assign pyc_xor_623 = (pyc_xor_616 ^ pyc_extract_622); +assign pyc_xor_624 = (pyc_xor_623 ^ pyc_or_603); +assign pyc_and_625 = (pyc_xor_616 & pyc_extract_622); +assign pyc_and_626 = (pyc_xor_616 & pyc_or_603); +assign pyc_or_627 = (pyc_and_625 | pyc_and_626); +assign pyc_and_628 = (pyc_extract_622 & pyc_or_603); +assign pyc_or_629 = (pyc_or_627 | pyc_and_628); +assign pyc_extract_630 = PE_INT_WALLACE_DOT8_TREE_W19_in4[17]; +assign pyc_extract_631 = PE_INT_WALLACE_DOT8_TREE_W19_in5[17]; +assign pyc_extract_632 = PE_INT_WALLACE_DOT8_TREE_W19_in6[17]; +assign pyc_xor_633 = (pyc_extract_630 ^ pyc_extract_631); +assign pyc_xor_634 = (pyc_xor_633 ^ pyc_extract_632); +assign pyc_and_635 = (pyc_extract_630 & pyc_extract_631); +assign pyc_and_636 = (pyc_extract_630 & pyc_extract_632); +assign pyc_or_637 = (pyc_and_635 | pyc_and_636); +assign pyc_and_638 = (pyc_extract_631 & pyc_extract_632); +assign pyc_or_639 = (pyc_or_637 | pyc_and_638); +assign pyc_extract_640 = PE_INT_WALLACE_DOT8_TREE_W19_in7[17]; +assign pyc_xor_641 = (pyc_xor_634 ^ pyc_extract_640); +assign pyc_xor_642 = (pyc_xor_641 ^ pyc_or_621); +assign pyc_and_643 = (pyc_xor_634 & pyc_extract_640); +assign pyc_and_644 = (pyc_xor_634 & pyc_or_621); +assign pyc_or_645 = (pyc_and_643 | pyc_and_644); +assign pyc_and_646 = (pyc_extract_640 & pyc_or_621); +assign pyc_or_647 = (pyc_or_645 | pyc_and_646); +assign pyc_extract_648 = PE_INT_WALLACE_DOT8_TREE_W19_in4[18]; +assign pyc_extract_649 = PE_INT_WALLACE_DOT8_TREE_W19_in5[18]; +assign pyc_extract_650 = PE_INT_WALLACE_DOT8_TREE_W19_in6[18]; +assign pyc_xor_651 = (pyc_extract_648 ^ pyc_extract_649); +assign pyc_xor_652 = (pyc_xor_651 ^ pyc_extract_650); +assign pyc_extract_653 = PE_INT_WALLACE_DOT8_TREE_W19_in7[18]; +assign pyc_xor_654 = (pyc_xor_652 ^ pyc_extract_653); +assign pyc_xor_655 = (pyc_xor_654 ^ pyc_or_639); +assign pyc_xor_656 = (pyc_xor_13 ^ pyc_xor_340); +assign pyc_and_657 = (pyc_xor_13 & pyc_xor_340); +assign pyc_xor_658 = (pyc_xor_27 ^ pyc_and_14); +assign pyc_xor_659 = (pyc_xor_658 ^ pyc_xor_354); +assign pyc_and_660 = (pyc_xor_27 & pyc_and_14); +assign pyc_and_661 = (pyc_xor_27 & pyc_xor_354); +assign pyc_or_662 = (pyc_and_660 | pyc_and_661); +assign pyc_and_663 = (pyc_and_14 & pyc_xor_354); +assign pyc_or_664 = (pyc_or_662 | pyc_and_663); +assign pyc_xor_665 = (pyc_xor_659 ^ pyc_and_341); +assign pyc_xor_666 = (pyc_xor_665 ^ pyc_and_657); +assign pyc_and_667 = (pyc_xor_659 & pyc_and_341); +assign pyc_and_668 = (pyc_xor_659 & pyc_and_657); +assign pyc_or_669 = (pyc_and_667 | pyc_and_668); +assign pyc_and_670 = (pyc_and_341 & pyc_and_657); +assign pyc_or_671 = (pyc_or_669 | pyc_and_670); +assign pyc_xor_672 = (pyc_xor_45 ^ pyc_or_32); +assign pyc_xor_673 = (pyc_xor_672 ^ pyc_xor_372); +assign pyc_and_674 = (pyc_xor_45 & pyc_or_32); +assign pyc_and_675 = (pyc_xor_45 & pyc_xor_372); +assign pyc_or_676 = (pyc_and_674 | pyc_and_675); +assign pyc_and_677 = (pyc_or_32 & pyc_xor_372); +assign pyc_or_678 = (pyc_or_676 | pyc_and_677); +assign pyc_xor_679 = (pyc_xor_673 ^ pyc_or_359); +assign pyc_xor_680 = (pyc_xor_679 ^ pyc_or_664); +assign pyc_and_681 = (pyc_xor_673 & pyc_or_359); +assign pyc_and_682 = (pyc_xor_673 & pyc_or_664); +assign pyc_or_683 = (pyc_and_681 | pyc_and_682); +assign pyc_and_684 = (pyc_or_359 & pyc_or_664); +assign pyc_or_685 = (pyc_or_683 | pyc_and_684); +assign pyc_xor_686 = (pyc_xor_63 ^ pyc_or_50); +assign pyc_xor_687 = (pyc_xor_686 ^ pyc_xor_390); +assign pyc_and_688 = (pyc_xor_63 & pyc_or_50); +assign pyc_and_689 = (pyc_xor_63 & pyc_xor_390); +assign pyc_or_690 = (pyc_and_688 | pyc_and_689); +assign pyc_and_691 = (pyc_or_50 & pyc_xor_390); +assign pyc_or_692 = (pyc_or_690 | pyc_and_691); +assign pyc_xor_693 = (pyc_xor_687 ^ pyc_or_377); +assign pyc_xor_694 = (pyc_xor_693 ^ pyc_or_678); +assign pyc_and_695 = (pyc_xor_687 & pyc_or_377); +assign pyc_and_696 = (pyc_xor_687 & pyc_or_678); +assign pyc_or_697 = (pyc_and_695 | pyc_and_696); +assign pyc_and_698 = (pyc_or_377 & pyc_or_678); +assign pyc_or_699 = (pyc_or_697 | pyc_and_698); +assign pyc_xor_700 = (pyc_xor_81 ^ pyc_or_68); +assign pyc_xor_701 = (pyc_xor_700 ^ pyc_xor_408); +assign pyc_and_702 = (pyc_xor_81 & pyc_or_68); +assign pyc_and_703 = (pyc_xor_81 & pyc_xor_408); +assign pyc_or_704 = (pyc_and_702 | pyc_and_703); +assign pyc_and_705 = (pyc_or_68 & pyc_xor_408); +assign pyc_or_706 = (pyc_or_704 | pyc_and_705); +assign pyc_xor_707 = (pyc_xor_701 ^ pyc_or_395); +assign pyc_xor_708 = (pyc_xor_707 ^ pyc_or_692); +assign pyc_and_709 = (pyc_xor_701 & pyc_or_395); +assign pyc_and_710 = (pyc_xor_701 & pyc_or_692); +assign pyc_or_711 = (pyc_and_709 | pyc_and_710); +assign pyc_and_712 = (pyc_or_395 & pyc_or_692); +assign pyc_or_713 = (pyc_or_711 | pyc_and_712); +assign pyc_xor_714 = (pyc_xor_99 ^ pyc_or_86); +assign pyc_xor_715 = (pyc_xor_714 ^ pyc_xor_426); +assign pyc_and_716 = (pyc_xor_99 & pyc_or_86); +assign pyc_and_717 = (pyc_xor_99 & pyc_xor_426); +assign pyc_or_718 = (pyc_and_716 | pyc_and_717); +assign pyc_and_719 = (pyc_or_86 & pyc_xor_426); +assign pyc_or_720 = (pyc_or_718 | pyc_and_719); +assign pyc_xor_721 = (pyc_xor_715 ^ pyc_or_413); +assign pyc_xor_722 = (pyc_xor_721 ^ pyc_or_706); +assign pyc_and_723 = (pyc_xor_715 & pyc_or_413); +assign pyc_and_724 = (pyc_xor_715 & pyc_or_706); +assign pyc_or_725 = (pyc_and_723 | pyc_and_724); +assign pyc_and_726 = (pyc_or_413 & pyc_or_706); +assign pyc_or_727 = (pyc_or_725 | pyc_and_726); +assign pyc_xor_728 = (pyc_xor_117 ^ pyc_or_104); +assign pyc_xor_729 = (pyc_xor_728 ^ pyc_xor_444); +assign pyc_and_730 = (pyc_xor_117 & pyc_or_104); +assign pyc_and_731 = (pyc_xor_117 & pyc_xor_444); +assign pyc_or_732 = (pyc_and_730 | pyc_and_731); +assign pyc_and_733 = (pyc_or_104 & pyc_xor_444); +assign pyc_or_734 = (pyc_or_732 | pyc_and_733); +assign pyc_xor_735 = (pyc_xor_729 ^ pyc_or_431); +assign pyc_xor_736 = (pyc_xor_735 ^ pyc_or_720); +assign pyc_and_737 = (pyc_xor_729 & pyc_or_431); +assign pyc_and_738 = (pyc_xor_729 & pyc_or_720); +assign pyc_or_739 = (pyc_and_737 | pyc_and_738); +assign pyc_and_740 = (pyc_or_431 & pyc_or_720); +assign pyc_or_741 = (pyc_or_739 | pyc_and_740); +assign pyc_xor_742 = (pyc_xor_135 ^ pyc_or_122); +assign pyc_xor_743 = (pyc_xor_742 ^ pyc_xor_462); +assign pyc_and_744 = (pyc_xor_135 & pyc_or_122); +assign pyc_and_745 = (pyc_xor_135 & pyc_xor_462); +assign pyc_or_746 = (pyc_and_744 | pyc_and_745); +assign pyc_and_747 = (pyc_or_122 & pyc_xor_462); +assign pyc_or_748 = (pyc_or_746 | pyc_and_747); +assign pyc_xor_749 = (pyc_xor_743 ^ pyc_or_449); +assign pyc_xor_750 = (pyc_xor_749 ^ pyc_or_734); +assign pyc_and_751 = (pyc_xor_743 & pyc_or_449); +assign pyc_and_752 = (pyc_xor_743 & pyc_or_734); +assign pyc_or_753 = (pyc_and_751 | pyc_and_752); +assign pyc_and_754 = (pyc_or_449 & pyc_or_734); +assign pyc_or_755 = (pyc_or_753 | pyc_and_754); +assign pyc_xor_756 = (pyc_xor_153 ^ pyc_or_140); +assign pyc_xor_757 = (pyc_xor_756 ^ pyc_xor_480); +assign pyc_and_758 = (pyc_xor_153 & pyc_or_140); +assign pyc_and_759 = (pyc_xor_153 & pyc_xor_480); +assign pyc_or_760 = (pyc_and_758 | pyc_and_759); +assign pyc_and_761 = (pyc_or_140 & pyc_xor_480); +assign pyc_or_762 = (pyc_or_760 | pyc_and_761); +assign pyc_xor_763 = (pyc_xor_757 ^ pyc_or_467); +assign pyc_xor_764 = (pyc_xor_763 ^ pyc_or_748); +assign pyc_and_765 = (pyc_xor_757 & pyc_or_467); +assign pyc_and_766 = (pyc_xor_757 & pyc_or_748); +assign pyc_or_767 = (pyc_and_765 | pyc_and_766); +assign pyc_and_768 = (pyc_or_467 & pyc_or_748); +assign pyc_or_769 = (pyc_or_767 | pyc_and_768); +assign pyc_xor_770 = (pyc_xor_171 ^ pyc_or_158); +assign pyc_xor_771 = (pyc_xor_770 ^ pyc_xor_498); +assign pyc_and_772 = (pyc_xor_171 & pyc_or_158); +assign pyc_and_773 = (pyc_xor_171 & pyc_xor_498); +assign pyc_or_774 = (pyc_and_772 | pyc_and_773); +assign pyc_and_775 = (pyc_or_158 & pyc_xor_498); +assign pyc_or_776 = (pyc_or_774 | pyc_and_775); +assign pyc_xor_777 = (pyc_xor_771 ^ pyc_or_485); +assign pyc_xor_778 = (pyc_xor_777 ^ pyc_or_762); +assign pyc_and_779 = (pyc_xor_771 & pyc_or_485); +assign pyc_and_780 = (pyc_xor_771 & pyc_or_762); +assign pyc_or_781 = (pyc_and_779 | pyc_and_780); +assign pyc_and_782 = (pyc_or_485 & pyc_or_762); +assign pyc_or_783 = (pyc_or_781 | pyc_and_782); +assign pyc_xor_784 = (pyc_xor_189 ^ pyc_or_176); +assign pyc_xor_785 = (pyc_xor_784 ^ pyc_xor_516); +assign pyc_and_786 = (pyc_xor_189 & pyc_or_176); +assign pyc_and_787 = (pyc_xor_189 & pyc_xor_516); +assign pyc_or_788 = (pyc_and_786 | pyc_and_787); +assign pyc_and_789 = (pyc_or_176 & pyc_xor_516); +assign pyc_or_790 = (pyc_or_788 | pyc_and_789); +assign pyc_xor_791 = (pyc_xor_785 ^ pyc_or_503); +assign pyc_xor_792 = (pyc_xor_791 ^ pyc_or_776); +assign pyc_and_793 = (pyc_xor_785 & pyc_or_503); +assign pyc_and_794 = (pyc_xor_785 & pyc_or_776); +assign pyc_or_795 = (pyc_and_793 | pyc_and_794); +assign pyc_and_796 = (pyc_or_503 & pyc_or_776); +assign pyc_or_797 = (pyc_or_795 | pyc_and_796); +assign pyc_xor_798 = (pyc_xor_207 ^ pyc_or_194); +assign pyc_xor_799 = (pyc_xor_798 ^ pyc_xor_534); +assign pyc_and_800 = (pyc_xor_207 & pyc_or_194); +assign pyc_and_801 = (pyc_xor_207 & pyc_xor_534); +assign pyc_or_802 = (pyc_and_800 | pyc_and_801); +assign pyc_and_803 = (pyc_or_194 & pyc_xor_534); +assign pyc_or_804 = (pyc_or_802 | pyc_and_803); +assign pyc_xor_805 = (pyc_xor_799 ^ pyc_or_521); +assign pyc_xor_806 = (pyc_xor_805 ^ pyc_or_790); +assign pyc_and_807 = (pyc_xor_799 & pyc_or_521); +assign pyc_and_808 = (pyc_xor_799 & pyc_or_790); +assign pyc_or_809 = (pyc_and_807 | pyc_and_808); +assign pyc_and_810 = (pyc_or_521 & pyc_or_790); +assign pyc_or_811 = (pyc_or_809 | pyc_and_810); +assign pyc_xor_812 = (pyc_xor_225 ^ pyc_or_212); +assign pyc_xor_813 = (pyc_xor_812 ^ pyc_xor_552); +assign pyc_and_814 = (pyc_xor_225 & pyc_or_212); +assign pyc_and_815 = (pyc_xor_225 & pyc_xor_552); +assign pyc_or_816 = (pyc_and_814 | pyc_and_815); +assign pyc_and_817 = (pyc_or_212 & pyc_xor_552); +assign pyc_or_818 = (pyc_or_816 | pyc_and_817); +assign pyc_xor_819 = (pyc_xor_813 ^ pyc_or_539); +assign pyc_xor_820 = (pyc_xor_819 ^ pyc_or_804); +assign pyc_and_821 = (pyc_xor_813 & pyc_or_539); +assign pyc_and_822 = (pyc_xor_813 & pyc_or_804); +assign pyc_or_823 = (pyc_and_821 | pyc_and_822); +assign pyc_and_824 = (pyc_or_539 & pyc_or_804); +assign pyc_or_825 = (pyc_or_823 | pyc_and_824); +assign pyc_xor_826 = (pyc_xor_243 ^ pyc_or_230); +assign pyc_xor_827 = (pyc_xor_826 ^ pyc_xor_570); +assign pyc_and_828 = (pyc_xor_243 & pyc_or_230); +assign pyc_and_829 = (pyc_xor_243 & pyc_xor_570); +assign pyc_or_830 = (pyc_and_828 | pyc_and_829); +assign pyc_and_831 = (pyc_or_230 & pyc_xor_570); +assign pyc_or_832 = (pyc_or_830 | pyc_and_831); +assign pyc_xor_833 = (pyc_xor_827 ^ pyc_or_557); +assign pyc_xor_834 = (pyc_xor_833 ^ pyc_or_818); +assign pyc_and_835 = (pyc_xor_827 & pyc_or_557); +assign pyc_and_836 = (pyc_xor_827 & pyc_or_818); +assign pyc_or_837 = (pyc_and_835 | pyc_and_836); +assign pyc_and_838 = (pyc_or_557 & pyc_or_818); +assign pyc_or_839 = (pyc_or_837 | pyc_and_838); +assign pyc_xor_840 = (pyc_xor_261 ^ pyc_or_248); +assign pyc_xor_841 = (pyc_xor_840 ^ pyc_xor_588); +assign pyc_and_842 = (pyc_xor_261 & pyc_or_248); +assign pyc_and_843 = (pyc_xor_261 & pyc_xor_588); +assign pyc_or_844 = (pyc_and_842 | pyc_and_843); +assign pyc_and_845 = (pyc_or_248 & pyc_xor_588); +assign pyc_or_846 = (pyc_or_844 | pyc_and_845); +assign pyc_xor_847 = (pyc_xor_841 ^ pyc_or_575); +assign pyc_xor_848 = (pyc_xor_847 ^ pyc_or_832); +assign pyc_and_849 = (pyc_xor_841 & pyc_or_575); +assign pyc_and_850 = (pyc_xor_841 & pyc_or_832); +assign pyc_or_851 = (pyc_and_849 | pyc_and_850); +assign pyc_and_852 = (pyc_or_575 & pyc_or_832); +assign pyc_or_853 = (pyc_or_851 | pyc_and_852); +assign pyc_xor_854 = (pyc_xor_279 ^ pyc_or_266); +assign pyc_xor_855 = (pyc_xor_854 ^ pyc_xor_606); +assign pyc_and_856 = (pyc_xor_279 & pyc_or_266); +assign pyc_and_857 = (pyc_xor_279 & pyc_xor_606); +assign pyc_or_858 = (pyc_and_856 | pyc_and_857); +assign pyc_and_859 = (pyc_or_266 & pyc_xor_606); +assign pyc_or_860 = (pyc_or_858 | pyc_and_859); +assign pyc_xor_861 = (pyc_xor_855 ^ pyc_or_593); +assign pyc_xor_862 = (pyc_xor_861 ^ pyc_or_846); +assign pyc_and_863 = (pyc_xor_855 & pyc_or_593); +assign pyc_and_864 = (pyc_xor_855 & pyc_or_846); +assign pyc_or_865 = (pyc_and_863 | pyc_and_864); +assign pyc_and_866 = (pyc_or_593 & pyc_or_846); +assign pyc_or_867 = (pyc_or_865 | pyc_and_866); +assign pyc_xor_868 = (pyc_xor_297 ^ pyc_or_284); +assign pyc_xor_869 = (pyc_xor_868 ^ pyc_xor_624); +assign pyc_and_870 = (pyc_xor_297 & pyc_or_284); +assign pyc_and_871 = (pyc_xor_297 & pyc_xor_624); +assign pyc_or_872 = (pyc_and_870 | pyc_and_871); +assign pyc_and_873 = (pyc_or_284 & pyc_xor_624); +assign pyc_or_874 = (pyc_or_872 | pyc_and_873); +assign pyc_xor_875 = (pyc_xor_869 ^ pyc_or_611); +assign pyc_xor_876 = (pyc_xor_875 ^ pyc_or_860); +assign pyc_and_877 = (pyc_xor_869 & pyc_or_611); +assign pyc_and_878 = (pyc_xor_869 & pyc_or_860); +assign pyc_or_879 = (pyc_and_877 | pyc_and_878); +assign pyc_and_880 = (pyc_or_611 & pyc_or_860); +assign pyc_or_881 = (pyc_or_879 | pyc_and_880); +assign pyc_xor_882 = (pyc_xor_315 ^ pyc_or_302); +assign pyc_xor_883 = (pyc_xor_882 ^ pyc_xor_642); +assign pyc_and_884 = (pyc_xor_315 & pyc_or_302); +assign pyc_and_885 = (pyc_xor_315 & pyc_xor_642); +assign pyc_or_886 = (pyc_and_884 | pyc_and_885); +assign pyc_and_887 = (pyc_or_302 & pyc_xor_642); +assign pyc_or_888 = (pyc_or_886 | pyc_and_887); +assign pyc_xor_889 = (pyc_xor_883 ^ pyc_or_629); +assign pyc_xor_890 = (pyc_xor_889 ^ pyc_or_874); +assign pyc_and_891 = (pyc_xor_883 & pyc_or_629); +assign pyc_and_892 = (pyc_xor_883 & pyc_or_874); +assign pyc_or_893 = (pyc_and_891 | pyc_and_892); +assign pyc_and_894 = (pyc_or_629 & pyc_or_874); +assign pyc_or_895 = (pyc_or_893 | pyc_and_894); +assign pyc_xor_896 = (pyc_xor_328 ^ pyc_or_320); +assign pyc_xor_897 = (pyc_xor_896 ^ pyc_xor_655); +assign pyc_xor_898 = (pyc_xor_897 ^ pyc_or_647); +assign pyc_xor_899 = (pyc_xor_898 ^ pyc_or_888); +assign pyc_concat_900 = {pyc_xor_899, pyc_xor_890, pyc_xor_876, pyc_xor_862, pyc_xor_848, pyc_xor_834, pyc_xor_820, pyc_xor_806, pyc_xor_792, pyc_xor_778, pyc_xor_764, pyc_xor_750, pyc_xor_736, pyc_xor_722, pyc_xor_708, pyc_xor_694, pyc_xor_680, pyc_xor_666, pyc_xor_656}; +assign pyc_concat_901 = {pyc_or_895, pyc_or_881, pyc_or_867, pyc_or_853, pyc_or_839, pyc_or_825, pyc_or_811, pyc_or_797, pyc_or_783, pyc_or_769, pyc_or_755, pyc_or_741, pyc_or_727, pyc_or_713, pyc_or_699, pyc_or_685, pyc_or_671, pyc_constant_1, pyc_constant_1}; +assign pyc_add_902 = (pyc_concat_900 + pyc_concat_901); +assign pyc_comb_903 = pyc_add_902; + +assign PE_INT_WALLACE_DOT8_TREE_W19_sum = pyc_comb_903; + +endmodule + diff --git a/designs/PE_INT/sim/run_all_wsl.sh b/designs/PE_INT/sim/run_all_wsl.sh index f47d39b..8be7f64 100644 --- a/designs/PE_INT/sim/run_all_wsl.sh +++ b/designs/PE_INT/sim/run_all_wsl.sh @@ -41,7 +41,6 @@ CASES=( VERILATOR_WARNING_FLAGS=( -Wno-DECLFILENAME -Wno-TIMESCALEMOD - -Wno-UNUSEDSIGNAL -Wno-BLKSEQ ) diff --git a/designs/PE_INT/sim/run_sim.sh b/designs/PE_INT/sim/run_sim.sh index dc55a03..4b61422 100644 --- a/designs/PE_INT/sim/run_sim.sh +++ b/designs/PE_INT/sim/run_sim.sh @@ -20,7 +20,6 @@ CASES=( VERILATOR_WARNING_FLAGS=( -Wno-DECLFILENAME -Wno-TIMESCALEMOD - -Wno-UNUSEDSIGNAL -Wno-BLKSEQ ) diff --git a/designs/PE_INT/tb/tb_pe_int_pycircuit.py b/designs/PE_INT/tb/tb_pe_int_pycircuit.py index b56268c..be52c03 100644 --- a/designs/PE_INT/tb/tb_pe_int_pycircuit.py +++ b/designs/PE_INT/tb/tb_pe_int_pycircuit.py @@ -84,15 +84,16 @@ def tb(t: Tb) -> None: tb.drive("b", _to_u(pack_s8x8_to_laneword([-1, -1, -1, -1, -1, -1, -1, -1]), 80)) tb.drive("b1", 0) - # drain and check outputs on target cycles. + # CycleAwareTb observes outputs after the active edge, so these checkpoints + # are one display-cycle earlier than the input-cycle + L notation. for _ in range(20): tb.next() tb.drive("vld", 0) - if tb.cycle == 5: + if tb.cycle == 4: tb.expect("vld_out", 1) tb.expect("out0", _to_u(exp2b.out0_19, 19)) tb.expect("out1", _to_u(exp2b.out1_16, 16)) - if tb.cycle == 6: + if tb.cycle == 5: tb.expect("vld_out", 1) tb.expect("out0", _to_u(exp2a.out0_19, 19)) diff --git a/designs/PE_INT/tb_rtl/README.md b/designs/PE_INT/tb_rtl/README.md index 7fc4c59..7d0e579 100644 --- a/designs/PE_INT/tb_rtl/README.md +++ b/designs/PE_INT/tb_rtl/README.md @@ -44,7 +44,7 @@ export PE_INT="$(pwd)" sed "s|\$PE_INT|${PE_INT}|g" filelist/pe_int.f > build/.pe_int.resolved.f sed "s|\$PE_INT|${PE_INT}|g" tb_rtl/tb.f > build/.tb.resolved.f verilator --binary --timing -Wall \ - -Wno-DECLFILENAME -Wno-TIMESCALEMOD -Wno-UNUSEDSIGNAL -Wno-BLKSEQ \ + -Wno-DECLFILENAME -Wno-TIMESCALEMOD -Wno-BLKSEQ \ -f build/.pe_int.resolved.f -f build/.tb.resolved.f \ --top-module tc_mode2b_sanity -o tc_mode2b_sanity ./obj_dir/tc_mode2b_sanity diff --git a/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v b/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v index 4b7f2a8..3e18e5b 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode_switch_random.v @@ -17,7 +17,7 @@ module tc_mode_switch_random; wire vld_out; integer i; - integer got; + integer got_idx; integer err; integer exp_count; localparam integer N_TX = 1000; @@ -36,7 +36,6 @@ module tc_mode_switch_random; reg [18:0] exp_o0 [0:N_EXP_MAX-1]; reg [15:0] exp_o1 [0:N_EXP_MAX-1]; - localparam string CASE_NAME = "rand"; PE_INT dut ( .clk(clk), .rst_n(rst_n), .vld(vld), .mode(mode), .a(a), .b(b), .b1(b1), @@ -44,23 +43,30 @@ module tc_mode_switch_random; ); `include "common_wave_dump.vh" - `include "common_exact_latency_scoreboard.vh" always #5 clk = ~clk; always @(posedge clk) begin - if (!rst_n) begin - sb_reset(); - end else begin - sb_tick(); + if (rst_n && vld_out) begin + if (got_idx >= exp_count) begin + $display("[ERR][rand] unexpected extra output out0=%0d out1=%0d", $signed(out0), $signed(out1)); + err <= err + 1; + end else begin + if (out0 !== exp_o0[got_idx] || out1 !== exp_o1[got_idx]) begin + $display("[ERR][rand] idx=%0d got(out0,out1)=(%0d,%0d) exp=(%0d,%0d)", + got_idx, $signed(out0), $signed(out1), $signed(exp_o0[got_idx]), $signed(exp_o1[got_idx])); + err <= err + 1; + end + end + got_idx <= got_idx + 1; end end initial begin clk = 0; rst_n = 0; vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; - exp_count = 0; sb_reset(); + got_idx = 0; err = 0; + exp_count = 0; if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin gen_dir = "tb_rtl/case/generated"; @@ -98,7 +104,11 @@ module tc_mode_switch_random; vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; repeat (30) @(posedge clk); - sb_final_check(); + + if (got_idx !== exp_count) begin + $display("[ERR][rand] expected %0d outputs, got %0d", exp_count, got_idx); + err = err + 1; + end if (err == 0) begin $display("[PASS] tc_mode_switch_random"); From c88b634d5932c4b8f2328dedb86e567a0d5d0aea Mon Sep 17 00:00:00 2001 From: HenryLee Date: Thu, 7 May 2026 19:02:45 +0800 Subject: [PATCH 08/10] fix(designs): strengthen PE_INT flow closure Record optimizer topology status, regression evidence, and pre-push review gates so PE_INT closure is traceable beyond functional PASS. Co-authored-by: Cursor --- .../.cursor/skills/circuit-optimizer/SKILL.md | 118 + .../skills/pe-int-implementation/SKILL.md | 31 + .../skills/pe-int-pycircuiteval-flow/SKILL.md | 143 + .../skills/pre-push-code-review-gate/SKILL.md | 65 + .../PE_INT/docs/circuit_optimizer_report.md | 262 + designs/PE_INT/docs/design_spec.md | 519 +- designs/PE_INT/docs/regression_report.md | 78 + designs/PE_INT/model/test_pe_int.py | 62 + designs/PE_INT/python/pe_int/lane_mac.py | 99 +- designs/PE_INT/python/pe_int/mac_modes.py | 39 +- designs/PE_INT/rtl/build/pe_int.v | 7964 ++++++++++++----- .../rtl/build/pe_int_wallace_dot8_tree_w16.v | 2688 +++--- .../rtl/build/pe_int_wallace_dot8_tree_w19.v | 3246 +++---- designs/PE_INT/sim/run_all_wsl.sh | 4 + .../case/tc_mode2a_sanity_rand_timing.v | 3 +- .../case/tc_mode2b_sanity_rand_timing.v | 3 +- .../case/tc_mode2c_sanity_rand_timing.v | 3 +- .../case/tc_mode2d_sanity_rand_timing.v | 3 +- designs/PE_INT/tb_rtl/tb.f | 16 +- 19 files changed, 10294 insertions(+), 5052 deletions(-) create mode 100644 designs/PE_INT/.cursor/skills/circuit-optimizer/SKILL.md create mode 100644 designs/PE_INT/.cursor/skills/pre-push-code-review-gate/SKILL.md create mode 100644 designs/PE_INT/docs/circuit_optimizer_report.md create mode 100644 designs/PE_INT/docs/regression_report.md diff --git a/designs/PE_INT/.cursor/skills/circuit-optimizer/SKILL.md b/designs/PE_INT/.cursor/skills/circuit-optimizer/SKILL.md new file mode 100644 index 0000000..72b486e --- /dev/null +++ b/designs/PE_INT/.cursor/skills/circuit-optimizer/SKILL.md @@ -0,0 +1,118 @@ +--- +name: circuit-optimizer +description: Selects and iterates RTL circuit topologies for datapath modules. Use when choosing multiplier, reducer, adder, shifter, mux, pipeline partition, logic depth, area, or power tradeoffs from a base design spec and generated RTL. +--- + +# Circuit Optimizer + +Use this skill as the instruction set for a dedicated Circuit Optimizer +sub-agent after a base `design_spec.md` has separated source-spec contracts from +unspecified structural choices. + +## Sub-Agent Invocation + +Invoke Circuit Optimizer as an independent sub-agent, not as part of the +implementation/coding agent's own reasoning. + +Required invocation contract: + +1. Launch a dedicated sub-agent titled `Circuit Optimizer`. +2. Provide the inputs listed below explicitly in the prompt. +3. Ask the sub-agent to return only optimizer-owned decisions and evidence. +4. The parent implementation agent may copy the accepted optimizer output into + `design_spec.md` and the optimizer report, but must preserve provenance. +5. The optimizer sub-agent must not edit implementation files directly. +6. The optimizer sub-agent must not claim that its topology decisions are + derived from `docs/spec.md`; they are optimization decisions. + +Use `subagent_type="generalPurpose"` unless the environment provides a more +specific circuit optimization sub-agent type. + +## Inputs + +Require these inputs before proposing topology: + +1. `docs/spec.md` and the current `docs/design_spec.md`. +2. Logic-depth rules or project timing targets. +3. User optimization objective, such as logic depth first, area first, power + first, or balanced. If absent, use balanced and state that assumption. +4. User-specified maximum iteration count. If absent, use the project default: + pass 0 before implementation plus 2 post-build optimizer iterations. +5. Current generated RTL and reports when optimizing after implementation. + +## Pass 0: Initial Topology Proposal + +For each `Unspecified by source spec` item, propose a concrete topology and +record: + +- selected topology +- rationale +- estimated logic-depth impact +- area/power tradeoff +- implementation status: `Planned`, `Implemented`, `Partially implemented`, or + `Deferred` +- evidence pointer: expected PyCircuit symbol, generated RTL module/signal, or + report section +- provenance: `Optimizer-subagent-selected, pass 0` + +Do not present the selection as if it came from `docs/spec.md`. + +## Wallace Compression Tree Contract + +When selecting a Wallace-style compression tree, describe the cell-level +structure instead of only naming the topology: + +1. List allowed compressor cells, such as `CMPE42`, `FA`, and `HA`. +2. Define each cell's input pins, output pins, bit-weight relationship, and + carry direction. +3. Define `CMPE42` as a 5-input / 3-output compressor-style cell: four + same-weight data inputs plus `Cix`, and outputs `sum`, `carry`, and `Cox`. +4. State whether same-level `CMPE42.Cox` feeds the next peer cell's `Cix`. +5. Define `FA` as three same-weight inputs to same-weight `sum` plus next-weight + `carry`. +6. Define `HA` as two same-weight inputs to same-weight `sum` plus next-weight + `carry`. +7. State that compression stops when each column has at most two remaining bits. +8. Define the final carry-propagate adder topology separately. +9. If the implementation cannot express this structure and falls back to `+` + operator trees, report that as an implementation limitation. + +## Post-Build Iteration + +After PyCircuit build, RTL generation, and functional regression pass: + +1. Inspect generated RTL hierarchy, operators, widths, registers, muxes, and + warnings. +2. Use synthesis reports when available. Without synthesis, use RTL proxy + metrics only and label them as estimates. +3. Compare against objective and timing/depth targets. +4. If a better topology or pipeline partition is justified, update the optimizer + section of `design_spec.md`, regenerate implementation, and rerun regression. +5. Before returning `stop / keep current`, verify every optimizer-selected + topology has matching implementation status in `design_spec.md`. +6. Any unimplemented topology must be explicitly marked `Deferred` in both + `design_spec.md` and the optimizer report, with reason, risk, and next + required evidence. +7. Stop only when the user/default iteration limit is reached, the objective is + met, or no material improvement remains. + +## Closure Rule + +Do not claim closure from functional PASS alone. If `design_spec.md` contains an +optimizer-selected topology, closure requires each item to be either: + +- implemented and evidenced in PyCircuit source / generated RTL / reports, or +- explicitly deferred with risk and required future evidence. + +## Report Format + +Write or update an optimizer report with: + +- pass number +- inputs reviewed +- objective +- selected topology per block +- estimated depth/area/power impact +- evidence from RTL/synthesis reports +- recommended next action + diff --git a/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md index d3df16b..f207480 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-implementation/SKILL.md @@ -69,6 +69,37 @@ If area and dynamic power conflict, prioritize dynamic power. treat that as a framework limitation to report, not as a normal coding pattern to copy. +## Structural Self-Audit Before Closure + +After coding and before reporting completion: + +1. Compare `docs/design_spec.md` optimizer-selected topology against PyCircuit + source and generated RTL. +2. For each topology item, state one of: `Implemented`, + `Partially implemented`, or `Deferred`. +3. If an item is deferred, update `docs/design_spec.md` and + `docs/circuit_optimizer_report.md` with reason, risk, and next evidence. +4. Do not claim closure by functional PASS alone. + +Required checks: + +- natural-width product widths +- multiplier topology and any deferred status +- Wallace / `CMPE42` / `FA` / `HA` structure +- terminal carry and truncation policy +- mode-2c shift/merge topology +- final CPA topology +- mode-2a `out1` hold +- no generic `+` tree where the design spec forbids it + +## Known Framework Limitation + +The PE_INT flow currently treats configurable generated RTL reset polarity/name +and reset release handling as a known PyCircuit framework limitation. Do not +silently change `docs/spec.md` to hide this. Report the limitation and keep +functional reset behavior tested; dedicated reset synchronizer closure requires +user-approved framework/spec work. + ## Mandatory Stage Coding Contract Top-level coding must be explicit: diff --git a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md index 5e44d6b..733c2fe 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md @@ -54,6 +54,96 @@ Extract executable checks from `docs/spec.md`: - cross-mode stage consistency - mode-2a `out1` stability policy +### Step A.1: Generate Design Spec + +When deriving `design_spec.md` from `docs/spec.md`, make the design spec a +low-level circuit-structure document first, not a business-behavior restatement. + +Required content: + +1. Decouple business functions from circuit modules. Describe the reusable + circuit modules first, then describe how each PE_INT mode maps onto their + parameters, selects, and data paths. +2. Define low-level module contracts for basic components such as `MUL`, `ADD`, + `SHIFTER`, `MUX`, `DEMUX`, D flip-flops/registers, comparators, counters, + valid/ready or backpressure blocks, and FSMs when they exist. +3. For every circuit component, state input/output bit widths, signedness, + latency/register boundary, reset behavior if stateful, and overflow/truncation + contract. Do not add arbitrary margin widths. +4. Specify intended structures/topologies, for example Booth multiplier, + compressor tree, carry-lookahead/prefix/ripple adder, mux tree, shifter + style, pipeline register placement, and whether a block is pure + combinational or stateful. +5. Describe bus routing explicitly: how buses are sliced, packed, muxed, + demuxed, sign/zero-extended, shifted, and merged across pipeline stages. +6. For backpressure or flow-control blocks, define ready/valid behavior, stall + propagation, skid/hold behavior, and what state is allowed to update during + stalls. +7. For FSMs, list states, transition conditions, outputs per state, reset state, + and illegal-state handling. +8. Include typical scenario waveform diagrams showing the protocol timing, + latency convention, valid/data alignment, reset behavior, and mode-specific + output stability requirements. +9. If `docs/spec.md` does not specify a structural topology, mark that item as + `Unspecified by source spec` in `design_spec.md`. Do not infer topology from + prior chat history, generated RTL, existing implementation, or reviewer + comments. +10. If a structural topology is required for implementation or review, require + either an upstream `docs/spec.md` update or an explicit user-approved + structural-policy source before generating it into `design_spec.md`. A + documented Circuit Optimizer pass may be used as this source, but its + selections must be labeled as optimizer decisions rather than source-spec + contracts. +11. For every optimizer-selected topology, include implementation status: + `Planned`, `Implemented`, `Partially implemented`, or `Deferred`. +12. For each topology status, include evidence pointers to PyCircuit symbols, + generated RTL modules/signals, reports, or deferred-risk notes. +13. Do not state a topology as implemented if the optimizer report or generated + RTL shows it is deferred or only partially implemented. + +### Step A.2: Circuit Optimizer Topology Selection + +After generating the base `design_spec.md`, launch an independent Circuit +Optimizer sub-agent for items marked `Unspecified by source spec` when the user +asks for implementation topology selection or optimization. The implementation +agent must not silently make these topology choices itself. + +Required inputs: + +1. `docs/spec.md` and base `docs/design_spec.md`. +2. Logic-depth rules and project timing targets. +3. User optimization objective (`logic-depth`, `area`, `power`, or `balanced`). +4. User-specified maximum iteration count. If absent, use the project default: + pass 0 before implementation plus 2 post-build optimizer iterations. +5. Generated RTL and synthesis reports for post-build optimization passes. + +Rules: + +1. Invoke the Circuit Optimizer as a dedicated sub-agent, titled + `Circuit Optimizer`, with explicit inputs and requested output format. +2. Pass 0 may propose topology before implementation, using estimated + logic-depth/area/power tradeoffs. +3. Write topology choices into an optimizer-owned section of `design_spec.md` + with provenance such as `Optimizer-subagent-selected, pass 0`. +4. Keep the sub-agent output in an optimizer report so later implementation and + review can trace decisions back to the optimizer pass. +5. Do not rewrite source-derived contracts as optimizer decisions. +6. After PyCircuit build, RTL generation, and functional regression pass, rerun + the optimizer sub-agent using generated RTL and available reports. +7. If the optimizer recommends a topology or pipeline change, update + `design_spec.md`, regenerate PyCircuit/RTL, and rerun regression. +8. If the optimizer selects a Wallace-style compression tree, expand it into + cell-level contracts in `design_spec.md`: allowed `CMPE42`/`FA`/`HA` cells, + cell input/output pins, bit-weight movement, `Cix`/`Cox` chaining policy, + residual-column handling, compression termination, and final CPA boundary. + The implementation must not silently replace this with generic `+` operator + trees without reporting a limitation. +9. Before stopping, verify every optimizer-selected topology is either + implemented and evidenced, or explicitly marked `Deferred` with reason, risk, + and next required evidence in both `design_spec.md` and the optimizer report. +10. Stop when the user/default iteration limit is reached, the objective is met, or no + material improvement remains. + ### Step B: Implement in PyCircuit, Then Build RTL 1. Implement in `python/`. @@ -84,6 +174,22 @@ Top-level must be reviewable as: No hidden full register-chain helper loops. +### Step B.3: Structural Self-Audit + +After coding and before declaring implementation closure: + +1. Compare the optimizer topology table in `docs/design_spec.md` against + PyCircuit source. +2. Build generated RTL and compare PyCircuit source against `rtl/build/`. +3. For every topology item, report `Implemented`, `Partially implemented`, or + `Deferred`. +4. If not implemented, update `docs/design_spec.md` and + `docs/circuit_optimizer_report.md` before claiming closure. +5. Check natural-width product widths, multiplier topology, Wallace + `CMPE42`/`FA`/`HA` structure, terminal carry/truncation policy, mode-2c + shift/merge topology, final CPA topology, mode-2a `out1` hold, and absence of + generic `+` trees where the design spec forbids them. + ### Step C: Build Verification Assets - `model/`: math + timing model regression @@ -92,6 +198,13 @@ No hidden full register-chain helper loops. - one-to-one valid mapping - fixed latency and cross-mode consistency - no bubble under full-pipeline working window + - mode-2a `out1` hold/stable policy at model and RTL level + - random valid timing and back-to-back mode switching + - signed boundary vectors for S8/S4/S5 products + +Model tests must validate protocol-visible behavior, not only math. If a +mathematical output is don't-care, the protocol model must still check the +chosen stability policy. ### Step C.1: Latency Counting Rule (Mandatory) @@ -113,15 +226,24 @@ Only run this step after user confirms explicitly: 1. Build RTL from PyCircuit source. 2. Run `tb_rtl/` testcases on both `iverilog` and `verilator`. 3. Report pass/fail and key outputs. +4. Save or update a regression summary file such as + `docs/regression_report.md` containing command lines, date/time, worktree + status or git hash, PyCircuit build result, PyCircuit TB result, model + unittest result, vector generation result, iverilog case results, Verilator + case results, and warning summary. ## 4) Current Vector Baseline Current project baseline: - `tc_mode2a_sanity`: 1000 +- `tc_mode2a_sanity_rand_timing`: 1000 - `tc_mode2b_sanity`: 1000 +- `tc_mode2b_sanity_rand_timing`: 1000 - `tc_mode2c_sanity`: 1000 +- `tc_mode2c_sanity_rand_timing`: 1000 - `tc_mode2d_sanity`: 1000 +- `tc_mode2d_sanity_rand_timing`: 1000 - `tc_mode_switch_random`: 1000 Simulation script baseline: @@ -148,6 +270,27 @@ If optional Step D is approved: - `tb_rtl/` testcases run successfully - `iverilog` passes - `verilator` passes +- `docs/regression_report.md` records the latest full regression evidence + +No flow stage may claim closure by functional PASS alone. If `design_spec.md` +contains optimizer-selected topology, closure requires spec/design/code/RTL/model/test +status to be either implemented and evidenced, or explicitly deferred with risk +and next required evidence. + +## 5.1) Pre-Push Review Gate + +Before any `git push` or PR creation, apply the project skill +`pre-push-code-review-gate`. + +Mandatory rule: + +1. Launch a dedicated `codereviewer` sub-agent before pushing. +2. Provide changed files, source spec, design spec, optimizer report when + present, generated RTL context, and latest regression evidence. +3. Fix all blocking findings before push. +4. If the reviewer reports only non-blocking findings, record the rationale for + proceeding. +5. Do not push if the `codereviewer` sub-agent has not run. ## 6) Fixed Debug SOP diff --git a/designs/PE_INT/.cursor/skills/pre-push-code-review-gate/SKILL.md b/designs/PE_INT/.cursor/skills/pre-push-code-review-gate/SKILL.md new file mode 100644 index 0000000..97c2e69 --- /dev/null +++ b/designs/PE_INT/.cursor/skills/pre-push-code-review-gate/SKILL.md @@ -0,0 +1,65 @@ +--- +name: pre-push-code-review-gate +description: Requires a codereviewer sub-agent review before git push. Use when preparing PE_INT changes for push, PR creation, or any remote publication after implementation, generated RTL, docs, or test changes. +--- + +# Pre-Push Code Review Gate + +Use this skill before any `git push` or PR creation that publishes PE_INT +changes to a remote repository. + +## Mandatory Gate + +Before pushing: + +1. Confirm the intended push scope and current changed files. +2. Confirm required builds/regressions have been run or explicitly record why + they were not run. +3. Launch a dedicated `codereviewer` sub-agent. +4. Provide the reviewer with: + - changed files and a concise change summary + - relevant specs: `docs/spec.md`, `docs/design_spec.md` + - relevant reports: `docs/circuit_optimizer_report.md` when present + - latest build/regression evidence + - known deferred items or accepted limitations + - optimizer topology implementation status and evidence +5. Treat blocking findings as must-fix before push. +6. If findings are non-blocking, record the rationale for proceeding. +7. Only push after the review result is clean or all blocking findings are + resolved and rechecked. + +## Reviewer Prompt Requirements + +The `codereviewer` prompt must ask for: + +- functional correctness risks +- spec/design_spec mismatch +- generated RTL consistency with PyCircuit source +- model/testbench/golden-reference mismatch +- latency/control-data alignment issues +- width/sign-extension/truncation risks +- unused/dead signal risks +- missing regression evidence +- optimizer-selected topology that is claimed but not implemented +- mode-2a `out1` hold coverage in model and RTL tests +- whether the changes are safe to push + +Known limitation handling: + +- The current PE_INT reset release mismatch caused by PyCircuit framework reset + generation may be marked as a known deferred framework limitation when the + user has explicitly accepted it for the current push. +- The reviewer should still report it, but it should not block by itself unless + new reset behavior was changed or the limitation is no longer documented. + +## Stop Conditions + +Do not push if: + +- the `codereviewer` sub-agent has not run +- the review reports unresolved blocking issues +- generated RTL was changed but not rebuilt from PyCircuit +- required regression evidence is missing without explicit user approval +- `design_spec.md` claims an optimizer-selected topology is implemented while + PyCircuit source or generated RTL shows it is deferred or absent + diff --git a/designs/PE_INT/docs/circuit_optimizer_report.md b/designs/PE_INT/docs/circuit_optimizer_report.md new file mode 100644 index 0000000..08f1dd1 --- /dev/null +++ b/designs/PE_INT/docs/circuit_optimizer_report.md @@ -0,0 +1,262 @@ +# PE_INT Circuit Optimizer Report + +Pass: `0` + +Provenance: `Optimizer-subagent-selected, pass 0` + +Scope: topology optimization decisions only. No source-spec behavior is changed, +and no topology decision here is claimed as derived from `docs/spec.md`. + +## Inputs Reviewed + +- `docs/spec.md`, baseline v2.0.6 +- Current `docs/design_spec.md` +- `.cursor/skills/circuit-optimizer/SKILL.md` +- `.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md`, Step A.1/A.2 +- Project logic-depth policy: input prelogic `<= 8`, main pipeline stage target + about 25 effective logic layers + +## Objective + +Objective: `balanced` + +Priority: + +1. Meet fixed latency `L=4`. +2. Keep input-pin to first-register logic `<= 8`. +3. Keep main stages near about 25 effective logic layers. +4. Then reduce area and power. + +Default optimizer budget: + +- Pass 0 topology selection before implementation. +- 2 post-build optimizer iterations after generated RTL and verification + evidence exist unless the user explicitly specifies another budget. + +## Pass 0 Decisions + +| Item | Decision | Reason | +|---|---|---| +| Multiplier | Radix-4 Booth is the pass-0 target for S8-involved products; current implementation remains natural-width signed shift/add/sub style. S5*S5 uses direct signed partial products. | Keep structural Booth intent for timing/area optimization, but defer implementation until synthesis/timing/area evidence justifies the rewrite risk. | +| Dot8 reduction | Wallace-style carry-save compression tree with explicit `CMPE42`/`FA`/`HA` cells. | Avoids serial carry propagation through multiple adders and supports the 25-layer stage target. | +| Final CPA | Brent-Kung prefix adder for 16-bit and 19-bit final sums. | Better depth than RCA with lower wire/area pressure than Kogge-Stone. | +| Mode 2c shifter | Fixed shift-by-0/1/2 wiring plus 3-way mux. | Matches the bounded E1 scale requirement without full barrel-shifter cost. | +| Mode output MUX | Balanced staged 2:1 mux tree with pipelined mode decode. | Predictable shallow select path; avoids long priority chains. | +| Mode 2a `out1` policy | Hold previous registered `out1` value on valid mode-2a commit. | Minimizes unnecessary output toggles and satisfies stability without queue/FIFO state. | + +## Estimated Logic Depth + +These are pass 0 estimates only; multiplier and mapped prefix-adder depth must +be checked after RTL/synthesis. + +| Cone | Estimate | Risk | +|---|---:|---| +| Input prelogic | About 2 to 6 effective layers | Should fit `<= 8` if limited to slicing, sign decode, mode decode, and shift-select decode. | +| S8-involved multiplier stage | Design-dependent, roughly medium depth | Highest unknown before RTL; Booth sign correction and local reduction must be inspected. | +| S5*S5 multiplier stage | Lower than S8 paths | Low to medium risk. | +| Dot8 Wallace compression | About 2 to 3 compressor layers | Medium risk if generated as serial `+` tree instead of explicit compression. | +| Brent-Kung final CPA 16/19-bit | About 15 to 20 effective layers | Expected to fit one stage with muxing, but close enough to require post-build inspection. | +| Mode 2c shift + merge | About 2 mux layers plus small CSA merge | Medium risk if placed in the same cone as final CPA without a register boundary. | +| Output mux | About 2 mux layers | Low risk if implemented as balanced tree. | + +## Area / Power Tradeoff + +- Booth S8 multipliers reduce partial-product rows and switching in wider paths, + at the cost of recoder and correction logic. +- Direct S5*S5 multipliers avoid over-optimizing tiny lanes and should reduce + area/power versus Booth for that case. +- Wallace compression uses more structured compressor cells and wiring than a + simple adder tree, but avoids repeated carry propagation. +- Brent-Kung CPA is the balanced choice: less area/wire than Kogge-Stone and + much lower depth than ripple for 16/19-bit sums. +- Mode 2c fixed shifters avoid the area/power of generic barrel shifters. +- Mode-2a `out1` hold adds a feedback mux but avoids toggling the registered + output unnecessarily. + +## Post-Build Checks + +Run these after PyCircuit implementation, RTL generation, and functional +regression: + +1. Confirm real register count gives `vld -> vld_out` latency `L=4` for all + modes. +2. Confirm `out0`, `out1`, and `vld_out` are registered at the same boundary. +3. Inspect whether multiplier RTL matches the selected Booth/direct split. +4. Inspect whether Dot8 reduction uses compressor structure; flag any generic + serial `+` tree as an implementation limitation. +5. Check that `CMPE42.Cox`/`Cix` chaining preserves bit weight and does not drop + MSB chain carry. +6. Check mode 2c shift/merge is bounded shift-by-0/1/2, not a generic barrel + shifter. +7. Check final CPA topology or inferred structure; compare Brent-Kung intent + against generated RTL and synthesis mapping. +8. Check output mux depth and mode-2a `out1` hold behavior. +9. Collect area/timing/power reports if synthesis is available. +10. If reports show a critical path or excessive area/power, perform post-build + optimizer iteration 1 of 2. + +## Pass 1 (Post-Build) — Decision: `modify` + +Pass: `1` + +Provenance: `Optimizer-subagent-selected, pass 1` + +Inputs: + +- Generated RTL and post-build functional regression evidence +- Prior pass 0 topology intent +- Iteration 1 required fixes for CPA boundary and mode-2c merge structure + +### Pass 1 Applied Changes + +| Item | Pass 1 Decision | Implementation Status | +|---|---|---| +| Mode-2c low/high merge | Replace generic `+` with explicit `brent_kung_cpa_truncated(lo_scaled, hi_scaled, width)` | Done in `python/pe_int/lane_mac.py::sum_shift_pair()` | +| Dot8 terminal `Cox` policy | Apply explicit fixed-width truncation policy at final CPA boundary when carry weight is `2^W` and `W` is reducer output width | Done in `python/pe_int/lane_mac.py::_wallace_dot8_reduce()` and documented in `docs/design_spec.md` section 10.3 | +| Multiplier topology | Keep current natural-width signed functional implementation; defer full radix-4 Booth structural realization for S8-involved products | Deferred (`needs-synthesis / deferred structural improvement`) | + +### Multiplier Deferred Note + +Current multiplier implementation is functionally correct and natural-width with +sign-correction behavior, but does not yet provide a fully explicit radix-4 +Booth structural realization for all S8-involved products in generated RTL. +This item is deferred to a follow-up structural iteration with synthesis-backed +evidence (`needs-synthesis / deferred structural improvement`). + +### Rationale + +1. The explicit BK CPA replacement removes mode-2c generic adder merge at the + intended final-merge boundary. +2. The terminal `Cox` handling is now explicit policy rather than implicit + behavior: out-of-range carry beyond fixed output width is intentionally + truncated. +3. Multiplier structural conversion risk is non-trivial relative to current + all-pass functional baseline; therefore deferred to avoid destabilizing RTL + while preserving correctness. + +## Pass 2 + +Provenance: `Optimizer-subagent-selected, pass 2` + +Decision: `stop / keep current` + +### Inputs Reviewed + +- `docs/spec.md` +- `docs/design_spec.md` +- `docs/circuit_optimizer_report.md` +- `.cursor/skills/circuit-optimizer/SKILL.md` +- `python/pe_int/lane_mac.py` +- `python/pe_int/mac_modes.py` +- `python/pe_int/top.py` +- `rtl/build/pe_int.v` +- `rtl/build/pe_int_wallace_dot8_tree_w16.v` +- `rtl/build/pe_int_wallace_dot8_tree_w19.v` +- `filelist/pe_int.f` + +### Pass 2 Findings + +| Item | Status | Decision | +|---|---|---| +| Mode-2c final merge | Pass 1 fix is effective. `sum_shift_pair()` now calls `brent_kung_cpa_truncated(...)`; generated RTL shows bounded shift muxing followed by bit-level prefix carry logic, not a generic final `+`. | Keep current | +| Dot8 terminal `Cox` policy | Pass 1 fix is effective. `_wallace_dot8_reduce()` explicitly treats terminal `Cox` as weight `2^W` and intentionally truncates it at the fixed-width CPA boundary. This is now documented policy, not an accidental drop. | Keep current | +| Unused-bit / Verilator risk | No new structural unused-bit risk found in the inspected generated RTL. The latest final pass has no Verilator warning. | Keep current | +| Actual radix-4 Booth | Not implemented as explicit radix-4 Booth in generated RTL. Current multiplier remains natural-width signed shift/add plus sign-correction structure. Functional regressions pass, but structural Booth benefit cannot be proven without synthesis/timing/area evidence. | Defer to synthesis | +| Dot8 Wallace reducers | Generated W16/W19 reducer modules are explicit gate-level compressor/prefix structures with no `+` operator matches. | Keep current | +| Output commit / mode-2a `out1` hold | Generated RTL keeps `out1` as a registered state with valid-gated hold and mode-2a feedback hold. | Keep current | +| Model protocol coverage (mode-2a `out1`) | Added explicit model unittest coverage for hold/stable policy at valid commit boundary (`model/test_pe_int.py::test_mode2a_out1_hold_policy_on_vld_out`). | Keep current | + +### RTL Proxy Metrics + +No synthesis timing, area, or power report was available; the following are RTL +proxy estimates only. + +| Metric | RTL Proxy Observation | Estimate | +|---|---|---| +| Input prelogic depth | Top RTL captures raw buses directly and only predecodes mode equality before `reg0`. | Fits `<= 8` effective layers. | +| Comb1 multiplier depth | Multipliers are unrolled shift/add/sub structures. Example S8 path shows serial add chain plus sign corrections. | Highest remaining depth risk; acceptable only because regressions pass and no synthesis evidence says it fails. | +| Comb2 Dot8 reduction depth | 5 W19 and 4 W16 Wallace reducer instances. Reducer files contain compressor/prefix gate structure and no `+` operator. | Better than serial adder tree; likely within intended reduction-stage target, but STA required. | +| Comb3 mode2c merge depth | Shift-by-0/1/2 muxing plus explicit 16/19-bit Brent-Kung-style prefix CPA and 2-level output mux. | Expected near but reasonable for ~25-layer target; STA required for closure. | +| Area proxy | Top RTL has 106 `PYC_REG` instances, 5 W19 reducers, 4 W16 reducers; top still contains many multiplier add/sub/mux nodes. | Area dominated by replicated natural-width multipliers and reducer instances. | +| Power proxy | Mode-2a `out1` hold reduces output toggling; fixed shifters avoid barrel shifter cost. Multipliers still likely toggle more than a true Booth implementation. | Current power is acceptable for functional closure; Booth may improve later if synthesis supports it. | + +### Stop Condition + +No further Pass 2 modification is recommended. The requested two post-build +optimizer iterations are complete, functional regressions are passing, Pass 1's +targeted risks are resolved, and the only meaningful remaining improvement is +structural radix-4 Booth. That item is deferred until synthesis/timing/area +evidence exists instead of being forced into the current all-pass RTL baseline. + +## Current Topology / Status Audit + +Decision: `stop / keep current` + +The default optimizer budget is satisfied: pass 0 topology selection plus two +post-build optimizer iterations. Current closure is based on PyCircuit source +and generated RTL proxy evidence; no synthesis timing, area, or power report is +available. + +Reset note: reset behavior is treated as a user-accepted known PyCircuit +framework limitation for this audit and is not a blocking topology issue. + +Outstanding deferred item: explicit radix-4 Booth structural multiplier +implementation for S8-involved products. The current natural-width signed +multiplier implementation is functionally retained; structural Booth conversion +should wait for synthesis/timing/area evidence. + +## Post-Build CircuitOpt Rerun — 2 Iterations + +Provenance: `Optimizer-subagent-rerun, post-build default 2 iterations` + +Scope: read-only topology audit against current `docs/design_spec.md`, +PyCircuit source, generated `rtl/build/*.v`, model tests, and latest regression +evidence. No DS/code/RTL/test changes were made by this optimizer rerun. + +### Iteration 1/2 — Decision: `keep current` + +Current synced RTL already contains the prior targeted post-build fixes: +mode-2c low/high merge uses explicit `brent_kung_cpa_truncated(...)`, and Dot8 +terminal `Cox` is documented/implemented as intentional fixed-width truncation +at the final CPA boundary. No new blocking topology mismatch was found. + +Keep-current evidence: + +| Topology Item | Status | Evidence | +|---|---|---| +| Multiplier | `Partially implemented / Deferred` | PyCircuit uses natural-width signed shift/add/sub style product generation. Explicit radix-4 Booth for S8-involved products remains deferred until synthesis/timing/area evidence justifies the structural rewrite. | +| Dot8 Wallace reducer | `Implemented` | `PE_INT_WALLACE_DOT8_TREE_W19` and `PE_INT_WALLACE_DOT8_TREE_W16` generated modules are explicit compressor/prefix gate structures; no generic `+`/`*` operator is present in the reducer modules. | +| Final CPA | `Implemented` | `brent_kung_cpa_truncated()` is used for reducer final sums and mode-2c low/high merge; generated RTL shows bit-level prefix carry logic. | +| Mode2c shifter/merge | `Implemented` | Generated RTL uses bounded shift-by-0/1/2 plus muxing, then explicit prefix CPA merge. | +| Output mux | `Implemented` | Generated RTL uses staged 2:1 mux selection for mode output merge. | +| Mode2a `out1` hold | `Implemented` | Generated RTL keeps `out1` as registered feedback state with valid-gated mode-2a hold; model includes commit-boundary hold coverage. | +| Unused signal risk | `Keep current` | Latest regression evidence reports Verilator `-Wall`, no `-Wno-UNUSEDSIGNAL`, and no observed `UNUSEDSIGNAL`. | +| Regression evidence | `PASS` | Model unittest PASS, PyCircuit build/RTL sync PASS, compiled PyCircuit TB PASS, full RTL regression PASS on iverilog + Verilator. | + +Reset note: reset behavior is treated as a user-accepted known PyCircuit +framework limitation for this audit and is not a blocking topology issue. + +### Iteration 2/2 — Decision: `stop / keep current` + +No further post-build modification is recommended within the default +two-iteration budget. The remaining meaningful topology improvement is explicit +radix-4 Booth structural realization for S8-involved multipliers, but current +evidence is functional/regression-only and does not include synthesis timing, +area, or power reports. Forcing that rewrite now would risk destabilizing an +all-pass baseline without proof of QoR benefit. + +Stop condition: + +- Default post-build iteration budget is complete. +- All required functional/regression evidence is passing. +- Optimizer-selected topologies are either implemented and evidenced, or + explicitly deferred. +- No new unused-signal warning risk is reported. +- Reset limitation is noted as accepted framework behavior, not a blocking + topology issue. + +Next optimization candidate, if synthesis evidence becomes available: compare +current natural-width signed multiplier cones against explicit radix-4 Booth +implementations for timing, area, and power before changing PyCircuit source or +regenerated RTL. + diff --git a/designs/PE_INT/docs/design_spec.md b/designs/PE_INT/docs/design_spec.md index fb134b6..6a979e1 100644 --- a/designs/PE_INT/docs/design_spec.md +++ b/designs/PE_INT/docs/design_spec.md @@ -1,305 +1,400 @@ -# PE_INT Design Spec (DS) +# PE_INT Design Spec -Version: v0.4 -Source of truth for function: `docs/spec.md` (baseline v2.0.6) -This DS defines low-level circuit structure and stage-level implementation constraints. +Version: v0.8 +Generated from: `docs/spec.md` baseline v2.0.6 +Generation rule: `.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md` ---- - -## 1. Scope and Design Policy - -- Functional behavior, mode semantics, and top-level contract are inherited from `docs/spec.md`. -- This DS is implementation-oriented and focuses on: - - bit-slice decode and lane mapping - - arithmetic unit structure - - pipeline partition and register boundaries - - control/data alignment at output commit points -- Pipeline partition follows logic-depth guidance: - - target per comb stage: around 25 effective logic layers - - input pin to first register: <= 8 effective logic layers - -### 1.1 Top-Level IO Behavior Contract - -| Port | Dir | Width | Behavior Contract | -|------|-----|-------|-------------------| -| `clk` | in | 1 | Single clock domain, posedge sequential behavior | -| `rst_n` | in | 1 | Active-low reset, async assert + sync release | -| `vld` | in | 1 | Input transaction qualifier, no ready backpressure | -| `mode` | in | 2 | Per-transaction mode (`2a/2b/2c/2d`) | -| `a` | in | 80 | Shared packed A bus | -| `b` | in | 80 | Shared packed B/B0 bus | -| `b1` | in | 80 | Shared packed B1 bus | -| `e1_a` | in | 2 | E1 scale bits for A groups (mode `2c`) | -| `e1_b0` | in | 2 | E1 scale bits for B0 groups (mode `2c`) | -| `e1_b1` | in | 2 | E1 scale bits for B1 groups (mode `2c`) | -| `vld_out` | out | 1 | Output valid aligned with committed outputs | -| `out0` | out | 19 | Registered signed output 0 | -| `out1` | out | 16 | Registered signed output 1 with mode-2a hold policy | - -Hard IO constraints: - -- No additional top-level reset port is allowed in deliverable RTL. -- Pipeline latency and stage count are mode-invariant. -- In mode `2a`, `out1` must remain stable by hold policy (no unnecessary toggles). - -### 1.2 Latency Convention (Normative) - -- This DS uses a 0-based latency definition. -- `t0` is the input sample cycle where one transaction is accepted (`vld=1`). -- Fixed `L=4` means the corresponding committed output valid is observed at `t0+4`. -- Latency must be validated by counting real register boundaries on generated RTL paths. -- Do not infer latency from stage naming (`s0/s1/...`) or comments alone. +This document is the structure-first design spec derived from `docs/spec.md`. +It describes low-level circuit contracts, widths, bus routing, pipeline +boundaries, and protocol timing. Topologies not stated by the source spec are +first marked as `Unspecified by source spec`. Concrete topology choices may then +be added in an optimizer-owned section with explicit provenance from an +independent Circuit Optimizer sub-agent. --- -## 2. Data Types and Bit-Slice Mapping - -### 2.1 Unified lane container +## 1. Scope and Source Boundary -- Physical carrier lane width: 5 bits. -- Lane mapping: `lane[i] = x[5*i+4 : 5*i]`. +`docs/spec.md` defines behavior. This design spec maps that behavior onto +low-level circuit modules and register boundaries. -Decode rules: +Rules: -- `S8` (2a/2b/2d A-side and 2a B-side): combine two lanes' `[4:1]`. -- `S4` (2b B-side): lane `[4:1]`. -- `S5` (2c and 2d B-side): lane `[4:0]`. +1. Business modes (`2a/2b/2c/2d`) share one fixed-latency pipeline. +2. Circuit modules are described before mode-specific parameter mapping. +3. Widths use the minimum lossless contract derivable from `docs/spec.md`. +4. Arbitrary operand or result margin widths are forbidden. +5. Any topology not stated by `docs/spec.md` remains `Unspecified by source + spec` in source-derived sections. +6. Optimizer-selected topologies are design decisions, not source-spec + contracts, and must be labeled with sub-agent provenance, pass number, and + objective. -### 2.2 Signed extension rule +--- -- All decoded values are sign-extended before arithmetic. -- Internal width tracking follows no-loss arithmetic intent, not tool-default truncation. +## 2. Top-Level Module Contract + +| Port | Dir | Width | Signed | Circuit Contract | +|------|-----|-------|--------|------------------| +| `clk` | in | 1 | no | Single clock domain | +| `rst_n` | in | 1 | no | Active-low reset intent | +| `vld` | in | 1 | no | Input transaction qualifier | +| `mode` | in | 2 | no | Per-transaction mode selector | +| `a` | in | 80 | packed | Shared A input bus | +| `b` | in | 80 | packed | Shared B/B0 input bus | +| `b1` | in | 80 | packed | B1 input bus for mode 2c | +| `e1_a` | in | 2 | no | Mode 2c A group scale bits | +| `e1_b0` | in | 2 | no | Mode 2c B0 group scale bits | +| `e1_b1` | in | 2 | no | Mode 2c B1 group scale bits | +| `vld_out` | out | 1 | no | Registered output valid | +| `out0` | out | 19 | yes | Registered output 0 | +| `out1` | out | 16 | yes | Registered output 1 | + +Reset and flow control: + +- `rst_n` is the only top-level reset port required by the source spec. +- `out0`, `out1`, and `vld_out` are registered outputs. +- There is no `ready` signal and no backpressure interface. +- A new transaction is sampled only when `vld=1`. +- Independent FIFO/queue structures are forbidden. --- -## 3. Compute Unit Structure - -### 3.1 Multiplier units +## 3. Bus Decode and DEMUX -All signed multipliers follow the same structural intent: +### 3.1 Physical Lane Container -1. Modified Booth recode -2. Partial-product select/mux -3. Compressor tree (3:2 / 4:2 style reduction) -4. Final carry-propagate adder (prefix-family intent) +Each 80-bit bus contains 16 physical 5-bit lanes: -Applied widths: +`lane[i] = bus[5*i+4 : 5*i]`, for `i=0..15`. -- `M8x8` for mode 2a -- `M8x4` for mode 2b -- `M8x5` for mode 2d -- `M5x5` for mode 2c +### 3.2 Decode Components -### 3.2 Dot-product reduction +| Component | Input Slice | Output Width | Signed | Used By | +|-----------|-------------|--------------|--------|---------| +| `DEC_S8` | two adjacent lane nibbles `[4:1]` | 8 | yes | S8 operands | +| `DEC_S4` | one lane nibble `[4:1]` | 4 | yes | S4 operands | +| `DEC_S5` | one full lane `[4:0]` | 5 | yes | S5 operands | -- Dot8 reduction for 2a/2b/2d branch sums -- Dot16 path for 2c split into two Dot8 branches (`lo`, `hi`) before post-scale merge +Decode outputs are natural-width signed operands. They are not widened to +top-level output width before multiplication. -### 3.3 Post-scale and mode merge +### 3.3 Mode to Bus Mapping -- For mode 2c, `shift = e1_a[k] + e1_bx[k]` (`k=0/1`, shift in `{0,1,2}`) -- Implement post-scale with bounded shift options (`x1/x2/x4`), not full barrel shifter intent -- Mode merge uses one-hot controls from registered control metadata -- Avoid direct `mode == const` comparator chains in late stage merge logic +| Mode | A Path | B/B0 Path | B1 Path | +|------|--------|-----------|---------| +| 2a | `8 x DEC_S8(a)` | `8 x DEC_S8(b)` | unused | +| 2b | `8 x DEC_S8(a)` | `B0=8 x DEC_S4(b[39:0])`, `B1=8 x DEC_S4(b[79:40])` | unused | +| 2c | `16 x DEC_S5(a)` | `16 x DEC_S5(b)` | `16 x DEC_S5(b1)` | +| 2d | `8 x DEC_S8(a)` | `B0=8 x DEC_S5(b[39:0])`, `B1=8 x DEC_S5(b[79:40])` | unused | -### 3.4 out1 hold policy +Mode DEMUX: -- Update condition: committed transaction valid and `mode != 2a` -- Otherwise hold previous `out1_hold` value -- `out1_hold` update control must align with output commit boundary +- The mode field selects output branch results at the aligned merge stage. +- All in-flight transactions preserve FIFO order. --- -## 4. Depth Probe Baseline +## 4. Low-Level Circuit Components -Reference probes are generated by: +### 4.1 Signed Multiplier -- `model/depth_probe_units.py` -- `model/estimate_logic_depth.py` +The source spec defines signed operand types. Therefore multiplier input widths +are natural operand widths, and product widths are exact signed product widths. -Measured structural estimates (effective layers): +| Product | Operand A | Operand B | Product Width | Signed | +|---------|-----------|-----------|---------------|--------| +| `P2A` | S8 | S8 | 16 | yes | +| `P2B0` | S8 | S4 | 12 | yes | +| `P2B1` | S8 | S4 | 12 | yes | +| `P2C0` | S5 | S5 | 10 | yes | +| `P2C1` | S5 | S5 | 10 | yes | +| `P2D0` | S8 | S5 | 13 | yes | +| `P2D1` | S8 | S5 | 13 | yes | -- `booth_mul_8x8`: 19 -- `booth_mul_8x5`: 19 -- `booth_mul_8x4`: 19 -- `booth_mul_5x5`: 19 -- `dot8_reduce_16b`: 17 -- `dot8_reduce_12b`: 15 -- `dot8_reduce_10b`: 15 -- `dot16_split8_post_scale_14b`: 11 +Rules: -Stage planning notes: +- Do not implement `S8*S8`, `S8*S4`, `S8*S5`, or `S5*S5` by first extending + operands to `out0` or `out1` width. +- The signed product is extended only when entering a wider reduction path. +- Multiplier topology: `Unspecified by source spec`. -- `comb1` estimate: ~19 -- `comb2` estimate: ~17 -- `comb3` estimate: ~14 +### 4.2 Reduction -Logic-depth decision guidance: +Reduction sums signed products in Dot8 groups. -- `<= 25`: within target -- `26..30`: acceptable guideline overflow; warn user and suggest optional repartition -- `> 30`: strong risk; propose repartition or structural optimization +| Reduction Path | Inputs | Input Width at Reduction | Output Width | +|----------------|--------|--------------------------|--------------| +| 2a out0 | 8 x `P2A` | sign-extend product to 19 | 19 signed | +| 2b out0 | 8 x `P2B0` | sign-extend product to 19 | 19 signed | +| 2b out1 | 8 x `P2B1` | sign-extend product to 16 | 16 signed | +| 2c out0 low/high | 8 x `P2C0` per group | sign-extend product to 19 | 19 signed partial | +| 2c out1 low/high | 8 x `P2C1` per group | sign-extend product to 16 | 16 signed partial | +| 2d out0 | 8 x `P2D0` | sign-extend product to 19 | 19 signed | +| 2d out1 | 8 x `P2D1` | sign-extend product to 16 | 16 signed | ---- +Topology: -## 5. Pipeline Micro-Architecture (Normative) +- Compressor tree topology: `Unspecified by source spec`. +- Adder tree topology: `Unspecified by source spec`. +- Final carry-propagate adder topology: `Unspecified by source spec`. -Top-level auditable chain: +### 4.3 Mode 2c Shifter -`input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3/output` +Mode 2c group scaling: -This partition is the DS baseline because it keeps each major comb stage near target guidance. +- `shift_lo = e1_a[0] + e1_bx[0]` +- `shift_hi = e1_a[1] + e1_bx[1]` +- legal shift values are `0`, `1`, and `2` -### 5.1 `comb0` (input-side prelogic) +The circuit needs only bounded x1/x2/x4 scaling. Exact shifter topology is +`Unspecified by source spec`. -Responsibilities: +### 4.4 MUX / DEMUX -- mode predecode and control fanout preparation -- input lane-wiring preparation -- valid/control preconditioning for stage entry +Mode selection routes reduced branch results to output candidates: -Constraint: +- `out0` candidates: 2a, 2b0, 2c0, 2d0 +- `out1` candidates: 2b1, 2c1, 2d1, plus the mode-2a stability policy -- input pin to `reg0`: <= 8 layers +Exact mux-tree topology is `Unspecified by source spec`. -### 5.2 `reg0` (input capture) +### 4.5 Registers / D Flip-Flops -Capture one transaction payload: +Required state: -- `vld, mode, a, b, b1, e1_a, e1_b0, e1_b1` +- Input capture registers. +- Pipeline registers to maintain fixed mode-invariant latency. +- Registered `vld_out`, `out0`, and `out1`. +- `out1` hold state or an equivalent documented stable-constant policy for + mode 2a. -### 5.3 `comb1` (product generation) +All modes traverse the same number of real register boundaries. -Datapath: +--- -- lane decode (`S8/S4/S5`) -- per-lane multiply generation for all mode branches +## 5. Pipeline Contract -Control-path: +The flow requires an auditable full pipeline: -- one-hot mode controls and aligned branch-control metadata preparation +`input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3/output` -### 5.4 `reg1` (post-product boundary) +Latency: -- register `comb1` outputs and aligned control metadata +- Fixed `L=4`. +- 0-based convention: a transaction sampled at `t0` produces committed output at + `t0+4`. +- `vld_out`, `out0`, and `out1` update at the same output register boundary. -### 5.5 `comb2` (dot reduction) +Input prelogic: -Datapath: +- Effective logic depth from input pins to the first register is `<= 8` layers. -- dot8 reductions for 2a/2b/2d -- split dot16 partial reductions for 2c (`lo`, `hi`) +Stage logic: -Control-path: +- Main target for each pipeline stage is around 25 effective logic layers. +- Exact topology choices remain source-bound in Section 4 and optimizer-owned + in Section 10. -- propagate aligned transaction controls in parallel +--- -### 5.6 `reg2` (post-reduction boundary) +## 6. Business Mode Mapping to Circuit Parameters -- register reduction outputs and aligned controls +| Mode | Multiplier Parameters | Reduction Parameters | Post-Scale | Output Rule | +|------|-----------------------|----------------------|------------|-------------| +| 2a | 8 x S8*S8 -> P16 | sign-extend P16 to 19, sum 8 | none | `out0=sum`, `out1` stable | +| 2b | 8 x S8*S4 -> P12 per path | B0: sign-extend to 19; B1: sign-extend to 16 | none | dual output | +| 2c | 16 x S5*S5 -> P10 per path | split low/high Dot8 groups | x1/x2/x4 per group | dual output | +| 2d | 8 x S8*S5 -> P13 per path | B0: sign-extend to 19; B1: sign-extend to 16 | none | dual output | -### 5.7 `comb3` (post-scale + mode merge) +--- -Datapath: +## 7. Flow Control and FSM -- 2c post-scale and `lo/hi` merge -- final mode-select merge to `out0_raw` and `out1_raw` +There is no multi-state controller FSM implied by `docs/spec.md`. -Control-path: +Valid behavior: -- derive aligned output-commit control metadata +- `vld=1` samples one input transaction. +- `vld=0` samples no new transaction. +- Back-to-back `vld=1` with mode changes is allowed. +- Transaction ordering remains FIFO at output. +- Under sustained valid traffic after pipeline fill, no output bubbles are + allowed. -Hard constraints: +Mode 2a `out1` behavior: -- `comb3` must be pure combinational logic (no state update) -- mode merge select controls come from registered one-hot metadata -- do not build independent side control chain that can drift from data order +- `out1` is mathematically don't-care in mode 2a. +- The circuit must avoid unnecessary toggles by holding the previous value or by + using a documented stable constant. -### 5.8 `reg3/output` (final output commit stage) +--- + +## 8. Typical Waveforms + +### 8.1 Single Transaction Latency -- commit `vld_out`, `out0`, `out1` from the same transaction boundary -- this stage is mandatory for fixed `L=4` under 0-based definition +```text +cycle t0 t1 t2 t3 t4 +vld 1 0 0 0 0 +mode/data M0 x x x x +vld_out 0 0 0 0 1 +out0/out1 hold hold hold hold result(M0) +``` -Normative commit intent: +### 8.2 Back-to-Back Mode Switch -- `out0_commit = out0_raw_aligned` -- `out1_commit = (vld_commit && out1_en_commit) ? out1_raw_aligned : out1_hold` -- `if (vld_commit) out1_hold <= out1_commit` +```text +cycle t0 t1 t2 t3 t4 t5 +vld 1 1 0 0 0 0 +mode 2b 2a x x x x +vld_out 0 0 0 0 1 1 +out0 hold hold hold hold 2b 2a +out1 hold hold hold hold 2b stable/hold +``` -Hard constraints: +### 8.3 Mode 2c Group Scaling -- no extra policy state on `out0` -- `out1_hold` update point must align with commit control point -- no cross-stage mixing of control and committed data +```text +LO = sum lanes[0..7] +HI = sum lanes[8..15] +SH_LO = e1_a[0] + e1_bx[0] +SH_HI = e1_a[1] + e1_bx[1] +OUT = (LO << SH_LO) + (HI << SH_HI) +``` --- -## 6. Mode-Specific Datapath Mapping +## 9. Source-Limited Structural Items -### 6.1 Mode 2a (`mode=00`) +The following items are intentionally not specified because `docs/spec.md` does +not define them: -- Decode `A_i: S8`, `B_i: S8` for 8 lanes -- `P_i = A_i * B_i` -- `out0 = sum_{i=0..7}(P_i)` sliced/extended to 19-bit contract -- `out1` follows hold policy +- Booth versus array versus other multiplier topology. +- Wallace/Dadda/compressor-tree versus adder-tree reduction topology. +- Carry-lookahead versus prefix versus ripple final adder topology. +- Exact bounded-shifter topology. +- Exact mux-tree shape. -### 6.2 Mode 2b (`mode=01`) +If any of these topologies are required for implementation or review, update +`docs/spec.md`, provide an explicit user-approved structural-policy source, or +record a Circuit Optimizer decision, then regenerate this design spec. -- `A_i: S8` -- `B0_i: S4` from `b[39:0]`, `B1_i: S4` from `b[79:40]` -- `out0 = sum(A_i * B0_i)` -- `out1 = sum(A_i * B1_i)` +--- -### 6.3 Mode 2d (`mode=11`) +## 10. Circuit Optimizer Pass 0 Topology Proposal -- Same dual-branch flow as mode 2b, with `B0/B1` as `S5` +Provenance: `Optimizer-subagent-selected, pass 0` -### 6.4 Mode 2c (`mode=10`) +This section records optimizer-owned topology decisions. These decisions are not +derived from `docs/spec.md`; they are selected by the independent Circuit +Optimizer for implementation guidance. -- 16-lane `S5` datapath for `A/B0/B1` -- Branch 0: - - `LO0 = sum_{i=0..7}(A_i * B0_i)` - - `HI0 = sum_{i=8..15}(A_i * B0_i)` - - `SUM0 = (LO0 << (e1_a[0]+e1_b0[0])) + (HI0 << (e1_a[1]+e1_b0[1]))` -- Branch 1 uses `B1/e1_b1` with the same structure +Objective: `balanced` ---- +Priority order: -## 7. Control Path Contract +1. Meet fixed `L=4`. +2. Keep input-pin to first-register prelogic `<= 8` effective logic layers. +3. Keep each main pipeline stage near the project target of about 25 effective + logic layers. +4. Then optimize area and power. -- one input `vld=1` transaction maps to one output `vld_out=1` transaction -- no FIFO/reorder semantics in datapath -- back-to-back mode switching is allowed -- transaction order must remain FIFO at output -- control and data must stay aligned at each register boundary +Iteration budget: ---- +- Default optimizer budget: pass 0 topology selection before implementation plus + 2 post-build optimizer iterations after PyCircuit build, generated RTL, and + functional regression evidence are available. -## 8. Verification Hooks - -Mandatory checks: - -1. **Contract consistency** - - `spec` and `DS` share same latency semantics (0-based, `t0 -> t0+L`) -2. **Stage audit** - - reviewer can identify `comb0/reg0 -> comb1/reg1 -> comb2/reg2 -> comb3/reg3/output` -3. **Real-path register count (generated RTL)** - - control path `vld -> vld_out` is exactly `L=4` - - committed data paths to `out0/out1` align with same transaction boundary -4. **Commit-point alignment** - - qualifier and outputs come from same commit stage - - `out1_hold` update aligns with commit control -5. **Logic-depth recording** - - record per-stage estimates and classify by decision guidance (`<=25`, `26..30`, `>30`) -6. **Regression and ordering** - - regression passes - - no bubble under sustained valid traffic after fill - - no reorder under alternating mode pairs (for example `2b -> 2a`) +### 10.1 Selected Topologies and Current Status ---- +| Block | Selection | Implementation Status | Evidence Pointer | Risk / Next Evidence | Provenance | +|---|---|---|---|---|---| +| Pipeline placement | Fixed `input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3/output`, `L=4`. | Implemented | `python/pe_int/top.py::build()`, generated `rtl/build/pe_int.v` register boundaries. | Confirm with RTL regression latency checks. | `Optimizer-subagent-selected, pass 0`; latency from `docs/spec.md`. | +| Signed multipliers | Natural-width signed products. Radix-4 Booth remains the S8-involved structural optimization intent, but current RTL uses signed shift/add/sub style product generation. | Partially implemented / Deferred | `python/pe_int/lane_mac.py::booth_mul_signed()`, `_mul_signed_twos_complement()`, generated multiplier add/sub chains in `rtl/build/pe_int.v`. | Explicit radix-4 Booth is deferred until synthesis/timing/area evidence justifies the structural rewrite. | `Optimizer-subagent-selected, pass 0`; post-build status audit. | +| Dot8 reduction | Wallace-style carry-save compression tree using `CMPE42`, `FA`, and `HA`, followed by one final CPA. | Implemented | `python/pe_int/lane_mac.py::_wallace_dot8_reduce()`, `rtl/build/pe_int_wallace_dot8_tree_w16.v`, `rtl/build/pe_int_wallace_dot8_tree_w19.v`. | STA required for real timing depth. | `Optimizer-subagent-selected, pass 0`; pass 1 terminal carry policy retained. | +| Final CPA | Brent-Kung-style prefix CPA for W16/W19 reductions and mode-2c low/high merge. | Implemented | `python/pe_int/lane_mac.py::brent_kung_cpa_truncated()`, `sum_shift_pair()`, generated prefix-style RTL. | Synthesis may remap; next evidence is mapped timing/netlist. | `Optimizer-subagent-selected, pass 0`; pass 1 mode-2c merge fix. | +| Mode 2c shifter | Fixed shift-by-0/1/2 using wire shifts plus muxing before final CPA. | Implemented | `python/pe_int/lane_mac.py::shift_scale_x1_x2_x4()`, generated shift/mux RTL in `rtl/build/pe_int.v`. | Check comb3 timing with STA. | `Optimizer-subagent-selected, pass 0`. | +| Mode output MUX | Balanced staged 2:1 mux tree using pipelined mode decode. | Implemented | `python/pe_int/lane_mac.py::select_one_hot4()`, `python/pe_int/mac_modes.py::comb3_mode_merge()`, generated mux tree in `rtl/build/pe_int.v`. | Mapped timing/power evidence still pending. | `Optimizer-subagent-selected, pass 0`. | +| Mode 2a `out1` stable policy | Hold previous registered `out1` on valid mode-2a commit. | Implemented | `python/pe_int/top.py` output commit logic, generated `pe_int_out1` feedback register/mux, and model protocol coverage in `model/test_pe_int.py::test_mode2a_out1_hold_policy_on_vld_out`. | Keep RTL regression for mode switching and mode-2a stability. | `Optimizer-subagent-selected, pass 0`; stability requirement from `docs/spec.md`. | + +### 10.2 Pipeline Placement Intent -## 9. Notes +Use the fixed latency shape: + +`input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3/output` -- This DS is low-level and structure-first. -- If arithmetic topology changes, rerun depth estimation and update Section 4. -- If stage partition changes, re-validate latency and commit alignment using generated RTL real-path counts. +Pass 0 placement: + +| Region | Intended Work | +|---|---| +| `comb0` | Lane slicing, sign decode, mode one-hot/predecode, mode-2c shift-select decode. Must remain `<= 8` effective layers from input pins to `reg0`. | +| `comb1` | Multiplier partial-product generation and local small reduction for natural-width products. | +| `comb2` | Dot8 Wallace compression to final two-vector carry-save form. For mode 2c, also perform bounded shift wiring/muxing and low/high carry-save merge where practical. | +| `comb3` | Brent-Kung final CPA, sign extension to top-level width, balanced output mux, and output-register commit/hold policy. | + +### 10.3 Wallace Dot8 Cell-Level Contract + +The selected Dot8 reduction is a Wallace-style carry-save compression tree, not +a serial `+` operator tree. + +Allowed cells: + +| Cell | Pins | Bit-Weight Contract | +|---|---|---| +| `CMPE42[k]` | Inputs: `x0`, `x1`, `x2`, `x3`, `Cix`. Outputs: `sum`, `carry`, `Cox`. | `x0..x3` and `Cix` have weight `2^k`. `sum` has weight `2^k`. `carry` has weight `2^(k+1)`. `Cox` has weight `2^(k+1)` and may feed the next higher column peer cell's `Cix`. | +| `FA[k]` | Inputs: `x0`, `x1`, `x2`. Outputs: `sum`, `carry`. | Inputs and `sum` have weight `2^k`; `carry` has weight `2^(k+1)`. | +| `HA[k]` | Inputs: `x0`, `x1`. Outputs: `sum`, `carry`. | Inputs and `sum` have weight `2^k`; `carry` has weight `2^(k+1)`. | + +Chaining policy: + +- Within one compression layer, `CMPE42[k].Cox` may feed `CMPE42[k+1].Cix`. +- The least-significant column chain input is tied to zero. +- The most-significant `Cox` is preserved as a residual next-weight bit; it + must not be dropped. +- `FA` and `HA` carries are forwarded to the next higher bit column in the next + compression layer. + +Residual-column handling: + +- Use `CMPE42` where column height and adjacent-chain availability make it + useful. +- Use `FA` for residual triples. +- Use `HA` only when it reduces the next layer's maximum height or is needed for + termination. +- One or two remaining bits in a column may pass through unchanged. + +Termination: + +- Compression stops when every bit column has at most two remaining bits. +- The remaining bits form two aligned carry-save vectors. +- The final carry-propagate boundary is the selected Brent-Kung CPA. +- For fixed-width reducer outputs (`W=19` for `out0` paths, `W=16` for `out1` + paths), any carry bit with weight `2^W` is outside the source-spec output + width contract and is intentionally truncated at the fixed-width final CPA + boundary. This is an explicit fixed-width arithmetic policy, not a silent + implementation drop. +- For mode 2c, low/high Dot8 carry-save vectors should be shifted and merged in + carry-save form before the final CPA when possible, so the path uses one final + CPA rather than per-group CPAs plus another adder. + +### 10.4 Post-Build Evidence Required + +After PyCircuit coding, `pycc` RTL generation, and functional regression, +collect: + +1. Generated RTL hierarchy and whether multiplier/reduction structure matches + this pass 0 topology. +2. Evidence that Dot8 reductions are compressor trees, not generic serial `+` + chains. +3. Register-boundary count for `out0`, `out1`, and `vld_out`; confirm fixed + `L=4`. +4. Input-pin to first-register logic cone estimate; confirm `<= 8`. +5. Per-stage logic-depth estimate, especially multiplier stage and final CPA/mux + stage. +6. Width audit for product, sign extension, shift, carry-save vectors, final + CPA, and top-level outputs. +7. Mux-depth audit for mode output selection and mode-2a `out1` hold. +8. Functional regression results for all modes and back-to-back mode switching. +9. Synthesis timing/area/power reports when available; otherwise use RTL proxy + metrics only. diff --git a/designs/PE_INT/docs/regression_report.md b/designs/PE_INT/docs/regression_report.md new file mode 100644 index 0000000..c51f855 --- /dev/null +++ b/designs/PE_INT/docs/regression_report.md @@ -0,0 +1,78 @@ +# PE_INT Regression Report + +Date: 2026-05-07 + +Git HEAD at run start: `1372963` + +Scope: + +- Model unittest +- PyCircuit build and generated RTL sync +- Compiled PyCircuit testbench +- RTL testcase regeneration +- RTL regression with `iverilog` +- RTL regression with `verilator -Wall` + +Known deferred item: + +- Reset release mismatch is treated as a user-accepted PyCircuit framework + limitation for this run. +- Explicit radix-4 Booth structural multiplier implementation for S8-involved + products remains deferred pending synthesis/timing/area evidence. + +## Commands + +Model unittest: + +```bash +wsl bash -lc 'cd /mnt/d/git-repo/pycircuit/designs/PE_INT && PYTHONPATH=/mnt/d/git-repo/pycircuit/compiler/frontend:/mnt/d/git-repo/pycircuit/designs/PE_INT/python python3 model/test_pe_int.py' +``` + +PyCircuit build and generated RTL sync: + +```bash +wsl bash -lc 'cd /mnt/d/git-repo/pycircuit/designs/PE_INT && PATH=/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:$HOME/.local/bin PYTHONPATH=/mnt/d/git-repo/pycircuit/compiler/frontend:/mnt/d/git-repo/pycircuit/designs/PE_INT/python python3 python/build.py --target both --out-dir build/pe_int --jobs 8 --pyc-tb-vectors 8' +``` + +Compiled PyCircuit testbench: + +```bash +wsl bash -lc 'cd /mnt/d/git-repo/pycircuit/designs/PE_INT && ./build/pe_int/cpp_build/build/pyc_tb' +``` + +Full RTL regression: + +```bash +wsl bash -lc 'cd /mnt/d/git-repo/pycircuit/designs/PE_INT && PATH=/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:$HOME/.local/bin bash sim/run_all_wsl.sh' +``` + +## Results + +| Step | Result | Evidence | +|---|---|---| +| Model unittest | PASS | `build/regression_logs/model_unittest.log`: 5 tests, OK | +| PyCircuit build | PASS | `build/regression_logs/pycircuit_build.log`: `pycircuit.cli build --target both`, `Synced generated RTL into .../rtl/build` | +| PyCircuit TB | PASS | `build/regression_logs/pycircuit_tb.log`: `OK` | +| RTL vector generation | PASS | `build/regression_logs/rtl_regression.log`: `Regenerating testcase vectors from model/ ...` | +| RTL iverilog regression | PASS | `build/regression_logs/rtl_regression.log`: all 9 cases passed before Verilator stage | +| RTL Verilator regression | PASS | `build/regression_logs/rtl_regression.log`: all 9 cases passed; final line reports all cases passed on `iverilog + verilator` | + +RTL cases: + +- `tc_mode2a_sanity` +- `tc_mode2a_sanity_rand_timing` +- `tc_mode2b_sanity` +- `tc_mode2b_sanity_rand_timing` +- `tc_mode2c_sanity` +- `tc_mode2c_sanity_rand_timing` +- `tc_mode2d_sanity` +- `tc_mode2d_sanity_rand_timing` +- `tc_mode_switch_random` + +Warning summary: + +- Verilator was run with `-Wall` and the project warning flags in + `sim/run_all_wsl.sh`. +- `-Wno-UNUSEDSIGNAL` is not used. +- No `UNUSEDSIGNAL` warning was observed in the full RTL regression log. + diff --git a/designs/PE_INT/model/test_pe_int.py b/designs/PE_INT/model/test_pe_int.py index 47498a0..6f27794 100644 --- a/designs/PE_INT/model/test_pe_int.py +++ b/designs/PE_INT/model/test_pe_int.py @@ -158,6 +158,68 @@ def test_mode2a_out1_no_toggle(self) -> None: dut.step(rst_n=1, vld=1, mode=MODE_2A, a=a, b=b, b1=b1, e1_a=e1a, e1_b0=e1b0, e1_b1=e1b1) self.assertEqual(dut.out1, base_out1) + def test_mode2a_out1_hold_policy_on_vld_out(self) -> None: + dut = PEIntModel() + for _ in range(3): + dut.step( + rst_n=1, + vld=0, + mode=MODE_2A, + a=0, + b=0, + b1=0, + e1_a=(0, 0), + e1_b0=(0, 0), + e1_b1=(0, 0), + ) + + tx_modes = [MODE_2B, MODE_2A, MODE_2A, MODE_2D] + expected: list[tuple[int, int, int]] = [] + hold_out1 = 0 + for mode in tx_modes: + a, b, b1, e1a, e1b0, e1b1 = _make_txn(mode) + ref = compute_transaction(mode, a, b, b1, e1a, e1b0, e1b1) + exp_out1 = hold_out1 if mode == MODE_2A else ref.out1_16 + expected.append((mode, ref.out0_19, exp_out1)) + if mode != MODE_2A: + hold_out1 = ref.out1_16 + dut.step( + rst_n=1, + vld=1, + mode=mode, + a=a, + b=b, + b1=b1, + e1_a=e1a, + e1_b0=e1b0, + e1_b1=e1b1, + ) + + got: list[tuple[int, int, int]] = [] + for _ in range(DEFAULT_PIPELINE_L + 4): + step = dut.step( + rst_n=1, + vld=0, + mode=MODE_2A, + a=0, + b=0, + b1=0, + e1_a=(0, 0), + e1_b0=(0, 0), + e1_b1=(0, 0), + ) + if step.vld_out: + mode, exp_out0, exp_out1 = expected[len(got)] + got.append((mode, step.out0, step.out1)) + self.assertEqual(step.out0, exp_out0) + self.assertEqual( + step.out1, + exp_out1, + msg=f"mode {mode} committed unexpected out1 hold behavior", + ) + + self.assertEqual(len(got), len(expected)) + def test_async_reset_clears_pipeline(self) -> None: dut = PEIntModel() # inject a valid sample diff --git a/designs/PE_INT/python/pe_int/lane_mac.py b/designs/PE_INT/python/pe_int/lane_mac.py index 1ff12b1..ac6f306 100644 --- a/designs/PE_INT/python/pe_int/lane_mac.py +++ b/designs/PE_INT/python/pe_int/lane_mac.py @@ -13,11 +13,49 @@ def booth_mul_signed(lhs, rhs): """ - DS §3.1 multiplier structural policy entry. - RTL generation is expected to map this operation into the - shared booth+compressor+BK template tracked by depth-probe flow. + Current functional signed multiplier entry point. + + Explicit radix-4 Booth remains a documented deferred topology optimization; + this implementation keeps natural-width signed shift/add/sub behavior. """ - return lhs * rhs + lhs_w = wire_of(lhs) + rhs_w = wire_of(rhs) + lhs_bits = lhs_w.width + rhs_bits = rhs_w.width + if lhs_bits <= 8 and rhs_bits <= 8: + return _mul_signed_twos_complement(lhs_w, rhs_w) + return lhs_w * rhs_w + + +def _mul_unsigned_rows(lhs, rhs, *, width: int): + lhs_w = wire_of(lhs) + rhs_w = wire_of(rhs) + zero = zext(lhs_w[0:1], width) & 0 + acc = zero + for bit_idx in range(rhs_w.width): + row = wire_of(zext(lhs_w, width) << bit_idx)[0:width] + acc = acc + wire_of(rhs_w[bit_idx : bit_idx + 1]).select(row, zero) + return wire_of(acc)[0:width] + + +def _mul_signed_twos_complement(lhs, rhs): + lhs_w = wire_of(lhs) + rhs_w = wire_of(rhs) + lhs_bits = lhs_w.width + rhs_bits = rhs_w.width + product_w = lhs_bits + rhs_bits + zero = zext(lhs_w[0:1], product_w) & 0 + + unsigned_product = _mul_unsigned_rows(lhs_w, rhs_w, width=product_w) + lhs_correction = wire_of(rhs_w[rhs_bits - 1 : rhs_bits]).select( + wire_of(zext(lhs_w, product_w) << rhs_bits)[0:product_w], + zero, + ) + rhs_correction = wire_of(lhs_w[lhs_bits - 1 : lhs_bits]).select( + wire_of(zext(rhs_w, product_w) << lhs_bits)[0:product_w], + zero, + ) + return wire_of(unsigned_product - lhs_correction - rhs_correction)[0:product_w].as_signed() def _pack_lsb_bits(bits: Sequence[object]): @@ -69,6 +107,37 @@ def cmpe42(in0, in1, in2, in3, cix, *, width: int = REDUCE_W): return _pack_lsb_bits(sum_bits), _shift_carry_bits(carry_bits, width=width), cox_bits[-1] +def brent_kung_cpa_truncated(lhs, rhs, *, width: int): + lhs_w = wire_of(lhs)[0:width] + rhs_w = wire_of(rhs)[0:width] + p_init = [_bit(lhs_w, bit_idx) ^ _bit(rhs_w, bit_idx) for bit_idx in range(width)] + g = [_bit(lhs_w, bit_idx) & _bit(rhs_w, bit_idx) for bit_idx in range(width)] + p = list(p_init) + + step = 1 + while step < width: + for bit_idx in range((2 * step) - 1, width, 2 * step): + prev_idx = bit_idx - step + g[bit_idx] = g[bit_idx] | (p[bit_idx] & g[prev_idx]) + p[bit_idx] = p[bit_idx] & p[prev_idx] + step *= 2 + + step //= 4 + while step >= 1: + for bit_idx in range((3 * step) - 1, width, 2 * step): + prev_idx = bit_idx - step + g[bit_idx] = g[bit_idx] | (p[bit_idx] & g[prev_idx]) + p[bit_idx] = p[bit_idx] & p[prev_idx] + step //= 2 + + zero = _bit(lhs_w, 0) & 0 + sum_bits = [] + for bit_idx in range(width): + carry_in = zero if bit_idx == 0 else g[bit_idx - 1] + sum_bits.append(p_init[bit_idx] ^ carry_in) + return _pack_lsb_bits(sum_bits) + + def _wallace_dot8_reduce(products: Sequence[object], *, width: int = REDUCE_W): if len(products) != 8: raise ValueError("dot8_reduce expects exactly 8 products") @@ -79,8 +148,14 @@ def _wallace_dot8_reduce(products: Sequence[object], *, width: int = REDUCE_W): # row merge is intentionally left as the only CPA in this reduction. lo_sum, lo_carry, _ = cmpe42(terms[0], terms[1], terms[2], terms[3], zero_cix, width=width) hi_sum, hi_carry, _ = cmpe42(terms[4], terms[5], terms[6], terms[7], zero_cix, width=width) - final_sum, final_carry, _ = cmpe42(lo_sum, lo_carry, hi_sum, hi_carry, zero_cix, width=width) - return final_sum + final_carry + final_sum, final_carry, terminal_cox = cmpe42(lo_sum, lo_carry, hi_sum, hi_carry, zero_cix, width=width) + + # Intentional truncation policy: + # `terminal_cox` has weight 2^width, which is outside the fixed-width output + # contract of this dot8 reducer (`sum[width-1:0]`). We intentionally drop + # this out-of-range carry at the fixed-width final CPA boundary. + _ = terminal_cox + return brent_kung_cpa_truncated(final_sum, final_carry, width=width) def wallace_dot8_tree(m, domain, *, inputs: dict | None = None, width: int = REDUCE_W, prefix: str = "wallace_dot8"): @@ -144,13 +219,9 @@ def select_one_hot4(sel0, sel1, sel2, cand0, cand1, cand2, cand3): One-hot mode selection. Use muxes instead of boolean-masked multiplication so PyCircuit does not insert balancing registers in comb3. """ - return wire_of(sel0)._select_internal( - wire_of(cand0), - wire_of(sel1)._select_internal( - wire_of(cand1), - wire_of(sel2)._select_internal(wire_of(cand2), wire_of(cand3)), - ), - ) + lo_pair = wire_of(sel0)._select_internal(wire_of(cand0), wire_of(cand1)) + hi_pair = wire_of(sel2)._select_internal(wire_of(cand2), wire_of(cand3)) + return wire_of(sel0 | sel1)._select_internal(lo_pair, hi_pair) def sum_shift_pair(lo, hi, e1_a, e1_b, *, width: int = REDUCE_W): @@ -160,4 +231,4 @@ def sum_shift_pair(lo, hi, e1_a, e1_b, *, width: int = REDUCE_W): sh_hi = zext(e1_a_w[1:2], 2) + zext(e1_b_w[1:2], 2) lo_scaled = wire_of(shift_scale_x1_x2_x4(wire_of(lo)[0:width], sh_lo))[0:width] hi_scaled = wire_of(shift_scale_x1_x2_x4(wire_of(hi)[0:width], sh_hi))[0:width] - return lo_scaled + hi_scaled + return brent_kung_cpa_truncated(lo_scaled, hi_scaled, width=width) diff --git a/designs/PE_INT/python/pe_int/mac_modes.py b/designs/PE_INT/python/pe_int/mac_modes.py index d8cd221..7314613 100644 --- a/designs/PE_INT/python/pe_int/mac_modes.py +++ b/designs/PE_INT/python/pe_int/mac_modes.py @@ -3,7 +3,7 @@ from pycircuit import wire_of from .constants import OUT0_W, OUT1_W -from .decode import decode_s4_from_40, decode_s4_hi_from_80, decode_s5, decode_s5_hi_from_80, decode_s8_from_lane_word +from .decode import decode_s4_from_40, decode_s4_hi_from_80, decode_s5, decode_s5_hi_from_80, decode_s8_from_lane_word, sext from .lane_mac import booth_mul_signed, select_one_hot4, sum_shift_pair, wallace_dot8_tree_w16, wallace_dot8_tree_w19 @@ -32,26 +32,25 @@ def comb1_generate_products(a, b, b1): p2c1 = [] for lane_idx in range(8): - a8_o0_i = decode_s8_from_lane_word(a, lane_idx, bits=OUT0_W) - a8_o1_i = decode_s8_from_lane_word(a, lane_idx, bits=OUT1_W) - b8_i = decode_s8_from_lane_word(b, lane_idx, bits=OUT0_W) - b4_0_i = decode_s4_from_40(b_lo40, lane_idx, bits=OUT0_W) - b4_1_i = decode_s4_hi_from_80(b, lane_idx, bits=OUT1_W) - b5_0_i = decode_s5(b_lo40, lane_idx, bits=OUT0_W) - b5_1_i = decode_s5_hi_from_80(b, lane_idx, bits=OUT1_W) - p2a.append(booth_mul_signed(a8_o0_i, b8_i)) - p2b0.append(booth_mul_signed(a8_o0_i, b4_0_i)) - p2b1.append(booth_mul_signed(a8_o1_i, b4_1_i)) - p2d0.append(booth_mul_signed(a8_o0_i, b5_0_i)) - p2d1.append(booth_mul_signed(a8_o1_i, b5_1_i)) + a8_i = decode_s8_from_lane_word(a, lane_idx, bits=8) + b8_i = decode_s8_from_lane_word(b, lane_idx, bits=8) + b4_0_i = decode_s4_from_40(b_lo40, lane_idx, bits=4) + b4_1_i = decode_s4_hi_from_80(b, lane_idx, bits=4) + b5_0_i = decode_s5(b_lo40, lane_idx, bits=5) + b5_1_i = decode_s5_hi_from_80(b, lane_idx, bits=5) + p2a.append(booth_mul_signed(a8_i, b8_i)) + p2b0.append(booth_mul_signed(a8_i, b4_0_i)) + p2b1.append(booth_mul_signed(a8_i, b4_1_i)) + p2d0.append(booth_mul_signed(a8_i, b5_0_i)) + p2d1.append(booth_mul_signed(a8_i, b5_1_i)) for lane_idx in range(16): - a5_o0_i = decode_s5(a, lane_idx, bits=OUT0_W) - a5_o1_i = decode_s5(a, lane_idx, bits=OUT1_W) - b0_5_i = decode_s5(b, lane_idx, bits=OUT0_W) - b1_5_i = decode_s5(b1, lane_idx, bits=OUT1_W) - p2c0.append(booth_mul_signed(a5_o0_i, b0_5_i)) - p2c1.append(booth_mul_signed(a5_o1_i, b1_5_i)) + # Keep mode-2c multipliers at natural operand width (S5*S5 -> 10). + a5_i = decode_s5(a, lane_idx, bits=5) + b0_5_i = decode_s5(b, lane_idx, bits=5) + b1_5_i = decode_s5(b1, lane_idx, bits=5) + p2c0.append(booth_mul_signed(a5_i, b0_5_i)) + p2c1.append(booth_mul_signed(a5_i, b1_5_i)) return { "p2a": p2a, @@ -68,7 +67,7 @@ def _wallace_dot8(domain, products, *, width: int, prefix: str): module = wallace_dot8_tree_w19 if width == OUT0_W else wallace_dot8_tree_w16 return domain.call( module, - inputs={f"in{idx}": wire_of(product)[0:width] for idx, product in enumerate(products)}, + inputs={f"in{idx}": sext(product, width) for idx, product in enumerate(products)}, prefix=prefix, )["sum"] diff --git a/designs/PE_INT/rtl/build/pe_int.v b/designs/PE_INT/rtl/build/pe_int.v index f60f84d..2180e46 100644 --- a/designs/PE_INT/rtl/build/pe_int.v +++ b/designs/PE_INT/rtl/build/pe_int.v @@ -59,150 +59,150 @@ wire pe_int_s1_is_2b; // pyc.name="pe_int_s1_is_2b" wire pe_int_s1_is_2b__next; // pyc.name="pe_int_s1_is_2b__next" wire pe_int_s1_is_2c; // pyc.name="pe_int_s1_is_2c" wire pe_int_s1_is_2c__next; // pyc.name="pe_int_s1_is_2c__next" -wire [18:0] pe_int_s1_p2a_0; // pyc.name="pe_int_s1_p2a_0" -wire [18:0] pe_int_s1_p2a_0__next; // pyc.name="pe_int_s1_p2a_0__next" -wire [18:0] pe_int_s1_p2a_1; // pyc.name="pe_int_s1_p2a_1" -wire [18:0] pe_int_s1_p2a_1__next; // pyc.name="pe_int_s1_p2a_1__next" -wire [18:0] pe_int_s1_p2a_2; // pyc.name="pe_int_s1_p2a_2" -wire [18:0] pe_int_s1_p2a_2__next; // pyc.name="pe_int_s1_p2a_2__next" -wire [18:0] pe_int_s1_p2a_3; // pyc.name="pe_int_s1_p2a_3" -wire [18:0] pe_int_s1_p2a_3__next; // pyc.name="pe_int_s1_p2a_3__next" -wire [18:0] pe_int_s1_p2a_4; // pyc.name="pe_int_s1_p2a_4" -wire [18:0] pe_int_s1_p2a_4__next; // pyc.name="pe_int_s1_p2a_4__next" -wire [18:0] pe_int_s1_p2a_5; // pyc.name="pe_int_s1_p2a_5" -wire [18:0] pe_int_s1_p2a_5__next; // pyc.name="pe_int_s1_p2a_5__next" -wire [18:0] pe_int_s1_p2a_6; // pyc.name="pe_int_s1_p2a_6" -wire [18:0] pe_int_s1_p2a_6__next; // pyc.name="pe_int_s1_p2a_6__next" -wire [18:0] pe_int_s1_p2a_7; // pyc.name="pe_int_s1_p2a_7" -wire [18:0] pe_int_s1_p2a_7__next; // pyc.name="pe_int_s1_p2a_7__next" -wire [18:0] pe_int_s1_p2b0_0; // pyc.name="pe_int_s1_p2b0_0" -wire [18:0] pe_int_s1_p2b0_0__next; // pyc.name="pe_int_s1_p2b0_0__next" -wire [18:0] pe_int_s1_p2b0_1; // pyc.name="pe_int_s1_p2b0_1" -wire [18:0] pe_int_s1_p2b0_1__next; // pyc.name="pe_int_s1_p2b0_1__next" -wire [18:0] pe_int_s1_p2b0_2; // pyc.name="pe_int_s1_p2b0_2" -wire [18:0] pe_int_s1_p2b0_2__next; // pyc.name="pe_int_s1_p2b0_2__next" -wire [18:0] pe_int_s1_p2b0_3; // pyc.name="pe_int_s1_p2b0_3" -wire [18:0] pe_int_s1_p2b0_3__next; // pyc.name="pe_int_s1_p2b0_3__next" -wire [18:0] pe_int_s1_p2b0_4; // pyc.name="pe_int_s1_p2b0_4" -wire [18:0] pe_int_s1_p2b0_4__next; // pyc.name="pe_int_s1_p2b0_4__next" -wire [18:0] pe_int_s1_p2b0_5; // pyc.name="pe_int_s1_p2b0_5" -wire [18:0] pe_int_s1_p2b0_5__next; // pyc.name="pe_int_s1_p2b0_5__next" -wire [18:0] pe_int_s1_p2b0_6; // pyc.name="pe_int_s1_p2b0_6" -wire [18:0] pe_int_s1_p2b0_6__next; // pyc.name="pe_int_s1_p2b0_6__next" -wire [18:0] pe_int_s1_p2b0_7; // pyc.name="pe_int_s1_p2b0_7" -wire [18:0] pe_int_s1_p2b0_7__next; // pyc.name="pe_int_s1_p2b0_7__next" -wire [15:0] pe_int_s1_p2b1_0; // pyc.name="pe_int_s1_p2b1_0" -wire [15:0] pe_int_s1_p2b1_0__next; // pyc.name="pe_int_s1_p2b1_0__next" -wire [15:0] pe_int_s1_p2b1_1; // pyc.name="pe_int_s1_p2b1_1" -wire [15:0] pe_int_s1_p2b1_1__next; // pyc.name="pe_int_s1_p2b1_1__next" -wire [15:0] pe_int_s1_p2b1_2; // pyc.name="pe_int_s1_p2b1_2" -wire [15:0] pe_int_s1_p2b1_2__next; // pyc.name="pe_int_s1_p2b1_2__next" -wire [15:0] pe_int_s1_p2b1_3; // pyc.name="pe_int_s1_p2b1_3" -wire [15:0] pe_int_s1_p2b1_3__next; // pyc.name="pe_int_s1_p2b1_3__next" -wire [15:0] pe_int_s1_p2b1_4; // pyc.name="pe_int_s1_p2b1_4" -wire [15:0] pe_int_s1_p2b1_4__next; // pyc.name="pe_int_s1_p2b1_4__next" -wire [15:0] pe_int_s1_p2b1_5; // pyc.name="pe_int_s1_p2b1_5" -wire [15:0] pe_int_s1_p2b1_5__next; // pyc.name="pe_int_s1_p2b1_5__next" -wire [15:0] pe_int_s1_p2b1_6; // pyc.name="pe_int_s1_p2b1_6" -wire [15:0] pe_int_s1_p2b1_6__next; // pyc.name="pe_int_s1_p2b1_6__next" -wire [15:0] pe_int_s1_p2b1_7; // pyc.name="pe_int_s1_p2b1_7" -wire [15:0] pe_int_s1_p2b1_7__next; // pyc.name="pe_int_s1_p2b1_7__next" -wire [18:0] pe_int_s1_p2c0_0; // pyc.name="pe_int_s1_p2c0_0" -wire [18:0] pe_int_s1_p2c0_0__next; // pyc.name="pe_int_s1_p2c0_0__next" -wire [18:0] pe_int_s1_p2c0_1; // pyc.name="pe_int_s1_p2c0_1" -wire [18:0] pe_int_s1_p2c0_10; // pyc.name="pe_int_s1_p2c0_10" -wire [18:0] pe_int_s1_p2c0_10__next; // pyc.name="pe_int_s1_p2c0_10__next" -wire [18:0] pe_int_s1_p2c0_11; // pyc.name="pe_int_s1_p2c0_11" -wire [18:0] pe_int_s1_p2c0_11__next; // pyc.name="pe_int_s1_p2c0_11__next" -wire [18:0] pe_int_s1_p2c0_12; // pyc.name="pe_int_s1_p2c0_12" -wire [18:0] pe_int_s1_p2c0_12__next; // pyc.name="pe_int_s1_p2c0_12__next" -wire [18:0] pe_int_s1_p2c0_13; // pyc.name="pe_int_s1_p2c0_13" -wire [18:0] pe_int_s1_p2c0_13__next; // pyc.name="pe_int_s1_p2c0_13__next" -wire [18:0] pe_int_s1_p2c0_14; // pyc.name="pe_int_s1_p2c0_14" -wire [18:0] pe_int_s1_p2c0_14__next; // pyc.name="pe_int_s1_p2c0_14__next" -wire [18:0] pe_int_s1_p2c0_15; // pyc.name="pe_int_s1_p2c0_15" -wire [18:0] pe_int_s1_p2c0_15__next; // pyc.name="pe_int_s1_p2c0_15__next" -wire [18:0] pe_int_s1_p2c0_1__next; // pyc.name="pe_int_s1_p2c0_1__next" -wire [18:0] pe_int_s1_p2c0_2; // pyc.name="pe_int_s1_p2c0_2" -wire [18:0] pe_int_s1_p2c0_2__next; // pyc.name="pe_int_s1_p2c0_2__next" -wire [18:0] pe_int_s1_p2c0_3; // pyc.name="pe_int_s1_p2c0_3" -wire [18:0] pe_int_s1_p2c0_3__next; // pyc.name="pe_int_s1_p2c0_3__next" -wire [18:0] pe_int_s1_p2c0_4; // pyc.name="pe_int_s1_p2c0_4" -wire [18:0] pe_int_s1_p2c0_4__next; // pyc.name="pe_int_s1_p2c0_4__next" -wire [18:0] pe_int_s1_p2c0_5; // pyc.name="pe_int_s1_p2c0_5" -wire [18:0] pe_int_s1_p2c0_5__next; // pyc.name="pe_int_s1_p2c0_5__next" -wire [18:0] pe_int_s1_p2c0_6; // pyc.name="pe_int_s1_p2c0_6" -wire [18:0] pe_int_s1_p2c0_6__next; // pyc.name="pe_int_s1_p2c0_6__next" -wire [18:0] pe_int_s1_p2c0_7; // pyc.name="pe_int_s1_p2c0_7" -wire [18:0] pe_int_s1_p2c0_7__next; // pyc.name="pe_int_s1_p2c0_7__next" -wire [18:0] pe_int_s1_p2c0_8; // pyc.name="pe_int_s1_p2c0_8" -wire [18:0] pe_int_s1_p2c0_8__next; // pyc.name="pe_int_s1_p2c0_8__next" -wire [18:0] pe_int_s1_p2c0_9; // pyc.name="pe_int_s1_p2c0_9" -wire [18:0] pe_int_s1_p2c0_9__next; // pyc.name="pe_int_s1_p2c0_9__next" -wire [15:0] pe_int_s1_p2c1_0; // pyc.name="pe_int_s1_p2c1_0" -wire [15:0] pe_int_s1_p2c1_0__next; // pyc.name="pe_int_s1_p2c1_0__next" -wire [15:0] pe_int_s1_p2c1_1; // pyc.name="pe_int_s1_p2c1_1" -wire [15:0] pe_int_s1_p2c1_10; // pyc.name="pe_int_s1_p2c1_10" -wire [15:0] pe_int_s1_p2c1_10__next; // pyc.name="pe_int_s1_p2c1_10__next" -wire [15:0] pe_int_s1_p2c1_11; // pyc.name="pe_int_s1_p2c1_11" -wire [15:0] pe_int_s1_p2c1_11__next; // pyc.name="pe_int_s1_p2c1_11__next" -wire [15:0] pe_int_s1_p2c1_12; // pyc.name="pe_int_s1_p2c1_12" -wire [15:0] pe_int_s1_p2c1_12__next; // pyc.name="pe_int_s1_p2c1_12__next" -wire [15:0] pe_int_s1_p2c1_13; // pyc.name="pe_int_s1_p2c1_13" -wire [15:0] pe_int_s1_p2c1_13__next; // pyc.name="pe_int_s1_p2c1_13__next" -wire [15:0] pe_int_s1_p2c1_14; // pyc.name="pe_int_s1_p2c1_14" -wire [15:0] pe_int_s1_p2c1_14__next; // pyc.name="pe_int_s1_p2c1_14__next" -wire [15:0] pe_int_s1_p2c1_15; // pyc.name="pe_int_s1_p2c1_15" -wire [15:0] pe_int_s1_p2c1_15__next; // pyc.name="pe_int_s1_p2c1_15__next" -wire [15:0] pe_int_s1_p2c1_1__next; // pyc.name="pe_int_s1_p2c1_1__next" -wire [15:0] pe_int_s1_p2c1_2; // pyc.name="pe_int_s1_p2c1_2" -wire [15:0] pe_int_s1_p2c1_2__next; // pyc.name="pe_int_s1_p2c1_2__next" -wire [15:0] pe_int_s1_p2c1_3; // pyc.name="pe_int_s1_p2c1_3" -wire [15:0] pe_int_s1_p2c1_3__next; // pyc.name="pe_int_s1_p2c1_3__next" -wire [15:0] pe_int_s1_p2c1_4; // pyc.name="pe_int_s1_p2c1_4" -wire [15:0] pe_int_s1_p2c1_4__next; // pyc.name="pe_int_s1_p2c1_4__next" -wire [15:0] pe_int_s1_p2c1_5; // pyc.name="pe_int_s1_p2c1_5" -wire [15:0] pe_int_s1_p2c1_5__next; // pyc.name="pe_int_s1_p2c1_5__next" -wire [15:0] pe_int_s1_p2c1_6; // pyc.name="pe_int_s1_p2c1_6" -wire [15:0] pe_int_s1_p2c1_6__next; // pyc.name="pe_int_s1_p2c1_6__next" -wire [15:0] pe_int_s1_p2c1_7; // pyc.name="pe_int_s1_p2c1_7" -wire [15:0] pe_int_s1_p2c1_7__next; // pyc.name="pe_int_s1_p2c1_7__next" -wire [15:0] pe_int_s1_p2c1_8; // pyc.name="pe_int_s1_p2c1_8" -wire [15:0] pe_int_s1_p2c1_8__next; // pyc.name="pe_int_s1_p2c1_8__next" -wire [15:0] pe_int_s1_p2c1_9; // pyc.name="pe_int_s1_p2c1_9" -wire [15:0] pe_int_s1_p2c1_9__next; // pyc.name="pe_int_s1_p2c1_9__next" -wire [18:0] pe_int_s1_p2d0_0; // pyc.name="pe_int_s1_p2d0_0" -wire [18:0] pe_int_s1_p2d0_0__next; // pyc.name="pe_int_s1_p2d0_0__next" -wire [18:0] pe_int_s1_p2d0_1; // pyc.name="pe_int_s1_p2d0_1" -wire [18:0] pe_int_s1_p2d0_1__next; // pyc.name="pe_int_s1_p2d0_1__next" -wire [18:0] pe_int_s1_p2d0_2; // pyc.name="pe_int_s1_p2d0_2" -wire [18:0] pe_int_s1_p2d0_2__next; // pyc.name="pe_int_s1_p2d0_2__next" -wire [18:0] pe_int_s1_p2d0_3; // pyc.name="pe_int_s1_p2d0_3" -wire [18:0] pe_int_s1_p2d0_3__next; // pyc.name="pe_int_s1_p2d0_3__next" -wire [18:0] pe_int_s1_p2d0_4; // pyc.name="pe_int_s1_p2d0_4" -wire [18:0] pe_int_s1_p2d0_4__next; // pyc.name="pe_int_s1_p2d0_4__next" -wire [18:0] pe_int_s1_p2d0_5; // pyc.name="pe_int_s1_p2d0_5" -wire [18:0] pe_int_s1_p2d0_5__next; // pyc.name="pe_int_s1_p2d0_5__next" -wire [18:0] pe_int_s1_p2d0_6; // pyc.name="pe_int_s1_p2d0_6" -wire [18:0] pe_int_s1_p2d0_6__next; // pyc.name="pe_int_s1_p2d0_6__next" -wire [18:0] pe_int_s1_p2d0_7; // pyc.name="pe_int_s1_p2d0_7" -wire [18:0] pe_int_s1_p2d0_7__next; // pyc.name="pe_int_s1_p2d0_7__next" -wire [15:0] pe_int_s1_p2d1_0; // pyc.name="pe_int_s1_p2d1_0" -wire [15:0] pe_int_s1_p2d1_0__next; // pyc.name="pe_int_s1_p2d1_0__next" -wire [15:0] pe_int_s1_p2d1_1; // pyc.name="pe_int_s1_p2d1_1" -wire [15:0] pe_int_s1_p2d1_1__next; // pyc.name="pe_int_s1_p2d1_1__next" -wire [15:0] pe_int_s1_p2d1_2; // pyc.name="pe_int_s1_p2d1_2" -wire [15:0] pe_int_s1_p2d1_2__next; // pyc.name="pe_int_s1_p2d1_2__next" -wire [15:0] pe_int_s1_p2d1_3; // pyc.name="pe_int_s1_p2d1_3" -wire [15:0] pe_int_s1_p2d1_3__next; // pyc.name="pe_int_s1_p2d1_3__next" -wire [15:0] pe_int_s1_p2d1_4; // pyc.name="pe_int_s1_p2d1_4" -wire [15:0] pe_int_s1_p2d1_4__next; // pyc.name="pe_int_s1_p2d1_4__next" -wire [15:0] pe_int_s1_p2d1_5; // pyc.name="pe_int_s1_p2d1_5" -wire [15:0] pe_int_s1_p2d1_5__next; // pyc.name="pe_int_s1_p2d1_5__next" -wire [15:0] pe_int_s1_p2d1_6; // pyc.name="pe_int_s1_p2d1_6" -wire [15:0] pe_int_s1_p2d1_6__next; // pyc.name="pe_int_s1_p2d1_6__next" -wire [15:0] pe_int_s1_p2d1_7; // pyc.name="pe_int_s1_p2d1_7" -wire [15:0] pe_int_s1_p2d1_7__next; // pyc.name="pe_int_s1_p2d1_7__next" +wire [15:0] pe_int_s1_p2a_0; // pyc.name="pe_int_s1_p2a_0" +wire [15:0] pe_int_s1_p2a_0__next; // pyc.name="pe_int_s1_p2a_0__next" +wire [15:0] pe_int_s1_p2a_1; // pyc.name="pe_int_s1_p2a_1" +wire [15:0] pe_int_s1_p2a_1__next; // pyc.name="pe_int_s1_p2a_1__next" +wire [15:0] pe_int_s1_p2a_2; // pyc.name="pe_int_s1_p2a_2" +wire [15:0] pe_int_s1_p2a_2__next; // pyc.name="pe_int_s1_p2a_2__next" +wire [15:0] pe_int_s1_p2a_3; // pyc.name="pe_int_s1_p2a_3" +wire [15:0] pe_int_s1_p2a_3__next; // pyc.name="pe_int_s1_p2a_3__next" +wire [15:0] pe_int_s1_p2a_4; // pyc.name="pe_int_s1_p2a_4" +wire [15:0] pe_int_s1_p2a_4__next; // pyc.name="pe_int_s1_p2a_4__next" +wire [15:0] pe_int_s1_p2a_5; // pyc.name="pe_int_s1_p2a_5" +wire [15:0] pe_int_s1_p2a_5__next; // pyc.name="pe_int_s1_p2a_5__next" +wire [15:0] pe_int_s1_p2a_6; // pyc.name="pe_int_s1_p2a_6" +wire [15:0] pe_int_s1_p2a_6__next; // pyc.name="pe_int_s1_p2a_6__next" +wire [15:0] pe_int_s1_p2a_7; // pyc.name="pe_int_s1_p2a_7" +wire [15:0] pe_int_s1_p2a_7__next; // pyc.name="pe_int_s1_p2a_7__next" +wire [11:0] pe_int_s1_p2b0_0; // pyc.name="pe_int_s1_p2b0_0" +wire [11:0] pe_int_s1_p2b0_0__next; // pyc.name="pe_int_s1_p2b0_0__next" +wire [11:0] pe_int_s1_p2b0_1; // pyc.name="pe_int_s1_p2b0_1" +wire [11:0] pe_int_s1_p2b0_1__next; // pyc.name="pe_int_s1_p2b0_1__next" +wire [11:0] pe_int_s1_p2b0_2; // pyc.name="pe_int_s1_p2b0_2" +wire [11:0] pe_int_s1_p2b0_2__next; // pyc.name="pe_int_s1_p2b0_2__next" +wire [11:0] pe_int_s1_p2b0_3; // pyc.name="pe_int_s1_p2b0_3" +wire [11:0] pe_int_s1_p2b0_3__next; // pyc.name="pe_int_s1_p2b0_3__next" +wire [11:0] pe_int_s1_p2b0_4; // pyc.name="pe_int_s1_p2b0_4" +wire [11:0] pe_int_s1_p2b0_4__next; // pyc.name="pe_int_s1_p2b0_4__next" +wire [11:0] pe_int_s1_p2b0_5; // pyc.name="pe_int_s1_p2b0_5" +wire [11:0] pe_int_s1_p2b0_5__next; // pyc.name="pe_int_s1_p2b0_5__next" +wire [11:0] pe_int_s1_p2b0_6; // pyc.name="pe_int_s1_p2b0_6" +wire [11:0] pe_int_s1_p2b0_6__next; // pyc.name="pe_int_s1_p2b0_6__next" +wire [11:0] pe_int_s1_p2b0_7; // pyc.name="pe_int_s1_p2b0_7" +wire [11:0] pe_int_s1_p2b0_7__next; // pyc.name="pe_int_s1_p2b0_7__next" +wire [11:0] pe_int_s1_p2b1_0; // pyc.name="pe_int_s1_p2b1_0" +wire [11:0] pe_int_s1_p2b1_0__next; // pyc.name="pe_int_s1_p2b1_0__next" +wire [11:0] pe_int_s1_p2b1_1; // pyc.name="pe_int_s1_p2b1_1" +wire [11:0] pe_int_s1_p2b1_1__next; // pyc.name="pe_int_s1_p2b1_1__next" +wire [11:0] pe_int_s1_p2b1_2; // pyc.name="pe_int_s1_p2b1_2" +wire [11:0] pe_int_s1_p2b1_2__next; // pyc.name="pe_int_s1_p2b1_2__next" +wire [11:0] pe_int_s1_p2b1_3; // pyc.name="pe_int_s1_p2b1_3" +wire [11:0] pe_int_s1_p2b1_3__next; // pyc.name="pe_int_s1_p2b1_3__next" +wire [11:0] pe_int_s1_p2b1_4; // pyc.name="pe_int_s1_p2b1_4" +wire [11:0] pe_int_s1_p2b1_4__next; // pyc.name="pe_int_s1_p2b1_4__next" +wire [11:0] pe_int_s1_p2b1_5; // pyc.name="pe_int_s1_p2b1_5" +wire [11:0] pe_int_s1_p2b1_5__next; // pyc.name="pe_int_s1_p2b1_5__next" +wire [11:0] pe_int_s1_p2b1_6; // pyc.name="pe_int_s1_p2b1_6" +wire [11:0] pe_int_s1_p2b1_6__next; // pyc.name="pe_int_s1_p2b1_6__next" +wire [11:0] pe_int_s1_p2b1_7; // pyc.name="pe_int_s1_p2b1_7" +wire [11:0] pe_int_s1_p2b1_7__next; // pyc.name="pe_int_s1_p2b1_7__next" +wire [9:0] pe_int_s1_p2c0_0; // pyc.name="pe_int_s1_p2c0_0" +wire [9:0] pe_int_s1_p2c0_0__next; // pyc.name="pe_int_s1_p2c0_0__next" +wire [9:0] pe_int_s1_p2c0_1; // pyc.name="pe_int_s1_p2c0_1" +wire [9:0] pe_int_s1_p2c0_10; // pyc.name="pe_int_s1_p2c0_10" +wire [9:0] pe_int_s1_p2c0_10__next; // pyc.name="pe_int_s1_p2c0_10__next" +wire [9:0] pe_int_s1_p2c0_11; // pyc.name="pe_int_s1_p2c0_11" +wire [9:0] pe_int_s1_p2c0_11__next; // pyc.name="pe_int_s1_p2c0_11__next" +wire [9:0] pe_int_s1_p2c0_12; // pyc.name="pe_int_s1_p2c0_12" +wire [9:0] pe_int_s1_p2c0_12__next; // pyc.name="pe_int_s1_p2c0_12__next" +wire [9:0] pe_int_s1_p2c0_13; // pyc.name="pe_int_s1_p2c0_13" +wire [9:0] pe_int_s1_p2c0_13__next; // pyc.name="pe_int_s1_p2c0_13__next" +wire [9:0] pe_int_s1_p2c0_14; // pyc.name="pe_int_s1_p2c0_14" +wire [9:0] pe_int_s1_p2c0_14__next; // pyc.name="pe_int_s1_p2c0_14__next" +wire [9:0] pe_int_s1_p2c0_15; // pyc.name="pe_int_s1_p2c0_15" +wire [9:0] pe_int_s1_p2c0_15__next; // pyc.name="pe_int_s1_p2c0_15__next" +wire [9:0] pe_int_s1_p2c0_1__next; // pyc.name="pe_int_s1_p2c0_1__next" +wire [9:0] pe_int_s1_p2c0_2; // pyc.name="pe_int_s1_p2c0_2" +wire [9:0] pe_int_s1_p2c0_2__next; // pyc.name="pe_int_s1_p2c0_2__next" +wire [9:0] pe_int_s1_p2c0_3; // pyc.name="pe_int_s1_p2c0_3" +wire [9:0] pe_int_s1_p2c0_3__next; // pyc.name="pe_int_s1_p2c0_3__next" +wire [9:0] pe_int_s1_p2c0_4; // pyc.name="pe_int_s1_p2c0_4" +wire [9:0] pe_int_s1_p2c0_4__next; // pyc.name="pe_int_s1_p2c0_4__next" +wire [9:0] pe_int_s1_p2c0_5; // pyc.name="pe_int_s1_p2c0_5" +wire [9:0] pe_int_s1_p2c0_5__next; // pyc.name="pe_int_s1_p2c0_5__next" +wire [9:0] pe_int_s1_p2c0_6; // pyc.name="pe_int_s1_p2c0_6" +wire [9:0] pe_int_s1_p2c0_6__next; // pyc.name="pe_int_s1_p2c0_6__next" +wire [9:0] pe_int_s1_p2c0_7; // pyc.name="pe_int_s1_p2c0_7" +wire [9:0] pe_int_s1_p2c0_7__next; // pyc.name="pe_int_s1_p2c0_7__next" +wire [9:0] pe_int_s1_p2c0_8; // pyc.name="pe_int_s1_p2c0_8" +wire [9:0] pe_int_s1_p2c0_8__next; // pyc.name="pe_int_s1_p2c0_8__next" +wire [9:0] pe_int_s1_p2c0_9; // pyc.name="pe_int_s1_p2c0_9" +wire [9:0] pe_int_s1_p2c0_9__next; // pyc.name="pe_int_s1_p2c0_9__next" +wire [9:0] pe_int_s1_p2c1_0; // pyc.name="pe_int_s1_p2c1_0" +wire [9:0] pe_int_s1_p2c1_0__next; // pyc.name="pe_int_s1_p2c1_0__next" +wire [9:0] pe_int_s1_p2c1_1; // pyc.name="pe_int_s1_p2c1_1" +wire [9:0] pe_int_s1_p2c1_10; // pyc.name="pe_int_s1_p2c1_10" +wire [9:0] pe_int_s1_p2c1_10__next; // pyc.name="pe_int_s1_p2c1_10__next" +wire [9:0] pe_int_s1_p2c1_11; // pyc.name="pe_int_s1_p2c1_11" +wire [9:0] pe_int_s1_p2c1_11__next; // pyc.name="pe_int_s1_p2c1_11__next" +wire [9:0] pe_int_s1_p2c1_12; // pyc.name="pe_int_s1_p2c1_12" +wire [9:0] pe_int_s1_p2c1_12__next; // pyc.name="pe_int_s1_p2c1_12__next" +wire [9:0] pe_int_s1_p2c1_13; // pyc.name="pe_int_s1_p2c1_13" +wire [9:0] pe_int_s1_p2c1_13__next; // pyc.name="pe_int_s1_p2c1_13__next" +wire [9:0] pe_int_s1_p2c1_14; // pyc.name="pe_int_s1_p2c1_14" +wire [9:0] pe_int_s1_p2c1_14__next; // pyc.name="pe_int_s1_p2c1_14__next" +wire [9:0] pe_int_s1_p2c1_15; // pyc.name="pe_int_s1_p2c1_15" +wire [9:0] pe_int_s1_p2c1_15__next; // pyc.name="pe_int_s1_p2c1_15__next" +wire [9:0] pe_int_s1_p2c1_1__next; // pyc.name="pe_int_s1_p2c1_1__next" +wire [9:0] pe_int_s1_p2c1_2; // pyc.name="pe_int_s1_p2c1_2" +wire [9:0] pe_int_s1_p2c1_2__next; // pyc.name="pe_int_s1_p2c1_2__next" +wire [9:0] pe_int_s1_p2c1_3; // pyc.name="pe_int_s1_p2c1_3" +wire [9:0] pe_int_s1_p2c1_3__next; // pyc.name="pe_int_s1_p2c1_3__next" +wire [9:0] pe_int_s1_p2c1_4; // pyc.name="pe_int_s1_p2c1_4" +wire [9:0] pe_int_s1_p2c1_4__next; // pyc.name="pe_int_s1_p2c1_4__next" +wire [9:0] pe_int_s1_p2c1_5; // pyc.name="pe_int_s1_p2c1_5" +wire [9:0] pe_int_s1_p2c1_5__next; // pyc.name="pe_int_s1_p2c1_5__next" +wire [9:0] pe_int_s1_p2c1_6; // pyc.name="pe_int_s1_p2c1_6" +wire [9:0] pe_int_s1_p2c1_6__next; // pyc.name="pe_int_s1_p2c1_6__next" +wire [9:0] pe_int_s1_p2c1_7; // pyc.name="pe_int_s1_p2c1_7" +wire [9:0] pe_int_s1_p2c1_7__next; // pyc.name="pe_int_s1_p2c1_7__next" +wire [9:0] pe_int_s1_p2c1_8; // pyc.name="pe_int_s1_p2c1_8" +wire [9:0] pe_int_s1_p2c1_8__next; // pyc.name="pe_int_s1_p2c1_8__next" +wire [9:0] pe_int_s1_p2c1_9; // pyc.name="pe_int_s1_p2c1_9" +wire [9:0] pe_int_s1_p2c1_9__next; // pyc.name="pe_int_s1_p2c1_9__next" +wire [12:0] pe_int_s1_p2d0_0; // pyc.name="pe_int_s1_p2d0_0" +wire [12:0] pe_int_s1_p2d0_0__next; // pyc.name="pe_int_s1_p2d0_0__next" +wire [12:0] pe_int_s1_p2d0_1; // pyc.name="pe_int_s1_p2d0_1" +wire [12:0] pe_int_s1_p2d0_1__next; // pyc.name="pe_int_s1_p2d0_1__next" +wire [12:0] pe_int_s1_p2d0_2; // pyc.name="pe_int_s1_p2d0_2" +wire [12:0] pe_int_s1_p2d0_2__next; // pyc.name="pe_int_s1_p2d0_2__next" +wire [12:0] pe_int_s1_p2d0_3; // pyc.name="pe_int_s1_p2d0_3" +wire [12:0] pe_int_s1_p2d0_3__next; // pyc.name="pe_int_s1_p2d0_3__next" +wire [12:0] pe_int_s1_p2d0_4; // pyc.name="pe_int_s1_p2d0_4" +wire [12:0] pe_int_s1_p2d0_4__next; // pyc.name="pe_int_s1_p2d0_4__next" +wire [12:0] pe_int_s1_p2d0_5; // pyc.name="pe_int_s1_p2d0_5" +wire [12:0] pe_int_s1_p2d0_5__next; // pyc.name="pe_int_s1_p2d0_5__next" +wire [12:0] pe_int_s1_p2d0_6; // pyc.name="pe_int_s1_p2d0_6" +wire [12:0] pe_int_s1_p2d0_6__next; // pyc.name="pe_int_s1_p2d0_6__next" +wire [12:0] pe_int_s1_p2d0_7; // pyc.name="pe_int_s1_p2d0_7" +wire [12:0] pe_int_s1_p2d0_7__next; // pyc.name="pe_int_s1_p2d0_7__next" +wire [12:0] pe_int_s1_p2d1_0; // pyc.name="pe_int_s1_p2d1_0" +wire [12:0] pe_int_s1_p2d1_0__next; // pyc.name="pe_int_s1_p2d1_0__next" +wire [12:0] pe_int_s1_p2d1_1; // pyc.name="pe_int_s1_p2d1_1" +wire [12:0] pe_int_s1_p2d1_1__next; // pyc.name="pe_int_s1_p2d1_1__next" +wire [12:0] pe_int_s1_p2d1_2; // pyc.name="pe_int_s1_p2d1_2" +wire [12:0] pe_int_s1_p2d1_2__next; // pyc.name="pe_int_s1_p2d1_2__next" +wire [12:0] pe_int_s1_p2d1_3; // pyc.name="pe_int_s1_p2d1_3" +wire [12:0] pe_int_s1_p2d1_3__next; // pyc.name="pe_int_s1_p2d1_3__next" +wire [12:0] pe_int_s1_p2d1_4; // pyc.name="pe_int_s1_p2d1_4" +wire [12:0] pe_int_s1_p2d1_4__next; // pyc.name="pe_int_s1_p2d1_4__next" +wire [12:0] pe_int_s1_p2d1_5; // pyc.name="pe_int_s1_p2d1_5" +wire [12:0] pe_int_s1_p2d1_5__next; // pyc.name="pe_int_s1_p2d1_5__next" +wire [12:0] pe_int_s1_p2d1_6; // pyc.name="pe_int_s1_p2d1_6" +wire [12:0] pe_int_s1_p2d1_6__next; // pyc.name="pe_int_s1_p2d1_6__next" +wire [12:0] pe_int_s1_p2d1_7; // pyc.name="pe_int_s1_p2d1_7" +wire [12:0] pe_int_s1_p2d1_7__next; // pyc.name="pe_int_s1_p2d1_7__next" wire pe_int_s1_vld; // pyc.name="pe_int_s1_vld" wire pe_int_s1_vld__next; // pyc.name="pe_int_s1_vld__next" wire [1:0] pe_int_s2_e1_a; // pyc.name="pe_int_s2_e1_a" @@ -237,712 +237,2672 @@ wire [15:0] pe_int_s2_s2d1; // pyc.name="pe_int_s2_s2d1" wire [15:0] pe_int_s2_s2d1__next; // pyc.name="pe_int_s2_s2d1__next" wire pe_int_s2_vld; // pyc.name="pe_int_s2_vld" wire pe_int_s2_vld__next; // pyc.name="pe_int_s2_vld__next" -wire [1:0] pyc_add_548; // op=pyc.add -wire [1:0] pyc_add_553; // op=pyc.add -wire [18:0] pyc_add_566; // op=pyc.add -wire [1:0] pyc_add_569; // op=pyc.add -wire [1:0] pyc_add_572; // op=pyc.add -wire [15:0] pyc_add_585; // op=pyc.add -wire [1:0] pyc_comb_12; // op=pyc.comb -wire [15:0] pyc_comb_13; // op=pyc.comb -wire [18:0] pyc_comb_14; // op=pyc.comb +wire [15:0] pyc_add_1022; // op=pyc.add +wire [15:0] pyc_add_1026; // op=pyc.add +wire [15:0] pyc_add_1030; // op=pyc.add +wire [15:0] pyc_add_1034; // op=pyc.add +wire [15:0] pyc_add_1038; // op=pyc.add +wire [15:0] pyc_add_1042; // op=pyc.add +wire [15:0] pyc_add_1046; // op=pyc.add +wire [11:0] pyc_add_1061; // op=pyc.add +wire [11:0] pyc_add_1065; // op=pyc.add +wire [11:0] pyc_add_1069; // op=pyc.add +wire [11:0] pyc_add_1081; // op=pyc.add +wire [11:0] pyc_add_1084; // op=pyc.add +wire [11:0] pyc_add_1087; // op=pyc.add +wire [12:0] pyc_add_1100; // op=pyc.add +wire [12:0] pyc_add_1104; // op=pyc.add +wire [12:0] pyc_add_1108; // op=pyc.add +wire [11:0] pyc_add_111; // op=pyc.add +wire [12:0] pyc_add_1112; // op=pyc.add +wire [12:0] pyc_add_1124; // op=pyc.add +wire [12:0] pyc_add_1127; // op=pyc.add +wire [12:0] pyc_add_1130; // op=pyc.add +wire [12:0] pyc_add_1133; // op=pyc.add +wire [9:0] pyc_add_1147; // op=pyc.add +wire [11:0] pyc_add_115; // op=pyc.add +wire [9:0] pyc_add_1151; // op=pyc.add +wire [9:0] pyc_add_1155; // op=pyc.add +wire [9:0] pyc_add_1159; // op=pyc.add +wire [9:0] pyc_add_1172; // op=pyc.add +wire [9:0] pyc_add_1175; // op=pyc.add +wire [9:0] pyc_add_1178; // op=pyc.add +wire [9:0] pyc_add_1181; // op=pyc.add +wire [11:0] pyc_add_119; // op=pyc.add +wire [9:0] pyc_add_1195; // op=pyc.add +wire [9:0] pyc_add_1199; // op=pyc.add +wire [9:0] pyc_add_1203; // op=pyc.add +wire [9:0] pyc_add_1207; // op=pyc.add +wire [9:0] pyc_add_1220; // op=pyc.add +wire [9:0] pyc_add_1223; // op=pyc.add +wire [9:0] pyc_add_1226; // op=pyc.add +wire [9:0] pyc_add_1229; // op=pyc.add +wire [9:0] pyc_add_1243; // op=pyc.add +wire [9:0] pyc_add_1247; // op=pyc.add +wire [9:0] pyc_add_1251; // op=pyc.add +wire [9:0] pyc_add_1255; // op=pyc.add +wire [9:0] pyc_add_1268; // op=pyc.add +wire [9:0] pyc_add_1271; // op=pyc.add +wire [9:0] pyc_add_1274; // op=pyc.add +wire [9:0] pyc_add_1277; // op=pyc.add +wire [9:0] pyc_add_1291; // op=pyc.add +wire [9:0] pyc_add_1295; // op=pyc.add +wire [9:0] pyc_add_1299; // op=pyc.add +wire [9:0] pyc_add_1303; // op=pyc.add +wire [11:0] pyc_add_131; // op=pyc.add +wire [9:0] pyc_add_1316; // op=pyc.add +wire [9:0] pyc_add_1319; // op=pyc.add +wire [9:0] pyc_add_1322; // op=pyc.add +wire [9:0] pyc_add_1325; // op=pyc.add +wire [9:0] pyc_add_1339; // op=pyc.add +wire [11:0] pyc_add_134; // op=pyc.add +wire [9:0] pyc_add_1343; // op=pyc.add +wire [9:0] pyc_add_1347; // op=pyc.add +wire [9:0] pyc_add_1351; // op=pyc.add +wire [9:0] pyc_add_1364; // op=pyc.add +wire [9:0] pyc_add_1367; // op=pyc.add +wire [11:0] pyc_add_137; // op=pyc.add +wire [9:0] pyc_add_1370; // op=pyc.add +wire [9:0] pyc_add_1373; // op=pyc.add +wire [9:0] pyc_add_1387; // op=pyc.add +wire [9:0] pyc_add_1391; // op=pyc.add +wire [9:0] pyc_add_1395; // op=pyc.add +wire [9:0] pyc_add_1399; // op=pyc.add +wire [9:0] pyc_add_1412; // op=pyc.add +wire [9:0] pyc_add_1415; // op=pyc.add +wire [9:0] pyc_add_1418; // op=pyc.add +wire [9:0] pyc_add_1421; // op=pyc.add +wire [9:0] pyc_add_1435; // op=pyc.add +wire [9:0] pyc_add_1439; // op=pyc.add +wire [9:0] pyc_add_1443; // op=pyc.add +wire [9:0] pyc_add_1447; // op=pyc.add +wire [9:0] pyc_add_1460; // op=pyc.add +wire [9:0] pyc_add_1463; // op=pyc.add +wire [9:0] pyc_add_1466; // op=pyc.add +wire [9:0] pyc_add_1469; // op=pyc.add +wire [9:0] pyc_add_1483; // op=pyc.add +wire [9:0] pyc_add_1487; // op=pyc.add +wire [9:0] pyc_add_1491; // op=pyc.add +wire [9:0] pyc_add_1495; // op=pyc.add +wire [12:0] pyc_add_150; // op=pyc.add +wire [9:0] pyc_add_1508; // op=pyc.add +wire [9:0] pyc_add_1511; // op=pyc.add +wire [9:0] pyc_add_1514; // op=pyc.add +wire [9:0] pyc_add_1517; // op=pyc.add +wire [9:0] pyc_add_1529; // op=pyc.add +wire [9:0] pyc_add_1532; // op=pyc.add +wire [9:0] pyc_add_1535; // op=pyc.add +wire [9:0] pyc_add_1538; // op=pyc.add +wire [12:0] pyc_add_154; // op=pyc.add +wire [9:0] pyc_add_1551; // op=pyc.add +wire [9:0] pyc_add_1554; // op=pyc.add +wire [9:0] pyc_add_1557; // op=pyc.add +wire [9:0] pyc_add_1560; // op=pyc.add +wire [9:0] pyc_add_1572; // op=pyc.add +wire [9:0] pyc_add_1575; // op=pyc.add +wire [9:0] pyc_add_1578; // op=pyc.add +wire [12:0] pyc_add_158; // op=pyc.add +wire [9:0] pyc_add_1581; // op=pyc.add +wire [9:0] pyc_add_1594; // op=pyc.add +wire [9:0] pyc_add_1597; // op=pyc.add +wire [9:0] pyc_add_1600; // op=pyc.add +wire [9:0] pyc_add_1603; // op=pyc.add +wire [9:0] pyc_add_1615; // op=pyc.add +wire [9:0] pyc_add_1618; // op=pyc.add +wire [12:0] pyc_add_162; // op=pyc.add +wire [9:0] pyc_add_1621; // op=pyc.add +wire [9:0] pyc_add_1624; // op=pyc.add +wire [9:0] pyc_add_1637; // op=pyc.add +wire [9:0] pyc_add_1640; // op=pyc.add +wire [9:0] pyc_add_1643; // op=pyc.add +wire [9:0] pyc_add_1646; // op=pyc.add +wire [9:0] pyc_add_1658; // op=pyc.add +wire [9:0] pyc_add_1661; // op=pyc.add +wire [9:0] pyc_add_1664; // op=pyc.add +wire [9:0] pyc_add_1667; // op=pyc.add +wire [9:0] pyc_add_1680; // op=pyc.add +wire [9:0] pyc_add_1683; // op=pyc.add +wire [9:0] pyc_add_1686; // op=pyc.add +wire [9:0] pyc_add_1689; // op=pyc.add +wire [9:0] pyc_add_1701; // op=pyc.add +wire [9:0] pyc_add_1704; // op=pyc.add +wire [9:0] pyc_add_1707; // op=pyc.add +wire [9:0] pyc_add_1710; // op=pyc.add +wire [9:0] pyc_add_1723; // op=pyc.add +wire [9:0] pyc_add_1726; // op=pyc.add +wire [9:0] pyc_add_1729; // op=pyc.add +wire [9:0] pyc_add_1732; // op=pyc.add +wire [12:0] pyc_add_174; // op=pyc.add +wire [9:0] pyc_add_1744; // op=pyc.add +wire [9:0] pyc_add_1747; // op=pyc.add +wire [9:0] pyc_add_1750; // op=pyc.add +wire [9:0] pyc_add_1753; // op=pyc.add +wire [9:0] pyc_add_1766; // op=pyc.add +wire [9:0] pyc_add_1769; // op=pyc.add +wire [12:0] pyc_add_177; // op=pyc.add +wire [9:0] pyc_add_1772; // op=pyc.add +wire [9:0] pyc_add_1775; // op=pyc.add +wire [9:0] pyc_add_1787; // op=pyc.add +wire [9:0] pyc_add_1790; // op=pyc.add +wire [9:0] pyc_add_1793; // op=pyc.add +wire [9:0] pyc_add_1796; // op=pyc.add +wire [12:0] pyc_add_180; // op=pyc.add +wire [9:0] pyc_add_1809; // op=pyc.add +wire [9:0] pyc_add_1812; // op=pyc.add +wire [9:0] pyc_add_1815; // op=pyc.add +wire [9:0] pyc_add_1818; // op=pyc.add +wire [12:0] pyc_add_183; // op=pyc.add +wire [9:0] pyc_add_1830; // op=pyc.add +wire [9:0] pyc_add_1833; // op=pyc.add +wire [9:0] pyc_add_1836; // op=pyc.add +wire [9:0] pyc_add_1839; // op=pyc.add +wire [9:0] pyc_add_1852; // op=pyc.add +wire [9:0] pyc_add_1855; // op=pyc.add +wire [9:0] pyc_add_1858; // op=pyc.add +wire [9:0] pyc_add_1861; // op=pyc.add +wire [15:0] pyc_add_210; // op=pyc.add +wire [15:0] pyc_add_214; // op=pyc.add +wire [15:0] pyc_add_218; // op=pyc.add +wire [1:0] pyc_add_2219; // op=pyc.add +wire [15:0] pyc_add_222; // op=pyc.add +wire [1:0] pyc_add_2224; // op=pyc.add +wire [15:0] pyc_add_226; // op=pyc.add +wire [15:0] pyc_add_230; // op=pyc.add +wire [15:0] pyc_add_234; // op=pyc.add +wire [1:0] pyc_add_2403; // op=pyc.add +wire [1:0] pyc_add_2406; // op=pyc.add +wire [11:0] pyc_add_249; // op=pyc.add +wire [11:0] pyc_add_253; // op=pyc.add +wire [11:0] pyc_add_257; // op=pyc.add +wire [11:0] pyc_add_269; // op=pyc.add +wire [11:0] pyc_add_272; // op=pyc.add +wire [11:0] pyc_add_275; // op=pyc.add +wire [12:0] pyc_add_288; // op=pyc.add +wire [12:0] pyc_add_292; // op=pyc.add +wire [12:0] pyc_add_296; // op=pyc.add +wire [12:0] pyc_add_300; // op=pyc.add +wire [12:0] pyc_add_312; // op=pyc.add +wire [12:0] pyc_add_315; // op=pyc.add +wire [12:0] pyc_add_318; // op=pyc.add +wire [12:0] pyc_add_321; // op=pyc.add +wire [15:0] pyc_add_348; // op=pyc.add +wire [15:0] pyc_add_352; // op=pyc.add +wire [15:0] pyc_add_356; // op=pyc.add +wire [15:0] pyc_add_360; // op=pyc.add +wire [15:0] pyc_add_364; // op=pyc.add +wire [15:0] pyc_add_368; // op=pyc.add +wire [15:0] pyc_add_372; // op=pyc.add +wire [11:0] pyc_add_387; // op=pyc.add +wire [11:0] pyc_add_391; // op=pyc.add +wire [11:0] pyc_add_395; // op=pyc.add +wire [11:0] pyc_add_407; // op=pyc.add +wire [11:0] pyc_add_410; // op=pyc.add +wire [11:0] pyc_add_413; // op=pyc.add +wire [12:0] pyc_add_426; // op=pyc.add +wire [12:0] pyc_add_430; // op=pyc.add +wire [12:0] pyc_add_434; // op=pyc.add +wire [12:0] pyc_add_438; // op=pyc.add +wire [12:0] pyc_add_450; // op=pyc.add +wire [12:0] pyc_add_453; // op=pyc.add +wire [12:0] pyc_add_456; // op=pyc.add +wire [12:0] pyc_add_459; // op=pyc.add +wire [15:0] pyc_add_486; // op=pyc.add +wire [15:0] pyc_add_490; // op=pyc.add +wire [15:0] pyc_add_494; // op=pyc.add +wire [15:0] pyc_add_498; // op=pyc.add +wire [15:0] pyc_add_502; // op=pyc.add +wire [15:0] pyc_add_506; // op=pyc.add +wire [15:0] pyc_add_510; // op=pyc.add +wire [11:0] pyc_add_525; // op=pyc.add +wire [11:0] pyc_add_529; // op=pyc.add +wire [11:0] pyc_add_533; // op=pyc.add +wire [11:0] pyc_add_545; // op=pyc.add +wire [11:0] pyc_add_548; // op=pyc.add +wire [11:0] pyc_add_551; // op=pyc.add +wire [12:0] pyc_add_564; // op=pyc.add +wire [12:0] pyc_add_568; // op=pyc.add +wire [12:0] pyc_add_572; // op=pyc.add +wire [12:0] pyc_add_576; // op=pyc.add +wire [12:0] pyc_add_588; // op=pyc.add +wire [12:0] pyc_add_591; // op=pyc.add +wire [12:0] pyc_add_594; // op=pyc.add +wire [12:0] pyc_add_597; // op=pyc.add +wire [15:0] pyc_add_620; // op=pyc.add +wire [15:0] pyc_add_624; // op=pyc.add +wire [15:0] pyc_add_628; // op=pyc.add +wire [15:0] pyc_add_632; // op=pyc.add +wire [15:0] pyc_add_636; // op=pyc.add +wire [15:0] pyc_add_640; // op=pyc.add +wire [15:0] pyc_add_644; // op=pyc.add +wire [11:0] pyc_add_659; // op=pyc.add +wire [11:0] pyc_add_663; // op=pyc.add +wire [11:0] pyc_add_667; // op=pyc.add +wire [11:0] pyc_add_679; // op=pyc.add +wire [11:0] pyc_add_682; // op=pyc.add +wire [11:0] pyc_add_685; // op=pyc.add +wire [12:0] pyc_add_698; // op=pyc.add +wire [12:0] pyc_add_702; // op=pyc.add +wire [12:0] pyc_add_706; // op=pyc.add +wire [12:0] pyc_add_710; // op=pyc.add +wire [15:0] pyc_add_72; // op=pyc.add +wire [12:0] pyc_add_722; // op=pyc.add +wire [12:0] pyc_add_725; // op=pyc.add +wire [12:0] pyc_add_728; // op=pyc.add +wire [12:0] pyc_add_731; // op=pyc.add +wire [15:0] pyc_add_754; // op=pyc.add +wire [15:0] pyc_add_758; // op=pyc.add +wire [15:0] pyc_add_76; // op=pyc.add +wire [15:0] pyc_add_762; // op=pyc.add +wire [15:0] pyc_add_766; // op=pyc.add +wire [15:0] pyc_add_770; // op=pyc.add +wire [15:0] pyc_add_774; // op=pyc.add +wire [15:0] pyc_add_778; // op=pyc.add +wire [11:0] pyc_add_793; // op=pyc.add +wire [11:0] pyc_add_797; // op=pyc.add +wire [15:0] pyc_add_80; // op=pyc.add +wire [11:0] pyc_add_801; // op=pyc.add +wire [11:0] pyc_add_813; // op=pyc.add +wire [11:0] pyc_add_816; // op=pyc.add +wire [11:0] pyc_add_819; // op=pyc.add +wire [12:0] pyc_add_832; // op=pyc.add +wire [12:0] pyc_add_836; // op=pyc.add +wire [15:0] pyc_add_84; // op=pyc.add +wire [12:0] pyc_add_840; // op=pyc.add +wire [12:0] pyc_add_844; // op=pyc.add +wire [12:0] pyc_add_856; // op=pyc.add +wire [12:0] pyc_add_859; // op=pyc.add +wire [12:0] pyc_add_862; // op=pyc.add +wire [12:0] pyc_add_865; // op=pyc.add +wire [15:0] pyc_add_88; // op=pyc.add +wire [15:0] pyc_add_888; // op=pyc.add +wire [15:0] pyc_add_892; // op=pyc.add +wire [15:0] pyc_add_896; // op=pyc.add +wire [15:0] pyc_add_900; // op=pyc.add +wire [15:0] pyc_add_904; // op=pyc.add +wire [15:0] pyc_add_908; // op=pyc.add +wire [15:0] pyc_add_912; // op=pyc.add +wire [15:0] pyc_add_92; // op=pyc.add +wire [11:0] pyc_add_927; // op=pyc.add +wire [11:0] pyc_add_931; // op=pyc.add +wire [11:0] pyc_add_935; // op=pyc.add +wire [11:0] pyc_add_947; // op=pyc.add +wire [11:0] pyc_add_950; // op=pyc.add +wire [11:0] pyc_add_953; // op=pyc.add +wire [15:0] pyc_add_96; // op=pyc.add +wire [12:0] pyc_add_966; // op=pyc.add +wire [12:0] pyc_add_970; // op=pyc.add +wire [12:0] pyc_add_974; // op=pyc.add +wire [12:0] pyc_add_978; // op=pyc.add +wire [12:0] pyc_add_990; // op=pyc.add +wire [12:0] pyc_add_993; // op=pyc.add +wire [12:0] pyc_add_996; // op=pyc.add +wire [12:0] pyc_add_999; // op=pyc.add +wire pyc_and_2294; // op=pyc.and +wire pyc_and_2295; // op=pyc.and +wire pyc_and_2296; // op=pyc.and +wire pyc_and_2297; // op=pyc.and +wire pyc_and_2298; // op=pyc.and +wire pyc_and_2299; // op=pyc.and +wire pyc_and_2300; // op=pyc.and +wire pyc_and_2301; // op=pyc.and +wire pyc_and_2302; // op=pyc.and +wire pyc_and_2303; // op=pyc.and +wire pyc_and_2304; // op=pyc.and +wire pyc_and_2305; // op=pyc.and +wire pyc_and_2306; // op=pyc.and +wire pyc_and_2307; // op=pyc.and +wire pyc_and_2308; // op=pyc.and +wire pyc_and_2309; // op=pyc.and +wire pyc_and_2310; // op=pyc.and +wire pyc_and_2311; // op=pyc.and +wire pyc_and_2312; // op=pyc.and +wire pyc_and_2314; // op=pyc.and +wire pyc_and_2316; // op=pyc.and +wire pyc_and_2317; // op=pyc.and +wire pyc_and_2319; // op=pyc.and +wire pyc_and_2320; // op=pyc.and +wire pyc_and_2322; // op=pyc.and +wire pyc_and_2323; // op=pyc.and +wire pyc_and_2325; // op=pyc.and +wire pyc_and_2326; // op=pyc.and +wire pyc_and_2328; // op=pyc.and +wire pyc_and_2329; // op=pyc.and +wire pyc_and_2331; // op=pyc.and +wire pyc_and_2332; // op=pyc.and +wire pyc_and_2334; // op=pyc.and +wire pyc_and_2335; // op=pyc.and +wire pyc_and_2337; // op=pyc.and +wire pyc_and_2338; // op=pyc.and +wire pyc_and_2340; // op=pyc.and +wire pyc_and_2342; // op=pyc.and +wire pyc_and_2343; // op=pyc.and +wire pyc_and_2345; // op=pyc.and +wire pyc_and_2346; // op=pyc.and +wire pyc_and_2348; // op=pyc.and +wire pyc_and_2349; // op=pyc.and +wire pyc_and_2351; // op=pyc.and +wire pyc_and_2353; // op=pyc.and +wire pyc_and_2354; // op=pyc.and +wire pyc_and_2356; // op=pyc.and +wire pyc_and_2358; // op=pyc.and +wire pyc_and_2360; // op=pyc.and +wire pyc_and_2362; // op=pyc.and +wire pyc_and_2364; // op=pyc.and +wire pyc_and_2366; // op=pyc.and +wire pyc_and_2368; // op=pyc.and +wire pyc_and_2370; // op=pyc.and +wire pyc_and_2372; // op=pyc.and +wire pyc_and_2374; // op=pyc.and +wire pyc_and_2376; // op=pyc.and +wire pyc_and_2378; // op=pyc.and +wire pyc_and_2380; // op=pyc.and +wire pyc_and_2467; // op=pyc.and +wire pyc_and_2468; // op=pyc.and +wire pyc_and_2469; // op=pyc.and +wire pyc_and_2470; // op=pyc.and +wire pyc_and_2471; // op=pyc.and +wire pyc_and_2472; // op=pyc.and +wire pyc_and_2473; // op=pyc.and +wire pyc_and_2474; // op=pyc.and +wire pyc_and_2475; // op=pyc.and +wire pyc_and_2476; // op=pyc.and +wire pyc_and_2477; // op=pyc.and +wire pyc_and_2478; // op=pyc.and +wire pyc_and_2479; // op=pyc.and +wire pyc_and_2480; // op=pyc.and +wire pyc_and_2481; // op=pyc.and +wire pyc_and_2482; // op=pyc.and +wire pyc_and_2484; // op=pyc.and +wire pyc_and_2486; // op=pyc.and +wire pyc_and_2487; // op=pyc.and +wire pyc_and_2489; // op=pyc.and +wire pyc_and_2490; // op=pyc.and +wire pyc_and_2492; // op=pyc.and +wire pyc_and_2493; // op=pyc.and +wire pyc_and_2495; // op=pyc.and +wire pyc_and_2496; // op=pyc.and +wire pyc_and_2498; // op=pyc.and +wire pyc_and_2499; // op=pyc.and +wire pyc_and_2501; // op=pyc.and +wire pyc_and_2502; // op=pyc.and +wire pyc_and_2504; // op=pyc.and +wire pyc_and_2506; // op=pyc.and +wire pyc_and_2507; // op=pyc.and +wire pyc_and_2509; // op=pyc.and +wire pyc_and_2510; // op=pyc.and +wire pyc_and_2512; // op=pyc.and +wire pyc_and_2514; // op=pyc.and +wire pyc_and_2516; // op=pyc.and +wire pyc_and_2518; // op=pyc.and +wire pyc_and_2520; // op=pyc.and +wire pyc_and_2522; // op=pyc.and +wire pyc_and_2524; // op=pyc.and +wire pyc_and_2526; // op=pyc.and +wire pyc_and_2528; // op=pyc.and +wire pyc_and_2530; // op=pyc.and +wire pyc_and_2532; // op=pyc.and wire [1:0] pyc_comb_15; // op=pyc.comb -wire [79:0] pyc_comb_16; // op=pyc.comb -wire pyc_comb_17; // op=pyc.comb -wire pyc_comb_18; // op=pyc.comb -wire [1:0] pyc_comb_19; // op=pyc.comb -wire [1:0] pyc_comb_20; // op=pyc.comb +wire [18:0] pyc_comb_16; // op=pyc.comb +wire [9:0] pyc_comb_17; // op=pyc.comb +wire [12:0] pyc_comb_18; // op=pyc.comb +wire [1:0] pyc_comb_1868; // op=pyc.comb +wire [15:0] pyc_comb_1869; // op=pyc.comb +wire [11:0] pyc_comb_1870; // op=pyc.comb +wire [11:0] pyc_comb_1871; // op=pyc.comb +wire [12:0] pyc_comb_1872; // op=pyc.comb +wire [12:0] pyc_comb_1873; // op=pyc.comb +wire [15:0] pyc_comb_1874; // op=pyc.comb +wire [11:0] pyc_comb_1875; // op=pyc.comb +wire [11:0] pyc_comb_1876; // op=pyc.comb +wire [12:0] pyc_comb_1877; // op=pyc.comb +wire [12:0] pyc_comb_1878; // op=pyc.comb +wire [15:0] pyc_comb_1879; // op=pyc.comb +wire [11:0] pyc_comb_1880; // op=pyc.comb +wire [11:0] pyc_comb_1881; // op=pyc.comb +wire [12:0] pyc_comb_1882; // op=pyc.comb +wire [12:0] pyc_comb_1883; // op=pyc.comb +wire [15:0] pyc_comb_1884; // op=pyc.comb +wire [11:0] pyc_comb_1885; // op=pyc.comb +wire [11:0] pyc_comb_1886; // op=pyc.comb +wire [12:0] pyc_comb_1887; // op=pyc.comb +wire [12:0] pyc_comb_1888; // op=pyc.comb +wire [15:0] pyc_comb_1889; // op=pyc.comb +wire [11:0] pyc_comb_1890; // op=pyc.comb +wire [11:0] pyc_comb_1891; // op=pyc.comb +wire [12:0] pyc_comb_1892; // op=pyc.comb +wire [12:0] pyc_comb_1893; // op=pyc.comb +wire [15:0] pyc_comb_1894; // op=pyc.comb +wire [11:0] pyc_comb_1895; // op=pyc.comb +wire [11:0] pyc_comb_1896; // op=pyc.comb +wire [12:0] pyc_comb_1897; // op=pyc.comb +wire [12:0] pyc_comb_1898; // op=pyc.comb +wire [15:0] pyc_comb_1899; // op=pyc.comb +wire [11:0] pyc_comb_19; // op=pyc.comb +wire [11:0] pyc_comb_1900; // op=pyc.comb +wire [11:0] pyc_comb_1901; // op=pyc.comb +wire [12:0] pyc_comb_1902; // op=pyc.comb +wire [12:0] pyc_comb_1903; // op=pyc.comb +wire [15:0] pyc_comb_1904; // op=pyc.comb +wire [11:0] pyc_comb_1905; // op=pyc.comb +wire [11:0] pyc_comb_1906; // op=pyc.comb +wire [12:0] pyc_comb_1907; // op=pyc.comb +wire [12:0] pyc_comb_1908; // op=pyc.comb +wire [9:0] pyc_comb_1909; // op=pyc.comb +wire [9:0] pyc_comb_1910; // op=pyc.comb +wire [9:0] pyc_comb_1911; // op=pyc.comb +wire [9:0] pyc_comb_1912; // op=pyc.comb +wire [9:0] pyc_comb_1913; // op=pyc.comb +wire [9:0] pyc_comb_1914; // op=pyc.comb +wire [9:0] pyc_comb_1915; // op=pyc.comb +wire [9:0] pyc_comb_1916; // op=pyc.comb +wire [9:0] pyc_comb_1917; // op=pyc.comb +wire [9:0] pyc_comb_1918; // op=pyc.comb +wire [9:0] pyc_comb_1919; // op=pyc.comb +wire [9:0] pyc_comb_1920; // op=pyc.comb +wire [9:0] pyc_comb_1921; // op=pyc.comb +wire [9:0] pyc_comb_1922; // op=pyc.comb +wire [9:0] pyc_comb_1923; // op=pyc.comb +wire [9:0] pyc_comb_1924; // op=pyc.comb +wire [9:0] pyc_comb_1925; // op=pyc.comb +wire [9:0] pyc_comb_1926; // op=pyc.comb +wire [9:0] pyc_comb_1927; // op=pyc.comb +wire [9:0] pyc_comb_1928; // op=pyc.comb +wire [9:0] pyc_comb_1929; // op=pyc.comb +wire [9:0] pyc_comb_1930; // op=pyc.comb +wire [9:0] pyc_comb_1931; // op=pyc.comb +wire [9:0] pyc_comb_1932; // op=pyc.comb +wire [9:0] pyc_comb_1933; // op=pyc.comb +wire [9:0] pyc_comb_1934; // op=pyc.comb +wire [9:0] pyc_comb_1935; // op=pyc.comb +wire [9:0] pyc_comb_1936; // op=pyc.comb +wire [9:0] pyc_comb_1937; // op=pyc.comb +wire [9:0] pyc_comb_1938; // op=pyc.comb +wire [9:0] pyc_comb_1939; // op=pyc.comb +wire [9:0] pyc_comb_1940; // op=pyc.comb +wire pyc_comb_1942; // op=pyc.comb +wire pyc_comb_1944; // op=pyc.comb +wire pyc_comb_1946; // op=pyc.comb +wire pyc_comb_1948; // op=pyc.comb +wire [1:0] pyc_comb_1950; // op=pyc.comb +wire [1:0] pyc_comb_1952; // op=pyc.comb +wire [1:0] pyc_comb_1954; // op=pyc.comb +wire [15:0] pyc_comb_20; // op=pyc.comb +wire [9:0] pyc_comb_2035; // op=pyc.comb +wire [18:0] pyc_comb_2036; // op=pyc.comb +wire [18:0] pyc_comb_2037; // op=pyc.comb +wire [18:0] pyc_comb_2038; // op=pyc.comb +wire [18:0] pyc_comb_2039; // op=pyc.comb +wire [18:0] pyc_comb_2040; // op=pyc.comb +wire [18:0] pyc_comb_2041; // op=pyc.comb +wire [18:0] pyc_comb_2042; // op=pyc.comb +wire [18:0] pyc_comb_2043; // op=pyc.comb +wire [18:0] pyc_comb_2053; // op=pyc.comb +wire [18:0] pyc_comb_2054; // op=pyc.comb +wire [18:0] pyc_comb_2055; // op=pyc.comb +wire [18:0] pyc_comb_2056; // op=pyc.comb +wire [18:0] pyc_comb_2057; // op=pyc.comb +wire [18:0] pyc_comb_2058; // op=pyc.comb +wire [18:0] pyc_comb_2059; // op=pyc.comb +wire [18:0] pyc_comb_2060; // op=pyc.comb +wire [18:0] pyc_comb_2061; // op=pyc.comb +wire [18:0] pyc_comb_2071; // op=pyc.comb +wire [15:0] pyc_comb_2072; // op=pyc.comb +wire [15:0] pyc_comb_2073; // op=pyc.comb +wire [15:0] pyc_comb_2074; // op=pyc.comb +wire [15:0] pyc_comb_2075; // op=pyc.comb +wire [15:0] pyc_comb_2076; // op=pyc.comb +wire [15:0] pyc_comb_2077; // op=pyc.comb +wire [15:0] pyc_comb_2078; // op=pyc.comb +wire [15:0] pyc_comb_2079; // op=pyc.comb +wire [15:0] pyc_comb_2089; // op=pyc.comb +wire [18:0] pyc_comb_2090; // op=pyc.comb +wire [18:0] pyc_comb_2091; // op=pyc.comb +wire [18:0] pyc_comb_2092; // op=pyc.comb +wire [18:0] pyc_comb_2093; // op=pyc.comb +wire [18:0] pyc_comb_2094; // op=pyc.comb +wire [18:0] pyc_comb_2095; // op=pyc.comb +wire [18:0] pyc_comb_2096; // op=pyc.comb +wire [18:0] pyc_comb_2097; // op=pyc.comb wire [1:0] pyc_comb_21; // op=pyc.comb +wire [18:0] pyc_comb_2107; // op=pyc.comb +wire [15:0] pyc_comb_2108; // op=pyc.comb +wire [15:0] pyc_comb_2109; // op=pyc.comb +wire [15:0] pyc_comb_2110; // op=pyc.comb +wire [15:0] pyc_comb_2111; // op=pyc.comb +wire [15:0] pyc_comb_2112; // op=pyc.comb +wire [15:0] pyc_comb_2113; // op=pyc.comb +wire [15:0] pyc_comb_2114; // op=pyc.comb +wire [15:0] pyc_comb_2115; // op=pyc.comb +wire [15:0] pyc_comb_2125; // op=pyc.comb +wire [18:0] pyc_comb_2126; // op=pyc.comb +wire [18:0] pyc_comb_2127; // op=pyc.comb +wire [18:0] pyc_comb_2128; // op=pyc.comb +wire [18:0] pyc_comb_2129; // op=pyc.comb +wire [18:0] pyc_comb_2130; // op=pyc.comb +wire [18:0] pyc_comb_2131; // op=pyc.comb +wire [18:0] pyc_comb_2132; // op=pyc.comb +wire [18:0] pyc_comb_2133; // op=pyc.comb +wire [18:0] pyc_comb_2143; // op=pyc.comb +wire [18:0] pyc_comb_2144; // op=pyc.comb +wire [18:0] pyc_comb_2145; // op=pyc.comb +wire [18:0] pyc_comb_2146; // op=pyc.comb +wire [18:0] pyc_comb_2147; // op=pyc.comb +wire [18:0] pyc_comb_2148; // op=pyc.comb +wire [18:0] pyc_comb_2149; // op=pyc.comb +wire [18:0] pyc_comb_2150; // op=pyc.comb +wire [18:0] pyc_comb_2151; // op=pyc.comb +wire [18:0] pyc_comb_2161; // op=pyc.comb +wire [15:0] pyc_comb_2162; // op=pyc.comb +wire [15:0] pyc_comb_2163; // op=pyc.comb +wire [15:0] pyc_comb_2164; // op=pyc.comb +wire [15:0] pyc_comb_2165; // op=pyc.comb +wire [15:0] pyc_comb_2166; // op=pyc.comb +wire [15:0] pyc_comb_2167; // op=pyc.comb +wire [15:0] pyc_comb_2168; // op=pyc.comb +wire [15:0] pyc_comb_2169; // op=pyc.comb +wire [15:0] pyc_comb_2179; // op=pyc.comb +wire [15:0] pyc_comb_2180; // op=pyc.comb +wire [15:0] pyc_comb_2181; // op=pyc.comb +wire [15:0] pyc_comb_2182; // op=pyc.comb +wire [15:0] pyc_comb_2183; // op=pyc.comb +wire [15:0] pyc_comb_2184; // op=pyc.comb +wire [15:0] pyc_comb_2185; // op=pyc.comb +wire [15:0] pyc_comb_2186; // op=pyc.comb +wire [15:0] pyc_comb_2187; // op=pyc.comb +wire pyc_comb_2192; // op=pyc.comb +wire pyc_comb_2193; // op=pyc.comb +wire [2:0] pyc_comb_2194; // op=pyc.comb +wire [2:0] pyc_comb_2195; // op=pyc.comb wire [79:0] pyc_comb_22; // op=pyc.comb -wire [79:0] pyc_comb_23; // op=pyc.comb -wire [79:0] pyc_comb_24; // op=pyc.comb -wire pyc_comb_25; // op=pyc.comb -wire pyc_comb_26; // op=pyc.comb -wire pyc_comb_27; // op=pyc.comb -wire pyc_comb_28; // op=pyc.comb -wire pyc_comb_30; // op=pyc.comb +wire pyc_comb_2200; // op=pyc.comb +wire pyc_comb_2201; // op=pyc.comb +wire pyc_comb_2202; // op=pyc.comb +wire pyc_comb_23; // op=pyc.comb +wire pyc_comb_24; // op=pyc.comb +wire [1:0] pyc_comb_25; // op=pyc.comb +wire [18:0] pyc_comb_2557; // op=pyc.comb +wire [15:0] pyc_comb_2558; // op=pyc.comb +wire [15:0] pyc_comb_2562; // op=pyc.comb +wire [15:0] pyc_comb_2563; // op=pyc.comb +wire [1:0] pyc_comb_26; // op=pyc.comb +wire [1:0] pyc_comb_27; // op=pyc.comb +wire [79:0] pyc_comb_28; // op=pyc.comb +wire [79:0] pyc_comb_29; // op=pyc.comb +wire [79:0] pyc_comb_30; // op=pyc.comb +wire pyc_comb_31; // op=pyc.comb wire pyc_comb_32; // op=pyc.comb +wire pyc_comb_33; // op=pyc.comb wire pyc_comb_34; // op=pyc.comb -wire [1:0] pyc_comb_350; // op=pyc.comb -wire [18:0] pyc_comb_351; // op=pyc.comb -wire [18:0] pyc_comb_352; // op=pyc.comb -wire [15:0] pyc_comb_353; // op=pyc.comb -wire [18:0] pyc_comb_354; // op=pyc.comb -wire [15:0] pyc_comb_355; // op=pyc.comb -wire [18:0] pyc_comb_356; // op=pyc.comb -wire [18:0] pyc_comb_357; // op=pyc.comb -wire [15:0] pyc_comb_358; // op=pyc.comb -wire [18:0] pyc_comb_359; // op=pyc.comb wire pyc_comb_36; // op=pyc.comb -wire [15:0] pyc_comb_360; // op=pyc.comb -wire [18:0] pyc_comb_361; // op=pyc.comb -wire [18:0] pyc_comb_362; // op=pyc.comb -wire [15:0] pyc_comb_363; // op=pyc.comb -wire [18:0] pyc_comb_364; // op=pyc.comb -wire [15:0] pyc_comb_365; // op=pyc.comb -wire [18:0] pyc_comb_366; // op=pyc.comb -wire [18:0] pyc_comb_367; // op=pyc.comb -wire [15:0] pyc_comb_368; // op=pyc.comb -wire [18:0] pyc_comb_369; // op=pyc.comb -wire [15:0] pyc_comb_370; // op=pyc.comb -wire [18:0] pyc_comb_371; // op=pyc.comb -wire [18:0] pyc_comb_372; // op=pyc.comb -wire [15:0] pyc_comb_373; // op=pyc.comb -wire [18:0] pyc_comb_374; // op=pyc.comb -wire [15:0] pyc_comb_375; // op=pyc.comb -wire [18:0] pyc_comb_376; // op=pyc.comb -wire [18:0] pyc_comb_377; // op=pyc.comb -wire [15:0] pyc_comb_378; // op=pyc.comb -wire [18:0] pyc_comb_379; // op=pyc.comb -wire [15:0] pyc_comb_380; // op=pyc.comb -wire [18:0] pyc_comb_381; // op=pyc.comb -wire [18:0] pyc_comb_382; // op=pyc.comb -wire [15:0] pyc_comb_383; // op=pyc.comb -wire [18:0] pyc_comb_384; // op=pyc.comb -wire [15:0] pyc_comb_385; // op=pyc.comb -wire [18:0] pyc_comb_386; // op=pyc.comb -wire [18:0] pyc_comb_387; // op=pyc.comb -wire [15:0] pyc_comb_388; // op=pyc.comb -wire [18:0] pyc_comb_389; // op=pyc.comb -wire [15:0] pyc_comb_390; // op=pyc.comb -wire [18:0] pyc_comb_391; // op=pyc.comb -wire [15:0] pyc_comb_392; // op=pyc.comb -wire [18:0] pyc_comb_393; // op=pyc.comb -wire [15:0] pyc_comb_394; // op=pyc.comb -wire [18:0] pyc_comb_395; // op=pyc.comb -wire [15:0] pyc_comb_396; // op=pyc.comb -wire [18:0] pyc_comb_397; // op=pyc.comb -wire [15:0] pyc_comb_398; // op=pyc.comb -wire [18:0] pyc_comb_399; // op=pyc.comb -wire [15:0] pyc_comb_400; // op=pyc.comb -wire [18:0] pyc_comb_401; // op=pyc.comb -wire [15:0] pyc_comb_402; // op=pyc.comb -wire [18:0] pyc_comb_403; // op=pyc.comb -wire [15:0] pyc_comb_404; // op=pyc.comb -wire [18:0] pyc_comb_405; // op=pyc.comb -wire [15:0] pyc_comb_406; // op=pyc.comb -wire [18:0] pyc_comb_407; // op=pyc.comb -wire [15:0] pyc_comb_408; // op=pyc.comb -wire [18:0] pyc_comb_409; // op=pyc.comb -wire [1:0] pyc_comb_41; // op=pyc.comb -wire [15:0] pyc_comb_410; // op=pyc.comb -wire [18:0] pyc_comb_411; // op=pyc.comb -wire [15:0] pyc_comb_412; // op=pyc.comb -wire [18:0] pyc_comb_413; // op=pyc.comb -wire [15:0] pyc_comb_414; // op=pyc.comb -wire [18:0] pyc_comb_415; // op=pyc.comb -wire [15:0] pyc_comb_416; // op=pyc.comb -wire [18:0] pyc_comb_417; // op=pyc.comb -wire [15:0] pyc_comb_418; // op=pyc.comb -wire [18:0] pyc_comb_419; // op=pyc.comb -wire [15:0] pyc_comb_420; // op=pyc.comb -wire [18:0] pyc_comb_421; // op=pyc.comb -wire [15:0] pyc_comb_422; // op=pyc.comb -wire pyc_comb_424; // op=pyc.comb -wire pyc_comb_426; // op=pyc.comb -wire pyc_comb_428; // op=pyc.comb -wire [1:0] pyc_comb_43; // op=pyc.comb -wire pyc_comb_430; // op=pyc.comb -wire [1:0] pyc_comb_432; // op=pyc.comb -wire [1:0] pyc_comb_434; // op=pyc.comb -wire [1:0] pyc_comb_436; // op=pyc.comb -wire pyc_comb_521; // op=pyc.comb -wire pyc_comb_522; // op=pyc.comb -wire [2:0] pyc_comb_523; // op=pyc.comb -wire [2:0] pyc_comb_524; // op=pyc.comb -wire pyc_comb_529; // op=pyc.comb -wire pyc_comb_530; // op=pyc.comb -wire pyc_comb_531; // op=pyc.comb -wire [18:0] pyc_comb_591; // op=pyc.comb -wire [15:0] pyc_comb_592; // op=pyc.comb -wire [15:0] pyc_comb_596; // op=pyc.comb -wire [15:0] pyc_comb_597; // op=pyc.comb -wire [7:0] pyc_concat_102; // op=pyc.concat -wire [7:0] pyc_concat_109; // op=pyc.concat -wire [7:0] pyc_concat_128; // op=pyc.concat -wire [7:0] pyc_concat_135; // op=pyc.concat -wire [7:0] pyc_concat_154; // op=pyc.concat -wire [7:0] pyc_concat_157; // op=pyc.concat -wire [7:0] pyc_concat_176; // op=pyc.concat -wire [7:0] pyc_concat_179; // op=pyc.concat -wire [7:0] pyc_concat_198; // op=pyc.concat -wire [7:0] pyc_concat_201; // op=pyc.concat -wire [7:0] pyc_concat_220; // op=pyc.concat -wire [7:0] pyc_concat_225; // op=pyc.concat -wire [7:0] pyc_concat_50; // op=pyc.concat -wire [2:0] pyc_concat_519; // op=pyc.concat -wire [2:0] pyc_concat_520; // op=pyc.concat -wire [7:0] pyc_concat_57; // op=pyc.concat -wire [7:0] pyc_concat_76; // op=pyc.concat -wire [7:0] pyc_concat_83; // op=pyc.concat +wire pyc_comb_38; // op=pyc.comb +wire pyc_comb_40; // op=pyc.comb +wire pyc_comb_42; // op=pyc.comb +wire [1:0] pyc_comb_47; // op=pyc.comb +wire [1:0] pyc_comb_49; // op=pyc.comb +wire [7:0] pyc_concat_1010; // op=pyc.concat +wire [7:0] pyc_concat_1013; // op=pyc.concat +wire [7:0] pyc_concat_194; // op=pyc.concat +wire [7:0] pyc_concat_199; // op=pyc.concat +wire [2:0] pyc_concat_2190; // op=pyc.concat +wire [2:0] pyc_concat_2191; // op=pyc.concat +wire [18:0] pyc_concat_2400; // op=pyc.concat +wire [15:0] pyc_concat_2549; // op=pyc.concat +wire [7:0] pyc_concat_332; // op=pyc.concat +wire [7:0] pyc_concat_337; // op=pyc.concat +wire [7:0] pyc_concat_470; // op=pyc.concat +wire [7:0] pyc_concat_475; // op=pyc.concat +wire [7:0] pyc_concat_56; // op=pyc.concat +wire [7:0] pyc_concat_608; // op=pyc.concat +wire [7:0] pyc_concat_609; // op=pyc.concat +wire [7:0] pyc_concat_61; // op=pyc.concat +wire [7:0] pyc_concat_742; // op=pyc.concat +wire [7:0] pyc_concat_743; // op=pyc.concat +wire [7:0] pyc_concat_876; // op=pyc.concat +wire [7:0] pyc_concat_877; // op=pyc.concat wire [1:0] pyc_constant_1; // op=pyc.constant -wire [15:0] pyc_constant_2; // op=pyc.constant -wire [18:0] pyc_constant_3; // op=pyc.constant -wire [1:0] pyc_constant_4; // op=pyc.constant -wire [79:0] pyc_constant_5; // op=pyc.constant -wire [1:0] pyc_constant_6; // op=pyc.constant -wire pyc_constant_7; // op=pyc.constant -wire pyc_constant_8; // op=pyc.constant -wire pyc_eq_10; // op=pyc.eq -wire pyc_eq_11; // op=pyc.eq -wire pyc_eq_554; // op=pyc.eq -wire pyc_eq_555; // op=pyc.eq -wire pyc_eq_560; // op=pyc.eq -wire pyc_eq_561; // op=pyc.eq -wire pyc_eq_573; // op=pyc.eq -wire pyc_eq_574; // op=pyc.eq -wire pyc_eq_579; // op=pyc.eq -wire pyc_eq_580; // op=pyc.eq -wire pyc_eq_9; // op=pyc.eq -wire [3:0] pyc_extract_100; // op=pyc.extract -wire [3:0] pyc_extract_101; // op=pyc.extract -wire [4:0] pyc_extract_105; // op=pyc.extract -wire [4:0] pyc_extract_106; // op=pyc.extract -wire [3:0] pyc_extract_107; // op=pyc.extract -wire [3:0] pyc_extract_108; // op=pyc.extract -wire [4:0] pyc_extract_111; // op=pyc.extract -wire [3:0] pyc_extract_112; // op=pyc.extract -wire [4:0] pyc_extract_114; // op=pyc.extract -wire [3:0] pyc_extract_115; // op=pyc.extract -wire [4:0] pyc_extract_124; // op=pyc.extract -wire [4:0] pyc_extract_125; // op=pyc.extract -wire [3:0] pyc_extract_126; // op=pyc.extract -wire [3:0] pyc_extract_127; // op=pyc.extract -wire [4:0] pyc_extract_131; // op=pyc.extract -wire [4:0] pyc_extract_132; // op=pyc.extract -wire [3:0] pyc_extract_133; // op=pyc.extract -wire [3:0] pyc_extract_134; // op=pyc.extract -wire [4:0] pyc_extract_137; // op=pyc.extract -wire [3:0] pyc_extract_138; // op=pyc.extract -wire [4:0] pyc_extract_140; // op=pyc.extract -wire [3:0] pyc_extract_141; // op=pyc.extract -wire [4:0] pyc_extract_150; // op=pyc.extract -wire [4:0] pyc_extract_151; // op=pyc.extract -wire [3:0] pyc_extract_152; // op=pyc.extract -wire [3:0] pyc_extract_153; // op=pyc.extract -wire [4:0] pyc_extract_159; // op=pyc.extract -wire [3:0] pyc_extract_160; // op=pyc.extract -wire [4:0] pyc_extract_162; // op=pyc.extract -wire [3:0] pyc_extract_163; // op=pyc.extract -wire [4:0] pyc_extract_172; // op=pyc.extract -wire [4:0] pyc_extract_173; // op=pyc.extract -wire [3:0] pyc_extract_174; // op=pyc.extract -wire [3:0] pyc_extract_175; // op=pyc.extract -wire [4:0] pyc_extract_181; // op=pyc.extract -wire [3:0] pyc_extract_182; // op=pyc.extract -wire [4:0] pyc_extract_184; // op=pyc.extract -wire [3:0] pyc_extract_185; // op=pyc.extract -wire [4:0] pyc_extract_194; // op=pyc.extract +wire pyc_constant_10; // op=pyc.constant +wire pyc_constant_11; // op=pyc.constant +wire [18:0] pyc_constant_2; // op=pyc.constant +wire [9:0] pyc_constant_3; // op=pyc.constant +wire [12:0] pyc_constant_4; // op=pyc.constant +wire [11:0] pyc_constant_5; // op=pyc.constant +wire [15:0] pyc_constant_6; // op=pyc.constant +wire [1:0] pyc_constant_7; // op=pyc.constant +wire [79:0] pyc_constant_8; // op=pyc.constant +wire [1:0] pyc_constant_9; // op=pyc.constant +wire pyc_eq_12; // op=pyc.eq +wire pyc_eq_13; // op=pyc.eq +wire pyc_eq_14; // op=pyc.eq +wire pyc_eq_2225; // op=pyc.eq +wire pyc_eq_2226; // op=pyc.eq +wire pyc_eq_2231; // op=pyc.eq +wire pyc_eq_2232; // op=pyc.eq +wire pyc_eq_2407; // op=pyc.eq +wire pyc_eq_2408; // op=pyc.eq +wire pyc_eq_2413; // op=pyc.eq +wire pyc_eq_2414; // op=pyc.eq +wire [4:0] pyc_extract_1006; // op=pyc.extract +wire [4:0] pyc_extract_1007; // op=pyc.extract +wire [3:0] pyc_extract_1008; // op=pyc.extract +wire [3:0] pyc_extract_1009; // op=pyc.extract +wire [4:0] pyc_extract_1011; // op=pyc.extract +wire [3:0] pyc_extract_1012; // op=pyc.extract +wire [4:0] pyc_extract_1014; // op=pyc.extract +wire [3:0] pyc_extract_1015; // op=pyc.extract +wire pyc_extract_1017; // op=pyc.extract +wire pyc_extract_1020; // op=pyc.extract +wire pyc_extract_1024; // op=pyc.extract +wire pyc_extract_1028; // op=pyc.extract +wire pyc_extract_1032; // op=pyc.extract +wire pyc_extract_1036; // op=pyc.extract +wire pyc_extract_1040; // op=pyc.extract +wire pyc_extract_1044; // op=pyc.extract +wire pyc_extract_1049; // op=pyc.extract +wire pyc_extract_1056; // op=pyc.extract +wire pyc_extract_1059; // op=pyc.extract +wire pyc_extract_106; // op=pyc.extract +wire pyc_extract_1063; // op=pyc.extract +wire pyc_extract_1067; // op=pyc.extract +wire pyc_extract_1077; // op=pyc.extract +wire pyc_extract_1079; // op=pyc.extract +wire pyc_extract_1082; // op=pyc.extract +wire pyc_extract_1085; // op=pyc.extract +wire pyc_extract_109; // op=pyc.extract +wire pyc_extract_1095; // op=pyc.extract +wire pyc_extract_1098; // op=pyc.extract +wire pyc_extract_1102; // op=pyc.extract +wire pyc_extract_1106; // op=pyc.extract +wire pyc_extract_1110; // op=pyc.extract +wire pyc_extract_1120; // op=pyc.extract +wire pyc_extract_1122; // op=pyc.extract +wire pyc_extract_1125; // op=pyc.extract +wire pyc_extract_1128; // op=pyc.extract +wire pyc_extract_113; // op=pyc.extract +wire pyc_extract_1131; // op=pyc.extract +wire [4:0] pyc_extract_1140; // op=pyc.extract +wire pyc_extract_1142; // op=pyc.extract +wire pyc_extract_1145; // op=pyc.extract +wire pyc_extract_1149; // op=pyc.extract +wire pyc_extract_1153; // op=pyc.extract +wire pyc_extract_1157; // op=pyc.extract +wire pyc_extract_1162; // op=pyc.extract +wire pyc_extract_1168; // op=pyc.extract +wire pyc_extract_117; // op=pyc.extract +wire pyc_extract_1170; // op=pyc.extract +wire pyc_extract_1173; // op=pyc.extract +wire pyc_extract_1176; // op=pyc.extract +wire pyc_extract_1179; // op=pyc.extract +wire [4:0] pyc_extract_1188; // op=pyc.extract +wire pyc_extract_1190; // op=pyc.extract +wire pyc_extract_1193; // op=pyc.extract +wire pyc_extract_1197; // op=pyc.extract +wire pyc_extract_1201; // op=pyc.extract +wire pyc_extract_1205; // op=pyc.extract +wire pyc_extract_1210; // op=pyc.extract +wire pyc_extract_1216; // op=pyc.extract +wire pyc_extract_1218; // op=pyc.extract +wire pyc_extract_1221; // op=pyc.extract +wire pyc_extract_1224; // op=pyc.extract +wire pyc_extract_1227; // op=pyc.extract +wire [4:0] pyc_extract_1236; // op=pyc.extract +wire pyc_extract_1238; // op=pyc.extract +wire pyc_extract_1241; // op=pyc.extract +wire pyc_extract_1245; // op=pyc.extract +wire pyc_extract_1249; // op=pyc.extract +wire pyc_extract_1253; // op=pyc.extract +wire pyc_extract_1258; // op=pyc.extract +wire pyc_extract_1264; // op=pyc.extract +wire pyc_extract_1266; // op=pyc.extract +wire pyc_extract_1269; // op=pyc.extract +wire pyc_extract_127; // op=pyc.extract +wire pyc_extract_1272; // op=pyc.extract +wire pyc_extract_1275; // op=pyc.extract +wire [4:0] pyc_extract_1284; // op=pyc.extract +wire pyc_extract_1286; // op=pyc.extract +wire pyc_extract_1289; // op=pyc.extract +wire pyc_extract_129; // op=pyc.extract +wire pyc_extract_1293; // op=pyc.extract +wire pyc_extract_1297; // op=pyc.extract +wire pyc_extract_1301; // op=pyc.extract +wire pyc_extract_1306; // op=pyc.extract +wire pyc_extract_1312; // op=pyc.extract +wire pyc_extract_1314; // op=pyc.extract +wire pyc_extract_1317; // op=pyc.extract +wire pyc_extract_132; // op=pyc.extract +wire pyc_extract_1320; // op=pyc.extract +wire pyc_extract_1323; // op=pyc.extract +wire [4:0] pyc_extract_1332; // op=pyc.extract +wire pyc_extract_1334; // op=pyc.extract +wire pyc_extract_1337; // op=pyc.extract +wire pyc_extract_1341; // op=pyc.extract +wire pyc_extract_1345; // op=pyc.extract +wire pyc_extract_1349; // op=pyc.extract +wire pyc_extract_135; // op=pyc.extract +wire pyc_extract_1354; // op=pyc.extract +wire pyc_extract_1360; // op=pyc.extract +wire pyc_extract_1362; // op=pyc.extract +wire pyc_extract_1365; // op=pyc.extract +wire pyc_extract_1368; // op=pyc.extract +wire pyc_extract_1371; // op=pyc.extract +wire [4:0] pyc_extract_1380; // op=pyc.extract +wire pyc_extract_1382; // op=pyc.extract +wire pyc_extract_1385; // op=pyc.extract +wire pyc_extract_1389; // op=pyc.extract +wire pyc_extract_1393; // op=pyc.extract +wire pyc_extract_1397; // op=pyc.extract +wire pyc_extract_1402; // op=pyc.extract +wire pyc_extract_1408; // op=pyc.extract +wire pyc_extract_1410; // op=pyc.extract +wire pyc_extract_1413; // op=pyc.extract +wire pyc_extract_1416; // op=pyc.extract +wire pyc_extract_1419; // op=pyc.extract +wire [4:0] pyc_extract_1428; // op=pyc.extract +wire pyc_extract_1430; // op=pyc.extract +wire pyc_extract_1433; // op=pyc.extract +wire pyc_extract_1437; // op=pyc.extract +wire pyc_extract_1441; // op=pyc.extract +wire pyc_extract_1445; // op=pyc.extract +wire pyc_extract_145; // op=pyc.extract +wire pyc_extract_1450; // op=pyc.extract +wire pyc_extract_1456; // op=pyc.extract +wire pyc_extract_1458; // op=pyc.extract +wire pyc_extract_1461; // op=pyc.extract +wire pyc_extract_1464; // op=pyc.extract +wire pyc_extract_1467; // op=pyc.extract +wire [4:0] pyc_extract_1476; // op=pyc.extract +wire pyc_extract_1478; // op=pyc.extract +wire pyc_extract_148; // op=pyc.extract +wire pyc_extract_1481; // op=pyc.extract +wire pyc_extract_1485; // op=pyc.extract +wire pyc_extract_1489; // op=pyc.extract +wire pyc_extract_1493; // op=pyc.extract +wire pyc_extract_1498; // op=pyc.extract +wire pyc_extract_1504; // op=pyc.extract +wire pyc_extract_1506; // op=pyc.extract +wire pyc_extract_1509; // op=pyc.extract +wire pyc_extract_1512; // op=pyc.extract +wire pyc_extract_1515; // op=pyc.extract +wire pyc_extract_152; // op=pyc.extract +wire [4:0] pyc_extract_1524; // op=pyc.extract +wire pyc_extract_1541; // op=pyc.extract +wire pyc_extract_1547; // op=pyc.extract +wire pyc_extract_1549; // op=pyc.extract +wire pyc_extract_1552; // op=pyc.extract +wire pyc_extract_1555; // op=pyc.extract +wire pyc_extract_1558; // op=pyc.extract +wire pyc_extract_156; // op=pyc.extract +wire [4:0] pyc_extract_1567; // op=pyc.extract +wire pyc_extract_1584; // op=pyc.extract +wire pyc_extract_1590; // op=pyc.extract +wire pyc_extract_1592; // op=pyc.extract +wire pyc_extract_1595; // op=pyc.extract +wire pyc_extract_1598; // op=pyc.extract +wire pyc_extract_160; // op=pyc.extract +wire pyc_extract_1601; // op=pyc.extract +wire [4:0] pyc_extract_1610; // op=pyc.extract +wire pyc_extract_1627; // op=pyc.extract +wire pyc_extract_1633; // op=pyc.extract +wire pyc_extract_1635; // op=pyc.extract +wire pyc_extract_1638; // op=pyc.extract +wire pyc_extract_1641; // op=pyc.extract +wire pyc_extract_1644; // op=pyc.extract +wire [4:0] pyc_extract_1653; // op=pyc.extract +wire pyc_extract_1670; // op=pyc.extract +wire pyc_extract_1676; // op=pyc.extract +wire pyc_extract_1678; // op=pyc.extract +wire pyc_extract_1681; // op=pyc.extract +wire pyc_extract_1684; // op=pyc.extract +wire pyc_extract_1687; // op=pyc.extract +wire [4:0] pyc_extract_1696; // op=pyc.extract +wire pyc_extract_170; // op=pyc.extract +wire pyc_extract_1713; // op=pyc.extract +wire pyc_extract_1719; // op=pyc.extract +wire pyc_extract_172; // op=pyc.extract +wire pyc_extract_1721; // op=pyc.extract +wire pyc_extract_1724; // op=pyc.extract +wire pyc_extract_1727; // op=pyc.extract +wire pyc_extract_1730; // op=pyc.extract +wire [4:0] pyc_extract_1739; // op=pyc.extract +wire pyc_extract_175; // op=pyc.extract +wire pyc_extract_1756; // op=pyc.extract +wire pyc_extract_1762; // op=pyc.extract +wire pyc_extract_1764; // op=pyc.extract +wire pyc_extract_1767; // op=pyc.extract +wire pyc_extract_1770; // op=pyc.extract +wire pyc_extract_1773; // op=pyc.extract +wire pyc_extract_178; // op=pyc.extract +wire [4:0] pyc_extract_1782; // op=pyc.extract +wire pyc_extract_1799; // op=pyc.extract +wire pyc_extract_1805; // op=pyc.extract +wire pyc_extract_1807; // op=pyc.extract +wire pyc_extract_181; // op=pyc.extract +wire pyc_extract_1810; // op=pyc.extract +wire pyc_extract_1813; // op=pyc.extract +wire pyc_extract_1816; // op=pyc.extract +wire [4:0] pyc_extract_1825; // op=pyc.extract +wire pyc_extract_1842; // op=pyc.extract +wire pyc_extract_1848; // op=pyc.extract +wire pyc_extract_1850; // op=pyc.extract +wire pyc_extract_1853; // op=pyc.extract +wire pyc_extract_1856; // op=pyc.extract +wire pyc_extract_1859; // op=pyc.extract +wire [4:0] pyc_extract_190; // op=pyc.extract +wire [4:0] pyc_extract_191; // op=pyc.extract +wire [3:0] pyc_extract_192; // op=pyc.extract +wire [3:0] pyc_extract_193; // op=pyc.extract wire [4:0] pyc_extract_195; // op=pyc.extract -wire [3:0] pyc_extract_196; // op=pyc.extract +wire [4:0] pyc_extract_196; // op=pyc.extract wire [3:0] pyc_extract_197; // op=pyc.extract -wire [4:0] pyc_extract_203; // op=pyc.extract -wire [3:0] pyc_extract_204; // op=pyc.extract -wire [4:0] pyc_extract_206; // op=pyc.extract -wire [3:0] pyc_extract_207; // op=pyc.extract -wire [4:0] pyc_extract_216; // op=pyc.extract -wire [4:0] pyc_extract_217; // op=pyc.extract -wire [3:0] pyc_extract_218; // op=pyc.extract -wire [3:0] pyc_extract_219; // op=pyc.extract -wire [4:0] pyc_extract_223; // op=pyc.extract -wire [3:0] pyc_extract_224; // op=pyc.extract -wire [4:0] pyc_extract_227; // op=pyc.extract -wire [3:0] pyc_extract_228; // op=pyc.extract -wire [4:0] pyc_extract_241; // op=pyc.extract -wire [4:0] pyc_extract_248; // op=pyc.extract -wire [4:0] pyc_extract_255; // op=pyc.extract -wire [4:0] pyc_extract_262; // op=pyc.extract -wire [4:0] pyc_extract_269; // op=pyc.extract -wire [4:0] pyc_extract_276; // op=pyc.extract -wire [4:0] pyc_extract_283; // op=pyc.extract -wire [4:0] pyc_extract_290; // op=pyc.extract -wire [4:0] pyc_extract_297; // op=pyc.extract -wire [4:0] pyc_extract_304; // op=pyc.extract -wire [4:0] pyc_extract_311; // op=pyc.extract -wire [4:0] pyc_extract_318; // op=pyc.extract -wire [4:0] pyc_extract_325; // op=pyc.extract -wire [4:0] pyc_extract_332; // op=pyc.extract -wire [4:0] pyc_extract_339; // op=pyc.extract -wire [4:0] pyc_extract_346; // op=pyc.extract -wire [39:0] pyc_extract_45; // op=pyc.extract -wire [4:0] pyc_extract_46; // op=pyc.extract -wire [4:0] pyc_extract_47; // op=pyc.extract -wire [3:0] pyc_extract_48; // op=pyc.extract -wire [3:0] pyc_extract_49; // op=pyc.extract -wire pyc_extract_526; // op=pyc.extract +wire [3:0] pyc_extract_198; // op=pyc.extract +wire [4:0] pyc_extract_200; // op=pyc.extract +wire [3:0] pyc_extract_201; // op=pyc.extract +wire [4:0] pyc_extract_202; // op=pyc.extract +wire [3:0] pyc_extract_203; // op=pyc.extract +wire pyc_extract_205; // op=pyc.extract +wire pyc_extract_208; // op=pyc.extract +wire pyc_extract_212; // op=pyc.extract +wire pyc_extract_216; // op=pyc.extract +wire pyc_extract_2197; // op=pyc.extract +wire pyc_extract_2198; // op=pyc.extract +wire pyc_extract_2199; // op=pyc.extract +wire pyc_extract_220; // op=pyc.extract +wire pyc_extract_2215; // op=pyc.extract +wire pyc_extract_2217; // op=pyc.extract +wire pyc_extract_2220; // op=pyc.extract +wire pyc_extract_2222; // op=pyc.extract +wire pyc_extract_2237; // op=pyc.extract +wire pyc_extract_2238; // op=pyc.extract +wire pyc_extract_224; // op=pyc.extract +wire pyc_extract_2240; // op=pyc.extract +wire pyc_extract_2241; // op=pyc.extract +wire pyc_extract_2243; // op=pyc.extract +wire pyc_extract_2244; // op=pyc.extract +wire pyc_extract_2246; // op=pyc.extract +wire pyc_extract_2247; // op=pyc.extract +wire pyc_extract_2249; // op=pyc.extract +wire pyc_extract_2250; // op=pyc.extract +wire pyc_extract_2252; // op=pyc.extract +wire pyc_extract_2253; // op=pyc.extract +wire pyc_extract_2255; // op=pyc.extract +wire pyc_extract_2256; // op=pyc.extract +wire pyc_extract_2258; // op=pyc.extract +wire pyc_extract_2259; // op=pyc.extract +wire pyc_extract_2261; // op=pyc.extract +wire pyc_extract_2262; // op=pyc.extract +wire pyc_extract_2264; // op=pyc.extract +wire pyc_extract_2265; // op=pyc.extract +wire pyc_extract_2267; // op=pyc.extract +wire pyc_extract_2268; // op=pyc.extract +wire pyc_extract_2270; // op=pyc.extract +wire pyc_extract_2271; // op=pyc.extract +wire pyc_extract_2273; // op=pyc.extract +wire pyc_extract_2274; // op=pyc.extract +wire pyc_extract_2276; // op=pyc.extract +wire pyc_extract_2277; // op=pyc.extract +wire pyc_extract_2279; // op=pyc.extract +wire pyc_extract_228; // op=pyc.extract +wire pyc_extract_2280; // op=pyc.extract +wire pyc_extract_2282; // op=pyc.extract +wire pyc_extract_2283; // op=pyc.extract +wire pyc_extract_2285; // op=pyc.extract +wire pyc_extract_2286; // op=pyc.extract +wire pyc_extract_2288; // op=pyc.extract +wire pyc_extract_2289; // op=pyc.extract +wire pyc_extract_2291; // op=pyc.extract +wire pyc_extract_2292; // op=pyc.extract +wire pyc_extract_232; // op=pyc.extract +wire pyc_extract_237; // op=pyc.extract +wire pyc_extract_2401; // op=pyc.extract +wire pyc_extract_2404; // op=pyc.extract +wire pyc_extract_2419; // op=pyc.extract +wire pyc_extract_2420; // op=pyc.extract +wire pyc_extract_2422; // op=pyc.extract +wire pyc_extract_2423; // op=pyc.extract +wire pyc_extract_2425; // op=pyc.extract +wire pyc_extract_2426; // op=pyc.extract +wire pyc_extract_2428; // op=pyc.extract +wire pyc_extract_2429; // op=pyc.extract +wire pyc_extract_2431; // op=pyc.extract +wire pyc_extract_2432; // op=pyc.extract +wire pyc_extract_2434; // op=pyc.extract +wire pyc_extract_2435; // op=pyc.extract +wire pyc_extract_2437; // op=pyc.extract +wire pyc_extract_2438; // op=pyc.extract +wire pyc_extract_244; // op=pyc.extract +wire pyc_extract_2440; // op=pyc.extract +wire pyc_extract_2441; // op=pyc.extract +wire pyc_extract_2443; // op=pyc.extract +wire pyc_extract_2444; // op=pyc.extract +wire pyc_extract_2446; // op=pyc.extract +wire pyc_extract_2447; // op=pyc.extract +wire pyc_extract_2449; // op=pyc.extract +wire pyc_extract_2450; // op=pyc.extract +wire pyc_extract_2452; // op=pyc.extract +wire pyc_extract_2453; // op=pyc.extract +wire pyc_extract_2455; // op=pyc.extract +wire pyc_extract_2456; // op=pyc.extract +wire pyc_extract_2458; // op=pyc.extract +wire pyc_extract_2459; // op=pyc.extract +wire pyc_extract_2461; // op=pyc.extract +wire pyc_extract_2462; // op=pyc.extract +wire pyc_extract_2464; // op=pyc.extract +wire pyc_extract_2465; // op=pyc.extract +wire pyc_extract_247; // op=pyc.extract +wire pyc_extract_251; // op=pyc.extract +wire pyc_extract_255; // op=pyc.extract +wire pyc_extract_265; // op=pyc.extract +wire pyc_extract_267; // op=pyc.extract +wire pyc_extract_270; // op=pyc.extract +wire pyc_extract_273; // op=pyc.extract +wire pyc_extract_283; // op=pyc.extract +wire pyc_extract_286; // op=pyc.extract +wire pyc_extract_290; // op=pyc.extract +wire pyc_extract_294; // op=pyc.extract +wire pyc_extract_298; // op=pyc.extract +wire pyc_extract_308; // op=pyc.extract +wire pyc_extract_310; // op=pyc.extract +wire pyc_extract_313; // op=pyc.extract +wire pyc_extract_316; // op=pyc.extract +wire pyc_extract_319; // op=pyc.extract +wire [4:0] pyc_extract_328; // op=pyc.extract +wire [4:0] pyc_extract_329; // op=pyc.extract +wire [3:0] pyc_extract_330; // op=pyc.extract +wire [3:0] pyc_extract_331; // op=pyc.extract +wire [4:0] pyc_extract_333; // op=pyc.extract +wire [4:0] pyc_extract_334; // op=pyc.extract +wire [3:0] pyc_extract_335; // op=pyc.extract +wire [3:0] pyc_extract_336; // op=pyc.extract +wire [4:0] pyc_extract_338; // op=pyc.extract +wire [3:0] pyc_extract_339; // op=pyc.extract +wire [4:0] pyc_extract_340; // op=pyc.extract +wire [3:0] pyc_extract_341; // op=pyc.extract +wire pyc_extract_343; // op=pyc.extract +wire pyc_extract_346; // op=pyc.extract +wire pyc_extract_350; // op=pyc.extract +wire pyc_extract_354; // op=pyc.extract +wire pyc_extract_358; // op=pyc.extract +wire pyc_extract_362; // op=pyc.extract +wire pyc_extract_366; // op=pyc.extract +wire pyc_extract_370; // op=pyc.extract +wire pyc_extract_375; // op=pyc.extract +wire pyc_extract_382; // op=pyc.extract +wire pyc_extract_385; // op=pyc.extract +wire pyc_extract_389; // op=pyc.extract +wire pyc_extract_393; // op=pyc.extract +wire pyc_extract_403; // op=pyc.extract +wire pyc_extract_405; // op=pyc.extract +wire pyc_extract_408; // op=pyc.extract +wire pyc_extract_411; // op=pyc.extract +wire pyc_extract_421; // op=pyc.extract +wire pyc_extract_424; // op=pyc.extract +wire pyc_extract_428; // op=pyc.extract +wire pyc_extract_432; // op=pyc.extract +wire pyc_extract_436; // op=pyc.extract +wire pyc_extract_446; // op=pyc.extract +wire pyc_extract_448; // op=pyc.extract +wire pyc_extract_451; // op=pyc.extract +wire pyc_extract_454; // op=pyc.extract +wire pyc_extract_457; // op=pyc.extract +wire [4:0] pyc_extract_466; // op=pyc.extract +wire [4:0] pyc_extract_467; // op=pyc.extract +wire [3:0] pyc_extract_468; // op=pyc.extract +wire [3:0] pyc_extract_469; // op=pyc.extract +wire [4:0] pyc_extract_471; // op=pyc.extract +wire [4:0] pyc_extract_472; // op=pyc.extract +wire [3:0] pyc_extract_473; // op=pyc.extract +wire [3:0] pyc_extract_474; // op=pyc.extract +wire [4:0] pyc_extract_476; // op=pyc.extract +wire [3:0] pyc_extract_477; // op=pyc.extract +wire [4:0] pyc_extract_478; // op=pyc.extract +wire [3:0] pyc_extract_479; // op=pyc.extract +wire pyc_extract_481; // op=pyc.extract +wire pyc_extract_484; // op=pyc.extract +wire pyc_extract_488; // op=pyc.extract +wire pyc_extract_492; // op=pyc.extract +wire pyc_extract_496; // op=pyc.extract +wire pyc_extract_500; // op=pyc.extract +wire pyc_extract_504; // op=pyc.extract +wire pyc_extract_508; // op=pyc.extract +wire [39:0] pyc_extract_51; // op=pyc.extract +wire pyc_extract_513; // op=pyc.extract +wire [4:0] pyc_extract_52; // op=pyc.extract +wire pyc_extract_520; // op=pyc.extract +wire pyc_extract_523; // op=pyc.extract wire pyc_extract_527; // op=pyc.extract -wire pyc_extract_528; // op=pyc.extract wire [4:0] pyc_extract_53; // op=pyc.extract -wire [4:0] pyc_extract_54; // op=pyc.extract -wire pyc_extract_544; // op=pyc.extract +wire pyc_extract_531; // op=pyc.extract +wire [3:0] pyc_extract_54; // op=pyc.extract +wire pyc_extract_541; // op=pyc.extract +wire pyc_extract_543; // op=pyc.extract wire pyc_extract_546; // op=pyc.extract wire pyc_extract_549; // op=pyc.extract wire [3:0] pyc_extract_55; // op=pyc.extract -wire pyc_extract_551; // op=pyc.extract -wire [3:0] pyc_extract_56; // op=pyc.extract -wire pyc_extract_567; // op=pyc.extract +wire pyc_extract_559; // op=pyc.extract +wire pyc_extract_562; // op=pyc.extract +wire pyc_extract_566; // op=pyc.extract +wire [4:0] pyc_extract_57; // op=pyc.extract wire pyc_extract_570; // op=pyc.extract -wire [4:0] pyc_extract_59; // op=pyc.extract +wire pyc_extract_574; // op=pyc.extract +wire [4:0] pyc_extract_58; // op=pyc.extract +wire pyc_extract_584; // op=pyc.extract +wire pyc_extract_586; // op=pyc.extract +wire pyc_extract_589; // op=pyc.extract +wire [3:0] pyc_extract_59; // op=pyc.extract +wire pyc_extract_592; // op=pyc.extract +wire pyc_extract_595; // op=pyc.extract wire [3:0] pyc_extract_60; // op=pyc.extract +wire [4:0] pyc_extract_604; // op=pyc.extract +wire [4:0] pyc_extract_605; // op=pyc.extract +wire [3:0] pyc_extract_606; // op=pyc.extract +wire [3:0] pyc_extract_607; // op=pyc.extract +wire [4:0] pyc_extract_610; // op=pyc.extract +wire [3:0] pyc_extract_611; // op=pyc.extract +wire [4:0] pyc_extract_612; // op=pyc.extract +wire [3:0] pyc_extract_613; // op=pyc.extract +wire pyc_extract_615; // op=pyc.extract +wire pyc_extract_618; // op=pyc.extract wire [4:0] pyc_extract_62; // op=pyc.extract +wire pyc_extract_622; // op=pyc.extract +wire pyc_extract_626; // op=pyc.extract wire [3:0] pyc_extract_63; // op=pyc.extract -wire [4:0] pyc_extract_72; // op=pyc.extract -wire [4:0] pyc_extract_73; // op=pyc.extract -wire [3:0] pyc_extract_74; // op=pyc.extract -wire [3:0] pyc_extract_75; // op=pyc.extract -wire [4:0] pyc_extract_79; // op=pyc.extract -wire [4:0] pyc_extract_80; // op=pyc.extract -wire [3:0] pyc_extract_81; // op=pyc.extract -wire [3:0] pyc_extract_82; // op=pyc.extract -wire [4:0] pyc_extract_85; // op=pyc.extract -wire [3:0] pyc_extract_86; // op=pyc.extract -wire [4:0] pyc_extract_88; // op=pyc.extract -wire [3:0] pyc_extract_89; // op=pyc.extract -wire [4:0] pyc_extract_98; // op=pyc.extract -wire [4:0] pyc_extract_99; // op=pyc.extract -wire [18:0] pyc_instance_509; // op=pyc.instance -wire [18:0] pyc_instance_510; // op=pyc.instance -wire [15:0] pyc_instance_511; // op=pyc.instance -wire [18:0] pyc_instance_512; // op=pyc.instance -wire [15:0] pyc_instance_513; // op=pyc.instance -wire [18:0] pyc_instance_514; // op=pyc.instance -wire [18:0] pyc_instance_515; // op=pyc.instance -wire [15:0] pyc_instance_516; // op=pyc.instance -wire [15:0] pyc_instance_517; // op=pyc.instance -wire [18:0] pyc_mul_119; // op=pyc.mul -wire [18:0] pyc_mul_120; // op=pyc.mul -wire [15:0] pyc_mul_121; // op=pyc.mul -wire [18:0] pyc_mul_122; // op=pyc.mul -wire [15:0] pyc_mul_123; // op=pyc.mul -wire [18:0] pyc_mul_145; // op=pyc.mul -wire [18:0] pyc_mul_146; // op=pyc.mul -wire [15:0] pyc_mul_147; // op=pyc.mul -wire [18:0] pyc_mul_148; // op=pyc.mul -wire [15:0] pyc_mul_149; // op=pyc.mul -wire [18:0] pyc_mul_167; // op=pyc.mul -wire [18:0] pyc_mul_168; // op=pyc.mul -wire [15:0] pyc_mul_169; // op=pyc.mul -wire [18:0] pyc_mul_170; // op=pyc.mul -wire [15:0] pyc_mul_171; // op=pyc.mul -wire [18:0] pyc_mul_189; // op=pyc.mul -wire [18:0] pyc_mul_190; // op=pyc.mul -wire [15:0] pyc_mul_191; // op=pyc.mul -wire [18:0] pyc_mul_192; // op=pyc.mul -wire [15:0] pyc_mul_193; // op=pyc.mul -wire [18:0] pyc_mul_211; // op=pyc.mul -wire [18:0] pyc_mul_212; // op=pyc.mul -wire [15:0] pyc_mul_213; // op=pyc.mul -wire [18:0] pyc_mul_214; // op=pyc.mul -wire [15:0] pyc_mul_215; // op=pyc.mul -wire [18:0] pyc_mul_233; // op=pyc.mul -wire [18:0] pyc_mul_234; // op=pyc.mul -wire [15:0] pyc_mul_235; // op=pyc.mul -wire [18:0] pyc_mul_236; // op=pyc.mul -wire [15:0] pyc_mul_237; // op=pyc.mul -wire [18:0] pyc_mul_243; // op=pyc.mul -wire [15:0] pyc_mul_244; // op=pyc.mul -wire [18:0] pyc_mul_250; // op=pyc.mul -wire [15:0] pyc_mul_251; // op=pyc.mul -wire [18:0] pyc_mul_257; // op=pyc.mul -wire [15:0] pyc_mul_258; // op=pyc.mul -wire [18:0] pyc_mul_264; // op=pyc.mul -wire [15:0] pyc_mul_265; // op=pyc.mul -wire [18:0] pyc_mul_271; // op=pyc.mul -wire [15:0] pyc_mul_272; // op=pyc.mul -wire [18:0] pyc_mul_278; // op=pyc.mul -wire [15:0] pyc_mul_279; // op=pyc.mul -wire [18:0] pyc_mul_285; // op=pyc.mul -wire [15:0] pyc_mul_286; // op=pyc.mul -wire [18:0] pyc_mul_292; // op=pyc.mul -wire [15:0] pyc_mul_293; // op=pyc.mul -wire [18:0] pyc_mul_299; // op=pyc.mul -wire [15:0] pyc_mul_300; // op=pyc.mul -wire [18:0] pyc_mul_306; // op=pyc.mul -wire [15:0] pyc_mul_307; // op=pyc.mul -wire [18:0] pyc_mul_313; // op=pyc.mul -wire [15:0] pyc_mul_314; // op=pyc.mul -wire [18:0] pyc_mul_320; // op=pyc.mul -wire [15:0] pyc_mul_321; // op=pyc.mul -wire [18:0] pyc_mul_327; // op=pyc.mul -wire [15:0] pyc_mul_328; // op=pyc.mul -wire [18:0] pyc_mul_334; // op=pyc.mul -wire [15:0] pyc_mul_335; // op=pyc.mul -wire [18:0] pyc_mul_341; // op=pyc.mul -wire [15:0] pyc_mul_342; // op=pyc.mul -wire [18:0] pyc_mul_348; // op=pyc.mul -wire [15:0] pyc_mul_349; // op=pyc.mul -wire [18:0] pyc_mul_67; // op=pyc.mul -wire [18:0] pyc_mul_68; // op=pyc.mul -wire [15:0] pyc_mul_69; // op=pyc.mul -wire [18:0] pyc_mul_70; // op=pyc.mul -wire [15:0] pyc_mul_71; // op=pyc.mul -wire [18:0] pyc_mul_93; // op=pyc.mul -wire [18:0] pyc_mul_94; // op=pyc.mul -wire [15:0] pyc_mul_95; // op=pyc.mul -wire [18:0] pyc_mul_96; // op=pyc.mul -wire [15:0] pyc_mul_97; // op=pyc.mul -wire [18:0] pyc_mux_558; // op=pyc.mux -wire [18:0] pyc_mux_559; // op=pyc.mux -wire [18:0] pyc_mux_564; // op=pyc.mux -wire [18:0] pyc_mux_565; // op=pyc.mux -wire [15:0] pyc_mux_577; // op=pyc.mux -wire [15:0] pyc_mux_578; // op=pyc.mux -wire [15:0] pyc_mux_583; // op=pyc.mux -wire [15:0] pyc_mux_584; // op=pyc.mux -wire [18:0] pyc_mux_586; // op=pyc.mux -wire [18:0] pyc_mux_587; // op=pyc.mux -wire [18:0] pyc_mux_588; // op=pyc.mux -wire [15:0] pyc_mux_589; // op=pyc.mux -wire [15:0] pyc_mux_590; // op=pyc.mux -wire [15:0] pyc_mux_594; // op=pyc.mux -wire [15:0] pyc_mux_595; // op=pyc.mux -wire pyc_reg_29; // op=pyc.reg -wire pyc_reg_31; // op=pyc.reg -wire pyc_reg_33; // op=pyc.reg +wire pyc_extract_630; // op=pyc.extract +wire pyc_extract_634; // op=pyc.extract +wire pyc_extract_638; // op=pyc.extract +wire [4:0] pyc_extract_64; // op=pyc.extract +wire pyc_extract_642; // op=pyc.extract +wire pyc_extract_647; // op=pyc.extract +wire [3:0] pyc_extract_65; // op=pyc.extract +wire pyc_extract_654; // op=pyc.extract +wire pyc_extract_657; // op=pyc.extract +wire pyc_extract_661; // op=pyc.extract +wire pyc_extract_665; // op=pyc.extract +wire pyc_extract_67; // op=pyc.extract +wire pyc_extract_675; // op=pyc.extract +wire pyc_extract_677; // op=pyc.extract +wire pyc_extract_680; // op=pyc.extract +wire pyc_extract_683; // op=pyc.extract +wire pyc_extract_693; // op=pyc.extract +wire pyc_extract_696; // op=pyc.extract +wire pyc_extract_70; // op=pyc.extract +wire pyc_extract_700; // op=pyc.extract +wire pyc_extract_704; // op=pyc.extract +wire pyc_extract_708; // op=pyc.extract +wire pyc_extract_718; // op=pyc.extract +wire pyc_extract_720; // op=pyc.extract +wire pyc_extract_723; // op=pyc.extract +wire pyc_extract_726; // op=pyc.extract +wire pyc_extract_729; // op=pyc.extract +wire [4:0] pyc_extract_738; // op=pyc.extract +wire [4:0] pyc_extract_739; // op=pyc.extract +wire pyc_extract_74; // op=pyc.extract +wire [3:0] pyc_extract_740; // op=pyc.extract +wire [3:0] pyc_extract_741; // op=pyc.extract +wire [4:0] pyc_extract_744; // op=pyc.extract +wire [3:0] pyc_extract_745; // op=pyc.extract +wire [4:0] pyc_extract_746; // op=pyc.extract +wire [3:0] pyc_extract_747; // op=pyc.extract +wire pyc_extract_749; // op=pyc.extract +wire pyc_extract_752; // op=pyc.extract +wire pyc_extract_756; // op=pyc.extract +wire pyc_extract_760; // op=pyc.extract +wire pyc_extract_764; // op=pyc.extract +wire pyc_extract_768; // op=pyc.extract +wire pyc_extract_772; // op=pyc.extract +wire pyc_extract_776; // op=pyc.extract +wire pyc_extract_78; // op=pyc.extract +wire pyc_extract_781; // op=pyc.extract +wire pyc_extract_788; // op=pyc.extract +wire pyc_extract_791; // op=pyc.extract +wire pyc_extract_795; // op=pyc.extract +wire pyc_extract_799; // op=pyc.extract +wire pyc_extract_809; // op=pyc.extract +wire pyc_extract_811; // op=pyc.extract +wire pyc_extract_814; // op=pyc.extract +wire pyc_extract_817; // op=pyc.extract +wire pyc_extract_82; // op=pyc.extract +wire pyc_extract_827; // op=pyc.extract +wire pyc_extract_830; // op=pyc.extract +wire pyc_extract_834; // op=pyc.extract +wire pyc_extract_838; // op=pyc.extract +wire pyc_extract_842; // op=pyc.extract +wire pyc_extract_852; // op=pyc.extract +wire pyc_extract_854; // op=pyc.extract +wire pyc_extract_857; // op=pyc.extract +wire pyc_extract_86; // op=pyc.extract +wire pyc_extract_860; // op=pyc.extract +wire pyc_extract_863; // op=pyc.extract +wire [4:0] pyc_extract_872; // op=pyc.extract +wire [4:0] pyc_extract_873; // op=pyc.extract +wire [3:0] pyc_extract_874; // op=pyc.extract +wire [3:0] pyc_extract_875; // op=pyc.extract +wire [4:0] pyc_extract_878; // op=pyc.extract +wire [3:0] pyc_extract_879; // op=pyc.extract +wire [4:0] pyc_extract_880; // op=pyc.extract +wire [3:0] pyc_extract_881; // op=pyc.extract +wire pyc_extract_883; // op=pyc.extract +wire pyc_extract_886; // op=pyc.extract +wire pyc_extract_890; // op=pyc.extract +wire pyc_extract_894; // op=pyc.extract +wire pyc_extract_898; // op=pyc.extract +wire pyc_extract_90; // op=pyc.extract +wire pyc_extract_902; // op=pyc.extract +wire pyc_extract_906; // op=pyc.extract +wire pyc_extract_910; // op=pyc.extract +wire pyc_extract_915; // op=pyc.extract +wire pyc_extract_922; // op=pyc.extract +wire pyc_extract_925; // op=pyc.extract +wire pyc_extract_929; // op=pyc.extract +wire pyc_extract_933; // op=pyc.extract +wire pyc_extract_94; // op=pyc.extract +wire pyc_extract_943; // op=pyc.extract +wire pyc_extract_945; // op=pyc.extract +wire pyc_extract_948; // op=pyc.extract +wire pyc_extract_951; // op=pyc.extract +wire pyc_extract_961; // op=pyc.extract +wire pyc_extract_964; // op=pyc.extract +wire pyc_extract_968; // op=pyc.extract +wire pyc_extract_972; // op=pyc.extract +wire pyc_extract_976; // op=pyc.extract +wire pyc_extract_986; // op=pyc.extract +wire pyc_extract_988; // op=pyc.extract +wire pyc_extract_99; // op=pyc.extract +wire pyc_extract_991; // op=pyc.extract +wire pyc_extract_994; // op=pyc.extract +wire pyc_extract_997; // op=pyc.extract +wire [18:0] pyc_instance_2044; // op=pyc.instance +wire [18:0] pyc_instance_2062; // op=pyc.instance +wire [15:0] pyc_instance_2080; // op=pyc.instance +wire [18:0] pyc_instance_2098; // op=pyc.instance +wire [15:0] pyc_instance_2116; // op=pyc.instance +wire [18:0] pyc_instance_2134; // op=pyc.instance +wire [18:0] pyc_instance_2152; // op=pyc.instance +wire [15:0] pyc_instance_2170; // op=pyc.instance +wire [15:0] pyc_instance_2188; // op=pyc.instance +wire [12:0] pyc_mux_1000; // op=pyc.mux +wire [12:0] pyc_mux_1003; // op=pyc.mux +wire [15:0] pyc_mux_1018; // op=pyc.mux +wire [15:0] pyc_mux_102; // op=pyc.mux +wire [15:0] pyc_mux_1021; // op=pyc.mux +wire [15:0] pyc_mux_1025; // op=pyc.mux +wire [15:0] pyc_mux_1029; // op=pyc.mux +wire [15:0] pyc_mux_1033; // op=pyc.mux +wire [15:0] pyc_mux_1037; // op=pyc.mux +wire [15:0] pyc_mux_1041; // op=pyc.mux +wire [15:0] pyc_mux_1045; // op=pyc.mux +wire [15:0] pyc_mux_1048; // op=pyc.mux +wire [15:0] pyc_mux_1052; // op=pyc.mux +wire [11:0] pyc_mux_1057; // op=pyc.mux +wire [11:0] pyc_mux_1060; // op=pyc.mux +wire [11:0] pyc_mux_1064; // op=pyc.mux +wire [11:0] pyc_mux_1068; // op=pyc.mux +wire [11:0] pyc_mux_107; // op=pyc.mux +wire [11:0] pyc_mux_1071; // op=pyc.mux +wire [11:0] pyc_mux_1074; // op=pyc.mux +wire [11:0] pyc_mux_1078; // op=pyc.mux +wire [11:0] pyc_mux_1080; // op=pyc.mux +wire [11:0] pyc_mux_1083; // op=pyc.mux +wire [11:0] pyc_mux_1086; // op=pyc.mux +wire [11:0] pyc_mux_1088; // op=pyc.mux +wire [11:0] pyc_mux_1091; // op=pyc.mux +wire [12:0] pyc_mux_1096; // op=pyc.mux +wire [12:0] pyc_mux_1099; // op=pyc.mux +wire [11:0] pyc_mux_110; // op=pyc.mux +wire [12:0] pyc_mux_1103; // op=pyc.mux +wire [12:0] pyc_mux_1107; // op=pyc.mux +wire [12:0] pyc_mux_1111; // op=pyc.mux +wire [12:0] pyc_mux_1114; // op=pyc.mux +wire [12:0] pyc_mux_1117; // op=pyc.mux +wire [12:0] pyc_mux_1121; // op=pyc.mux +wire [12:0] pyc_mux_1123; // op=pyc.mux +wire [12:0] pyc_mux_1126; // op=pyc.mux +wire [12:0] pyc_mux_1129; // op=pyc.mux +wire [12:0] pyc_mux_1132; // op=pyc.mux +wire [12:0] pyc_mux_1134; // op=pyc.mux +wire [12:0] pyc_mux_1137; // op=pyc.mux +wire [11:0] pyc_mux_114; // op=pyc.mux +wire [9:0] pyc_mux_1143; // op=pyc.mux +wire [9:0] pyc_mux_1146; // op=pyc.mux +wire [9:0] pyc_mux_1150; // op=pyc.mux +wire [9:0] pyc_mux_1154; // op=pyc.mux +wire [9:0] pyc_mux_1158; // op=pyc.mux +wire [9:0] pyc_mux_1161; // op=pyc.mux +wire [9:0] pyc_mux_1165; // op=pyc.mux +wire [9:0] pyc_mux_1169; // op=pyc.mux +wire [9:0] pyc_mux_1171; // op=pyc.mux +wire [9:0] pyc_mux_1174; // op=pyc.mux +wire [9:0] pyc_mux_1177; // op=pyc.mux +wire [11:0] pyc_mux_118; // op=pyc.mux +wire [9:0] pyc_mux_1180; // op=pyc.mux +wire [9:0] pyc_mux_1182; // op=pyc.mux +wire [9:0] pyc_mux_1185; // op=pyc.mux +wire [9:0] pyc_mux_1191; // op=pyc.mux +wire [9:0] pyc_mux_1194; // op=pyc.mux +wire [9:0] pyc_mux_1198; // op=pyc.mux +wire [9:0] pyc_mux_1202; // op=pyc.mux +wire [9:0] pyc_mux_1206; // op=pyc.mux +wire [9:0] pyc_mux_1209; // op=pyc.mux +wire [11:0] pyc_mux_121; // op=pyc.mux +wire [9:0] pyc_mux_1213; // op=pyc.mux +wire [9:0] pyc_mux_1217; // op=pyc.mux +wire [9:0] pyc_mux_1219; // op=pyc.mux +wire [9:0] pyc_mux_1222; // op=pyc.mux +wire [9:0] pyc_mux_1225; // op=pyc.mux +wire [9:0] pyc_mux_1228; // op=pyc.mux +wire [9:0] pyc_mux_1230; // op=pyc.mux +wire [9:0] pyc_mux_1233; // op=pyc.mux +wire [9:0] pyc_mux_1239; // op=pyc.mux +wire [11:0] pyc_mux_124; // op=pyc.mux +wire [9:0] pyc_mux_1242; // op=pyc.mux +wire [9:0] pyc_mux_1246; // op=pyc.mux +wire [9:0] pyc_mux_1250; // op=pyc.mux +wire [9:0] pyc_mux_1254; // op=pyc.mux +wire [9:0] pyc_mux_1257; // op=pyc.mux +wire [9:0] pyc_mux_1261; // op=pyc.mux +wire [9:0] pyc_mux_1265; // op=pyc.mux +wire [9:0] pyc_mux_1267; // op=pyc.mux +wire [9:0] pyc_mux_1270; // op=pyc.mux +wire [9:0] pyc_mux_1273; // op=pyc.mux +wire [9:0] pyc_mux_1276; // op=pyc.mux +wire [9:0] pyc_mux_1278; // op=pyc.mux +wire [11:0] pyc_mux_128; // op=pyc.mux +wire [9:0] pyc_mux_1281; // op=pyc.mux +wire [9:0] pyc_mux_1287; // op=pyc.mux +wire [9:0] pyc_mux_1290; // op=pyc.mux +wire [9:0] pyc_mux_1294; // op=pyc.mux +wire [9:0] pyc_mux_1298; // op=pyc.mux +wire [11:0] pyc_mux_130; // op=pyc.mux +wire [9:0] pyc_mux_1302; // op=pyc.mux +wire [9:0] pyc_mux_1305; // op=pyc.mux +wire [9:0] pyc_mux_1309; // op=pyc.mux +wire [9:0] pyc_mux_1313; // op=pyc.mux +wire [9:0] pyc_mux_1315; // op=pyc.mux +wire [9:0] pyc_mux_1318; // op=pyc.mux +wire [9:0] pyc_mux_1321; // op=pyc.mux +wire [9:0] pyc_mux_1324; // op=pyc.mux +wire [9:0] pyc_mux_1326; // op=pyc.mux +wire [9:0] pyc_mux_1329; // op=pyc.mux +wire [11:0] pyc_mux_133; // op=pyc.mux +wire [9:0] pyc_mux_1335; // op=pyc.mux +wire [9:0] pyc_mux_1338; // op=pyc.mux +wire [9:0] pyc_mux_1342; // op=pyc.mux +wire [9:0] pyc_mux_1346; // op=pyc.mux +wire [9:0] pyc_mux_1350; // op=pyc.mux +wire [9:0] pyc_mux_1353; // op=pyc.mux +wire [9:0] pyc_mux_1357; // op=pyc.mux +wire [11:0] pyc_mux_136; // op=pyc.mux +wire [9:0] pyc_mux_1361; // op=pyc.mux +wire [9:0] pyc_mux_1363; // op=pyc.mux +wire [9:0] pyc_mux_1366; // op=pyc.mux +wire [9:0] pyc_mux_1369; // op=pyc.mux +wire [9:0] pyc_mux_1372; // op=pyc.mux +wire [9:0] pyc_mux_1374; // op=pyc.mux +wire [9:0] pyc_mux_1377; // op=pyc.mux +wire [11:0] pyc_mux_138; // op=pyc.mux +wire [9:0] pyc_mux_1383; // op=pyc.mux +wire [9:0] pyc_mux_1386; // op=pyc.mux +wire [9:0] pyc_mux_1390; // op=pyc.mux +wire [9:0] pyc_mux_1394; // op=pyc.mux +wire [9:0] pyc_mux_1398; // op=pyc.mux +wire [9:0] pyc_mux_1401; // op=pyc.mux +wire [9:0] pyc_mux_1405; // op=pyc.mux +wire [9:0] pyc_mux_1409; // op=pyc.mux +wire [11:0] pyc_mux_141; // op=pyc.mux +wire [9:0] pyc_mux_1411; // op=pyc.mux +wire [9:0] pyc_mux_1414; // op=pyc.mux +wire [9:0] pyc_mux_1417; // op=pyc.mux +wire [9:0] pyc_mux_1420; // op=pyc.mux +wire [9:0] pyc_mux_1422; // op=pyc.mux +wire [9:0] pyc_mux_1425; // op=pyc.mux +wire [9:0] pyc_mux_1431; // op=pyc.mux +wire [9:0] pyc_mux_1434; // op=pyc.mux +wire [9:0] pyc_mux_1438; // op=pyc.mux +wire [9:0] pyc_mux_1442; // op=pyc.mux +wire [9:0] pyc_mux_1446; // op=pyc.mux +wire [9:0] pyc_mux_1449; // op=pyc.mux +wire [9:0] pyc_mux_1453; // op=pyc.mux +wire [9:0] pyc_mux_1457; // op=pyc.mux +wire [9:0] pyc_mux_1459; // op=pyc.mux +wire [12:0] pyc_mux_146; // op=pyc.mux +wire [9:0] pyc_mux_1462; // op=pyc.mux +wire [9:0] pyc_mux_1465; // op=pyc.mux +wire [9:0] pyc_mux_1468; // op=pyc.mux +wire [9:0] pyc_mux_1470; // op=pyc.mux +wire [9:0] pyc_mux_1473; // op=pyc.mux +wire [9:0] pyc_mux_1479; // op=pyc.mux +wire [9:0] pyc_mux_1482; // op=pyc.mux +wire [9:0] pyc_mux_1486; // op=pyc.mux +wire [12:0] pyc_mux_149; // op=pyc.mux +wire [9:0] pyc_mux_1490; // op=pyc.mux +wire [9:0] pyc_mux_1494; // op=pyc.mux +wire [9:0] pyc_mux_1497; // op=pyc.mux +wire [9:0] pyc_mux_1501; // op=pyc.mux +wire [9:0] pyc_mux_1505; // op=pyc.mux +wire [9:0] pyc_mux_1507; // op=pyc.mux +wire [9:0] pyc_mux_1510; // op=pyc.mux +wire [9:0] pyc_mux_1513; // op=pyc.mux +wire [9:0] pyc_mux_1516; // op=pyc.mux +wire [9:0] pyc_mux_1518; // op=pyc.mux +wire [9:0] pyc_mux_1521; // op=pyc.mux +wire [9:0] pyc_mux_1526; // op=pyc.mux +wire [9:0] pyc_mux_1528; // op=pyc.mux +wire [12:0] pyc_mux_153; // op=pyc.mux +wire [9:0] pyc_mux_1531; // op=pyc.mux +wire [9:0] pyc_mux_1534; // op=pyc.mux +wire [9:0] pyc_mux_1537; // op=pyc.mux +wire [9:0] pyc_mux_1540; // op=pyc.mux +wire [9:0] pyc_mux_1544; // op=pyc.mux +wire [9:0] pyc_mux_1548; // op=pyc.mux +wire [9:0] pyc_mux_1550; // op=pyc.mux +wire [9:0] pyc_mux_1553; // op=pyc.mux +wire [9:0] pyc_mux_1556; // op=pyc.mux +wire [9:0] pyc_mux_1559; // op=pyc.mux +wire [9:0] pyc_mux_1561; // op=pyc.mux +wire [9:0] pyc_mux_1564; // op=pyc.mux +wire [9:0] pyc_mux_1569; // op=pyc.mux +wire [12:0] pyc_mux_157; // op=pyc.mux +wire [9:0] pyc_mux_1571; // op=pyc.mux +wire [9:0] pyc_mux_1574; // op=pyc.mux +wire [9:0] pyc_mux_1577; // op=pyc.mux +wire [9:0] pyc_mux_1580; // op=pyc.mux +wire [9:0] pyc_mux_1583; // op=pyc.mux +wire [9:0] pyc_mux_1587; // op=pyc.mux +wire [9:0] pyc_mux_1591; // op=pyc.mux +wire [9:0] pyc_mux_1593; // op=pyc.mux +wire [9:0] pyc_mux_1596; // op=pyc.mux +wire [9:0] pyc_mux_1599; // op=pyc.mux +wire [9:0] pyc_mux_1602; // op=pyc.mux +wire [9:0] pyc_mux_1604; // op=pyc.mux +wire [9:0] pyc_mux_1607; // op=pyc.mux +wire [12:0] pyc_mux_161; // op=pyc.mux +wire [9:0] pyc_mux_1612; // op=pyc.mux +wire [9:0] pyc_mux_1614; // op=pyc.mux +wire [9:0] pyc_mux_1617; // op=pyc.mux +wire [9:0] pyc_mux_1620; // op=pyc.mux +wire [9:0] pyc_mux_1623; // op=pyc.mux +wire [9:0] pyc_mux_1626; // op=pyc.mux +wire [9:0] pyc_mux_1630; // op=pyc.mux +wire [9:0] pyc_mux_1634; // op=pyc.mux +wire [9:0] pyc_mux_1636; // op=pyc.mux +wire [9:0] pyc_mux_1639; // op=pyc.mux +wire [12:0] pyc_mux_164; // op=pyc.mux +wire [9:0] pyc_mux_1642; // op=pyc.mux +wire [9:0] pyc_mux_1645; // op=pyc.mux +wire [9:0] pyc_mux_1647; // op=pyc.mux +wire [9:0] pyc_mux_1650; // op=pyc.mux +wire [9:0] pyc_mux_1655; // op=pyc.mux +wire [9:0] pyc_mux_1657; // op=pyc.mux +wire [9:0] pyc_mux_1660; // op=pyc.mux +wire [9:0] pyc_mux_1663; // op=pyc.mux +wire [9:0] pyc_mux_1666; // op=pyc.mux +wire [9:0] pyc_mux_1669; // op=pyc.mux +wire [12:0] pyc_mux_167; // op=pyc.mux +wire [9:0] pyc_mux_1673; // op=pyc.mux +wire [9:0] pyc_mux_1677; // op=pyc.mux +wire [9:0] pyc_mux_1679; // op=pyc.mux +wire [9:0] pyc_mux_1682; // op=pyc.mux +wire [9:0] pyc_mux_1685; // op=pyc.mux +wire [9:0] pyc_mux_1688; // op=pyc.mux +wire [9:0] pyc_mux_1690; // op=pyc.mux +wire [9:0] pyc_mux_1693; // op=pyc.mux +wire [9:0] pyc_mux_1698; // op=pyc.mux +wire [9:0] pyc_mux_1700; // op=pyc.mux +wire [9:0] pyc_mux_1703; // op=pyc.mux +wire [9:0] pyc_mux_1706; // op=pyc.mux +wire [9:0] pyc_mux_1709; // op=pyc.mux +wire [12:0] pyc_mux_171; // op=pyc.mux +wire [9:0] pyc_mux_1712; // op=pyc.mux +wire [9:0] pyc_mux_1716; // op=pyc.mux +wire [9:0] pyc_mux_1720; // op=pyc.mux +wire [9:0] pyc_mux_1722; // op=pyc.mux +wire [9:0] pyc_mux_1725; // op=pyc.mux +wire [9:0] pyc_mux_1728; // op=pyc.mux +wire [12:0] pyc_mux_173; // op=pyc.mux +wire [9:0] pyc_mux_1731; // op=pyc.mux +wire [9:0] pyc_mux_1733; // op=pyc.mux +wire [9:0] pyc_mux_1736; // op=pyc.mux +wire [9:0] pyc_mux_1741; // op=pyc.mux +wire [9:0] pyc_mux_1743; // op=pyc.mux +wire [9:0] pyc_mux_1746; // op=pyc.mux +wire [9:0] pyc_mux_1749; // op=pyc.mux +wire [9:0] pyc_mux_1752; // op=pyc.mux +wire [9:0] pyc_mux_1755; // op=pyc.mux +wire [9:0] pyc_mux_1759; // op=pyc.mux +wire [12:0] pyc_mux_176; // op=pyc.mux +wire [9:0] pyc_mux_1763; // op=pyc.mux +wire [9:0] pyc_mux_1765; // op=pyc.mux +wire [9:0] pyc_mux_1768; // op=pyc.mux +wire [9:0] pyc_mux_1771; // op=pyc.mux +wire [9:0] pyc_mux_1774; // op=pyc.mux +wire [9:0] pyc_mux_1776; // op=pyc.mux +wire [9:0] pyc_mux_1779; // op=pyc.mux +wire [9:0] pyc_mux_1784; // op=pyc.mux +wire [9:0] pyc_mux_1786; // op=pyc.mux +wire [9:0] pyc_mux_1789; // op=pyc.mux +wire [12:0] pyc_mux_179; // op=pyc.mux +wire [9:0] pyc_mux_1792; // op=pyc.mux +wire [9:0] pyc_mux_1795; // op=pyc.mux +wire [9:0] pyc_mux_1798; // op=pyc.mux +wire [9:0] pyc_mux_1802; // op=pyc.mux +wire [9:0] pyc_mux_1806; // op=pyc.mux +wire [9:0] pyc_mux_1808; // op=pyc.mux +wire [9:0] pyc_mux_1811; // op=pyc.mux +wire [9:0] pyc_mux_1814; // op=pyc.mux +wire [9:0] pyc_mux_1817; // op=pyc.mux +wire [9:0] pyc_mux_1819; // op=pyc.mux +wire [12:0] pyc_mux_182; // op=pyc.mux +wire [9:0] pyc_mux_1822; // op=pyc.mux +wire [9:0] pyc_mux_1827; // op=pyc.mux +wire [9:0] pyc_mux_1829; // op=pyc.mux +wire [9:0] pyc_mux_1832; // op=pyc.mux +wire [9:0] pyc_mux_1835; // op=pyc.mux +wire [9:0] pyc_mux_1838; // op=pyc.mux +wire [12:0] pyc_mux_184; // op=pyc.mux +wire [9:0] pyc_mux_1841; // op=pyc.mux +wire [9:0] pyc_mux_1845; // op=pyc.mux +wire [9:0] pyc_mux_1849; // op=pyc.mux +wire [9:0] pyc_mux_1851; // op=pyc.mux +wire [9:0] pyc_mux_1854; // op=pyc.mux +wire [9:0] pyc_mux_1857; // op=pyc.mux +wire [9:0] pyc_mux_1860; // op=pyc.mux +wire [9:0] pyc_mux_1862; // op=pyc.mux +wire [9:0] pyc_mux_1865; // op=pyc.mux +wire [12:0] pyc_mux_187; // op=pyc.mux +wire [15:0] pyc_mux_206; // op=pyc.mux +wire [15:0] pyc_mux_209; // op=pyc.mux +wire [15:0] pyc_mux_213; // op=pyc.mux +wire [15:0] pyc_mux_217; // op=pyc.mux +wire [15:0] pyc_mux_221; // op=pyc.mux +wire [18:0] pyc_mux_2229; // op=pyc.mux +wire [18:0] pyc_mux_2230; // op=pyc.mux +wire [18:0] pyc_mux_2235; // op=pyc.mux +wire [18:0] pyc_mux_2236; // op=pyc.mux +wire [15:0] pyc_mux_225; // op=pyc.mux +wire [15:0] pyc_mux_229; // op=pyc.mux +wire [15:0] pyc_mux_233; // op=pyc.mux +wire [15:0] pyc_mux_236; // op=pyc.mux +wire [15:0] pyc_mux_240; // op=pyc.mux +wire [15:0] pyc_mux_2411; // op=pyc.mux +wire [15:0] pyc_mux_2412; // op=pyc.mux +wire [15:0] pyc_mux_2417; // op=pyc.mux +wire [15:0] pyc_mux_2418; // op=pyc.mux +wire [11:0] pyc_mux_245; // op=pyc.mux +wire [11:0] pyc_mux_248; // op=pyc.mux +wire [11:0] pyc_mux_252; // op=pyc.mux +wire [18:0] pyc_mux_2550; // op=pyc.mux +wire [18:0] pyc_mux_2551; // op=pyc.mux +wire [18:0] pyc_mux_2553; // op=pyc.mux +wire [15:0] pyc_mux_2554; // op=pyc.mux +wire [15:0] pyc_mux_2555; // op=pyc.mux +wire [15:0] pyc_mux_2556; // op=pyc.mux +wire [11:0] pyc_mux_256; // op=pyc.mux +wire [15:0] pyc_mux_2560; // op=pyc.mux +wire [15:0] pyc_mux_2561; // op=pyc.mux +wire [11:0] pyc_mux_259; // op=pyc.mux +wire [11:0] pyc_mux_262; // op=pyc.mux +wire [11:0] pyc_mux_266; // op=pyc.mux +wire [11:0] pyc_mux_268; // op=pyc.mux +wire [11:0] pyc_mux_271; // op=pyc.mux +wire [11:0] pyc_mux_274; // op=pyc.mux +wire [11:0] pyc_mux_276; // op=pyc.mux +wire [11:0] pyc_mux_279; // op=pyc.mux +wire [12:0] pyc_mux_284; // op=pyc.mux +wire [12:0] pyc_mux_287; // op=pyc.mux +wire [12:0] pyc_mux_291; // op=pyc.mux +wire [12:0] pyc_mux_295; // op=pyc.mux +wire [12:0] pyc_mux_299; // op=pyc.mux +wire [12:0] pyc_mux_302; // op=pyc.mux +wire [12:0] pyc_mux_305; // op=pyc.mux +wire [12:0] pyc_mux_309; // op=pyc.mux +wire [12:0] pyc_mux_311; // op=pyc.mux +wire [12:0] pyc_mux_314; // op=pyc.mux +wire [12:0] pyc_mux_317; // op=pyc.mux +wire [12:0] pyc_mux_320; // op=pyc.mux +wire [12:0] pyc_mux_322; // op=pyc.mux +wire [12:0] pyc_mux_325; // op=pyc.mux +wire [15:0] pyc_mux_344; // op=pyc.mux +wire [15:0] pyc_mux_347; // op=pyc.mux +wire [15:0] pyc_mux_351; // op=pyc.mux +wire [15:0] pyc_mux_355; // op=pyc.mux +wire [15:0] pyc_mux_359; // op=pyc.mux +wire [15:0] pyc_mux_363; // op=pyc.mux +wire [15:0] pyc_mux_367; // op=pyc.mux +wire [15:0] pyc_mux_371; // op=pyc.mux +wire [15:0] pyc_mux_374; // op=pyc.mux +wire [15:0] pyc_mux_378; // op=pyc.mux +wire [11:0] pyc_mux_383; // op=pyc.mux +wire [11:0] pyc_mux_386; // op=pyc.mux +wire [11:0] pyc_mux_390; // op=pyc.mux +wire [11:0] pyc_mux_394; // op=pyc.mux +wire [11:0] pyc_mux_397; // op=pyc.mux +wire [11:0] pyc_mux_400; // op=pyc.mux +wire [11:0] pyc_mux_404; // op=pyc.mux +wire [11:0] pyc_mux_406; // op=pyc.mux +wire [11:0] pyc_mux_409; // op=pyc.mux +wire [11:0] pyc_mux_412; // op=pyc.mux +wire [11:0] pyc_mux_414; // op=pyc.mux +wire [11:0] pyc_mux_417; // op=pyc.mux +wire [12:0] pyc_mux_422; // op=pyc.mux +wire [12:0] pyc_mux_425; // op=pyc.mux +wire [12:0] pyc_mux_429; // op=pyc.mux +wire [12:0] pyc_mux_433; // op=pyc.mux +wire [12:0] pyc_mux_437; // op=pyc.mux +wire [12:0] pyc_mux_440; // op=pyc.mux +wire [12:0] pyc_mux_443; // op=pyc.mux +wire [12:0] pyc_mux_447; // op=pyc.mux +wire [12:0] pyc_mux_449; // op=pyc.mux +wire [12:0] pyc_mux_452; // op=pyc.mux +wire [12:0] pyc_mux_455; // op=pyc.mux +wire [12:0] pyc_mux_458; // op=pyc.mux +wire [12:0] pyc_mux_460; // op=pyc.mux +wire [12:0] pyc_mux_463; // op=pyc.mux +wire [15:0] pyc_mux_482; // op=pyc.mux +wire [15:0] pyc_mux_485; // op=pyc.mux +wire [15:0] pyc_mux_489; // op=pyc.mux +wire [15:0] pyc_mux_493; // op=pyc.mux +wire [15:0] pyc_mux_497; // op=pyc.mux +wire [15:0] pyc_mux_501; // op=pyc.mux +wire [15:0] pyc_mux_505; // op=pyc.mux +wire [15:0] pyc_mux_509; // op=pyc.mux +wire [15:0] pyc_mux_512; // op=pyc.mux +wire [15:0] pyc_mux_516; // op=pyc.mux +wire [11:0] pyc_mux_521; // op=pyc.mux +wire [11:0] pyc_mux_524; // op=pyc.mux +wire [11:0] pyc_mux_528; // op=pyc.mux +wire [11:0] pyc_mux_532; // op=pyc.mux +wire [11:0] pyc_mux_535; // op=pyc.mux +wire [11:0] pyc_mux_538; // op=pyc.mux +wire [11:0] pyc_mux_542; // op=pyc.mux +wire [11:0] pyc_mux_544; // op=pyc.mux +wire [11:0] pyc_mux_547; // op=pyc.mux +wire [11:0] pyc_mux_550; // op=pyc.mux +wire [11:0] pyc_mux_552; // op=pyc.mux +wire [11:0] pyc_mux_555; // op=pyc.mux +wire [12:0] pyc_mux_560; // op=pyc.mux +wire [12:0] pyc_mux_563; // op=pyc.mux +wire [12:0] pyc_mux_567; // op=pyc.mux +wire [12:0] pyc_mux_571; // op=pyc.mux +wire [12:0] pyc_mux_575; // op=pyc.mux +wire [12:0] pyc_mux_578; // op=pyc.mux +wire [12:0] pyc_mux_581; // op=pyc.mux +wire [12:0] pyc_mux_585; // op=pyc.mux +wire [12:0] pyc_mux_587; // op=pyc.mux +wire [12:0] pyc_mux_590; // op=pyc.mux +wire [12:0] pyc_mux_593; // op=pyc.mux +wire [12:0] pyc_mux_596; // op=pyc.mux +wire [12:0] pyc_mux_598; // op=pyc.mux +wire [12:0] pyc_mux_601; // op=pyc.mux +wire [15:0] pyc_mux_616; // op=pyc.mux +wire [15:0] pyc_mux_619; // op=pyc.mux +wire [15:0] pyc_mux_623; // op=pyc.mux +wire [15:0] pyc_mux_627; // op=pyc.mux +wire [15:0] pyc_mux_631; // op=pyc.mux +wire [15:0] pyc_mux_635; // op=pyc.mux +wire [15:0] pyc_mux_639; // op=pyc.mux +wire [15:0] pyc_mux_643; // op=pyc.mux +wire [15:0] pyc_mux_646; // op=pyc.mux +wire [15:0] pyc_mux_650; // op=pyc.mux +wire [11:0] pyc_mux_655; // op=pyc.mux +wire [11:0] pyc_mux_658; // op=pyc.mux +wire [11:0] pyc_mux_662; // op=pyc.mux +wire [11:0] pyc_mux_666; // op=pyc.mux +wire [11:0] pyc_mux_669; // op=pyc.mux +wire [11:0] pyc_mux_672; // op=pyc.mux +wire [11:0] pyc_mux_676; // op=pyc.mux +wire [11:0] pyc_mux_678; // op=pyc.mux +wire [15:0] pyc_mux_68; // op=pyc.mux +wire [11:0] pyc_mux_681; // op=pyc.mux +wire [11:0] pyc_mux_684; // op=pyc.mux +wire [11:0] pyc_mux_686; // op=pyc.mux +wire [11:0] pyc_mux_689; // op=pyc.mux +wire [12:0] pyc_mux_694; // op=pyc.mux +wire [12:0] pyc_mux_697; // op=pyc.mux +wire [12:0] pyc_mux_701; // op=pyc.mux +wire [12:0] pyc_mux_705; // op=pyc.mux +wire [12:0] pyc_mux_709; // op=pyc.mux +wire [15:0] pyc_mux_71; // op=pyc.mux +wire [12:0] pyc_mux_712; // op=pyc.mux +wire [12:0] pyc_mux_715; // op=pyc.mux +wire [12:0] pyc_mux_719; // op=pyc.mux +wire [12:0] pyc_mux_721; // op=pyc.mux +wire [12:0] pyc_mux_724; // op=pyc.mux +wire [12:0] pyc_mux_727; // op=pyc.mux +wire [12:0] pyc_mux_730; // op=pyc.mux +wire [12:0] pyc_mux_732; // op=pyc.mux +wire [12:0] pyc_mux_735; // op=pyc.mux +wire [15:0] pyc_mux_75; // op=pyc.mux +wire [15:0] pyc_mux_750; // op=pyc.mux +wire [15:0] pyc_mux_753; // op=pyc.mux +wire [15:0] pyc_mux_757; // op=pyc.mux +wire [15:0] pyc_mux_761; // op=pyc.mux +wire [15:0] pyc_mux_765; // op=pyc.mux +wire [15:0] pyc_mux_769; // op=pyc.mux +wire [15:0] pyc_mux_773; // op=pyc.mux +wire [15:0] pyc_mux_777; // op=pyc.mux +wire [15:0] pyc_mux_780; // op=pyc.mux +wire [15:0] pyc_mux_784; // op=pyc.mux +wire [11:0] pyc_mux_789; // op=pyc.mux +wire [15:0] pyc_mux_79; // op=pyc.mux +wire [11:0] pyc_mux_792; // op=pyc.mux +wire [11:0] pyc_mux_796; // op=pyc.mux +wire [11:0] pyc_mux_800; // op=pyc.mux +wire [11:0] pyc_mux_803; // op=pyc.mux +wire [11:0] pyc_mux_806; // op=pyc.mux +wire [11:0] pyc_mux_810; // op=pyc.mux +wire [11:0] pyc_mux_812; // op=pyc.mux +wire [11:0] pyc_mux_815; // op=pyc.mux +wire [11:0] pyc_mux_818; // op=pyc.mux +wire [11:0] pyc_mux_820; // op=pyc.mux +wire [11:0] pyc_mux_823; // op=pyc.mux +wire [12:0] pyc_mux_828; // op=pyc.mux +wire [15:0] pyc_mux_83; // op=pyc.mux +wire [12:0] pyc_mux_831; // op=pyc.mux +wire [12:0] pyc_mux_835; // op=pyc.mux +wire [12:0] pyc_mux_839; // op=pyc.mux +wire [12:0] pyc_mux_843; // op=pyc.mux +wire [12:0] pyc_mux_846; // op=pyc.mux +wire [12:0] pyc_mux_849; // op=pyc.mux +wire [12:0] pyc_mux_853; // op=pyc.mux +wire [12:0] pyc_mux_855; // op=pyc.mux +wire [12:0] pyc_mux_858; // op=pyc.mux +wire [12:0] pyc_mux_861; // op=pyc.mux +wire [12:0] pyc_mux_864; // op=pyc.mux +wire [12:0] pyc_mux_866; // op=pyc.mux +wire [12:0] pyc_mux_869; // op=pyc.mux +wire [15:0] pyc_mux_87; // op=pyc.mux +wire [15:0] pyc_mux_884; // op=pyc.mux +wire [15:0] pyc_mux_887; // op=pyc.mux +wire [15:0] pyc_mux_891; // op=pyc.mux +wire [15:0] pyc_mux_895; // op=pyc.mux +wire [15:0] pyc_mux_899; // op=pyc.mux +wire [15:0] pyc_mux_903; // op=pyc.mux +wire [15:0] pyc_mux_907; // op=pyc.mux +wire [15:0] pyc_mux_91; // op=pyc.mux +wire [15:0] pyc_mux_911; // op=pyc.mux +wire [15:0] pyc_mux_914; // op=pyc.mux +wire [15:0] pyc_mux_918; // op=pyc.mux +wire [11:0] pyc_mux_923; // op=pyc.mux +wire [11:0] pyc_mux_926; // op=pyc.mux +wire [11:0] pyc_mux_930; // op=pyc.mux +wire [11:0] pyc_mux_934; // op=pyc.mux +wire [11:0] pyc_mux_937; // op=pyc.mux +wire [11:0] pyc_mux_940; // op=pyc.mux +wire [11:0] pyc_mux_944; // op=pyc.mux +wire [11:0] pyc_mux_946; // op=pyc.mux +wire [11:0] pyc_mux_949; // op=pyc.mux +wire [15:0] pyc_mux_95; // op=pyc.mux +wire [11:0] pyc_mux_952; // op=pyc.mux +wire [11:0] pyc_mux_954; // op=pyc.mux +wire [11:0] pyc_mux_957; // op=pyc.mux +wire [12:0] pyc_mux_962; // op=pyc.mux +wire [12:0] pyc_mux_965; // op=pyc.mux +wire [12:0] pyc_mux_969; // op=pyc.mux +wire [12:0] pyc_mux_973; // op=pyc.mux +wire [12:0] pyc_mux_977; // op=pyc.mux +wire [15:0] pyc_mux_98; // op=pyc.mux +wire [12:0] pyc_mux_980; // op=pyc.mux +wire [12:0] pyc_mux_983; // op=pyc.mux +wire [12:0] pyc_mux_987; // op=pyc.mux +wire [12:0] pyc_mux_989; // op=pyc.mux +wire [12:0] pyc_mux_992; // op=pyc.mux +wire [12:0] pyc_mux_995; // op=pyc.mux +wire [12:0] pyc_mux_998; // op=pyc.mux +wire pyc_or_2313; // op=pyc.or +wire pyc_or_2315; // op=pyc.or +wire pyc_or_2318; // op=pyc.or +wire pyc_or_2321; // op=pyc.or +wire pyc_or_2324; // op=pyc.or +wire pyc_or_2327; // op=pyc.or +wire pyc_or_2330; // op=pyc.or +wire pyc_or_2333; // op=pyc.or +wire pyc_or_2336; // op=pyc.or +wire pyc_or_2339; // op=pyc.or +wire pyc_or_2341; // op=pyc.or +wire pyc_or_2344; // op=pyc.or +wire pyc_or_2347; // op=pyc.or +wire pyc_or_2350; // op=pyc.or +wire pyc_or_2352; // op=pyc.or +wire pyc_or_2355; // op=pyc.or +wire pyc_or_2357; // op=pyc.or +wire pyc_or_2359; // op=pyc.or +wire pyc_or_2361; // op=pyc.or +wire pyc_or_2363; // op=pyc.or +wire pyc_or_2365; // op=pyc.or +wire pyc_or_2367; // op=pyc.or +wire pyc_or_2369; // op=pyc.or +wire pyc_or_2371; // op=pyc.or +wire pyc_or_2373; // op=pyc.or +wire pyc_or_2375; // op=pyc.or +wire pyc_or_2377; // op=pyc.or +wire pyc_or_2379; // op=pyc.or +wire pyc_or_2381; // op=pyc.or +wire pyc_or_2483; // op=pyc.or +wire pyc_or_2485; // op=pyc.or +wire pyc_or_2488; // op=pyc.or +wire pyc_or_2491; // op=pyc.or +wire pyc_or_2494; // op=pyc.or +wire pyc_or_2497; // op=pyc.or +wire pyc_or_2500; // op=pyc.or +wire pyc_or_2503; // op=pyc.or +wire pyc_or_2505; // op=pyc.or +wire pyc_or_2508; // op=pyc.or +wire pyc_or_2511; // op=pyc.or +wire pyc_or_2513; // op=pyc.or +wire pyc_or_2515; // op=pyc.or +wire pyc_or_2517; // op=pyc.or +wire pyc_or_2519; // op=pyc.or +wire pyc_or_2521; // op=pyc.or +wire pyc_or_2523; // op=pyc.or +wire pyc_or_2525; // op=pyc.or +wire pyc_or_2527; // op=pyc.or +wire pyc_or_2529; // op=pyc.or +wire pyc_or_2531; // op=pyc.or +wire pyc_or_2533; // op=pyc.or +wire pyc_or_2552; // op=pyc.or +wire pyc_reg_1941; // op=pyc.reg +wire pyc_reg_1943; // op=pyc.reg +wire pyc_reg_1945; // op=pyc.reg +wire pyc_reg_1947; // op=pyc.reg +wire [1:0] pyc_reg_1949; // op=pyc.reg +wire [1:0] pyc_reg_1951; // op=pyc.reg +wire [1:0] pyc_reg_1953; // op=pyc.reg +wire [15:0] pyc_reg_1955; // op=pyc.reg +wire [15:0] pyc_reg_1956; // op=pyc.reg +wire [15:0] pyc_reg_1957; // op=pyc.reg +wire [15:0] pyc_reg_1958; // op=pyc.reg +wire [15:0] pyc_reg_1959; // op=pyc.reg +wire [15:0] pyc_reg_1960; // op=pyc.reg +wire [15:0] pyc_reg_1961; // op=pyc.reg +wire [15:0] pyc_reg_1962; // op=pyc.reg +wire [11:0] pyc_reg_1963; // op=pyc.reg +wire [11:0] pyc_reg_1964; // op=pyc.reg +wire [11:0] pyc_reg_1965; // op=pyc.reg +wire [11:0] pyc_reg_1966; // op=pyc.reg +wire [11:0] pyc_reg_1967; // op=pyc.reg +wire [11:0] pyc_reg_1968; // op=pyc.reg +wire [11:0] pyc_reg_1969; // op=pyc.reg +wire [11:0] pyc_reg_1970; // op=pyc.reg +wire [11:0] pyc_reg_1971; // op=pyc.reg +wire [11:0] pyc_reg_1972; // op=pyc.reg +wire [11:0] pyc_reg_1973; // op=pyc.reg +wire [11:0] pyc_reg_1974; // op=pyc.reg +wire [11:0] pyc_reg_1975; // op=pyc.reg +wire [11:0] pyc_reg_1976; // op=pyc.reg +wire [11:0] pyc_reg_1977; // op=pyc.reg +wire [11:0] pyc_reg_1978; // op=pyc.reg +wire [12:0] pyc_reg_1979; // op=pyc.reg +wire [12:0] pyc_reg_1980; // op=pyc.reg +wire [12:0] pyc_reg_1981; // op=pyc.reg +wire [12:0] pyc_reg_1982; // op=pyc.reg +wire [12:0] pyc_reg_1983; // op=pyc.reg +wire [12:0] pyc_reg_1984; // op=pyc.reg +wire [12:0] pyc_reg_1985; // op=pyc.reg +wire [12:0] pyc_reg_1986; // op=pyc.reg +wire [12:0] pyc_reg_1987; // op=pyc.reg +wire [12:0] pyc_reg_1988; // op=pyc.reg +wire [12:0] pyc_reg_1989; // op=pyc.reg +wire [12:0] pyc_reg_1990; // op=pyc.reg +wire [12:0] pyc_reg_1991; // op=pyc.reg +wire [12:0] pyc_reg_1992; // op=pyc.reg +wire [12:0] pyc_reg_1993; // op=pyc.reg +wire [12:0] pyc_reg_1994; // op=pyc.reg +wire [9:0] pyc_reg_1995; // op=pyc.reg +wire [9:0] pyc_reg_1996; // op=pyc.reg +wire [9:0] pyc_reg_1997; // op=pyc.reg +wire [9:0] pyc_reg_1998; // op=pyc.reg +wire [9:0] pyc_reg_1999; // op=pyc.reg +wire [9:0] pyc_reg_2000; // op=pyc.reg +wire [9:0] pyc_reg_2001; // op=pyc.reg +wire [9:0] pyc_reg_2002; // op=pyc.reg +wire [9:0] pyc_reg_2003; // op=pyc.reg +wire [9:0] pyc_reg_2004; // op=pyc.reg +wire [9:0] pyc_reg_2005; // op=pyc.reg +wire [9:0] pyc_reg_2006; // op=pyc.reg +wire [9:0] pyc_reg_2007; // op=pyc.reg +wire [9:0] pyc_reg_2008; // op=pyc.reg +wire [9:0] pyc_reg_2009; // op=pyc.reg +wire [9:0] pyc_reg_2010; // op=pyc.reg +wire [9:0] pyc_reg_2011; // op=pyc.reg +wire [9:0] pyc_reg_2012; // op=pyc.reg +wire [9:0] pyc_reg_2013; // op=pyc.reg +wire [9:0] pyc_reg_2014; // op=pyc.reg +wire [9:0] pyc_reg_2015; // op=pyc.reg +wire [9:0] pyc_reg_2016; // op=pyc.reg +wire [9:0] pyc_reg_2017; // op=pyc.reg +wire [9:0] pyc_reg_2018; // op=pyc.reg +wire [9:0] pyc_reg_2019; // op=pyc.reg +wire [9:0] pyc_reg_2020; // op=pyc.reg +wire [9:0] pyc_reg_2021; // op=pyc.reg +wire [9:0] pyc_reg_2022; // op=pyc.reg +wire [9:0] pyc_reg_2023; // op=pyc.reg +wire [9:0] pyc_reg_2024; // op=pyc.reg +wire [9:0] pyc_reg_2025; // op=pyc.reg +wire [9:0] pyc_reg_2026; // op=pyc.reg +wire pyc_reg_2189; // op=pyc.reg +wire [2:0] pyc_reg_2196; // op=pyc.reg +wire [1:0] pyc_reg_2203; // op=pyc.reg +wire [1:0] pyc_reg_2204; // op=pyc.reg +wire [1:0] pyc_reg_2205; // op=pyc.reg +wire [18:0] pyc_reg_2206; // op=pyc.reg +wire [18:0] pyc_reg_2207; // op=pyc.reg +wire [15:0] pyc_reg_2208; // op=pyc.reg +wire [18:0] pyc_reg_2209; // op=pyc.reg +wire [15:0] pyc_reg_2210; // op=pyc.reg +wire [18:0] pyc_reg_2211; // op=pyc.reg +wire [18:0] pyc_reg_2212; // op=pyc.reg +wire [15:0] pyc_reg_2213; // op=pyc.reg +wire [15:0] pyc_reg_2214; // op=pyc.reg +wire [15:0] pyc_reg_2559; // op=pyc.reg +wire pyc_reg_2564; // op=pyc.reg +wire [18:0] pyc_reg_2565; // op=pyc.reg wire pyc_reg_35; // op=pyc.reg -wire [79:0] pyc_reg_37; // op=pyc.reg -wire [79:0] pyc_reg_38; // op=pyc.reg -wire [79:0] pyc_reg_39; // op=pyc.reg -wire [1:0] pyc_reg_40; // op=pyc.reg -wire [1:0] pyc_reg_42; // op=pyc.reg -wire pyc_reg_423; // op=pyc.reg -wire pyc_reg_425; // op=pyc.reg -wire pyc_reg_427; // op=pyc.reg -wire pyc_reg_429; // op=pyc.reg -wire [1:0] pyc_reg_431; // op=pyc.reg -wire [1:0] pyc_reg_433; // op=pyc.reg -wire [1:0] pyc_reg_435; // op=pyc.reg -wire [18:0] pyc_reg_437; // op=pyc.reg -wire [18:0] pyc_reg_438; // op=pyc.reg -wire [18:0] pyc_reg_439; // op=pyc.reg -wire [1:0] pyc_reg_44; // op=pyc.reg -wire [18:0] pyc_reg_440; // op=pyc.reg -wire [18:0] pyc_reg_441; // op=pyc.reg -wire [18:0] pyc_reg_442; // op=pyc.reg -wire [18:0] pyc_reg_443; // op=pyc.reg -wire [18:0] pyc_reg_444; // op=pyc.reg -wire [18:0] pyc_reg_445; // op=pyc.reg -wire [18:0] pyc_reg_446; // op=pyc.reg -wire [18:0] pyc_reg_447; // op=pyc.reg -wire [18:0] pyc_reg_448; // op=pyc.reg -wire [18:0] pyc_reg_449; // op=pyc.reg -wire [18:0] pyc_reg_450; // op=pyc.reg -wire [18:0] pyc_reg_451; // op=pyc.reg -wire [18:0] pyc_reg_452; // op=pyc.reg -wire [15:0] pyc_reg_453; // op=pyc.reg -wire [15:0] pyc_reg_454; // op=pyc.reg -wire [15:0] pyc_reg_455; // op=pyc.reg -wire [15:0] pyc_reg_456; // op=pyc.reg -wire [15:0] pyc_reg_457; // op=pyc.reg -wire [15:0] pyc_reg_458; // op=pyc.reg -wire [15:0] pyc_reg_459; // op=pyc.reg -wire [15:0] pyc_reg_460; // op=pyc.reg -wire [18:0] pyc_reg_461; // op=pyc.reg -wire [18:0] pyc_reg_462; // op=pyc.reg -wire [18:0] pyc_reg_463; // op=pyc.reg -wire [18:0] pyc_reg_464; // op=pyc.reg -wire [18:0] pyc_reg_465; // op=pyc.reg -wire [18:0] pyc_reg_466; // op=pyc.reg -wire [18:0] pyc_reg_467; // op=pyc.reg -wire [18:0] pyc_reg_468; // op=pyc.reg -wire [15:0] pyc_reg_469; // op=pyc.reg -wire [15:0] pyc_reg_470; // op=pyc.reg -wire [15:0] pyc_reg_471; // op=pyc.reg -wire [15:0] pyc_reg_472; // op=pyc.reg -wire [15:0] pyc_reg_473; // op=pyc.reg -wire [15:0] pyc_reg_474; // op=pyc.reg -wire [15:0] pyc_reg_475; // op=pyc.reg -wire [15:0] pyc_reg_476; // op=pyc.reg -wire [18:0] pyc_reg_477; // op=pyc.reg -wire [18:0] pyc_reg_478; // op=pyc.reg -wire [18:0] pyc_reg_479; // op=pyc.reg -wire [18:0] pyc_reg_480; // op=pyc.reg -wire [18:0] pyc_reg_481; // op=pyc.reg -wire [18:0] pyc_reg_482; // op=pyc.reg -wire [18:0] pyc_reg_483; // op=pyc.reg -wire [18:0] pyc_reg_484; // op=pyc.reg -wire [18:0] pyc_reg_485; // op=pyc.reg -wire [18:0] pyc_reg_486; // op=pyc.reg -wire [18:0] pyc_reg_487; // op=pyc.reg -wire [18:0] pyc_reg_488; // op=pyc.reg -wire [18:0] pyc_reg_489; // op=pyc.reg -wire [18:0] pyc_reg_490; // op=pyc.reg -wire [18:0] pyc_reg_491; // op=pyc.reg -wire [18:0] pyc_reg_492; // op=pyc.reg -wire [15:0] pyc_reg_493; // op=pyc.reg -wire [15:0] pyc_reg_494; // op=pyc.reg -wire [15:0] pyc_reg_495; // op=pyc.reg -wire [15:0] pyc_reg_496; // op=pyc.reg -wire [15:0] pyc_reg_497; // op=pyc.reg -wire [15:0] pyc_reg_498; // op=pyc.reg -wire [15:0] pyc_reg_499; // op=pyc.reg -wire [15:0] pyc_reg_500; // op=pyc.reg -wire [15:0] pyc_reg_501; // op=pyc.reg -wire [15:0] pyc_reg_502; // op=pyc.reg -wire [15:0] pyc_reg_503; // op=pyc.reg -wire [15:0] pyc_reg_504; // op=pyc.reg -wire [15:0] pyc_reg_505; // op=pyc.reg -wire [15:0] pyc_reg_506; // op=pyc.reg -wire [15:0] pyc_reg_507; // op=pyc.reg -wire [15:0] pyc_reg_508; // op=pyc.reg -wire pyc_reg_518; // op=pyc.reg -wire [2:0] pyc_reg_525; // op=pyc.reg -wire [1:0] pyc_reg_532; // op=pyc.reg -wire [1:0] pyc_reg_533; // op=pyc.reg -wire [1:0] pyc_reg_534; // op=pyc.reg -wire [18:0] pyc_reg_535; // op=pyc.reg -wire [18:0] pyc_reg_536; // op=pyc.reg -wire [15:0] pyc_reg_537; // op=pyc.reg -wire [18:0] pyc_reg_538; // op=pyc.reg -wire [15:0] pyc_reg_539; // op=pyc.reg -wire [18:0] pyc_reg_540; // op=pyc.reg -wire [18:0] pyc_reg_541; // op=pyc.reg -wire [15:0] pyc_reg_542; // op=pyc.reg -wire [15:0] pyc_reg_543; // op=pyc.reg -wire [15:0] pyc_reg_593; // op=pyc.reg -wire pyc_reg_598; // op=pyc.reg -wire [18:0] pyc_reg_599; // op=pyc.reg -wire [18:0] pyc_sext_103; // op=pyc.sext -wire [15:0] pyc_sext_104; // op=pyc.sext -wire [18:0] pyc_sext_110; // op=pyc.sext -wire [18:0] pyc_sext_113; // op=pyc.sext -wire [15:0] pyc_sext_116; // op=pyc.sext -wire [18:0] pyc_sext_117; // op=pyc.sext -wire [15:0] pyc_sext_118; // op=pyc.sext -wire [18:0] pyc_sext_129; // op=pyc.sext -wire [15:0] pyc_sext_130; // op=pyc.sext -wire [18:0] pyc_sext_136; // op=pyc.sext -wire [18:0] pyc_sext_139; // op=pyc.sext -wire [15:0] pyc_sext_142; // op=pyc.sext -wire [18:0] pyc_sext_143; // op=pyc.sext -wire [15:0] pyc_sext_144; // op=pyc.sext -wire [18:0] pyc_sext_155; // op=pyc.sext -wire [15:0] pyc_sext_156; // op=pyc.sext -wire [18:0] pyc_sext_158; // op=pyc.sext -wire [18:0] pyc_sext_161; // op=pyc.sext -wire [15:0] pyc_sext_164; // op=pyc.sext -wire [18:0] pyc_sext_165; // op=pyc.sext -wire [15:0] pyc_sext_166; // op=pyc.sext -wire [18:0] pyc_sext_177; // op=pyc.sext -wire [15:0] pyc_sext_178; // op=pyc.sext -wire [18:0] pyc_sext_180; // op=pyc.sext -wire [18:0] pyc_sext_183; // op=pyc.sext -wire [15:0] pyc_sext_186; // op=pyc.sext -wire [18:0] pyc_sext_187; // op=pyc.sext -wire [15:0] pyc_sext_188; // op=pyc.sext -wire [18:0] pyc_sext_199; // op=pyc.sext -wire [15:0] pyc_sext_200; // op=pyc.sext -wire [18:0] pyc_sext_202; // op=pyc.sext -wire [18:0] pyc_sext_205; // op=pyc.sext -wire [15:0] pyc_sext_208; // op=pyc.sext -wire [18:0] pyc_sext_209; // op=pyc.sext -wire [15:0] pyc_sext_210; // op=pyc.sext -wire [18:0] pyc_sext_221; // op=pyc.sext -wire [15:0] pyc_sext_222; // op=pyc.sext -wire [18:0] pyc_sext_226; // op=pyc.sext -wire [18:0] pyc_sext_229; // op=pyc.sext -wire [15:0] pyc_sext_230; // op=pyc.sext -wire [18:0] pyc_sext_231; // op=pyc.sext -wire [15:0] pyc_sext_232; // op=pyc.sext -wire [18:0] pyc_sext_238; // op=pyc.sext -wire [15:0] pyc_sext_239; // op=pyc.sext -wire [18:0] pyc_sext_240; // op=pyc.sext -wire [15:0] pyc_sext_242; // op=pyc.sext -wire [18:0] pyc_sext_245; // op=pyc.sext -wire [15:0] pyc_sext_246; // op=pyc.sext -wire [18:0] pyc_sext_247; // op=pyc.sext -wire [15:0] pyc_sext_249; // op=pyc.sext -wire [18:0] pyc_sext_252; // op=pyc.sext -wire [15:0] pyc_sext_253; // op=pyc.sext -wire [18:0] pyc_sext_254; // op=pyc.sext -wire [15:0] pyc_sext_256; // op=pyc.sext -wire [18:0] pyc_sext_259; // op=pyc.sext -wire [15:0] pyc_sext_260; // op=pyc.sext -wire [18:0] pyc_sext_261; // op=pyc.sext -wire [15:0] pyc_sext_263; // op=pyc.sext -wire [18:0] pyc_sext_266; // op=pyc.sext -wire [15:0] pyc_sext_267; // op=pyc.sext -wire [18:0] pyc_sext_268; // op=pyc.sext -wire [15:0] pyc_sext_270; // op=pyc.sext -wire [18:0] pyc_sext_273; // op=pyc.sext -wire [15:0] pyc_sext_274; // op=pyc.sext -wire [18:0] pyc_sext_275; // op=pyc.sext -wire [15:0] pyc_sext_277; // op=pyc.sext -wire [18:0] pyc_sext_280; // op=pyc.sext -wire [15:0] pyc_sext_281; // op=pyc.sext -wire [18:0] pyc_sext_282; // op=pyc.sext -wire [15:0] pyc_sext_284; // op=pyc.sext -wire [18:0] pyc_sext_287; // op=pyc.sext -wire [15:0] pyc_sext_288; // op=pyc.sext -wire [18:0] pyc_sext_289; // op=pyc.sext -wire [15:0] pyc_sext_291; // op=pyc.sext -wire [18:0] pyc_sext_294; // op=pyc.sext -wire [15:0] pyc_sext_295; // op=pyc.sext -wire [18:0] pyc_sext_296; // op=pyc.sext -wire [15:0] pyc_sext_298; // op=pyc.sext -wire [18:0] pyc_sext_301; // op=pyc.sext -wire [15:0] pyc_sext_302; // op=pyc.sext -wire [18:0] pyc_sext_303; // op=pyc.sext -wire [15:0] pyc_sext_305; // op=pyc.sext -wire [18:0] pyc_sext_308; // op=pyc.sext -wire [15:0] pyc_sext_309; // op=pyc.sext -wire [18:0] pyc_sext_310; // op=pyc.sext -wire [15:0] pyc_sext_312; // op=pyc.sext -wire [18:0] pyc_sext_315; // op=pyc.sext -wire [15:0] pyc_sext_316; // op=pyc.sext -wire [18:0] pyc_sext_317; // op=pyc.sext -wire [15:0] pyc_sext_319; // op=pyc.sext -wire [18:0] pyc_sext_322; // op=pyc.sext -wire [15:0] pyc_sext_323; // op=pyc.sext -wire [18:0] pyc_sext_324; // op=pyc.sext -wire [15:0] pyc_sext_326; // op=pyc.sext -wire [18:0] pyc_sext_329; // op=pyc.sext -wire [15:0] pyc_sext_330; // op=pyc.sext -wire [18:0] pyc_sext_331; // op=pyc.sext -wire [15:0] pyc_sext_333; // op=pyc.sext -wire [18:0] pyc_sext_336; // op=pyc.sext -wire [15:0] pyc_sext_337; // op=pyc.sext -wire [18:0] pyc_sext_338; // op=pyc.sext -wire [15:0] pyc_sext_340; // op=pyc.sext -wire [18:0] pyc_sext_343; // op=pyc.sext -wire [15:0] pyc_sext_344; // op=pyc.sext -wire [18:0] pyc_sext_345; // op=pyc.sext -wire [15:0] pyc_sext_347; // op=pyc.sext -wire [18:0] pyc_sext_51; // op=pyc.sext -wire [15:0] pyc_sext_52; // op=pyc.sext -wire [18:0] pyc_sext_58; // op=pyc.sext -wire [18:0] pyc_sext_61; // op=pyc.sext -wire [15:0] pyc_sext_64; // op=pyc.sext -wire [18:0] pyc_sext_65; // op=pyc.sext -wire [15:0] pyc_sext_66; // op=pyc.sext -wire [18:0] pyc_sext_77; // op=pyc.sext -wire [15:0] pyc_sext_78; // op=pyc.sext -wire [18:0] pyc_sext_84; // op=pyc.sext -wire [18:0] pyc_sext_87; // op=pyc.sext -wire [15:0] pyc_sext_90; // op=pyc.sext -wire [18:0] pyc_sext_91; // op=pyc.sext -wire [15:0] pyc_sext_92; // op=pyc.sext -wire [18:0] pyc_shli_556; // op=pyc.shli -wire [18:0] pyc_shli_557; // op=pyc.shli -wire [18:0] pyc_shli_562; // op=pyc.shli -wire [18:0] pyc_shli_563; // op=pyc.shli -wire [15:0] pyc_shli_575; // op=pyc.shli -wire [15:0] pyc_shli_576; // op=pyc.shli -wire [15:0] pyc_shli_581; // op=pyc.shli -wire [15:0] pyc_shli_582; // op=pyc.shli -wire [1:0] pyc_zext_545; // op=pyc.zext -wire [1:0] pyc_zext_547; // op=pyc.zext -wire [1:0] pyc_zext_550; // op=pyc.zext -wire [1:0] pyc_zext_552; // op=pyc.zext -wire [1:0] pyc_zext_568; // op=pyc.zext -wire [1:0] pyc_zext_571; // op=pyc.zext +wire pyc_reg_37; // op=pyc.reg +wire pyc_reg_39; // op=pyc.reg +wire pyc_reg_41; // op=pyc.reg +wire [79:0] pyc_reg_43; // op=pyc.reg +wire [79:0] pyc_reg_44; // op=pyc.reg +wire [79:0] pyc_reg_45; // op=pyc.reg +wire [1:0] pyc_reg_46; // op=pyc.reg +wire [1:0] pyc_reg_48; // op=pyc.reg +wire [1:0] pyc_reg_50; // op=pyc.reg +wire [18:0] pyc_sext_2027; // op=pyc.sext +wire [18:0] pyc_sext_2028; // op=pyc.sext +wire [18:0] pyc_sext_2029; // op=pyc.sext +wire [18:0] pyc_sext_2030; // op=pyc.sext +wire [18:0] pyc_sext_2031; // op=pyc.sext +wire [18:0] pyc_sext_2032; // op=pyc.sext +wire [18:0] pyc_sext_2033; // op=pyc.sext +wire [18:0] pyc_sext_2034; // op=pyc.sext +wire [18:0] pyc_sext_2045; // op=pyc.sext +wire [18:0] pyc_sext_2046; // op=pyc.sext +wire [18:0] pyc_sext_2047; // op=pyc.sext +wire [18:0] pyc_sext_2048; // op=pyc.sext +wire [18:0] pyc_sext_2049; // op=pyc.sext +wire [18:0] pyc_sext_2050; // op=pyc.sext +wire [18:0] pyc_sext_2051; // op=pyc.sext +wire [18:0] pyc_sext_2052; // op=pyc.sext +wire [15:0] pyc_sext_2063; // op=pyc.sext +wire [15:0] pyc_sext_2064; // op=pyc.sext +wire [15:0] pyc_sext_2065; // op=pyc.sext +wire [15:0] pyc_sext_2066; // op=pyc.sext +wire [15:0] pyc_sext_2067; // op=pyc.sext +wire [15:0] pyc_sext_2068; // op=pyc.sext +wire [15:0] pyc_sext_2069; // op=pyc.sext +wire [15:0] pyc_sext_2070; // op=pyc.sext +wire [18:0] pyc_sext_2081; // op=pyc.sext +wire [18:0] pyc_sext_2082; // op=pyc.sext +wire [18:0] pyc_sext_2083; // op=pyc.sext +wire [18:0] pyc_sext_2084; // op=pyc.sext +wire [18:0] pyc_sext_2085; // op=pyc.sext +wire [18:0] pyc_sext_2086; // op=pyc.sext +wire [18:0] pyc_sext_2087; // op=pyc.sext +wire [18:0] pyc_sext_2088; // op=pyc.sext +wire [15:0] pyc_sext_2099; // op=pyc.sext +wire [15:0] pyc_sext_2100; // op=pyc.sext +wire [15:0] pyc_sext_2101; // op=pyc.sext +wire [15:0] pyc_sext_2102; // op=pyc.sext +wire [15:0] pyc_sext_2103; // op=pyc.sext +wire [15:0] pyc_sext_2104; // op=pyc.sext +wire [15:0] pyc_sext_2105; // op=pyc.sext +wire [15:0] pyc_sext_2106; // op=pyc.sext +wire [18:0] pyc_sext_2117; // op=pyc.sext +wire [18:0] pyc_sext_2118; // op=pyc.sext +wire [18:0] pyc_sext_2119; // op=pyc.sext +wire [18:0] pyc_sext_2120; // op=pyc.sext +wire [18:0] pyc_sext_2121; // op=pyc.sext +wire [18:0] pyc_sext_2122; // op=pyc.sext +wire [18:0] pyc_sext_2123; // op=pyc.sext +wire [18:0] pyc_sext_2124; // op=pyc.sext +wire [18:0] pyc_sext_2135; // op=pyc.sext +wire [18:0] pyc_sext_2136; // op=pyc.sext +wire [18:0] pyc_sext_2137; // op=pyc.sext +wire [18:0] pyc_sext_2138; // op=pyc.sext +wire [18:0] pyc_sext_2139; // op=pyc.sext +wire [18:0] pyc_sext_2140; // op=pyc.sext +wire [18:0] pyc_sext_2141; // op=pyc.sext +wire [18:0] pyc_sext_2142; // op=pyc.sext +wire [15:0] pyc_sext_2153; // op=pyc.sext +wire [15:0] pyc_sext_2154; // op=pyc.sext +wire [15:0] pyc_sext_2155; // op=pyc.sext +wire [15:0] pyc_sext_2156; // op=pyc.sext +wire [15:0] pyc_sext_2157; // op=pyc.sext +wire [15:0] pyc_sext_2158; // op=pyc.sext +wire [15:0] pyc_sext_2159; // op=pyc.sext +wire [15:0] pyc_sext_2160; // op=pyc.sext +wire [15:0] pyc_sext_2171; // op=pyc.sext +wire [15:0] pyc_sext_2172; // op=pyc.sext +wire [15:0] pyc_sext_2173; // op=pyc.sext +wire [15:0] pyc_sext_2174; // op=pyc.sext +wire [15:0] pyc_sext_2175; // op=pyc.sext +wire [15:0] pyc_sext_2176; // op=pyc.sext +wire [15:0] pyc_sext_2177; // op=pyc.sext +wire [15:0] pyc_sext_2178; // op=pyc.sext +wire [12:0] pyc_shli_1002; // op=pyc.shli +wire [15:0] pyc_shli_101; // op=pyc.shli +wire [15:0] pyc_shli_1019; // op=pyc.shli +wire [15:0] pyc_shli_1023; // op=pyc.shli +wire [15:0] pyc_shli_1027; // op=pyc.shli +wire [15:0] pyc_shli_1031; // op=pyc.shli +wire [15:0] pyc_shli_1035; // op=pyc.shli +wire [15:0] pyc_shli_1039; // op=pyc.shli +wire [15:0] pyc_shli_1043; // op=pyc.shli +wire [15:0] pyc_shli_1047; // op=pyc.shli +wire [15:0] pyc_shli_1051; // op=pyc.shli +wire [11:0] pyc_shli_1058; // op=pyc.shli +wire [11:0] pyc_shli_1062; // op=pyc.shli +wire [11:0] pyc_shli_1066; // op=pyc.shli +wire [11:0] pyc_shli_1070; // op=pyc.shli +wire [11:0] pyc_shli_1073; // op=pyc.shli +wire [11:0] pyc_shli_108; // op=pyc.shli +wire [11:0] pyc_shli_1090; // op=pyc.shli +wire [12:0] pyc_shli_1097; // op=pyc.shli +wire [12:0] pyc_shli_1101; // op=pyc.shli +wire [12:0] pyc_shli_1105; // op=pyc.shli +wire [12:0] pyc_shli_1109; // op=pyc.shli +wire [12:0] pyc_shli_1113; // op=pyc.shli +wire [12:0] pyc_shli_1116; // op=pyc.shli +wire [11:0] pyc_shli_112; // op=pyc.shli +wire [12:0] pyc_shli_1136; // op=pyc.shli +wire [9:0] pyc_shli_1144; // op=pyc.shli +wire [9:0] pyc_shli_1148; // op=pyc.shli +wire [9:0] pyc_shli_1152; // op=pyc.shli +wire [9:0] pyc_shli_1156; // op=pyc.shli +wire [11:0] pyc_shli_116; // op=pyc.shli +wire [9:0] pyc_shli_1160; // op=pyc.shli +wire [9:0] pyc_shli_1164; // op=pyc.shli +wire [9:0] pyc_shli_1184; // op=pyc.shli +wire [9:0] pyc_shli_1192; // op=pyc.shli +wire [9:0] pyc_shli_1196; // op=pyc.shli +wire [11:0] pyc_shli_120; // op=pyc.shli +wire [9:0] pyc_shli_1200; // op=pyc.shli +wire [9:0] pyc_shli_1204; // op=pyc.shli +wire [9:0] pyc_shli_1208; // op=pyc.shli +wire [9:0] pyc_shli_1212; // op=pyc.shli +wire [11:0] pyc_shli_123; // op=pyc.shli +wire [9:0] pyc_shli_1232; // op=pyc.shli +wire [9:0] pyc_shli_1240; // op=pyc.shli +wire [9:0] pyc_shli_1244; // op=pyc.shli +wire [9:0] pyc_shli_1248; // op=pyc.shli +wire [9:0] pyc_shli_1252; // op=pyc.shli +wire [9:0] pyc_shli_1256; // op=pyc.shli +wire [9:0] pyc_shli_1260; // op=pyc.shli +wire [9:0] pyc_shli_1280; // op=pyc.shli +wire [9:0] pyc_shli_1288; // op=pyc.shli +wire [9:0] pyc_shli_1292; // op=pyc.shli +wire [9:0] pyc_shli_1296; // op=pyc.shli +wire [9:0] pyc_shli_1300; // op=pyc.shli +wire [9:0] pyc_shli_1304; // op=pyc.shli +wire [9:0] pyc_shli_1308; // op=pyc.shli +wire [9:0] pyc_shli_1328; // op=pyc.shli +wire [9:0] pyc_shli_1336; // op=pyc.shli +wire [9:0] pyc_shli_1340; // op=pyc.shli +wire [9:0] pyc_shli_1344; // op=pyc.shli +wire [9:0] pyc_shli_1348; // op=pyc.shli +wire [9:0] pyc_shli_1352; // op=pyc.shli +wire [9:0] pyc_shli_1356; // op=pyc.shli +wire [9:0] pyc_shli_1376; // op=pyc.shli +wire [9:0] pyc_shli_1384; // op=pyc.shli +wire [9:0] pyc_shli_1388; // op=pyc.shli +wire [9:0] pyc_shli_1392; // op=pyc.shli +wire [9:0] pyc_shli_1396; // op=pyc.shli +wire [11:0] pyc_shli_140; // op=pyc.shli +wire [9:0] pyc_shli_1400; // op=pyc.shli +wire [9:0] pyc_shli_1404; // op=pyc.shli +wire [9:0] pyc_shli_1424; // op=pyc.shli +wire [9:0] pyc_shli_1432; // op=pyc.shli +wire [9:0] pyc_shli_1436; // op=pyc.shli +wire [9:0] pyc_shli_1440; // op=pyc.shli +wire [9:0] pyc_shli_1444; // op=pyc.shli +wire [9:0] pyc_shli_1448; // op=pyc.shli +wire [9:0] pyc_shli_1452; // op=pyc.shli +wire [12:0] pyc_shli_147; // op=pyc.shli +wire [9:0] pyc_shli_1472; // op=pyc.shli +wire [9:0] pyc_shli_1480; // op=pyc.shli +wire [9:0] pyc_shli_1484; // op=pyc.shli +wire [9:0] pyc_shli_1488; // op=pyc.shli +wire [9:0] pyc_shli_1492; // op=pyc.shli +wire [9:0] pyc_shli_1496; // op=pyc.shli +wire [9:0] pyc_shli_1500; // op=pyc.shli +wire [12:0] pyc_shli_151; // op=pyc.shli +wire [9:0] pyc_shli_1520; // op=pyc.shli +wire [9:0] pyc_shli_1527; // op=pyc.shli +wire [9:0] pyc_shli_1530; // op=pyc.shli +wire [9:0] pyc_shli_1533; // op=pyc.shli +wire [9:0] pyc_shli_1536; // op=pyc.shli +wire [9:0] pyc_shli_1539; // op=pyc.shli +wire [9:0] pyc_shli_1543; // op=pyc.shli +wire [12:0] pyc_shli_155; // op=pyc.shli +wire [9:0] pyc_shli_1563; // op=pyc.shli +wire [9:0] pyc_shli_1570; // op=pyc.shli +wire [9:0] pyc_shli_1573; // op=pyc.shli +wire [9:0] pyc_shli_1576; // op=pyc.shli +wire [9:0] pyc_shli_1579; // op=pyc.shli +wire [9:0] pyc_shli_1582; // op=pyc.shli +wire [9:0] pyc_shli_1586; // op=pyc.shli +wire [12:0] pyc_shli_159; // op=pyc.shli +wire [9:0] pyc_shli_1606; // op=pyc.shli +wire [9:0] pyc_shli_1613; // op=pyc.shli +wire [9:0] pyc_shli_1616; // op=pyc.shli +wire [9:0] pyc_shli_1619; // op=pyc.shli +wire [9:0] pyc_shli_1622; // op=pyc.shli +wire [9:0] pyc_shli_1625; // op=pyc.shli +wire [9:0] pyc_shli_1629; // op=pyc.shli +wire [12:0] pyc_shli_163; // op=pyc.shli +wire [9:0] pyc_shli_1649; // op=pyc.shli +wire [9:0] pyc_shli_1656; // op=pyc.shli +wire [9:0] pyc_shli_1659; // op=pyc.shli +wire [12:0] pyc_shli_166; // op=pyc.shli +wire [9:0] pyc_shli_1662; // op=pyc.shli +wire [9:0] pyc_shli_1665; // op=pyc.shli +wire [9:0] pyc_shli_1668; // op=pyc.shli +wire [9:0] pyc_shli_1672; // op=pyc.shli +wire [9:0] pyc_shli_1692; // op=pyc.shli +wire [9:0] pyc_shli_1699; // op=pyc.shli +wire [9:0] pyc_shli_1702; // op=pyc.shli +wire [9:0] pyc_shli_1705; // op=pyc.shli +wire [9:0] pyc_shli_1708; // op=pyc.shli +wire [9:0] pyc_shli_1711; // op=pyc.shli +wire [9:0] pyc_shli_1715; // op=pyc.shli +wire [9:0] pyc_shli_1735; // op=pyc.shli +wire [9:0] pyc_shli_1742; // op=pyc.shli +wire [9:0] pyc_shli_1745; // op=pyc.shli +wire [9:0] pyc_shli_1748; // op=pyc.shli +wire [9:0] pyc_shli_1751; // op=pyc.shli +wire [9:0] pyc_shli_1754; // op=pyc.shli +wire [9:0] pyc_shli_1758; // op=pyc.shli +wire [9:0] pyc_shli_1778; // op=pyc.shli +wire [9:0] pyc_shli_1785; // op=pyc.shli +wire [9:0] pyc_shli_1788; // op=pyc.shli +wire [9:0] pyc_shli_1791; // op=pyc.shli +wire [9:0] pyc_shli_1794; // op=pyc.shli +wire [9:0] pyc_shli_1797; // op=pyc.shli +wire [9:0] pyc_shli_1801; // op=pyc.shli +wire [9:0] pyc_shli_1821; // op=pyc.shli +wire [9:0] pyc_shli_1828; // op=pyc.shli +wire [9:0] pyc_shli_1831; // op=pyc.shli +wire [9:0] pyc_shli_1834; // op=pyc.shli +wire [9:0] pyc_shli_1837; // op=pyc.shli +wire [9:0] pyc_shli_1840; // op=pyc.shli +wire [9:0] pyc_shli_1844; // op=pyc.shli +wire [12:0] pyc_shli_186; // op=pyc.shli +wire [9:0] pyc_shli_1864; // op=pyc.shli +wire [15:0] pyc_shli_207; // op=pyc.shli +wire [15:0] pyc_shli_211; // op=pyc.shli +wire [15:0] pyc_shli_215; // op=pyc.shli +wire [15:0] pyc_shli_219; // op=pyc.shli +wire [18:0] pyc_shli_2227; // op=pyc.shli +wire [18:0] pyc_shli_2228; // op=pyc.shli +wire [15:0] pyc_shli_223; // op=pyc.shli +wire [18:0] pyc_shli_2233; // op=pyc.shli +wire [18:0] pyc_shli_2234; // op=pyc.shli +wire [15:0] pyc_shli_227; // op=pyc.shli +wire [15:0] pyc_shli_231; // op=pyc.shli +wire [15:0] pyc_shli_235; // op=pyc.shli +wire [15:0] pyc_shli_239; // op=pyc.shli +wire [15:0] pyc_shli_2409; // op=pyc.shli +wire [15:0] pyc_shli_2410; // op=pyc.shli +wire [15:0] pyc_shli_2415; // op=pyc.shli +wire [15:0] pyc_shli_2416; // op=pyc.shli +wire [11:0] pyc_shli_246; // op=pyc.shli +wire [11:0] pyc_shli_250; // op=pyc.shli +wire [11:0] pyc_shli_254; // op=pyc.shli +wire [11:0] pyc_shli_258; // op=pyc.shli +wire [11:0] pyc_shli_261; // op=pyc.shli +wire [11:0] pyc_shli_278; // op=pyc.shli +wire [12:0] pyc_shli_285; // op=pyc.shli +wire [12:0] pyc_shli_289; // op=pyc.shli +wire [12:0] pyc_shli_293; // op=pyc.shli +wire [12:0] pyc_shli_297; // op=pyc.shli +wire [12:0] pyc_shli_301; // op=pyc.shli +wire [12:0] pyc_shli_304; // op=pyc.shli +wire [12:0] pyc_shli_324; // op=pyc.shli +wire [15:0] pyc_shli_345; // op=pyc.shli +wire [15:0] pyc_shli_349; // op=pyc.shli +wire [15:0] pyc_shli_353; // op=pyc.shli +wire [15:0] pyc_shli_357; // op=pyc.shli +wire [15:0] pyc_shli_361; // op=pyc.shli +wire [15:0] pyc_shli_365; // op=pyc.shli +wire [15:0] pyc_shli_369; // op=pyc.shli +wire [15:0] pyc_shli_373; // op=pyc.shli +wire [15:0] pyc_shli_377; // op=pyc.shli +wire [11:0] pyc_shli_384; // op=pyc.shli +wire [11:0] pyc_shli_388; // op=pyc.shli +wire [11:0] pyc_shli_392; // op=pyc.shli +wire [11:0] pyc_shli_396; // op=pyc.shli +wire [11:0] pyc_shli_399; // op=pyc.shli +wire [11:0] pyc_shli_416; // op=pyc.shli +wire [12:0] pyc_shli_423; // op=pyc.shli +wire [12:0] pyc_shli_427; // op=pyc.shli +wire [12:0] pyc_shli_431; // op=pyc.shli +wire [12:0] pyc_shli_435; // op=pyc.shli +wire [12:0] pyc_shli_439; // op=pyc.shli +wire [12:0] pyc_shli_442; // op=pyc.shli +wire [12:0] pyc_shli_462; // op=pyc.shli +wire [15:0] pyc_shli_483; // op=pyc.shli +wire [15:0] pyc_shli_487; // op=pyc.shli +wire [15:0] pyc_shli_491; // op=pyc.shli +wire [15:0] pyc_shli_495; // op=pyc.shli +wire [15:0] pyc_shli_499; // op=pyc.shli +wire [15:0] pyc_shli_503; // op=pyc.shli +wire [15:0] pyc_shli_507; // op=pyc.shli +wire [15:0] pyc_shli_511; // op=pyc.shli +wire [15:0] pyc_shli_515; // op=pyc.shli +wire [11:0] pyc_shli_522; // op=pyc.shli +wire [11:0] pyc_shli_526; // op=pyc.shli +wire [11:0] pyc_shli_530; // op=pyc.shli +wire [11:0] pyc_shli_534; // op=pyc.shli +wire [11:0] pyc_shli_537; // op=pyc.shli +wire [11:0] pyc_shli_554; // op=pyc.shli +wire [12:0] pyc_shli_561; // op=pyc.shli +wire [12:0] pyc_shli_565; // op=pyc.shli +wire [12:0] pyc_shli_569; // op=pyc.shli +wire [12:0] pyc_shli_573; // op=pyc.shli +wire [12:0] pyc_shli_577; // op=pyc.shli +wire [12:0] pyc_shli_580; // op=pyc.shli +wire [12:0] pyc_shli_600; // op=pyc.shli +wire [15:0] pyc_shli_617; // op=pyc.shli +wire [15:0] pyc_shli_621; // op=pyc.shli +wire [15:0] pyc_shli_625; // op=pyc.shli +wire [15:0] pyc_shli_629; // op=pyc.shli +wire [15:0] pyc_shli_633; // op=pyc.shli +wire [15:0] pyc_shli_637; // op=pyc.shli +wire [15:0] pyc_shli_641; // op=pyc.shli +wire [15:0] pyc_shli_645; // op=pyc.shli +wire [15:0] pyc_shli_649; // op=pyc.shli +wire [11:0] pyc_shli_656; // op=pyc.shli +wire [11:0] pyc_shli_660; // op=pyc.shli +wire [11:0] pyc_shli_664; // op=pyc.shli +wire [11:0] pyc_shli_668; // op=pyc.shli +wire [11:0] pyc_shli_671; // op=pyc.shli +wire [11:0] pyc_shli_688; // op=pyc.shli +wire [15:0] pyc_shli_69; // op=pyc.shli +wire [12:0] pyc_shli_695; // op=pyc.shli +wire [12:0] pyc_shli_699; // op=pyc.shli +wire [12:0] pyc_shli_703; // op=pyc.shli +wire [12:0] pyc_shli_707; // op=pyc.shli +wire [12:0] pyc_shli_711; // op=pyc.shli +wire [12:0] pyc_shli_714; // op=pyc.shli +wire [15:0] pyc_shli_73; // op=pyc.shli +wire [12:0] pyc_shli_734; // op=pyc.shli +wire [15:0] pyc_shli_751; // op=pyc.shli +wire [15:0] pyc_shli_755; // op=pyc.shli +wire [15:0] pyc_shli_759; // op=pyc.shli +wire [15:0] pyc_shli_763; // op=pyc.shli +wire [15:0] pyc_shli_767; // op=pyc.shli +wire [15:0] pyc_shli_77; // op=pyc.shli +wire [15:0] pyc_shli_771; // op=pyc.shli +wire [15:0] pyc_shli_775; // op=pyc.shli +wire [15:0] pyc_shli_779; // op=pyc.shli +wire [15:0] pyc_shli_783; // op=pyc.shli +wire [11:0] pyc_shli_790; // op=pyc.shli +wire [11:0] pyc_shli_794; // op=pyc.shli +wire [11:0] pyc_shli_798; // op=pyc.shli +wire [11:0] pyc_shli_802; // op=pyc.shli +wire [11:0] pyc_shli_805; // op=pyc.shli +wire [15:0] pyc_shli_81; // op=pyc.shli +wire [11:0] pyc_shli_822; // op=pyc.shli +wire [12:0] pyc_shli_829; // op=pyc.shli +wire [12:0] pyc_shli_833; // op=pyc.shli +wire [12:0] pyc_shli_837; // op=pyc.shli +wire [12:0] pyc_shli_841; // op=pyc.shli +wire [12:0] pyc_shli_845; // op=pyc.shli +wire [12:0] pyc_shli_848; // op=pyc.shli +wire [15:0] pyc_shli_85; // op=pyc.shli +wire [12:0] pyc_shli_868; // op=pyc.shli +wire [15:0] pyc_shli_885; // op=pyc.shli +wire [15:0] pyc_shli_889; // op=pyc.shli +wire [15:0] pyc_shli_89; // op=pyc.shli +wire [15:0] pyc_shli_893; // op=pyc.shli +wire [15:0] pyc_shli_897; // op=pyc.shli +wire [15:0] pyc_shli_901; // op=pyc.shli +wire [15:0] pyc_shli_905; // op=pyc.shli +wire [15:0] pyc_shli_909; // op=pyc.shli +wire [15:0] pyc_shli_913; // op=pyc.shli +wire [15:0] pyc_shli_917; // op=pyc.shli +wire [11:0] pyc_shli_924; // op=pyc.shli +wire [11:0] pyc_shli_928; // op=pyc.shli +wire [15:0] pyc_shli_93; // op=pyc.shli +wire [11:0] pyc_shli_932; // op=pyc.shli +wire [11:0] pyc_shli_936; // op=pyc.shli +wire [11:0] pyc_shli_939; // op=pyc.shli +wire [11:0] pyc_shli_956; // op=pyc.shli +wire [12:0] pyc_shli_963; // op=pyc.shli +wire [12:0] pyc_shli_967; // op=pyc.shli +wire [15:0] pyc_shli_97; // op=pyc.shli +wire [12:0] pyc_shli_971; // op=pyc.shli +wire [12:0] pyc_shli_975; // op=pyc.shli +wire [12:0] pyc_shli_979; // op=pyc.shli +wire [12:0] pyc_shli_982; // op=pyc.shli +wire [12:0] pyc_sub_1004; // op=pyc.sub +wire [12:0] pyc_sub_1005; // op=pyc.sub +wire [15:0] pyc_sub_103; // op=pyc.sub +wire [15:0] pyc_sub_104; // op=pyc.sub +wire [15:0] pyc_sub_1053; // op=pyc.sub +wire [15:0] pyc_sub_1054; // op=pyc.sub +wire [11:0] pyc_sub_1075; // op=pyc.sub +wire [11:0] pyc_sub_1076; // op=pyc.sub +wire [11:0] pyc_sub_1092; // op=pyc.sub +wire [11:0] pyc_sub_1093; // op=pyc.sub +wire [12:0] pyc_sub_1118; // op=pyc.sub +wire [12:0] pyc_sub_1119; // op=pyc.sub +wire [12:0] pyc_sub_1138; // op=pyc.sub +wire [12:0] pyc_sub_1139; // op=pyc.sub +wire [9:0] pyc_sub_1166; // op=pyc.sub +wire [9:0] pyc_sub_1167; // op=pyc.sub +wire [9:0] pyc_sub_1186; // op=pyc.sub +wire [9:0] pyc_sub_1187; // op=pyc.sub +wire [9:0] pyc_sub_1214; // op=pyc.sub +wire [9:0] pyc_sub_1215; // op=pyc.sub +wire [9:0] pyc_sub_1234; // op=pyc.sub +wire [9:0] pyc_sub_1235; // op=pyc.sub +wire [11:0] pyc_sub_125; // op=pyc.sub +wire [11:0] pyc_sub_126; // op=pyc.sub +wire [9:0] pyc_sub_1262; // op=pyc.sub +wire [9:0] pyc_sub_1263; // op=pyc.sub +wire [9:0] pyc_sub_1282; // op=pyc.sub +wire [9:0] pyc_sub_1283; // op=pyc.sub +wire [9:0] pyc_sub_1310; // op=pyc.sub +wire [9:0] pyc_sub_1311; // op=pyc.sub +wire [9:0] pyc_sub_1330; // op=pyc.sub +wire [9:0] pyc_sub_1331; // op=pyc.sub +wire [9:0] pyc_sub_1358; // op=pyc.sub +wire [9:0] pyc_sub_1359; // op=pyc.sub +wire [9:0] pyc_sub_1378; // op=pyc.sub +wire [9:0] pyc_sub_1379; // op=pyc.sub +wire [9:0] pyc_sub_1406; // op=pyc.sub +wire [9:0] pyc_sub_1407; // op=pyc.sub +wire [11:0] pyc_sub_142; // op=pyc.sub +wire [9:0] pyc_sub_1426; // op=pyc.sub +wire [9:0] pyc_sub_1427; // op=pyc.sub +wire [11:0] pyc_sub_143; // op=pyc.sub +wire [9:0] pyc_sub_1454; // op=pyc.sub +wire [9:0] pyc_sub_1455; // op=pyc.sub +wire [9:0] pyc_sub_1474; // op=pyc.sub +wire [9:0] pyc_sub_1475; // op=pyc.sub +wire [9:0] pyc_sub_1502; // op=pyc.sub +wire [9:0] pyc_sub_1503; // op=pyc.sub +wire [9:0] pyc_sub_1522; // op=pyc.sub +wire [9:0] pyc_sub_1523; // op=pyc.sub +wire [9:0] pyc_sub_1545; // op=pyc.sub +wire [9:0] pyc_sub_1546; // op=pyc.sub +wire [9:0] pyc_sub_1565; // op=pyc.sub +wire [9:0] pyc_sub_1566; // op=pyc.sub +wire [9:0] pyc_sub_1588; // op=pyc.sub +wire [9:0] pyc_sub_1589; // op=pyc.sub +wire [9:0] pyc_sub_1608; // op=pyc.sub +wire [9:0] pyc_sub_1609; // op=pyc.sub +wire [9:0] pyc_sub_1631; // op=pyc.sub +wire [9:0] pyc_sub_1632; // op=pyc.sub +wire [9:0] pyc_sub_1651; // op=pyc.sub +wire [9:0] pyc_sub_1652; // op=pyc.sub +wire [9:0] pyc_sub_1674; // op=pyc.sub +wire [9:0] pyc_sub_1675; // op=pyc.sub +wire [12:0] pyc_sub_168; // op=pyc.sub +wire [12:0] pyc_sub_169; // op=pyc.sub +wire [9:0] pyc_sub_1694; // op=pyc.sub +wire [9:0] pyc_sub_1695; // op=pyc.sub +wire [9:0] pyc_sub_1717; // op=pyc.sub +wire [9:0] pyc_sub_1718; // op=pyc.sub +wire [9:0] pyc_sub_1737; // op=pyc.sub +wire [9:0] pyc_sub_1738; // op=pyc.sub +wire [9:0] pyc_sub_1760; // op=pyc.sub +wire [9:0] pyc_sub_1761; // op=pyc.sub +wire [9:0] pyc_sub_1780; // op=pyc.sub +wire [9:0] pyc_sub_1781; // op=pyc.sub +wire [9:0] pyc_sub_1803; // op=pyc.sub +wire [9:0] pyc_sub_1804; // op=pyc.sub +wire [9:0] pyc_sub_1823; // op=pyc.sub +wire [9:0] pyc_sub_1824; // op=pyc.sub +wire [9:0] pyc_sub_1846; // op=pyc.sub +wire [9:0] pyc_sub_1847; // op=pyc.sub +wire [9:0] pyc_sub_1866; // op=pyc.sub +wire [9:0] pyc_sub_1867; // op=pyc.sub +wire [12:0] pyc_sub_188; // op=pyc.sub +wire [12:0] pyc_sub_189; // op=pyc.sub +wire [15:0] pyc_sub_241; // op=pyc.sub +wire [15:0] pyc_sub_242; // op=pyc.sub +wire [11:0] pyc_sub_263; // op=pyc.sub +wire [11:0] pyc_sub_264; // op=pyc.sub +wire [11:0] pyc_sub_280; // op=pyc.sub +wire [11:0] pyc_sub_281; // op=pyc.sub +wire [12:0] pyc_sub_306; // op=pyc.sub +wire [12:0] pyc_sub_307; // op=pyc.sub +wire [12:0] pyc_sub_326; // op=pyc.sub +wire [12:0] pyc_sub_327; // op=pyc.sub +wire [15:0] pyc_sub_379; // op=pyc.sub +wire [15:0] pyc_sub_380; // op=pyc.sub +wire [11:0] pyc_sub_401; // op=pyc.sub +wire [11:0] pyc_sub_402; // op=pyc.sub +wire [11:0] pyc_sub_418; // op=pyc.sub +wire [11:0] pyc_sub_419; // op=pyc.sub +wire [12:0] pyc_sub_444; // op=pyc.sub +wire [12:0] pyc_sub_445; // op=pyc.sub +wire [12:0] pyc_sub_464; // op=pyc.sub +wire [12:0] pyc_sub_465; // op=pyc.sub +wire [15:0] pyc_sub_517; // op=pyc.sub +wire [15:0] pyc_sub_518; // op=pyc.sub +wire [11:0] pyc_sub_539; // op=pyc.sub +wire [11:0] pyc_sub_540; // op=pyc.sub +wire [11:0] pyc_sub_556; // op=pyc.sub +wire [11:0] pyc_sub_557; // op=pyc.sub +wire [12:0] pyc_sub_582; // op=pyc.sub +wire [12:0] pyc_sub_583; // op=pyc.sub +wire [12:0] pyc_sub_602; // op=pyc.sub +wire [12:0] pyc_sub_603; // op=pyc.sub +wire [15:0] pyc_sub_651; // op=pyc.sub +wire [15:0] pyc_sub_652; // op=pyc.sub +wire [11:0] pyc_sub_673; // op=pyc.sub +wire [11:0] pyc_sub_674; // op=pyc.sub +wire [11:0] pyc_sub_690; // op=pyc.sub +wire [11:0] pyc_sub_691; // op=pyc.sub +wire [12:0] pyc_sub_716; // op=pyc.sub +wire [12:0] pyc_sub_717; // op=pyc.sub +wire [12:0] pyc_sub_736; // op=pyc.sub +wire [12:0] pyc_sub_737; // op=pyc.sub +wire [15:0] pyc_sub_785; // op=pyc.sub +wire [15:0] pyc_sub_786; // op=pyc.sub +wire [11:0] pyc_sub_807; // op=pyc.sub +wire [11:0] pyc_sub_808; // op=pyc.sub +wire [11:0] pyc_sub_824; // op=pyc.sub +wire [11:0] pyc_sub_825; // op=pyc.sub +wire [12:0] pyc_sub_850; // op=pyc.sub +wire [12:0] pyc_sub_851; // op=pyc.sub +wire [12:0] pyc_sub_870; // op=pyc.sub +wire [12:0] pyc_sub_871; // op=pyc.sub +wire [15:0] pyc_sub_919; // op=pyc.sub +wire [15:0] pyc_sub_920; // op=pyc.sub +wire [11:0] pyc_sub_941; // op=pyc.sub +wire [11:0] pyc_sub_942; // op=pyc.sub +wire [11:0] pyc_sub_958; // op=pyc.sub +wire [11:0] pyc_sub_959; // op=pyc.sub +wire [12:0] pyc_sub_984; // op=pyc.sub +wire [12:0] pyc_sub_985; // op=pyc.sub +wire pyc_xor_2239; // op=pyc.xor +wire pyc_xor_2242; // op=pyc.xor +wire pyc_xor_2245; // op=pyc.xor +wire pyc_xor_2248; // op=pyc.xor +wire pyc_xor_2251; // op=pyc.xor +wire pyc_xor_2254; // op=pyc.xor +wire pyc_xor_2257; // op=pyc.xor +wire pyc_xor_2260; // op=pyc.xor +wire pyc_xor_2263; // op=pyc.xor +wire pyc_xor_2266; // op=pyc.xor +wire pyc_xor_2269; // op=pyc.xor +wire pyc_xor_2272; // op=pyc.xor +wire pyc_xor_2275; // op=pyc.xor +wire pyc_xor_2278; // op=pyc.xor +wire pyc_xor_2281; // op=pyc.xor +wire pyc_xor_2284; // op=pyc.xor +wire pyc_xor_2287; // op=pyc.xor +wire pyc_xor_2290; // op=pyc.xor +wire pyc_xor_2293; // op=pyc.xor +wire pyc_xor_2382; // op=pyc.xor +wire pyc_xor_2383; // op=pyc.xor +wire pyc_xor_2384; // op=pyc.xor +wire pyc_xor_2385; // op=pyc.xor +wire pyc_xor_2386; // op=pyc.xor +wire pyc_xor_2387; // op=pyc.xor +wire pyc_xor_2388; // op=pyc.xor +wire pyc_xor_2389; // op=pyc.xor +wire pyc_xor_2390; // op=pyc.xor +wire pyc_xor_2391; // op=pyc.xor +wire pyc_xor_2392; // op=pyc.xor +wire pyc_xor_2393; // op=pyc.xor +wire pyc_xor_2394; // op=pyc.xor +wire pyc_xor_2395; // op=pyc.xor +wire pyc_xor_2396; // op=pyc.xor +wire pyc_xor_2397; // op=pyc.xor +wire pyc_xor_2398; // op=pyc.xor +wire pyc_xor_2399; // op=pyc.xor +wire pyc_xor_2421; // op=pyc.xor +wire pyc_xor_2424; // op=pyc.xor +wire pyc_xor_2427; // op=pyc.xor +wire pyc_xor_2430; // op=pyc.xor +wire pyc_xor_2433; // op=pyc.xor +wire pyc_xor_2436; // op=pyc.xor +wire pyc_xor_2439; // op=pyc.xor +wire pyc_xor_2442; // op=pyc.xor +wire pyc_xor_2445; // op=pyc.xor +wire pyc_xor_2448; // op=pyc.xor +wire pyc_xor_2451; // op=pyc.xor +wire pyc_xor_2454; // op=pyc.xor +wire pyc_xor_2457; // op=pyc.xor +wire pyc_xor_2460; // op=pyc.xor +wire pyc_xor_2463; // op=pyc.xor +wire pyc_xor_2466; // op=pyc.xor +wire pyc_xor_2534; // op=pyc.xor +wire pyc_xor_2535; // op=pyc.xor +wire pyc_xor_2536; // op=pyc.xor +wire pyc_xor_2537; // op=pyc.xor +wire pyc_xor_2538; // op=pyc.xor +wire pyc_xor_2539; // op=pyc.xor +wire pyc_xor_2540; // op=pyc.xor +wire pyc_xor_2541; // op=pyc.xor +wire pyc_xor_2542; // op=pyc.xor +wire pyc_xor_2543; // op=pyc.xor +wire pyc_xor_2544; // op=pyc.xor +wire pyc_xor_2545; // op=pyc.xor +wire pyc_xor_2546; // op=pyc.xor +wire pyc_xor_2547; // op=pyc.xor +wire pyc_xor_2548; // op=pyc.xor +wire [15:0] pyc_zext_100; // op=pyc.zext +wire [12:0] pyc_zext_1001; // op=pyc.zext +wire [15:0] pyc_zext_1016; // op=pyc.zext +wire [11:0] pyc_zext_105; // op=pyc.zext +wire [15:0] pyc_zext_1050; // op=pyc.zext +wire [11:0] pyc_zext_1055; // op=pyc.zext +wire [11:0] pyc_zext_1072; // op=pyc.zext +wire [11:0] pyc_zext_1089; // op=pyc.zext +wire [12:0] pyc_zext_1094; // op=pyc.zext +wire [12:0] pyc_zext_1115; // op=pyc.zext +wire [12:0] pyc_zext_1135; // op=pyc.zext +wire [9:0] pyc_zext_1141; // op=pyc.zext +wire [9:0] pyc_zext_1163; // op=pyc.zext +wire [9:0] pyc_zext_1183; // op=pyc.zext +wire [9:0] pyc_zext_1189; // op=pyc.zext +wire [9:0] pyc_zext_1211; // op=pyc.zext +wire [11:0] pyc_zext_122; // op=pyc.zext +wire [9:0] pyc_zext_1231; // op=pyc.zext +wire [9:0] pyc_zext_1237; // op=pyc.zext +wire [9:0] pyc_zext_1259; // op=pyc.zext +wire [9:0] pyc_zext_1279; // op=pyc.zext +wire [9:0] pyc_zext_1285; // op=pyc.zext +wire [9:0] pyc_zext_1307; // op=pyc.zext +wire [9:0] pyc_zext_1327; // op=pyc.zext +wire [9:0] pyc_zext_1333; // op=pyc.zext +wire [9:0] pyc_zext_1355; // op=pyc.zext +wire [9:0] pyc_zext_1375; // op=pyc.zext +wire [9:0] pyc_zext_1381; // op=pyc.zext +wire [11:0] pyc_zext_139; // op=pyc.zext +wire [9:0] pyc_zext_1403; // op=pyc.zext +wire [9:0] pyc_zext_1423; // op=pyc.zext +wire [9:0] pyc_zext_1429; // op=pyc.zext +wire [12:0] pyc_zext_144; // op=pyc.zext +wire [9:0] pyc_zext_1451; // op=pyc.zext +wire [9:0] pyc_zext_1471; // op=pyc.zext +wire [9:0] pyc_zext_1477; // op=pyc.zext +wire [9:0] pyc_zext_1499; // op=pyc.zext +wire [9:0] pyc_zext_1519; // op=pyc.zext +wire [9:0] pyc_zext_1525; // op=pyc.zext +wire [9:0] pyc_zext_1542; // op=pyc.zext +wire [9:0] pyc_zext_1562; // op=pyc.zext +wire [9:0] pyc_zext_1568; // op=pyc.zext +wire [9:0] pyc_zext_1585; // op=pyc.zext +wire [9:0] pyc_zext_1605; // op=pyc.zext +wire [9:0] pyc_zext_1611; // op=pyc.zext +wire [9:0] pyc_zext_1628; // op=pyc.zext +wire [9:0] pyc_zext_1648; // op=pyc.zext +wire [12:0] pyc_zext_165; // op=pyc.zext +wire [9:0] pyc_zext_1654; // op=pyc.zext +wire [9:0] pyc_zext_1671; // op=pyc.zext +wire [9:0] pyc_zext_1691; // op=pyc.zext +wire [9:0] pyc_zext_1697; // op=pyc.zext +wire [9:0] pyc_zext_1714; // op=pyc.zext +wire [9:0] pyc_zext_1734; // op=pyc.zext +wire [9:0] pyc_zext_1740; // op=pyc.zext +wire [9:0] pyc_zext_1757; // op=pyc.zext +wire [9:0] pyc_zext_1777; // op=pyc.zext +wire [9:0] pyc_zext_1783; // op=pyc.zext +wire [9:0] pyc_zext_1800; // op=pyc.zext +wire [9:0] pyc_zext_1820; // op=pyc.zext +wire [9:0] pyc_zext_1826; // op=pyc.zext +wire [9:0] pyc_zext_1843; // op=pyc.zext +wire [12:0] pyc_zext_185; // op=pyc.zext +wire [9:0] pyc_zext_1863; // op=pyc.zext +wire [15:0] pyc_zext_204; // op=pyc.zext +wire [1:0] pyc_zext_2216; // op=pyc.zext +wire [1:0] pyc_zext_2218; // op=pyc.zext +wire [1:0] pyc_zext_2221; // op=pyc.zext +wire [1:0] pyc_zext_2223; // op=pyc.zext +wire [15:0] pyc_zext_238; // op=pyc.zext +wire [1:0] pyc_zext_2402; // op=pyc.zext +wire [1:0] pyc_zext_2405; // op=pyc.zext +wire [11:0] pyc_zext_243; // op=pyc.zext +wire [11:0] pyc_zext_260; // op=pyc.zext +wire [11:0] pyc_zext_277; // op=pyc.zext +wire [12:0] pyc_zext_282; // op=pyc.zext +wire [12:0] pyc_zext_303; // op=pyc.zext +wire [12:0] pyc_zext_323; // op=pyc.zext +wire [15:0] pyc_zext_342; // op=pyc.zext +wire [15:0] pyc_zext_376; // op=pyc.zext +wire [11:0] pyc_zext_381; // op=pyc.zext +wire [11:0] pyc_zext_398; // op=pyc.zext +wire [11:0] pyc_zext_415; // op=pyc.zext +wire [12:0] pyc_zext_420; // op=pyc.zext +wire [12:0] pyc_zext_441; // op=pyc.zext +wire [12:0] pyc_zext_461; // op=pyc.zext +wire [15:0] pyc_zext_480; // op=pyc.zext +wire [15:0] pyc_zext_514; // op=pyc.zext +wire [11:0] pyc_zext_519; // op=pyc.zext +wire [11:0] pyc_zext_536; // op=pyc.zext +wire [11:0] pyc_zext_553; // op=pyc.zext +wire [12:0] pyc_zext_558; // op=pyc.zext +wire [12:0] pyc_zext_579; // op=pyc.zext +wire [12:0] pyc_zext_599; // op=pyc.zext +wire [15:0] pyc_zext_614; // op=pyc.zext +wire [15:0] pyc_zext_648; // op=pyc.zext +wire [11:0] pyc_zext_653; // op=pyc.zext +wire [15:0] pyc_zext_66; // op=pyc.zext +wire [11:0] pyc_zext_670; // op=pyc.zext +wire [11:0] pyc_zext_687; // op=pyc.zext +wire [12:0] pyc_zext_692; // op=pyc.zext +wire [12:0] pyc_zext_713; // op=pyc.zext +wire [12:0] pyc_zext_733; // op=pyc.zext +wire [15:0] pyc_zext_748; // op=pyc.zext +wire [15:0] pyc_zext_782; // op=pyc.zext +wire [11:0] pyc_zext_787; // op=pyc.zext +wire [11:0] pyc_zext_804; // op=pyc.zext +wire [11:0] pyc_zext_821; // op=pyc.zext +wire [12:0] pyc_zext_826; // op=pyc.zext +wire [12:0] pyc_zext_847; // op=pyc.zext +wire [12:0] pyc_zext_867; // op=pyc.zext +wire [15:0] pyc_zext_882; // op=pyc.zext +wire [15:0] pyc_zext_916; // op=pyc.zext +wire [11:0] pyc_zext_921; // op=pyc.zext +wire [11:0] pyc_zext_938; // op=pyc.zext +wire [11:0] pyc_zext_955; // op=pyc.zext +wire [12:0] pyc_zext_960; // op=pyc.zext +wire [12:0] pyc_zext_981; // op=pyc.zext // --- Combinational (netlist) -assign pe_int_out0 = pyc_reg_599; -assign pe_int_out_vld = pyc_reg_598; -assign pe_int_s0_a = pyc_reg_37; -assign pe_int_s0_b = pyc_reg_38; -assign pe_int_s0_b1 = pyc_reg_39; -assign pe_int_s1_p2a_0 = pyc_reg_437; -assign pe_int_s1_p2a_1 = pyc_reg_438; -assign pe_int_s1_p2a_2 = pyc_reg_439; -assign pe_int_s1_p2a_3 = pyc_reg_440; -assign pe_int_s1_p2a_4 = pyc_reg_441; -assign pe_int_s1_p2a_5 = pyc_reg_442; -assign pe_int_s1_p2a_6 = pyc_reg_443; -assign pe_int_s1_p2a_7 = pyc_reg_444; -assign pe_int_s1_p2b0_0 = pyc_reg_445; -assign pe_int_s1_p2b0_1 = pyc_reg_446; -assign pe_int_s1_p2b0_2 = pyc_reg_447; -assign pe_int_s1_p2b0_3 = pyc_reg_448; -assign pe_int_s1_p2b0_4 = pyc_reg_449; -assign pe_int_s1_p2b0_5 = pyc_reg_450; -assign pe_int_s1_p2b0_6 = pyc_reg_451; -assign pe_int_s1_p2b0_7 = pyc_reg_452; -assign pe_int_s1_p2b1_0 = pyc_reg_453; -assign pe_int_s1_p2b1_1 = pyc_reg_454; -assign pe_int_s1_p2b1_2 = pyc_reg_455; -assign pe_int_s1_p2b1_3 = pyc_reg_456; -assign pe_int_s1_p2b1_4 = pyc_reg_457; -assign pe_int_s1_p2b1_5 = pyc_reg_458; -assign pe_int_s1_p2b1_6 = pyc_reg_459; -assign pe_int_s1_p2b1_7 = pyc_reg_460; -assign pe_int_s1_p2c0_0 = pyc_reg_477; -assign pe_int_s1_p2c0_1 = pyc_reg_478; -assign pe_int_s1_p2c0_10 = pyc_reg_487; -assign pe_int_s1_p2c0_11 = pyc_reg_488; -assign pe_int_s1_p2c0_12 = pyc_reg_489; -assign pe_int_s1_p2c0_13 = pyc_reg_490; -assign pe_int_s1_p2c0_14 = pyc_reg_491; -assign pe_int_s1_p2c0_15 = pyc_reg_492; -assign pe_int_s1_p2c0_2 = pyc_reg_479; -assign pe_int_s1_p2c0_3 = pyc_reg_480; -assign pe_int_s1_p2c0_4 = pyc_reg_481; -assign pe_int_s1_p2c0_5 = pyc_reg_482; -assign pe_int_s1_p2c0_6 = pyc_reg_483; -assign pe_int_s1_p2c0_7 = pyc_reg_484; -assign pe_int_s1_p2c0_8 = pyc_reg_485; -assign pe_int_s1_p2c0_9 = pyc_reg_486; -assign pe_int_s1_p2c1_0 = pyc_reg_493; -assign pe_int_s1_p2c1_1 = pyc_reg_494; -assign pe_int_s1_p2c1_10 = pyc_reg_503; -assign pe_int_s1_p2c1_11 = pyc_reg_504; -assign pe_int_s1_p2c1_12 = pyc_reg_505; -assign pe_int_s1_p2c1_13 = pyc_reg_506; -assign pe_int_s1_p2c1_14 = pyc_reg_507; -assign pe_int_s1_p2c1_15 = pyc_reg_508; -assign pe_int_s1_p2c1_2 = pyc_reg_495; -assign pe_int_s1_p2c1_3 = pyc_reg_496; -assign pe_int_s1_p2c1_4 = pyc_reg_497; -assign pe_int_s1_p2c1_5 = pyc_reg_498; -assign pe_int_s1_p2c1_6 = pyc_reg_499; -assign pe_int_s1_p2c1_7 = pyc_reg_500; -assign pe_int_s1_p2c1_8 = pyc_reg_501; -assign pe_int_s1_p2c1_9 = pyc_reg_502; -assign pe_int_s1_p2d0_0 = pyc_reg_461; -assign pe_int_s1_p2d0_1 = pyc_reg_462; -assign pe_int_s1_p2d0_2 = pyc_reg_463; -assign pe_int_s1_p2d0_3 = pyc_reg_464; -assign pe_int_s1_p2d0_4 = pyc_reg_465; -assign pe_int_s1_p2d0_5 = pyc_reg_466; -assign pe_int_s1_p2d0_6 = pyc_reg_467; -assign pe_int_s1_p2d0_7 = pyc_reg_468; -assign pe_int_s1_p2d1_0 = pyc_reg_469; -assign pe_int_s1_p2d1_1 = pyc_reg_470; -assign pe_int_s1_p2d1_2 = pyc_reg_471; -assign pe_int_s1_p2d1_3 = pyc_reg_472; -assign pe_int_s1_p2d1_4 = pyc_reg_473; -assign pe_int_s1_p2d1_5 = pyc_reg_474; -assign pe_int_s1_p2d1_6 = pyc_reg_475; -assign pe_int_s1_p2d1_7 = pyc_reg_476; -assign pe_int_s2_e1_a = pyc_reg_532; -assign pe_int_s2_e1_b0 = pyc_reg_533; -assign pe_int_s2_e1_b1 = pyc_reg_534; -assign pe_int_s2_s2a = pyc_reg_535; -assign pe_int_s2_s2a__next = pyc_instance_509; -assign pe_int_s2_s2b0 = pyc_reg_536; -assign pe_int_s2_s2b0__next = pyc_instance_510; -assign pe_int_s2_s2b1 = pyc_reg_537; -assign pe_int_s2_s2b1__next = pyc_instance_511; -assign pe_int_s2_s2c0_hi = pyc_reg_541; -assign pe_int_s2_s2c0_hi__next = pyc_instance_515; -assign pe_int_s2_s2c0_lo = pyc_reg_540; -assign pe_int_s2_s2c0_lo__next = pyc_instance_514; -assign pe_int_s2_s2c1_hi__next = pyc_instance_517; -assign pe_int_s2_s2c1_lo = pyc_reg_542; -assign pe_int_s2_s2c1_lo__next = pyc_instance_516; -assign pe_int_s2_s2d0 = pyc_reg_538; -assign pe_int_s2_s2d0__next = pyc_instance_512; -assign pe_int_s2_s2d1 = pyc_reg_539; -assign pe_int_s2_s2d1__next = pyc_instance_513; +assign pe_int_out0 = pyc_reg_2565; +assign pe_int_out_vld = pyc_reg_2564; +assign pe_int_s0_a = pyc_reg_43; +assign pe_int_s0_b = pyc_reg_44; +assign pe_int_s0_b1 = pyc_reg_45; +assign pe_int_s1_p2a_0 = pyc_reg_1955; +assign pe_int_s1_p2a_1 = pyc_reg_1956; +assign pe_int_s1_p2a_2 = pyc_reg_1957; +assign pe_int_s1_p2a_3 = pyc_reg_1958; +assign pe_int_s1_p2a_4 = pyc_reg_1959; +assign pe_int_s1_p2a_5 = pyc_reg_1960; +assign pe_int_s1_p2a_6 = pyc_reg_1961; +assign pe_int_s1_p2a_7 = pyc_reg_1962; +assign pe_int_s1_p2b0_0 = pyc_reg_1963; +assign pe_int_s1_p2b0_1 = pyc_reg_1964; +assign pe_int_s1_p2b0_2 = pyc_reg_1965; +assign pe_int_s1_p2b0_3 = pyc_reg_1966; +assign pe_int_s1_p2b0_4 = pyc_reg_1967; +assign pe_int_s1_p2b0_5 = pyc_reg_1968; +assign pe_int_s1_p2b0_6 = pyc_reg_1969; +assign pe_int_s1_p2b0_7 = pyc_reg_1970; +assign pe_int_s1_p2b1_0 = pyc_reg_1971; +assign pe_int_s1_p2b1_1 = pyc_reg_1972; +assign pe_int_s1_p2b1_2 = pyc_reg_1973; +assign pe_int_s1_p2b1_3 = pyc_reg_1974; +assign pe_int_s1_p2b1_4 = pyc_reg_1975; +assign pe_int_s1_p2b1_5 = pyc_reg_1976; +assign pe_int_s1_p2b1_6 = pyc_reg_1977; +assign pe_int_s1_p2b1_7 = pyc_reg_1978; +assign pe_int_s1_p2c0_0 = pyc_reg_1995; +assign pe_int_s1_p2c0_1 = pyc_reg_1996; +assign pe_int_s1_p2c0_10 = pyc_reg_2005; +assign pe_int_s1_p2c0_11 = pyc_reg_2006; +assign pe_int_s1_p2c0_12 = pyc_reg_2007; +assign pe_int_s1_p2c0_13 = pyc_reg_2008; +assign pe_int_s1_p2c0_14 = pyc_reg_2009; +assign pe_int_s1_p2c0_15 = pyc_reg_2010; +assign pe_int_s1_p2c0_2 = pyc_reg_1997; +assign pe_int_s1_p2c0_3 = pyc_reg_1998; +assign pe_int_s1_p2c0_4 = pyc_reg_1999; +assign pe_int_s1_p2c0_5 = pyc_reg_2000; +assign pe_int_s1_p2c0_6 = pyc_reg_2001; +assign pe_int_s1_p2c0_7 = pyc_reg_2002; +assign pe_int_s1_p2c0_8 = pyc_reg_2003; +assign pe_int_s1_p2c0_9 = pyc_reg_2004; +assign pe_int_s1_p2c1_0 = pyc_reg_2011; +assign pe_int_s1_p2c1_1 = pyc_reg_2012; +assign pe_int_s1_p2c1_10 = pyc_reg_2021; +assign pe_int_s1_p2c1_11 = pyc_reg_2022; +assign pe_int_s1_p2c1_12 = pyc_reg_2023; +assign pe_int_s1_p2c1_13 = pyc_reg_2024; +assign pe_int_s1_p2c1_14 = pyc_reg_2025; +assign pe_int_s1_p2c1_2 = pyc_reg_2013; +assign pe_int_s1_p2c1_3 = pyc_reg_2014; +assign pe_int_s1_p2c1_4 = pyc_reg_2015; +assign pe_int_s1_p2c1_5 = pyc_reg_2016; +assign pe_int_s1_p2c1_6 = pyc_reg_2017; +assign pe_int_s1_p2c1_7 = pyc_reg_2018; +assign pe_int_s1_p2c1_8 = pyc_reg_2019; +assign pe_int_s1_p2c1_9 = pyc_reg_2020; +assign pe_int_s1_p2d0_0 = pyc_reg_1979; +assign pe_int_s1_p2d0_1 = pyc_reg_1980; +assign pe_int_s1_p2d0_2 = pyc_reg_1981; +assign pe_int_s1_p2d0_3 = pyc_reg_1982; +assign pe_int_s1_p2d0_4 = pyc_reg_1983; +assign pe_int_s1_p2d0_5 = pyc_reg_1984; +assign pe_int_s1_p2d0_6 = pyc_reg_1985; +assign pe_int_s1_p2d0_7 = pyc_reg_1986; +assign pe_int_s1_p2d1_0 = pyc_reg_1987; +assign pe_int_s1_p2d1_1 = pyc_reg_1988; +assign pe_int_s1_p2d1_2 = pyc_reg_1989; +assign pe_int_s1_p2d1_3 = pyc_reg_1990; +assign pe_int_s1_p2d1_4 = pyc_reg_1991; +assign pe_int_s1_p2d1_5 = pyc_reg_1992; +assign pe_int_s1_p2d1_6 = pyc_reg_1993; +assign pe_int_s1_p2d1_7 = pyc_reg_1994; +assign pe_int_s2_e1_a = pyc_reg_2203; +assign pe_int_s2_e1_b0 = pyc_reg_2204; +assign pe_int_s2_e1_b1 = pyc_reg_2205; +assign pe_int_s2_s2a = pyc_reg_2206; +assign pe_int_s2_s2b0 = pyc_reg_2207; +assign pe_int_s2_s2b1 = pyc_reg_2208; +assign pe_int_s2_s2c0_hi = pyc_reg_2212; +assign pe_int_s2_s2c0_lo = pyc_reg_2211; +assign pe_int_s2_s2c1_hi__next = pyc_instance_2188; +assign pe_int_s2_s2c1_lo = pyc_reg_2213; +assign pe_int_s2_s2d0 = pyc_reg_2209; +assign pe_int_s2_s2d1 = pyc_reg_2210; assign pyc_constant_1 = 2'd1; -assign pyc_constant_2 = 16'd0; -assign pyc_constant_3 = 19'd0; -assign pyc_constant_4 = 2'd0; -assign pyc_constant_5 = 80'd0; -assign pyc_constant_6 = 2'd2; -assign pyc_constant_7 = 1'd1; -assign pyc_constant_8 = 1'd0; +assign pyc_constant_2 = 19'd0; +assign pyc_constant_3 = 10'd0; +assign pyc_constant_4 = 13'd0; +assign pyc_constant_5 = 12'd0; +assign pyc_constant_6 = 16'd0; +assign pyc_constant_7 = 2'd0; +assign pyc_constant_8 = 80'd0; +assign pyc_constant_9 = 2'd2; +assign pyc_constant_10 = 1'd1; +assign pyc_constant_11 = 1'd0; assign pe_int_s0_e1_b1__next = e1_b1; assign pe_int_s0_e1_b0__next = e1_b0; assign pe_int_s0_e1_a__next = e1_a; @@ -950,1549 +2910,3521 @@ assign pe_int_s0_b1__next = b1; assign pe_int_s0_b__next = b; assign pe_int_s0_a__next = a; assign pe_int_s0_vld__next = vld; -assign pyc_eq_9 = (mode == pyc_constant_4); -assign pe_int_s0_is_2a__next = pyc_eq_9; -assign pyc_eq_10 = (mode == pyc_constant_1); -assign pe_int_s0_is_2b__next = pyc_eq_10; -assign pyc_eq_11 = (mode == pyc_constant_6); -assign pe_int_s0_is_2c__next = pyc_eq_11; -assign pyc_comb_12 = pyc_constant_1; -assign pyc_comb_13 = pyc_constant_2; -assign pyc_comb_14 = pyc_constant_3; -assign pyc_comb_15 = pyc_constant_4; -assign pyc_comb_16 = pyc_constant_5; -assign pyc_comb_17 = pyc_constant_7; -assign pyc_comb_18 = pyc_constant_8; -assign pyc_comb_19 = pe_int_s0_e1_b1__next; -assign pyc_comb_20 = pe_int_s0_e1_b0__next; -assign pyc_comb_21 = pe_int_s0_e1_a__next; -assign pyc_comb_22 = pe_int_s0_b1__next; -assign pyc_comb_23 = pe_int_s0_b__next; -assign pyc_comb_24 = pe_int_s0_a__next; -assign pyc_comb_25 = pe_int_s0_vld__next; -assign pyc_comb_26 = pe_int_s0_is_2a__next; -assign pyc_comb_27 = pe_int_s0_is_2b__next; -assign pyc_comb_28 = pe_int_s0_is_2c__next; -assign pe_int_s0_vld = pyc_reg_29; -assign pe_int_s1_vld__next = pe_int_s0_vld; -assign pyc_comb_30 = pe_int_s1_vld__next; -assign pe_int_s0_is_2a = pyc_reg_31; -assign pe_int_s1_is_2a__next = pe_int_s0_is_2a; -assign pyc_comb_32 = pe_int_s1_is_2a__next; -assign pe_int_s0_is_2b = pyc_reg_33; -assign pe_int_s1_is_2b__next = pe_int_s0_is_2b; -assign pyc_comb_34 = pe_int_s1_is_2b__next; -assign pe_int_s0_e1_b1 = pyc_reg_44; +assign pyc_eq_12 = (mode == pyc_constant_7); +assign pe_int_s0_is_2a__next = pyc_eq_12; +assign pyc_eq_13 = (mode == pyc_constant_1); +assign pe_int_s0_is_2b__next = pyc_eq_13; +assign pyc_eq_14 = (mode == pyc_constant_9); +assign pe_int_s0_is_2c__next = pyc_eq_14; +assign pyc_comb_15 = pyc_constant_1; +assign pyc_comb_16 = pyc_constant_2; +assign pyc_comb_17 = pyc_constant_3; +assign pyc_comb_18 = pyc_constant_4; +assign pyc_comb_19 = pyc_constant_5; +assign pyc_comb_20 = pyc_constant_6; +assign pyc_comb_21 = pyc_constant_7; +assign pyc_comb_22 = pyc_constant_8; +assign pyc_comb_23 = pyc_constant_10; +assign pyc_comb_24 = pyc_constant_11; +assign pyc_comb_25 = pe_int_s0_e1_b1__next; +assign pyc_comb_26 = pe_int_s0_e1_b0__next; +assign pyc_comb_27 = pe_int_s0_e1_a__next; +assign pyc_comb_28 = pe_int_s0_b1__next; +assign pyc_comb_29 = pe_int_s0_b__next; +assign pyc_comb_30 = pe_int_s0_a__next; +assign pyc_comb_31 = pe_int_s0_vld__next; +assign pyc_comb_32 = pe_int_s0_is_2a__next; +assign pyc_comb_33 = pe_int_s0_is_2b__next; +assign pyc_comb_34 = pe_int_s0_is_2c__next; +assign pe_int_s0_e1_b1 = pyc_reg_50; assign pe_int_s1_e1_b1__next = pe_int_s0_e1_b1; -assign pyc_extract_45 = pe_int_s0_b[39:0]; -assign pyc_extract_46 = pe_int_s0_a[4:0]; -assign pyc_extract_47 = pe_int_s0_a[9:5]; -assign pyc_extract_48 = pyc_extract_46[4:1]; -assign pyc_extract_49 = pyc_extract_47[4:1]; -assign pyc_concat_50 = {pyc_extract_49, pyc_extract_48}; -assign pyc_sext_51 = {{11{pyc_concat_50[7]}}, pyc_concat_50}; -assign pyc_sext_52 = {{8{pyc_concat_50[7]}}, pyc_concat_50}; -assign pyc_extract_53 = pe_int_s0_b[4:0]; -assign pyc_extract_54 = pe_int_s0_b[9:5]; +assign pyc_extract_51 = pe_int_s0_b[39:0]; +assign pyc_extract_52 = pe_int_s0_a[4:0]; +assign pyc_extract_53 = pe_int_s0_a[9:5]; +assign pyc_extract_54 = pyc_extract_52[4:1]; assign pyc_extract_55 = pyc_extract_53[4:1]; -assign pyc_extract_56 = pyc_extract_54[4:1]; -assign pyc_concat_57 = {pyc_extract_56, pyc_extract_55}; -assign pyc_sext_58 = {{11{pyc_concat_57[7]}}, pyc_concat_57}; -assign pyc_extract_59 = pyc_extract_45[4:0]; -assign pyc_extract_60 = pyc_extract_59[4:1]; -assign pyc_sext_61 = {{15{pyc_extract_60[3]}}, pyc_extract_60}; -assign pyc_extract_62 = pe_int_s0_b[44:40]; +assign pyc_concat_56 = {pyc_extract_55, pyc_extract_54}; +assign pyc_extract_57 = pe_int_s0_b[4:0]; +assign pyc_extract_58 = pe_int_s0_b[9:5]; +assign pyc_extract_59 = pyc_extract_57[4:1]; +assign pyc_extract_60 = pyc_extract_58[4:1]; +assign pyc_concat_61 = {pyc_extract_60, pyc_extract_59}; +assign pyc_extract_62 = pyc_extract_51[4:0]; assign pyc_extract_63 = pyc_extract_62[4:1]; -assign pyc_sext_64 = {{12{pyc_extract_63[3]}}, pyc_extract_63}; -assign pyc_sext_65 = {{14{pyc_extract_59[4]}}, pyc_extract_59}; -assign pyc_sext_66 = {{11{pyc_extract_62[4]}}, pyc_extract_62}; -assign pyc_mul_67 = (pyc_sext_51 * pyc_sext_58); -assign pe_int_s1_p2a_0__next = pyc_mul_67; -assign pyc_mul_68 = (pyc_sext_51 * pyc_sext_61); -assign pe_int_s1_p2b0_0__next = pyc_mul_68; -assign pyc_mul_69 = (pyc_sext_52 * pyc_sext_64); -assign pe_int_s1_p2b1_0__next = pyc_mul_69; -assign pyc_mul_70 = (pyc_sext_51 * pyc_sext_65); -assign pe_int_s1_p2d0_0__next = pyc_mul_70; -assign pyc_mul_71 = (pyc_sext_52 * pyc_sext_66); -assign pe_int_s1_p2d1_0__next = pyc_mul_71; -assign pyc_extract_72 = pe_int_s0_a[14:10]; -assign pyc_extract_73 = pe_int_s0_a[19:15]; -assign pyc_extract_74 = pyc_extract_72[4:1]; -assign pyc_extract_75 = pyc_extract_73[4:1]; -assign pyc_concat_76 = {pyc_extract_75, pyc_extract_74}; -assign pyc_sext_77 = {{11{pyc_concat_76[7]}}, pyc_concat_76}; -assign pyc_sext_78 = {{8{pyc_concat_76[7]}}, pyc_concat_76}; -assign pyc_extract_79 = pe_int_s0_b[14:10]; -assign pyc_extract_80 = pe_int_s0_b[19:15]; -assign pyc_extract_81 = pyc_extract_79[4:1]; -assign pyc_extract_82 = pyc_extract_80[4:1]; -assign pyc_concat_83 = {pyc_extract_82, pyc_extract_81}; -assign pyc_sext_84 = {{11{pyc_concat_83[7]}}, pyc_concat_83}; -assign pyc_extract_85 = pyc_extract_45[9:5]; -assign pyc_extract_86 = pyc_extract_85[4:1]; -assign pyc_sext_87 = {{15{pyc_extract_86[3]}}, pyc_extract_86}; -assign pyc_extract_88 = pe_int_s0_b[49:45]; -assign pyc_extract_89 = pyc_extract_88[4:1]; -assign pyc_sext_90 = {{12{pyc_extract_89[3]}}, pyc_extract_89}; -assign pyc_sext_91 = {{14{pyc_extract_85[4]}}, pyc_extract_85}; -assign pyc_sext_92 = {{11{pyc_extract_88[4]}}, pyc_extract_88}; -assign pyc_mul_93 = (pyc_sext_77 * pyc_sext_84); -assign pe_int_s1_p2a_1__next = pyc_mul_93; -assign pyc_mul_94 = (pyc_sext_77 * pyc_sext_87); -assign pe_int_s1_p2b0_1__next = pyc_mul_94; -assign pyc_mul_95 = (pyc_sext_78 * pyc_sext_90); -assign pe_int_s1_p2b1_1__next = pyc_mul_95; -assign pyc_mul_96 = (pyc_sext_77 * pyc_sext_91); -assign pe_int_s1_p2d0_1__next = pyc_mul_96; -assign pyc_mul_97 = (pyc_sext_78 * pyc_sext_92); -assign pe_int_s1_p2d1_1__next = pyc_mul_97; -assign pyc_extract_98 = pe_int_s0_a[24:20]; -assign pyc_extract_99 = pe_int_s0_a[29:25]; -assign pyc_extract_100 = pyc_extract_98[4:1]; -assign pyc_extract_101 = pyc_extract_99[4:1]; -assign pyc_concat_102 = {pyc_extract_101, pyc_extract_100}; -assign pyc_sext_103 = {{11{pyc_concat_102[7]}}, pyc_concat_102}; -assign pyc_sext_104 = {{8{pyc_concat_102[7]}}, pyc_concat_102}; -assign pyc_extract_105 = pe_int_s0_b[24:20]; -assign pyc_extract_106 = pe_int_s0_b[29:25]; -assign pyc_extract_107 = pyc_extract_105[4:1]; -assign pyc_extract_108 = pyc_extract_106[4:1]; -assign pyc_concat_109 = {pyc_extract_108, pyc_extract_107}; -assign pyc_sext_110 = {{11{pyc_concat_109[7]}}, pyc_concat_109}; -assign pyc_extract_111 = pyc_extract_45[14:10]; -assign pyc_extract_112 = pyc_extract_111[4:1]; -assign pyc_sext_113 = {{15{pyc_extract_112[3]}}, pyc_extract_112}; -assign pyc_extract_114 = pe_int_s0_b[54:50]; -assign pyc_extract_115 = pyc_extract_114[4:1]; -assign pyc_sext_116 = {{12{pyc_extract_115[3]}}, pyc_extract_115}; -assign pyc_sext_117 = {{14{pyc_extract_111[4]}}, pyc_extract_111}; -assign pyc_sext_118 = {{11{pyc_extract_114[4]}}, pyc_extract_114}; -assign pyc_mul_119 = (pyc_sext_103 * pyc_sext_110); -assign pe_int_s1_p2a_2__next = pyc_mul_119; -assign pyc_mul_120 = (pyc_sext_103 * pyc_sext_113); -assign pe_int_s1_p2b0_2__next = pyc_mul_120; -assign pyc_mul_121 = (pyc_sext_104 * pyc_sext_116); -assign pe_int_s1_p2b1_2__next = pyc_mul_121; -assign pyc_mul_122 = (pyc_sext_103 * pyc_sext_117); -assign pe_int_s1_p2d0_2__next = pyc_mul_122; -assign pyc_mul_123 = (pyc_sext_104 * pyc_sext_118); -assign pe_int_s1_p2d1_2__next = pyc_mul_123; -assign pyc_extract_124 = pe_int_s0_a[34:30]; -assign pyc_extract_125 = pe_int_s0_a[39:35]; -assign pyc_extract_126 = pyc_extract_124[4:1]; -assign pyc_extract_127 = pyc_extract_125[4:1]; -assign pyc_concat_128 = {pyc_extract_127, pyc_extract_126}; -assign pyc_sext_129 = {{11{pyc_concat_128[7]}}, pyc_concat_128}; -assign pyc_sext_130 = {{8{pyc_concat_128[7]}}, pyc_concat_128}; -assign pyc_extract_131 = pe_int_s0_b[34:30]; -assign pyc_extract_132 = pe_int_s0_b[39:35]; -assign pyc_extract_133 = pyc_extract_131[4:1]; -assign pyc_extract_134 = pyc_extract_132[4:1]; -assign pyc_concat_135 = {pyc_extract_134, pyc_extract_133}; -assign pyc_sext_136 = {{11{pyc_concat_135[7]}}, pyc_concat_135}; -assign pyc_extract_137 = pyc_extract_45[19:15]; -assign pyc_extract_138 = pyc_extract_137[4:1]; -assign pyc_sext_139 = {{15{pyc_extract_138[3]}}, pyc_extract_138}; -assign pyc_extract_140 = pe_int_s0_b[59:55]; -assign pyc_extract_141 = pyc_extract_140[4:1]; -assign pyc_sext_142 = {{12{pyc_extract_141[3]}}, pyc_extract_141}; -assign pyc_sext_143 = {{14{pyc_extract_137[4]}}, pyc_extract_137}; -assign pyc_sext_144 = {{11{pyc_extract_140[4]}}, pyc_extract_140}; -assign pyc_mul_145 = (pyc_sext_129 * pyc_sext_136); -assign pe_int_s1_p2a_3__next = pyc_mul_145; -assign pyc_mul_146 = (pyc_sext_129 * pyc_sext_139); -assign pe_int_s1_p2b0_3__next = pyc_mul_146; -assign pyc_mul_147 = (pyc_sext_130 * pyc_sext_142); -assign pe_int_s1_p2b1_3__next = pyc_mul_147; -assign pyc_mul_148 = (pyc_sext_129 * pyc_sext_143); -assign pe_int_s1_p2d0_3__next = pyc_mul_148; -assign pyc_mul_149 = (pyc_sext_130 * pyc_sext_144); -assign pe_int_s1_p2d1_3__next = pyc_mul_149; -assign pyc_extract_150 = pe_int_s0_a[44:40]; -assign pyc_extract_151 = pe_int_s0_a[49:45]; -assign pyc_extract_152 = pyc_extract_150[4:1]; -assign pyc_extract_153 = pyc_extract_151[4:1]; -assign pyc_concat_154 = {pyc_extract_153, pyc_extract_152}; -assign pyc_sext_155 = {{11{pyc_concat_154[7]}}, pyc_concat_154}; -assign pyc_sext_156 = {{8{pyc_concat_154[7]}}, pyc_concat_154}; -assign pyc_concat_157 = {pyc_extract_89, pyc_extract_63}; -assign pyc_sext_158 = {{11{pyc_concat_157[7]}}, pyc_concat_157}; -assign pyc_extract_159 = pyc_extract_45[24:20]; -assign pyc_extract_160 = pyc_extract_159[4:1]; -assign pyc_sext_161 = {{15{pyc_extract_160[3]}}, pyc_extract_160}; -assign pyc_extract_162 = pe_int_s0_b[64:60]; -assign pyc_extract_163 = pyc_extract_162[4:1]; -assign pyc_sext_164 = {{12{pyc_extract_163[3]}}, pyc_extract_163}; -assign pyc_sext_165 = {{14{pyc_extract_159[4]}}, pyc_extract_159}; -assign pyc_sext_166 = {{11{pyc_extract_162[4]}}, pyc_extract_162}; -assign pyc_mul_167 = (pyc_sext_155 * pyc_sext_158); -assign pe_int_s1_p2a_4__next = pyc_mul_167; -assign pyc_mul_168 = (pyc_sext_155 * pyc_sext_161); -assign pe_int_s1_p2b0_4__next = pyc_mul_168; -assign pyc_mul_169 = (pyc_sext_156 * pyc_sext_164); -assign pe_int_s1_p2b1_4__next = pyc_mul_169; -assign pyc_mul_170 = (pyc_sext_155 * pyc_sext_165); -assign pe_int_s1_p2d0_4__next = pyc_mul_170; -assign pyc_mul_171 = (pyc_sext_156 * pyc_sext_166); -assign pe_int_s1_p2d1_4__next = pyc_mul_171; -assign pyc_extract_172 = pe_int_s0_a[54:50]; -assign pyc_extract_173 = pe_int_s0_a[59:55]; -assign pyc_extract_174 = pyc_extract_172[4:1]; -assign pyc_extract_175 = pyc_extract_173[4:1]; -assign pyc_concat_176 = {pyc_extract_175, pyc_extract_174}; -assign pyc_sext_177 = {{11{pyc_concat_176[7]}}, pyc_concat_176}; -assign pyc_sext_178 = {{8{pyc_concat_176[7]}}, pyc_concat_176}; -assign pyc_concat_179 = {pyc_extract_141, pyc_extract_115}; -assign pyc_sext_180 = {{11{pyc_concat_179[7]}}, pyc_concat_179}; -assign pyc_extract_181 = pyc_extract_45[29:25]; -assign pyc_extract_182 = pyc_extract_181[4:1]; -assign pyc_sext_183 = {{15{pyc_extract_182[3]}}, pyc_extract_182}; -assign pyc_extract_184 = pe_int_s0_b[69:65]; -assign pyc_extract_185 = pyc_extract_184[4:1]; -assign pyc_sext_186 = {{12{pyc_extract_185[3]}}, pyc_extract_185}; -assign pyc_sext_187 = {{14{pyc_extract_181[4]}}, pyc_extract_181}; -assign pyc_sext_188 = {{11{pyc_extract_184[4]}}, pyc_extract_184}; -assign pyc_mul_189 = (pyc_sext_177 * pyc_sext_180); -assign pe_int_s1_p2a_5__next = pyc_mul_189; -assign pyc_mul_190 = (pyc_sext_177 * pyc_sext_183); -assign pe_int_s1_p2b0_5__next = pyc_mul_190; -assign pyc_mul_191 = (pyc_sext_178 * pyc_sext_186); -assign pe_int_s1_p2b1_5__next = pyc_mul_191; -assign pyc_mul_192 = (pyc_sext_177 * pyc_sext_187); -assign pe_int_s1_p2d0_5__next = pyc_mul_192; -assign pyc_mul_193 = (pyc_sext_178 * pyc_sext_188); -assign pe_int_s1_p2d1_5__next = pyc_mul_193; -assign pyc_extract_194 = pe_int_s0_a[64:60]; -assign pyc_extract_195 = pe_int_s0_a[69:65]; -assign pyc_extract_196 = pyc_extract_194[4:1]; +assign pyc_extract_64 = pe_int_s0_b[44:40]; +assign pyc_extract_65 = pyc_extract_64[4:1]; +assign pyc_zext_66 = {{8{1'b0}}, pyc_concat_56}; +assign pyc_extract_67 = pyc_concat_61[0]; +assign pyc_mux_68 = (pyc_extract_67 ? pyc_zext_66 : pyc_comb_20); +assign pyc_shli_69 = (pyc_zext_66 << 1); +assign pyc_extract_70 = pyc_concat_61[1]; +assign pyc_mux_71 = (pyc_extract_70 ? pyc_shli_69 : pyc_comb_20); +assign pyc_add_72 = (pyc_mux_68 + pyc_mux_71); +assign pyc_shli_73 = (pyc_zext_66 << 2); +assign pyc_extract_74 = pyc_concat_61[2]; +assign pyc_mux_75 = (pyc_extract_74 ? pyc_shli_73 : pyc_comb_20); +assign pyc_add_76 = (pyc_add_72 + pyc_mux_75); +assign pyc_shli_77 = (pyc_zext_66 << 3); +assign pyc_extract_78 = pyc_concat_61[3]; +assign pyc_mux_79 = (pyc_extract_78 ? pyc_shli_77 : pyc_comb_20); +assign pyc_add_80 = (pyc_add_76 + pyc_mux_79); +assign pyc_shli_81 = (pyc_zext_66 << 4); +assign pyc_extract_82 = pyc_concat_61[4]; +assign pyc_mux_83 = (pyc_extract_82 ? pyc_shli_81 : pyc_comb_20); +assign pyc_add_84 = (pyc_add_80 + pyc_mux_83); +assign pyc_shli_85 = (pyc_zext_66 << 5); +assign pyc_extract_86 = pyc_concat_61[5]; +assign pyc_mux_87 = (pyc_extract_86 ? pyc_shli_85 : pyc_comb_20); +assign pyc_add_88 = (pyc_add_84 + pyc_mux_87); +assign pyc_shli_89 = (pyc_zext_66 << 6); +assign pyc_extract_90 = pyc_concat_61[6]; +assign pyc_mux_91 = (pyc_extract_90 ? pyc_shli_89 : pyc_comb_20); +assign pyc_add_92 = (pyc_add_88 + pyc_mux_91); +assign pyc_shli_93 = (pyc_zext_66 << 7); +assign pyc_extract_94 = pyc_concat_61[7]; +assign pyc_mux_95 = (pyc_extract_94 ? pyc_shli_93 : pyc_comb_20); +assign pyc_add_96 = (pyc_add_92 + pyc_mux_95); +assign pyc_shli_97 = (pyc_zext_66 << 8); +assign pyc_mux_98 = (pyc_extract_94 ? pyc_shli_97 : pyc_comb_20); +assign pyc_extract_99 = pyc_concat_56[7]; +assign pyc_zext_100 = {{8{1'b0}}, pyc_concat_61}; +assign pyc_shli_101 = (pyc_zext_100 << 8); +assign pyc_mux_102 = (pyc_extract_99 ? pyc_shli_101 : pyc_comb_20); +assign pyc_sub_103 = (pyc_add_96 - pyc_mux_98); +assign pyc_sub_104 = (pyc_sub_103 - pyc_mux_102); +assign pe_int_s1_p2a_0__next = pyc_sub_104; +assign pyc_zext_105 = {{4{1'b0}}, pyc_concat_56}; +assign pyc_extract_106 = pyc_extract_63[0]; +assign pyc_mux_107 = (pyc_extract_106 ? pyc_zext_105 : pyc_comb_19); +assign pyc_shli_108 = (pyc_zext_105 << 1); +assign pyc_extract_109 = pyc_extract_63[1]; +assign pyc_mux_110 = (pyc_extract_109 ? pyc_shli_108 : pyc_comb_19); +assign pyc_add_111 = (pyc_mux_107 + pyc_mux_110); +assign pyc_shli_112 = (pyc_zext_105 << 2); +assign pyc_extract_113 = pyc_extract_63[2]; +assign pyc_mux_114 = (pyc_extract_113 ? pyc_shli_112 : pyc_comb_19); +assign pyc_add_115 = (pyc_add_111 + pyc_mux_114); +assign pyc_shli_116 = (pyc_zext_105 << 3); +assign pyc_extract_117 = pyc_extract_63[3]; +assign pyc_mux_118 = (pyc_extract_117 ? pyc_shli_116 : pyc_comb_19); +assign pyc_add_119 = (pyc_add_115 + pyc_mux_118); +assign pyc_shli_120 = (pyc_zext_105 << 4); +assign pyc_mux_121 = (pyc_extract_117 ? pyc_shli_120 : pyc_comb_19); +assign pyc_zext_122 = {{8{1'b0}}, pyc_extract_63}; +assign pyc_shli_123 = (pyc_zext_122 << 8); +assign pyc_mux_124 = (pyc_extract_99 ? pyc_shli_123 : pyc_comb_19); +assign pyc_sub_125 = (pyc_add_119 - pyc_mux_121); +assign pyc_sub_126 = (pyc_sub_125 - pyc_mux_124); +assign pe_int_s1_p2b0_0__next = pyc_sub_126; +assign pyc_extract_127 = pyc_extract_65[0]; +assign pyc_mux_128 = (pyc_extract_127 ? pyc_zext_105 : pyc_comb_19); +assign pyc_extract_129 = pyc_extract_65[1]; +assign pyc_mux_130 = (pyc_extract_129 ? pyc_shli_108 : pyc_comb_19); +assign pyc_add_131 = (pyc_mux_128 + pyc_mux_130); +assign pyc_extract_132 = pyc_extract_65[2]; +assign pyc_mux_133 = (pyc_extract_132 ? pyc_shli_112 : pyc_comb_19); +assign pyc_add_134 = (pyc_add_131 + pyc_mux_133); +assign pyc_extract_135 = pyc_extract_65[3]; +assign pyc_mux_136 = (pyc_extract_135 ? pyc_shli_116 : pyc_comb_19); +assign pyc_add_137 = (pyc_add_134 + pyc_mux_136); +assign pyc_mux_138 = (pyc_extract_135 ? pyc_shli_120 : pyc_comb_19); +assign pyc_zext_139 = {{8{1'b0}}, pyc_extract_65}; +assign pyc_shli_140 = (pyc_zext_139 << 8); +assign pyc_mux_141 = (pyc_extract_99 ? pyc_shli_140 : pyc_comb_19); +assign pyc_sub_142 = (pyc_add_137 - pyc_mux_138); +assign pyc_sub_143 = (pyc_sub_142 - pyc_mux_141); +assign pe_int_s1_p2b1_0__next = pyc_sub_143; +assign pyc_zext_144 = {{5{1'b0}}, pyc_concat_56}; +assign pyc_extract_145 = pyc_extract_62[0]; +assign pyc_mux_146 = (pyc_extract_145 ? pyc_zext_144 : pyc_comb_18); +assign pyc_shli_147 = (pyc_zext_144 << 1); +assign pyc_extract_148 = pyc_extract_62[1]; +assign pyc_mux_149 = (pyc_extract_148 ? pyc_shli_147 : pyc_comb_18); +assign pyc_add_150 = (pyc_mux_146 + pyc_mux_149); +assign pyc_shli_151 = (pyc_zext_144 << 2); +assign pyc_extract_152 = pyc_extract_62[2]; +assign pyc_mux_153 = (pyc_extract_152 ? pyc_shli_151 : pyc_comb_18); +assign pyc_add_154 = (pyc_add_150 + pyc_mux_153); +assign pyc_shli_155 = (pyc_zext_144 << 3); +assign pyc_extract_156 = pyc_extract_62[3]; +assign pyc_mux_157 = (pyc_extract_156 ? pyc_shli_155 : pyc_comb_18); +assign pyc_add_158 = (pyc_add_154 + pyc_mux_157); +assign pyc_shli_159 = (pyc_zext_144 << 4); +assign pyc_extract_160 = pyc_extract_62[4]; +assign pyc_mux_161 = (pyc_extract_160 ? pyc_shli_159 : pyc_comb_18); +assign pyc_add_162 = (pyc_add_158 + pyc_mux_161); +assign pyc_shli_163 = (pyc_zext_144 << 5); +assign pyc_mux_164 = (pyc_extract_160 ? pyc_shli_163 : pyc_comb_18); +assign pyc_zext_165 = {{8{1'b0}}, pyc_extract_62}; +assign pyc_shli_166 = (pyc_zext_165 << 8); +assign pyc_mux_167 = (pyc_extract_99 ? pyc_shli_166 : pyc_comb_18); +assign pyc_sub_168 = (pyc_add_162 - pyc_mux_164); +assign pyc_sub_169 = (pyc_sub_168 - pyc_mux_167); +assign pe_int_s1_p2d0_0__next = pyc_sub_169; +assign pyc_extract_170 = pyc_extract_64[0]; +assign pyc_mux_171 = (pyc_extract_170 ? pyc_zext_144 : pyc_comb_18); +assign pyc_extract_172 = pyc_extract_64[1]; +assign pyc_mux_173 = (pyc_extract_172 ? pyc_shli_147 : pyc_comb_18); +assign pyc_add_174 = (pyc_mux_171 + pyc_mux_173); +assign pyc_extract_175 = pyc_extract_64[2]; +assign pyc_mux_176 = (pyc_extract_175 ? pyc_shli_151 : pyc_comb_18); +assign pyc_add_177 = (pyc_add_174 + pyc_mux_176); +assign pyc_extract_178 = pyc_extract_64[3]; +assign pyc_mux_179 = (pyc_extract_178 ? pyc_shli_155 : pyc_comb_18); +assign pyc_add_180 = (pyc_add_177 + pyc_mux_179); +assign pyc_extract_181 = pyc_extract_64[4]; +assign pyc_mux_182 = (pyc_extract_181 ? pyc_shli_159 : pyc_comb_18); +assign pyc_add_183 = (pyc_add_180 + pyc_mux_182); +assign pyc_mux_184 = (pyc_extract_181 ? pyc_shli_163 : pyc_comb_18); +assign pyc_zext_185 = {{8{1'b0}}, pyc_extract_64}; +assign pyc_shli_186 = (pyc_zext_185 << 8); +assign pyc_mux_187 = (pyc_extract_99 ? pyc_shli_186 : pyc_comb_18); +assign pyc_sub_188 = (pyc_add_183 - pyc_mux_184); +assign pyc_sub_189 = (pyc_sub_188 - pyc_mux_187); +assign pe_int_s1_p2d1_0__next = pyc_sub_189; +assign pyc_extract_190 = pe_int_s0_a[14:10]; +assign pyc_extract_191 = pe_int_s0_a[19:15]; +assign pyc_extract_192 = pyc_extract_190[4:1]; +assign pyc_extract_193 = pyc_extract_191[4:1]; +assign pyc_concat_194 = {pyc_extract_193, pyc_extract_192}; +assign pyc_extract_195 = pe_int_s0_b[14:10]; +assign pyc_extract_196 = pe_int_s0_b[19:15]; assign pyc_extract_197 = pyc_extract_195[4:1]; -assign pyc_concat_198 = {pyc_extract_197, pyc_extract_196}; -assign pyc_sext_199 = {{11{pyc_concat_198[7]}}, pyc_concat_198}; -assign pyc_sext_200 = {{8{pyc_concat_198[7]}}, pyc_concat_198}; -assign pyc_concat_201 = {pyc_extract_185, pyc_extract_163}; -assign pyc_sext_202 = {{11{pyc_concat_201[7]}}, pyc_concat_201}; -assign pyc_extract_203 = pyc_extract_45[34:30]; -assign pyc_extract_204 = pyc_extract_203[4:1]; -assign pyc_sext_205 = {{15{pyc_extract_204[3]}}, pyc_extract_204}; -assign pyc_extract_206 = pe_int_s0_b[74:70]; -assign pyc_extract_207 = pyc_extract_206[4:1]; -assign pyc_sext_208 = {{12{pyc_extract_207[3]}}, pyc_extract_207}; -assign pyc_sext_209 = {{14{pyc_extract_203[4]}}, pyc_extract_203}; -assign pyc_sext_210 = {{11{pyc_extract_206[4]}}, pyc_extract_206}; -assign pyc_mul_211 = (pyc_sext_199 * pyc_sext_202); -assign pe_int_s1_p2a_6__next = pyc_mul_211; -assign pyc_mul_212 = (pyc_sext_199 * pyc_sext_205); -assign pe_int_s1_p2b0_6__next = pyc_mul_212; -assign pyc_mul_213 = (pyc_sext_200 * pyc_sext_208); -assign pe_int_s1_p2b1_6__next = pyc_mul_213; -assign pyc_mul_214 = (pyc_sext_199 * pyc_sext_209); -assign pe_int_s1_p2d0_6__next = pyc_mul_214; -assign pyc_mul_215 = (pyc_sext_200 * pyc_sext_210); -assign pe_int_s1_p2d1_6__next = pyc_mul_215; -assign pyc_extract_216 = pe_int_s0_a[74:70]; -assign pyc_extract_217 = pe_int_s0_a[79:75]; -assign pyc_extract_218 = pyc_extract_216[4:1]; -assign pyc_extract_219 = pyc_extract_217[4:1]; -assign pyc_concat_220 = {pyc_extract_219, pyc_extract_218}; -assign pyc_sext_221 = {{11{pyc_concat_220[7]}}, pyc_concat_220}; -assign pyc_sext_222 = {{8{pyc_concat_220[7]}}, pyc_concat_220}; -assign pyc_extract_223 = pe_int_s0_b[79:75]; -assign pyc_extract_224 = pyc_extract_223[4:1]; -assign pyc_concat_225 = {pyc_extract_224, pyc_extract_207}; -assign pyc_sext_226 = {{11{pyc_concat_225[7]}}, pyc_concat_225}; -assign pyc_extract_227 = pyc_extract_45[39:35]; -assign pyc_extract_228 = pyc_extract_227[4:1]; -assign pyc_sext_229 = {{15{pyc_extract_228[3]}}, pyc_extract_228}; -assign pyc_sext_230 = {{12{pyc_extract_224[3]}}, pyc_extract_224}; -assign pyc_sext_231 = {{14{pyc_extract_227[4]}}, pyc_extract_227}; -assign pyc_sext_232 = {{11{pyc_extract_223[4]}}, pyc_extract_223}; -assign pyc_mul_233 = (pyc_sext_221 * pyc_sext_226); -assign pe_int_s1_p2a_7__next = pyc_mul_233; -assign pyc_mul_234 = (pyc_sext_221 * pyc_sext_229); -assign pe_int_s1_p2b0_7__next = pyc_mul_234; -assign pyc_mul_235 = (pyc_sext_222 * pyc_sext_230); -assign pe_int_s1_p2b1_7__next = pyc_mul_235; -assign pyc_mul_236 = (pyc_sext_221 * pyc_sext_231); -assign pe_int_s1_p2d0_7__next = pyc_mul_236; -assign pyc_mul_237 = (pyc_sext_222 * pyc_sext_232); -assign pe_int_s1_p2d1_7__next = pyc_mul_237; -assign pyc_sext_238 = {{14{pyc_extract_46[4]}}, pyc_extract_46}; -assign pyc_sext_239 = {{11{pyc_extract_46[4]}}, pyc_extract_46}; -assign pyc_sext_240 = {{14{pyc_extract_53[4]}}, pyc_extract_53}; -assign pyc_extract_241 = pe_int_s0_b1[4:0]; -assign pyc_sext_242 = {{11{pyc_extract_241[4]}}, pyc_extract_241}; -assign pyc_mul_243 = (pyc_sext_238 * pyc_sext_240); -assign pe_int_s1_p2c0_0__next = pyc_mul_243; -assign pyc_mul_244 = (pyc_sext_239 * pyc_sext_242); -assign pe_int_s1_p2c1_0__next = pyc_mul_244; -assign pyc_sext_245 = {{14{pyc_extract_47[4]}}, pyc_extract_47}; -assign pyc_sext_246 = {{11{pyc_extract_47[4]}}, pyc_extract_47}; -assign pyc_sext_247 = {{14{pyc_extract_54[4]}}, pyc_extract_54}; -assign pyc_extract_248 = pe_int_s0_b1[9:5]; -assign pyc_sext_249 = {{11{pyc_extract_248[4]}}, pyc_extract_248}; -assign pyc_mul_250 = (pyc_sext_245 * pyc_sext_247); -assign pe_int_s1_p2c0_1__next = pyc_mul_250; -assign pyc_mul_251 = (pyc_sext_246 * pyc_sext_249); -assign pe_int_s1_p2c1_1__next = pyc_mul_251; -assign pyc_sext_252 = {{14{pyc_extract_72[4]}}, pyc_extract_72}; -assign pyc_sext_253 = {{11{pyc_extract_72[4]}}, pyc_extract_72}; -assign pyc_sext_254 = {{14{pyc_extract_79[4]}}, pyc_extract_79}; -assign pyc_extract_255 = pe_int_s0_b1[14:10]; -assign pyc_sext_256 = {{11{pyc_extract_255[4]}}, pyc_extract_255}; -assign pyc_mul_257 = (pyc_sext_252 * pyc_sext_254); -assign pe_int_s1_p2c0_2__next = pyc_mul_257; -assign pyc_mul_258 = (pyc_sext_253 * pyc_sext_256); -assign pe_int_s1_p2c1_2__next = pyc_mul_258; -assign pyc_sext_259 = {{14{pyc_extract_73[4]}}, pyc_extract_73}; -assign pyc_sext_260 = {{11{pyc_extract_73[4]}}, pyc_extract_73}; -assign pyc_sext_261 = {{14{pyc_extract_80[4]}}, pyc_extract_80}; -assign pyc_extract_262 = pe_int_s0_b1[19:15]; -assign pyc_sext_263 = {{11{pyc_extract_262[4]}}, pyc_extract_262}; -assign pyc_mul_264 = (pyc_sext_259 * pyc_sext_261); -assign pe_int_s1_p2c0_3__next = pyc_mul_264; -assign pyc_mul_265 = (pyc_sext_260 * pyc_sext_263); -assign pe_int_s1_p2c1_3__next = pyc_mul_265; -assign pyc_sext_266 = {{14{pyc_extract_98[4]}}, pyc_extract_98}; -assign pyc_sext_267 = {{11{pyc_extract_98[4]}}, pyc_extract_98}; -assign pyc_sext_268 = {{14{pyc_extract_105[4]}}, pyc_extract_105}; -assign pyc_extract_269 = pe_int_s0_b1[24:20]; -assign pyc_sext_270 = {{11{pyc_extract_269[4]}}, pyc_extract_269}; -assign pyc_mul_271 = (pyc_sext_266 * pyc_sext_268); -assign pe_int_s1_p2c0_4__next = pyc_mul_271; -assign pyc_mul_272 = (pyc_sext_267 * pyc_sext_270); -assign pe_int_s1_p2c1_4__next = pyc_mul_272; -assign pyc_sext_273 = {{14{pyc_extract_99[4]}}, pyc_extract_99}; -assign pyc_sext_274 = {{11{pyc_extract_99[4]}}, pyc_extract_99}; -assign pyc_sext_275 = {{14{pyc_extract_106[4]}}, pyc_extract_106}; -assign pyc_extract_276 = pe_int_s0_b1[29:25]; -assign pyc_sext_277 = {{11{pyc_extract_276[4]}}, pyc_extract_276}; -assign pyc_mul_278 = (pyc_sext_273 * pyc_sext_275); -assign pe_int_s1_p2c0_5__next = pyc_mul_278; -assign pyc_mul_279 = (pyc_sext_274 * pyc_sext_277); -assign pe_int_s1_p2c1_5__next = pyc_mul_279; -assign pyc_sext_280 = {{14{pyc_extract_124[4]}}, pyc_extract_124}; -assign pyc_sext_281 = {{11{pyc_extract_124[4]}}, pyc_extract_124}; -assign pyc_sext_282 = {{14{pyc_extract_131[4]}}, pyc_extract_131}; -assign pyc_extract_283 = pe_int_s0_b1[34:30]; -assign pyc_sext_284 = {{11{pyc_extract_283[4]}}, pyc_extract_283}; -assign pyc_mul_285 = (pyc_sext_280 * pyc_sext_282); -assign pe_int_s1_p2c0_6__next = pyc_mul_285; -assign pyc_mul_286 = (pyc_sext_281 * pyc_sext_284); -assign pe_int_s1_p2c1_6__next = pyc_mul_286; -assign pyc_sext_287 = {{14{pyc_extract_125[4]}}, pyc_extract_125}; -assign pyc_sext_288 = {{11{pyc_extract_125[4]}}, pyc_extract_125}; -assign pyc_sext_289 = {{14{pyc_extract_132[4]}}, pyc_extract_132}; -assign pyc_extract_290 = pe_int_s0_b1[39:35]; -assign pyc_sext_291 = {{11{pyc_extract_290[4]}}, pyc_extract_290}; -assign pyc_mul_292 = (pyc_sext_287 * pyc_sext_289); -assign pe_int_s1_p2c0_7__next = pyc_mul_292; -assign pyc_mul_293 = (pyc_sext_288 * pyc_sext_291); -assign pe_int_s1_p2c1_7__next = pyc_mul_293; -assign pyc_sext_294 = {{14{pyc_extract_150[4]}}, pyc_extract_150}; -assign pyc_sext_295 = {{11{pyc_extract_150[4]}}, pyc_extract_150}; -assign pyc_sext_296 = {{14{pyc_extract_62[4]}}, pyc_extract_62}; -assign pyc_extract_297 = pe_int_s0_b1[44:40]; -assign pyc_sext_298 = {{11{pyc_extract_297[4]}}, pyc_extract_297}; -assign pyc_mul_299 = (pyc_sext_294 * pyc_sext_296); -assign pe_int_s1_p2c0_8__next = pyc_mul_299; -assign pyc_mul_300 = (pyc_sext_295 * pyc_sext_298); -assign pe_int_s1_p2c1_8__next = pyc_mul_300; -assign pyc_sext_301 = {{14{pyc_extract_151[4]}}, pyc_extract_151}; -assign pyc_sext_302 = {{11{pyc_extract_151[4]}}, pyc_extract_151}; -assign pyc_sext_303 = {{14{pyc_extract_88[4]}}, pyc_extract_88}; -assign pyc_extract_304 = pe_int_s0_b1[49:45]; -assign pyc_sext_305 = {{11{pyc_extract_304[4]}}, pyc_extract_304}; -assign pyc_mul_306 = (pyc_sext_301 * pyc_sext_303); -assign pe_int_s1_p2c0_9__next = pyc_mul_306; -assign pyc_mul_307 = (pyc_sext_302 * pyc_sext_305); -assign pe_int_s1_p2c1_9__next = pyc_mul_307; -assign pyc_sext_308 = {{14{pyc_extract_172[4]}}, pyc_extract_172}; -assign pyc_sext_309 = {{11{pyc_extract_172[4]}}, pyc_extract_172}; -assign pyc_sext_310 = {{14{pyc_extract_114[4]}}, pyc_extract_114}; -assign pyc_extract_311 = pe_int_s0_b1[54:50]; -assign pyc_sext_312 = {{11{pyc_extract_311[4]}}, pyc_extract_311}; -assign pyc_mul_313 = (pyc_sext_308 * pyc_sext_310); -assign pe_int_s1_p2c0_10__next = pyc_mul_313; -assign pyc_mul_314 = (pyc_sext_309 * pyc_sext_312); -assign pe_int_s1_p2c1_10__next = pyc_mul_314; -assign pyc_sext_315 = {{14{pyc_extract_173[4]}}, pyc_extract_173}; -assign pyc_sext_316 = {{11{pyc_extract_173[4]}}, pyc_extract_173}; -assign pyc_sext_317 = {{14{pyc_extract_140[4]}}, pyc_extract_140}; -assign pyc_extract_318 = pe_int_s0_b1[59:55]; -assign pyc_sext_319 = {{11{pyc_extract_318[4]}}, pyc_extract_318}; -assign pyc_mul_320 = (pyc_sext_315 * pyc_sext_317); -assign pe_int_s1_p2c0_11__next = pyc_mul_320; -assign pyc_mul_321 = (pyc_sext_316 * pyc_sext_319); -assign pe_int_s1_p2c1_11__next = pyc_mul_321; -assign pyc_sext_322 = {{14{pyc_extract_194[4]}}, pyc_extract_194}; -assign pyc_sext_323 = {{11{pyc_extract_194[4]}}, pyc_extract_194}; -assign pyc_sext_324 = {{14{pyc_extract_162[4]}}, pyc_extract_162}; -assign pyc_extract_325 = pe_int_s0_b1[64:60]; -assign pyc_sext_326 = {{11{pyc_extract_325[4]}}, pyc_extract_325}; -assign pyc_mul_327 = (pyc_sext_322 * pyc_sext_324); -assign pe_int_s1_p2c0_12__next = pyc_mul_327; -assign pyc_mul_328 = (pyc_sext_323 * pyc_sext_326); -assign pe_int_s1_p2c1_12__next = pyc_mul_328; -assign pyc_sext_329 = {{14{pyc_extract_195[4]}}, pyc_extract_195}; -assign pyc_sext_330 = {{11{pyc_extract_195[4]}}, pyc_extract_195}; -assign pyc_sext_331 = {{14{pyc_extract_184[4]}}, pyc_extract_184}; -assign pyc_extract_332 = pe_int_s0_b1[69:65]; -assign pyc_sext_333 = {{11{pyc_extract_332[4]}}, pyc_extract_332}; -assign pyc_mul_334 = (pyc_sext_329 * pyc_sext_331); -assign pe_int_s1_p2c0_13__next = pyc_mul_334; -assign pyc_mul_335 = (pyc_sext_330 * pyc_sext_333); -assign pe_int_s1_p2c1_13__next = pyc_mul_335; -assign pyc_sext_336 = {{14{pyc_extract_216[4]}}, pyc_extract_216}; -assign pyc_sext_337 = {{11{pyc_extract_216[4]}}, pyc_extract_216}; -assign pyc_sext_338 = {{14{pyc_extract_206[4]}}, pyc_extract_206}; -assign pyc_extract_339 = pe_int_s0_b1[74:70]; -assign pyc_sext_340 = {{11{pyc_extract_339[4]}}, pyc_extract_339}; -assign pyc_mul_341 = (pyc_sext_336 * pyc_sext_338); -assign pe_int_s1_p2c0_14__next = pyc_mul_341; -assign pyc_mul_342 = (pyc_sext_337 * pyc_sext_340); -assign pe_int_s1_p2c1_14__next = pyc_mul_342; -assign pyc_sext_343 = {{14{pyc_extract_217[4]}}, pyc_extract_217}; -assign pyc_sext_344 = {{11{pyc_extract_217[4]}}, pyc_extract_217}; -assign pyc_sext_345 = {{14{pyc_extract_223[4]}}, pyc_extract_223}; -assign pyc_extract_346 = pe_int_s0_b1[79:75]; -assign pyc_sext_347 = {{11{pyc_extract_346[4]}}, pyc_extract_346}; -assign pyc_mul_348 = (pyc_sext_343 * pyc_sext_345); -assign pe_int_s1_p2c0_15__next = pyc_mul_348; -assign pyc_mul_349 = (pyc_sext_344 * pyc_sext_347); -assign pe_int_s1_p2c1_15__next = pyc_mul_349; -assign pyc_comb_350 = pe_int_s1_e1_b1__next; -assign pyc_comb_351 = pe_int_s1_p2a_0__next; -assign pyc_comb_352 = pe_int_s1_p2b0_0__next; -assign pyc_comb_353 = pe_int_s1_p2b1_0__next; -assign pyc_comb_354 = pe_int_s1_p2d0_0__next; -assign pyc_comb_355 = pe_int_s1_p2d1_0__next; -assign pyc_comb_356 = pe_int_s1_p2a_1__next; -assign pyc_comb_357 = pe_int_s1_p2b0_1__next; -assign pyc_comb_358 = pe_int_s1_p2b1_1__next; -assign pyc_comb_359 = pe_int_s1_p2d0_1__next; -assign pyc_comb_360 = pe_int_s1_p2d1_1__next; -assign pyc_comb_361 = pe_int_s1_p2a_2__next; -assign pyc_comb_362 = pe_int_s1_p2b0_2__next; -assign pyc_comb_363 = pe_int_s1_p2b1_2__next; -assign pyc_comb_364 = pe_int_s1_p2d0_2__next; -assign pyc_comb_365 = pe_int_s1_p2d1_2__next; -assign pyc_comb_366 = pe_int_s1_p2a_3__next; -assign pyc_comb_367 = pe_int_s1_p2b0_3__next; -assign pyc_comb_368 = pe_int_s1_p2b1_3__next; -assign pyc_comb_369 = pe_int_s1_p2d0_3__next; -assign pyc_comb_370 = pe_int_s1_p2d1_3__next; -assign pyc_comb_371 = pe_int_s1_p2a_4__next; -assign pyc_comb_372 = pe_int_s1_p2b0_4__next; -assign pyc_comb_373 = pe_int_s1_p2b1_4__next; -assign pyc_comb_374 = pe_int_s1_p2d0_4__next; -assign pyc_comb_375 = pe_int_s1_p2d1_4__next; -assign pyc_comb_376 = pe_int_s1_p2a_5__next; -assign pyc_comb_377 = pe_int_s1_p2b0_5__next; -assign pyc_comb_378 = pe_int_s1_p2b1_5__next; -assign pyc_comb_379 = pe_int_s1_p2d0_5__next; -assign pyc_comb_380 = pe_int_s1_p2d1_5__next; -assign pyc_comb_381 = pe_int_s1_p2a_6__next; -assign pyc_comb_382 = pe_int_s1_p2b0_6__next; -assign pyc_comb_383 = pe_int_s1_p2b1_6__next; -assign pyc_comb_384 = pe_int_s1_p2d0_6__next; -assign pyc_comb_385 = pe_int_s1_p2d1_6__next; -assign pyc_comb_386 = pe_int_s1_p2a_7__next; -assign pyc_comb_387 = pe_int_s1_p2b0_7__next; -assign pyc_comb_388 = pe_int_s1_p2b1_7__next; -assign pyc_comb_389 = pe_int_s1_p2d0_7__next; -assign pyc_comb_390 = pe_int_s1_p2d1_7__next; -assign pyc_comb_391 = pe_int_s1_p2c0_0__next; -assign pyc_comb_392 = pe_int_s1_p2c1_0__next; -assign pyc_comb_393 = pe_int_s1_p2c0_1__next; -assign pyc_comb_394 = pe_int_s1_p2c1_1__next; -assign pyc_comb_395 = pe_int_s1_p2c0_2__next; -assign pyc_comb_396 = pe_int_s1_p2c1_2__next; -assign pyc_comb_397 = pe_int_s1_p2c0_3__next; -assign pyc_comb_398 = pe_int_s1_p2c1_3__next; -assign pyc_comb_399 = pe_int_s1_p2c0_4__next; -assign pyc_comb_400 = pe_int_s1_p2c1_4__next; -assign pyc_comb_401 = pe_int_s1_p2c0_5__next; -assign pyc_comb_402 = pe_int_s1_p2c1_5__next; -assign pyc_comb_403 = pe_int_s1_p2c0_6__next; -assign pyc_comb_404 = pe_int_s1_p2c1_6__next; -assign pyc_comb_405 = pe_int_s1_p2c0_7__next; -assign pyc_comb_406 = pe_int_s1_p2c1_7__next; -assign pyc_comb_407 = pe_int_s1_p2c0_8__next; -assign pyc_comb_408 = pe_int_s1_p2c1_8__next; -assign pyc_comb_409 = pe_int_s1_p2c0_9__next; -assign pyc_comb_410 = pe_int_s1_p2c1_9__next; -assign pyc_comb_411 = pe_int_s1_p2c0_10__next; -assign pyc_comb_412 = pe_int_s1_p2c1_10__next; -assign pyc_comb_413 = pe_int_s1_p2c0_11__next; -assign pyc_comb_414 = pe_int_s1_p2c1_11__next; -assign pyc_comb_415 = pe_int_s1_p2c0_12__next; -assign pyc_comb_416 = pe_int_s1_p2c1_12__next; -assign pyc_comb_417 = pe_int_s1_p2c0_13__next; -assign pyc_comb_418 = pe_int_s1_p2c1_13__next; -assign pyc_comb_419 = pe_int_s1_p2c0_14__next; -assign pyc_comb_420 = pe_int_s1_p2c1_14__next; -assign pyc_comb_421 = pe_int_s1_p2c0_15__next; -assign pyc_comb_422 = pe_int_s1_p2c1_15__next; -assign pe_int_s0_is_2c = pyc_reg_35; -assign pe_int_s1_is_2c__next = pe_int_s0_is_2c; -assign pyc_comb_36 = pe_int_s1_is_2c__next; -assign pe_int_s0_e1_a = pyc_reg_40; -assign pe_int_s1_e1_a__next = pe_int_s0_e1_a; -assign pyc_comb_41 = pe_int_s1_e1_a__next; -assign pe_int_s1_vld = pyc_reg_423; +assign pyc_extract_198 = pyc_extract_196[4:1]; +assign pyc_concat_199 = {pyc_extract_198, pyc_extract_197}; +assign pyc_extract_200 = pyc_extract_51[9:5]; +assign pyc_extract_201 = pyc_extract_200[4:1]; +assign pyc_extract_202 = pe_int_s0_b[49:45]; +assign pyc_extract_203 = pyc_extract_202[4:1]; +assign pyc_zext_204 = {{8{1'b0}}, pyc_concat_194}; +assign pyc_extract_205 = pyc_concat_199[0]; +assign pyc_mux_206 = (pyc_extract_205 ? pyc_zext_204 : pyc_comb_20); +assign pyc_shli_207 = (pyc_zext_204 << 1); +assign pyc_extract_208 = pyc_concat_199[1]; +assign pyc_mux_209 = (pyc_extract_208 ? pyc_shli_207 : pyc_comb_20); +assign pyc_add_210 = (pyc_mux_206 + pyc_mux_209); +assign pyc_shli_211 = (pyc_zext_204 << 2); +assign pyc_extract_212 = pyc_concat_199[2]; +assign pyc_mux_213 = (pyc_extract_212 ? pyc_shli_211 : pyc_comb_20); +assign pyc_add_214 = (pyc_add_210 + pyc_mux_213); +assign pyc_shli_215 = (pyc_zext_204 << 3); +assign pyc_extract_216 = pyc_concat_199[3]; +assign pyc_mux_217 = (pyc_extract_216 ? pyc_shli_215 : pyc_comb_20); +assign pyc_add_218 = (pyc_add_214 + pyc_mux_217); +assign pyc_shli_219 = (pyc_zext_204 << 4); +assign pyc_extract_220 = pyc_concat_199[4]; +assign pyc_mux_221 = (pyc_extract_220 ? pyc_shli_219 : pyc_comb_20); +assign pyc_add_222 = (pyc_add_218 + pyc_mux_221); +assign pyc_shli_223 = (pyc_zext_204 << 5); +assign pyc_extract_224 = pyc_concat_199[5]; +assign pyc_mux_225 = (pyc_extract_224 ? pyc_shli_223 : pyc_comb_20); +assign pyc_add_226 = (pyc_add_222 + pyc_mux_225); +assign pyc_shli_227 = (pyc_zext_204 << 6); +assign pyc_extract_228 = pyc_concat_199[6]; +assign pyc_mux_229 = (pyc_extract_228 ? pyc_shli_227 : pyc_comb_20); +assign pyc_add_230 = (pyc_add_226 + pyc_mux_229); +assign pyc_shli_231 = (pyc_zext_204 << 7); +assign pyc_extract_232 = pyc_concat_199[7]; +assign pyc_mux_233 = (pyc_extract_232 ? pyc_shli_231 : pyc_comb_20); +assign pyc_add_234 = (pyc_add_230 + pyc_mux_233); +assign pyc_shli_235 = (pyc_zext_204 << 8); +assign pyc_mux_236 = (pyc_extract_232 ? pyc_shli_235 : pyc_comb_20); +assign pyc_extract_237 = pyc_concat_194[7]; +assign pyc_zext_238 = {{8{1'b0}}, pyc_concat_199}; +assign pyc_shli_239 = (pyc_zext_238 << 8); +assign pyc_mux_240 = (pyc_extract_237 ? pyc_shli_239 : pyc_comb_20); +assign pyc_sub_241 = (pyc_add_234 - pyc_mux_236); +assign pyc_sub_242 = (pyc_sub_241 - pyc_mux_240); +assign pe_int_s1_p2a_1__next = pyc_sub_242; +assign pyc_zext_243 = {{4{1'b0}}, pyc_concat_194}; +assign pyc_extract_244 = pyc_extract_201[0]; +assign pyc_mux_245 = (pyc_extract_244 ? pyc_zext_243 : pyc_comb_19); +assign pyc_shli_246 = (pyc_zext_243 << 1); +assign pyc_extract_247 = pyc_extract_201[1]; +assign pyc_mux_248 = (pyc_extract_247 ? pyc_shli_246 : pyc_comb_19); +assign pyc_add_249 = (pyc_mux_245 + pyc_mux_248); +assign pyc_shli_250 = (pyc_zext_243 << 2); +assign pyc_extract_251 = pyc_extract_201[2]; +assign pyc_mux_252 = (pyc_extract_251 ? pyc_shli_250 : pyc_comb_19); +assign pyc_add_253 = (pyc_add_249 + pyc_mux_252); +assign pyc_shli_254 = (pyc_zext_243 << 3); +assign pyc_extract_255 = pyc_extract_201[3]; +assign pyc_mux_256 = (pyc_extract_255 ? pyc_shli_254 : pyc_comb_19); +assign pyc_add_257 = (pyc_add_253 + pyc_mux_256); +assign pyc_shli_258 = (pyc_zext_243 << 4); +assign pyc_mux_259 = (pyc_extract_255 ? pyc_shli_258 : pyc_comb_19); +assign pyc_zext_260 = {{8{1'b0}}, pyc_extract_201}; +assign pyc_shli_261 = (pyc_zext_260 << 8); +assign pyc_mux_262 = (pyc_extract_237 ? pyc_shli_261 : pyc_comb_19); +assign pyc_sub_263 = (pyc_add_257 - pyc_mux_259); +assign pyc_sub_264 = (pyc_sub_263 - pyc_mux_262); +assign pe_int_s1_p2b0_1__next = pyc_sub_264; +assign pyc_extract_265 = pyc_extract_203[0]; +assign pyc_mux_266 = (pyc_extract_265 ? pyc_zext_243 : pyc_comb_19); +assign pyc_extract_267 = pyc_extract_203[1]; +assign pyc_mux_268 = (pyc_extract_267 ? pyc_shli_246 : pyc_comb_19); +assign pyc_add_269 = (pyc_mux_266 + pyc_mux_268); +assign pyc_extract_270 = pyc_extract_203[2]; +assign pyc_mux_271 = (pyc_extract_270 ? pyc_shli_250 : pyc_comb_19); +assign pyc_add_272 = (pyc_add_269 + pyc_mux_271); +assign pyc_extract_273 = pyc_extract_203[3]; +assign pyc_mux_274 = (pyc_extract_273 ? pyc_shli_254 : pyc_comb_19); +assign pyc_add_275 = (pyc_add_272 + pyc_mux_274); +assign pyc_mux_276 = (pyc_extract_273 ? pyc_shli_258 : pyc_comb_19); +assign pyc_zext_277 = {{8{1'b0}}, pyc_extract_203}; +assign pyc_shli_278 = (pyc_zext_277 << 8); +assign pyc_mux_279 = (pyc_extract_237 ? pyc_shli_278 : pyc_comb_19); +assign pyc_sub_280 = (pyc_add_275 - pyc_mux_276); +assign pyc_sub_281 = (pyc_sub_280 - pyc_mux_279); +assign pe_int_s1_p2b1_1__next = pyc_sub_281; +assign pyc_zext_282 = {{5{1'b0}}, pyc_concat_194}; +assign pyc_extract_283 = pyc_extract_200[0]; +assign pyc_mux_284 = (pyc_extract_283 ? pyc_zext_282 : pyc_comb_18); +assign pyc_shli_285 = (pyc_zext_282 << 1); +assign pyc_extract_286 = pyc_extract_200[1]; +assign pyc_mux_287 = (pyc_extract_286 ? pyc_shli_285 : pyc_comb_18); +assign pyc_add_288 = (pyc_mux_284 + pyc_mux_287); +assign pyc_shli_289 = (pyc_zext_282 << 2); +assign pyc_extract_290 = pyc_extract_200[2]; +assign pyc_mux_291 = (pyc_extract_290 ? pyc_shli_289 : pyc_comb_18); +assign pyc_add_292 = (pyc_add_288 + pyc_mux_291); +assign pyc_shli_293 = (pyc_zext_282 << 3); +assign pyc_extract_294 = pyc_extract_200[3]; +assign pyc_mux_295 = (pyc_extract_294 ? pyc_shli_293 : pyc_comb_18); +assign pyc_add_296 = (pyc_add_292 + pyc_mux_295); +assign pyc_shli_297 = (pyc_zext_282 << 4); +assign pyc_extract_298 = pyc_extract_200[4]; +assign pyc_mux_299 = (pyc_extract_298 ? pyc_shli_297 : pyc_comb_18); +assign pyc_add_300 = (pyc_add_296 + pyc_mux_299); +assign pyc_shli_301 = (pyc_zext_282 << 5); +assign pyc_mux_302 = (pyc_extract_298 ? pyc_shli_301 : pyc_comb_18); +assign pyc_zext_303 = {{8{1'b0}}, pyc_extract_200}; +assign pyc_shli_304 = (pyc_zext_303 << 8); +assign pyc_mux_305 = (pyc_extract_237 ? pyc_shli_304 : pyc_comb_18); +assign pyc_sub_306 = (pyc_add_300 - pyc_mux_302); +assign pyc_sub_307 = (pyc_sub_306 - pyc_mux_305); +assign pe_int_s1_p2d0_1__next = pyc_sub_307; +assign pyc_extract_308 = pyc_extract_202[0]; +assign pyc_mux_309 = (pyc_extract_308 ? pyc_zext_282 : pyc_comb_18); +assign pyc_extract_310 = pyc_extract_202[1]; +assign pyc_mux_311 = (pyc_extract_310 ? pyc_shli_285 : pyc_comb_18); +assign pyc_add_312 = (pyc_mux_309 + pyc_mux_311); +assign pyc_extract_313 = pyc_extract_202[2]; +assign pyc_mux_314 = (pyc_extract_313 ? pyc_shli_289 : pyc_comb_18); +assign pyc_add_315 = (pyc_add_312 + pyc_mux_314); +assign pyc_extract_316 = pyc_extract_202[3]; +assign pyc_mux_317 = (pyc_extract_316 ? pyc_shli_293 : pyc_comb_18); +assign pyc_add_318 = (pyc_add_315 + pyc_mux_317); +assign pyc_extract_319 = pyc_extract_202[4]; +assign pyc_mux_320 = (pyc_extract_319 ? pyc_shli_297 : pyc_comb_18); +assign pyc_add_321 = (pyc_add_318 + pyc_mux_320); +assign pyc_mux_322 = (pyc_extract_319 ? pyc_shli_301 : pyc_comb_18); +assign pyc_zext_323 = {{8{1'b0}}, pyc_extract_202}; +assign pyc_shli_324 = (pyc_zext_323 << 8); +assign pyc_mux_325 = (pyc_extract_237 ? pyc_shli_324 : pyc_comb_18); +assign pyc_sub_326 = (pyc_add_321 - pyc_mux_322); +assign pyc_sub_327 = (pyc_sub_326 - pyc_mux_325); +assign pe_int_s1_p2d1_1__next = pyc_sub_327; +assign pyc_extract_328 = pe_int_s0_a[24:20]; +assign pyc_extract_329 = pe_int_s0_a[29:25]; +assign pyc_extract_330 = pyc_extract_328[4:1]; +assign pyc_extract_331 = pyc_extract_329[4:1]; +assign pyc_concat_332 = {pyc_extract_331, pyc_extract_330}; +assign pyc_extract_333 = pe_int_s0_b[24:20]; +assign pyc_extract_334 = pe_int_s0_b[29:25]; +assign pyc_extract_335 = pyc_extract_333[4:1]; +assign pyc_extract_336 = pyc_extract_334[4:1]; +assign pyc_concat_337 = {pyc_extract_336, pyc_extract_335}; +assign pyc_extract_338 = pyc_extract_51[14:10]; +assign pyc_extract_339 = pyc_extract_338[4:1]; +assign pyc_extract_340 = pe_int_s0_b[54:50]; +assign pyc_extract_341 = pyc_extract_340[4:1]; +assign pyc_zext_342 = {{8{1'b0}}, pyc_concat_332}; +assign pyc_extract_343 = pyc_concat_337[0]; +assign pyc_mux_344 = (pyc_extract_343 ? pyc_zext_342 : pyc_comb_20); +assign pyc_shli_345 = (pyc_zext_342 << 1); +assign pyc_extract_346 = pyc_concat_337[1]; +assign pyc_mux_347 = (pyc_extract_346 ? pyc_shli_345 : pyc_comb_20); +assign pyc_add_348 = (pyc_mux_344 + pyc_mux_347); +assign pyc_shli_349 = (pyc_zext_342 << 2); +assign pyc_extract_350 = pyc_concat_337[2]; +assign pyc_mux_351 = (pyc_extract_350 ? pyc_shli_349 : pyc_comb_20); +assign pyc_add_352 = (pyc_add_348 + pyc_mux_351); +assign pyc_shli_353 = (pyc_zext_342 << 3); +assign pyc_extract_354 = pyc_concat_337[3]; +assign pyc_mux_355 = (pyc_extract_354 ? pyc_shli_353 : pyc_comb_20); +assign pyc_add_356 = (pyc_add_352 + pyc_mux_355); +assign pyc_shli_357 = (pyc_zext_342 << 4); +assign pyc_extract_358 = pyc_concat_337[4]; +assign pyc_mux_359 = (pyc_extract_358 ? pyc_shli_357 : pyc_comb_20); +assign pyc_add_360 = (pyc_add_356 + pyc_mux_359); +assign pyc_shli_361 = (pyc_zext_342 << 5); +assign pyc_extract_362 = pyc_concat_337[5]; +assign pyc_mux_363 = (pyc_extract_362 ? pyc_shli_361 : pyc_comb_20); +assign pyc_add_364 = (pyc_add_360 + pyc_mux_363); +assign pyc_shli_365 = (pyc_zext_342 << 6); +assign pyc_extract_366 = pyc_concat_337[6]; +assign pyc_mux_367 = (pyc_extract_366 ? pyc_shli_365 : pyc_comb_20); +assign pyc_add_368 = (pyc_add_364 + pyc_mux_367); +assign pyc_shli_369 = (pyc_zext_342 << 7); +assign pyc_extract_370 = pyc_concat_337[7]; +assign pyc_mux_371 = (pyc_extract_370 ? pyc_shli_369 : pyc_comb_20); +assign pyc_add_372 = (pyc_add_368 + pyc_mux_371); +assign pyc_shli_373 = (pyc_zext_342 << 8); +assign pyc_mux_374 = (pyc_extract_370 ? pyc_shli_373 : pyc_comb_20); +assign pyc_extract_375 = pyc_concat_332[7]; +assign pyc_zext_376 = {{8{1'b0}}, pyc_concat_337}; +assign pyc_shli_377 = (pyc_zext_376 << 8); +assign pyc_mux_378 = (pyc_extract_375 ? pyc_shli_377 : pyc_comb_20); +assign pyc_sub_379 = (pyc_add_372 - pyc_mux_374); +assign pyc_sub_380 = (pyc_sub_379 - pyc_mux_378); +assign pe_int_s1_p2a_2__next = pyc_sub_380; +assign pyc_zext_381 = {{4{1'b0}}, pyc_concat_332}; +assign pyc_extract_382 = pyc_extract_339[0]; +assign pyc_mux_383 = (pyc_extract_382 ? pyc_zext_381 : pyc_comb_19); +assign pyc_shli_384 = (pyc_zext_381 << 1); +assign pyc_extract_385 = pyc_extract_339[1]; +assign pyc_mux_386 = (pyc_extract_385 ? pyc_shli_384 : pyc_comb_19); +assign pyc_add_387 = (pyc_mux_383 + pyc_mux_386); +assign pyc_shli_388 = (pyc_zext_381 << 2); +assign pyc_extract_389 = pyc_extract_339[2]; +assign pyc_mux_390 = (pyc_extract_389 ? pyc_shli_388 : pyc_comb_19); +assign pyc_add_391 = (pyc_add_387 + pyc_mux_390); +assign pyc_shli_392 = (pyc_zext_381 << 3); +assign pyc_extract_393 = pyc_extract_339[3]; +assign pyc_mux_394 = (pyc_extract_393 ? pyc_shli_392 : pyc_comb_19); +assign pyc_add_395 = (pyc_add_391 + pyc_mux_394); +assign pyc_shli_396 = (pyc_zext_381 << 4); +assign pyc_mux_397 = (pyc_extract_393 ? pyc_shli_396 : pyc_comb_19); +assign pyc_zext_398 = {{8{1'b0}}, pyc_extract_339}; +assign pyc_shli_399 = (pyc_zext_398 << 8); +assign pyc_mux_400 = (pyc_extract_375 ? pyc_shli_399 : pyc_comb_19); +assign pyc_sub_401 = (pyc_add_395 - pyc_mux_397); +assign pyc_sub_402 = (pyc_sub_401 - pyc_mux_400); +assign pe_int_s1_p2b0_2__next = pyc_sub_402; +assign pyc_extract_403 = pyc_extract_341[0]; +assign pyc_mux_404 = (pyc_extract_403 ? pyc_zext_381 : pyc_comb_19); +assign pyc_extract_405 = pyc_extract_341[1]; +assign pyc_mux_406 = (pyc_extract_405 ? pyc_shli_384 : pyc_comb_19); +assign pyc_add_407 = (pyc_mux_404 + pyc_mux_406); +assign pyc_extract_408 = pyc_extract_341[2]; +assign pyc_mux_409 = (pyc_extract_408 ? pyc_shli_388 : pyc_comb_19); +assign pyc_add_410 = (pyc_add_407 + pyc_mux_409); +assign pyc_extract_411 = pyc_extract_341[3]; +assign pyc_mux_412 = (pyc_extract_411 ? pyc_shli_392 : pyc_comb_19); +assign pyc_add_413 = (pyc_add_410 + pyc_mux_412); +assign pyc_mux_414 = (pyc_extract_411 ? pyc_shli_396 : pyc_comb_19); +assign pyc_zext_415 = {{8{1'b0}}, pyc_extract_341}; +assign pyc_shli_416 = (pyc_zext_415 << 8); +assign pyc_mux_417 = (pyc_extract_375 ? pyc_shli_416 : pyc_comb_19); +assign pyc_sub_418 = (pyc_add_413 - pyc_mux_414); +assign pyc_sub_419 = (pyc_sub_418 - pyc_mux_417); +assign pe_int_s1_p2b1_2__next = pyc_sub_419; +assign pyc_zext_420 = {{5{1'b0}}, pyc_concat_332}; +assign pyc_extract_421 = pyc_extract_338[0]; +assign pyc_mux_422 = (pyc_extract_421 ? pyc_zext_420 : pyc_comb_18); +assign pyc_shli_423 = (pyc_zext_420 << 1); +assign pyc_extract_424 = pyc_extract_338[1]; +assign pyc_mux_425 = (pyc_extract_424 ? pyc_shli_423 : pyc_comb_18); +assign pyc_add_426 = (pyc_mux_422 + pyc_mux_425); +assign pyc_shli_427 = (pyc_zext_420 << 2); +assign pyc_extract_428 = pyc_extract_338[2]; +assign pyc_mux_429 = (pyc_extract_428 ? pyc_shli_427 : pyc_comb_18); +assign pyc_add_430 = (pyc_add_426 + pyc_mux_429); +assign pyc_shli_431 = (pyc_zext_420 << 3); +assign pyc_extract_432 = pyc_extract_338[3]; +assign pyc_mux_433 = (pyc_extract_432 ? pyc_shli_431 : pyc_comb_18); +assign pyc_add_434 = (pyc_add_430 + pyc_mux_433); +assign pyc_shli_435 = (pyc_zext_420 << 4); +assign pyc_extract_436 = pyc_extract_338[4]; +assign pyc_mux_437 = (pyc_extract_436 ? pyc_shli_435 : pyc_comb_18); +assign pyc_add_438 = (pyc_add_434 + pyc_mux_437); +assign pyc_shli_439 = (pyc_zext_420 << 5); +assign pyc_mux_440 = (pyc_extract_436 ? pyc_shli_439 : pyc_comb_18); +assign pyc_zext_441 = {{8{1'b0}}, pyc_extract_338}; +assign pyc_shli_442 = (pyc_zext_441 << 8); +assign pyc_mux_443 = (pyc_extract_375 ? pyc_shli_442 : pyc_comb_18); +assign pyc_sub_444 = (pyc_add_438 - pyc_mux_440); +assign pyc_sub_445 = (pyc_sub_444 - pyc_mux_443); +assign pe_int_s1_p2d0_2__next = pyc_sub_445; +assign pyc_extract_446 = pyc_extract_340[0]; +assign pyc_mux_447 = (pyc_extract_446 ? pyc_zext_420 : pyc_comb_18); +assign pyc_extract_448 = pyc_extract_340[1]; +assign pyc_mux_449 = (pyc_extract_448 ? pyc_shli_423 : pyc_comb_18); +assign pyc_add_450 = (pyc_mux_447 + pyc_mux_449); +assign pyc_extract_451 = pyc_extract_340[2]; +assign pyc_mux_452 = (pyc_extract_451 ? pyc_shli_427 : pyc_comb_18); +assign pyc_add_453 = (pyc_add_450 + pyc_mux_452); +assign pyc_extract_454 = pyc_extract_340[3]; +assign pyc_mux_455 = (pyc_extract_454 ? pyc_shli_431 : pyc_comb_18); +assign pyc_add_456 = (pyc_add_453 + pyc_mux_455); +assign pyc_extract_457 = pyc_extract_340[4]; +assign pyc_mux_458 = (pyc_extract_457 ? pyc_shli_435 : pyc_comb_18); +assign pyc_add_459 = (pyc_add_456 + pyc_mux_458); +assign pyc_mux_460 = (pyc_extract_457 ? pyc_shli_439 : pyc_comb_18); +assign pyc_zext_461 = {{8{1'b0}}, pyc_extract_340}; +assign pyc_shli_462 = (pyc_zext_461 << 8); +assign pyc_mux_463 = (pyc_extract_375 ? pyc_shli_462 : pyc_comb_18); +assign pyc_sub_464 = (pyc_add_459 - pyc_mux_460); +assign pyc_sub_465 = (pyc_sub_464 - pyc_mux_463); +assign pe_int_s1_p2d1_2__next = pyc_sub_465; +assign pyc_extract_466 = pe_int_s0_a[34:30]; +assign pyc_extract_467 = pe_int_s0_a[39:35]; +assign pyc_extract_468 = pyc_extract_466[4:1]; +assign pyc_extract_469 = pyc_extract_467[4:1]; +assign pyc_concat_470 = {pyc_extract_469, pyc_extract_468}; +assign pyc_extract_471 = pe_int_s0_b[34:30]; +assign pyc_extract_472 = pe_int_s0_b[39:35]; +assign pyc_extract_473 = pyc_extract_471[4:1]; +assign pyc_extract_474 = pyc_extract_472[4:1]; +assign pyc_concat_475 = {pyc_extract_474, pyc_extract_473}; +assign pyc_extract_476 = pyc_extract_51[19:15]; +assign pyc_extract_477 = pyc_extract_476[4:1]; +assign pyc_extract_478 = pe_int_s0_b[59:55]; +assign pyc_extract_479 = pyc_extract_478[4:1]; +assign pyc_zext_480 = {{8{1'b0}}, pyc_concat_470}; +assign pyc_extract_481 = pyc_concat_475[0]; +assign pyc_mux_482 = (pyc_extract_481 ? pyc_zext_480 : pyc_comb_20); +assign pyc_shli_483 = (pyc_zext_480 << 1); +assign pyc_extract_484 = pyc_concat_475[1]; +assign pyc_mux_485 = (pyc_extract_484 ? pyc_shli_483 : pyc_comb_20); +assign pyc_add_486 = (pyc_mux_482 + pyc_mux_485); +assign pyc_shli_487 = (pyc_zext_480 << 2); +assign pyc_extract_488 = pyc_concat_475[2]; +assign pyc_mux_489 = (pyc_extract_488 ? pyc_shli_487 : pyc_comb_20); +assign pyc_add_490 = (pyc_add_486 + pyc_mux_489); +assign pyc_shli_491 = (pyc_zext_480 << 3); +assign pyc_extract_492 = pyc_concat_475[3]; +assign pyc_mux_493 = (pyc_extract_492 ? pyc_shli_491 : pyc_comb_20); +assign pyc_add_494 = (pyc_add_490 + pyc_mux_493); +assign pyc_shli_495 = (pyc_zext_480 << 4); +assign pyc_extract_496 = pyc_concat_475[4]; +assign pyc_mux_497 = (pyc_extract_496 ? pyc_shli_495 : pyc_comb_20); +assign pyc_add_498 = (pyc_add_494 + pyc_mux_497); +assign pyc_shli_499 = (pyc_zext_480 << 5); +assign pyc_extract_500 = pyc_concat_475[5]; +assign pyc_mux_501 = (pyc_extract_500 ? pyc_shli_499 : pyc_comb_20); +assign pyc_add_502 = (pyc_add_498 + pyc_mux_501); +assign pyc_shli_503 = (pyc_zext_480 << 6); +assign pyc_extract_504 = pyc_concat_475[6]; +assign pyc_mux_505 = (pyc_extract_504 ? pyc_shli_503 : pyc_comb_20); +assign pyc_add_506 = (pyc_add_502 + pyc_mux_505); +assign pyc_shli_507 = (pyc_zext_480 << 7); +assign pyc_extract_508 = pyc_concat_475[7]; +assign pyc_mux_509 = (pyc_extract_508 ? pyc_shli_507 : pyc_comb_20); +assign pyc_add_510 = (pyc_add_506 + pyc_mux_509); +assign pyc_shli_511 = (pyc_zext_480 << 8); +assign pyc_mux_512 = (pyc_extract_508 ? pyc_shli_511 : pyc_comb_20); +assign pyc_extract_513 = pyc_concat_470[7]; +assign pyc_zext_514 = {{8{1'b0}}, pyc_concat_475}; +assign pyc_shli_515 = (pyc_zext_514 << 8); +assign pyc_mux_516 = (pyc_extract_513 ? pyc_shli_515 : pyc_comb_20); +assign pyc_sub_517 = (pyc_add_510 - pyc_mux_512); +assign pyc_sub_518 = (pyc_sub_517 - pyc_mux_516); +assign pe_int_s1_p2a_3__next = pyc_sub_518; +assign pyc_zext_519 = {{4{1'b0}}, pyc_concat_470}; +assign pyc_extract_520 = pyc_extract_477[0]; +assign pyc_mux_521 = (pyc_extract_520 ? pyc_zext_519 : pyc_comb_19); +assign pyc_shli_522 = (pyc_zext_519 << 1); +assign pyc_extract_523 = pyc_extract_477[1]; +assign pyc_mux_524 = (pyc_extract_523 ? pyc_shli_522 : pyc_comb_19); +assign pyc_add_525 = (pyc_mux_521 + pyc_mux_524); +assign pyc_shli_526 = (pyc_zext_519 << 2); +assign pyc_extract_527 = pyc_extract_477[2]; +assign pyc_mux_528 = (pyc_extract_527 ? pyc_shli_526 : pyc_comb_19); +assign pyc_add_529 = (pyc_add_525 + pyc_mux_528); +assign pyc_shli_530 = (pyc_zext_519 << 3); +assign pyc_extract_531 = pyc_extract_477[3]; +assign pyc_mux_532 = (pyc_extract_531 ? pyc_shli_530 : pyc_comb_19); +assign pyc_add_533 = (pyc_add_529 + pyc_mux_532); +assign pyc_shli_534 = (pyc_zext_519 << 4); +assign pyc_mux_535 = (pyc_extract_531 ? pyc_shli_534 : pyc_comb_19); +assign pyc_zext_536 = {{8{1'b0}}, pyc_extract_477}; +assign pyc_shli_537 = (pyc_zext_536 << 8); +assign pyc_mux_538 = (pyc_extract_513 ? pyc_shli_537 : pyc_comb_19); +assign pyc_sub_539 = (pyc_add_533 - pyc_mux_535); +assign pyc_sub_540 = (pyc_sub_539 - pyc_mux_538); +assign pe_int_s1_p2b0_3__next = pyc_sub_540; +assign pyc_extract_541 = pyc_extract_479[0]; +assign pyc_mux_542 = (pyc_extract_541 ? pyc_zext_519 : pyc_comb_19); +assign pyc_extract_543 = pyc_extract_479[1]; +assign pyc_mux_544 = (pyc_extract_543 ? pyc_shli_522 : pyc_comb_19); +assign pyc_add_545 = (pyc_mux_542 + pyc_mux_544); +assign pyc_extract_546 = pyc_extract_479[2]; +assign pyc_mux_547 = (pyc_extract_546 ? pyc_shli_526 : pyc_comb_19); +assign pyc_add_548 = (pyc_add_545 + pyc_mux_547); +assign pyc_extract_549 = pyc_extract_479[3]; +assign pyc_mux_550 = (pyc_extract_549 ? pyc_shli_530 : pyc_comb_19); +assign pyc_add_551 = (pyc_add_548 + pyc_mux_550); +assign pyc_mux_552 = (pyc_extract_549 ? pyc_shli_534 : pyc_comb_19); +assign pyc_zext_553 = {{8{1'b0}}, pyc_extract_479}; +assign pyc_shli_554 = (pyc_zext_553 << 8); +assign pyc_mux_555 = (pyc_extract_513 ? pyc_shli_554 : pyc_comb_19); +assign pyc_sub_556 = (pyc_add_551 - pyc_mux_552); +assign pyc_sub_557 = (pyc_sub_556 - pyc_mux_555); +assign pe_int_s1_p2b1_3__next = pyc_sub_557; +assign pyc_zext_558 = {{5{1'b0}}, pyc_concat_470}; +assign pyc_extract_559 = pyc_extract_476[0]; +assign pyc_mux_560 = (pyc_extract_559 ? pyc_zext_558 : pyc_comb_18); +assign pyc_shli_561 = (pyc_zext_558 << 1); +assign pyc_extract_562 = pyc_extract_476[1]; +assign pyc_mux_563 = (pyc_extract_562 ? pyc_shli_561 : pyc_comb_18); +assign pyc_add_564 = (pyc_mux_560 + pyc_mux_563); +assign pyc_shli_565 = (pyc_zext_558 << 2); +assign pyc_extract_566 = pyc_extract_476[2]; +assign pyc_mux_567 = (pyc_extract_566 ? pyc_shli_565 : pyc_comb_18); +assign pyc_add_568 = (pyc_add_564 + pyc_mux_567); +assign pyc_shli_569 = (pyc_zext_558 << 3); +assign pyc_extract_570 = pyc_extract_476[3]; +assign pyc_mux_571 = (pyc_extract_570 ? pyc_shli_569 : pyc_comb_18); +assign pyc_add_572 = (pyc_add_568 + pyc_mux_571); +assign pyc_shli_573 = (pyc_zext_558 << 4); +assign pyc_extract_574 = pyc_extract_476[4]; +assign pyc_mux_575 = (pyc_extract_574 ? pyc_shli_573 : pyc_comb_18); +assign pyc_add_576 = (pyc_add_572 + pyc_mux_575); +assign pyc_shli_577 = (pyc_zext_558 << 5); +assign pyc_mux_578 = (pyc_extract_574 ? pyc_shli_577 : pyc_comb_18); +assign pyc_zext_579 = {{8{1'b0}}, pyc_extract_476}; +assign pyc_shli_580 = (pyc_zext_579 << 8); +assign pyc_mux_581 = (pyc_extract_513 ? pyc_shli_580 : pyc_comb_18); +assign pyc_sub_582 = (pyc_add_576 - pyc_mux_578); +assign pyc_sub_583 = (pyc_sub_582 - pyc_mux_581); +assign pe_int_s1_p2d0_3__next = pyc_sub_583; +assign pyc_extract_584 = pyc_extract_478[0]; +assign pyc_mux_585 = (pyc_extract_584 ? pyc_zext_558 : pyc_comb_18); +assign pyc_extract_586 = pyc_extract_478[1]; +assign pyc_mux_587 = (pyc_extract_586 ? pyc_shli_561 : pyc_comb_18); +assign pyc_add_588 = (pyc_mux_585 + pyc_mux_587); +assign pyc_extract_589 = pyc_extract_478[2]; +assign pyc_mux_590 = (pyc_extract_589 ? pyc_shli_565 : pyc_comb_18); +assign pyc_add_591 = (pyc_add_588 + pyc_mux_590); +assign pyc_extract_592 = pyc_extract_478[3]; +assign pyc_mux_593 = (pyc_extract_592 ? pyc_shli_569 : pyc_comb_18); +assign pyc_add_594 = (pyc_add_591 + pyc_mux_593); +assign pyc_extract_595 = pyc_extract_478[4]; +assign pyc_mux_596 = (pyc_extract_595 ? pyc_shli_573 : pyc_comb_18); +assign pyc_add_597 = (pyc_add_594 + pyc_mux_596); +assign pyc_mux_598 = (pyc_extract_595 ? pyc_shli_577 : pyc_comb_18); +assign pyc_zext_599 = {{8{1'b0}}, pyc_extract_478}; +assign pyc_shli_600 = (pyc_zext_599 << 8); +assign pyc_mux_601 = (pyc_extract_513 ? pyc_shli_600 : pyc_comb_18); +assign pyc_sub_602 = (pyc_add_597 - pyc_mux_598); +assign pyc_sub_603 = (pyc_sub_602 - pyc_mux_601); +assign pe_int_s1_p2d1_3__next = pyc_sub_603; +assign pyc_extract_604 = pe_int_s0_a[44:40]; +assign pyc_extract_605 = pe_int_s0_a[49:45]; +assign pyc_extract_606 = pyc_extract_604[4:1]; +assign pyc_extract_607 = pyc_extract_605[4:1]; +assign pyc_concat_608 = {pyc_extract_607, pyc_extract_606}; +assign pyc_concat_609 = {pyc_extract_203, pyc_extract_65}; +assign pyc_extract_610 = pyc_extract_51[24:20]; +assign pyc_extract_611 = pyc_extract_610[4:1]; +assign pyc_extract_612 = pe_int_s0_b[64:60]; +assign pyc_extract_613 = pyc_extract_612[4:1]; +assign pyc_zext_614 = {{8{1'b0}}, pyc_concat_608}; +assign pyc_extract_615 = pyc_concat_609[0]; +assign pyc_mux_616 = (pyc_extract_615 ? pyc_zext_614 : pyc_comb_20); +assign pyc_shli_617 = (pyc_zext_614 << 1); +assign pyc_extract_618 = pyc_concat_609[1]; +assign pyc_mux_619 = (pyc_extract_618 ? pyc_shli_617 : pyc_comb_20); +assign pyc_add_620 = (pyc_mux_616 + pyc_mux_619); +assign pyc_shli_621 = (pyc_zext_614 << 2); +assign pyc_extract_622 = pyc_concat_609[2]; +assign pyc_mux_623 = (pyc_extract_622 ? pyc_shli_621 : pyc_comb_20); +assign pyc_add_624 = (pyc_add_620 + pyc_mux_623); +assign pyc_shli_625 = (pyc_zext_614 << 3); +assign pyc_extract_626 = pyc_concat_609[3]; +assign pyc_mux_627 = (pyc_extract_626 ? pyc_shli_625 : pyc_comb_20); +assign pyc_add_628 = (pyc_add_624 + pyc_mux_627); +assign pyc_shli_629 = (pyc_zext_614 << 4); +assign pyc_extract_630 = pyc_concat_609[4]; +assign pyc_mux_631 = (pyc_extract_630 ? pyc_shli_629 : pyc_comb_20); +assign pyc_add_632 = (pyc_add_628 + pyc_mux_631); +assign pyc_shli_633 = (pyc_zext_614 << 5); +assign pyc_extract_634 = pyc_concat_609[5]; +assign pyc_mux_635 = (pyc_extract_634 ? pyc_shli_633 : pyc_comb_20); +assign pyc_add_636 = (pyc_add_632 + pyc_mux_635); +assign pyc_shli_637 = (pyc_zext_614 << 6); +assign pyc_extract_638 = pyc_concat_609[6]; +assign pyc_mux_639 = (pyc_extract_638 ? pyc_shli_637 : pyc_comb_20); +assign pyc_add_640 = (pyc_add_636 + pyc_mux_639); +assign pyc_shli_641 = (pyc_zext_614 << 7); +assign pyc_extract_642 = pyc_concat_609[7]; +assign pyc_mux_643 = (pyc_extract_642 ? pyc_shli_641 : pyc_comb_20); +assign pyc_add_644 = (pyc_add_640 + pyc_mux_643); +assign pyc_shli_645 = (pyc_zext_614 << 8); +assign pyc_mux_646 = (pyc_extract_642 ? pyc_shli_645 : pyc_comb_20); +assign pyc_extract_647 = pyc_concat_608[7]; +assign pyc_zext_648 = {{8{1'b0}}, pyc_concat_609}; +assign pyc_shli_649 = (pyc_zext_648 << 8); +assign pyc_mux_650 = (pyc_extract_647 ? pyc_shli_649 : pyc_comb_20); +assign pyc_sub_651 = (pyc_add_644 - pyc_mux_646); +assign pyc_sub_652 = (pyc_sub_651 - pyc_mux_650); +assign pe_int_s1_p2a_4__next = pyc_sub_652; +assign pyc_zext_653 = {{4{1'b0}}, pyc_concat_608}; +assign pyc_extract_654 = pyc_extract_611[0]; +assign pyc_mux_655 = (pyc_extract_654 ? pyc_zext_653 : pyc_comb_19); +assign pyc_shli_656 = (pyc_zext_653 << 1); +assign pyc_extract_657 = pyc_extract_611[1]; +assign pyc_mux_658 = (pyc_extract_657 ? pyc_shli_656 : pyc_comb_19); +assign pyc_add_659 = (pyc_mux_655 + pyc_mux_658); +assign pyc_shli_660 = (pyc_zext_653 << 2); +assign pyc_extract_661 = pyc_extract_611[2]; +assign pyc_mux_662 = (pyc_extract_661 ? pyc_shli_660 : pyc_comb_19); +assign pyc_add_663 = (pyc_add_659 + pyc_mux_662); +assign pyc_shli_664 = (pyc_zext_653 << 3); +assign pyc_extract_665 = pyc_extract_611[3]; +assign pyc_mux_666 = (pyc_extract_665 ? pyc_shli_664 : pyc_comb_19); +assign pyc_add_667 = (pyc_add_663 + pyc_mux_666); +assign pyc_shli_668 = (pyc_zext_653 << 4); +assign pyc_mux_669 = (pyc_extract_665 ? pyc_shli_668 : pyc_comb_19); +assign pyc_zext_670 = {{8{1'b0}}, pyc_extract_611}; +assign pyc_shli_671 = (pyc_zext_670 << 8); +assign pyc_mux_672 = (pyc_extract_647 ? pyc_shli_671 : pyc_comb_19); +assign pyc_sub_673 = (pyc_add_667 - pyc_mux_669); +assign pyc_sub_674 = (pyc_sub_673 - pyc_mux_672); +assign pe_int_s1_p2b0_4__next = pyc_sub_674; +assign pyc_extract_675 = pyc_extract_613[0]; +assign pyc_mux_676 = (pyc_extract_675 ? pyc_zext_653 : pyc_comb_19); +assign pyc_extract_677 = pyc_extract_613[1]; +assign pyc_mux_678 = (pyc_extract_677 ? pyc_shli_656 : pyc_comb_19); +assign pyc_add_679 = (pyc_mux_676 + pyc_mux_678); +assign pyc_extract_680 = pyc_extract_613[2]; +assign pyc_mux_681 = (pyc_extract_680 ? pyc_shli_660 : pyc_comb_19); +assign pyc_add_682 = (pyc_add_679 + pyc_mux_681); +assign pyc_extract_683 = pyc_extract_613[3]; +assign pyc_mux_684 = (pyc_extract_683 ? pyc_shli_664 : pyc_comb_19); +assign pyc_add_685 = (pyc_add_682 + pyc_mux_684); +assign pyc_mux_686 = (pyc_extract_683 ? pyc_shli_668 : pyc_comb_19); +assign pyc_zext_687 = {{8{1'b0}}, pyc_extract_613}; +assign pyc_shli_688 = (pyc_zext_687 << 8); +assign pyc_mux_689 = (pyc_extract_647 ? pyc_shli_688 : pyc_comb_19); +assign pyc_sub_690 = (pyc_add_685 - pyc_mux_686); +assign pyc_sub_691 = (pyc_sub_690 - pyc_mux_689); +assign pe_int_s1_p2b1_4__next = pyc_sub_691; +assign pyc_zext_692 = {{5{1'b0}}, pyc_concat_608}; +assign pyc_extract_693 = pyc_extract_610[0]; +assign pyc_mux_694 = (pyc_extract_693 ? pyc_zext_692 : pyc_comb_18); +assign pyc_shli_695 = (pyc_zext_692 << 1); +assign pyc_extract_696 = pyc_extract_610[1]; +assign pyc_mux_697 = (pyc_extract_696 ? pyc_shli_695 : pyc_comb_18); +assign pyc_add_698 = (pyc_mux_694 + pyc_mux_697); +assign pyc_shli_699 = (pyc_zext_692 << 2); +assign pyc_extract_700 = pyc_extract_610[2]; +assign pyc_mux_701 = (pyc_extract_700 ? pyc_shli_699 : pyc_comb_18); +assign pyc_add_702 = (pyc_add_698 + pyc_mux_701); +assign pyc_shli_703 = (pyc_zext_692 << 3); +assign pyc_extract_704 = pyc_extract_610[3]; +assign pyc_mux_705 = (pyc_extract_704 ? pyc_shli_703 : pyc_comb_18); +assign pyc_add_706 = (pyc_add_702 + pyc_mux_705); +assign pyc_shli_707 = (pyc_zext_692 << 4); +assign pyc_extract_708 = pyc_extract_610[4]; +assign pyc_mux_709 = (pyc_extract_708 ? pyc_shli_707 : pyc_comb_18); +assign pyc_add_710 = (pyc_add_706 + pyc_mux_709); +assign pyc_shli_711 = (pyc_zext_692 << 5); +assign pyc_mux_712 = (pyc_extract_708 ? pyc_shli_711 : pyc_comb_18); +assign pyc_zext_713 = {{8{1'b0}}, pyc_extract_610}; +assign pyc_shli_714 = (pyc_zext_713 << 8); +assign pyc_mux_715 = (pyc_extract_647 ? pyc_shli_714 : pyc_comb_18); +assign pyc_sub_716 = (pyc_add_710 - pyc_mux_712); +assign pyc_sub_717 = (pyc_sub_716 - pyc_mux_715); +assign pe_int_s1_p2d0_4__next = pyc_sub_717; +assign pyc_extract_718 = pyc_extract_612[0]; +assign pyc_mux_719 = (pyc_extract_718 ? pyc_zext_692 : pyc_comb_18); +assign pyc_extract_720 = pyc_extract_612[1]; +assign pyc_mux_721 = (pyc_extract_720 ? pyc_shli_695 : pyc_comb_18); +assign pyc_add_722 = (pyc_mux_719 + pyc_mux_721); +assign pyc_extract_723 = pyc_extract_612[2]; +assign pyc_mux_724 = (pyc_extract_723 ? pyc_shli_699 : pyc_comb_18); +assign pyc_add_725 = (pyc_add_722 + pyc_mux_724); +assign pyc_extract_726 = pyc_extract_612[3]; +assign pyc_mux_727 = (pyc_extract_726 ? pyc_shli_703 : pyc_comb_18); +assign pyc_add_728 = (pyc_add_725 + pyc_mux_727); +assign pyc_extract_729 = pyc_extract_612[4]; +assign pyc_mux_730 = (pyc_extract_729 ? pyc_shli_707 : pyc_comb_18); +assign pyc_add_731 = (pyc_add_728 + pyc_mux_730); +assign pyc_mux_732 = (pyc_extract_729 ? pyc_shli_711 : pyc_comb_18); +assign pyc_zext_733 = {{8{1'b0}}, pyc_extract_612}; +assign pyc_shli_734 = (pyc_zext_733 << 8); +assign pyc_mux_735 = (pyc_extract_647 ? pyc_shli_734 : pyc_comb_18); +assign pyc_sub_736 = (pyc_add_731 - pyc_mux_732); +assign pyc_sub_737 = (pyc_sub_736 - pyc_mux_735); +assign pe_int_s1_p2d1_4__next = pyc_sub_737; +assign pyc_extract_738 = pe_int_s0_a[54:50]; +assign pyc_extract_739 = pe_int_s0_a[59:55]; +assign pyc_extract_740 = pyc_extract_738[4:1]; +assign pyc_extract_741 = pyc_extract_739[4:1]; +assign pyc_concat_742 = {pyc_extract_741, pyc_extract_740}; +assign pyc_concat_743 = {pyc_extract_479, pyc_extract_341}; +assign pyc_extract_744 = pyc_extract_51[29:25]; +assign pyc_extract_745 = pyc_extract_744[4:1]; +assign pyc_extract_746 = pe_int_s0_b[69:65]; +assign pyc_extract_747 = pyc_extract_746[4:1]; +assign pyc_zext_748 = {{8{1'b0}}, pyc_concat_742}; +assign pyc_extract_749 = pyc_concat_743[0]; +assign pyc_mux_750 = (pyc_extract_749 ? pyc_zext_748 : pyc_comb_20); +assign pyc_shli_751 = (pyc_zext_748 << 1); +assign pyc_extract_752 = pyc_concat_743[1]; +assign pyc_mux_753 = (pyc_extract_752 ? pyc_shli_751 : pyc_comb_20); +assign pyc_add_754 = (pyc_mux_750 + pyc_mux_753); +assign pyc_shli_755 = (pyc_zext_748 << 2); +assign pyc_extract_756 = pyc_concat_743[2]; +assign pyc_mux_757 = (pyc_extract_756 ? pyc_shli_755 : pyc_comb_20); +assign pyc_add_758 = (pyc_add_754 + pyc_mux_757); +assign pyc_shli_759 = (pyc_zext_748 << 3); +assign pyc_extract_760 = pyc_concat_743[3]; +assign pyc_mux_761 = (pyc_extract_760 ? pyc_shli_759 : pyc_comb_20); +assign pyc_add_762 = (pyc_add_758 + pyc_mux_761); +assign pyc_shli_763 = (pyc_zext_748 << 4); +assign pyc_extract_764 = pyc_concat_743[4]; +assign pyc_mux_765 = (pyc_extract_764 ? pyc_shli_763 : pyc_comb_20); +assign pyc_add_766 = (pyc_add_762 + pyc_mux_765); +assign pyc_shli_767 = (pyc_zext_748 << 5); +assign pyc_extract_768 = pyc_concat_743[5]; +assign pyc_mux_769 = (pyc_extract_768 ? pyc_shli_767 : pyc_comb_20); +assign pyc_add_770 = (pyc_add_766 + pyc_mux_769); +assign pyc_shli_771 = (pyc_zext_748 << 6); +assign pyc_extract_772 = pyc_concat_743[6]; +assign pyc_mux_773 = (pyc_extract_772 ? pyc_shli_771 : pyc_comb_20); +assign pyc_add_774 = (pyc_add_770 + pyc_mux_773); +assign pyc_shli_775 = (pyc_zext_748 << 7); +assign pyc_extract_776 = pyc_concat_743[7]; +assign pyc_mux_777 = (pyc_extract_776 ? pyc_shli_775 : pyc_comb_20); +assign pyc_add_778 = (pyc_add_774 + pyc_mux_777); +assign pyc_shli_779 = (pyc_zext_748 << 8); +assign pyc_mux_780 = (pyc_extract_776 ? pyc_shli_779 : pyc_comb_20); +assign pyc_extract_781 = pyc_concat_742[7]; +assign pyc_zext_782 = {{8{1'b0}}, pyc_concat_743}; +assign pyc_shli_783 = (pyc_zext_782 << 8); +assign pyc_mux_784 = (pyc_extract_781 ? pyc_shli_783 : pyc_comb_20); +assign pyc_sub_785 = (pyc_add_778 - pyc_mux_780); +assign pyc_sub_786 = (pyc_sub_785 - pyc_mux_784); +assign pe_int_s1_p2a_5__next = pyc_sub_786; +assign pyc_zext_787 = {{4{1'b0}}, pyc_concat_742}; +assign pyc_extract_788 = pyc_extract_745[0]; +assign pyc_mux_789 = (pyc_extract_788 ? pyc_zext_787 : pyc_comb_19); +assign pyc_shli_790 = (pyc_zext_787 << 1); +assign pyc_extract_791 = pyc_extract_745[1]; +assign pyc_mux_792 = (pyc_extract_791 ? pyc_shli_790 : pyc_comb_19); +assign pyc_add_793 = (pyc_mux_789 + pyc_mux_792); +assign pyc_shli_794 = (pyc_zext_787 << 2); +assign pyc_extract_795 = pyc_extract_745[2]; +assign pyc_mux_796 = (pyc_extract_795 ? pyc_shli_794 : pyc_comb_19); +assign pyc_add_797 = (pyc_add_793 + pyc_mux_796); +assign pyc_shli_798 = (pyc_zext_787 << 3); +assign pyc_extract_799 = pyc_extract_745[3]; +assign pyc_mux_800 = (pyc_extract_799 ? pyc_shli_798 : pyc_comb_19); +assign pyc_add_801 = (pyc_add_797 + pyc_mux_800); +assign pyc_shli_802 = (pyc_zext_787 << 4); +assign pyc_mux_803 = (pyc_extract_799 ? pyc_shli_802 : pyc_comb_19); +assign pyc_zext_804 = {{8{1'b0}}, pyc_extract_745}; +assign pyc_shli_805 = (pyc_zext_804 << 8); +assign pyc_mux_806 = (pyc_extract_781 ? pyc_shli_805 : pyc_comb_19); +assign pyc_sub_807 = (pyc_add_801 - pyc_mux_803); +assign pyc_sub_808 = (pyc_sub_807 - pyc_mux_806); +assign pe_int_s1_p2b0_5__next = pyc_sub_808; +assign pyc_extract_809 = pyc_extract_747[0]; +assign pyc_mux_810 = (pyc_extract_809 ? pyc_zext_787 : pyc_comb_19); +assign pyc_extract_811 = pyc_extract_747[1]; +assign pyc_mux_812 = (pyc_extract_811 ? pyc_shli_790 : pyc_comb_19); +assign pyc_add_813 = (pyc_mux_810 + pyc_mux_812); +assign pyc_extract_814 = pyc_extract_747[2]; +assign pyc_mux_815 = (pyc_extract_814 ? pyc_shli_794 : pyc_comb_19); +assign pyc_add_816 = (pyc_add_813 + pyc_mux_815); +assign pyc_extract_817 = pyc_extract_747[3]; +assign pyc_mux_818 = (pyc_extract_817 ? pyc_shli_798 : pyc_comb_19); +assign pyc_add_819 = (pyc_add_816 + pyc_mux_818); +assign pyc_mux_820 = (pyc_extract_817 ? pyc_shli_802 : pyc_comb_19); +assign pyc_zext_821 = {{8{1'b0}}, pyc_extract_747}; +assign pyc_shli_822 = (pyc_zext_821 << 8); +assign pyc_mux_823 = (pyc_extract_781 ? pyc_shli_822 : pyc_comb_19); +assign pyc_sub_824 = (pyc_add_819 - pyc_mux_820); +assign pyc_sub_825 = (pyc_sub_824 - pyc_mux_823); +assign pe_int_s1_p2b1_5__next = pyc_sub_825; +assign pyc_zext_826 = {{5{1'b0}}, pyc_concat_742}; +assign pyc_extract_827 = pyc_extract_744[0]; +assign pyc_mux_828 = (pyc_extract_827 ? pyc_zext_826 : pyc_comb_18); +assign pyc_shli_829 = (pyc_zext_826 << 1); +assign pyc_extract_830 = pyc_extract_744[1]; +assign pyc_mux_831 = (pyc_extract_830 ? pyc_shli_829 : pyc_comb_18); +assign pyc_add_832 = (pyc_mux_828 + pyc_mux_831); +assign pyc_shli_833 = (pyc_zext_826 << 2); +assign pyc_extract_834 = pyc_extract_744[2]; +assign pyc_mux_835 = (pyc_extract_834 ? pyc_shli_833 : pyc_comb_18); +assign pyc_add_836 = (pyc_add_832 + pyc_mux_835); +assign pyc_shli_837 = (pyc_zext_826 << 3); +assign pyc_extract_838 = pyc_extract_744[3]; +assign pyc_mux_839 = (pyc_extract_838 ? pyc_shli_837 : pyc_comb_18); +assign pyc_add_840 = (pyc_add_836 + pyc_mux_839); +assign pyc_shli_841 = (pyc_zext_826 << 4); +assign pyc_extract_842 = pyc_extract_744[4]; +assign pyc_mux_843 = (pyc_extract_842 ? pyc_shli_841 : pyc_comb_18); +assign pyc_add_844 = (pyc_add_840 + pyc_mux_843); +assign pyc_shli_845 = (pyc_zext_826 << 5); +assign pyc_mux_846 = (pyc_extract_842 ? pyc_shli_845 : pyc_comb_18); +assign pyc_zext_847 = {{8{1'b0}}, pyc_extract_744}; +assign pyc_shli_848 = (pyc_zext_847 << 8); +assign pyc_mux_849 = (pyc_extract_781 ? pyc_shli_848 : pyc_comb_18); +assign pyc_sub_850 = (pyc_add_844 - pyc_mux_846); +assign pyc_sub_851 = (pyc_sub_850 - pyc_mux_849); +assign pe_int_s1_p2d0_5__next = pyc_sub_851; +assign pyc_extract_852 = pyc_extract_746[0]; +assign pyc_mux_853 = (pyc_extract_852 ? pyc_zext_826 : pyc_comb_18); +assign pyc_extract_854 = pyc_extract_746[1]; +assign pyc_mux_855 = (pyc_extract_854 ? pyc_shli_829 : pyc_comb_18); +assign pyc_add_856 = (pyc_mux_853 + pyc_mux_855); +assign pyc_extract_857 = pyc_extract_746[2]; +assign pyc_mux_858 = (pyc_extract_857 ? pyc_shli_833 : pyc_comb_18); +assign pyc_add_859 = (pyc_add_856 + pyc_mux_858); +assign pyc_extract_860 = pyc_extract_746[3]; +assign pyc_mux_861 = (pyc_extract_860 ? pyc_shli_837 : pyc_comb_18); +assign pyc_add_862 = (pyc_add_859 + pyc_mux_861); +assign pyc_extract_863 = pyc_extract_746[4]; +assign pyc_mux_864 = (pyc_extract_863 ? pyc_shli_841 : pyc_comb_18); +assign pyc_add_865 = (pyc_add_862 + pyc_mux_864); +assign pyc_mux_866 = (pyc_extract_863 ? pyc_shli_845 : pyc_comb_18); +assign pyc_zext_867 = {{8{1'b0}}, pyc_extract_746}; +assign pyc_shli_868 = (pyc_zext_867 << 8); +assign pyc_mux_869 = (pyc_extract_781 ? pyc_shli_868 : pyc_comb_18); +assign pyc_sub_870 = (pyc_add_865 - pyc_mux_866); +assign pyc_sub_871 = (pyc_sub_870 - pyc_mux_869); +assign pe_int_s1_p2d1_5__next = pyc_sub_871; +assign pyc_extract_872 = pe_int_s0_a[64:60]; +assign pyc_extract_873 = pe_int_s0_a[69:65]; +assign pyc_extract_874 = pyc_extract_872[4:1]; +assign pyc_extract_875 = pyc_extract_873[4:1]; +assign pyc_concat_876 = {pyc_extract_875, pyc_extract_874}; +assign pyc_concat_877 = {pyc_extract_747, pyc_extract_613}; +assign pyc_extract_878 = pyc_extract_51[34:30]; +assign pyc_extract_879 = pyc_extract_878[4:1]; +assign pyc_extract_880 = pe_int_s0_b[74:70]; +assign pyc_extract_881 = pyc_extract_880[4:1]; +assign pyc_zext_882 = {{8{1'b0}}, pyc_concat_876}; +assign pyc_extract_883 = pyc_concat_877[0]; +assign pyc_mux_884 = (pyc_extract_883 ? pyc_zext_882 : pyc_comb_20); +assign pyc_shli_885 = (pyc_zext_882 << 1); +assign pyc_extract_886 = pyc_concat_877[1]; +assign pyc_mux_887 = (pyc_extract_886 ? pyc_shli_885 : pyc_comb_20); +assign pyc_add_888 = (pyc_mux_884 + pyc_mux_887); +assign pyc_shli_889 = (pyc_zext_882 << 2); +assign pyc_extract_890 = pyc_concat_877[2]; +assign pyc_mux_891 = (pyc_extract_890 ? pyc_shli_889 : pyc_comb_20); +assign pyc_add_892 = (pyc_add_888 + pyc_mux_891); +assign pyc_shli_893 = (pyc_zext_882 << 3); +assign pyc_extract_894 = pyc_concat_877[3]; +assign pyc_mux_895 = (pyc_extract_894 ? pyc_shli_893 : pyc_comb_20); +assign pyc_add_896 = (pyc_add_892 + pyc_mux_895); +assign pyc_shli_897 = (pyc_zext_882 << 4); +assign pyc_extract_898 = pyc_concat_877[4]; +assign pyc_mux_899 = (pyc_extract_898 ? pyc_shli_897 : pyc_comb_20); +assign pyc_add_900 = (pyc_add_896 + pyc_mux_899); +assign pyc_shli_901 = (pyc_zext_882 << 5); +assign pyc_extract_902 = pyc_concat_877[5]; +assign pyc_mux_903 = (pyc_extract_902 ? pyc_shli_901 : pyc_comb_20); +assign pyc_add_904 = (pyc_add_900 + pyc_mux_903); +assign pyc_shli_905 = (pyc_zext_882 << 6); +assign pyc_extract_906 = pyc_concat_877[6]; +assign pyc_mux_907 = (pyc_extract_906 ? pyc_shli_905 : pyc_comb_20); +assign pyc_add_908 = (pyc_add_904 + pyc_mux_907); +assign pyc_shli_909 = (pyc_zext_882 << 7); +assign pyc_extract_910 = pyc_concat_877[7]; +assign pyc_mux_911 = (pyc_extract_910 ? pyc_shli_909 : pyc_comb_20); +assign pyc_add_912 = (pyc_add_908 + pyc_mux_911); +assign pyc_shli_913 = (pyc_zext_882 << 8); +assign pyc_mux_914 = (pyc_extract_910 ? pyc_shli_913 : pyc_comb_20); +assign pyc_extract_915 = pyc_concat_876[7]; +assign pyc_zext_916 = {{8{1'b0}}, pyc_concat_877}; +assign pyc_shli_917 = (pyc_zext_916 << 8); +assign pyc_mux_918 = (pyc_extract_915 ? pyc_shli_917 : pyc_comb_20); +assign pyc_sub_919 = (pyc_add_912 - pyc_mux_914); +assign pyc_sub_920 = (pyc_sub_919 - pyc_mux_918); +assign pe_int_s1_p2a_6__next = pyc_sub_920; +assign pyc_zext_921 = {{4{1'b0}}, pyc_concat_876}; +assign pyc_extract_922 = pyc_extract_879[0]; +assign pyc_mux_923 = (pyc_extract_922 ? pyc_zext_921 : pyc_comb_19); +assign pyc_shli_924 = (pyc_zext_921 << 1); +assign pyc_extract_925 = pyc_extract_879[1]; +assign pyc_mux_926 = (pyc_extract_925 ? pyc_shli_924 : pyc_comb_19); +assign pyc_add_927 = (pyc_mux_923 + pyc_mux_926); +assign pyc_shli_928 = (pyc_zext_921 << 2); +assign pyc_extract_929 = pyc_extract_879[2]; +assign pyc_mux_930 = (pyc_extract_929 ? pyc_shli_928 : pyc_comb_19); +assign pyc_add_931 = (pyc_add_927 + pyc_mux_930); +assign pyc_shli_932 = (pyc_zext_921 << 3); +assign pyc_extract_933 = pyc_extract_879[3]; +assign pyc_mux_934 = (pyc_extract_933 ? pyc_shli_932 : pyc_comb_19); +assign pyc_add_935 = (pyc_add_931 + pyc_mux_934); +assign pyc_shli_936 = (pyc_zext_921 << 4); +assign pyc_mux_937 = (pyc_extract_933 ? pyc_shli_936 : pyc_comb_19); +assign pyc_zext_938 = {{8{1'b0}}, pyc_extract_879}; +assign pyc_shli_939 = (pyc_zext_938 << 8); +assign pyc_mux_940 = (pyc_extract_915 ? pyc_shli_939 : pyc_comb_19); +assign pyc_sub_941 = (pyc_add_935 - pyc_mux_937); +assign pyc_sub_942 = (pyc_sub_941 - pyc_mux_940); +assign pe_int_s1_p2b0_6__next = pyc_sub_942; +assign pyc_extract_943 = pyc_extract_881[0]; +assign pyc_mux_944 = (pyc_extract_943 ? pyc_zext_921 : pyc_comb_19); +assign pyc_extract_945 = pyc_extract_881[1]; +assign pyc_mux_946 = (pyc_extract_945 ? pyc_shli_924 : pyc_comb_19); +assign pyc_add_947 = (pyc_mux_944 + pyc_mux_946); +assign pyc_extract_948 = pyc_extract_881[2]; +assign pyc_mux_949 = (pyc_extract_948 ? pyc_shli_928 : pyc_comb_19); +assign pyc_add_950 = (pyc_add_947 + pyc_mux_949); +assign pyc_extract_951 = pyc_extract_881[3]; +assign pyc_mux_952 = (pyc_extract_951 ? pyc_shli_932 : pyc_comb_19); +assign pyc_add_953 = (pyc_add_950 + pyc_mux_952); +assign pyc_mux_954 = (pyc_extract_951 ? pyc_shli_936 : pyc_comb_19); +assign pyc_zext_955 = {{8{1'b0}}, pyc_extract_881}; +assign pyc_shli_956 = (pyc_zext_955 << 8); +assign pyc_mux_957 = (pyc_extract_915 ? pyc_shli_956 : pyc_comb_19); +assign pyc_sub_958 = (pyc_add_953 - pyc_mux_954); +assign pyc_sub_959 = (pyc_sub_958 - pyc_mux_957); +assign pe_int_s1_p2b1_6__next = pyc_sub_959; +assign pyc_zext_960 = {{5{1'b0}}, pyc_concat_876}; +assign pyc_extract_961 = pyc_extract_878[0]; +assign pyc_mux_962 = (pyc_extract_961 ? pyc_zext_960 : pyc_comb_18); +assign pyc_shli_963 = (pyc_zext_960 << 1); +assign pyc_extract_964 = pyc_extract_878[1]; +assign pyc_mux_965 = (pyc_extract_964 ? pyc_shli_963 : pyc_comb_18); +assign pyc_add_966 = (pyc_mux_962 + pyc_mux_965); +assign pyc_shli_967 = (pyc_zext_960 << 2); +assign pyc_extract_968 = pyc_extract_878[2]; +assign pyc_mux_969 = (pyc_extract_968 ? pyc_shli_967 : pyc_comb_18); +assign pyc_add_970 = (pyc_add_966 + pyc_mux_969); +assign pyc_shli_971 = (pyc_zext_960 << 3); +assign pyc_extract_972 = pyc_extract_878[3]; +assign pyc_mux_973 = (pyc_extract_972 ? pyc_shli_971 : pyc_comb_18); +assign pyc_add_974 = (pyc_add_970 + pyc_mux_973); +assign pyc_shli_975 = (pyc_zext_960 << 4); +assign pyc_extract_976 = pyc_extract_878[4]; +assign pyc_mux_977 = (pyc_extract_976 ? pyc_shli_975 : pyc_comb_18); +assign pyc_add_978 = (pyc_add_974 + pyc_mux_977); +assign pyc_shli_979 = (pyc_zext_960 << 5); +assign pyc_mux_980 = (pyc_extract_976 ? pyc_shli_979 : pyc_comb_18); +assign pyc_zext_981 = {{8{1'b0}}, pyc_extract_878}; +assign pyc_shli_982 = (pyc_zext_981 << 8); +assign pyc_mux_983 = (pyc_extract_915 ? pyc_shli_982 : pyc_comb_18); +assign pyc_sub_984 = (pyc_add_978 - pyc_mux_980); +assign pyc_sub_985 = (pyc_sub_984 - pyc_mux_983); +assign pe_int_s1_p2d0_6__next = pyc_sub_985; +assign pyc_extract_986 = pyc_extract_880[0]; +assign pyc_mux_987 = (pyc_extract_986 ? pyc_zext_960 : pyc_comb_18); +assign pyc_extract_988 = pyc_extract_880[1]; +assign pyc_mux_989 = (pyc_extract_988 ? pyc_shli_963 : pyc_comb_18); +assign pyc_add_990 = (pyc_mux_987 + pyc_mux_989); +assign pyc_extract_991 = pyc_extract_880[2]; +assign pyc_mux_992 = (pyc_extract_991 ? pyc_shli_967 : pyc_comb_18); +assign pyc_add_993 = (pyc_add_990 + pyc_mux_992); +assign pyc_extract_994 = pyc_extract_880[3]; +assign pyc_mux_995 = (pyc_extract_994 ? pyc_shli_971 : pyc_comb_18); +assign pyc_add_996 = (pyc_add_993 + pyc_mux_995); +assign pyc_extract_997 = pyc_extract_880[4]; +assign pyc_mux_998 = (pyc_extract_997 ? pyc_shli_975 : pyc_comb_18); +assign pyc_add_999 = (pyc_add_996 + pyc_mux_998); +assign pyc_mux_1000 = (pyc_extract_997 ? pyc_shli_979 : pyc_comb_18); +assign pyc_zext_1001 = {{8{1'b0}}, pyc_extract_880}; +assign pyc_shli_1002 = (pyc_zext_1001 << 8); +assign pyc_mux_1003 = (pyc_extract_915 ? pyc_shli_1002 : pyc_comb_18); +assign pyc_sub_1004 = (pyc_add_999 - pyc_mux_1000); +assign pyc_sub_1005 = (pyc_sub_1004 - pyc_mux_1003); +assign pe_int_s1_p2d1_6__next = pyc_sub_1005; +assign pyc_extract_1006 = pe_int_s0_a[74:70]; +assign pyc_extract_1007 = pe_int_s0_a[79:75]; +assign pyc_extract_1008 = pyc_extract_1006[4:1]; +assign pyc_extract_1009 = pyc_extract_1007[4:1]; +assign pyc_concat_1010 = {pyc_extract_1009, pyc_extract_1008}; +assign pyc_extract_1011 = pe_int_s0_b[79:75]; +assign pyc_extract_1012 = pyc_extract_1011[4:1]; +assign pyc_concat_1013 = {pyc_extract_1012, pyc_extract_881}; +assign pyc_extract_1014 = pyc_extract_51[39:35]; +assign pyc_extract_1015 = pyc_extract_1014[4:1]; +assign pyc_zext_1016 = {{8{1'b0}}, pyc_concat_1010}; +assign pyc_extract_1017 = pyc_concat_1013[0]; +assign pyc_mux_1018 = (pyc_extract_1017 ? pyc_zext_1016 : pyc_comb_20); +assign pyc_shli_1019 = (pyc_zext_1016 << 1); +assign pyc_extract_1020 = pyc_concat_1013[1]; +assign pyc_mux_1021 = (pyc_extract_1020 ? pyc_shli_1019 : pyc_comb_20); +assign pyc_add_1022 = (pyc_mux_1018 + pyc_mux_1021); +assign pyc_shli_1023 = (pyc_zext_1016 << 2); +assign pyc_extract_1024 = pyc_concat_1013[2]; +assign pyc_mux_1025 = (pyc_extract_1024 ? pyc_shli_1023 : pyc_comb_20); +assign pyc_add_1026 = (pyc_add_1022 + pyc_mux_1025); +assign pyc_shli_1027 = (pyc_zext_1016 << 3); +assign pyc_extract_1028 = pyc_concat_1013[3]; +assign pyc_mux_1029 = (pyc_extract_1028 ? pyc_shli_1027 : pyc_comb_20); +assign pyc_add_1030 = (pyc_add_1026 + pyc_mux_1029); +assign pyc_shli_1031 = (pyc_zext_1016 << 4); +assign pyc_extract_1032 = pyc_concat_1013[4]; +assign pyc_mux_1033 = (pyc_extract_1032 ? pyc_shli_1031 : pyc_comb_20); +assign pyc_add_1034 = (pyc_add_1030 + pyc_mux_1033); +assign pyc_shli_1035 = (pyc_zext_1016 << 5); +assign pyc_extract_1036 = pyc_concat_1013[5]; +assign pyc_mux_1037 = (pyc_extract_1036 ? pyc_shli_1035 : pyc_comb_20); +assign pyc_add_1038 = (pyc_add_1034 + pyc_mux_1037); +assign pyc_shli_1039 = (pyc_zext_1016 << 6); +assign pyc_extract_1040 = pyc_concat_1013[6]; +assign pyc_mux_1041 = (pyc_extract_1040 ? pyc_shli_1039 : pyc_comb_20); +assign pyc_add_1042 = (pyc_add_1038 + pyc_mux_1041); +assign pyc_shli_1043 = (pyc_zext_1016 << 7); +assign pyc_extract_1044 = pyc_concat_1013[7]; +assign pyc_mux_1045 = (pyc_extract_1044 ? pyc_shli_1043 : pyc_comb_20); +assign pyc_add_1046 = (pyc_add_1042 + pyc_mux_1045); +assign pyc_shli_1047 = (pyc_zext_1016 << 8); +assign pyc_mux_1048 = (pyc_extract_1044 ? pyc_shli_1047 : pyc_comb_20); +assign pyc_extract_1049 = pyc_concat_1010[7]; +assign pyc_zext_1050 = {{8{1'b0}}, pyc_concat_1013}; +assign pyc_shli_1051 = (pyc_zext_1050 << 8); +assign pyc_mux_1052 = (pyc_extract_1049 ? pyc_shli_1051 : pyc_comb_20); +assign pyc_sub_1053 = (pyc_add_1046 - pyc_mux_1048); +assign pyc_sub_1054 = (pyc_sub_1053 - pyc_mux_1052); +assign pe_int_s1_p2a_7__next = pyc_sub_1054; +assign pyc_zext_1055 = {{4{1'b0}}, pyc_concat_1010}; +assign pyc_extract_1056 = pyc_extract_1015[0]; +assign pyc_mux_1057 = (pyc_extract_1056 ? pyc_zext_1055 : pyc_comb_19); +assign pyc_shli_1058 = (pyc_zext_1055 << 1); +assign pyc_extract_1059 = pyc_extract_1015[1]; +assign pyc_mux_1060 = (pyc_extract_1059 ? pyc_shli_1058 : pyc_comb_19); +assign pyc_add_1061 = (pyc_mux_1057 + pyc_mux_1060); +assign pyc_shli_1062 = (pyc_zext_1055 << 2); +assign pyc_extract_1063 = pyc_extract_1015[2]; +assign pyc_mux_1064 = (pyc_extract_1063 ? pyc_shli_1062 : pyc_comb_19); +assign pyc_add_1065 = (pyc_add_1061 + pyc_mux_1064); +assign pyc_shli_1066 = (pyc_zext_1055 << 3); +assign pyc_extract_1067 = pyc_extract_1015[3]; +assign pyc_mux_1068 = (pyc_extract_1067 ? pyc_shli_1066 : pyc_comb_19); +assign pyc_add_1069 = (pyc_add_1065 + pyc_mux_1068); +assign pyc_shli_1070 = (pyc_zext_1055 << 4); +assign pyc_mux_1071 = (pyc_extract_1067 ? pyc_shli_1070 : pyc_comb_19); +assign pyc_zext_1072 = {{8{1'b0}}, pyc_extract_1015}; +assign pyc_shli_1073 = (pyc_zext_1072 << 8); +assign pyc_mux_1074 = (pyc_extract_1049 ? pyc_shli_1073 : pyc_comb_19); +assign pyc_sub_1075 = (pyc_add_1069 - pyc_mux_1071); +assign pyc_sub_1076 = (pyc_sub_1075 - pyc_mux_1074); +assign pe_int_s1_p2b0_7__next = pyc_sub_1076; +assign pyc_extract_1077 = pyc_extract_1012[0]; +assign pyc_mux_1078 = (pyc_extract_1077 ? pyc_zext_1055 : pyc_comb_19); +assign pyc_extract_1079 = pyc_extract_1012[1]; +assign pyc_mux_1080 = (pyc_extract_1079 ? pyc_shli_1058 : pyc_comb_19); +assign pyc_add_1081 = (pyc_mux_1078 + pyc_mux_1080); +assign pyc_extract_1082 = pyc_extract_1012[2]; +assign pyc_mux_1083 = (pyc_extract_1082 ? pyc_shli_1062 : pyc_comb_19); +assign pyc_add_1084 = (pyc_add_1081 + pyc_mux_1083); +assign pyc_extract_1085 = pyc_extract_1012[3]; +assign pyc_mux_1086 = (pyc_extract_1085 ? pyc_shli_1066 : pyc_comb_19); +assign pyc_add_1087 = (pyc_add_1084 + pyc_mux_1086); +assign pyc_mux_1088 = (pyc_extract_1085 ? pyc_shli_1070 : pyc_comb_19); +assign pyc_zext_1089 = {{8{1'b0}}, pyc_extract_1012}; +assign pyc_shli_1090 = (pyc_zext_1089 << 8); +assign pyc_mux_1091 = (pyc_extract_1049 ? pyc_shli_1090 : pyc_comb_19); +assign pyc_sub_1092 = (pyc_add_1087 - pyc_mux_1088); +assign pyc_sub_1093 = (pyc_sub_1092 - pyc_mux_1091); +assign pe_int_s1_p2b1_7__next = pyc_sub_1093; +assign pyc_zext_1094 = {{5{1'b0}}, pyc_concat_1010}; +assign pyc_extract_1095 = pyc_extract_1014[0]; +assign pyc_mux_1096 = (pyc_extract_1095 ? pyc_zext_1094 : pyc_comb_18); +assign pyc_shli_1097 = (pyc_zext_1094 << 1); +assign pyc_extract_1098 = pyc_extract_1014[1]; +assign pyc_mux_1099 = (pyc_extract_1098 ? pyc_shli_1097 : pyc_comb_18); +assign pyc_add_1100 = (pyc_mux_1096 + pyc_mux_1099); +assign pyc_shli_1101 = (pyc_zext_1094 << 2); +assign pyc_extract_1102 = pyc_extract_1014[2]; +assign pyc_mux_1103 = (pyc_extract_1102 ? pyc_shli_1101 : pyc_comb_18); +assign pyc_add_1104 = (pyc_add_1100 + pyc_mux_1103); +assign pyc_shli_1105 = (pyc_zext_1094 << 3); +assign pyc_extract_1106 = pyc_extract_1014[3]; +assign pyc_mux_1107 = (pyc_extract_1106 ? pyc_shli_1105 : pyc_comb_18); +assign pyc_add_1108 = (pyc_add_1104 + pyc_mux_1107); +assign pyc_shli_1109 = (pyc_zext_1094 << 4); +assign pyc_extract_1110 = pyc_extract_1014[4]; +assign pyc_mux_1111 = (pyc_extract_1110 ? pyc_shli_1109 : pyc_comb_18); +assign pyc_add_1112 = (pyc_add_1108 + pyc_mux_1111); +assign pyc_shli_1113 = (pyc_zext_1094 << 5); +assign pyc_mux_1114 = (pyc_extract_1110 ? pyc_shli_1113 : pyc_comb_18); +assign pyc_zext_1115 = {{8{1'b0}}, pyc_extract_1014}; +assign pyc_shli_1116 = (pyc_zext_1115 << 8); +assign pyc_mux_1117 = (pyc_extract_1049 ? pyc_shli_1116 : pyc_comb_18); +assign pyc_sub_1118 = (pyc_add_1112 - pyc_mux_1114); +assign pyc_sub_1119 = (pyc_sub_1118 - pyc_mux_1117); +assign pe_int_s1_p2d0_7__next = pyc_sub_1119; +assign pyc_extract_1120 = pyc_extract_1011[0]; +assign pyc_mux_1121 = (pyc_extract_1120 ? pyc_zext_1094 : pyc_comb_18); +assign pyc_extract_1122 = pyc_extract_1011[1]; +assign pyc_mux_1123 = (pyc_extract_1122 ? pyc_shli_1097 : pyc_comb_18); +assign pyc_add_1124 = (pyc_mux_1121 + pyc_mux_1123); +assign pyc_extract_1125 = pyc_extract_1011[2]; +assign pyc_mux_1126 = (pyc_extract_1125 ? pyc_shli_1101 : pyc_comb_18); +assign pyc_add_1127 = (pyc_add_1124 + pyc_mux_1126); +assign pyc_extract_1128 = pyc_extract_1011[3]; +assign pyc_mux_1129 = (pyc_extract_1128 ? pyc_shli_1105 : pyc_comb_18); +assign pyc_add_1130 = (pyc_add_1127 + pyc_mux_1129); +assign pyc_extract_1131 = pyc_extract_1011[4]; +assign pyc_mux_1132 = (pyc_extract_1131 ? pyc_shli_1109 : pyc_comb_18); +assign pyc_add_1133 = (pyc_add_1130 + pyc_mux_1132); +assign pyc_mux_1134 = (pyc_extract_1131 ? pyc_shli_1113 : pyc_comb_18); +assign pyc_zext_1135 = {{8{1'b0}}, pyc_extract_1011}; +assign pyc_shli_1136 = (pyc_zext_1135 << 8); +assign pyc_mux_1137 = (pyc_extract_1049 ? pyc_shli_1136 : pyc_comb_18); +assign pyc_sub_1138 = (pyc_add_1133 - pyc_mux_1134); +assign pyc_sub_1139 = (pyc_sub_1138 - pyc_mux_1137); +assign pe_int_s1_p2d1_7__next = pyc_sub_1139; +assign pyc_extract_1140 = pe_int_s0_b1[4:0]; +assign pyc_zext_1141 = {{5{1'b0}}, pyc_extract_52}; +assign pyc_extract_1142 = pyc_extract_57[0]; +assign pyc_mux_1143 = (pyc_extract_1142 ? pyc_zext_1141 : pyc_comb_17); +assign pyc_shli_1144 = (pyc_zext_1141 << 1); +assign pyc_extract_1145 = pyc_extract_57[1]; +assign pyc_mux_1146 = (pyc_extract_1145 ? pyc_shli_1144 : pyc_comb_17); +assign pyc_add_1147 = (pyc_mux_1143 + pyc_mux_1146); +assign pyc_shli_1148 = (pyc_zext_1141 << 2); +assign pyc_extract_1149 = pyc_extract_57[2]; +assign pyc_mux_1150 = (pyc_extract_1149 ? pyc_shli_1148 : pyc_comb_17); +assign pyc_add_1151 = (pyc_add_1147 + pyc_mux_1150); +assign pyc_shli_1152 = (pyc_zext_1141 << 3); +assign pyc_extract_1153 = pyc_extract_57[3]; +assign pyc_mux_1154 = (pyc_extract_1153 ? pyc_shli_1152 : pyc_comb_17); +assign pyc_add_1155 = (pyc_add_1151 + pyc_mux_1154); +assign pyc_shli_1156 = (pyc_zext_1141 << 4); +assign pyc_extract_1157 = pyc_extract_57[4]; +assign pyc_mux_1158 = (pyc_extract_1157 ? pyc_shli_1156 : pyc_comb_17); +assign pyc_add_1159 = (pyc_add_1155 + pyc_mux_1158); +assign pyc_shli_1160 = (pyc_zext_1141 << 5); +assign pyc_mux_1161 = (pyc_extract_1157 ? pyc_shli_1160 : pyc_comb_17); +assign pyc_extract_1162 = pyc_extract_52[4]; +assign pyc_zext_1163 = {{5{1'b0}}, pyc_extract_57}; +assign pyc_shli_1164 = (pyc_zext_1163 << 5); +assign pyc_mux_1165 = (pyc_extract_1162 ? pyc_shli_1164 : pyc_comb_17); +assign pyc_sub_1166 = (pyc_add_1159 - pyc_mux_1161); +assign pyc_sub_1167 = (pyc_sub_1166 - pyc_mux_1165); +assign pe_int_s1_p2c0_0__next = pyc_sub_1167; +assign pyc_extract_1168 = pyc_extract_1140[0]; +assign pyc_mux_1169 = (pyc_extract_1168 ? pyc_zext_1141 : pyc_comb_17); +assign pyc_extract_1170 = pyc_extract_1140[1]; +assign pyc_mux_1171 = (pyc_extract_1170 ? pyc_shli_1144 : pyc_comb_17); +assign pyc_add_1172 = (pyc_mux_1169 + pyc_mux_1171); +assign pyc_extract_1173 = pyc_extract_1140[2]; +assign pyc_mux_1174 = (pyc_extract_1173 ? pyc_shli_1148 : pyc_comb_17); +assign pyc_add_1175 = (pyc_add_1172 + pyc_mux_1174); +assign pyc_extract_1176 = pyc_extract_1140[3]; +assign pyc_mux_1177 = (pyc_extract_1176 ? pyc_shli_1152 : pyc_comb_17); +assign pyc_add_1178 = (pyc_add_1175 + pyc_mux_1177); +assign pyc_extract_1179 = pyc_extract_1140[4]; +assign pyc_mux_1180 = (pyc_extract_1179 ? pyc_shli_1156 : pyc_comb_17); +assign pyc_add_1181 = (pyc_add_1178 + pyc_mux_1180); +assign pyc_mux_1182 = (pyc_extract_1179 ? pyc_shli_1160 : pyc_comb_17); +assign pyc_zext_1183 = {{5{1'b0}}, pyc_extract_1140}; +assign pyc_shli_1184 = (pyc_zext_1183 << 5); +assign pyc_mux_1185 = (pyc_extract_1162 ? pyc_shli_1184 : pyc_comb_17); +assign pyc_sub_1186 = (pyc_add_1181 - pyc_mux_1182); +assign pyc_sub_1187 = (pyc_sub_1186 - pyc_mux_1185); +assign pe_int_s1_p2c1_0__next = pyc_sub_1187; +assign pyc_extract_1188 = pe_int_s0_b1[9:5]; +assign pyc_zext_1189 = {{5{1'b0}}, pyc_extract_53}; +assign pyc_extract_1190 = pyc_extract_58[0]; +assign pyc_mux_1191 = (pyc_extract_1190 ? pyc_zext_1189 : pyc_comb_17); +assign pyc_shli_1192 = (pyc_zext_1189 << 1); +assign pyc_extract_1193 = pyc_extract_58[1]; +assign pyc_mux_1194 = (pyc_extract_1193 ? pyc_shli_1192 : pyc_comb_17); +assign pyc_add_1195 = (pyc_mux_1191 + pyc_mux_1194); +assign pyc_shli_1196 = (pyc_zext_1189 << 2); +assign pyc_extract_1197 = pyc_extract_58[2]; +assign pyc_mux_1198 = (pyc_extract_1197 ? pyc_shli_1196 : pyc_comb_17); +assign pyc_add_1199 = (pyc_add_1195 + pyc_mux_1198); +assign pyc_shli_1200 = (pyc_zext_1189 << 3); +assign pyc_extract_1201 = pyc_extract_58[3]; +assign pyc_mux_1202 = (pyc_extract_1201 ? pyc_shli_1200 : pyc_comb_17); +assign pyc_add_1203 = (pyc_add_1199 + pyc_mux_1202); +assign pyc_shli_1204 = (pyc_zext_1189 << 4); +assign pyc_extract_1205 = pyc_extract_58[4]; +assign pyc_mux_1206 = (pyc_extract_1205 ? pyc_shli_1204 : pyc_comb_17); +assign pyc_add_1207 = (pyc_add_1203 + pyc_mux_1206); +assign pyc_shli_1208 = (pyc_zext_1189 << 5); +assign pyc_mux_1209 = (pyc_extract_1205 ? pyc_shli_1208 : pyc_comb_17); +assign pyc_extract_1210 = pyc_extract_53[4]; +assign pyc_zext_1211 = {{5{1'b0}}, pyc_extract_58}; +assign pyc_shli_1212 = (pyc_zext_1211 << 5); +assign pyc_mux_1213 = (pyc_extract_1210 ? pyc_shli_1212 : pyc_comb_17); +assign pyc_sub_1214 = (pyc_add_1207 - pyc_mux_1209); +assign pyc_sub_1215 = (pyc_sub_1214 - pyc_mux_1213); +assign pe_int_s1_p2c0_1__next = pyc_sub_1215; +assign pyc_extract_1216 = pyc_extract_1188[0]; +assign pyc_mux_1217 = (pyc_extract_1216 ? pyc_zext_1189 : pyc_comb_17); +assign pyc_extract_1218 = pyc_extract_1188[1]; +assign pyc_mux_1219 = (pyc_extract_1218 ? pyc_shli_1192 : pyc_comb_17); +assign pyc_add_1220 = (pyc_mux_1217 + pyc_mux_1219); +assign pyc_extract_1221 = pyc_extract_1188[2]; +assign pyc_mux_1222 = (pyc_extract_1221 ? pyc_shli_1196 : pyc_comb_17); +assign pyc_add_1223 = (pyc_add_1220 + pyc_mux_1222); +assign pyc_extract_1224 = pyc_extract_1188[3]; +assign pyc_mux_1225 = (pyc_extract_1224 ? pyc_shli_1200 : pyc_comb_17); +assign pyc_add_1226 = (pyc_add_1223 + pyc_mux_1225); +assign pyc_extract_1227 = pyc_extract_1188[4]; +assign pyc_mux_1228 = (pyc_extract_1227 ? pyc_shli_1204 : pyc_comb_17); +assign pyc_add_1229 = (pyc_add_1226 + pyc_mux_1228); +assign pyc_mux_1230 = (pyc_extract_1227 ? pyc_shli_1208 : pyc_comb_17); +assign pyc_zext_1231 = {{5{1'b0}}, pyc_extract_1188}; +assign pyc_shli_1232 = (pyc_zext_1231 << 5); +assign pyc_mux_1233 = (pyc_extract_1210 ? pyc_shli_1232 : pyc_comb_17); +assign pyc_sub_1234 = (pyc_add_1229 - pyc_mux_1230); +assign pyc_sub_1235 = (pyc_sub_1234 - pyc_mux_1233); +assign pe_int_s1_p2c1_1__next = pyc_sub_1235; +assign pyc_extract_1236 = pe_int_s0_b1[14:10]; +assign pyc_zext_1237 = {{5{1'b0}}, pyc_extract_190}; +assign pyc_extract_1238 = pyc_extract_195[0]; +assign pyc_mux_1239 = (pyc_extract_1238 ? pyc_zext_1237 : pyc_comb_17); +assign pyc_shli_1240 = (pyc_zext_1237 << 1); +assign pyc_extract_1241 = pyc_extract_195[1]; +assign pyc_mux_1242 = (pyc_extract_1241 ? pyc_shli_1240 : pyc_comb_17); +assign pyc_add_1243 = (pyc_mux_1239 + pyc_mux_1242); +assign pyc_shli_1244 = (pyc_zext_1237 << 2); +assign pyc_extract_1245 = pyc_extract_195[2]; +assign pyc_mux_1246 = (pyc_extract_1245 ? pyc_shli_1244 : pyc_comb_17); +assign pyc_add_1247 = (pyc_add_1243 + pyc_mux_1246); +assign pyc_shli_1248 = (pyc_zext_1237 << 3); +assign pyc_extract_1249 = pyc_extract_195[3]; +assign pyc_mux_1250 = (pyc_extract_1249 ? pyc_shli_1248 : pyc_comb_17); +assign pyc_add_1251 = (pyc_add_1247 + pyc_mux_1250); +assign pyc_shli_1252 = (pyc_zext_1237 << 4); +assign pyc_extract_1253 = pyc_extract_195[4]; +assign pyc_mux_1254 = (pyc_extract_1253 ? pyc_shli_1252 : pyc_comb_17); +assign pyc_add_1255 = (pyc_add_1251 + pyc_mux_1254); +assign pyc_shli_1256 = (pyc_zext_1237 << 5); +assign pyc_mux_1257 = (pyc_extract_1253 ? pyc_shli_1256 : pyc_comb_17); +assign pyc_extract_1258 = pyc_extract_190[4]; +assign pyc_zext_1259 = {{5{1'b0}}, pyc_extract_195}; +assign pyc_shli_1260 = (pyc_zext_1259 << 5); +assign pyc_mux_1261 = (pyc_extract_1258 ? pyc_shli_1260 : pyc_comb_17); +assign pyc_sub_1262 = (pyc_add_1255 - pyc_mux_1257); +assign pyc_sub_1263 = (pyc_sub_1262 - pyc_mux_1261); +assign pe_int_s1_p2c0_2__next = pyc_sub_1263; +assign pyc_extract_1264 = pyc_extract_1236[0]; +assign pyc_mux_1265 = (pyc_extract_1264 ? pyc_zext_1237 : pyc_comb_17); +assign pyc_extract_1266 = pyc_extract_1236[1]; +assign pyc_mux_1267 = (pyc_extract_1266 ? pyc_shli_1240 : pyc_comb_17); +assign pyc_add_1268 = (pyc_mux_1265 + pyc_mux_1267); +assign pyc_extract_1269 = pyc_extract_1236[2]; +assign pyc_mux_1270 = (pyc_extract_1269 ? pyc_shli_1244 : pyc_comb_17); +assign pyc_add_1271 = (pyc_add_1268 + pyc_mux_1270); +assign pyc_extract_1272 = pyc_extract_1236[3]; +assign pyc_mux_1273 = (pyc_extract_1272 ? pyc_shli_1248 : pyc_comb_17); +assign pyc_add_1274 = (pyc_add_1271 + pyc_mux_1273); +assign pyc_extract_1275 = pyc_extract_1236[4]; +assign pyc_mux_1276 = (pyc_extract_1275 ? pyc_shli_1252 : pyc_comb_17); +assign pyc_add_1277 = (pyc_add_1274 + pyc_mux_1276); +assign pyc_mux_1278 = (pyc_extract_1275 ? pyc_shli_1256 : pyc_comb_17); +assign pyc_zext_1279 = {{5{1'b0}}, pyc_extract_1236}; +assign pyc_shli_1280 = (pyc_zext_1279 << 5); +assign pyc_mux_1281 = (pyc_extract_1258 ? pyc_shli_1280 : pyc_comb_17); +assign pyc_sub_1282 = (pyc_add_1277 - pyc_mux_1278); +assign pyc_sub_1283 = (pyc_sub_1282 - pyc_mux_1281); +assign pe_int_s1_p2c1_2__next = pyc_sub_1283; +assign pyc_extract_1284 = pe_int_s0_b1[19:15]; +assign pyc_zext_1285 = {{5{1'b0}}, pyc_extract_191}; +assign pyc_extract_1286 = pyc_extract_196[0]; +assign pyc_mux_1287 = (pyc_extract_1286 ? pyc_zext_1285 : pyc_comb_17); +assign pyc_shli_1288 = (pyc_zext_1285 << 1); +assign pyc_extract_1289 = pyc_extract_196[1]; +assign pyc_mux_1290 = (pyc_extract_1289 ? pyc_shli_1288 : pyc_comb_17); +assign pyc_add_1291 = (pyc_mux_1287 + pyc_mux_1290); +assign pyc_shli_1292 = (pyc_zext_1285 << 2); +assign pyc_extract_1293 = pyc_extract_196[2]; +assign pyc_mux_1294 = (pyc_extract_1293 ? pyc_shli_1292 : pyc_comb_17); +assign pyc_add_1295 = (pyc_add_1291 + pyc_mux_1294); +assign pyc_shli_1296 = (pyc_zext_1285 << 3); +assign pyc_extract_1297 = pyc_extract_196[3]; +assign pyc_mux_1298 = (pyc_extract_1297 ? pyc_shli_1296 : pyc_comb_17); +assign pyc_add_1299 = (pyc_add_1295 + pyc_mux_1298); +assign pyc_shli_1300 = (pyc_zext_1285 << 4); +assign pyc_extract_1301 = pyc_extract_196[4]; +assign pyc_mux_1302 = (pyc_extract_1301 ? pyc_shli_1300 : pyc_comb_17); +assign pyc_add_1303 = (pyc_add_1299 + pyc_mux_1302); +assign pyc_shli_1304 = (pyc_zext_1285 << 5); +assign pyc_mux_1305 = (pyc_extract_1301 ? pyc_shli_1304 : pyc_comb_17); +assign pyc_extract_1306 = pyc_extract_191[4]; +assign pyc_zext_1307 = {{5{1'b0}}, pyc_extract_196}; +assign pyc_shli_1308 = (pyc_zext_1307 << 5); +assign pyc_mux_1309 = (pyc_extract_1306 ? pyc_shli_1308 : pyc_comb_17); +assign pyc_sub_1310 = (pyc_add_1303 - pyc_mux_1305); +assign pyc_sub_1311 = (pyc_sub_1310 - pyc_mux_1309); +assign pe_int_s1_p2c0_3__next = pyc_sub_1311; +assign pyc_extract_1312 = pyc_extract_1284[0]; +assign pyc_mux_1313 = (pyc_extract_1312 ? pyc_zext_1285 : pyc_comb_17); +assign pyc_extract_1314 = pyc_extract_1284[1]; +assign pyc_mux_1315 = (pyc_extract_1314 ? pyc_shli_1288 : pyc_comb_17); +assign pyc_add_1316 = (pyc_mux_1313 + pyc_mux_1315); +assign pyc_extract_1317 = pyc_extract_1284[2]; +assign pyc_mux_1318 = (pyc_extract_1317 ? pyc_shli_1292 : pyc_comb_17); +assign pyc_add_1319 = (pyc_add_1316 + pyc_mux_1318); +assign pyc_extract_1320 = pyc_extract_1284[3]; +assign pyc_mux_1321 = (pyc_extract_1320 ? pyc_shli_1296 : pyc_comb_17); +assign pyc_add_1322 = (pyc_add_1319 + pyc_mux_1321); +assign pyc_extract_1323 = pyc_extract_1284[4]; +assign pyc_mux_1324 = (pyc_extract_1323 ? pyc_shli_1300 : pyc_comb_17); +assign pyc_add_1325 = (pyc_add_1322 + pyc_mux_1324); +assign pyc_mux_1326 = (pyc_extract_1323 ? pyc_shli_1304 : pyc_comb_17); +assign pyc_zext_1327 = {{5{1'b0}}, pyc_extract_1284}; +assign pyc_shli_1328 = (pyc_zext_1327 << 5); +assign pyc_mux_1329 = (pyc_extract_1306 ? pyc_shli_1328 : pyc_comb_17); +assign pyc_sub_1330 = (pyc_add_1325 - pyc_mux_1326); +assign pyc_sub_1331 = (pyc_sub_1330 - pyc_mux_1329); +assign pe_int_s1_p2c1_3__next = pyc_sub_1331; +assign pyc_extract_1332 = pe_int_s0_b1[24:20]; +assign pyc_zext_1333 = {{5{1'b0}}, pyc_extract_328}; +assign pyc_extract_1334 = pyc_extract_333[0]; +assign pyc_mux_1335 = (pyc_extract_1334 ? pyc_zext_1333 : pyc_comb_17); +assign pyc_shli_1336 = (pyc_zext_1333 << 1); +assign pyc_extract_1337 = pyc_extract_333[1]; +assign pyc_mux_1338 = (pyc_extract_1337 ? pyc_shli_1336 : pyc_comb_17); +assign pyc_add_1339 = (pyc_mux_1335 + pyc_mux_1338); +assign pyc_shli_1340 = (pyc_zext_1333 << 2); +assign pyc_extract_1341 = pyc_extract_333[2]; +assign pyc_mux_1342 = (pyc_extract_1341 ? pyc_shli_1340 : pyc_comb_17); +assign pyc_add_1343 = (pyc_add_1339 + pyc_mux_1342); +assign pyc_shli_1344 = (pyc_zext_1333 << 3); +assign pyc_extract_1345 = pyc_extract_333[3]; +assign pyc_mux_1346 = (pyc_extract_1345 ? pyc_shli_1344 : pyc_comb_17); +assign pyc_add_1347 = (pyc_add_1343 + pyc_mux_1346); +assign pyc_shli_1348 = (pyc_zext_1333 << 4); +assign pyc_extract_1349 = pyc_extract_333[4]; +assign pyc_mux_1350 = (pyc_extract_1349 ? pyc_shli_1348 : pyc_comb_17); +assign pyc_add_1351 = (pyc_add_1347 + pyc_mux_1350); +assign pyc_shli_1352 = (pyc_zext_1333 << 5); +assign pyc_mux_1353 = (pyc_extract_1349 ? pyc_shli_1352 : pyc_comb_17); +assign pyc_extract_1354 = pyc_extract_328[4]; +assign pyc_zext_1355 = {{5{1'b0}}, pyc_extract_333}; +assign pyc_shli_1356 = (pyc_zext_1355 << 5); +assign pyc_mux_1357 = (pyc_extract_1354 ? pyc_shli_1356 : pyc_comb_17); +assign pyc_sub_1358 = (pyc_add_1351 - pyc_mux_1353); +assign pyc_sub_1359 = (pyc_sub_1358 - pyc_mux_1357); +assign pe_int_s1_p2c0_4__next = pyc_sub_1359; +assign pyc_extract_1360 = pyc_extract_1332[0]; +assign pyc_mux_1361 = (pyc_extract_1360 ? pyc_zext_1333 : pyc_comb_17); +assign pyc_extract_1362 = pyc_extract_1332[1]; +assign pyc_mux_1363 = (pyc_extract_1362 ? pyc_shli_1336 : pyc_comb_17); +assign pyc_add_1364 = (pyc_mux_1361 + pyc_mux_1363); +assign pyc_extract_1365 = pyc_extract_1332[2]; +assign pyc_mux_1366 = (pyc_extract_1365 ? pyc_shli_1340 : pyc_comb_17); +assign pyc_add_1367 = (pyc_add_1364 + pyc_mux_1366); +assign pyc_extract_1368 = pyc_extract_1332[3]; +assign pyc_mux_1369 = (pyc_extract_1368 ? pyc_shli_1344 : pyc_comb_17); +assign pyc_add_1370 = (pyc_add_1367 + pyc_mux_1369); +assign pyc_extract_1371 = pyc_extract_1332[4]; +assign pyc_mux_1372 = (pyc_extract_1371 ? pyc_shli_1348 : pyc_comb_17); +assign pyc_add_1373 = (pyc_add_1370 + pyc_mux_1372); +assign pyc_mux_1374 = (pyc_extract_1371 ? pyc_shli_1352 : pyc_comb_17); +assign pyc_zext_1375 = {{5{1'b0}}, pyc_extract_1332}; +assign pyc_shli_1376 = (pyc_zext_1375 << 5); +assign pyc_mux_1377 = (pyc_extract_1354 ? pyc_shli_1376 : pyc_comb_17); +assign pyc_sub_1378 = (pyc_add_1373 - pyc_mux_1374); +assign pyc_sub_1379 = (pyc_sub_1378 - pyc_mux_1377); +assign pe_int_s1_p2c1_4__next = pyc_sub_1379; +assign pyc_extract_1380 = pe_int_s0_b1[29:25]; +assign pyc_zext_1381 = {{5{1'b0}}, pyc_extract_329}; +assign pyc_extract_1382 = pyc_extract_334[0]; +assign pyc_mux_1383 = (pyc_extract_1382 ? pyc_zext_1381 : pyc_comb_17); +assign pyc_shli_1384 = (pyc_zext_1381 << 1); +assign pyc_extract_1385 = pyc_extract_334[1]; +assign pyc_mux_1386 = (pyc_extract_1385 ? pyc_shli_1384 : pyc_comb_17); +assign pyc_add_1387 = (pyc_mux_1383 + pyc_mux_1386); +assign pyc_shli_1388 = (pyc_zext_1381 << 2); +assign pyc_extract_1389 = pyc_extract_334[2]; +assign pyc_mux_1390 = (pyc_extract_1389 ? pyc_shli_1388 : pyc_comb_17); +assign pyc_add_1391 = (pyc_add_1387 + pyc_mux_1390); +assign pyc_shli_1392 = (pyc_zext_1381 << 3); +assign pyc_extract_1393 = pyc_extract_334[3]; +assign pyc_mux_1394 = (pyc_extract_1393 ? pyc_shli_1392 : pyc_comb_17); +assign pyc_add_1395 = (pyc_add_1391 + pyc_mux_1394); +assign pyc_shli_1396 = (pyc_zext_1381 << 4); +assign pyc_extract_1397 = pyc_extract_334[4]; +assign pyc_mux_1398 = (pyc_extract_1397 ? pyc_shli_1396 : pyc_comb_17); +assign pyc_add_1399 = (pyc_add_1395 + pyc_mux_1398); +assign pyc_shli_1400 = (pyc_zext_1381 << 5); +assign pyc_mux_1401 = (pyc_extract_1397 ? pyc_shli_1400 : pyc_comb_17); +assign pyc_extract_1402 = pyc_extract_329[4]; +assign pyc_zext_1403 = {{5{1'b0}}, pyc_extract_334}; +assign pyc_shli_1404 = (pyc_zext_1403 << 5); +assign pyc_mux_1405 = (pyc_extract_1402 ? pyc_shli_1404 : pyc_comb_17); +assign pyc_sub_1406 = (pyc_add_1399 - pyc_mux_1401); +assign pyc_sub_1407 = (pyc_sub_1406 - pyc_mux_1405); +assign pe_int_s1_p2c0_5__next = pyc_sub_1407; +assign pyc_extract_1408 = pyc_extract_1380[0]; +assign pyc_mux_1409 = (pyc_extract_1408 ? pyc_zext_1381 : pyc_comb_17); +assign pyc_extract_1410 = pyc_extract_1380[1]; +assign pyc_mux_1411 = (pyc_extract_1410 ? pyc_shli_1384 : pyc_comb_17); +assign pyc_add_1412 = (pyc_mux_1409 + pyc_mux_1411); +assign pyc_extract_1413 = pyc_extract_1380[2]; +assign pyc_mux_1414 = (pyc_extract_1413 ? pyc_shli_1388 : pyc_comb_17); +assign pyc_add_1415 = (pyc_add_1412 + pyc_mux_1414); +assign pyc_extract_1416 = pyc_extract_1380[3]; +assign pyc_mux_1417 = (pyc_extract_1416 ? pyc_shli_1392 : pyc_comb_17); +assign pyc_add_1418 = (pyc_add_1415 + pyc_mux_1417); +assign pyc_extract_1419 = pyc_extract_1380[4]; +assign pyc_mux_1420 = (pyc_extract_1419 ? pyc_shli_1396 : pyc_comb_17); +assign pyc_add_1421 = (pyc_add_1418 + pyc_mux_1420); +assign pyc_mux_1422 = (pyc_extract_1419 ? pyc_shli_1400 : pyc_comb_17); +assign pyc_zext_1423 = {{5{1'b0}}, pyc_extract_1380}; +assign pyc_shli_1424 = (pyc_zext_1423 << 5); +assign pyc_mux_1425 = (pyc_extract_1402 ? pyc_shli_1424 : pyc_comb_17); +assign pyc_sub_1426 = (pyc_add_1421 - pyc_mux_1422); +assign pyc_sub_1427 = (pyc_sub_1426 - pyc_mux_1425); +assign pe_int_s1_p2c1_5__next = pyc_sub_1427; +assign pyc_extract_1428 = pe_int_s0_b1[34:30]; +assign pyc_zext_1429 = {{5{1'b0}}, pyc_extract_466}; +assign pyc_extract_1430 = pyc_extract_471[0]; +assign pyc_mux_1431 = (pyc_extract_1430 ? pyc_zext_1429 : pyc_comb_17); +assign pyc_shli_1432 = (pyc_zext_1429 << 1); +assign pyc_extract_1433 = pyc_extract_471[1]; +assign pyc_mux_1434 = (pyc_extract_1433 ? pyc_shli_1432 : pyc_comb_17); +assign pyc_add_1435 = (pyc_mux_1431 + pyc_mux_1434); +assign pyc_shli_1436 = (pyc_zext_1429 << 2); +assign pyc_extract_1437 = pyc_extract_471[2]; +assign pyc_mux_1438 = (pyc_extract_1437 ? pyc_shli_1436 : pyc_comb_17); +assign pyc_add_1439 = (pyc_add_1435 + pyc_mux_1438); +assign pyc_shli_1440 = (pyc_zext_1429 << 3); +assign pyc_extract_1441 = pyc_extract_471[3]; +assign pyc_mux_1442 = (pyc_extract_1441 ? pyc_shli_1440 : pyc_comb_17); +assign pyc_add_1443 = (pyc_add_1439 + pyc_mux_1442); +assign pyc_shli_1444 = (pyc_zext_1429 << 4); +assign pyc_extract_1445 = pyc_extract_471[4]; +assign pyc_mux_1446 = (pyc_extract_1445 ? pyc_shli_1444 : pyc_comb_17); +assign pyc_add_1447 = (pyc_add_1443 + pyc_mux_1446); +assign pyc_shli_1448 = (pyc_zext_1429 << 5); +assign pyc_mux_1449 = (pyc_extract_1445 ? pyc_shli_1448 : pyc_comb_17); +assign pyc_extract_1450 = pyc_extract_466[4]; +assign pyc_zext_1451 = {{5{1'b0}}, pyc_extract_471}; +assign pyc_shli_1452 = (pyc_zext_1451 << 5); +assign pyc_mux_1453 = (pyc_extract_1450 ? pyc_shli_1452 : pyc_comb_17); +assign pyc_sub_1454 = (pyc_add_1447 - pyc_mux_1449); +assign pyc_sub_1455 = (pyc_sub_1454 - pyc_mux_1453); +assign pe_int_s1_p2c0_6__next = pyc_sub_1455; +assign pyc_extract_1456 = pyc_extract_1428[0]; +assign pyc_mux_1457 = (pyc_extract_1456 ? pyc_zext_1429 : pyc_comb_17); +assign pyc_extract_1458 = pyc_extract_1428[1]; +assign pyc_mux_1459 = (pyc_extract_1458 ? pyc_shli_1432 : pyc_comb_17); +assign pyc_add_1460 = (pyc_mux_1457 + pyc_mux_1459); +assign pyc_extract_1461 = pyc_extract_1428[2]; +assign pyc_mux_1462 = (pyc_extract_1461 ? pyc_shli_1436 : pyc_comb_17); +assign pyc_add_1463 = (pyc_add_1460 + pyc_mux_1462); +assign pyc_extract_1464 = pyc_extract_1428[3]; +assign pyc_mux_1465 = (pyc_extract_1464 ? pyc_shli_1440 : pyc_comb_17); +assign pyc_add_1466 = (pyc_add_1463 + pyc_mux_1465); +assign pyc_extract_1467 = pyc_extract_1428[4]; +assign pyc_mux_1468 = (pyc_extract_1467 ? pyc_shli_1444 : pyc_comb_17); +assign pyc_add_1469 = (pyc_add_1466 + pyc_mux_1468); +assign pyc_mux_1470 = (pyc_extract_1467 ? pyc_shli_1448 : pyc_comb_17); +assign pyc_zext_1471 = {{5{1'b0}}, pyc_extract_1428}; +assign pyc_shli_1472 = (pyc_zext_1471 << 5); +assign pyc_mux_1473 = (pyc_extract_1450 ? pyc_shli_1472 : pyc_comb_17); +assign pyc_sub_1474 = (pyc_add_1469 - pyc_mux_1470); +assign pyc_sub_1475 = (pyc_sub_1474 - pyc_mux_1473); +assign pe_int_s1_p2c1_6__next = pyc_sub_1475; +assign pyc_extract_1476 = pe_int_s0_b1[39:35]; +assign pyc_zext_1477 = {{5{1'b0}}, pyc_extract_467}; +assign pyc_extract_1478 = pyc_extract_472[0]; +assign pyc_mux_1479 = (pyc_extract_1478 ? pyc_zext_1477 : pyc_comb_17); +assign pyc_shli_1480 = (pyc_zext_1477 << 1); +assign pyc_extract_1481 = pyc_extract_472[1]; +assign pyc_mux_1482 = (pyc_extract_1481 ? pyc_shli_1480 : pyc_comb_17); +assign pyc_add_1483 = (pyc_mux_1479 + pyc_mux_1482); +assign pyc_shli_1484 = (pyc_zext_1477 << 2); +assign pyc_extract_1485 = pyc_extract_472[2]; +assign pyc_mux_1486 = (pyc_extract_1485 ? pyc_shli_1484 : pyc_comb_17); +assign pyc_add_1487 = (pyc_add_1483 + pyc_mux_1486); +assign pyc_shli_1488 = (pyc_zext_1477 << 3); +assign pyc_extract_1489 = pyc_extract_472[3]; +assign pyc_mux_1490 = (pyc_extract_1489 ? pyc_shli_1488 : pyc_comb_17); +assign pyc_add_1491 = (pyc_add_1487 + pyc_mux_1490); +assign pyc_shli_1492 = (pyc_zext_1477 << 4); +assign pyc_extract_1493 = pyc_extract_472[4]; +assign pyc_mux_1494 = (pyc_extract_1493 ? pyc_shli_1492 : pyc_comb_17); +assign pyc_add_1495 = (pyc_add_1491 + pyc_mux_1494); +assign pyc_shli_1496 = (pyc_zext_1477 << 5); +assign pyc_mux_1497 = (pyc_extract_1493 ? pyc_shli_1496 : pyc_comb_17); +assign pyc_extract_1498 = pyc_extract_467[4]; +assign pyc_zext_1499 = {{5{1'b0}}, pyc_extract_472}; +assign pyc_shli_1500 = (pyc_zext_1499 << 5); +assign pyc_mux_1501 = (pyc_extract_1498 ? pyc_shli_1500 : pyc_comb_17); +assign pyc_sub_1502 = (pyc_add_1495 - pyc_mux_1497); +assign pyc_sub_1503 = (pyc_sub_1502 - pyc_mux_1501); +assign pe_int_s1_p2c0_7__next = pyc_sub_1503; +assign pyc_extract_1504 = pyc_extract_1476[0]; +assign pyc_mux_1505 = (pyc_extract_1504 ? pyc_zext_1477 : pyc_comb_17); +assign pyc_extract_1506 = pyc_extract_1476[1]; +assign pyc_mux_1507 = (pyc_extract_1506 ? pyc_shli_1480 : pyc_comb_17); +assign pyc_add_1508 = (pyc_mux_1505 + pyc_mux_1507); +assign pyc_extract_1509 = pyc_extract_1476[2]; +assign pyc_mux_1510 = (pyc_extract_1509 ? pyc_shli_1484 : pyc_comb_17); +assign pyc_add_1511 = (pyc_add_1508 + pyc_mux_1510); +assign pyc_extract_1512 = pyc_extract_1476[3]; +assign pyc_mux_1513 = (pyc_extract_1512 ? pyc_shli_1488 : pyc_comb_17); +assign pyc_add_1514 = (pyc_add_1511 + pyc_mux_1513); +assign pyc_extract_1515 = pyc_extract_1476[4]; +assign pyc_mux_1516 = (pyc_extract_1515 ? pyc_shli_1492 : pyc_comb_17); +assign pyc_add_1517 = (pyc_add_1514 + pyc_mux_1516); +assign pyc_mux_1518 = (pyc_extract_1515 ? pyc_shli_1496 : pyc_comb_17); +assign pyc_zext_1519 = {{5{1'b0}}, pyc_extract_1476}; +assign pyc_shli_1520 = (pyc_zext_1519 << 5); +assign pyc_mux_1521 = (pyc_extract_1498 ? pyc_shli_1520 : pyc_comb_17); +assign pyc_sub_1522 = (pyc_add_1517 - pyc_mux_1518); +assign pyc_sub_1523 = (pyc_sub_1522 - pyc_mux_1521); +assign pe_int_s1_p2c1_7__next = pyc_sub_1523; +assign pyc_extract_1524 = pe_int_s0_b1[44:40]; +assign pyc_zext_1525 = {{5{1'b0}}, pyc_extract_604}; +assign pyc_mux_1526 = (pyc_extract_170 ? pyc_zext_1525 : pyc_comb_17); +assign pyc_shli_1527 = (pyc_zext_1525 << 1); +assign pyc_mux_1528 = (pyc_extract_172 ? pyc_shli_1527 : pyc_comb_17); +assign pyc_add_1529 = (pyc_mux_1526 + pyc_mux_1528); +assign pyc_shli_1530 = (pyc_zext_1525 << 2); +assign pyc_mux_1531 = (pyc_extract_175 ? pyc_shli_1530 : pyc_comb_17); +assign pyc_add_1532 = (pyc_add_1529 + pyc_mux_1531); +assign pyc_shli_1533 = (pyc_zext_1525 << 3); +assign pyc_mux_1534 = (pyc_extract_178 ? pyc_shli_1533 : pyc_comb_17); +assign pyc_add_1535 = (pyc_add_1532 + pyc_mux_1534); +assign pyc_shli_1536 = (pyc_zext_1525 << 4); +assign pyc_mux_1537 = (pyc_extract_181 ? pyc_shli_1536 : pyc_comb_17); +assign pyc_add_1538 = (pyc_add_1535 + pyc_mux_1537); +assign pyc_shli_1539 = (pyc_zext_1525 << 5); +assign pyc_mux_1540 = (pyc_extract_181 ? pyc_shli_1539 : pyc_comb_17); +assign pyc_extract_1541 = pyc_extract_604[4]; +assign pyc_zext_1542 = {{5{1'b0}}, pyc_extract_64}; +assign pyc_shli_1543 = (pyc_zext_1542 << 5); +assign pyc_mux_1544 = (pyc_extract_1541 ? pyc_shli_1543 : pyc_comb_17); +assign pyc_sub_1545 = (pyc_add_1538 - pyc_mux_1540); +assign pyc_sub_1546 = (pyc_sub_1545 - pyc_mux_1544); +assign pe_int_s1_p2c0_8__next = pyc_sub_1546; +assign pyc_extract_1547 = pyc_extract_1524[0]; +assign pyc_mux_1548 = (pyc_extract_1547 ? pyc_zext_1525 : pyc_comb_17); +assign pyc_extract_1549 = pyc_extract_1524[1]; +assign pyc_mux_1550 = (pyc_extract_1549 ? pyc_shli_1527 : pyc_comb_17); +assign pyc_add_1551 = (pyc_mux_1548 + pyc_mux_1550); +assign pyc_extract_1552 = pyc_extract_1524[2]; +assign pyc_mux_1553 = (pyc_extract_1552 ? pyc_shli_1530 : pyc_comb_17); +assign pyc_add_1554 = (pyc_add_1551 + pyc_mux_1553); +assign pyc_extract_1555 = pyc_extract_1524[3]; +assign pyc_mux_1556 = (pyc_extract_1555 ? pyc_shli_1533 : pyc_comb_17); +assign pyc_add_1557 = (pyc_add_1554 + pyc_mux_1556); +assign pyc_extract_1558 = pyc_extract_1524[4]; +assign pyc_mux_1559 = (pyc_extract_1558 ? pyc_shli_1536 : pyc_comb_17); +assign pyc_add_1560 = (pyc_add_1557 + pyc_mux_1559); +assign pyc_mux_1561 = (pyc_extract_1558 ? pyc_shli_1539 : pyc_comb_17); +assign pyc_zext_1562 = {{5{1'b0}}, pyc_extract_1524}; +assign pyc_shli_1563 = (pyc_zext_1562 << 5); +assign pyc_mux_1564 = (pyc_extract_1541 ? pyc_shli_1563 : pyc_comb_17); +assign pyc_sub_1565 = (pyc_add_1560 - pyc_mux_1561); +assign pyc_sub_1566 = (pyc_sub_1565 - pyc_mux_1564); +assign pe_int_s1_p2c1_8__next = pyc_sub_1566; +assign pyc_extract_1567 = pe_int_s0_b1[49:45]; +assign pyc_zext_1568 = {{5{1'b0}}, pyc_extract_605}; +assign pyc_mux_1569 = (pyc_extract_308 ? pyc_zext_1568 : pyc_comb_17); +assign pyc_shli_1570 = (pyc_zext_1568 << 1); +assign pyc_mux_1571 = (pyc_extract_310 ? pyc_shli_1570 : pyc_comb_17); +assign pyc_add_1572 = (pyc_mux_1569 + pyc_mux_1571); +assign pyc_shli_1573 = (pyc_zext_1568 << 2); +assign pyc_mux_1574 = (pyc_extract_313 ? pyc_shli_1573 : pyc_comb_17); +assign pyc_add_1575 = (pyc_add_1572 + pyc_mux_1574); +assign pyc_shli_1576 = (pyc_zext_1568 << 3); +assign pyc_mux_1577 = (pyc_extract_316 ? pyc_shli_1576 : pyc_comb_17); +assign pyc_add_1578 = (pyc_add_1575 + pyc_mux_1577); +assign pyc_shli_1579 = (pyc_zext_1568 << 4); +assign pyc_mux_1580 = (pyc_extract_319 ? pyc_shli_1579 : pyc_comb_17); +assign pyc_add_1581 = (pyc_add_1578 + pyc_mux_1580); +assign pyc_shli_1582 = (pyc_zext_1568 << 5); +assign pyc_mux_1583 = (pyc_extract_319 ? pyc_shli_1582 : pyc_comb_17); +assign pyc_extract_1584 = pyc_extract_605[4]; +assign pyc_zext_1585 = {{5{1'b0}}, pyc_extract_202}; +assign pyc_shli_1586 = (pyc_zext_1585 << 5); +assign pyc_mux_1587 = (pyc_extract_1584 ? pyc_shli_1586 : pyc_comb_17); +assign pyc_sub_1588 = (pyc_add_1581 - pyc_mux_1583); +assign pyc_sub_1589 = (pyc_sub_1588 - pyc_mux_1587); +assign pe_int_s1_p2c0_9__next = pyc_sub_1589; +assign pyc_extract_1590 = pyc_extract_1567[0]; +assign pyc_mux_1591 = (pyc_extract_1590 ? pyc_zext_1568 : pyc_comb_17); +assign pyc_extract_1592 = pyc_extract_1567[1]; +assign pyc_mux_1593 = (pyc_extract_1592 ? pyc_shli_1570 : pyc_comb_17); +assign pyc_add_1594 = (pyc_mux_1591 + pyc_mux_1593); +assign pyc_extract_1595 = pyc_extract_1567[2]; +assign pyc_mux_1596 = (pyc_extract_1595 ? pyc_shli_1573 : pyc_comb_17); +assign pyc_add_1597 = (pyc_add_1594 + pyc_mux_1596); +assign pyc_extract_1598 = pyc_extract_1567[3]; +assign pyc_mux_1599 = (pyc_extract_1598 ? pyc_shli_1576 : pyc_comb_17); +assign pyc_add_1600 = (pyc_add_1597 + pyc_mux_1599); +assign pyc_extract_1601 = pyc_extract_1567[4]; +assign pyc_mux_1602 = (pyc_extract_1601 ? pyc_shli_1579 : pyc_comb_17); +assign pyc_add_1603 = (pyc_add_1600 + pyc_mux_1602); +assign pyc_mux_1604 = (pyc_extract_1601 ? pyc_shli_1582 : pyc_comb_17); +assign pyc_zext_1605 = {{5{1'b0}}, pyc_extract_1567}; +assign pyc_shli_1606 = (pyc_zext_1605 << 5); +assign pyc_mux_1607 = (pyc_extract_1584 ? pyc_shli_1606 : pyc_comb_17); +assign pyc_sub_1608 = (pyc_add_1603 - pyc_mux_1604); +assign pyc_sub_1609 = (pyc_sub_1608 - pyc_mux_1607); +assign pe_int_s1_p2c1_9__next = pyc_sub_1609; +assign pyc_extract_1610 = pe_int_s0_b1[54:50]; +assign pyc_zext_1611 = {{5{1'b0}}, pyc_extract_738}; +assign pyc_mux_1612 = (pyc_extract_446 ? pyc_zext_1611 : pyc_comb_17); +assign pyc_shli_1613 = (pyc_zext_1611 << 1); +assign pyc_mux_1614 = (pyc_extract_448 ? pyc_shli_1613 : pyc_comb_17); +assign pyc_add_1615 = (pyc_mux_1612 + pyc_mux_1614); +assign pyc_shli_1616 = (pyc_zext_1611 << 2); +assign pyc_mux_1617 = (pyc_extract_451 ? pyc_shli_1616 : pyc_comb_17); +assign pyc_add_1618 = (pyc_add_1615 + pyc_mux_1617); +assign pyc_shli_1619 = (pyc_zext_1611 << 3); +assign pyc_mux_1620 = (pyc_extract_454 ? pyc_shli_1619 : pyc_comb_17); +assign pyc_add_1621 = (pyc_add_1618 + pyc_mux_1620); +assign pyc_shli_1622 = (pyc_zext_1611 << 4); +assign pyc_mux_1623 = (pyc_extract_457 ? pyc_shli_1622 : pyc_comb_17); +assign pyc_add_1624 = (pyc_add_1621 + pyc_mux_1623); +assign pyc_shli_1625 = (pyc_zext_1611 << 5); +assign pyc_mux_1626 = (pyc_extract_457 ? pyc_shli_1625 : pyc_comb_17); +assign pyc_extract_1627 = pyc_extract_738[4]; +assign pyc_zext_1628 = {{5{1'b0}}, pyc_extract_340}; +assign pyc_shli_1629 = (pyc_zext_1628 << 5); +assign pyc_mux_1630 = (pyc_extract_1627 ? pyc_shli_1629 : pyc_comb_17); +assign pyc_sub_1631 = (pyc_add_1624 - pyc_mux_1626); +assign pyc_sub_1632 = (pyc_sub_1631 - pyc_mux_1630); +assign pe_int_s1_p2c0_10__next = pyc_sub_1632; +assign pyc_extract_1633 = pyc_extract_1610[0]; +assign pyc_mux_1634 = (pyc_extract_1633 ? pyc_zext_1611 : pyc_comb_17); +assign pyc_extract_1635 = pyc_extract_1610[1]; +assign pyc_mux_1636 = (pyc_extract_1635 ? pyc_shli_1613 : pyc_comb_17); +assign pyc_add_1637 = (pyc_mux_1634 + pyc_mux_1636); +assign pyc_extract_1638 = pyc_extract_1610[2]; +assign pyc_mux_1639 = (pyc_extract_1638 ? pyc_shli_1616 : pyc_comb_17); +assign pyc_add_1640 = (pyc_add_1637 + pyc_mux_1639); +assign pyc_extract_1641 = pyc_extract_1610[3]; +assign pyc_mux_1642 = (pyc_extract_1641 ? pyc_shli_1619 : pyc_comb_17); +assign pyc_add_1643 = (pyc_add_1640 + pyc_mux_1642); +assign pyc_extract_1644 = pyc_extract_1610[4]; +assign pyc_mux_1645 = (pyc_extract_1644 ? pyc_shli_1622 : pyc_comb_17); +assign pyc_add_1646 = (pyc_add_1643 + pyc_mux_1645); +assign pyc_mux_1647 = (pyc_extract_1644 ? pyc_shli_1625 : pyc_comb_17); +assign pyc_zext_1648 = {{5{1'b0}}, pyc_extract_1610}; +assign pyc_shli_1649 = (pyc_zext_1648 << 5); +assign pyc_mux_1650 = (pyc_extract_1627 ? pyc_shli_1649 : pyc_comb_17); +assign pyc_sub_1651 = (pyc_add_1646 - pyc_mux_1647); +assign pyc_sub_1652 = (pyc_sub_1651 - pyc_mux_1650); +assign pe_int_s1_p2c1_10__next = pyc_sub_1652; +assign pyc_extract_1653 = pe_int_s0_b1[59:55]; +assign pyc_zext_1654 = {{5{1'b0}}, pyc_extract_739}; +assign pyc_mux_1655 = (pyc_extract_584 ? pyc_zext_1654 : pyc_comb_17); +assign pyc_shli_1656 = (pyc_zext_1654 << 1); +assign pyc_mux_1657 = (pyc_extract_586 ? pyc_shli_1656 : pyc_comb_17); +assign pyc_add_1658 = (pyc_mux_1655 + pyc_mux_1657); +assign pyc_shli_1659 = (pyc_zext_1654 << 2); +assign pyc_mux_1660 = (pyc_extract_589 ? pyc_shli_1659 : pyc_comb_17); +assign pyc_add_1661 = (pyc_add_1658 + pyc_mux_1660); +assign pyc_shli_1662 = (pyc_zext_1654 << 3); +assign pyc_mux_1663 = (pyc_extract_592 ? pyc_shli_1662 : pyc_comb_17); +assign pyc_add_1664 = (pyc_add_1661 + pyc_mux_1663); +assign pyc_shli_1665 = (pyc_zext_1654 << 4); +assign pyc_mux_1666 = (pyc_extract_595 ? pyc_shli_1665 : pyc_comb_17); +assign pyc_add_1667 = (pyc_add_1664 + pyc_mux_1666); +assign pyc_shli_1668 = (pyc_zext_1654 << 5); +assign pyc_mux_1669 = (pyc_extract_595 ? pyc_shli_1668 : pyc_comb_17); +assign pyc_extract_1670 = pyc_extract_739[4]; +assign pyc_zext_1671 = {{5{1'b0}}, pyc_extract_478}; +assign pyc_shli_1672 = (pyc_zext_1671 << 5); +assign pyc_mux_1673 = (pyc_extract_1670 ? pyc_shli_1672 : pyc_comb_17); +assign pyc_sub_1674 = (pyc_add_1667 - pyc_mux_1669); +assign pyc_sub_1675 = (pyc_sub_1674 - pyc_mux_1673); +assign pe_int_s1_p2c0_11__next = pyc_sub_1675; +assign pyc_extract_1676 = pyc_extract_1653[0]; +assign pyc_mux_1677 = (pyc_extract_1676 ? pyc_zext_1654 : pyc_comb_17); +assign pyc_extract_1678 = pyc_extract_1653[1]; +assign pyc_mux_1679 = (pyc_extract_1678 ? pyc_shli_1656 : pyc_comb_17); +assign pyc_add_1680 = (pyc_mux_1677 + pyc_mux_1679); +assign pyc_extract_1681 = pyc_extract_1653[2]; +assign pyc_mux_1682 = (pyc_extract_1681 ? pyc_shli_1659 : pyc_comb_17); +assign pyc_add_1683 = (pyc_add_1680 + pyc_mux_1682); +assign pyc_extract_1684 = pyc_extract_1653[3]; +assign pyc_mux_1685 = (pyc_extract_1684 ? pyc_shli_1662 : pyc_comb_17); +assign pyc_add_1686 = (pyc_add_1683 + pyc_mux_1685); +assign pyc_extract_1687 = pyc_extract_1653[4]; +assign pyc_mux_1688 = (pyc_extract_1687 ? pyc_shli_1665 : pyc_comb_17); +assign pyc_add_1689 = (pyc_add_1686 + pyc_mux_1688); +assign pyc_mux_1690 = (pyc_extract_1687 ? pyc_shli_1668 : pyc_comb_17); +assign pyc_zext_1691 = {{5{1'b0}}, pyc_extract_1653}; +assign pyc_shli_1692 = (pyc_zext_1691 << 5); +assign pyc_mux_1693 = (pyc_extract_1670 ? pyc_shli_1692 : pyc_comb_17); +assign pyc_sub_1694 = (pyc_add_1689 - pyc_mux_1690); +assign pyc_sub_1695 = (pyc_sub_1694 - pyc_mux_1693); +assign pe_int_s1_p2c1_11__next = pyc_sub_1695; +assign pyc_extract_1696 = pe_int_s0_b1[64:60]; +assign pyc_zext_1697 = {{5{1'b0}}, pyc_extract_872}; +assign pyc_mux_1698 = (pyc_extract_718 ? pyc_zext_1697 : pyc_comb_17); +assign pyc_shli_1699 = (pyc_zext_1697 << 1); +assign pyc_mux_1700 = (pyc_extract_720 ? pyc_shli_1699 : pyc_comb_17); +assign pyc_add_1701 = (pyc_mux_1698 + pyc_mux_1700); +assign pyc_shli_1702 = (pyc_zext_1697 << 2); +assign pyc_mux_1703 = (pyc_extract_723 ? pyc_shli_1702 : pyc_comb_17); +assign pyc_add_1704 = (pyc_add_1701 + pyc_mux_1703); +assign pyc_shli_1705 = (pyc_zext_1697 << 3); +assign pyc_mux_1706 = (pyc_extract_726 ? pyc_shli_1705 : pyc_comb_17); +assign pyc_add_1707 = (pyc_add_1704 + pyc_mux_1706); +assign pyc_shli_1708 = (pyc_zext_1697 << 4); +assign pyc_mux_1709 = (pyc_extract_729 ? pyc_shli_1708 : pyc_comb_17); +assign pyc_add_1710 = (pyc_add_1707 + pyc_mux_1709); +assign pyc_shli_1711 = (pyc_zext_1697 << 5); +assign pyc_mux_1712 = (pyc_extract_729 ? pyc_shli_1711 : pyc_comb_17); +assign pyc_extract_1713 = pyc_extract_872[4]; +assign pyc_zext_1714 = {{5{1'b0}}, pyc_extract_612}; +assign pyc_shli_1715 = (pyc_zext_1714 << 5); +assign pyc_mux_1716 = (pyc_extract_1713 ? pyc_shli_1715 : pyc_comb_17); +assign pyc_sub_1717 = (pyc_add_1710 - pyc_mux_1712); +assign pyc_sub_1718 = (pyc_sub_1717 - pyc_mux_1716); +assign pe_int_s1_p2c0_12__next = pyc_sub_1718; +assign pyc_extract_1719 = pyc_extract_1696[0]; +assign pyc_mux_1720 = (pyc_extract_1719 ? pyc_zext_1697 : pyc_comb_17); +assign pyc_extract_1721 = pyc_extract_1696[1]; +assign pyc_mux_1722 = (pyc_extract_1721 ? pyc_shli_1699 : pyc_comb_17); +assign pyc_add_1723 = (pyc_mux_1720 + pyc_mux_1722); +assign pyc_extract_1724 = pyc_extract_1696[2]; +assign pyc_mux_1725 = (pyc_extract_1724 ? pyc_shli_1702 : pyc_comb_17); +assign pyc_add_1726 = (pyc_add_1723 + pyc_mux_1725); +assign pyc_extract_1727 = pyc_extract_1696[3]; +assign pyc_mux_1728 = (pyc_extract_1727 ? pyc_shli_1705 : pyc_comb_17); +assign pyc_add_1729 = (pyc_add_1726 + pyc_mux_1728); +assign pyc_extract_1730 = pyc_extract_1696[4]; +assign pyc_mux_1731 = (pyc_extract_1730 ? pyc_shli_1708 : pyc_comb_17); +assign pyc_add_1732 = (pyc_add_1729 + pyc_mux_1731); +assign pyc_mux_1733 = (pyc_extract_1730 ? pyc_shli_1711 : pyc_comb_17); +assign pyc_zext_1734 = {{5{1'b0}}, pyc_extract_1696}; +assign pyc_shli_1735 = (pyc_zext_1734 << 5); +assign pyc_mux_1736 = (pyc_extract_1713 ? pyc_shli_1735 : pyc_comb_17); +assign pyc_sub_1737 = (pyc_add_1732 - pyc_mux_1733); +assign pyc_sub_1738 = (pyc_sub_1737 - pyc_mux_1736); +assign pe_int_s1_p2c1_12__next = pyc_sub_1738; +assign pyc_extract_1739 = pe_int_s0_b1[69:65]; +assign pyc_zext_1740 = {{5{1'b0}}, pyc_extract_873}; +assign pyc_mux_1741 = (pyc_extract_852 ? pyc_zext_1740 : pyc_comb_17); +assign pyc_shli_1742 = (pyc_zext_1740 << 1); +assign pyc_mux_1743 = (pyc_extract_854 ? pyc_shli_1742 : pyc_comb_17); +assign pyc_add_1744 = (pyc_mux_1741 + pyc_mux_1743); +assign pyc_shli_1745 = (pyc_zext_1740 << 2); +assign pyc_mux_1746 = (pyc_extract_857 ? pyc_shli_1745 : pyc_comb_17); +assign pyc_add_1747 = (pyc_add_1744 + pyc_mux_1746); +assign pyc_shli_1748 = (pyc_zext_1740 << 3); +assign pyc_mux_1749 = (pyc_extract_860 ? pyc_shli_1748 : pyc_comb_17); +assign pyc_add_1750 = (pyc_add_1747 + pyc_mux_1749); +assign pyc_shli_1751 = (pyc_zext_1740 << 4); +assign pyc_mux_1752 = (pyc_extract_863 ? pyc_shli_1751 : pyc_comb_17); +assign pyc_add_1753 = (pyc_add_1750 + pyc_mux_1752); +assign pyc_shli_1754 = (pyc_zext_1740 << 5); +assign pyc_mux_1755 = (pyc_extract_863 ? pyc_shli_1754 : pyc_comb_17); +assign pyc_extract_1756 = pyc_extract_873[4]; +assign pyc_zext_1757 = {{5{1'b0}}, pyc_extract_746}; +assign pyc_shli_1758 = (pyc_zext_1757 << 5); +assign pyc_mux_1759 = (pyc_extract_1756 ? pyc_shli_1758 : pyc_comb_17); +assign pyc_sub_1760 = (pyc_add_1753 - pyc_mux_1755); +assign pyc_sub_1761 = (pyc_sub_1760 - pyc_mux_1759); +assign pe_int_s1_p2c0_13__next = pyc_sub_1761; +assign pyc_extract_1762 = pyc_extract_1739[0]; +assign pyc_mux_1763 = (pyc_extract_1762 ? pyc_zext_1740 : pyc_comb_17); +assign pyc_extract_1764 = pyc_extract_1739[1]; +assign pyc_mux_1765 = (pyc_extract_1764 ? pyc_shli_1742 : pyc_comb_17); +assign pyc_add_1766 = (pyc_mux_1763 + pyc_mux_1765); +assign pyc_extract_1767 = pyc_extract_1739[2]; +assign pyc_mux_1768 = (pyc_extract_1767 ? pyc_shli_1745 : pyc_comb_17); +assign pyc_add_1769 = (pyc_add_1766 + pyc_mux_1768); +assign pyc_extract_1770 = pyc_extract_1739[3]; +assign pyc_mux_1771 = (pyc_extract_1770 ? pyc_shli_1748 : pyc_comb_17); +assign pyc_add_1772 = (pyc_add_1769 + pyc_mux_1771); +assign pyc_extract_1773 = pyc_extract_1739[4]; +assign pyc_mux_1774 = (pyc_extract_1773 ? pyc_shli_1751 : pyc_comb_17); +assign pyc_add_1775 = (pyc_add_1772 + pyc_mux_1774); +assign pyc_mux_1776 = (pyc_extract_1773 ? pyc_shli_1754 : pyc_comb_17); +assign pyc_zext_1777 = {{5{1'b0}}, pyc_extract_1739}; +assign pyc_shli_1778 = (pyc_zext_1777 << 5); +assign pyc_mux_1779 = (pyc_extract_1756 ? pyc_shli_1778 : pyc_comb_17); +assign pyc_sub_1780 = (pyc_add_1775 - pyc_mux_1776); +assign pyc_sub_1781 = (pyc_sub_1780 - pyc_mux_1779); +assign pe_int_s1_p2c1_13__next = pyc_sub_1781; +assign pyc_extract_1782 = pe_int_s0_b1[74:70]; +assign pyc_zext_1783 = {{5{1'b0}}, pyc_extract_1006}; +assign pyc_mux_1784 = (pyc_extract_986 ? pyc_zext_1783 : pyc_comb_17); +assign pyc_shli_1785 = (pyc_zext_1783 << 1); +assign pyc_mux_1786 = (pyc_extract_988 ? pyc_shli_1785 : pyc_comb_17); +assign pyc_add_1787 = (pyc_mux_1784 + pyc_mux_1786); +assign pyc_shli_1788 = (pyc_zext_1783 << 2); +assign pyc_mux_1789 = (pyc_extract_991 ? pyc_shli_1788 : pyc_comb_17); +assign pyc_add_1790 = (pyc_add_1787 + pyc_mux_1789); +assign pyc_shli_1791 = (pyc_zext_1783 << 3); +assign pyc_mux_1792 = (pyc_extract_994 ? pyc_shli_1791 : pyc_comb_17); +assign pyc_add_1793 = (pyc_add_1790 + pyc_mux_1792); +assign pyc_shli_1794 = (pyc_zext_1783 << 4); +assign pyc_mux_1795 = (pyc_extract_997 ? pyc_shli_1794 : pyc_comb_17); +assign pyc_add_1796 = (pyc_add_1793 + pyc_mux_1795); +assign pyc_shli_1797 = (pyc_zext_1783 << 5); +assign pyc_mux_1798 = (pyc_extract_997 ? pyc_shli_1797 : pyc_comb_17); +assign pyc_extract_1799 = pyc_extract_1006[4]; +assign pyc_zext_1800 = {{5{1'b0}}, pyc_extract_880}; +assign pyc_shli_1801 = (pyc_zext_1800 << 5); +assign pyc_mux_1802 = (pyc_extract_1799 ? pyc_shli_1801 : pyc_comb_17); +assign pyc_sub_1803 = (pyc_add_1796 - pyc_mux_1798); +assign pyc_sub_1804 = (pyc_sub_1803 - pyc_mux_1802); +assign pe_int_s1_p2c0_14__next = pyc_sub_1804; +assign pyc_extract_1805 = pyc_extract_1782[0]; +assign pyc_mux_1806 = (pyc_extract_1805 ? pyc_zext_1783 : pyc_comb_17); +assign pyc_extract_1807 = pyc_extract_1782[1]; +assign pyc_mux_1808 = (pyc_extract_1807 ? pyc_shli_1785 : pyc_comb_17); +assign pyc_add_1809 = (pyc_mux_1806 + pyc_mux_1808); +assign pyc_extract_1810 = pyc_extract_1782[2]; +assign pyc_mux_1811 = (pyc_extract_1810 ? pyc_shli_1788 : pyc_comb_17); +assign pyc_add_1812 = (pyc_add_1809 + pyc_mux_1811); +assign pyc_extract_1813 = pyc_extract_1782[3]; +assign pyc_mux_1814 = (pyc_extract_1813 ? pyc_shli_1791 : pyc_comb_17); +assign pyc_add_1815 = (pyc_add_1812 + pyc_mux_1814); +assign pyc_extract_1816 = pyc_extract_1782[4]; +assign pyc_mux_1817 = (pyc_extract_1816 ? pyc_shli_1794 : pyc_comb_17); +assign pyc_add_1818 = (pyc_add_1815 + pyc_mux_1817); +assign pyc_mux_1819 = (pyc_extract_1816 ? pyc_shli_1797 : pyc_comb_17); +assign pyc_zext_1820 = {{5{1'b0}}, pyc_extract_1782}; +assign pyc_shli_1821 = (pyc_zext_1820 << 5); +assign pyc_mux_1822 = (pyc_extract_1799 ? pyc_shli_1821 : pyc_comb_17); +assign pyc_sub_1823 = (pyc_add_1818 - pyc_mux_1819); +assign pyc_sub_1824 = (pyc_sub_1823 - pyc_mux_1822); +assign pe_int_s1_p2c1_14__next = pyc_sub_1824; +assign pyc_extract_1825 = pe_int_s0_b1[79:75]; +assign pyc_zext_1826 = {{5{1'b0}}, pyc_extract_1007}; +assign pyc_mux_1827 = (pyc_extract_1120 ? pyc_zext_1826 : pyc_comb_17); +assign pyc_shli_1828 = (pyc_zext_1826 << 1); +assign pyc_mux_1829 = (pyc_extract_1122 ? pyc_shli_1828 : pyc_comb_17); +assign pyc_add_1830 = (pyc_mux_1827 + pyc_mux_1829); +assign pyc_shli_1831 = (pyc_zext_1826 << 2); +assign pyc_mux_1832 = (pyc_extract_1125 ? pyc_shli_1831 : pyc_comb_17); +assign pyc_add_1833 = (pyc_add_1830 + pyc_mux_1832); +assign pyc_shli_1834 = (pyc_zext_1826 << 3); +assign pyc_mux_1835 = (pyc_extract_1128 ? pyc_shli_1834 : pyc_comb_17); +assign pyc_add_1836 = (pyc_add_1833 + pyc_mux_1835); +assign pyc_shli_1837 = (pyc_zext_1826 << 4); +assign pyc_mux_1838 = (pyc_extract_1131 ? pyc_shli_1837 : pyc_comb_17); +assign pyc_add_1839 = (pyc_add_1836 + pyc_mux_1838); +assign pyc_shli_1840 = (pyc_zext_1826 << 5); +assign pyc_mux_1841 = (pyc_extract_1131 ? pyc_shli_1840 : pyc_comb_17); +assign pyc_extract_1842 = pyc_extract_1007[4]; +assign pyc_zext_1843 = {{5{1'b0}}, pyc_extract_1011}; +assign pyc_shli_1844 = (pyc_zext_1843 << 5); +assign pyc_mux_1845 = (pyc_extract_1842 ? pyc_shli_1844 : pyc_comb_17); +assign pyc_sub_1846 = (pyc_add_1839 - pyc_mux_1841); +assign pyc_sub_1847 = (pyc_sub_1846 - pyc_mux_1845); +assign pe_int_s1_p2c0_15__next = pyc_sub_1847; +assign pyc_extract_1848 = pyc_extract_1825[0]; +assign pyc_mux_1849 = (pyc_extract_1848 ? pyc_zext_1826 : pyc_comb_17); +assign pyc_extract_1850 = pyc_extract_1825[1]; +assign pyc_mux_1851 = (pyc_extract_1850 ? pyc_shli_1828 : pyc_comb_17); +assign pyc_add_1852 = (pyc_mux_1849 + pyc_mux_1851); +assign pyc_extract_1853 = pyc_extract_1825[2]; +assign pyc_mux_1854 = (pyc_extract_1853 ? pyc_shli_1831 : pyc_comb_17); +assign pyc_add_1855 = (pyc_add_1852 + pyc_mux_1854); +assign pyc_extract_1856 = pyc_extract_1825[3]; +assign pyc_mux_1857 = (pyc_extract_1856 ? pyc_shli_1834 : pyc_comb_17); +assign pyc_add_1858 = (pyc_add_1855 + pyc_mux_1857); +assign pyc_extract_1859 = pyc_extract_1825[4]; +assign pyc_mux_1860 = (pyc_extract_1859 ? pyc_shli_1837 : pyc_comb_17); +assign pyc_add_1861 = (pyc_add_1858 + pyc_mux_1860); +assign pyc_mux_1862 = (pyc_extract_1859 ? pyc_shli_1840 : pyc_comb_17); +assign pyc_zext_1863 = {{5{1'b0}}, pyc_extract_1825}; +assign pyc_shli_1864 = (pyc_zext_1863 << 5); +assign pyc_mux_1865 = (pyc_extract_1842 ? pyc_shli_1864 : pyc_comb_17); +assign pyc_sub_1866 = (pyc_add_1861 - pyc_mux_1862); +assign pyc_sub_1867 = (pyc_sub_1866 - pyc_mux_1865); +assign pe_int_s1_p2c1_15__next = pyc_sub_1867; +assign pyc_comb_1868 = pe_int_s1_e1_b1__next; +assign pyc_comb_1869 = pe_int_s1_p2a_0__next; +assign pyc_comb_1870 = pe_int_s1_p2b0_0__next; +assign pyc_comb_1871 = pe_int_s1_p2b1_0__next; +assign pyc_comb_1872 = pe_int_s1_p2d0_0__next; +assign pyc_comb_1873 = pe_int_s1_p2d1_0__next; +assign pyc_comb_1874 = pe_int_s1_p2a_1__next; +assign pyc_comb_1875 = pe_int_s1_p2b0_1__next; +assign pyc_comb_1876 = pe_int_s1_p2b1_1__next; +assign pyc_comb_1877 = pe_int_s1_p2d0_1__next; +assign pyc_comb_1878 = pe_int_s1_p2d1_1__next; +assign pyc_comb_1879 = pe_int_s1_p2a_2__next; +assign pyc_comb_1880 = pe_int_s1_p2b0_2__next; +assign pyc_comb_1881 = pe_int_s1_p2b1_2__next; +assign pyc_comb_1882 = pe_int_s1_p2d0_2__next; +assign pyc_comb_1883 = pe_int_s1_p2d1_2__next; +assign pyc_comb_1884 = pe_int_s1_p2a_3__next; +assign pyc_comb_1885 = pe_int_s1_p2b0_3__next; +assign pyc_comb_1886 = pe_int_s1_p2b1_3__next; +assign pyc_comb_1887 = pe_int_s1_p2d0_3__next; +assign pyc_comb_1888 = pe_int_s1_p2d1_3__next; +assign pyc_comb_1889 = pe_int_s1_p2a_4__next; +assign pyc_comb_1890 = pe_int_s1_p2b0_4__next; +assign pyc_comb_1891 = pe_int_s1_p2b1_4__next; +assign pyc_comb_1892 = pe_int_s1_p2d0_4__next; +assign pyc_comb_1893 = pe_int_s1_p2d1_4__next; +assign pyc_comb_1894 = pe_int_s1_p2a_5__next; +assign pyc_comb_1895 = pe_int_s1_p2b0_5__next; +assign pyc_comb_1896 = pe_int_s1_p2b1_5__next; +assign pyc_comb_1897 = pe_int_s1_p2d0_5__next; +assign pyc_comb_1898 = pe_int_s1_p2d1_5__next; +assign pyc_comb_1899 = pe_int_s1_p2a_6__next; +assign pyc_comb_1900 = pe_int_s1_p2b0_6__next; +assign pyc_comb_1901 = pe_int_s1_p2b1_6__next; +assign pyc_comb_1902 = pe_int_s1_p2d0_6__next; +assign pyc_comb_1903 = pe_int_s1_p2d1_6__next; +assign pyc_comb_1904 = pe_int_s1_p2a_7__next; +assign pyc_comb_1905 = pe_int_s1_p2b0_7__next; +assign pyc_comb_1906 = pe_int_s1_p2b1_7__next; +assign pyc_comb_1907 = pe_int_s1_p2d0_7__next; +assign pyc_comb_1908 = pe_int_s1_p2d1_7__next; +assign pyc_comb_1909 = pe_int_s1_p2c0_0__next; +assign pyc_comb_1910 = pe_int_s1_p2c1_0__next; +assign pyc_comb_1911 = pe_int_s1_p2c0_1__next; +assign pyc_comb_1912 = pe_int_s1_p2c1_1__next; +assign pyc_comb_1913 = pe_int_s1_p2c0_2__next; +assign pyc_comb_1914 = pe_int_s1_p2c1_2__next; +assign pyc_comb_1915 = pe_int_s1_p2c0_3__next; +assign pyc_comb_1916 = pe_int_s1_p2c1_3__next; +assign pyc_comb_1917 = pe_int_s1_p2c0_4__next; +assign pyc_comb_1918 = pe_int_s1_p2c1_4__next; +assign pyc_comb_1919 = pe_int_s1_p2c0_5__next; +assign pyc_comb_1920 = pe_int_s1_p2c1_5__next; +assign pyc_comb_1921 = pe_int_s1_p2c0_6__next; +assign pyc_comb_1922 = pe_int_s1_p2c1_6__next; +assign pyc_comb_1923 = pe_int_s1_p2c0_7__next; +assign pyc_comb_1924 = pe_int_s1_p2c1_7__next; +assign pyc_comb_1925 = pe_int_s1_p2c0_8__next; +assign pyc_comb_1926 = pe_int_s1_p2c1_8__next; +assign pyc_comb_1927 = pe_int_s1_p2c0_9__next; +assign pyc_comb_1928 = pe_int_s1_p2c1_9__next; +assign pyc_comb_1929 = pe_int_s1_p2c0_10__next; +assign pyc_comb_1930 = pe_int_s1_p2c1_10__next; +assign pyc_comb_1931 = pe_int_s1_p2c0_11__next; +assign pyc_comb_1932 = pe_int_s1_p2c1_11__next; +assign pyc_comb_1933 = pe_int_s1_p2c0_12__next; +assign pyc_comb_1934 = pe_int_s1_p2c1_12__next; +assign pyc_comb_1935 = pe_int_s1_p2c0_13__next; +assign pyc_comb_1936 = pe_int_s1_p2c1_13__next; +assign pyc_comb_1937 = pe_int_s1_p2c0_14__next; +assign pyc_comb_1938 = pe_int_s1_p2c1_14__next; +assign pyc_comb_1939 = pe_int_s1_p2c0_15__next; +assign pyc_comb_1940 = pe_int_s1_p2c1_15__next; +assign pe_int_s1_vld = pyc_reg_1941; assign pe_int_s2_vld__next = pe_int_s1_vld; -assign pyc_comb_424 = pe_int_s2_vld__next; -assign pe_int_s1_is_2a = pyc_reg_425; +assign pyc_comb_1942 = pe_int_s2_vld__next; +assign pe_int_s1_is_2a = pyc_reg_1943; assign pe_int_s2_is_2a__next = pe_int_s1_is_2a; -assign pyc_comb_426 = pe_int_s2_is_2a__next; -assign pe_int_s1_is_2b = pyc_reg_427; +assign pyc_comb_1944 = pe_int_s2_is_2a__next; +assign pe_int_s1_is_2b = pyc_reg_1945; assign pe_int_s2_is_2b__next = pe_int_s1_is_2b; -assign pyc_comb_428 = pe_int_s2_is_2b__next; -assign pe_int_s0_e1_b0 = pyc_reg_42; -assign pe_int_s1_e1_b0__next = pe_int_s0_e1_b0; -assign pyc_comb_43 = pe_int_s1_e1_b0__next; -assign pe_int_s1_is_2c = pyc_reg_429; +assign pyc_comb_1946 = pe_int_s2_is_2b__next; +assign pe_int_s1_is_2c = pyc_reg_1947; assign pe_int_s2_is_2c__next = pe_int_s1_is_2c; -assign pyc_comb_430 = pe_int_s2_is_2c__next; -assign pe_int_s1_e1_a = pyc_reg_431; +assign pyc_comb_1948 = pe_int_s2_is_2c__next; +assign pe_int_s1_e1_a = pyc_reg_1949; assign pe_int_s2_e1_a__next = pe_int_s1_e1_a; -assign pyc_comb_432 = pe_int_s2_e1_a__next; -assign pe_int_s1_e1_b0 = pyc_reg_433; +assign pyc_comb_1950 = pe_int_s2_e1_a__next; +assign pe_int_s1_e1_b0 = pyc_reg_1951; assign pe_int_s2_e1_b0__next = pe_int_s1_e1_b0; -assign pyc_comb_434 = pe_int_s2_e1_b0__next; -assign pe_int_s1_e1_b1 = pyc_reg_435; +assign pyc_comb_1952 = pe_int_s2_e1_b0__next; +assign pe_int_s1_e1_b1 = pyc_reg_1953; assign pe_int_s2_e1_b1__next = pe_int_s1_e1_b1; -assign pyc_comb_436 = pe_int_s2_e1_b1__next; -assign pe_int_s2_vld = pyc_reg_518; +assign pyc_comb_1954 = pe_int_s2_e1_b1__next; +assign pe_int_s1_p2c1_15 = pyc_reg_2026; +assign pyc_sext_2027 = {{3{pe_int_s1_p2a_0[15]}}, pe_int_s1_p2a_0}; +assign pyc_sext_2028 = {{3{pe_int_s1_p2a_1[15]}}, pe_int_s1_p2a_1}; +assign pyc_sext_2029 = {{3{pe_int_s1_p2a_2[15]}}, pe_int_s1_p2a_2}; +assign pyc_sext_2030 = {{3{pe_int_s1_p2a_3[15]}}, pe_int_s1_p2a_3}; +assign pyc_sext_2031 = {{3{pe_int_s1_p2a_4[15]}}, pe_int_s1_p2a_4}; +assign pyc_sext_2032 = {{3{pe_int_s1_p2a_5[15]}}, pe_int_s1_p2a_5}; +assign pyc_sext_2033 = {{3{pe_int_s1_p2a_6[15]}}, pe_int_s1_p2a_6}; +assign pyc_sext_2034 = {{3{pe_int_s1_p2a_7[15]}}, pe_int_s1_p2a_7}; +assign pyc_comb_2035 = pe_int_s1_p2c1_15; +assign pyc_comb_2036 = pyc_sext_2027; +assign pyc_comb_2037 = pyc_sext_2028; +assign pyc_comb_2038 = pyc_sext_2029; +assign pyc_comb_2039 = pyc_sext_2030; +assign pyc_comb_2040 = pyc_sext_2031; +assign pyc_comb_2041 = pyc_sext_2032; +assign pyc_comb_2042 = pyc_sext_2033; +assign pyc_comb_2043 = pyc_sext_2034; +assign pe_int_s2_s2a__next = pyc_instance_2044; +assign pyc_sext_2045 = {{7{pe_int_s1_p2b0_0[11]}}, pe_int_s1_p2b0_0}; +assign pyc_sext_2046 = {{7{pe_int_s1_p2b0_1[11]}}, pe_int_s1_p2b0_1}; +assign pyc_sext_2047 = {{7{pe_int_s1_p2b0_2[11]}}, pe_int_s1_p2b0_2}; +assign pyc_sext_2048 = {{7{pe_int_s1_p2b0_3[11]}}, pe_int_s1_p2b0_3}; +assign pyc_sext_2049 = {{7{pe_int_s1_p2b0_4[11]}}, pe_int_s1_p2b0_4}; +assign pyc_sext_2050 = {{7{pe_int_s1_p2b0_5[11]}}, pe_int_s1_p2b0_5}; +assign pyc_sext_2051 = {{7{pe_int_s1_p2b0_6[11]}}, pe_int_s1_p2b0_6}; +assign pyc_sext_2052 = {{7{pe_int_s1_p2b0_7[11]}}, pe_int_s1_p2b0_7}; +assign pyc_comb_2053 = pe_int_s2_s2a__next; +assign pyc_comb_2054 = pyc_sext_2045; +assign pyc_comb_2055 = pyc_sext_2046; +assign pyc_comb_2056 = pyc_sext_2047; +assign pyc_comb_2057 = pyc_sext_2048; +assign pyc_comb_2058 = pyc_sext_2049; +assign pyc_comb_2059 = pyc_sext_2050; +assign pyc_comb_2060 = pyc_sext_2051; +assign pyc_comb_2061 = pyc_sext_2052; +assign pe_int_s2_s2b0__next = pyc_instance_2062; +assign pyc_sext_2063 = {{4{pe_int_s1_p2b1_0[11]}}, pe_int_s1_p2b1_0}; +assign pyc_sext_2064 = {{4{pe_int_s1_p2b1_1[11]}}, pe_int_s1_p2b1_1}; +assign pyc_sext_2065 = {{4{pe_int_s1_p2b1_2[11]}}, pe_int_s1_p2b1_2}; +assign pyc_sext_2066 = {{4{pe_int_s1_p2b1_3[11]}}, pe_int_s1_p2b1_3}; +assign pyc_sext_2067 = {{4{pe_int_s1_p2b1_4[11]}}, pe_int_s1_p2b1_4}; +assign pyc_sext_2068 = {{4{pe_int_s1_p2b1_5[11]}}, pe_int_s1_p2b1_5}; +assign pyc_sext_2069 = {{4{pe_int_s1_p2b1_6[11]}}, pe_int_s1_p2b1_6}; +assign pyc_sext_2070 = {{4{pe_int_s1_p2b1_7[11]}}, pe_int_s1_p2b1_7}; +assign pyc_comb_2071 = pe_int_s2_s2b0__next; +assign pyc_comb_2072 = pyc_sext_2063; +assign pyc_comb_2073 = pyc_sext_2064; +assign pyc_comb_2074 = pyc_sext_2065; +assign pyc_comb_2075 = pyc_sext_2066; +assign pyc_comb_2076 = pyc_sext_2067; +assign pyc_comb_2077 = pyc_sext_2068; +assign pyc_comb_2078 = pyc_sext_2069; +assign pyc_comb_2079 = pyc_sext_2070; +assign pe_int_s2_s2b1__next = pyc_instance_2080; +assign pyc_sext_2081 = {{6{pe_int_s1_p2d0_0[12]}}, pe_int_s1_p2d0_0}; +assign pyc_sext_2082 = {{6{pe_int_s1_p2d0_1[12]}}, pe_int_s1_p2d0_1}; +assign pyc_sext_2083 = {{6{pe_int_s1_p2d0_2[12]}}, pe_int_s1_p2d0_2}; +assign pyc_sext_2084 = {{6{pe_int_s1_p2d0_3[12]}}, pe_int_s1_p2d0_3}; +assign pyc_sext_2085 = {{6{pe_int_s1_p2d0_4[12]}}, pe_int_s1_p2d0_4}; +assign pyc_sext_2086 = {{6{pe_int_s1_p2d0_5[12]}}, pe_int_s1_p2d0_5}; +assign pyc_sext_2087 = {{6{pe_int_s1_p2d0_6[12]}}, pe_int_s1_p2d0_6}; +assign pyc_sext_2088 = {{6{pe_int_s1_p2d0_7[12]}}, pe_int_s1_p2d0_7}; +assign pyc_comb_2089 = pe_int_s2_s2b1__next; +assign pyc_comb_2090 = pyc_sext_2081; +assign pyc_comb_2091 = pyc_sext_2082; +assign pyc_comb_2092 = pyc_sext_2083; +assign pyc_comb_2093 = pyc_sext_2084; +assign pyc_comb_2094 = pyc_sext_2085; +assign pyc_comb_2095 = pyc_sext_2086; +assign pyc_comb_2096 = pyc_sext_2087; +assign pyc_comb_2097 = pyc_sext_2088; +assign pe_int_s2_s2d0__next = pyc_instance_2098; +assign pyc_sext_2099 = {{3{pe_int_s1_p2d1_0[12]}}, pe_int_s1_p2d1_0}; +assign pyc_sext_2100 = {{3{pe_int_s1_p2d1_1[12]}}, pe_int_s1_p2d1_1}; +assign pyc_sext_2101 = {{3{pe_int_s1_p2d1_2[12]}}, pe_int_s1_p2d1_2}; +assign pyc_sext_2102 = {{3{pe_int_s1_p2d1_3[12]}}, pe_int_s1_p2d1_3}; +assign pyc_sext_2103 = {{3{pe_int_s1_p2d1_4[12]}}, pe_int_s1_p2d1_4}; +assign pyc_sext_2104 = {{3{pe_int_s1_p2d1_5[12]}}, pe_int_s1_p2d1_5}; +assign pyc_sext_2105 = {{3{pe_int_s1_p2d1_6[12]}}, pe_int_s1_p2d1_6}; +assign pyc_sext_2106 = {{3{pe_int_s1_p2d1_7[12]}}, pe_int_s1_p2d1_7}; +assign pyc_comb_2107 = pe_int_s2_s2d0__next; +assign pyc_comb_2108 = pyc_sext_2099; +assign pyc_comb_2109 = pyc_sext_2100; +assign pyc_comb_2110 = pyc_sext_2101; +assign pyc_comb_2111 = pyc_sext_2102; +assign pyc_comb_2112 = pyc_sext_2103; +assign pyc_comb_2113 = pyc_sext_2104; +assign pyc_comb_2114 = pyc_sext_2105; +assign pyc_comb_2115 = pyc_sext_2106; +assign pe_int_s2_s2d1__next = pyc_instance_2116; +assign pyc_sext_2117 = {{9{pe_int_s1_p2c0_0[9]}}, pe_int_s1_p2c0_0}; +assign pyc_sext_2118 = {{9{pe_int_s1_p2c0_1[9]}}, pe_int_s1_p2c0_1}; +assign pyc_sext_2119 = {{9{pe_int_s1_p2c0_2[9]}}, pe_int_s1_p2c0_2}; +assign pyc_sext_2120 = {{9{pe_int_s1_p2c0_3[9]}}, pe_int_s1_p2c0_3}; +assign pyc_sext_2121 = {{9{pe_int_s1_p2c0_4[9]}}, pe_int_s1_p2c0_4}; +assign pyc_sext_2122 = {{9{pe_int_s1_p2c0_5[9]}}, pe_int_s1_p2c0_5}; +assign pyc_sext_2123 = {{9{pe_int_s1_p2c0_6[9]}}, pe_int_s1_p2c0_6}; +assign pyc_sext_2124 = {{9{pe_int_s1_p2c0_7[9]}}, pe_int_s1_p2c0_7}; +assign pyc_comb_2125 = pe_int_s2_s2d1__next; +assign pyc_comb_2126 = pyc_sext_2117; +assign pyc_comb_2127 = pyc_sext_2118; +assign pyc_comb_2128 = pyc_sext_2119; +assign pyc_comb_2129 = pyc_sext_2120; +assign pyc_comb_2130 = pyc_sext_2121; +assign pyc_comb_2131 = pyc_sext_2122; +assign pyc_comb_2132 = pyc_sext_2123; +assign pyc_comb_2133 = pyc_sext_2124; +assign pe_int_s2_s2c0_lo__next = pyc_instance_2134; +assign pyc_sext_2135 = {{9{pe_int_s1_p2c0_8[9]}}, pe_int_s1_p2c0_8}; +assign pyc_sext_2136 = {{9{pe_int_s1_p2c0_9[9]}}, pe_int_s1_p2c0_9}; +assign pyc_sext_2137 = {{9{pe_int_s1_p2c0_10[9]}}, pe_int_s1_p2c0_10}; +assign pyc_sext_2138 = {{9{pe_int_s1_p2c0_11[9]}}, pe_int_s1_p2c0_11}; +assign pyc_sext_2139 = {{9{pe_int_s1_p2c0_12[9]}}, pe_int_s1_p2c0_12}; +assign pyc_sext_2140 = {{9{pe_int_s1_p2c0_13[9]}}, pe_int_s1_p2c0_13}; +assign pyc_sext_2141 = {{9{pe_int_s1_p2c0_14[9]}}, pe_int_s1_p2c0_14}; +assign pyc_sext_2142 = {{9{pe_int_s1_p2c0_15[9]}}, pe_int_s1_p2c0_15}; +assign pyc_comb_2143 = pe_int_s2_s2c0_lo__next; +assign pyc_comb_2144 = pyc_sext_2135; +assign pyc_comb_2145 = pyc_sext_2136; +assign pyc_comb_2146 = pyc_sext_2137; +assign pyc_comb_2147 = pyc_sext_2138; +assign pyc_comb_2148 = pyc_sext_2139; +assign pyc_comb_2149 = pyc_sext_2140; +assign pyc_comb_2150 = pyc_sext_2141; +assign pyc_comb_2151 = pyc_sext_2142; +assign pe_int_s2_s2c0_hi__next = pyc_instance_2152; +assign pyc_sext_2153 = {{6{pe_int_s1_p2c1_0[9]}}, pe_int_s1_p2c1_0}; +assign pyc_sext_2154 = {{6{pe_int_s1_p2c1_1[9]}}, pe_int_s1_p2c1_1}; +assign pyc_sext_2155 = {{6{pe_int_s1_p2c1_2[9]}}, pe_int_s1_p2c1_2}; +assign pyc_sext_2156 = {{6{pe_int_s1_p2c1_3[9]}}, pe_int_s1_p2c1_3}; +assign pyc_sext_2157 = {{6{pe_int_s1_p2c1_4[9]}}, pe_int_s1_p2c1_4}; +assign pyc_sext_2158 = {{6{pe_int_s1_p2c1_5[9]}}, pe_int_s1_p2c1_5}; +assign pyc_sext_2159 = {{6{pe_int_s1_p2c1_6[9]}}, pe_int_s1_p2c1_6}; +assign pyc_sext_2160 = {{6{pe_int_s1_p2c1_7[9]}}, pe_int_s1_p2c1_7}; +assign pyc_comb_2161 = pe_int_s2_s2c0_hi__next; +assign pyc_comb_2162 = pyc_sext_2153; +assign pyc_comb_2163 = pyc_sext_2154; +assign pyc_comb_2164 = pyc_sext_2155; +assign pyc_comb_2165 = pyc_sext_2156; +assign pyc_comb_2166 = pyc_sext_2157; +assign pyc_comb_2167 = pyc_sext_2158; +assign pyc_comb_2168 = pyc_sext_2159; +assign pyc_comb_2169 = pyc_sext_2160; +assign pe_int_s2_s2c1_lo__next = pyc_instance_2170; +assign pyc_sext_2171 = {{6{pe_int_s1_p2c1_8[9]}}, pe_int_s1_p2c1_8}; +assign pyc_sext_2172 = {{6{pe_int_s1_p2c1_9[9]}}, pe_int_s1_p2c1_9}; +assign pyc_sext_2173 = {{6{pe_int_s1_p2c1_10[9]}}, pe_int_s1_p2c1_10}; +assign pyc_sext_2174 = {{6{pe_int_s1_p2c1_11[9]}}, pe_int_s1_p2c1_11}; +assign pyc_sext_2175 = {{6{pe_int_s1_p2c1_12[9]}}, pe_int_s1_p2c1_12}; +assign pyc_sext_2176 = {{6{pe_int_s1_p2c1_13[9]}}, pe_int_s1_p2c1_13}; +assign pyc_sext_2177 = {{6{pe_int_s1_p2c1_14[9]}}, pe_int_s1_p2c1_14}; +assign pyc_sext_2178 = {{6{pyc_comb_2035[9]}}, pyc_comb_2035}; +assign pyc_comb_2179 = pe_int_s2_s2c1_lo__next; +assign pyc_comb_2180 = pyc_sext_2171; +assign pyc_comb_2181 = pyc_sext_2172; +assign pyc_comb_2182 = pyc_sext_2173; +assign pyc_comb_2183 = pyc_sext_2174; +assign pyc_comb_2184 = pyc_sext_2175; +assign pyc_comb_2185 = pyc_sext_2176; +assign pyc_comb_2186 = pyc_sext_2177; +assign pyc_comb_2187 = pyc_sext_2178; +assign pe_int_s2_vld = pyc_reg_2189; assign pe_int_out_vld__next = pe_int_s2_vld; -assign pyc_concat_519 = {pyc_comb_430, pyc_comb_428, pyc_comb_426}; -assign pyc_concat_520 = {pyc_comb_18, pyc_comb_18, pyc_comb_18}; -assign pyc_comb_521 = pe_int_s2_vld; -assign pyc_comb_522 = pe_int_out_vld__next; -assign pyc_comb_523 = pyc_concat_519; -assign pyc_comb_524 = pyc_concat_520; -assign pyc_extract_526 = pyc_reg_525[0]; -assign pyc_extract_527 = pyc_reg_525[1]; -assign pyc_extract_528 = pyc_reg_525[2]; -assign pe_int_s2_is_2a = pyc_extract_526; -assign pe_int_s2_is_2b = pyc_extract_527; -assign pe_int_s2_is_2c = pyc_extract_528; -assign pyc_comb_529 = pe_int_s2_is_2a; -assign pyc_comb_530 = pe_int_s2_is_2b; -assign pyc_comb_531 = pe_int_s2_is_2c; -assign pe_int_s2_s2c1_hi = pyc_reg_543; -assign pyc_extract_544 = pe_int_s2_e1_a[0]; -assign pyc_zext_545 = {{1{1'b0}}, pyc_extract_544}; -assign pyc_extract_546 = pe_int_s2_e1_b0[0]; -assign pyc_zext_547 = {{1{1'b0}}, pyc_extract_546}; -assign pyc_add_548 = (pyc_zext_545 + pyc_zext_547); -assign pyc_extract_549 = pe_int_s2_e1_a[1]; -assign pyc_zext_550 = {{1{1'b0}}, pyc_extract_549}; -assign pyc_extract_551 = pe_int_s2_e1_b0[1]; -assign pyc_zext_552 = {{1{1'b0}}, pyc_extract_551}; -assign pyc_add_553 = (pyc_zext_550 + pyc_zext_552); -assign pyc_eq_554 = (pyc_add_548 == pyc_comb_15); -assign pyc_eq_555 = (pyc_add_548 == pyc_comb_12); -assign pyc_shli_556 = (pe_int_s2_s2c0_lo << 1); -assign pyc_shli_557 = (pe_int_s2_s2c0_lo << 2); -assign pyc_mux_558 = (pyc_eq_555 ? pyc_shli_556 : pyc_shli_557); -assign pyc_mux_559 = (pyc_eq_554 ? pe_int_s2_s2c0_lo : pyc_mux_558); -assign pyc_eq_560 = (pyc_add_553 == pyc_comb_15); -assign pyc_eq_561 = (pyc_add_553 == pyc_comb_12); -assign pyc_shli_562 = (pe_int_s2_s2c0_hi << 1); -assign pyc_shli_563 = (pe_int_s2_s2c0_hi << 2); -assign pyc_mux_564 = (pyc_eq_561 ? pyc_shli_562 : pyc_shli_563); -assign pyc_mux_565 = (pyc_eq_560 ? pe_int_s2_s2c0_hi : pyc_mux_564); -assign pyc_add_566 = (pyc_mux_559 + pyc_mux_565); -assign pyc_extract_567 = pe_int_s2_e1_b1[0]; -assign pyc_zext_568 = {{1{1'b0}}, pyc_extract_567}; -assign pyc_add_569 = (pyc_zext_545 + pyc_zext_568); -assign pyc_extract_570 = pe_int_s2_e1_b1[1]; -assign pyc_zext_571 = {{1{1'b0}}, pyc_extract_570}; -assign pyc_add_572 = (pyc_zext_550 + pyc_zext_571); -assign pyc_eq_573 = (pyc_add_569 == pyc_comb_15); -assign pyc_eq_574 = (pyc_add_569 == pyc_comb_12); -assign pyc_shli_575 = (pe_int_s2_s2c1_lo << 1); -assign pyc_shli_576 = (pe_int_s2_s2c1_lo << 2); -assign pyc_mux_577 = (pyc_eq_574 ? pyc_shli_575 : pyc_shli_576); -assign pyc_mux_578 = (pyc_eq_573 ? pe_int_s2_s2c1_lo : pyc_mux_577); -assign pyc_eq_579 = (pyc_add_572 == pyc_comb_15); -assign pyc_eq_580 = (pyc_add_572 == pyc_comb_12); -assign pyc_shli_581 = (pe_int_s2_s2c1_hi << 1); -assign pyc_shli_582 = (pe_int_s2_s2c1_hi << 2); -assign pyc_mux_583 = (pyc_eq_580 ? pyc_shli_581 : pyc_shli_582); -assign pyc_mux_584 = (pyc_eq_579 ? pe_int_s2_s2c1_hi : pyc_mux_583); -assign pyc_add_585 = (pyc_mux_578 + pyc_mux_584); -assign pyc_mux_586 = (pyc_comb_531 ? pyc_add_566 : pe_int_s2_s2d0); -assign pyc_mux_587 = (pyc_comb_530 ? pe_int_s2_s2b0 : pyc_mux_586); -assign pyc_mux_588 = (pyc_comb_529 ? pe_int_s2_s2a : pyc_mux_587); -assign pe_int_out0__next = pyc_mux_588; -assign pyc_mux_589 = (pyc_comb_531 ? pyc_add_585 : pe_int_s2_s2d1); -assign pyc_mux_590 = (pyc_comb_530 ? pe_int_s2_s2b1 : pyc_mux_589); -assign pyc_comb_591 = pe_int_out0__next; -assign pyc_comb_592 = pyc_mux_590; -assign pe_int_out1 = pyc_reg_593; -assign pyc_mux_594 = (pyc_comb_529 ? pe_int_out1 : pyc_comb_592); -assign pyc_mux_595 = (pyc_comb_521 ? pyc_mux_594 : pe_int_out1); -assign pyc_comb_596 = pe_int_out1; -assign pyc_comb_597 = pyc_mux_595; -assign pe_int_out1__next = pyc_comb_597; +assign pyc_concat_2190 = {pyc_comb_1948, pyc_comb_1946, pyc_comb_1944}; +assign pyc_concat_2191 = {pyc_comb_24, pyc_comb_24, pyc_comb_24}; +assign pyc_comb_2192 = pe_int_s2_vld; +assign pyc_comb_2193 = pe_int_out_vld__next; +assign pyc_comb_2194 = pyc_concat_2190; +assign pyc_comb_2195 = pyc_concat_2191; +assign pyc_extract_2197 = pyc_reg_2196[0]; +assign pyc_extract_2198 = pyc_reg_2196[1]; +assign pyc_extract_2199 = pyc_reg_2196[2]; +assign pe_int_s2_is_2a = pyc_extract_2197; +assign pe_int_s2_is_2b = pyc_extract_2198; +assign pe_int_s2_is_2c = pyc_extract_2199; +assign pyc_comb_2200 = pe_int_s2_is_2a; +assign pyc_comb_2201 = pe_int_s2_is_2b; +assign pyc_comb_2202 = pe_int_s2_is_2c; +assign pe_int_s2_s2c1_hi = pyc_reg_2214; +assign pyc_extract_2215 = pe_int_s2_e1_a[0]; +assign pyc_zext_2216 = {{1{1'b0}}, pyc_extract_2215}; +assign pyc_extract_2217 = pe_int_s2_e1_b0[0]; +assign pyc_zext_2218 = {{1{1'b0}}, pyc_extract_2217}; +assign pyc_add_2219 = (pyc_zext_2216 + pyc_zext_2218); +assign pyc_extract_2220 = pe_int_s2_e1_a[1]; +assign pyc_zext_2221 = {{1{1'b0}}, pyc_extract_2220}; +assign pyc_extract_2222 = pe_int_s2_e1_b0[1]; +assign pyc_zext_2223 = {{1{1'b0}}, pyc_extract_2222}; +assign pyc_add_2224 = (pyc_zext_2221 + pyc_zext_2223); +assign pyc_eq_2225 = (pyc_add_2219 == pyc_comb_21); +assign pyc_eq_2226 = (pyc_add_2219 == pyc_comb_15); +assign pyc_shli_2227 = (pe_int_s2_s2c0_lo << 1); +assign pyc_shli_2228 = (pe_int_s2_s2c0_lo << 2); +assign pyc_mux_2229 = (pyc_eq_2226 ? pyc_shli_2227 : pyc_shli_2228); +assign pyc_mux_2230 = (pyc_eq_2225 ? pe_int_s2_s2c0_lo : pyc_mux_2229); +assign pyc_eq_2231 = (pyc_add_2224 == pyc_comb_21); +assign pyc_eq_2232 = (pyc_add_2224 == pyc_comb_15); +assign pyc_shli_2233 = (pe_int_s2_s2c0_hi << 1); +assign pyc_shli_2234 = (pe_int_s2_s2c0_hi << 2); +assign pyc_mux_2235 = (pyc_eq_2232 ? pyc_shli_2233 : pyc_shli_2234); +assign pyc_mux_2236 = (pyc_eq_2231 ? pe_int_s2_s2c0_hi : pyc_mux_2235); +assign pyc_extract_2237 = pyc_mux_2230[0]; +assign pyc_extract_2238 = pyc_mux_2236[0]; +assign pyc_xor_2239 = (pyc_extract_2237 ^ pyc_extract_2238); +assign pyc_extract_2240 = pyc_mux_2230[1]; +assign pyc_extract_2241 = pyc_mux_2236[1]; +assign pyc_xor_2242 = (pyc_extract_2240 ^ pyc_extract_2241); +assign pyc_extract_2243 = pyc_mux_2230[2]; +assign pyc_extract_2244 = pyc_mux_2236[2]; +assign pyc_xor_2245 = (pyc_extract_2243 ^ pyc_extract_2244); +assign pyc_extract_2246 = pyc_mux_2230[3]; +assign pyc_extract_2247 = pyc_mux_2236[3]; +assign pyc_xor_2248 = (pyc_extract_2246 ^ pyc_extract_2247); +assign pyc_extract_2249 = pyc_mux_2230[4]; +assign pyc_extract_2250 = pyc_mux_2236[4]; +assign pyc_xor_2251 = (pyc_extract_2249 ^ pyc_extract_2250); +assign pyc_extract_2252 = pyc_mux_2230[5]; +assign pyc_extract_2253 = pyc_mux_2236[5]; +assign pyc_xor_2254 = (pyc_extract_2252 ^ pyc_extract_2253); +assign pyc_extract_2255 = pyc_mux_2230[6]; +assign pyc_extract_2256 = pyc_mux_2236[6]; +assign pyc_xor_2257 = (pyc_extract_2255 ^ pyc_extract_2256); +assign pyc_extract_2258 = pyc_mux_2230[7]; +assign pyc_extract_2259 = pyc_mux_2236[7]; +assign pyc_xor_2260 = (pyc_extract_2258 ^ pyc_extract_2259); +assign pyc_extract_2261 = pyc_mux_2230[8]; +assign pyc_extract_2262 = pyc_mux_2236[8]; +assign pyc_xor_2263 = (pyc_extract_2261 ^ pyc_extract_2262); +assign pyc_extract_2264 = pyc_mux_2230[9]; +assign pyc_extract_2265 = pyc_mux_2236[9]; +assign pyc_xor_2266 = (pyc_extract_2264 ^ pyc_extract_2265); +assign pyc_extract_2267 = pyc_mux_2230[10]; +assign pyc_extract_2268 = pyc_mux_2236[10]; +assign pyc_xor_2269 = (pyc_extract_2267 ^ pyc_extract_2268); +assign pyc_extract_2270 = pyc_mux_2230[11]; +assign pyc_extract_2271 = pyc_mux_2236[11]; +assign pyc_xor_2272 = (pyc_extract_2270 ^ pyc_extract_2271); +assign pyc_extract_2273 = pyc_mux_2230[12]; +assign pyc_extract_2274 = pyc_mux_2236[12]; +assign pyc_xor_2275 = (pyc_extract_2273 ^ pyc_extract_2274); +assign pyc_extract_2276 = pyc_mux_2230[13]; +assign pyc_extract_2277 = pyc_mux_2236[13]; +assign pyc_xor_2278 = (pyc_extract_2276 ^ pyc_extract_2277); +assign pyc_extract_2279 = pyc_mux_2230[14]; +assign pyc_extract_2280 = pyc_mux_2236[14]; +assign pyc_xor_2281 = (pyc_extract_2279 ^ pyc_extract_2280); +assign pyc_extract_2282 = pyc_mux_2230[15]; +assign pyc_extract_2283 = pyc_mux_2236[15]; +assign pyc_xor_2284 = (pyc_extract_2282 ^ pyc_extract_2283); +assign pyc_extract_2285 = pyc_mux_2230[16]; +assign pyc_extract_2286 = pyc_mux_2236[16]; +assign pyc_xor_2287 = (pyc_extract_2285 ^ pyc_extract_2286); +assign pyc_extract_2288 = pyc_mux_2230[17]; +assign pyc_extract_2289 = pyc_mux_2236[17]; +assign pyc_xor_2290 = (pyc_extract_2288 ^ pyc_extract_2289); +assign pyc_extract_2291 = pyc_mux_2230[18]; +assign pyc_extract_2292 = pyc_mux_2236[18]; +assign pyc_xor_2293 = (pyc_extract_2291 ^ pyc_extract_2292); +assign pyc_and_2294 = (pyc_extract_2237 & pyc_extract_2238); +assign pyc_and_2295 = (pyc_extract_2240 & pyc_extract_2241); +assign pyc_and_2296 = (pyc_extract_2243 & pyc_extract_2244); +assign pyc_and_2297 = (pyc_extract_2246 & pyc_extract_2247); +assign pyc_and_2298 = (pyc_extract_2249 & pyc_extract_2250); +assign pyc_and_2299 = (pyc_extract_2252 & pyc_extract_2253); +assign pyc_and_2300 = (pyc_extract_2255 & pyc_extract_2256); +assign pyc_and_2301 = (pyc_extract_2258 & pyc_extract_2259); +assign pyc_and_2302 = (pyc_extract_2261 & pyc_extract_2262); +assign pyc_and_2303 = (pyc_extract_2264 & pyc_extract_2265); +assign pyc_and_2304 = (pyc_extract_2267 & pyc_extract_2268); +assign pyc_and_2305 = (pyc_extract_2270 & pyc_extract_2271); +assign pyc_and_2306 = (pyc_extract_2273 & pyc_extract_2274); +assign pyc_and_2307 = (pyc_extract_2276 & pyc_extract_2277); +assign pyc_and_2308 = (pyc_extract_2279 & pyc_extract_2280); +assign pyc_and_2309 = (pyc_extract_2282 & pyc_extract_2283); +assign pyc_and_2310 = (pyc_extract_2285 & pyc_extract_2286); +assign pyc_and_2311 = (pyc_extract_2288 & pyc_extract_2289); +assign pyc_and_2312 = (pyc_xor_2242 & pyc_and_2294); +assign pyc_or_2313 = (pyc_and_2295 | pyc_and_2312); +assign pyc_and_2314 = (pyc_xor_2248 & pyc_and_2296); +assign pyc_or_2315 = (pyc_and_2297 | pyc_and_2314); +assign pyc_and_2316 = (pyc_xor_2248 & pyc_xor_2245); +assign pyc_and_2317 = (pyc_xor_2254 & pyc_and_2298); +assign pyc_or_2318 = (pyc_and_2299 | pyc_and_2317); +assign pyc_and_2319 = (pyc_xor_2254 & pyc_xor_2251); +assign pyc_and_2320 = (pyc_xor_2260 & pyc_and_2300); +assign pyc_or_2321 = (pyc_and_2301 | pyc_and_2320); +assign pyc_and_2322 = (pyc_xor_2260 & pyc_xor_2257); +assign pyc_and_2323 = (pyc_xor_2266 & pyc_and_2302); +assign pyc_or_2324 = (pyc_and_2303 | pyc_and_2323); +assign pyc_and_2325 = (pyc_xor_2266 & pyc_xor_2263); +assign pyc_and_2326 = (pyc_xor_2272 & pyc_and_2304); +assign pyc_or_2327 = (pyc_and_2305 | pyc_and_2326); +assign pyc_and_2328 = (pyc_xor_2272 & pyc_xor_2269); +assign pyc_and_2329 = (pyc_xor_2278 & pyc_and_2306); +assign pyc_or_2330 = (pyc_and_2307 | pyc_and_2329); +assign pyc_and_2331 = (pyc_xor_2278 & pyc_xor_2275); +assign pyc_and_2332 = (pyc_xor_2284 & pyc_and_2308); +assign pyc_or_2333 = (pyc_and_2309 | pyc_and_2332); +assign pyc_and_2334 = (pyc_xor_2284 & pyc_xor_2281); +assign pyc_and_2335 = (pyc_xor_2290 & pyc_and_2310); +assign pyc_or_2336 = (pyc_and_2311 | pyc_and_2335); +assign pyc_and_2337 = (pyc_xor_2290 & pyc_xor_2287); +assign pyc_and_2338 = (pyc_and_2316 & pyc_or_2313); +assign pyc_or_2339 = (pyc_or_2315 | pyc_and_2338); +assign pyc_and_2340 = (pyc_and_2322 & pyc_or_2318); +assign pyc_or_2341 = (pyc_or_2321 | pyc_and_2340); +assign pyc_and_2342 = (pyc_and_2322 & pyc_and_2319); +assign pyc_and_2343 = (pyc_and_2328 & pyc_or_2324); +assign pyc_or_2344 = (pyc_or_2327 | pyc_and_2343); +assign pyc_and_2345 = (pyc_and_2328 & pyc_and_2325); +assign pyc_and_2346 = (pyc_and_2334 & pyc_or_2330); +assign pyc_or_2347 = (pyc_or_2333 | pyc_and_2346); +assign pyc_and_2348 = (pyc_and_2334 & pyc_and_2331); +assign pyc_and_2349 = (pyc_and_2342 & pyc_or_2339); +assign pyc_or_2350 = (pyc_or_2341 | pyc_and_2349); +assign pyc_and_2351 = (pyc_and_2348 & pyc_or_2344); +assign pyc_or_2352 = (pyc_or_2347 | pyc_and_2351); +assign pyc_and_2353 = (pyc_and_2348 & pyc_and_2345); +assign pyc_and_2354 = (pyc_and_2353 & pyc_or_2350); +assign pyc_or_2355 = (pyc_or_2352 | pyc_and_2354); +assign pyc_and_2356 = (pyc_and_2345 & pyc_or_2350); +assign pyc_or_2357 = (pyc_or_2344 | pyc_and_2356); +assign pyc_and_2358 = (pyc_and_2319 & pyc_or_2339); +assign pyc_or_2359 = (pyc_or_2318 | pyc_and_2358); +assign pyc_and_2360 = (pyc_and_2325 & pyc_or_2350); +assign pyc_or_2361 = (pyc_or_2324 | pyc_and_2360); +assign pyc_and_2362 = (pyc_and_2331 & pyc_or_2357); +assign pyc_or_2363 = (pyc_or_2330 | pyc_and_2362); +assign pyc_and_2364 = (pyc_and_2337 & pyc_or_2355); +assign pyc_or_2365 = (pyc_or_2336 | pyc_and_2364); +assign pyc_and_2366 = (pyc_xor_2245 & pyc_or_2313); +assign pyc_or_2367 = (pyc_and_2296 | pyc_and_2366); +assign pyc_and_2368 = (pyc_xor_2251 & pyc_or_2339); +assign pyc_or_2369 = (pyc_and_2298 | pyc_and_2368); +assign pyc_and_2370 = (pyc_xor_2257 & pyc_or_2359); +assign pyc_or_2371 = (pyc_and_2300 | pyc_and_2370); +assign pyc_and_2372 = (pyc_xor_2263 & pyc_or_2350); +assign pyc_or_2373 = (pyc_and_2302 | pyc_and_2372); +assign pyc_and_2374 = (pyc_xor_2269 & pyc_or_2361); +assign pyc_or_2375 = (pyc_and_2304 | pyc_and_2374); +assign pyc_and_2376 = (pyc_xor_2275 & pyc_or_2357); +assign pyc_or_2377 = (pyc_and_2306 | pyc_and_2376); +assign pyc_and_2378 = (pyc_xor_2281 & pyc_or_2363); +assign pyc_or_2379 = (pyc_and_2308 | pyc_and_2378); +assign pyc_and_2380 = (pyc_xor_2287 & pyc_or_2355); +assign pyc_or_2381 = (pyc_and_2310 | pyc_and_2380); +assign pyc_xor_2382 = (pyc_xor_2242 ^ pyc_and_2294); +assign pyc_xor_2383 = (pyc_xor_2245 ^ pyc_or_2313); +assign pyc_xor_2384 = (pyc_xor_2248 ^ pyc_or_2367); +assign pyc_xor_2385 = (pyc_xor_2251 ^ pyc_or_2339); +assign pyc_xor_2386 = (pyc_xor_2254 ^ pyc_or_2369); +assign pyc_xor_2387 = (pyc_xor_2257 ^ pyc_or_2359); +assign pyc_xor_2388 = (pyc_xor_2260 ^ pyc_or_2371); +assign pyc_xor_2389 = (pyc_xor_2263 ^ pyc_or_2350); +assign pyc_xor_2390 = (pyc_xor_2266 ^ pyc_or_2373); +assign pyc_xor_2391 = (pyc_xor_2269 ^ pyc_or_2361); +assign pyc_xor_2392 = (pyc_xor_2272 ^ pyc_or_2375); +assign pyc_xor_2393 = (pyc_xor_2275 ^ pyc_or_2357); +assign pyc_xor_2394 = (pyc_xor_2278 ^ pyc_or_2377); +assign pyc_xor_2395 = (pyc_xor_2281 ^ pyc_or_2363); +assign pyc_xor_2396 = (pyc_xor_2284 ^ pyc_or_2379); +assign pyc_xor_2397 = (pyc_xor_2287 ^ pyc_or_2355); +assign pyc_xor_2398 = (pyc_xor_2290 ^ pyc_or_2381); +assign pyc_xor_2399 = (pyc_xor_2293 ^ pyc_or_2365); +assign pyc_concat_2400 = {pyc_xor_2399, pyc_xor_2398, pyc_xor_2397, pyc_xor_2396, pyc_xor_2395, pyc_xor_2394, pyc_xor_2393, pyc_xor_2392, pyc_xor_2391, pyc_xor_2390, pyc_xor_2389, pyc_xor_2388, pyc_xor_2387, pyc_xor_2386, pyc_xor_2385, pyc_xor_2384, pyc_xor_2383, pyc_xor_2382, pyc_xor_2239}; +assign pyc_extract_2401 = pe_int_s2_e1_b1[0]; +assign pyc_zext_2402 = {{1{1'b0}}, pyc_extract_2401}; +assign pyc_add_2403 = (pyc_zext_2216 + pyc_zext_2402); +assign pyc_extract_2404 = pe_int_s2_e1_b1[1]; +assign pyc_zext_2405 = {{1{1'b0}}, pyc_extract_2404}; +assign pyc_add_2406 = (pyc_zext_2221 + pyc_zext_2405); +assign pyc_eq_2407 = (pyc_add_2403 == pyc_comb_21); +assign pyc_eq_2408 = (pyc_add_2403 == pyc_comb_15); +assign pyc_shli_2409 = (pe_int_s2_s2c1_lo << 1); +assign pyc_shli_2410 = (pe_int_s2_s2c1_lo << 2); +assign pyc_mux_2411 = (pyc_eq_2408 ? pyc_shli_2409 : pyc_shli_2410); +assign pyc_mux_2412 = (pyc_eq_2407 ? pe_int_s2_s2c1_lo : pyc_mux_2411); +assign pyc_eq_2413 = (pyc_add_2406 == pyc_comb_21); +assign pyc_eq_2414 = (pyc_add_2406 == pyc_comb_15); +assign pyc_shli_2415 = (pe_int_s2_s2c1_hi << 1); +assign pyc_shli_2416 = (pe_int_s2_s2c1_hi << 2); +assign pyc_mux_2417 = (pyc_eq_2414 ? pyc_shli_2415 : pyc_shli_2416); +assign pyc_mux_2418 = (pyc_eq_2413 ? pe_int_s2_s2c1_hi : pyc_mux_2417); +assign pyc_extract_2419 = pyc_mux_2412[0]; +assign pyc_extract_2420 = pyc_mux_2418[0]; +assign pyc_xor_2421 = (pyc_extract_2419 ^ pyc_extract_2420); +assign pyc_extract_2422 = pyc_mux_2412[1]; +assign pyc_extract_2423 = pyc_mux_2418[1]; +assign pyc_xor_2424 = (pyc_extract_2422 ^ pyc_extract_2423); +assign pyc_extract_2425 = pyc_mux_2412[2]; +assign pyc_extract_2426 = pyc_mux_2418[2]; +assign pyc_xor_2427 = (pyc_extract_2425 ^ pyc_extract_2426); +assign pyc_extract_2428 = pyc_mux_2412[3]; +assign pyc_extract_2429 = pyc_mux_2418[3]; +assign pyc_xor_2430 = (pyc_extract_2428 ^ pyc_extract_2429); +assign pyc_extract_2431 = pyc_mux_2412[4]; +assign pyc_extract_2432 = pyc_mux_2418[4]; +assign pyc_xor_2433 = (pyc_extract_2431 ^ pyc_extract_2432); +assign pyc_extract_2434 = pyc_mux_2412[5]; +assign pyc_extract_2435 = pyc_mux_2418[5]; +assign pyc_xor_2436 = (pyc_extract_2434 ^ pyc_extract_2435); +assign pyc_extract_2437 = pyc_mux_2412[6]; +assign pyc_extract_2438 = pyc_mux_2418[6]; +assign pyc_xor_2439 = (pyc_extract_2437 ^ pyc_extract_2438); +assign pyc_extract_2440 = pyc_mux_2412[7]; +assign pyc_extract_2441 = pyc_mux_2418[7]; +assign pyc_xor_2442 = (pyc_extract_2440 ^ pyc_extract_2441); +assign pyc_extract_2443 = pyc_mux_2412[8]; +assign pyc_extract_2444 = pyc_mux_2418[8]; +assign pyc_xor_2445 = (pyc_extract_2443 ^ pyc_extract_2444); +assign pyc_extract_2446 = pyc_mux_2412[9]; +assign pyc_extract_2447 = pyc_mux_2418[9]; +assign pyc_xor_2448 = (pyc_extract_2446 ^ pyc_extract_2447); +assign pyc_extract_2449 = pyc_mux_2412[10]; +assign pyc_extract_2450 = pyc_mux_2418[10]; +assign pyc_xor_2451 = (pyc_extract_2449 ^ pyc_extract_2450); +assign pyc_extract_2452 = pyc_mux_2412[11]; +assign pyc_extract_2453 = pyc_mux_2418[11]; +assign pyc_xor_2454 = (pyc_extract_2452 ^ pyc_extract_2453); +assign pyc_extract_2455 = pyc_mux_2412[12]; +assign pyc_extract_2456 = pyc_mux_2418[12]; +assign pyc_xor_2457 = (pyc_extract_2455 ^ pyc_extract_2456); +assign pyc_extract_2458 = pyc_mux_2412[13]; +assign pyc_extract_2459 = pyc_mux_2418[13]; +assign pyc_xor_2460 = (pyc_extract_2458 ^ pyc_extract_2459); +assign pyc_extract_2461 = pyc_mux_2412[14]; +assign pyc_extract_2462 = pyc_mux_2418[14]; +assign pyc_xor_2463 = (pyc_extract_2461 ^ pyc_extract_2462); +assign pyc_extract_2464 = pyc_mux_2412[15]; +assign pyc_extract_2465 = pyc_mux_2418[15]; +assign pyc_xor_2466 = (pyc_extract_2464 ^ pyc_extract_2465); +assign pyc_and_2467 = (pyc_extract_2419 & pyc_extract_2420); +assign pyc_and_2468 = (pyc_extract_2422 & pyc_extract_2423); +assign pyc_and_2469 = (pyc_extract_2425 & pyc_extract_2426); +assign pyc_and_2470 = (pyc_extract_2428 & pyc_extract_2429); +assign pyc_and_2471 = (pyc_extract_2431 & pyc_extract_2432); +assign pyc_and_2472 = (pyc_extract_2434 & pyc_extract_2435); +assign pyc_and_2473 = (pyc_extract_2437 & pyc_extract_2438); +assign pyc_and_2474 = (pyc_extract_2440 & pyc_extract_2441); +assign pyc_and_2475 = (pyc_extract_2443 & pyc_extract_2444); +assign pyc_and_2476 = (pyc_extract_2446 & pyc_extract_2447); +assign pyc_and_2477 = (pyc_extract_2449 & pyc_extract_2450); +assign pyc_and_2478 = (pyc_extract_2452 & pyc_extract_2453); +assign pyc_and_2479 = (pyc_extract_2455 & pyc_extract_2456); +assign pyc_and_2480 = (pyc_extract_2458 & pyc_extract_2459); +assign pyc_and_2481 = (pyc_extract_2461 & pyc_extract_2462); +assign pyc_and_2482 = (pyc_xor_2424 & pyc_and_2467); +assign pyc_or_2483 = (pyc_and_2468 | pyc_and_2482); +assign pyc_and_2484 = (pyc_xor_2430 & pyc_and_2469); +assign pyc_or_2485 = (pyc_and_2470 | pyc_and_2484); +assign pyc_and_2486 = (pyc_xor_2430 & pyc_xor_2427); +assign pyc_and_2487 = (pyc_xor_2436 & pyc_and_2471); +assign pyc_or_2488 = (pyc_and_2472 | pyc_and_2487); +assign pyc_and_2489 = (pyc_xor_2436 & pyc_xor_2433); +assign pyc_and_2490 = (pyc_xor_2442 & pyc_and_2473); +assign pyc_or_2491 = (pyc_and_2474 | pyc_and_2490); +assign pyc_and_2492 = (pyc_xor_2442 & pyc_xor_2439); +assign pyc_and_2493 = (pyc_xor_2448 & pyc_and_2475); +assign pyc_or_2494 = (pyc_and_2476 | pyc_and_2493); +assign pyc_and_2495 = (pyc_xor_2448 & pyc_xor_2445); +assign pyc_and_2496 = (pyc_xor_2454 & pyc_and_2477); +assign pyc_or_2497 = (pyc_and_2478 | pyc_and_2496); +assign pyc_and_2498 = (pyc_xor_2454 & pyc_xor_2451); +assign pyc_and_2499 = (pyc_xor_2460 & pyc_and_2479); +assign pyc_or_2500 = (pyc_and_2480 | pyc_and_2499); +assign pyc_and_2501 = (pyc_xor_2460 & pyc_xor_2457); +assign pyc_and_2502 = (pyc_and_2486 & pyc_or_2483); +assign pyc_or_2503 = (pyc_or_2485 | pyc_and_2502); +assign pyc_and_2504 = (pyc_and_2492 & pyc_or_2488); +assign pyc_or_2505 = (pyc_or_2491 | pyc_and_2504); +assign pyc_and_2506 = (pyc_and_2492 & pyc_and_2489); +assign pyc_and_2507 = (pyc_and_2498 & pyc_or_2494); +assign pyc_or_2508 = (pyc_or_2497 | pyc_and_2507); +assign pyc_and_2509 = (pyc_and_2498 & pyc_and_2495); +assign pyc_and_2510 = (pyc_and_2506 & pyc_or_2503); +assign pyc_or_2511 = (pyc_or_2505 | pyc_and_2510); +assign pyc_and_2512 = (pyc_and_2509 & pyc_or_2511); +assign pyc_or_2513 = (pyc_or_2508 | pyc_and_2512); +assign pyc_and_2514 = (pyc_and_2489 & pyc_or_2503); +assign pyc_or_2515 = (pyc_or_2488 | pyc_and_2514); +assign pyc_and_2516 = (pyc_and_2495 & pyc_or_2511); +assign pyc_or_2517 = (pyc_or_2494 | pyc_and_2516); +assign pyc_and_2518 = (pyc_and_2501 & pyc_or_2513); +assign pyc_or_2519 = (pyc_or_2500 | pyc_and_2518); +assign pyc_and_2520 = (pyc_xor_2427 & pyc_or_2483); +assign pyc_or_2521 = (pyc_and_2469 | pyc_and_2520); +assign pyc_and_2522 = (pyc_xor_2433 & pyc_or_2503); +assign pyc_or_2523 = (pyc_and_2471 | pyc_and_2522); +assign pyc_and_2524 = (pyc_xor_2439 & pyc_or_2515); +assign pyc_or_2525 = (pyc_and_2473 | pyc_and_2524); +assign pyc_and_2526 = (pyc_xor_2445 & pyc_or_2511); +assign pyc_or_2527 = (pyc_and_2475 | pyc_and_2526); +assign pyc_and_2528 = (pyc_xor_2451 & pyc_or_2517); +assign pyc_or_2529 = (pyc_and_2477 | pyc_and_2528); +assign pyc_and_2530 = (pyc_xor_2457 & pyc_or_2513); +assign pyc_or_2531 = (pyc_and_2479 | pyc_and_2530); +assign pyc_and_2532 = (pyc_xor_2463 & pyc_or_2519); +assign pyc_or_2533 = (pyc_and_2481 | pyc_and_2532); +assign pyc_xor_2534 = (pyc_xor_2424 ^ pyc_and_2467); +assign pyc_xor_2535 = (pyc_xor_2427 ^ pyc_or_2483); +assign pyc_xor_2536 = (pyc_xor_2430 ^ pyc_or_2521); +assign pyc_xor_2537 = (pyc_xor_2433 ^ pyc_or_2503); +assign pyc_xor_2538 = (pyc_xor_2436 ^ pyc_or_2523); +assign pyc_xor_2539 = (pyc_xor_2439 ^ pyc_or_2515); +assign pyc_xor_2540 = (pyc_xor_2442 ^ pyc_or_2525); +assign pyc_xor_2541 = (pyc_xor_2445 ^ pyc_or_2511); +assign pyc_xor_2542 = (pyc_xor_2448 ^ pyc_or_2527); +assign pyc_xor_2543 = (pyc_xor_2451 ^ pyc_or_2517); +assign pyc_xor_2544 = (pyc_xor_2454 ^ pyc_or_2529); +assign pyc_xor_2545 = (pyc_xor_2457 ^ pyc_or_2513); +assign pyc_xor_2546 = (pyc_xor_2460 ^ pyc_or_2531); +assign pyc_xor_2547 = (pyc_xor_2463 ^ pyc_or_2519); +assign pyc_xor_2548 = (pyc_xor_2466 ^ pyc_or_2533); +assign pyc_concat_2549 = {pyc_xor_2548, pyc_xor_2547, pyc_xor_2546, pyc_xor_2545, pyc_xor_2544, pyc_xor_2543, pyc_xor_2542, pyc_xor_2541, pyc_xor_2540, pyc_xor_2539, pyc_xor_2538, pyc_xor_2537, pyc_xor_2536, pyc_xor_2535, pyc_xor_2534, pyc_xor_2421}; +assign pyc_mux_2550 = (pyc_comb_2200 ? pe_int_s2_s2a : pe_int_s2_s2b0); +assign pyc_mux_2551 = (pyc_comb_2202 ? pyc_concat_2400 : pe_int_s2_s2d0); +assign pyc_or_2552 = (pyc_comb_2200 | pyc_comb_2201); +assign pyc_mux_2553 = (pyc_or_2552 ? pyc_mux_2550 : pyc_mux_2551); +assign pe_int_out0__next = pyc_mux_2553; +assign pyc_mux_2554 = (pyc_comb_2200 ? pyc_comb_20 : pe_int_s2_s2b1); +assign pyc_mux_2555 = (pyc_comb_2202 ? pyc_concat_2549 : pe_int_s2_s2d1); +assign pyc_mux_2556 = (pyc_or_2552 ? pyc_mux_2554 : pyc_mux_2555); +assign pyc_comb_2557 = pe_int_out0__next; +assign pyc_comb_2558 = pyc_mux_2556; +assign pe_int_out1 = pyc_reg_2559; +assign pyc_mux_2560 = (pyc_comb_2200 ? pe_int_out1 : pyc_comb_2558); +assign pyc_mux_2561 = (pyc_comb_2192 ? pyc_mux_2560 : pe_int_out1); +assign pyc_comb_2562 = pe_int_out1; +assign pyc_comb_2563 = pyc_mux_2561; +assign pe_int_out1__next = pyc_comb_2563; +assign pe_int_s0_vld = pyc_reg_35; +assign pe_int_s1_vld__next = pe_int_s0_vld; +assign pyc_comb_36 = pe_int_s1_vld__next; +assign pe_int_s0_is_2a = pyc_reg_37; +assign pe_int_s1_is_2a__next = pe_int_s0_is_2a; +assign pyc_comb_38 = pe_int_s1_is_2a__next; +assign pe_int_s0_is_2b = pyc_reg_39; +assign pe_int_s1_is_2b__next = pe_int_s0_is_2b; +assign pyc_comb_40 = pe_int_s1_is_2b__next; +assign pe_int_s0_is_2c = pyc_reg_41; +assign pe_int_s1_is_2c__next = pe_int_s0_is_2c; +assign pyc_comb_42 = pe_int_s1_is_2c__next; +assign pe_int_s0_e1_a = pyc_reg_46; +assign pe_int_s1_e1_a__next = pe_int_s0_e1_a; +assign pyc_comb_47 = pe_int_s1_e1_a__next; +assign pe_int_s0_e1_b0 = pyc_reg_48; +assign pe_int_s1_e1_b0__next = pe_int_s0_e1_b0; +assign pyc_comb_49 = pe_int_s1_e1_b0__next; // --- Submodules PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2a_wallace ( - .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2a_0), - .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2a_1), - .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2a_2), - .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2a_3), - .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2a_4), - .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2a_5), - .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2a_6), - .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2a_7), - .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_509) + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pyc_comb_2036), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pyc_comb_2037), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pyc_comb_2038), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pyc_comb_2039), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pyc_comb_2040), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pyc_comb_2041), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pyc_comb_2042), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pyc_comb_2043), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_2044) ); PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2b0_wallace ( - .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2b0_0), - .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2b0_1), - .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2b0_2), - .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2b0_3), - .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2b0_4), - .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2b0_5), - .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2b0_6), - .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2b0_7), - .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_510) + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pyc_comb_2054), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pyc_comb_2055), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pyc_comb_2056), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pyc_comb_2057), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pyc_comb_2058), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pyc_comb_2059), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pyc_comb_2060), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pyc_comb_2061), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_2062) ); PE_INT_WALLACE_DOT8_TREE_W16 pe_int_s2b1_wallace ( - .PE_INT_WALLACE_DOT8_TREE_W16_in0(pe_int_s1_p2b1_0), - .PE_INT_WALLACE_DOT8_TREE_W16_in1(pe_int_s1_p2b1_1), - .PE_INT_WALLACE_DOT8_TREE_W16_in2(pe_int_s1_p2b1_2), - .PE_INT_WALLACE_DOT8_TREE_W16_in3(pe_int_s1_p2b1_3), - .PE_INT_WALLACE_DOT8_TREE_W16_in4(pe_int_s1_p2b1_4), - .PE_INT_WALLACE_DOT8_TREE_W16_in5(pe_int_s1_p2b1_5), - .PE_INT_WALLACE_DOT8_TREE_W16_in6(pe_int_s1_p2b1_6), - .PE_INT_WALLACE_DOT8_TREE_W16_in7(pe_int_s1_p2b1_7), - .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_511) + .PE_INT_WALLACE_DOT8_TREE_W16_in0(pyc_comb_2072), + .PE_INT_WALLACE_DOT8_TREE_W16_in1(pyc_comb_2073), + .PE_INT_WALLACE_DOT8_TREE_W16_in2(pyc_comb_2074), + .PE_INT_WALLACE_DOT8_TREE_W16_in3(pyc_comb_2075), + .PE_INT_WALLACE_DOT8_TREE_W16_in4(pyc_comb_2076), + .PE_INT_WALLACE_DOT8_TREE_W16_in5(pyc_comb_2077), + .PE_INT_WALLACE_DOT8_TREE_W16_in6(pyc_comb_2078), + .PE_INT_WALLACE_DOT8_TREE_W16_in7(pyc_comb_2079), + .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_2080) ); PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2d0_wallace ( - .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2d0_0), - .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2d0_1), - .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2d0_2), - .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2d0_3), - .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2d0_4), - .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2d0_5), - .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2d0_6), - .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2d0_7), - .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_512) + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pyc_comb_2090), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pyc_comb_2091), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pyc_comb_2092), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pyc_comb_2093), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pyc_comb_2094), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pyc_comb_2095), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pyc_comb_2096), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pyc_comb_2097), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_2098) ); PE_INT_WALLACE_DOT8_TREE_W16 pe_int_s2d1_wallace ( - .PE_INT_WALLACE_DOT8_TREE_W16_in0(pe_int_s1_p2d1_0), - .PE_INT_WALLACE_DOT8_TREE_W16_in1(pe_int_s1_p2d1_1), - .PE_INT_WALLACE_DOT8_TREE_W16_in2(pe_int_s1_p2d1_2), - .PE_INT_WALLACE_DOT8_TREE_W16_in3(pe_int_s1_p2d1_3), - .PE_INT_WALLACE_DOT8_TREE_W16_in4(pe_int_s1_p2d1_4), - .PE_INT_WALLACE_DOT8_TREE_W16_in5(pe_int_s1_p2d1_5), - .PE_INT_WALLACE_DOT8_TREE_W16_in6(pe_int_s1_p2d1_6), - .PE_INT_WALLACE_DOT8_TREE_W16_in7(pe_int_s1_p2d1_7), - .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_513) + .PE_INT_WALLACE_DOT8_TREE_W16_in0(pyc_comb_2108), + .PE_INT_WALLACE_DOT8_TREE_W16_in1(pyc_comb_2109), + .PE_INT_WALLACE_DOT8_TREE_W16_in2(pyc_comb_2110), + .PE_INT_WALLACE_DOT8_TREE_W16_in3(pyc_comb_2111), + .PE_INT_WALLACE_DOT8_TREE_W16_in4(pyc_comb_2112), + .PE_INT_WALLACE_DOT8_TREE_W16_in5(pyc_comb_2113), + .PE_INT_WALLACE_DOT8_TREE_W16_in6(pyc_comb_2114), + .PE_INT_WALLACE_DOT8_TREE_W16_in7(pyc_comb_2115), + .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_2116) ); PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2c0_lo_wallace ( - .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2c0_0), - .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2c0_1), - .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2c0_2), - .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2c0_3), - .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2c0_4), - .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2c0_5), - .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2c0_6), - .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2c0_7), - .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_514) + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pyc_comb_2126), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pyc_comb_2127), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pyc_comb_2128), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pyc_comb_2129), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pyc_comb_2130), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pyc_comb_2131), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pyc_comb_2132), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pyc_comb_2133), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_2134) ); PE_INT_WALLACE_DOT8_TREE_W19 pe_int_s2c0_hi_wallace ( - .PE_INT_WALLACE_DOT8_TREE_W19_in0(pe_int_s1_p2c0_8), - .PE_INT_WALLACE_DOT8_TREE_W19_in1(pe_int_s1_p2c0_9), - .PE_INT_WALLACE_DOT8_TREE_W19_in2(pe_int_s1_p2c0_10), - .PE_INT_WALLACE_DOT8_TREE_W19_in3(pe_int_s1_p2c0_11), - .PE_INT_WALLACE_DOT8_TREE_W19_in4(pe_int_s1_p2c0_12), - .PE_INT_WALLACE_DOT8_TREE_W19_in5(pe_int_s1_p2c0_13), - .PE_INT_WALLACE_DOT8_TREE_W19_in6(pe_int_s1_p2c0_14), - .PE_INT_WALLACE_DOT8_TREE_W19_in7(pe_int_s1_p2c0_15), - .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_515) + .PE_INT_WALLACE_DOT8_TREE_W19_in0(pyc_comb_2144), + .PE_INT_WALLACE_DOT8_TREE_W19_in1(pyc_comb_2145), + .PE_INT_WALLACE_DOT8_TREE_W19_in2(pyc_comb_2146), + .PE_INT_WALLACE_DOT8_TREE_W19_in3(pyc_comb_2147), + .PE_INT_WALLACE_DOT8_TREE_W19_in4(pyc_comb_2148), + .PE_INT_WALLACE_DOT8_TREE_W19_in5(pyc_comb_2149), + .PE_INT_WALLACE_DOT8_TREE_W19_in6(pyc_comb_2150), + .PE_INT_WALLACE_DOT8_TREE_W19_in7(pyc_comb_2151), + .PE_INT_WALLACE_DOT8_TREE_W19_sum(pyc_instance_2152) ); PE_INT_WALLACE_DOT8_TREE_W16 pe_int_s2c1_lo_wallace ( - .PE_INT_WALLACE_DOT8_TREE_W16_in0(pe_int_s1_p2c1_0), - .PE_INT_WALLACE_DOT8_TREE_W16_in1(pe_int_s1_p2c1_1), - .PE_INT_WALLACE_DOT8_TREE_W16_in2(pe_int_s1_p2c1_2), - .PE_INT_WALLACE_DOT8_TREE_W16_in3(pe_int_s1_p2c1_3), - .PE_INT_WALLACE_DOT8_TREE_W16_in4(pe_int_s1_p2c1_4), - .PE_INT_WALLACE_DOT8_TREE_W16_in5(pe_int_s1_p2c1_5), - .PE_INT_WALLACE_DOT8_TREE_W16_in6(pe_int_s1_p2c1_6), - .PE_INT_WALLACE_DOT8_TREE_W16_in7(pe_int_s1_p2c1_7), - .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_516) + .PE_INT_WALLACE_DOT8_TREE_W16_in0(pyc_comb_2162), + .PE_INT_WALLACE_DOT8_TREE_W16_in1(pyc_comb_2163), + .PE_INT_WALLACE_DOT8_TREE_W16_in2(pyc_comb_2164), + .PE_INT_WALLACE_DOT8_TREE_W16_in3(pyc_comb_2165), + .PE_INT_WALLACE_DOT8_TREE_W16_in4(pyc_comb_2166), + .PE_INT_WALLACE_DOT8_TREE_W16_in5(pyc_comb_2167), + .PE_INT_WALLACE_DOT8_TREE_W16_in6(pyc_comb_2168), + .PE_INT_WALLACE_DOT8_TREE_W16_in7(pyc_comb_2169), + .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_2170) ); PE_INT_WALLACE_DOT8_TREE_W16 pe_int_s2c1_hi_wallace ( - .PE_INT_WALLACE_DOT8_TREE_W16_in0(pe_int_s1_p2c1_8), - .PE_INT_WALLACE_DOT8_TREE_W16_in1(pe_int_s1_p2c1_9), - .PE_INT_WALLACE_DOT8_TREE_W16_in2(pe_int_s1_p2c1_10), - .PE_INT_WALLACE_DOT8_TREE_W16_in3(pe_int_s1_p2c1_11), - .PE_INT_WALLACE_DOT8_TREE_W16_in4(pe_int_s1_p2c1_12), - .PE_INT_WALLACE_DOT8_TREE_W16_in5(pe_int_s1_p2c1_13), - .PE_INT_WALLACE_DOT8_TREE_W16_in6(pe_int_s1_p2c1_14), - .PE_INT_WALLACE_DOT8_TREE_W16_in7(pe_int_s1_p2c1_15), - .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_517) + .PE_INT_WALLACE_DOT8_TREE_W16_in0(pyc_comb_2180), + .PE_INT_WALLACE_DOT8_TREE_W16_in1(pyc_comb_2181), + .PE_INT_WALLACE_DOT8_TREE_W16_in2(pyc_comb_2182), + .PE_INT_WALLACE_DOT8_TREE_W16_in3(pyc_comb_2183), + .PE_INT_WALLACE_DOT8_TREE_W16_in4(pyc_comb_2184), + .PE_INT_WALLACE_DOT8_TREE_W16_in5(pyc_comb_2185), + .PE_INT_WALLACE_DOT8_TREE_W16_in6(pyc_comb_2186), + .PE_INT_WALLACE_DOT8_TREE_W16_in7(pyc_comb_2187), + .PE_INT_WALLACE_DOT8_TREE_W16_sum(pyc_instance_2188) ); // --- Sequential primitives -PYC_REG #(.WIDTH(1)) pyc_reg_29_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_1941_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_25), - .init(pyc_comb_18), - .q(pyc_reg_29) + .en(pyc_comb_23), + .d(pyc_comb_36), + .init(pyc_comb_24), + .q(pyc_reg_1941) ); -PYC_REG #(.WIDTH(1)) pyc_reg_31_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_1943_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_26), - .init(pyc_comb_18), - .q(pyc_reg_31) + .en(pyc_comb_23), + .d(pyc_comb_38), + .init(pyc_comb_24), + .q(pyc_reg_1943) ); -PYC_REG #(.WIDTH(1)) pyc_reg_33_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_1945_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_27), - .init(pyc_comb_18), - .q(pyc_reg_33) + .en(pyc_comb_23), + .d(pyc_comb_40), + .init(pyc_comb_24), + .q(pyc_reg_1945) ); -PYC_REG #(.WIDTH(1)) pyc_reg_35_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_1947_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_28), - .init(pyc_comb_18), - .q(pyc_reg_35) + .en(pyc_comb_23), + .d(pyc_comb_42), + .init(pyc_comb_24), + .q(pyc_reg_1947) ); -PYC_REG #(.WIDTH(80)) pyc_reg_37_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_1949_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_24), - .init(pyc_comb_16), - .q(pyc_reg_37) + .en(pyc_comb_23), + .d(pyc_comb_47), + .init(pyc_comb_21), + .q(pyc_reg_1949) ); -PYC_REG #(.WIDTH(80)) pyc_reg_38_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_1951_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_23), - .init(pyc_comb_16), - .q(pyc_reg_38) + .en(pyc_comb_23), + .d(pyc_comb_49), + .init(pyc_comb_21), + .q(pyc_reg_1951) ); -PYC_REG #(.WIDTH(80)) pyc_reg_39_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_1953_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_22), - .init(pyc_comb_16), - .q(pyc_reg_39) + .en(pyc_comb_23), + .d(pyc_comb_1868), + .init(pyc_comb_21), + .q(pyc_reg_1953) ); -PYC_REG #(.WIDTH(2)) pyc_reg_40_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_1955_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_21), - .init(pyc_comb_15), - .q(pyc_reg_40) + .en(pyc_comb_23), + .d(pyc_comb_1869), + .init(pyc_comb_20), + .q(pyc_reg_1955) ); -PYC_REG #(.WIDTH(2)) pyc_reg_42_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_1956_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_20), - .init(pyc_comb_15), - .q(pyc_reg_42) + .en(pyc_comb_23), + .d(pyc_comb_1874), + .init(pyc_comb_20), + .q(pyc_reg_1956) ); -PYC_REG #(.WIDTH(1)) pyc_reg_423_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_1957_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_30), - .init(pyc_comb_18), - .q(pyc_reg_423) + .en(pyc_comb_23), + .d(pyc_comb_1879), + .init(pyc_comb_20), + .q(pyc_reg_1957) ); -PYC_REG #(.WIDTH(1)) pyc_reg_425_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_1958_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_32), - .init(pyc_comb_18), - .q(pyc_reg_425) + .en(pyc_comb_23), + .d(pyc_comb_1884), + .init(pyc_comb_20), + .q(pyc_reg_1958) ); -PYC_REG #(.WIDTH(1)) pyc_reg_427_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_1959_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_34), - .init(pyc_comb_18), - .q(pyc_reg_427) + .en(pyc_comb_23), + .d(pyc_comb_1889), + .init(pyc_comb_20), + .q(pyc_reg_1959) ); -PYC_REG #(.WIDTH(1)) pyc_reg_429_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_1960_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_36), - .init(pyc_comb_18), - .q(pyc_reg_429) + .en(pyc_comb_23), + .d(pyc_comb_1894), + .init(pyc_comb_20), + .q(pyc_reg_1960) ); -PYC_REG #(.WIDTH(2)) pyc_reg_431_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_1961_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_41), - .init(pyc_comb_15), - .q(pyc_reg_431) + .en(pyc_comb_23), + .d(pyc_comb_1899), + .init(pyc_comb_20), + .q(pyc_reg_1961) ); -PYC_REG #(.WIDTH(2)) pyc_reg_433_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_1962_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_43), - .init(pyc_comb_15), - .q(pyc_reg_433) + .en(pyc_comb_23), + .d(pyc_comb_1904), + .init(pyc_comb_20), + .q(pyc_reg_1962) ); -PYC_REG #(.WIDTH(2)) pyc_reg_435_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1963_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_350), - .init(pyc_comb_15), - .q(pyc_reg_435) + .en(pyc_comb_23), + .d(pyc_comb_1870), + .init(pyc_comb_19), + .q(pyc_reg_1963) ); -PYC_REG #(.WIDTH(19)) pyc_reg_437_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1964_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_351), - .init(pyc_comb_14), - .q(pyc_reg_437) + .en(pyc_comb_23), + .d(pyc_comb_1875), + .init(pyc_comb_19), + .q(pyc_reg_1964) ); -PYC_REG #(.WIDTH(19)) pyc_reg_438_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1965_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_356), - .init(pyc_comb_14), - .q(pyc_reg_438) + .en(pyc_comb_23), + .d(pyc_comb_1880), + .init(pyc_comb_19), + .q(pyc_reg_1965) ); -PYC_REG #(.WIDTH(19)) pyc_reg_439_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1966_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_361), - .init(pyc_comb_14), - .q(pyc_reg_439) + .en(pyc_comb_23), + .d(pyc_comb_1885), + .init(pyc_comb_19), + .q(pyc_reg_1966) ); -PYC_REG #(.WIDTH(2)) pyc_reg_44_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1967_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_19), - .init(pyc_comb_15), - .q(pyc_reg_44) + .en(pyc_comb_23), + .d(pyc_comb_1890), + .init(pyc_comb_19), + .q(pyc_reg_1967) ); -PYC_REG #(.WIDTH(19)) pyc_reg_440_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1968_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_366), - .init(pyc_comb_14), - .q(pyc_reg_440) + .en(pyc_comb_23), + .d(pyc_comb_1895), + .init(pyc_comb_19), + .q(pyc_reg_1968) ); -PYC_REG #(.WIDTH(19)) pyc_reg_441_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1969_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_371), - .init(pyc_comb_14), - .q(pyc_reg_441) + .en(pyc_comb_23), + .d(pyc_comb_1900), + .init(pyc_comb_19), + .q(pyc_reg_1969) ); -PYC_REG #(.WIDTH(19)) pyc_reg_442_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1970_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_376), - .init(pyc_comb_14), - .q(pyc_reg_442) + .en(pyc_comb_23), + .d(pyc_comb_1905), + .init(pyc_comb_19), + .q(pyc_reg_1970) ); -PYC_REG #(.WIDTH(19)) pyc_reg_443_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1971_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_381), - .init(pyc_comb_14), - .q(pyc_reg_443) + .en(pyc_comb_23), + .d(pyc_comb_1871), + .init(pyc_comb_19), + .q(pyc_reg_1971) ); -PYC_REG #(.WIDTH(19)) pyc_reg_444_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1972_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_386), - .init(pyc_comb_14), - .q(pyc_reg_444) + .en(pyc_comb_23), + .d(pyc_comb_1876), + .init(pyc_comb_19), + .q(pyc_reg_1972) ); -PYC_REG #(.WIDTH(19)) pyc_reg_445_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1973_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_352), - .init(pyc_comb_14), - .q(pyc_reg_445) + .en(pyc_comb_23), + .d(pyc_comb_1881), + .init(pyc_comb_19), + .q(pyc_reg_1973) ); -PYC_REG #(.WIDTH(19)) pyc_reg_446_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1974_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_357), - .init(pyc_comb_14), - .q(pyc_reg_446) + .en(pyc_comb_23), + .d(pyc_comb_1886), + .init(pyc_comb_19), + .q(pyc_reg_1974) ); -PYC_REG #(.WIDTH(19)) pyc_reg_447_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1975_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_362), - .init(pyc_comb_14), - .q(pyc_reg_447) + .en(pyc_comb_23), + .d(pyc_comb_1891), + .init(pyc_comb_19), + .q(pyc_reg_1975) ); -PYC_REG #(.WIDTH(19)) pyc_reg_448_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1976_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_367), - .init(pyc_comb_14), - .q(pyc_reg_448) + .en(pyc_comb_23), + .d(pyc_comb_1896), + .init(pyc_comb_19), + .q(pyc_reg_1976) ); -PYC_REG #(.WIDTH(19)) pyc_reg_449_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1977_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_372), - .init(pyc_comb_14), - .q(pyc_reg_449) + .en(pyc_comb_23), + .d(pyc_comb_1901), + .init(pyc_comb_19), + .q(pyc_reg_1977) ); -PYC_REG #(.WIDTH(19)) pyc_reg_450_inst ( +PYC_REG #(.WIDTH(12)) pyc_reg_1978_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_377), - .init(pyc_comb_14), - .q(pyc_reg_450) + .en(pyc_comb_23), + .d(pyc_comb_1906), + .init(pyc_comb_19), + .q(pyc_reg_1978) ); -PYC_REG #(.WIDTH(19)) pyc_reg_451_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1979_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_382), - .init(pyc_comb_14), - .q(pyc_reg_451) + .en(pyc_comb_23), + .d(pyc_comb_1872), + .init(pyc_comb_18), + .q(pyc_reg_1979) ); -PYC_REG #(.WIDTH(19)) pyc_reg_452_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1980_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_387), - .init(pyc_comb_14), - .q(pyc_reg_452) + .en(pyc_comb_23), + .d(pyc_comb_1877), + .init(pyc_comb_18), + .q(pyc_reg_1980) ); -PYC_REG #(.WIDTH(16)) pyc_reg_453_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1981_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_353), - .init(pyc_comb_13), - .q(pyc_reg_453) + .en(pyc_comb_23), + .d(pyc_comb_1882), + .init(pyc_comb_18), + .q(pyc_reg_1981) ); -PYC_REG #(.WIDTH(16)) pyc_reg_454_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1982_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_358), - .init(pyc_comb_13), - .q(pyc_reg_454) + .en(pyc_comb_23), + .d(pyc_comb_1887), + .init(pyc_comb_18), + .q(pyc_reg_1982) ); -PYC_REG #(.WIDTH(16)) pyc_reg_455_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1983_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_363), - .init(pyc_comb_13), - .q(pyc_reg_455) + .en(pyc_comb_23), + .d(pyc_comb_1892), + .init(pyc_comb_18), + .q(pyc_reg_1983) ); -PYC_REG #(.WIDTH(16)) pyc_reg_456_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1984_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_368), - .init(pyc_comb_13), - .q(pyc_reg_456) + .en(pyc_comb_23), + .d(pyc_comb_1897), + .init(pyc_comb_18), + .q(pyc_reg_1984) ); -PYC_REG #(.WIDTH(16)) pyc_reg_457_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1985_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_373), - .init(pyc_comb_13), - .q(pyc_reg_457) + .en(pyc_comb_23), + .d(pyc_comb_1902), + .init(pyc_comb_18), + .q(pyc_reg_1985) ); -PYC_REG #(.WIDTH(16)) pyc_reg_458_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1986_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_378), - .init(pyc_comb_13), - .q(pyc_reg_458) + .en(pyc_comb_23), + .d(pyc_comb_1907), + .init(pyc_comb_18), + .q(pyc_reg_1986) ); -PYC_REG #(.WIDTH(16)) pyc_reg_459_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1987_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_383), - .init(pyc_comb_13), - .q(pyc_reg_459) + .en(pyc_comb_23), + .d(pyc_comb_1873), + .init(pyc_comb_18), + .q(pyc_reg_1987) ); -PYC_REG #(.WIDTH(16)) pyc_reg_460_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1988_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_388), - .init(pyc_comb_13), - .q(pyc_reg_460) + .en(pyc_comb_23), + .d(pyc_comb_1878), + .init(pyc_comb_18), + .q(pyc_reg_1988) ); -PYC_REG #(.WIDTH(19)) pyc_reg_461_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1989_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_354), - .init(pyc_comb_14), - .q(pyc_reg_461) + .en(pyc_comb_23), + .d(pyc_comb_1883), + .init(pyc_comb_18), + .q(pyc_reg_1989) ); -PYC_REG #(.WIDTH(19)) pyc_reg_462_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1990_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_359), - .init(pyc_comb_14), - .q(pyc_reg_462) + .en(pyc_comb_23), + .d(pyc_comb_1888), + .init(pyc_comb_18), + .q(pyc_reg_1990) ); -PYC_REG #(.WIDTH(19)) pyc_reg_463_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1991_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_364), - .init(pyc_comb_14), - .q(pyc_reg_463) + .en(pyc_comb_23), + .d(pyc_comb_1893), + .init(pyc_comb_18), + .q(pyc_reg_1991) ); -PYC_REG #(.WIDTH(19)) pyc_reg_464_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1992_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_369), - .init(pyc_comb_14), - .q(pyc_reg_464) + .en(pyc_comb_23), + .d(pyc_comb_1898), + .init(pyc_comb_18), + .q(pyc_reg_1992) ); -PYC_REG #(.WIDTH(19)) pyc_reg_465_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1993_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_374), - .init(pyc_comb_14), - .q(pyc_reg_465) + .en(pyc_comb_23), + .d(pyc_comb_1903), + .init(pyc_comb_18), + .q(pyc_reg_1993) ); -PYC_REG #(.WIDTH(19)) pyc_reg_466_inst ( +PYC_REG #(.WIDTH(13)) pyc_reg_1994_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_379), - .init(pyc_comb_14), - .q(pyc_reg_466) + .en(pyc_comb_23), + .d(pyc_comb_1908), + .init(pyc_comb_18), + .q(pyc_reg_1994) ); -PYC_REG #(.WIDTH(19)) pyc_reg_467_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_1995_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_384), - .init(pyc_comb_14), - .q(pyc_reg_467) + .en(pyc_comb_23), + .d(pyc_comb_1909), + .init(pyc_comb_17), + .q(pyc_reg_1995) ); -PYC_REG #(.WIDTH(19)) pyc_reg_468_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_1996_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_389), - .init(pyc_comb_14), - .q(pyc_reg_468) + .en(pyc_comb_23), + .d(pyc_comb_1911), + .init(pyc_comb_17), + .q(pyc_reg_1996) ); -PYC_REG #(.WIDTH(16)) pyc_reg_469_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_1997_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_355), - .init(pyc_comb_13), - .q(pyc_reg_469) + .en(pyc_comb_23), + .d(pyc_comb_1913), + .init(pyc_comb_17), + .q(pyc_reg_1997) ); -PYC_REG #(.WIDTH(16)) pyc_reg_470_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_1998_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_360), - .init(pyc_comb_13), - .q(pyc_reg_470) + .en(pyc_comb_23), + .d(pyc_comb_1915), + .init(pyc_comb_17), + .q(pyc_reg_1998) ); -PYC_REG #(.WIDTH(16)) pyc_reg_471_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_1999_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_365), - .init(pyc_comb_13), - .q(pyc_reg_471) + .en(pyc_comb_23), + .d(pyc_comb_1917), + .init(pyc_comb_17), + .q(pyc_reg_1999) ); -PYC_REG #(.WIDTH(16)) pyc_reg_472_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2000_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_370), - .init(pyc_comb_13), - .q(pyc_reg_472) + .en(pyc_comb_23), + .d(pyc_comb_1919), + .init(pyc_comb_17), + .q(pyc_reg_2000) ); -PYC_REG #(.WIDTH(16)) pyc_reg_473_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2001_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_375), - .init(pyc_comb_13), - .q(pyc_reg_473) + .en(pyc_comb_23), + .d(pyc_comb_1921), + .init(pyc_comb_17), + .q(pyc_reg_2001) ); -PYC_REG #(.WIDTH(16)) pyc_reg_474_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2002_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_380), - .init(pyc_comb_13), - .q(pyc_reg_474) + .en(pyc_comb_23), + .d(pyc_comb_1923), + .init(pyc_comb_17), + .q(pyc_reg_2002) ); -PYC_REG #(.WIDTH(16)) pyc_reg_475_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2003_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_385), - .init(pyc_comb_13), - .q(pyc_reg_475) + .en(pyc_comb_23), + .d(pyc_comb_1925), + .init(pyc_comb_17), + .q(pyc_reg_2003) ); -PYC_REG #(.WIDTH(16)) pyc_reg_476_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2004_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_390), - .init(pyc_comb_13), - .q(pyc_reg_476) + .en(pyc_comb_23), + .d(pyc_comb_1927), + .init(pyc_comb_17), + .q(pyc_reg_2004) ); -PYC_REG #(.WIDTH(19)) pyc_reg_477_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2005_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_391), - .init(pyc_comb_14), - .q(pyc_reg_477) + .en(pyc_comb_23), + .d(pyc_comb_1929), + .init(pyc_comb_17), + .q(pyc_reg_2005) ); -PYC_REG #(.WIDTH(19)) pyc_reg_478_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2006_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_393), - .init(pyc_comb_14), - .q(pyc_reg_478) + .en(pyc_comb_23), + .d(pyc_comb_1931), + .init(pyc_comb_17), + .q(pyc_reg_2006) ); -PYC_REG #(.WIDTH(19)) pyc_reg_479_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2007_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_395), - .init(pyc_comb_14), - .q(pyc_reg_479) + .en(pyc_comb_23), + .d(pyc_comb_1933), + .init(pyc_comb_17), + .q(pyc_reg_2007) ); -PYC_REG #(.WIDTH(19)) pyc_reg_480_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2008_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_397), - .init(pyc_comb_14), - .q(pyc_reg_480) + .en(pyc_comb_23), + .d(pyc_comb_1935), + .init(pyc_comb_17), + .q(pyc_reg_2008) ); -PYC_REG #(.WIDTH(19)) pyc_reg_481_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2009_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_399), - .init(pyc_comb_14), - .q(pyc_reg_481) + .en(pyc_comb_23), + .d(pyc_comb_1937), + .init(pyc_comb_17), + .q(pyc_reg_2009) ); -PYC_REG #(.WIDTH(19)) pyc_reg_482_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2010_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_401), - .init(pyc_comb_14), - .q(pyc_reg_482) + .en(pyc_comb_23), + .d(pyc_comb_1939), + .init(pyc_comb_17), + .q(pyc_reg_2010) ); -PYC_REG #(.WIDTH(19)) pyc_reg_483_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2011_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_403), - .init(pyc_comb_14), - .q(pyc_reg_483) + .en(pyc_comb_23), + .d(pyc_comb_1910), + .init(pyc_comb_17), + .q(pyc_reg_2011) ); -PYC_REG #(.WIDTH(19)) pyc_reg_484_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2012_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_405), - .init(pyc_comb_14), - .q(pyc_reg_484) + .en(pyc_comb_23), + .d(pyc_comb_1912), + .init(pyc_comb_17), + .q(pyc_reg_2012) ); -PYC_REG #(.WIDTH(19)) pyc_reg_485_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2013_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_407), - .init(pyc_comb_14), - .q(pyc_reg_485) + .en(pyc_comb_23), + .d(pyc_comb_1914), + .init(pyc_comb_17), + .q(pyc_reg_2013) ); -PYC_REG #(.WIDTH(19)) pyc_reg_486_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2014_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_409), - .init(pyc_comb_14), - .q(pyc_reg_486) + .en(pyc_comb_23), + .d(pyc_comb_1916), + .init(pyc_comb_17), + .q(pyc_reg_2014) ); -PYC_REG #(.WIDTH(19)) pyc_reg_487_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2015_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_411), - .init(pyc_comb_14), - .q(pyc_reg_487) + .en(pyc_comb_23), + .d(pyc_comb_1918), + .init(pyc_comb_17), + .q(pyc_reg_2015) ); -PYC_REG #(.WIDTH(19)) pyc_reg_488_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2016_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_413), - .init(pyc_comb_14), - .q(pyc_reg_488) + .en(pyc_comb_23), + .d(pyc_comb_1920), + .init(pyc_comb_17), + .q(pyc_reg_2016) ); -PYC_REG #(.WIDTH(19)) pyc_reg_489_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2017_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_415), - .init(pyc_comb_14), - .q(pyc_reg_489) + .en(pyc_comb_23), + .d(pyc_comb_1922), + .init(pyc_comb_17), + .q(pyc_reg_2017) ); -PYC_REG #(.WIDTH(19)) pyc_reg_490_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2018_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_417), - .init(pyc_comb_14), - .q(pyc_reg_490) + .en(pyc_comb_23), + .d(pyc_comb_1924), + .init(pyc_comb_17), + .q(pyc_reg_2018) ); -PYC_REG #(.WIDTH(19)) pyc_reg_491_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2019_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_419), - .init(pyc_comb_14), - .q(pyc_reg_491) + .en(pyc_comb_23), + .d(pyc_comb_1926), + .init(pyc_comb_17), + .q(pyc_reg_2019) ); -PYC_REG #(.WIDTH(19)) pyc_reg_492_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2020_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_421), - .init(pyc_comb_14), - .q(pyc_reg_492) + .en(pyc_comb_23), + .d(pyc_comb_1928), + .init(pyc_comb_17), + .q(pyc_reg_2020) ); -PYC_REG #(.WIDTH(16)) pyc_reg_493_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2021_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_392), - .init(pyc_comb_13), - .q(pyc_reg_493) + .en(pyc_comb_23), + .d(pyc_comb_1930), + .init(pyc_comb_17), + .q(pyc_reg_2021) ); -PYC_REG #(.WIDTH(16)) pyc_reg_494_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2022_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_394), - .init(pyc_comb_13), - .q(pyc_reg_494) + .en(pyc_comb_23), + .d(pyc_comb_1932), + .init(pyc_comb_17), + .q(pyc_reg_2022) ); -PYC_REG #(.WIDTH(16)) pyc_reg_495_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2023_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_396), - .init(pyc_comb_13), - .q(pyc_reg_495) + .en(pyc_comb_23), + .d(pyc_comb_1934), + .init(pyc_comb_17), + .q(pyc_reg_2023) ); -PYC_REG #(.WIDTH(16)) pyc_reg_496_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2024_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_398), - .init(pyc_comb_13), - .q(pyc_reg_496) + .en(pyc_comb_23), + .d(pyc_comb_1936), + .init(pyc_comb_17), + .q(pyc_reg_2024) ); -PYC_REG #(.WIDTH(16)) pyc_reg_497_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2025_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_400), - .init(pyc_comb_13), - .q(pyc_reg_497) + .en(pyc_comb_23), + .d(pyc_comb_1938), + .init(pyc_comb_17), + .q(pyc_reg_2025) ); -PYC_REG #(.WIDTH(16)) pyc_reg_498_inst ( +PYC_REG #(.WIDTH(10)) pyc_reg_2026_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_402), - .init(pyc_comb_13), - .q(pyc_reg_498) + .en(pyc_comb_23), + .d(pyc_comb_1940), + .init(pyc_comb_17), + .q(pyc_reg_2026) ); -PYC_REG #(.WIDTH(16)) pyc_reg_499_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_2189_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_404), - .init(pyc_comb_13), - .q(pyc_reg_499) + .en(pyc_comb_23), + .d(pyc_comb_1942), + .init(pyc_comb_24), + .q(pyc_reg_2189) ); -PYC_REG #(.WIDTH(16)) pyc_reg_500_inst ( +PYC_REG #(.WIDTH(3)) pyc_reg_2196_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_406), - .init(pyc_comb_13), - .q(pyc_reg_500) + .en(pyc_comb_23), + .d(pyc_comb_2194), + .init(pyc_comb_2195), + .q(pyc_reg_2196) ); -PYC_REG #(.WIDTH(16)) pyc_reg_501_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_2203_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_408), - .init(pyc_comb_13), - .q(pyc_reg_501) + .en(pyc_comb_23), + .d(pyc_comb_1950), + .init(pyc_comb_21), + .q(pyc_reg_2203) ); -PYC_REG #(.WIDTH(16)) pyc_reg_502_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_2204_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_410), - .init(pyc_comb_13), - .q(pyc_reg_502) + .en(pyc_comb_23), + .d(pyc_comb_1952), + .init(pyc_comb_21), + .q(pyc_reg_2204) ); -PYC_REG #(.WIDTH(16)) pyc_reg_503_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_2205_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_412), - .init(pyc_comb_13), - .q(pyc_reg_503) + .en(pyc_comb_23), + .d(pyc_comb_1954), + .init(pyc_comb_21), + .q(pyc_reg_2205) ); -PYC_REG #(.WIDTH(16)) pyc_reg_504_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_2206_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_414), - .init(pyc_comb_13), - .q(pyc_reg_504) + .en(pyc_comb_23), + .d(pyc_comb_2053), + .init(pyc_comb_16), + .q(pyc_reg_2206) ); -PYC_REG #(.WIDTH(16)) pyc_reg_505_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_2207_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_416), - .init(pyc_comb_13), - .q(pyc_reg_505) + .en(pyc_comb_23), + .d(pyc_comb_2071), + .init(pyc_comb_16), + .q(pyc_reg_2207) ); -PYC_REG #(.WIDTH(16)) pyc_reg_506_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_2208_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_418), - .init(pyc_comb_13), - .q(pyc_reg_506) + .en(pyc_comb_23), + .d(pyc_comb_2089), + .init(pyc_comb_20), + .q(pyc_reg_2208) ); -PYC_REG #(.WIDTH(16)) pyc_reg_507_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_2209_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_420), - .init(pyc_comb_13), - .q(pyc_reg_507) + .en(pyc_comb_23), + .d(pyc_comb_2107), + .init(pyc_comb_16), + .q(pyc_reg_2209) ); -PYC_REG #(.WIDTH(16)) pyc_reg_508_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_2210_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_422), - .init(pyc_comb_13), - .q(pyc_reg_508) + .en(pyc_comb_23), + .d(pyc_comb_2125), + .init(pyc_comb_20), + .q(pyc_reg_2210) ); -PYC_REG #(.WIDTH(1)) pyc_reg_518_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_2211_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_424), - .init(pyc_comb_18), - .q(pyc_reg_518) + .en(pyc_comb_23), + .d(pyc_comb_2143), + .init(pyc_comb_16), + .q(pyc_reg_2211) ); -PYC_REG #(.WIDTH(3)) pyc_reg_525_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_2212_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_523), - .init(pyc_comb_524), - .q(pyc_reg_525) + .en(pyc_comb_23), + .d(pyc_comb_2161), + .init(pyc_comb_16), + .q(pyc_reg_2212) ); -PYC_REG #(.WIDTH(2)) pyc_reg_532_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_2213_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_432), - .init(pyc_comb_15), - .q(pyc_reg_532) + .en(pyc_comb_23), + .d(pyc_comb_2179), + .init(pyc_comb_20), + .q(pyc_reg_2213) ); -PYC_REG #(.WIDTH(2)) pyc_reg_533_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_2214_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_434), - .init(pyc_comb_15), - .q(pyc_reg_533) + .en(pyc_comb_23), + .d(pe_int_s2_s2c1_hi__next), + .init(pyc_comb_20), + .q(pyc_reg_2214) ); -PYC_REG #(.WIDTH(2)) pyc_reg_534_inst ( +PYC_REG #(.WIDTH(16)) pyc_reg_2559_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_436), - .init(pyc_comb_15), - .q(pyc_reg_534) + .en(pyc_comb_23), + .d(pe_int_out1__next), + .init(pyc_comb_20), + .q(pyc_reg_2559) ); -PYC_REG #(.WIDTH(19)) pyc_reg_535_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_2564_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_s2_s2a__next), - .init(pyc_comb_14), - .q(pyc_reg_535) + .en(pyc_comb_23), + .d(pyc_comb_2193), + .init(pyc_comb_24), + .q(pyc_reg_2564) ); -PYC_REG #(.WIDTH(19)) pyc_reg_536_inst ( +PYC_REG #(.WIDTH(19)) pyc_reg_2565_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_s2_s2b0__next), - .init(pyc_comb_14), - .q(pyc_reg_536) + .en(pyc_comb_23), + .d(pyc_comb_2557), + .init(pyc_comb_16), + .q(pyc_reg_2565) ); -PYC_REG #(.WIDTH(16)) pyc_reg_537_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_35_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_s2_s2b1__next), - .init(pyc_comb_13), - .q(pyc_reg_537) + .en(pyc_comb_23), + .d(pyc_comb_31), + .init(pyc_comb_24), + .q(pyc_reg_35) ); -PYC_REG #(.WIDTH(19)) pyc_reg_538_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_37_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_s2_s2d0__next), - .init(pyc_comb_14), - .q(pyc_reg_538) + .en(pyc_comb_23), + .d(pyc_comb_32), + .init(pyc_comb_24), + .q(pyc_reg_37) ); -PYC_REG #(.WIDTH(16)) pyc_reg_539_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_39_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_s2_s2d1__next), - .init(pyc_comb_13), - .q(pyc_reg_539) + .en(pyc_comb_23), + .d(pyc_comb_33), + .init(pyc_comb_24), + .q(pyc_reg_39) ); -PYC_REG #(.WIDTH(19)) pyc_reg_540_inst ( +PYC_REG #(.WIDTH(1)) pyc_reg_41_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_s2_s2c0_lo__next), - .init(pyc_comb_14), - .q(pyc_reg_540) + .en(pyc_comb_23), + .d(pyc_comb_34), + .init(pyc_comb_24), + .q(pyc_reg_41) ); -PYC_REG #(.WIDTH(19)) pyc_reg_541_inst ( +PYC_REG #(.WIDTH(80)) pyc_reg_43_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_s2_s2c0_hi__next), - .init(pyc_comb_14), - .q(pyc_reg_541) + .en(pyc_comb_23), + .d(pyc_comb_30), + .init(pyc_comb_22), + .q(pyc_reg_43) ); -PYC_REG #(.WIDTH(16)) pyc_reg_542_inst ( +PYC_REG #(.WIDTH(80)) pyc_reg_44_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_s2_s2c1_lo__next), - .init(pyc_comb_13), - .q(pyc_reg_542) + .en(pyc_comb_23), + .d(pyc_comb_29), + .init(pyc_comb_22), + .q(pyc_reg_44) ); -PYC_REG #(.WIDTH(16)) pyc_reg_543_inst ( +PYC_REG #(.WIDTH(80)) pyc_reg_45_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_s2_s2c1_hi__next), - .init(pyc_comb_13), - .q(pyc_reg_543) + .en(pyc_comb_23), + .d(pyc_comb_28), + .init(pyc_comb_22), + .q(pyc_reg_45) ); -PYC_REG #(.WIDTH(16)) pyc_reg_593_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_46_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pe_int_out1__next), - .init(pyc_comb_13), - .q(pyc_reg_593) + .en(pyc_comb_23), + .d(pyc_comb_27), + .init(pyc_comb_21), + .q(pyc_reg_46) ); -PYC_REG #(.WIDTH(1)) pyc_reg_598_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_48_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_522), - .init(pyc_comb_18), - .q(pyc_reg_598) + .en(pyc_comb_23), + .d(pyc_comb_26), + .init(pyc_comb_21), + .q(pyc_reg_48) ); -PYC_REG #(.WIDTH(19)) pyc_reg_599_inst ( +PYC_REG #(.WIDTH(2)) pyc_reg_50_inst ( .clk(clk), .rst(rst), - .en(pyc_comb_17), - .d(pyc_comb_591), - .init(pyc_comb_14), - .q(pyc_reg_599) + .en(pyc_comb_23), + .d(pyc_comb_25), + .init(pyc_comb_21), + .q(pyc_reg_50) ); assign vld_out = pe_int_out_vld; assign out0 = pe_int_out0; -assign out1 = pyc_comb_596; +assign out1 = pyc_comb_2562; endmodule diff --git a/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w16.v b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w16.v index 40eb07e..9b59d72 100644 --- a/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w16.v +++ b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w16.v @@ -13,1516 +13,1680 @@ module PE_INT_WALLACE_DOT8_TREE_W16 ( output [15:0] PE_INT_WALLACE_DOT8_TREE_W16_sum ); -wire [15:0] pyc_add_752; // op=pyc.add -wire pyc_and_10; // op=pyc.and wire pyc_and_100; // op=pyc.and -wire pyc_and_101; // op=pyc.and -wire pyc_and_103; // op=pyc.and +wire pyc_and_102; // op=pyc.and +wire pyc_and_109; // op=pyc.and wire pyc_and_110; // op=pyc.and -wire pyc_and_111; // op=pyc.and -wire pyc_and_113; // op=pyc.and +wire pyc_and_112; // op=pyc.and +wire pyc_and_117; // op=pyc.and wire pyc_and_118; // op=pyc.and -wire pyc_and_119; // op=pyc.and -wire pyc_and_121; // op=pyc.and +wire pyc_and_120; // op=pyc.and +wire pyc_and_127; // op=pyc.and wire pyc_and_128; // op=pyc.and -wire pyc_and_129; // op=pyc.and -wire pyc_and_131; // op=pyc.and +wire pyc_and_13; // op=pyc.and +wire pyc_and_130; // op=pyc.and +wire pyc_and_135; // op=pyc.and wire pyc_and_136; // op=pyc.and -wire pyc_and_137; // op=pyc.and -wire pyc_and_139; // op=pyc.and -wire pyc_and_14; // op=pyc.and +wire pyc_and_138; // op=pyc.and +wire pyc_and_145; // op=pyc.and wire pyc_and_146; // op=pyc.and -wire pyc_and_147; // op=pyc.and -wire pyc_and_149; // op=pyc.and +wire pyc_and_148; // op=pyc.and +wire pyc_and_153; // op=pyc.and wire pyc_and_154; // op=pyc.and -wire pyc_and_155; // op=pyc.and -wire pyc_and_157; // op=pyc.and +wire pyc_and_156; // op=pyc.and +wire pyc_and_163; // op=pyc.and wire pyc_and_164; // op=pyc.and -wire pyc_and_165; // op=pyc.and -wire pyc_and_167; // op=pyc.and +wire pyc_and_166; // op=pyc.and +wire pyc_and_171; // op=pyc.and wire pyc_and_172; // op=pyc.and -wire pyc_and_173; // op=pyc.and -wire pyc_and_175; // op=pyc.and +wire pyc_and_174; // op=pyc.and +wire pyc_and_181; // op=pyc.and wire pyc_and_182; // op=pyc.and -wire pyc_and_183; // op=pyc.and -wire pyc_and_185; // op=pyc.and +wire pyc_and_184; // op=pyc.and +wire pyc_and_189; // op=pyc.and +wire pyc_and_19; // op=pyc.and wire pyc_and_190; // op=pyc.and -wire pyc_and_191; // op=pyc.and -wire pyc_and_193; // op=pyc.and +wire pyc_and_192; // op=pyc.and +wire pyc_and_199; // op=pyc.and wire pyc_and_20; // op=pyc.and wire pyc_and_200; // op=pyc.and -wire pyc_and_201; // op=pyc.and -wire pyc_and_203; // op=pyc.and +wire pyc_and_202; // op=pyc.and +wire pyc_and_207; // op=pyc.and wire pyc_and_208; // op=pyc.and -wire pyc_and_209; // op=pyc.and -wire pyc_and_21; // op=pyc.and -wire pyc_and_211; // op=pyc.and +wire pyc_and_210; // op=pyc.and +wire pyc_and_217; // op=pyc.and wire pyc_and_218; // op=pyc.and -wire pyc_and_219; // op=pyc.and -wire pyc_and_221; // op=pyc.and +wire pyc_and_22; // op=pyc.and +wire pyc_and_220; // op=pyc.and +wire pyc_and_225; // op=pyc.and wire pyc_and_226; // op=pyc.and -wire pyc_and_227; // op=pyc.and -wire pyc_and_229; // op=pyc.and -wire pyc_and_23; // op=pyc.and +wire pyc_and_228; // op=pyc.and +wire pyc_and_235; // op=pyc.and wire pyc_and_236; // op=pyc.and -wire pyc_and_237; // op=pyc.and -wire pyc_and_239; // op=pyc.and +wire pyc_and_238; // op=pyc.and +wire pyc_and_243; // op=pyc.and wire pyc_and_244; // op=pyc.and -wire pyc_and_245; // op=pyc.and -wire pyc_and_247; // op=pyc.and +wire pyc_and_246; // op=pyc.and +wire pyc_and_253; // op=pyc.and wire pyc_and_254; // op=pyc.and -wire pyc_and_255; // op=pyc.and -wire pyc_and_257; // op=pyc.and +wire pyc_and_256; // op=pyc.and +wire pyc_and_261; // op=pyc.and wire pyc_and_262; // op=pyc.and -wire pyc_and_263; // op=pyc.and -wire pyc_and_265; // op=pyc.and +wire pyc_and_264; // op=pyc.and +wire pyc_and_27; // op=pyc.and +wire pyc_and_279; // op=pyc.and wire pyc_and_28; // op=pyc.and wire pyc_and_280; // op=pyc.and -wire pyc_and_281; // op=pyc.and -wire pyc_and_283; // op=pyc.and -wire pyc_and_287; // op=pyc.and -wire pyc_and_29; // op=pyc.and +wire pyc_and_282; // op=pyc.and +wire pyc_and_286; // op=pyc.and +wire pyc_and_292; // op=pyc.and wire pyc_and_293; // op=pyc.and -wire pyc_and_294; // op=pyc.and -wire pyc_and_296; // op=pyc.and +wire pyc_and_295; // op=pyc.and +wire pyc_and_30; // op=pyc.and +wire pyc_and_300; // op=pyc.and wire pyc_and_301; // op=pyc.and -wire pyc_and_302; // op=pyc.and -wire pyc_and_304; // op=pyc.and -wire pyc_and_31; // op=pyc.and +wire pyc_and_303; // op=pyc.and +wire pyc_and_310; // op=pyc.and wire pyc_and_311; // op=pyc.and -wire pyc_and_312; // op=pyc.and -wire pyc_and_314; // op=pyc.and +wire pyc_and_313; // op=pyc.and +wire pyc_and_318; // op=pyc.and wire pyc_and_319; // op=pyc.and -wire pyc_and_320; // op=pyc.and -wire pyc_and_322; // op=pyc.and +wire pyc_and_321; // op=pyc.and +wire pyc_and_328; // op=pyc.and wire pyc_and_329; // op=pyc.and -wire pyc_and_330; // op=pyc.and -wire pyc_and_332; // op=pyc.and +wire pyc_and_331; // op=pyc.and +wire pyc_and_336; // op=pyc.and wire pyc_and_337; // op=pyc.and -wire pyc_and_338; // op=pyc.and -wire pyc_and_340; // op=pyc.and +wire pyc_and_339; // op=pyc.and +wire pyc_and_346; // op=pyc.and wire pyc_and_347; // op=pyc.and -wire pyc_and_348; // op=pyc.and -wire pyc_and_350; // op=pyc.and +wire pyc_and_349; // op=pyc.and +wire pyc_and_354; // op=pyc.and wire pyc_and_355; // op=pyc.and -wire pyc_and_356; // op=pyc.and -wire pyc_and_358; // op=pyc.and +wire pyc_and_357; // op=pyc.and +wire pyc_and_364; // op=pyc.and wire pyc_and_365; // op=pyc.and -wire pyc_and_366; // op=pyc.and -wire pyc_and_368; // op=pyc.and +wire pyc_and_367; // op=pyc.and +wire pyc_and_37; // op=pyc.and +wire pyc_and_372; // op=pyc.and wire pyc_and_373; // op=pyc.and -wire pyc_and_374; // op=pyc.and -wire pyc_and_376; // op=pyc.and +wire pyc_and_375; // op=pyc.and wire pyc_and_38; // op=pyc.and +wire pyc_and_382; // op=pyc.and wire pyc_and_383; // op=pyc.and -wire pyc_and_384; // op=pyc.and -wire pyc_and_386; // op=pyc.and -wire pyc_and_39; // op=pyc.and +wire pyc_and_385; // op=pyc.and +wire pyc_and_390; // op=pyc.and wire pyc_and_391; // op=pyc.and -wire pyc_and_392; // op=pyc.and -wire pyc_and_394; // op=pyc.and +wire pyc_and_393; // op=pyc.and +wire pyc_and_40; // op=pyc.and +wire pyc_and_400; // op=pyc.and wire pyc_and_401; // op=pyc.and -wire pyc_and_402; // op=pyc.and -wire pyc_and_404; // op=pyc.and +wire pyc_and_403; // op=pyc.and +wire pyc_and_408; // op=pyc.and wire pyc_and_409; // op=pyc.and -wire pyc_and_41; // op=pyc.and -wire pyc_and_410; // op=pyc.and -wire pyc_and_412; // op=pyc.and +wire pyc_and_411; // op=pyc.and +wire pyc_and_418; // op=pyc.and wire pyc_and_419; // op=pyc.and -wire pyc_and_420; // op=pyc.and -wire pyc_and_422; // op=pyc.and +wire pyc_and_421; // op=pyc.and +wire pyc_and_426; // op=pyc.and wire pyc_and_427; // op=pyc.and -wire pyc_and_428; // op=pyc.and -wire pyc_and_430; // op=pyc.and +wire pyc_and_429; // op=pyc.and +wire pyc_and_436; // op=pyc.and wire pyc_and_437; // op=pyc.and -wire pyc_and_438; // op=pyc.and -wire pyc_and_440; // op=pyc.and +wire pyc_and_439; // op=pyc.and +wire pyc_and_444; // op=pyc.and wire pyc_and_445; // op=pyc.and -wire pyc_and_446; // op=pyc.and -wire pyc_and_448; // op=pyc.and +wire pyc_and_447; // op=pyc.and +wire pyc_and_45; // op=pyc.and +wire pyc_and_454; // op=pyc.and wire pyc_and_455; // op=pyc.and -wire pyc_and_456; // op=pyc.and -wire pyc_and_458; // op=pyc.and +wire pyc_and_457; // op=pyc.and wire pyc_and_46; // op=pyc.and +wire pyc_and_462; // op=pyc.and wire pyc_and_463; // op=pyc.and -wire pyc_and_464; // op=pyc.and -wire pyc_and_466; // op=pyc.and -wire pyc_and_47; // op=pyc.and +wire pyc_and_465; // op=pyc.and +wire pyc_and_472; // op=pyc.and wire pyc_and_473; // op=pyc.and -wire pyc_and_474; // op=pyc.and -wire pyc_and_476; // op=pyc.and +wire pyc_and_475; // op=pyc.and +wire pyc_and_48; // op=pyc.and +wire pyc_and_480; // op=pyc.and wire pyc_and_481; // op=pyc.and -wire pyc_and_482; // op=pyc.and -wire pyc_and_484; // op=pyc.and -wire pyc_and_49; // op=pyc.and +wire pyc_and_483; // op=pyc.and +wire pyc_and_490; // op=pyc.and wire pyc_and_491; // op=pyc.and -wire pyc_and_492; // op=pyc.and -wire pyc_and_494; // op=pyc.and +wire pyc_and_493; // op=pyc.and +wire pyc_and_498; // op=pyc.and wire pyc_and_499; // op=pyc.and -wire pyc_and_500; // op=pyc.and -wire pyc_and_502; // op=pyc.and +wire pyc_and_501; // op=pyc.and +wire pyc_and_508; // op=pyc.and wire pyc_and_509; // op=pyc.and -wire pyc_and_510; // op=pyc.and -wire pyc_and_512; // op=pyc.and +wire pyc_and_511; // op=pyc.and +wire pyc_and_516; // op=pyc.and wire pyc_and_517; // op=pyc.and -wire pyc_and_518; // op=pyc.and -wire pyc_and_520; // op=pyc.and +wire pyc_and_519; // op=pyc.and +wire pyc_and_526; // op=pyc.and wire pyc_and_527; // op=pyc.and -wire pyc_and_528; // op=pyc.and -wire pyc_and_530; // op=pyc.and +wire pyc_and_529; // op=pyc.and +wire pyc_and_534; // op=pyc.and wire pyc_and_535; // op=pyc.and -wire pyc_and_536; // op=pyc.and -wire pyc_and_538; // op=pyc.and -wire pyc_and_549; // op=pyc.and +wire pyc_and_537; // op=pyc.and +wire pyc_and_548; // op=pyc.and +wire pyc_and_55; // op=pyc.and +wire pyc_and_551; // op=pyc.and wire pyc_and_552; // op=pyc.and -wire pyc_and_553; // op=pyc.and -wire pyc_and_555; // op=pyc.and +wire pyc_and_554; // op=pyc.and +wire pyc_and_558; // op=pyc.and wire pyc_and_559; // op=pyc.and wire pyc_and_56; // op=pyc.and -wire pyc_and_560; // op=pyc.and -wire pyc_and_562; // op=pyc.and +wire pyc_and_561; // op=pyc.and +wire pyc_and_565; // op=pyc.and wire pyc_and_566; // op=pyc.and -wire pyc_and_567; // op=pyc.and -wire pyc_and_569; // op=pyc.and -wire pyc_and_57; // op=pyc.and +wire pyc_and_568; // op=pyc.and +wire pyc_and_572; // op=pyc.and wire pyc_and_573; // op=pyc.and -wire pyc_and_574; // op=pyc.and -wire pyc_and_576; // op=pyc.and +wire pyc_and_575; // op=pyc.and +wire pyc_and_579; // op=pyc.and +wire pyc_and_58; // op=pyc.and wire pyc_and_580; // op=pyc.and -wire pyc_and_581; // op=pyc.and -wire pyc_and_583; // op=pyc.and +wire pyc_and_582; // op=pyc.and +wire pyc_and_586; // op=pyc.and wire pyc_and_587; // op=pyc.and -wire pyc_and_588; // op=pyc.and -wire pyc_and_59; // op=pyc.and -wire pyc_and_590; // op=pyc.and +wire pyc_and_589; // op=pyc.and +wire pyc_and_593; // op=pyc.and wire pyc_and_594; // op=pyc.and -wire pyc_and_595; // op=pyc.and -wire pyc_and_597; // op=pyc.and +wire pyc_and_596; // op=pyc.and +wire pyc_and_6; // op=pyc.and +wire pyc_and_600; // op=pyc.and wire pyc_and_601; // op=pyc.and -wire pyc_and_602; // op=pyc.and -wire pyc_and_604; // op=pyc.and +wire pyc_and_603; // op=pyc.and +wire pyc_and_607; // op=pyc.and wire pyc_and_608; // op=pyc.and -wire pyc_and_609; // op=pyc.and -wire pyc_and_611; // op=pyc.and +wire pyc_and_610; // op=pyc.and +wire pyc_and_614; // op=pyc.and wire pyc_and_615; // op=pyc.and -wire pyc_and_616; // op=pyc.and -wire pyc_and_618; // op=pyc.and +wire pyc_and_617; // op=pyc.and +wire pyc_and_621; // op=pyc.and wire pyc_and_622; // op=pyc.and -wire pyc_and_623; // op=pyc.and -wire pyc_and_625; // op=pyc.and +wire pyc_and_624; // op=pyc.and +wire pyc_and_628; // op=pyc.and wire pyc_and_629; // op=pyc.and -wire pyc_and_630; // op=pyc.and -wire pyc_and_632; // op=pyc.and +wire pyc_and_63; // op=pyc.and +wire pyc_and_631; // op=pyc.and +wire pyc_and_635; // op=pyc.and wire pyc_and_636; // op=pyc.and -wire pyc_and_637; // op=pyc.and -wire pyc_and_639; // op=pyc.and +wire pyc_and_638; // op=pyc.and wire pyc_and_64; // op=pyc.and +wire pyc_and_642; // op=pyc.and wire pyc_and_643; // op=pyc.and -wire pyc_and_644; // op=pyc.and -wire pyc_and_646; // op=pyc.and -wire pyc_and_65; // op=pyc.and +wire pyc_and_645; // op=pyc.and +wire pyc_and_649; // op=pyc.and wire pyc_and_650; // op=pyc.and -wire pyc_and_651; // op=pyc.and -wire pyc_and_653; // op=pyc.and +wire pyc_and_652; // op=pyc.and +wire pyc_and_656; // op=pyc.and wire pyc_and_657; // op=pyc.and -wire pyc_and_658; // op=pyc.and -wire pyc_and_660; // op=pyc.and +wire pyc_and_659; // op=pyc.and +wire pyc_and_66; // op=pyc.and +wire pyc_and_663; // op=pyc.and wire pyc_and_664; // op=pyc.and -wire pyc_and_665; // op=pyc.and -wire pyc_and_667; // op=pyc.and -wire pyc_and_67; // op=pyc.and +wire pyc_and_666; // op=pyc.and +wire pyc_and_670; // op=pyc.and wire pyc_and_671; // op=pyc.and -wire pyc_and_672; // op=pyc.and -wire pyc_and_674; // op=pyc.and +wire pyc_and_673; // op=pyc.and +wire pyc_and_677; // op=pyc.and wire pyc_and_678; // op=pyc.and -wire pyc_and_679; // op=pyc.and -wire pyc_and_681; // op=pyc.and +wire pyc_and_680; // op=pyc.and +wire pyc_and_684; // op=pyc.and wire pyc_and_685; // op=pyc.and -wire pyc_and_686; // op=pyc.and -wire pyc_and_688; // op=pyc.and +wire pyc_and_687; // op=pyc.and +wire pyc_and_691; // op=pyc.and wire pyc_and_692; // op=pyc.and -wire pyc_and_693; // op=pyc.and -wire pyc_and_695; // op=pyc.and +wire pyc_and_694; // op=pyc.and +wire pyc_and_698; // op=pyc.and wire pyc_and_699; // op=pyc.and wire pyc_and_7; // op=pyc.and -wire pyc_and_700; // op=pyc.and -wire pyc_and_702; // op=pyc.and +wire pyc_and_701; // op=pyc.and +wire pyc_and_705; // op=pyc.and wire pyc_and_706; // op=pyc.and -wire pyc_and_707; // op=pyc.and -wire pyc_and_709; // op=pyc.and +wire pyc_and_708; // op=pyc.and +wire pyc_and_712; // op=pyc.and wire pyc_and_713; // op=pyc.and -wire pyc_and_714; // op=pyc.and -wire pyc_and_716; // op=pyc.and +wire pyc_and_715; // op=pyc.and +wire pyc_and_719; // op=pyc.and wire pyc_and_720; // op=pyc.and -wire pyc_and_721; // op=pyc.and -wire pyc_and_723; // op=pyc.and +wire pyc_and_722; // op=pyc.and +wire pyc_and_726; // op=pyc.and wire pyc_and_727; // op=pyc.and -wire pyc_and_728; // op=pyc.and -wire pyc_and_730; // op=pyc.and +wire pyc_and_729; // op=pyc.and +wire pyc_and_73; // op=pyc.and +wire pyc_and_733; // op=pyc.and wire pyc_and_734; // op=pyc.and -wire pyc_and_735; // op=pyc.and -wire pyc_and_737; // op=pyc.and +wire pyc_and_736; // op=pyc.and wire pyc_and_74; // op=pyc.and +wire pyc_and_740; // op=pyc.and wire pyc_and_741; // op=pyc.and -wire pyc_and_742; // op=pyc.and -wire pyc_and_744; // op=pyc.and -wire pyc_and_75; // op=pyc.and -wire pyc_and_77; // op=pyc.and -wire pyc_and_8; // op=pyc.and +wire pyc_and_743; // op=pyc.and +wire pyc_and_76; // op=pyc.and +wire pyc_and_763; // op=pyc.and +wire pyc_and_764; // op=pyc.and +wire pyc_and_765; // op=pyc.and +wire pyc_and_766; // op=pyc.and +wire pyc_and_767; // op=pyc.and +wire pyc_and_768; // op=pyc.and +wire pyc_and_769; // op=pyc.and +wire pyc_and_770; // op=pyc.and +wire pyc_and_771; // op=pyc.and +wire pyc_and_772; // op=pyc.and +wire pyc_and_773; // op=pyc.and +wire pyc_and_774; // op=pyc.and +wire pyc_and_775; // op=pyc.and +wire pyc_and_776; // op=pyc.and +wire pyc_and_778; // op=pyc.and +wire pyc_and_780; // op=pyc.and +wire pyc_and_781; // op=pyc.and +wire pyc_and_783; // op=pyc.and +wire pyc_and_784; // op=pyc.and +wire pyc_and_786; // op=pyc.and +wire pyc_and_787; // op=pyc.and +wire pyc_and_789; // op=pyc.and +wire pyc_and_790; // op=pyc.and +wire pyc_and_792; // op=pyc.and +wire pyc_and_793; // op=pyc.and +wire pyc_and_795; // op=pyc.and +wire pyc_and_796; // op=pyc.and +wire pyc_and_798; // op=pyc.and +wire pyc_and_799; // op=pyc.and +wire pyc_and_801; // op=pyc.and +wire pyc_and_803; // op=pyc.and +wire pyc_and_805; // op=pyc.and +wire pyc_and_807; // op=pyc.and +wire pyc_and_809; // op=pyc.and +wire pyc_and_81; // op=pyc.and +wire pyc_and_811; // op=pyc.and +wire pyc_and_813; // op=pyc.and +wire pyc_and_815; // op=pyc.and +wire pyc_and_817; // op=pyc.and +wire pyc_and_819; // op=pyc.and wire pyc_and_82; // op=pyc.and -wire pyc_and_83; // op=pyc.and -wire pyc_and_85; // op=pyc.and +wire pyc_and_84; // op=pyc.and +wire pyc_and_9; // op=pyc.and +wire pyc_and_91; // op=pyc.and wire pyc_and_92; // op=pyc.and -wire pyc_and_93; // op=pyc.and -wire pyc_and_95; // op=pyc.and -wire [15:0] pyc_comb_753; // op=pyc.comb -wire [15:0] pyc_concat_750; // op=pyc.concat -wire [15:0] pyc_concat_751; // op=pyc.concat -wire pyc_constant_1; // op=pyc.constant +wire pyc_and_94; // op=pyc.and +wire pyc_and_99; // op=pyc.and +wire [15:0] pyc_comb_835; // op=pyc.comb +wire [15:0] pyc_concat_834; // op=pyc.concat +wire pyc_extract_1; // op=pyc.extract +wire pyc_extract_104; // op=pyc.extract wire pyc_extract_105; // op=pyc.extract wire pyc_extract_106; // op=pyc.extract -wire pyc_extract_107; // op=pyc.extract -wire pyc_extract_115; // op=pyc.extract -wire pyc_extract_12; // op=pyc.extract +wire pyc_extract_11; // op=pyc.extract +wire pyc_extract_114; // op=pyc.extract +wire pyc_extract_122; // op=pyc.extract wire pyc_extract_123; // op=pyc.extract wire pyc_extract_124; // op=pyc.extract -wire pyc_extract_125; // op=pyc.extract -wire pyc_extract_133; // op=pyc.extract +wire pyc_extract_132; // op=pyc.extract +wire pyc_extract_14; // op=pyc.extract +wire pyc_extract_140; // op=pyc.extract wire pyc_extract_141; // op=pyc.extract wire pyc_extract_142; // op=pyc.extract -wire pyc_extract_143; // op=pyc.extract wire pyc_extract_15; // op=pyc.extract -wire pyc_extract_151; // op=pyc.extract +wire pyc_extract_150; // op=pyc.extract +wire pyc_extract_158; // op=pyc.extract wire pyc_extract_159; // op=pyc.extract wire pyc_extract_16; // op=pyc.extract wire pyc_extract_160; // op=pyc.extract -wire pyc_extract_161; // op=pyc.extract -wire pyc_extract_169; // op=pyc.extract -wire pyc_extract_17; // op=pyc.extract +wire pyc_extract_168; // op=pyc.extract +wire pyc_extract_176; // op=pyc.extract wire pyc_extract_177; // op=pyc.extract wire pyc_extract_178; // op=pyc.extract -wire pyc_extract_179; // op=pyc.extract -wire pyc_extract_187; // op=pyc.extract +wire pyc_extract_186; // op=pyc.extract +wire pyc_extract_194; // op=pyc.extract wire pyc_extract_195; // op=pyc.extract wire pyc_extract_196; // op=pyc.extract -wire pyc_extract_197; // op=pyc.extract wire pyc_extract_2; // op=pyc.extract -wire pyc_extract_205; // op=pyc.extract +wire pyc_extract_204; // op=pyc.extract +wire pyc_extract_212; // op=pyc.extract wire pyc_extract_213; // op=pyc.extract wire pyc_extract_214; // op=pyc.extract -wire pyc_extract_215; // op=pyc.extract -wire pyc_extract_223; // op=pyc.extract +wire pyc_extract_222; // op=pyc.extract +wire pyc_extract_230; // op=pyc.extract wire pyc_extract_231; // op=pyc.extract wire pyc_extract_232; // op=pyc.extract -wire pyc_extract_233; // op=pyc.extract -wire pyc_extract_241; // op=pyc.extract +wire pyc_extract_24; // op=pyc.extract +wire pyc_extract_240; // op=pyc.extract +wire pyc_extract_248; // op=pyc.extract wire pyc_extract_249; // op=pyc.extract -wire pyc_extract_25; // op=pyc.extract wire pyc_extract_250; // op=pyc.extract -wire pyc_extract_251; // op=pyc.extract -wire pyc_extract_259; // op=pyc.extract +wire pyc_extract_258; // op=pyc.extract +wire pyc_extract_266; // op=pyc.extract wire pyc_extract_267; // op=pyc.extract wire pyc_extract_268; // op=pyc.extract -wire pyc_extract_269; // op=pyc.extract -wire pyc_extract_272; // op=pyc.extract +wire pyc_extract_271; // op=pyc.extract +wire pyc_extract_274; // op=pyc.extract wire pyc_extract_275; // op=pyc.extract wire pyc_extract_276; // op=pyc.extract -wire pyc_extract_277; // op=pyc.extract -wire pyc_extract_285; // op=pyc.extract +wire pyc_extract_284; // op=pyc.extract +wire pyc_extract_287; // op=pyc.extract wire pyc_extract_288; // op=pyc.extract wire pyc_extract_289; // op=pyc.extract -wire pyc_extract_290; // op=pyc.extract -wire pyc_extract_298; // op=pyc.extract +wire pyc_extract_297; // op=pyc.extract wire pyc_extract_3; // op=pyc.extract +wire pyc_extract_305; // op=pyc.extract wire pyc_extract_306; // op=pyc.extract wire pyc_extract_307; // op=pyc.extract -wire pyc_extract_308; // op=pyc.extract -wire pyc_extract_316; // op=pyc.extract +wire pyc_extract_315; // op=pyc.extract +wire pyc_extract_32; // op=pyc.extract +wire pyc_extract_323; // op=pyc.extract wire pyc_extract_324; // op=pyc.extract wire pyc_extract_325; // op=pyc.extract -wire pyc_extract_326; // op=pyc.extract wire pyc_extract_33; // op=pyc.extract -wire pyc_extract_334; // op=pyc.extract +wire pyc_extract_333; // op=pyc.extract wire pyc_extract_34; // op=pyc.extract +wire pyc_extract_341; // op=pyc.extract wire pyc_extract_342; // op=pyc.extract wire pyc_extract_343; // op=pyc.extract -wire pyc_extract_344; // op=pyc.extract -wire pyc_extract_35; // op=pyc.extract -wire pyc_extract_352; // op=pyc.extract +wire pyc_extract_351; // op=pyc.extract +wire pyc_extract_359; // op=pyc.extract wire pyc_extract_360; // op=pyc.extract wire pyc_extract_361; // op=pyc.extract -wire pyc_extract_362; // op=pyc.extract -wire pyc_extract_370; // op=pyc.extract +wire pyc_extract_369; // op=pyc.extract +wire pyc_extract_377; // op=pyc.extract wire pyc_extract_378; // op=pyc.extract wire pyc_extract_379; // op=pyc.extract -wire pyc_extract_380; // op=pyc.extract -wire pyc_extract_388; // op=pyc.extract +wire pyc_extract_387; // op=pyc.extract +wire pyc_extract_395; // op=pyc.extract wire pyc_extract_396; // op=pyc.extract wire pyc_extract_397; // op=pyc.extract -wire pyc_extract_398; // op=pyc.extract -wire pyc_extract_4; // op=pyc.extract -wire pyc_extract_406; // op=pyc.extract +wire pyc_extract_405; // op=pyc.extract +wire pyc_extract_413; // op=pyc.extract wire pyc_extract_414; // op=pyc.extract wire pyc_extract_415; // op=pyc.extract -wire pyc_extract_416; // op=pyc.extract -wire pyc_extract_424; // op=pyc.extract -wire pyc_extract_43; // op=pyc.extract +wire pyc_extract_42; // op=pyc.extract +wire pyc_extract_423; // op=pyc.extract +wire pyc_extract_431; // op=pyc.extract wire pyc_extract_432; // op=pyc.extract wire pyc_extract_433; // op=pyc.extract -wire pyc_extract_434; // op=pyc.extract -wire pyc_extract_442; // op=pyc.extract +wire pyc_extract_441; // op=pyc.extract +wire pyc_extract_449; // op=pyc.extract wire pyc_extract_450; // op=pyc.extract wire pyc_extract_451; // op=pyc.extract -wire pyc_extract_452; // op=pyc.extract -wire pyc_extract_460; // op=pyc.extract +wire pyc_extract_459; // op=pyc.extract +wire pyc_extract_467; // op=pyc.extract wire pyc_extract_468; // op=pyc.extract wire pyc_extract_469; // op=pyc.extract -wire pyc_extract_470; // op=pyc.extract -wire pyc_extract_478; // op=pyc.extract +wire pyc_extract_477; // op=pyc.extract +wire pyc_extract_485; // op=pyc.extract wire pyc_extract_486; // op=pyc.extract wire pyc_extract_487; // op=pyc.extract -wire pyc_extract_488; // op=pyc.extract -wire pyc_extract_496; // op=pyc.extract +wire pyc_extract_495; // op=pyc.extract +wire pyc_extract_50; // op=pyc.extract +wire pyc_extract_503; // op=pyc.extract wire pyc_extract_504; // op=pyc.extract wire pyc_extract_505; // op=pyc.extract -wire pyc_extract_506; // op=pyc.extract wire pyc_extract_51; // op=pyc.extract -wire pyc_extract_514; // op=pyc.extract +wire pyc_extract_513; // op=pyc.extract wire pyc_extract_52; // op=pyc.extract +wire pyc_extract_521; // op=pyc.extract wire pyc_extract_522; // op=pyc.extract wire pyc_extract_523; // op=pyc.extract -wire pyc_extract_524; // op=pyc.extract -wire pyc_extract_53; // op=pyc.extract -wire pyc_extract_532; // op=pyc.extract +wire pyc_extract_531; // op=pyc.extract +wire pyc_extract_539; // op=pyc.extract wire pyc_extract_540; // op=pyc.extract wire pyc_extract_541; // op=pyc.extract -wire pyc_extract_542; // op=pyc.extract -wire pyc_extract_545; // op=pyc.extract -wire pyc_extract_61; // op=pyc.extract +wire pyc_extract_544; // op=pyc.extract +wire pyc_extract_60; // op=pyc.extract +wire pyc_extract_68; // op=pyc.extract wire pyc_extract_69; // op=pyc.extract wire pyc_extract_70; // op=pyc.extract -wire pyc_extract_71; // op=pyc.extract -wire pyc_extract_79; // op=pyc.extract +wire pyc_extract_78; // op=pyc.extract +wire pyc_extract_86; // op=pyc.extract wire pyc_extract_87; // op=pyc.extract wire pyc_extract_88; // op=pyc.extract -wire pyc_extract_89; // op=pyc.extract -wire pyc_extract_97; // op=pyc.extract -wire pyc_or_102; // op=pyc.or -wire pyc_or_104; // op=pyc.or -wire pyc_or_11; // op=pyc.or -wire pyc_or_112; // op=pyc.or -wire pyc_or_114; // op=pyc.or -wire pyc_or_120; // op=pyc.or -wire pyc_or_122; // op=pyc.or -wire pyc_or_130; // op=pyc.or -wire pyc_or_132; // op=pyc.or -wire pyc_or_138; // op=pyc.or -wire pyc_or_140; // op=pyc.or -wire pyc_or_148; // op=pyc.or -wire pyc_or_150; // op=pyc.or -wire pyc_or_156; // op=pyc.or -wire pyc_or_158; // op=pyc.or -wire pyc_or_166; // op=pyc.or -wire pyc_or_168; // op=pyc.or -wire pyc_or_174; // op=pyc.or -wire pyc_or_176; // op=pyc.or -wire pyc_or_184; // op=pyc.or -wire pyc_or_186; // op=pyc.or -wire pyc_or_192; // op=pyc.or -wire pyc_or_194; // op=pyc.or -wire pyc_or_202; // op=pyc.or -wire pyc_or_204; // op=pyc.or -wire pyc_or_210; // op=pyc.or -wire pyc_or_212; // op=pyc.or -wire pyc_or_22; // op=pyc.or -wire pyc_or_220; // op=pyc.or -wire pyc_or_222; // op=pyc.or -wire pyc_or_228; // op=pyc.or -wire pyc_or_230; // op=pyc.or -wire pyc_or_238; // op=pyc.or -wire pyc_or_24; // op=pyc.or -wire pyc_or_240; // op=pyc.or -wire pyc_or_246; // op=pyc.or -wire pyc_or_248; // op=pyc.or -wire pyc_or_256; // op=pyc.or -wire pyc_or_258; // op=pyc.or -wire pyc_or_264; // op=pyc.or -wire pyc_or_266; // op=pyc.or -wire pyc_or_282; // op=pyc.or -wire pyc_or_284; // op=pyc.or -wire pyc_or_295; // op=pyc.or -wire pyc_or_297; // op=pyc.or -wire pyc_or_30; // op=pyc.or -wire pyc_or_303; // op=pyc.or -wire pyc_or_305; // op=pyc.or -wire pyc_or_313; // op=pyc.or -wire pyc_or_315; // op=pyc.or -wire pyc_or_32; // op=pyc.or -wire pyc_or_321; // op=pyc.or -wire pyc_or_323; // op=pyc.or -wire pyc_or_331; // op=pyc.or -wire pyc_or_333; // op=pyc.or -wire pyc_or_339; // op=pyc.or -wire pyc_or_341; // op=pyc.or -wire pyc_or_349; // op=pyc.or -wire pyc_or_351; // op=pyc.or -wire pyc_or_357; // op=pyc.or -wire pyc_or_359; // op=pyc.or -wire pyc_or_367; // op=pyc.or -wire pyc_or_369; // op=pyc.or -wire pyc_or_375; // op=pyc.or -wire pyc_or_377; // op=pyc.or -wire pyc_or_385; // op=pyc.or -wire pyc_or_387; // op=pyc.or -wire pyc_or_393; // op=pyc.or -wire pyc_or_395; // op=pyc.or -wire pyc_or_40; // op=pyc.or -wire pyc_or_403; // op=pyc.or -wire pyc_or_405; // op=pyc.or -wire pyc_or_411; // op=pyc.or -wire pyc_or_413; // op=pyc.or -wire pyc_or_42; // op=pyc.or -wire pyc_or_421; // op=pyc.or -wire pyc_or_423; // op=pyc.or -wire pyc_or_429; // op=pyc.or -wire pyc_or_431; // op=pyc.or -wire pyc_or_439; // op=pyc.or -wire pyc_or_441; // op=pyc.or -wire pyc_or_447; // op=pyc.or -wire pyc_or_449; // op=pyc.or -wire pyc_or_457; // op=pyc.or -wire pyc_or_459; // op=pyc.or -wire pyc_or_465; // op=pyc.or -wire pyc_or_467; // op=pyc.or -wire pyc_or_475; // op=pyc.or -wire pyc_or_477; // op=pyc.or -wire pyc_or_48; // op=pyc.or -wire pyc_or_483; // op=pyc.or -wire pyc_or_485; // op=pyc.or -wire pyc_or_493; // op=pyc.or -wire pyc_or_495; // op=pyc.or -wire pyc_or_50; // op=pyc.or -wire pyc_or_501; // op=pyc.or -wire pyc_or_503; // op=pyc.or -wire pyc_or_511; // op=pyc.or -wire pyc_or_513; // op=pyc.or -wire pyc_or_519; // op=pyc.or -wire pyc_or_521; // op=pyc.or -wire pyc_or_529; // op=pyc.or -wire pyc_or_531; // op=pyc.or -wire pyc_or_537; // op=pyc.or -wire pyc_or_539; // op=pyc.or -wire pyc_or_554; // op=pyc.or -wire pyc_or_556; // op=pyc.or -wire pyc_or_561; // op=pyc.or -wire pyc_or_563; // op=pyc.or -wire pyc_or_568; // op=pyc.or -wire pyc_or_570; // op=pyc.or -wire pyc_or_575; // op=pyc.or -wire pyc_or_577; // op=pyc.or -wire pyc_or_58; // op=pyc.or -wire pyc_or_582; // op=pyc.or -wire pyc_or_584; // op=pyc.or -wire pyc_or_589; // op=pyc.or -wire pyc_or_591; // op=pyc.or -wire pyc_or_596; // op=pyc.or -wire pyc_or_598; // op=pyc.or -wire pyc_or_60; // op=pyc.or -wire pyc_or_603; // op=pyc.or -wire pyc_or_605; // op=pyc.or -wire pyc_or_610; // op=pyc.or -wire pyc_or_612; // op=pyc.or -wire pyc_or_617; // op=pyc.or -wire pyc_or_619; // op=pyc.or -wire pyc_or_624; // op=pyc.or -wire pyc_or_626; // op=pyc.or -wire pyc_or_631; // op=pyc.or -wire pyc_or_633; // op=pyc.or -wire pyc_or_638; // op=pyc.or -wire pyc_or_640; // op=pyc.or -wire pyc_or_645; // op=pyc.or -wire pyc_or_647; // op=pyc.or -wire pyc_or_652; // op=pyc.or -wire pyc_or_654; // op=pyc.or -wire pyc_or_659; // op=pyc.or -wire pyc_or_66; // op=pyc.or -wire pyc_or_661; // op=pyc.or -wire pyc_or_666; // op=pyc.or -wire pyc_or_668; // op=pyc.or -wire pyc_or_673; // op=pyc.or -wire pyc_or_675; // op=pyc.or -wire pyc_or_68; // op=pyc.or -wire pyc_or_680; // op=pyc.or -wire pyc_or_682; // op=pyc.or -wire pyc_or_687; // op=pyc.or -wire pyc_or_689; // op=pyc.or -wire pyc_or_694; // op=pyc.or -wire pyc_or_696; // op=pyc.or -wire pyc_or_701; // op=pyc.or -wire pyc_or_703; // op=pyc.or -wire pyc_or_708; // op=pyc.or -wire pyc_or_710; // op=pyc.or -wire pyc_or_715; // op=pyc.or -wire pyc_or_717; // op=pyc.or -wire pyc_or_722; // op=pyc.or -wire pyc_or_724; // op=pyc.or -wire pyc_or_729; // op=pyc.or -wire pyc_or_731; // op=pyc.or -wire pyc_or_736; // op=pyc.or -wire pyc_or_738; // op=pyc.or -wire pyc_or_743; // op=pyc.or -wire pyc_or_745; // op=pyc.or -wire pyc_or_76; // op=pyc.or -wire pyc_or_78; // op=pyc.or -wire pyc_or_84; // op=pyc.or -wire pyc_or_86; // op=pyc.or -wire pyc_or_9; // op=pyc.or -wire pyc_or_94; // op=pyc.or -wire pyc_or_96; // op=pyc.or +wire pyc_extract_96; // op=pyc.extract +wire pyc_or_10; // op=pyc.or +wire pyc_or_101; // op=pyc.or +wire pyc_or_103; // op=pyc.or +wire pyc_or_111; // op=pyc.or +wire pyc_or_113; // op=pyc.or +wire pyc_or_119; // op=pyc.or +wire pyc_or_121; // op=pyc.or +wire pyc_or_129; // op=pyc.or +wire pyc_or_131; // op=pyc.or +wire pyc_or_137; // op=pyc.or +wire pyc_or_139; // op=pyc.or +wire pyc_or_147; // op=pyc.or +wire pyc_or_149; // op=pyc.or +wire pyc_or_155; // op=pyc.or +wire pyc_or_157; // op=pyc.or +wire pyc_or_165; // op=pyc.or +wire pyc_or_167; // op=pyc.or +wire pyc_or_173; // op=pyc.or +wire pyc_or_175; // op=pyc.or +wire pyc_or_183; // op=pyc.or +wire pyc_or_185; // op=pyc.or +wire pyc_or_191; // op=pyc.or +wire pyc_or_193; // op=pyc.or +wire pyc_or_201; // op=pyc.or +wire pyc_or_203; // op=pyc.or +wire pyc_or_209; // op=pyc.or +wire pyc_or_21; // op=pyc.or +wire pyc_or_211; // op=pyc.or +wire pyc_or_219; // op=pyc.or +wire pyc_or_221; // op=pyc.or +wire pyc_or_227; // op=pyc.or +wire pyc_or_229; // op=pyc.or +wire pyc_or_23; // op=pyc.or +wire pyc_or_237; // op=pyc.or +wire pyc_or_239; // op=pyc.or +wire pyc_or_245; // op=pyc.or +wire pyc_or_247; // op=pyc.or +wire pyc_or_255; // op=pyc.or +wire pyc_or_257; // op=pyc.or +wire pyc_or_263; // op=pyc.or +wire pyc_or_265; // op=pyc.or +wire pyc_or_281; // op=pyc.or +wire pyc_or_283; // op=pyc.or +wire pyc_or_29; // op=pyc.or +wire pyc_or_294; // op=pyc.or +wire pyc_or_296; // op=pyc.or +wire pyc_or_302; // op=pyc.or +wire pyc_or_304; // op=pyc.or +wire pyc_or_31; // op=pyc.or +wire pyc_or_312; // op=pyc.or +wire pyc_or_314; // op=pyc.or +wire pyc_or_320; // op=pyc.or +wire pyc_or_322; // op=pyc.or +wire pyc_or_330; // op=pyc.or +wire pyc_or_332; // op=pyc.or +wire pyc_or_338; // op=pyc.or +wire pyc_or_340; // op=pyc.or +wire pyc_or_348; // op=pyc.or +wire pyc_or_350; // op=pyc.or +wire pyc_or_356; // op=pyc.or +wire pyc_or_358; // op=pyc.or +wire pyc_or_366; // op=pyc.or +wire pyc_or_368; // op=pyc.or +wire pyc_or_374; // op=pyc.or +wire pyc_or_376; // op=pyc.or +wire pyc_or_384; // op=pyc.or +wire pyc_or_386; // op=pyc.or +wire pyc_or_39; // op=pyc.or +wire pyc_or_392; // op=pyc.or +wire pyc_or_394; // op=pyc.or +wire pyc_or_402; // op=pyc.or +wire pyc_or_404; // op=pyc.or +wire pyc_or_41; // op=pyc.or +wire pyc_or_410; // op=pyc.or +wire pyc_or_412; // op=pyc.or +wire pyc_or_420; // op=pyc.or +wire pyc_or_422; // op=pyc.or +wire pyc_or_428; // op=pyc.or +wire pyc_or_430; // op=pyc.or +wire pyc_or_438; // op=pyc.or +wire pyc_or_440; // op=pyc.or +wire pyc_or_446; // op=pyc.or +wire pyc_or_448; // op=pyc.or +wire pyc_or_456; // op=pyc.or +wire pyc_or_458; // op=pyc.or +wire pyc_or_464; // op=pyc.or +wire pyc_or_466; // op=pyc.or +wire pyc_or_47; // op=pyc.or +wire pyc_or_474; // op=pyc.or +wire pyc_or_476; // op=pyc.or +wire pyc_or_482; // op=pyc.or +wire pyc_or_484; // op=pyc.or +wire pyc_or_49; // op=pyc.or +wire pyc_or_492; // op=pyc.or +wire pyc_or_494; // op=pyc.or +wire pyc_or_500; // op=pyc.or +wire pyc_or_502; // op=pyc.or +wire pyc_or_510; // op=pyc.or +wire pyc_or_512; // op=pyc.or +wire pyc_or_518; // op=pyc.or +wire pyc_or_520; // op=pyc.or +wire pyc_or_528; // op=pyc.or +wire pyc_or_530; // op=pyc.or +wire pyc_or_536; // op=pyc.or +wire pyc_or_538; // op=pyc.or +wire pyc_or_553; // op=pyc.or +wire pyc_or_555; // op=pyc.or +wire pyc_or_560; // op=pyc.or +wire pyc_or_562; // op=pyc.or +wire pyc_or_567; // op=pyc.or +wire pyc_or_569; // op=pyc.or +wire pyc_or_57; // op=pyc.or +wire pyc_or_574; // op=pyc.or +wire pyc_or_576; // op=pyc.or +wire pyc_or_581; // op=pyc.or +wire pyc_or_583; // op=pyc.or +wire pyc_or_588; // op=pyc.or +wire pyc_or_59; // op=pyc.or +wire pyc_or_590; // op=pyc.or +wire pyc_or_595; // op=pyc.or +wire pyc_or_597; // op=pyc.or +wire pyc_or_602; // op=pyc.or +wire pyc_or_604; // op=pyc.or +wire pyc_or_609; // op=pyc.or +wire pyc_or_611; // op=pyc.or +wire pyc_or_616; // op=pyc.or +wire pyc_or_618; // op=pyc.or +wire pyc_or_623; // op=pyc.or +wire pyc_or_625; // op=pyc.or +wire pyc_or_630; // op=pyc.or +wire pyc_or_632; // op=pyc.or +wire pyc_or_637; // op=pyc.or +wire pyc_or_639; // op=pyc.or +wire pyc_or_644; // op=pyc.or +wire pyc_or_646; // op=pyc.or +wire pyc_or_65; // op=pyc.or +wire pyc_or_651; // op=pyc.or +wire pyc_or_653; // op=pyc.or +wire pyc_or_658; // op=pyc.or +wire pyc_or_660; // op=pyc.or +wire pyc_or_665; // op=pyc.or +wire pyc_or_667; // op=pyc.or +wire pyc_or_67; // op=pyc.or +wire pyc_or_672; // op=pyc.or +wire pyc_or_674; // op=pyc.or +wire pyc_or_679; // op=pyc.or +wire pyc_or_681; // op=pyc.or +wire pyc_or_686; // op=pyc.or +wire pyc_or_688; // op=pyc.or +wire pyc_or_693; // op=pyc.or +wire pyc_or_695; // op=pyc.or +wire pyc_or_700; // op=pyc.or +wire pyc_or_702; // op=pyc.or +wire pyc_or_707; // op=pyc.or +wire pyc_or_709; // op=pyc.or +wire pyc_or_714; // op=pyc.or +wire pyc_or_716; // op=pyc.or +wire pyc_or_721; // op=pyc.or +wire pyc_or_723; // op=pyc.or +wire pyc_or_728; // op=pyc.or +wire pyc_or_730; // op=pyc.or +wire pyc_or_735; // op=pyc.or +wire pyc_or_737; // op=pyc.or +wire pyc_or_742; // op=pyc.or +wire pyc_or_744; // op=pyc.or +wire pyc_or_75; // op=pyc.or +wire pyc_or_77; // op=pyc.or +wire pyc_or_777; // op=pyc.or +wire pyc_or_779; // op=pyc.or +wire pyc_or_782; // op=pyc.or +wire pyc_or_785; // op=pyc.or +wire pyc_or_788; // op=pyc.or +wire pyc_or_791; // op=pyc.or +wire pyc_or_794; // op=pyc.or +wire pyc_or_797; // op=pyc.or +wire pyc_or_8; // op=pyc.or +wire pyc_or_800; // op=pyc.or +wire pyc_or_802; // op=pyc.or +wire pyc_or_804; // op=pyc.or +wire pyc_or_806; // op=pyc.or +wire pyc_or_808; // op=pyc.or +wire pyc_or_810; // op=pyc.or +wire pyc_or_812; // op=pyc.or +wire pyc_or_814; // op=pyc.or +wire pyc_or_816; // op=pyc.or +wire pyc_or_818; // op=pyc.or +wire pyc_or_820; // op=pyc.or +wire pyc_or_83; // op=pyc.or +wire pyc_or_85; // op=pyc.or +wire pyc_or_93; // op=pyc.or +wire pyc_or_95; // op=pyc.or +wire pyc_xor_107; // op=pyc.xor wire pyc_xor_108; // op=pyc.xor -wire pyc_xor_109; // op=pyc.xor +wire pyc_xor_115; // op=pyc.xor wire pyc_xor_116; // op=pyc.xor -wire pyc_xor_117; // op=pyc.xor +wire pyc_xor_12; // op=pyc.xor +wire pyc_xor_125; // op=pyc.xor wire pyc_xor_126; // op=pyc.xor -wire pyc_xor_127; // op=pyc.xor -wire pyc_xor_13; // op=pyc.xor +wire pyc_xor_133; // op=pyc.xor wire pyc_xor_134; // op=pyc.xor -wire pyc_xor_135; // op=pyc.xor +wire pyc_xor_143; // op=pyc.xor wire pyc_xor_144; // op=pyc.xor -wire pyc_xor_145; // op=pyc.xor +wire pyc_xor_151; // op=pyc.xor wire pyc_xor_152; // op=pyc.xor -wire pyc_xor_153; // op=pyc.xor +wire pyc_xor_161; // op=pyc.xor wire pyc_xor_162; // op=pyc.xor -wire pyc_xor_163; // op=pyc.xor +wire pyc_xor_169; // op=pyc.xor +wire pyc_xor_17; // op=pyc.xor wire pyc_xor_170; // op=pyc.xor -wire pyc_xor_171; // op=pyc.xor +wire pyc_xor_179; // op=pyc.xor wire pyc_xor_18; // op=pyc.xor wire pyc_xor_180; // op=pyc.xor -wire pyc_xor_181; // op=pyc.xor +wire pyc_xor_187; // op=pyc.xor wire pyc_xor_188; // op=pyc.xor -wire pyc_xor_189; // op=pyc.xor -wire pyc_xor_19; // op=pyc.xor +wire pyc_xor_197; // op=pyc.xor wire pyc_xor_198; // op=pyc.xor -wire pyc_xor_199; // op=pyc.xor +wire pyc_xor_205; // op=pyc.xor wire pyc_xor_206; // op=pyc.xor -wire pyc_xor_207; // op=pyc.xor +wire pyc_xor_215; // op=pyc.xor wire pyc_xor_216; // op=pyc.xor -wire pyc_xor_217; // op=pyc.xor +wire pyc_xor_223; // op=pyc.xor wire pyc_xor_224; // op=pyc.xor -wire pyc_xor_225; // op=pyc.xor +wire pyc_xor_233; // op=pyc.xor wire pyc_xor_234; // op=pyc.xor -wire pyc_xor_235; // op=pyc.xor +wire pyc_xor_241; // op=pyc.xor wire pyc_xor_242; // op=pyc.xor -wire pyc_xor_243; // op=pyc.xor +wire pyc_xor_25; // op=pyc.xor +wire pyc_xor_251; // op=pyc.xor wire pyc_xor_252; // op=pyc.xor -wire pyc_xor_253; // op=pyc.xor +wire pyc_xor_259; // op=pyc.xor wire pyc_xor_26; // op=pyc.xor wire pyc_xor_260; // op=pyc.xor -wire pyc_xor_261; // op=pyc.xor -wire pyc_xor_27; // op=pyc.xor +wire pyc_xor_269; // op=pyc.xor wire pyc_xor_270; // op=pyc.xor -wire pyc_xor_271; // op=pyc.xor +wire pyc_xor_272; // op=pyc.xor wire pyc_xor_273; // op=pyc.xor -wire pyc_xor_274; // op=pyc.xor +wire pyc_xor_277; // op=pyc.xor wire pyc_xor_278; // op=pyc.xor -wire pyc_xor_279; // op=pyc.xor -wire pyc_xor_286; // op=pyc.xor +wire pyc_xor_285; // op=pyc.xor +wire pyc_xor_290; // op=pyc.xor wire pyc_xor_291; // op=pyc.xor -wire pyc_xor_292; // op=pyc.xor +wire pyc_xor_298; // op=pyc.xor wire pyc_xor_299; // op=pyc.xor -wire pyc_xor_300; // op=pyc.xor +wire pyc_xor_308; // op=pyc.xor wire pyc_xor_309; // op=pyc.xor -wire pyc_xor_310; // op=pyc.xor +wire pyc_xor_316; // op=pyc.xor wire pyc_xor_317; // op=pyc.xor -wire pyc_xor_318; // op=pyc.xor +wire pyc_xor_326; // op=pyc.xor wire pyc_xor_327; // op=pyc.xor -wire pyc_xor_328; // op=pyc.xor +wire pyc_xor_334; // op=pyc.xor wire pyc_xor_335; // op=pyc.xor -wire pyc_xor_336; // op=pyc.xor +wire pyc_xor_344; // op=pyc.xor wire pyc_xor_345; // op=pyc.xor -wire pyc_xor_346; // op=pyc.xor +wire pyc_xor_35; // op=pyc.xor +wire pyc_xor_352; // op=pyc.xor wire pyc_xor_353; // op=pyc.xor -wire pyc_xor_354; // op=pyc.xor wire pyc_xor_36; // op=pyc.xor +wire pyc_xor_362; // op=pyc.xor wire pyc_xor_363; // op=pyc.xor -wire pyc_xor_364; // op=pyc.xor -wire pyc_xor_37; // op=pyc.xor +wire pyc_xor_370; // op=pyc.xor wire pyc_xor_371; // op=pyc.xor -wire pyc_xor_372; // op=pyc.xor +wire pyc_xor_380; // op=pyc.xor wire pyc_xor_381; // op=pyc.xor -wire pyc_xor_382; // op=pyc.xor +wire pyc_xor_388; // op=pyc.xor wire pyc_xor_389; // op=pyc.xor -wire pyc_xor_390; // op=pyc.xor +wire pyc_xor_398; // op=pyc.xor wire pyc_xor_399; // op=pyc.xor -wire pyc_xor_400; // op=pyc.xor +wire pyc_xor_4; // op=pyc.xor +wire pyc_xor_406; // op=pyc.xor wire pyc_xor_407; // op=pyc.xor -wire pyc_xor_408; // op=pyc.xor +wire pyc_xor_416; // op=pyc.xor wire pyc_xor_417; // op=pyc.xor -wire pyc_xor_418; // op=pyc.xor +wire pyc_xor_424; // op=pyc.xor wire pyc_xor_425; // op=pyc.xor -wire pyc_xor_426; // op=pyc.xor +wire pyc_xor_43; // op=pyc.xor +wire pyc_xor_434; // op=pyc.xor wire pyc_xor_435; // op=pyc.xor -wire pyc_xor_436; // op=pyc.xor wire pyc_xor_44; // op=pyc.xor +wire pyc_xor_442; // op=pyc.xor wire pyc_xor_443; // op=pyc.xor -wire pyc_xor_444; // op=pyc.xor -wire pyc_xor_45; // op=pyc.xor +wire pyc_xor_452; // op=pyc.xor wire pyc_xor_453; // op=pyc.xor -wire pyc_xor_454; // op=pyc.xor +wire pyc_xor_460; // op=pyc.xor wire pyc_xor_461; // op=pyc.xor -wire pyc_xor_462; // op=pyc.xor +wire pyc_xor_470; // op=pyc.xor wire pyc_xor_471; // op=pyc.xor -wire pyc_xor_472; // op=pyc.xor +wire pyc_xor_478; // op=pyc.xor wire pyc_xor_479; // op=pyc.xor -wire pyc_xor_480; // op=pyc.xor +wire pyc_xor_488; // op=pyc.xor wire pyc_xor_489; // op=pyc.xor -wire pyc_xor_490; // op=pyc.xor +wire pyc_xor_496; // op=pyc.xor wire pyc_xor_497; // op=pyc.xor -wire pyc_xor_498; // op=pyc.xor wire pyc_xor_5; // op=pyc.xor +wire pyc_xor_506; // op=pyc.xor wire pyc_xor_507; // op=pyc.xor -wire pyc_xor_508; // op=pyc.xor +wire pyc_xor_514; // op=pyc.xor wire pyc_xor_515; // op=pyc.xor -wire pyc_xor_516; // op=pyc.xor +wire pyc_xor_524; // op=pyc.xor wire pyc_xor_525; // op=pyc.xor -wire pyc_xor_526; // op=pyc.xor +wire pyc_xor_53; // op=pyc.xor +wire pyc_xor_532; // op=pyc.xor wire pyc_xor_533; // op=pyc.xor -wire pyc_xor_534; // op=pyc.xor wire pyc_xor_54; // op=pyc.xor +wire pyc_xor_542; // op=pyc.xor wire pyc_xor_543; // op=pyc.xor -wire pyc_xor_544; // op=pyc.xor +wire pyc_xor_545; // op=pyc.xor wire pyc_xor_546; // op=pyc.xor wire pyc_xor_547; // op=pyc.xor -wire pyc_xor_548; // op=pyc.xor -wire pyc_xor_55; // op=pyc.xor +wire pyc_xor_549; // op=pyc.xor wire pyc_xor_550; // op=pyc.xor -wire pyc_xor_551; // op=pyc.xor +wire pyc_xor_556; // op=pyc.xor wire pyc_xor_557; // op=pyc.xor -wire pyc_xor_558; // op=pyc.xor +wire pyc_xor_563; // op=pyc.xor wire pyc_xor_564; // op=pyc.xor -wire pyc_xor_565; // op=pyc.xor +wire pyc_xor_570; // op=pyc.xor wire pyc_xor_571; // op=pyc.xor -wire pyc_xor_572; // op=pyc.xor +wire pyc_xor_577; // op=pyc.xor wire pyc_xor_578; // op=pyc.xor -wire pyc_xor_579; // op=pyc.xor +wire pyc_xor_584; // op=pyc.xor wire pyc_xor_585; // op=pyc.xor -wire pyc_xor_586; // op=pyc.xor +wire pyc_xor_591; // op=pyc.xor wire pyc_xor_592; // op=pyc.xor -wire pyc_xor_593; // op=pyc.xor +wire pyc_xor_598; // op=pyc.xor wire pyc_xor_599; // op=pyc.xor -wire pyc_xor_6; // op=pyc.xor -wire pyc_xor_600; // op=pyc.xor +wire pyc_xor_605; // op=pyc.xor wire pyc_xor_606; // op=pyc.xor -wire pyc_xor_607; // op=pyc.xor +wire pyc_xor_61; // op=pyc.xor +wire pyc_xor_612; // op=pyc.xor wire pyc_xor_613; // op=pyc.xor -wire pyc_xor_614; // op=pyc.xor +wire pyc_xor_619; // op=pyc.xor wire pyc_xor_62; // op=pyc.xor wire pyc_xor_620; // op=pyc.xor -wire pyc_xor_621; // op=pyc.xor +wire pyc_xor_626; // op=pyc.xor wire pyc_xor_627; // op=pyc.xor -wire pyc_xor_628; // op=pyc.xor -wire pyc_xor_63; // op=pyc.xor +wire pyc_xor_633; // op=pyc.xor wire pyc_xor_634; // op=pyc.xor -wire pyc_xor_635; // op=pyc.xor +wire pyc_xor_640; // op=pyc.xor wire pyc_xor_641; // op=pyc.xor -wire pyc_xor_642; // op=pyc.xor +wire pyc_xor_647; // op=pyc.xor wire pyc_xor_648; // op=pyc.xor -wire pyc_xor_649; // op=pyc.xor +wire pyc_xor_654; // op=pyc.xor wire pyc_xor_655; // op=pyc.xor -wire pyc_xor_656; // op=pyc.xor +wire pyc_xor_661; // op=pyc.xor wire pyc_xor_662; // op=pyc.xor -wire pyc_xor_663; // op=pyc.xor +wire pyc_xor_668; // op=pyc.xor wire pyc_xor_669; // op=pyc.xor -wire pyc_xor_670; // op=pyc.xor +wire pyc_xor_675; // op=pyc.xor wire pyc_xor_676; // op=pyc.xor -wire pyc_xor_677; // op=pyc.xor +wire pyc_xor_682; // op=pyc.xor wire pyc_xor_683; // op=pyc.xor -wire pyc_xor_684; // op=pyc.xor +wire pyc_xor_689; // op=pyc.xor wire pyc_xor_690; // op=pyc.xor -wire pyc_xor_691; // op=pyc.xor +wire pyc_xor_696; // op=pyc.xor wire pyc_xor_697; // op=pyc.xor -wire pyc_xor_698; // op=pyc.xor +wire pyc_xor_703; // op=pyc.xor wire pyc_xor_704; // op=pyc.xor -wire pyc_xor_705; // op=pyc.xor +wire pyc_xor_71; // op=pyc.xor +wire pyc_xor_710; // op=pyc.xor wire pyc_xor_711; // op=pyc.xor -wire pyc_xor_712; // op=pyc.xor +wire pyc_xor_717; // op=pyc.xor wire pyc_xor_718; // op=pyc.xor -wire pyc_xor_719; // op=pyc.xor wire pyc_xor_72; // op=pyc.xor +wire pyc_xor_724; // op=pyc.xor wire pyc_xor_725; // op=pyc.xor -wire pyc_xor_726; // op=pyc.xor -wire pyc_xor_73; // op=pyc.xor +wire pyc_xor_731; // op=pyc.xor wire pyc_xor_732; // op=pyc.xor -wire pyc_xor_733; // op=pyc.xor +wire pyc_xor_738; // op=pyc.xor wire pyc_xor_739; // op=pyc.xor -wire pyc_xor_740; // op=pyc.xor +wire pyc_xor_745; // op=pyc.xor wire pyc_xor_746; // op=pyc.xor wire pyc_xor_747; // op=pyc.xor wire pyc_xor_748; // op=pyc.xor wire pyc_xor_749; // op=pyc.xor +wire pyc_xor_750; // op=pyc.xor +wire pyc_xor_751; // op=pyc.xor +wire pyc_xor_752; // op=pyc.xor +wire pyc_xor_753; // op=pyc.xor +wire pyc_xor_754; // op=pyc.xor +wire pyc_xor_755; // op=pyc.xor +wire pyc_xor_756; // op=pyc.xor +wire pyc_xor_757; // op=pyc.xor +wire pyc_xor_758; // op=pyc.xor +wire pyc_xor_759; // op=pyc.xor +wire pyc_xor_760; // op=pyc.xor +wire pyc_xor_761; // op=pyc.xor +wire pyc_xor_762; // op=pyc.xor +wire pyc_xor_79; // op=pyc.xor wire pyc_xor_80; // op=pyc.xor -wire pyc_xor_81; // op=pyc.xor +wire pyc_xor_821; // op=pyc.xor +wire pyc_xor_822; // op=pyc.xor +wire pyc_xor_823; // op=pyc.xor +wire pyc_xor_824; // op=pyc.xor +wire pyc_xor_825; // op=pyc.xor +wire pyc_xor_826; // op=pyc.xor +wire pyc_xor_827; // op=pyc.xor +wire pyc_xor_828; // op=pyc.xor +wire pyc_xor_829; // op=pyc.xor +wire pyc_xor_830; // op=pyc.xor +wire pyc_xor_831; // op=pyc.xor +wire pyc_xor_832; // op=pyc.xor +wire pyc_xor_833; // op=pyc.xor +wire pyc_xor_89; // op=pyc.xor wire pyc_xor_90; // op=pyc.xor -wire pyc_xor_91; // op=pyc.xor +wire pyc_xor_97; // op=pyc.xor wire pyc_xor_98; // op=pyc.xor -wire pyc_xor_99; // op=pyc.xor // --- Combinational (netlist) -assign pyc_constant_1 = 1'd0; -assign pyc_extract_2 = PE_INT_WALLACE_DOT8_TREE_W16_in0[0]; -assign pyc_extract_3 = PE_INT_WALLACE_DOT8_TREE_W16_in1[0]; -assign pyc_extract_4 = PE_INT_WALLACE_DOT8_TREE_W16_in2[0]; -assign pyc_xor_5 = (pyc_extract_2 ^ pyc_extract_3); -assign pyc_xor_6 = (pyc_xor_5 ^ pyc_extract_4); -assign pyc_and_7 = (pyc_extract_2 & pyc_extract_3); -assign pyc_and_8 = (pyc_extract_2 & pyc_extract_4); -assign pyc_or_9 = (pyc_and_7 | pyc_and_8); -assign pyc_and_10 = (pyc_extract_3 & pyc_extract_4); -assign pyc_or_11 = (pyc_or_9 | pyc_and_10); -assign pyc_extract_12 = PE_INT_WALLACE_DOT8_TREE_W16_in3[0]; -assign pyc_xor_13 = (pyc_xor_6 ^ pyc_extract_12); -assign pyc_and_14 = (pyc_xor_6 & pyc_extract_12); -assign pyc_extract_15 = PE_INT_WALLACE_DOT8_TREE_W16_in0[1]; -assign pyc_extract_16 = PE_INT_WALLACE_DOT8_TREE_W16_in1[1]; -assign pyc_extract_17 = PE_INT_WALLACE_DOT8_TREE_W16_in2[1]; -assign pyc_xor_18 = (pyc_extract_15 ^ pyc_extract_16); -assign pyc_xor_19 = (pyc_xor_18 ^ pyc_extract_17); -assign pyc_and_20 = (pyc_extract_15 & pyc_extract_16); -assign pyc_and_21 = (pyc_extract_15 & pyc_extract_17); -assign pyc_or_22 = (pyc_and_20 | pyc_and_21); -assign pyc_and_23 = (pyc_extract_16 & pyc_extract_17); -assign pyc_or_24 = (pyc_or_22 | pyc_and_23); -assign pyc_extract_25 = PE_INT_WALLACE_DOT8_TREE_W16_in3[1]; -assign pyc_xor_26 = (pyc_xor_19 ^ pyc_extract_25); -assign pyc_xor_27 = (pyc_xor_26 ^ pyc_or_11); -assign pyc_and_28 = (pyc_xor_19 & pyc_extract_25); -assign pyc_and_29 = (pyc_xor_19 & pyc_or_11); -assign pyc_or_30 = (pyc_and_28 | pyc_and_29); -assign pyc_and_31 = (pyc_extract_25 & pyc_or_11); -assign pyc_or_32 = (pyc_or_30 | pyc_and_31); -assign pyc_extract_33 = PE_INT_WALLACE_DOT8_TREE_W16_in0[2]; -assign pyc_extract_34 = PE_INT_WALLACE_DOT8_TREE_W16_in1[2]; -assign pyc_extract_35 = PE_INT_WALLACE_DOT8_TREE_W16_in2[2]; -assign pyc_xor_36 = (pyc_extract_33 ^ pyc_extract_34); -assign pyc_xor_37 = (pyc_xor_36 ^ pyc_extract_35); -assign pyc_and_38 = (pyc_extract_33 & pyc_extract_34); -assign pyc_and_39 = (pyc_extract_33 & pyc_extract_35); -assign pyc_or_40 = (pyc_and_38 | pyc_and_39); -assign pyc_and_41 = (pyc_extract_34 & pyc_extract_35); -assign pyc_or_42 = (pyc_or_40 | pyc_and_41); -assign pyc_extract_43 = PE_INT_WALLACE_DOT8_TREE_W16_in3[2]; -assign pyc_xor_44 = (pyc_xor_37 ^ pyc_extract_43); -assign pyc_xor_45 = (pyc_xor_44 ^ pyc_or_24); -assign pyc_and_46 = (pyc_xor_37 & pyc_extract_43); -assign pyc_and_47 = (pyc_xor_37 & pyc_or_24); -assign pyc_or_48 = (pyc_and_46 | pyc_and_47); -assign pyc_and_49 = (pyc_extract_43 & pyc_or_24); -assign pyc_or_50 = (pyc_or_48 | pyc_and_49); -assign pyc_extract_51 = PE_INT_WALLACE_DOT8_TREE_W16_in0[3]; -assign pyc_extract_52 = PE_INT_WALLACE_DOT8_TREE_W16_in1[3]; -assign pyc_extract_53 = PE_INT_WALLACE_DOT8_TREE_W16_in2[3]; -assign pyc_xor_54 = (pyc_extract_51 ^ pyc_extract_52); -assign pyc_xor_55 = (pyc_xor_54 ^ pyc_extract_53); -assign pyc_and_56 = (pyc_extract_51 & pyc_extract_52); -assign pyc_and_57 = (pyc_extract_51 & pyc_extract_53); -assign pyc_or_58 = (pyc_and_56 | pyc_and_57); -assign pyc_and_59 = (pyc_extract_52 & pyc_extract_53); -assign pyc_or_60 = (pyc_or_58 | pyc_and_59); -assign pyc_extract_61 = PE_INT_WALLACE_DOT8_TREE_W16_in3[3]; -assign pyc_xor_62 = (pyc_xor_55 ^ pyc_extract_61); -assign pyc_xor_63 = (pyc_xor_62 ^ pyc_or_42); -assign pyc_and_64 = (pyc_xor_55 & pyc_extract_61); -assign pyc_and_65 = (pyc_xor_55 & pyc_or_42); -assign pyc_or_66 = (pyc_and_64 | pyc_and_65); -assign pyc_and_67 = (pyc_extract_61 & pyc_or_42); -assign pyc_or_68 = (pyc_or_66 | pyc_and_67); -assign pyc_extract_69 = PE_INT_WALLACE_DOT8_TREE_W16_in0[4]; -assign pyc_extract_70 = PE_INT_WALLACE_DOT8_TREE_W16_in1[4]; -assign pyc_extract_71 = PE_INT_WALLACE_DOT8_TREE_W16_in2[4]; -assign pyc_xor_72 = (pyc_extract_69 ^ pyc_extract_70); -assign pyc_xor_73 = (pyc_xor_72 ^ pyc_extract_71); -assign pyc_and_74 = (pyc_extract_69 & pyc_extract_70); -assign pyc_and_75 = (pyc_extract_69 & pyc_extract_71); -assign pyc_or_76 = (pyc_and_74 | pyc_and_75); -assign pyc_and_77 = (pyc_extract_70 & pyc_extract_71); -assign pyc_or_78 = (pyc_or_76 | pyc_and_77); -assign pyc_extract_79 = PE_INT_WALLACE_DOT8_TREE_W16_in3[4]; -assign pyc_xor_80 = (pyc_xor_73 ^ pyc_extract_79); -assign pyc_xor_81 = (pyc_xor_80 ^ pyc_or_60); -assign pyc_and_82 = (pyc_xor_73 & pyc_extract_79); -assign pyc_and_83 = (pyc_xor_73 & pyc_or_60); -assign pyc_or_84 = (pyc_and_82 | pyc_and_83); -assign pyc_and_85 = (pyc_extract_79 & pyc_or_60); -assign pyc_or_86 = (pyc_or_84 | pyc_and_85); -assign pyc_extract_87 = PE_INT_WALLACE_DOT8_TREE_W16_in0[5]; -assign pyc_extract_88 = PE_INT_WALLACE_DOT8_TREE_W16_in1[5]; -assign pyc_extract_89 = PE_INT_WALLACE_DOT8_TREE_W16_in2[5]; -assign pyc_xor_90 = (pyc_extract_87 ^ pyc_extract_88); -assign pyc_xor_91 = (pyc_xor_90 ^ pyc_extract_89); -assign pyc_and_92 = (pyc_extract_87 & pyc_extract_88); -assign pyc_and_93 = (pyc_extract_87 & pyc_extract_89); -assign pyc_or_94 = (pyc_and_92 | pyc_and_93); -assign pyc_and_95 = (pyc_extract_88 & pyc_extract_89); -assign pyc_or_96 = (pyc_or_94 | pyc_and_95); -assign pyc_extract_97 = PE_INT_WALLACE_DOT8_TREE_W16_in3[5]; -assign pyc_xor_98 = (pyc_xor_91 ^ pyc_extract_97); -assign pyc_xor_99 = (pyc_xor_98 ^ pyc_or_78); -assign pyc_and_100 = (pyc_xor_91 & pyc_extract_97); -assign pyc_and_101 = (pyc_xor_91 & pyc_or_78); -assign pyc_or_102 = (pyc_and_100 | pyc_and_101); -assign pyc_and_103 = (pyc_extract_97 & pyc_or_78); -assign pyc_or_104 = (pyc_or_102 | pyc_and_103); -assign pyc_extract_105 = PE_INT_WALLACE_DOT8_TREE_W16_in0[6]; -assign pyc_extract_106 = PE_INT_WALLACE_DOT8_TREE_W16_in1[6]; -assign pyc_extract_107 = PE_INT_WALLACE_DOT8_TREE_W16_in2[6]; -assign pyc_xor_108 = (pyc_extract_105 ^ pyc_extract_106); -assign pyc_xor_109 = (pyc_xor_108 ^ pyc_extract_107); -assign pyc_and_110 = (pyc_extract_105 & pyc_extract_106); -assign pyc_and_111 = (pyc_extract_105 & pyc_extract_107); -assign pyc_or_112 = (pyc_and_110 | pyc_and_111); -assign pyc_and_113 = (pyc_extract_106 & pyc_extract_107); -assign pyc_or_114 = (pyc_or_112 | pyc_and_113); -assign pyc_extract_115 = PE_INT_WALLACE_DOT8_TREE_W16_in3[6]; -assign pyc_xor_116 = (pyc_xor_109 ^ pyc_extract_115); -assign pyc_xor_117 = (pyc_xor_116 ^ pyc_or_96); -assign pyc_and_118 = (pyc_xor_109 & pyc_extract_115); -assign pyc_and_119 = (pyc_xor_109 & pyc_or_96); -assign pyc_or_120 = (pyc_and_118 | pyc_and_119); -assign pyc_and_121 = (pyc_extract_115 & pyc_or_96); -assign pyc_or_122 = (pyc_or_120 | pyc_and_121); -assign pyc_extract_123 = PE_INT_WALLACE_DOT8_TREE_W16_in0[7]; -assign pyc_extract_124 = PE_INT_WALLACE_DOT8_TREE_W16_in1[7]; -assign pyc_extract_125 = PE_INT_WALLACE_DOT8_TREE_W16_in2[7]; -assign pyc_xor_126 = (pyc_extract_123 ^ pyc_extract_124); -assign pyc_xor_127 = (pyc_xor_126 ^ pyc_extract_125); -assign pyc_and_128 = (pyc_extract_123 & pyc_extract_124); -assign pyc_and_129 = (pyc_extract_123 & pyc_extract_125); -assign pyc_or_130 = (pyc_and_128 | pyc_and_129); -assign pyc_and_131 = (pyc_extract_124 & pyc_extract_125); -assign pyc_or_132 = (pyc_or_130 | pyc_and_131); -assign pyc_extract_133 = PE_INT_WALLACE_DOT8_TREE_W16_in3[7]; -assign pyc_xor_134 = (pyc_xor_127 ^ pyc_extract_133); -assign pyc_xor_135 = (pyc_xor_134 ^ pyc_or_114); -assign pyc_and_136 = (pyc_xor_127 & pyc_extract_133); -assign pyc_and_137 = (pyc_xor_127 & pyc_or_114); -assign pyc_or_138 = (pyc_and_136 | pyc_and_137); -assign pyc_and_139 = (pyc_extract_133 & pyc_or_114); -assign pyc_or_140 = (pyc_or_138 | pyc_and_139); -assign pyc_extract_141 = PE_INT_WALLACE_DOT8_TREE_W16_in0[8]; -assign pyc_extract_142 = PE_INT_WALLACE_DOT8_TREE_W16_in1[8]; -assign pyc_extract_143 = PE_INT_WALLACE_DOT8_TREE_W16_in2[8]; -assign pyc_xor_144 = (pyc_extract_141 ^ pyc_extract_142); -assign pyc_xor_145 = (pyc_xor_144 ^ pyc_extract_143); -assign pyc_and_146 = (pyc_extract_141 & pyc_extract_142); -assign pyc_and_147 = (pyc_extract_141 & pyc_extract_143); -assign pyc_or_148 = (pyc_and_146 | pyc_and_147); -assign pyc_and_149 = (pyc_extract_142 & pyc_extract_143); -assign pyc_or_150 = (pyc_or_148 | pyc_and_149); -assign pyc_extract_151 = PE_INT_WALLACE_DOT8_TREE_W16_in3[8]; -assign pyc_xor_152 = (pyc_xor_145 ^ pyc_extract_151); -assign pyc_xor_153 = (pyc_xor_152 ^ pyc_or_132); -assign pyc_and_154 = (pyc_xor_145 & pyc_extract_151); -assign pyc_and_155 = (pyc_xor_145 & pyc_or_132); -assign pyc_or_156 = (pyc_and_154 | pyc_and_155); -assign pyc_and_157 = (pyc_extract_151 & pyc_or_132); -assign pyc_or_158 = (pyc_or_156 | pyc_and_157); -assign pyc_extract_159 = PE_INT_WALLACE_DOT8_TREE_W16_in0[9]; -assign pyc_extract_160 = PE_INT_WALLACE_DOT8_TREE_W16_in1[9]; -assign pyc_extract_161 = PE_INT_WALLACE_DOT8_TREE_W16_in2[9]; -assign pyc_xor_162 = (pyc_extract_159 ^ pyc_extract_160); -assign pyc_xor_163 = (pyc_xor_162 ^ pyc_extract_161); -assign pyc_and_164 = (pyc_extract_159 & pyc_extract_160); -assign pyc_and_165 = (pyc_extract_159 & pyc_extract_161); -assign pyc_or_166 = (pyc_and_164 | pyc_and_165); -assign pyc_and_167 = (pyc_extract_160 & pyc_extract_161); -assign pyc_or_168 = (pyc_or_166 | pyc_and_167); -assign pyc_extract_169 = PE_INT_WALLACE_DOT8_TREE_W16_in3[9]; -assign pyc_xor_170 = (pyc_xor_163 ^ pyc_extract_169); -assign pyc_xor_171 = (pyc_xor_170 ^ pyc_or_150); -assign pyc_and_172 = (pyc_xor_163 & pyc_extract_169); -assign pyc_and_173 = (pyc_xor_163 & pyc_or_150); -assign pyc_or_174 = (pyc_and_172 | pyc_and_173); -assign pyc_and_175 = (pyc_extract_169 & pyc_or_150); -assign pyc_or_176 = (pyc_or_174 | pyc_and_175); -assign pyc_extract_177 = PE_INT_WALLACE_DOT8_TREE_W16_in0[10]; -assign pyc_extract_178 = PE_INT_WALLACE_DOT8_TREE_W16_in1[10]; -assign pyc_extract_179 = PE_INT_WALLACE_DOT8_TREE_W16_in2[10]; -assign pyc_xor_180 = (pyc_extract_177 ^ pyc_extract_178); -assign pyc_xor_181 = (pyc_xor_180 ^ pyc_extract_179); -assign pyc_and_182 = (pyc_extract_177 & pyc_extract_178); -assign pyc_and_183 = (pyc_extract_177 & pyc_extract_179); -assign pyc_or_184 = (pyc_and_182 | pyc_and_183); -assign pyc_and_185 = (pyc_extract_178 & pyc_extract_179); -assign pyc_or_186 = (pyc_or_184 | pyc_and_185); -assign pyc_extract_187 = PE_INT_WALLACE_DOT8_TREE_W16_in3[10]; -assign pyc_xor_188 = (pyc_xor_181 ^ pyc_extract_187); -assign pyc_xor_189 = (pyc_xor_188 ^ pyc_or_168); -assign pyc_and_190 = (pyc_xor_181 & pyc_extract_187); -assign pyc_and_191 = (pyc_xor_181 & pyc_or_168); -assign pyc_or_192 = (pyc_and_190 | pyc_and_191); -assign pyc_and_193 = (pyc_extract_187 & pyc_or_168); -assign pyc_or_194 = (pyc_or_192 | pyc_and_193); -assign pyc_extract_195 = PE_INT_WALLACE_DOT8_TREE_W16_in0[11]; -assign pyc_extract_196 = PE_INT_WALLACE_DOT8_TREE_W16_in1[11]; -assign pyc_extract_197 = PE_INT_WALLACE_DOT8_TREE_W16_in2[11]; -assign pyc_xor_198 = (pyc_extract_195 ^ pyc_extract_196); -assign pyc_xor_199 = (pyc_xor_198 ^ pyc_extract_197); -assign pyc_and_200 = (pyc_extract_195 & pyc_extract_196); -assign pyc_and_201 = (pyc_extract_195 & pyc_extract_197); -assign pyc_or_202 = (pyc_and_200 | pyc_and_201); -assign pyc_and_203 = (pyc_extract_196 & pyc_extract_197); -assign pyc_or_204 = (pyc_or_202 | pyc_and_203); -assign pyc_extract_205 = PE_INT_WALLACE_DOT8_TREE_W16_in3[11]; -assign pyc_xor_206 = (pyc_xor_199 ^ pyc_extract_205); -assign pyc_xor_207 = (pyc_xor_206 ^ pyc_or_186); -assign pyc_and_208 = (pyc_xor_199 & pyc_extract_205); -assign pyc_and_209 = (pyc_xor_199 & pyc_or_186); -assign pyc_or_210 = (pyc_and_208 | pyc_and_209); -assign pyc_and_211 = (pyc_extract_205 & pyc_or_186); -assign pyc_or_212 = (pyc_or_210 | pyc_and_211); -assign pyc_extract_213 = PE_INT_WALLACE_DOT8_TREE_W16_in0[12]; -assign pyc_extract_214 = PE_INT_WALLACE_DOT8_TREE_W16_in1[12]; -assign pyc_extract_215 = PE_INT_WALLACE_DOT8_TREE_W16_in2[12]; -assign pyc_xor_216 = (pyc_extract_213 ^ pyc_extract_214); -assign pyc_xor_217 = (pyc_xor_216 ^ pyc_extract_215); -assign pyc_and_218 = (pyc_extract_213 & pyc_extract_214); -assign pyc_and_219 = (pyc_extract_213 & pyc_extract_215); -assign pyc_or_220 = (pyc_and_218 | pyc_and_219); -assign pyc_and_221 = (pyc_extract_214 & pyc_extract_215); -assign pyc_or_222 = (pyc_or_220 | pyc_and_221); -assign pyc_extract_223 = PE_INT_WALLACE_DOT8_TREE_W16_in3[12]; -assign pyc_xor_224 = (pyc_xor_217 ^ pyc_extract_223); -assign pyc_xor_225 = (pyc_xor_224 ^ pyc_or_204); -assign pyc_and_226 = (pyc_xor_217 & pyc_extract_223); -assign pyc_and_227 = (pyc_xor_217 & pyc_or_204); -assign pyc_or_228 = (pyc_and_226 | pyc_and_227); -assign pyc_and_229 = (pyc_extract_223 & pyc_or_204); -assign pyc_or_230 = (pyc_or_228 | pyc_and_229); -assign pyc_extract_231 = PE_INT_WALLACE_DOT8_TREE_W16_in0[13]; -assign pyc_extract_232 = PE_INT_WALLACE_DOT8_TREE_W16_in1[13]; -assign pyc_extract_233 = PE_INT_WALLACE_DOT8_TREE_W16_in2[13]; -assign pyc_xor_234 = (pyc_extract_231 ^ pyc_extract_232); -assign pyc_xor_235 = (pyc_xor_234 ^ pyc_extract_233); -assign pyc_and_236 = (pyc_extract_231 & pyc_extract_232); -assign pyc_and_237 = (pyc_extract_231 & pyc_extract_233); -assign pyc_or_238 = (pyc_and_236 | pyc_and_237); -assign pyc_and_239 = (pyc_extract_232 & pyc_extract_233); -assign pyc_or_240 = (pyc_or_238 | pyc_and_239); -assign pyc_extract_241 = PE_INT_WALLACE_DOT8_TREE_W16_in3[13]; -assign pyc_xor_242 = (pyc_xor_235 ^ pyc_extract_241); -assign pyc_xor_243 = (pyc_xor_242 ^ pyc_or_222); -assign pyc_and_244 = (pyc_xor_235 & pyc_extract_241); -assign pyc_and_245 = (pyc_xor_235 & pyc_or_222); -assign pyc_or_246 = (pyc_and_244 | pyc_and_245); -assign pyc_and_247 = (pyc_extract_241 & pyc_or_222); -assign pyc_or_248 = (pyc_or_246 | pyc_and_247); -assign pyc_extract_249 = PE_INT_WALLACE_DOT8_TREE_W16_in0[14]; -assign pyc_extract_250 = PE_INT_WALLACE_DOT8_TREE_W16_in1[14]; -assign pyc_extract_251 = PE_INT_WALLACE_DOT8_TREE_W16_in2[14]; -assign pyc_xor_252 = (pyc_extract_249 ^ pyc_extract_250); -assign pyc_xor_253 = (pyc_xor_252 ^ pyc_extract_251); -assign pyc_and_254 = (pyc_extract_249 & pyc_extract_250); -assign pyc_and_255 = (pyc_extract_249 & pyc_extract_251); -assign pyc_or_256 = (pyc_and_254 | pyc_and_255); -assign pyc_and_257 = (pyc_extract_250 & pyc_extract_251); -assign pyc_or_258 = (pyc_or_256 | pyc_and_257); -assign pyc_extract_259 = PE_INT_WALLACE_DOT8_TREE_W16_in3[14]; -assign pyc_xor_260 = (pyc_xor_253 ^ pyc_extract_259); -assign pyc_xor_261 = (pyc_xor_260 ^ pyc_or_240); -assign pyc_and_262 = (pyc_xor_253 & pyc_extract_259); -assign pyc_and_263 = (pyc_xor_253 & pyc_or_240); -assign pyc_or_264 = (pyc_and_262 | pyc_and_263); -assign pyc_and_265 = (pyc_extract_259 & pyc_or_240); -assign pyc_or_266 = (pyc_or_264 | pyc_and_265); -assign pyc_extract_267 = PE_INT_WALLACE_DOT8_TREE_W16_in0[15]; -assign pyc_extract_268 = PE_INT_WALLACE_DOT8_TREE_W16_in1[15]; -assign pyc_extract_269 = PE_INT_WALLACE_DOT8_TREE_W16_in2[15]; -assign pyc_xor_270 = (pyc_extract_267 ^ pyc_extract_268); -assign pyc_xor_271 = (pyc_xor_270 ^ pyc_extract_269); -assign pyc_extract_272 = PE_INT_WALLACE_DOT8_TREE_W16_in3[15]; -assign pyc_xor_273 = (pyc_xor_271 ^ pyc_extract_272); -assign pyc_xor_274 = (pyc_xor_273 ^ pyc_or_258); -assign pyc_extract_275 = PE_INT_WALLACE_DOT8_TREE_W16_in4[0]; -assign pyc_extract_276 = PE_INT_WALLACE_DOT8_TREE_W16_in5[0]; -assign pyc_extract_277 = PE_INT_WALLACE_DOT8_TREE_W16_in6[0]; -assign pyc_xor_278 = (pyc_extract_275 ^ pyc_extract_276); -assign pyc_xor_279 = (pyc_xor_278 ^ pyc_extract_277); -assign pyc_and_280 = (pyc_extract_275 & pyc_extract_276); -assign pyc_and_281 = (pyc_extract_275 & pyc_extract_277); -assign pyc_or_282 = (pyc_and_280 | pyc_and_281); -assign pyc_and_283 = (pyc_extract_276 & pyc_extract_277); -assign pyc_or_284 = (pyc_or_282 | pyc_and_283); -assign pyc_extract_285 = PE_INT_WALLACE_DOT8_TREE_W16_in7[0]; -assign pyc_xor_286 = (pyc_xor_279 ^ pyc_extract_285); -assign pyc_and_287 = (pyc_xor_279 & pyc_extract_285); -assign pyc_extract_288 = PE_INT_WALLACE_DOT8_TREE_W16_in4[1]; -assign pyc_extract_289 = PE_INT_WALLACE_DOT8_TREE_W16_in5[1]; -assign pyc_extract_290 = PE_INT_WALLACE_DOT8_TREE_W16_in6[1]; -assign pyc_xor_291 = (pyc_extract_288 ^ pyc_extract_289); -assign pyc_xor_292 = (pyc_xor_291 ^ pyc_extract_290); -assign pyc_and_293 = (pyc_extract_288 & pyc_extract_289); -assign pyc_and_294 = (pyc_extract_288 & pyc_extract_290); -assign pyc_or_295 = (pyc_and_293 | pyc_and_294); -assign pyc_and_296 = (pyc_extract_289 & pyc_extract_290); -assign pyc_or_297 = (pyc_or_295 | pyc_and_296); -assign pyc_extract_298 = PE_INT_WALLACE_DOT8_TREE_W16_in7[1]; -assign pyc_xor_299 = (pyc_xor_292 ^ pyc_extract_298); -assign pyc_xor_300 = (pyc_xor_299 ^ pyc_or_284); -assign pyc_and_301 = (pyc_xor_292 & pyc_extract_298); -assign pyc_and_302 = (pyc_xor_292 & pyc_or_284); -assign pyc_or_303 = (pyc_and_301 | pyc_and_302); -assign pyc_and_304 = (pyc_extract_298 & pyc_or_284); -assign pyc_or_305 = (pyc_or_303 | pyc_and_304); -assign pyc_extract_306 = PE_INT_WALLACE_DOT8_TREE_W16_in4[2]; -assign pyc_extract_307 = PE_INT_WALLACE_DOT8_TREE_W16_in5[2]; -assign pyc_extract_308 = PE_INT_WALLACE_DOT8_TREE_W16_in6[2]; -assign pyc_xor_309 = (pyc_extract_306 ^ pyc_extract_307); -assign pyc_xor_310 = (pyc_xor_309 ^ pyc_extract_308); -assign pyc_and_311 = (pyc_extract_306 & pyc_extract_307); -assign pyc_and_312 = (pyc_extract_306 & pyc_extract_308); -assign pyc_or_313 = (pyc_and_311 | pyc_and_312); -assign pyc_and_314 = (pyc_extract_307 & pyc_extract_308); -assign pyc_or_315 = (pyc_or_313 | pyc_and_314); -assign pyc_extract_316 = PE_INT_WALLACE_DOT8_TREE_W16_in7[2]; -assign pyc_xor_317 = (pyc_xor_310 ^ pyc_extract_316); -assign pyc_xor_318 = (pyc_xor_317 ^ pyc_or_297); -assign pyc_and_319 = (pyc_xor_310 & pyc_extract_316); -assign pyc_and_320 = (pyc_xor_310 & pyc_or_297); -assign pyc_or_321 = (pyc_and_319 | pyc_and_320); -assign pyc_and_322 = (pyc_extract_316 & pyc_or_297); -assign pyc_or_323 = (pyc_or_321 | pyc_and_322); -assign pyc_extract_324 = PE_INT_WALLACE_DOT8_TREE_W16_in4[3]; -assign pyc_extract_325 = PE_INT_WALLACE_DOT8_TREE_W16_in5[3]; -assign pyc_extract_326 = PE_INT_WALLACE_DOT8_TREE_W16_in6[3]; -assign pyc_xor_327 = (pyc_extract_324 ^ pyc_extract_325); -assign pyc_xor_328 = (pyc_xor_327 ^ pyc_extract_326); -assign pyc_and_329 = (pyc_extract_324 & pyc_extract_325); -assign pyc_and_330 = (pyc_extract_324 & pyc_extract_326); -assign pyc_or_331 = (pyc_and_329 | pyc_and_330); -assign pyc_and_332 = (pyc_extract_325 & pyc_extract_326); -assign pyc_or_333 = (pyc_or_331 | pyc_and_332); -assign pyc_extract_334 = PE_INT_WALLACE_DOT8_TREE_W16_in7[3]; -assign pyc_xor_335 = (pyc_xor_328 ^ pyc_extract_334); -assign pyc_xor_336 = (pyc_xor_335 ^ pyc_or_315); -assign pyc_and_337 = (pyc_xor_328 & pyc_extract_334); -assign pyc_and_338 = (pyc_xor_328 & pyc_or_315); -assign pyc_or_339 = (pyc_and_337 | pyc_and_338); -assign pyc_and_340 = (pyc_extract_334 & pyc_or_315); -assign pyc_or_341 = (pyc_or_339 | pyc_and_340); -assign pyc_extract_342 = PE_INT_WALLACE_DOT8_TREE_W16_in4[4]; -assign pyc_extract_343 = PE_INT_WALLACE_DOT8_TREE_W16_in5[4]; -assign pyc_extract_344 = PE_INT_WALLACE_DOT8_TREE_W16_in6[4]; -assign pyc_xor_345 = (pyc_extract_342 ^ pyc_extract_343); -assign pyc_xor_346 = (pyc_xor_345 ^ pyc_extract_344); -assign pyc_and_347 = (pyc_extract_342 & pyc_extract_343); -assign pyc_and_348 = (pyc_extract_342 & pyc_extract_344); -assign pyc_or_349 = (pyc_and_347 | pyc_and_348); -assign pyc_and_350 = (pyc_extract_343 & pyc_extract_344); -assign pyc_or_351 = (pyc_or_349 | pyc_and_350); -assign pyc_extract_352 = PE_INT_WALLACE_DOT8_TREE_W16_in7[4]; -assign pyc_xor_353 = (pyc_xor_346 ^ pyc_extract_352); -assign pyc_xor_354 = (pyc_xor_353 ^ pyc_or_333); -assign pyc_and_355 = (pyc_xor_346 & pyc_extract_352); -assign pyc_and_356 = (pyc_xor_346 & pyc_or_333); -assign pyc_or_357 = (pyc_and_355 | pyc_and_356); -assign pyc_and_358 = (pyc_extract_352 & pyc_or_333); -assign pyc_or_359 = (pyc_or_357 | pyc_and_358); -assign pyc_extract_360 = PE_INT_WALLACE_DOT8_TREE_W16_in4[5]; -assign pyc_extract_361 = PE_INT_WALLACE_DOT8_TREE_W16_in5[5]; -assign pyc_extract_362 = PE_INT_WALLACE_DOT8_TREE_W16_in6[5]; -assign pyc_xor_363 = (pyc_extract_360 ^ pyc_extract_361); -assign pyc_xor_364 = (pyc_xor_363 ^ pyc_extract_362); -assign pyc_and_365 = (pyc_extract_360 & pyc_extract_361); -assign pyc_and_366 = (pyc_extract_360 & pyc_extract_362); -assign pyc_or_367 = (pyc_and_365 | pyc_and_366); -assign pyc_and_368 = (pyc_extract_361 & pyc_extract_362); -assign pyc_or_369 = (pyc_or_367 | pyc_and_368); -assign pyc_extract_370 = PE_INT_WALLACE_DOT8_TREE_W16_in7[5]; -assign pyc_xor_371 = (pyc_xor_364 ^ pyc_extract_370); -assign pyc_xor_372 = (pyc_xor_371 ^ pyc_or_351); -assign pyc_and_373 = (pyc_xor_364 & pyc_extract_370); -assign pyc_and_374 = (pyc_xor_364 & pyc_or_351); -assign pyc_or_375 = (pyc_and_373 | pyc_and_374); -assign pyc_and_376 = (pyc_extract_370 & pyc_or_351); -assign pyc_or_377 = (pyc_or_375 | pyc_and_376); -assign pyc_extract_378 = PE_INT_WALLACE_DOT8_TREE_W16_in4[6]; -assign pyc_extract_379 = PE_INT_WALLACE_DOT8_TREE_W16_in5[6]; -assign pyc_extract_380 = PE_INT_WALLACE_DOT8_TREE_W16_in6[6]; -assign pyc_xor_381 = (pyc_extract_378 ^ pyc_extract_379); -assign pyc_xor_382 = (pyc_xor_381 ^ pyc_extract_380); -assign pyc_and_383 = (pyc_extract_378 & pyc_extract_379); -assign pyc_and_384 = (pyc_extract_378 & pyc_extract_380); -assign pyc_or_385 = (pyc_and_383 | pyc_and_384); -assign pyc_and_386 = (pyc_extract_379 & pyc_extract_380); -assign pyc_or_387 = (pyc_or_385 | pyc_and_386); -assign pyc_extract_388 = PE_INT_WALLACE_DOT8_TREE_W16_in7[6]; -assign pyc_xor_389 = (pyc_xor_382 ^ pyc_extract_388); -assign pyc_xor_390 = (pyc_xor_389 ^ pyc_or_369); -assign pyc_and_391 = (pyc_xor_382 & pyc_extract_388); -assign pyc_and_392 = (pyc_xor_382 & pyc_or_369); -assign pyc_or_393 = (pyc_and_391 | pyc_and_392); -assign pyc_and_394 = (pyc_extract_388 & pyc_or_369); -assign pyc_or_395 = (pyc_or_393 | pyc_and_394); -assign pyc_extract_396 = PE_INT_WALLACE_DOT8_TREE_W16_in4[7]; -assign pyc_extract_397 = PE_INT_WALLACE_DOT8_TREE_W16_in5[7]; -assign pyc_extract_398 = PE_INT_WALLACE_DOT8_TREE_W16_in6[7]; -assign pyc_xor_399 = (pyc_extract_396 ^ pyc_extract_397); -assign pyc_xor_400 = (pyc_xor_399 ^ pyc_extract_398); -assign pyc_and_401 = (pyc_extract_396 & pyc_extract_397); -assign pyc_and_402 = (pyc_extract_396 & pyc_extract_398); -assign pyc_or_403 = (pyc_and_401 | pyc_and_402); -assign pyc_and_404 = (pyc_extract_397 & pyc_extract_398); -assign pyc_or_405 = (pyc_or_403 | pyc_and_404); -assign pyc_extract_406 = PE_INT_WALLACE_DOT8_TREE_W16_in7[7]; -assign pyc_xor_407 = (pyc_xor_400 ^ pyc_extract_406); -assign pyc_xor_408 = (pyc_xor_407 ^ pyc_or_387); -assign pyc_and_409 = (pyc_xor_400 & pyc_extract_406); -assign pyc_and_410 = (pyc_xor_400 & pyc_or_387); -assign pyc_or_411 = (pyc_and_409 | pyc_and_410); -assign pyc_and_412 = (pyc_extract_406 & pyc_or_387); -assign pyc_or_413 = (pyc_or_411 | pyc_and_412); -assign pyc_extract_414 = PE_INT_WALLACE_DOT8_TREE_W16_in4[8]; -assign pyc_extract_415 = PE_INT_WALLACE_DOT8_TREE_W16_in5[8]; -assign pyc_extract_416 = PE_INT_WALLACE_DOT8_TREE_W16_in6[8]; -assign pyc_xor_417 = (pyc_extract_414 ^ pyc_extract_415); -assign pyc_xor_418 = (pyc_xor_417 ^ pyc_extract_416); -assign pyc_and_419 = (pyc_extract_414 & pyc_extract_415); -assign pyc_and_420 = (pyc_extract_414 & pyc_extract_416); -assign pyc_or_421 = (pyc_and_419 | pyc_and_420); -assign pyc_and_422 = (pyc_extract_415 & pyc_extract_416); -assign pyc_or_423 = (pyc_or_421 | pyc_and_422); -assign pyc_extract_424 = PE_INT_WALLACE_DOT8_TREE_W16_in7[8]; -assign pyc_xor_425 = (pyc_xor_418 ^ pyc_extract_424); -assign pyc_xor_426 = (pyc_xor_425 ^ pyc_or_405); -assign pyc_and_427 = (pyc_xor_418 & pyc_extract_424); -assign pyc_and_428 = (pyc_xor_418 & pyc_or_405); -assign pyc_or_429 = (pyc_and_427 | pyc_and_428); -assign pyc_and_430 = (pyc_extract_424 & pyc_or_405); -assign pyc_or_431 = (pyc_or_429 | pyc_and_430); -assign pyc_extract_432 = PE_INT_WALLACE_DOT8_TREE_W16_in4[9]; -assign pyc_extract_433 = PE_INT_WALLACE_DOT8_TREE_W16_in5[9]; -assign pyc_extract_434 = PE_INT_WALLACE_DOT8_TREE_W16_in6[9]; -assign pyc_xor_435 = (pyc_extract_432 ^ pyc_extract_433); -assign pyc_xor_436 = (pyc_xor_435 ^ pyc_extract_434); -assign pyc_and_437 = (pyc_extract_432 & pyc_extract_433); -assign pyc_and_438 = (pyc_extract_432 & pyc_extract_434); -assign pyc_or_439 = (pyc_and_437 | pyc_and_438); -assign pyc_and_440 = (pyc_extract_433 & pyc_extract_434); -assign pyc_or_441 = (pyc_or_439 | pyc_and_440); -assign pyc_extract_442 = PE_INT_WALLACE_DOT8_TREE_W16_in7[9]; -assign pyc_xor_443 = (pyc_xor_436 ^ pyc_extract_442); -assign pyc_xor_444 = (pyc_xor_443 ^ pyc_or_423); -assign pyc_and_445 = (pyc_xor_436 & pyc_extract_442); -assign pyc_and_446 = (pyc_xor_436 & pyc_or_423); -assign pyc_or_447 = (pyc_and_445 | pyc_and_446); -assign pyc_and_448 = (pyc_extract_442 & pyc_or_423); -assign pyc_or_449 = (pyc_or_447 | pyc_and_448); -assign pyc_extract_450 = PE_INT_WALLACE_DOT8_TREE_W16_in4[10]; -assign pyc_extract_451 = PE_INT_WALLACE_DOT8_TREE_W16_in5[10]; -assign pyc_extract_452 = PE_INT_WALLACE_DOT8_TREE_W16_in6[10]; -assign pyc_xor_453 = (pyc_extract_450 ^ pyc_extract_451); -assign pyc_xor_454 = (pyc_xor_453 ^ pyc_extract_452); -assign pyc_and_455 = (pyc_extract_450 & pyc_extract_451); -assign pyc_and_456 = (pyc_extract_450 & pyc_extract_452); -assign pyc_or_457 = (pyc_and_455 | pyc_and_456); -assign pyc_and_458 = (pyc_extract_451 & pyc_extract_452); -assign pyc_or_459 = (pyc_or_457 | pyc_and_458); -assign pyc_extract_460 = PE_INT_WALLACE_DOT8_TREE_W16_in7[10]; -assign pyc_xor_461 = (pyc_xor_454 ^ pyc_extract_460); -assign pyc_xor_462 = (pyc_xor_461 ^ pyc_or_441); -assign pyc_and_463 = (pyc_xor_454 & pyc_extract_460); -assign pyc_and_464 = (pyc_xor_454 & pyc_or_441); -assign pyc_or_465 = (pyc_and_463 | pyc_and_464); -assign pyc_and_466 = (pyc_extract_460 & pyc_or_441); -assign pyc_or_467 = (pyc_or_465 | pyc_and_466); -assign pyc_extract_468 = PE_INT_WALLACE_DOT8_TREE_W16_in4[11]; -assign pyc_extract_469 = PE_INT_WALLACE_DOT8_TREE_W16_in5[11]; -assign pyc_extract_470 = PE_INT_WALLACE_DOT8_TREE_W16_in6[11]; -assign pyc_xor_471 = (pyc_extract_468 ^ pyc_extract_469); -assign pyc_xor_472 = (pyc_xor_471 ^ pyc_extract_470); -assign pyc_and_473 = (pyc_extract_468 & pyc_extract_469); -assign pyc_and_474 = (pyc_extract_468 & pyc_extract_470); -assign pyc_or_475 = (pyc_and_473 | pyc_and_474); -assign pyc_and_476 = (pyc_extract_469 & pyc_extract_470); -assign pyc_or_477 = (pyc_or_475 | pyc_and_476); -assign pyc_extract_478 = PE_INT_WALLACE_DOT8_TREE_W16_in7[11]; -assign pyc_xor_479 = (pyc_xor_472 ^ pyc_extract_478); -assign pyc_xor_480 = (pyc_xor_479 ^ pyc_or_459); -assign pyc_and_481 = (pyc_xor_472 & pyc_extract_478); -assign pyc_and_482 = (pyc_xor_472 & pyc_or_459); -assign pyc_or_483 = (pyc_and_481 | pyc_and_482); -assign pyc_and_484 = (pyc_extract_478 & pyc_or_459); -assign pyc_or_485 = (pyc_or_483 | pyc_and_484); -assign pyc_extract_486 = PE_INT_WALLACE_DOT8_TREE_W16_in4[12]; -assign pyc_extract_487 = PE_INT_WALLACE_DOT8_TREE_W16_in5[12]; -assign pyc_extract_488 = PE_INT_WALLACE_DOT8_TREE_W16_in6[12]; -assign pyc_xor_489 = (pyc_extract_486 ^ pyc_extract_487); -assign pyc_xor_490 = (pyc_xor_489 ^ pyc_extract_488); -assign pyc_and_491 = (pyc_extract_486 & pyc_extract_487); -assign pyc_and_492 = (pyc_extract_486 & pyc_extract_488); -assign pyc_or_493 = (pyc_and_491 | pyc_and_492); -assign pyc_and_494 = (pyc_extract_487 & pyc_extract_488); -assign pyc_or_495 = (pyc_or_493 | pyc_and_494); -assign pyc_extract_496 = PE_INT_WALLACE_DOT8_TREE_W16_in7[12]; -assign pyc_xor_497 = (pyc_xor_490 ^ pyc_extract_496); -assign pyc_xor_498 = (pyc_xor_497 ^ pyc_or_477); -assign pyc_and_499 = (pyc_xor_490 & pyc_extract_496); -assign pyc_and_500 = (pyc_xor_490 & pyc_or_477); -assign pyc_or_501 = (pyc_and_499 | pyc_and_500); -assign pyc_and_502 = (pyc_extract_496 & pyc_or_477); -assign pyc_or_503 = (pyc_or_501 | pyc_and_502); -assign pyc_extract_504 = PE_INT_WALLACE_DOT8_TREE_W16_in4[13]; -assign pyc_extract_505 = PE_INT_WALLACE_DOT8_TREE_W16_in5[13]; -assign pyc_extract_506 = PE_INT_WALLACE_DOT8_TREE_W16_in6[13]; -assign pyc_xor_507 = (pyc_extract_504 ^ pyc_extract_505); -assign pyc_xor_508 = (pyc_xor_507 ^ pyc_extract_506); -assign pyc_and_509 = (pyc_extract_504 & pyc_extract_505); -assign pyc_and_510 = (pyc_extract_504 & pyc_extract_506); -assign pyc_or_511 = (pyc_and_509 | pyc_and_510); -assign pyc_and_512 = (pyc_extract_505 & pyc_extract_506); -assign pyc_or_513 = (pyc_or_511 | pyc_and_512); -assign pyc_extract_514 = PE_INT_WALLACE_DOT8_TREE_W16_in7[13]; -assign pyc_xor_515 = (pyc_xor_508 ^ pyc_extract_514); -assign pyc_xor_516 = (pyc_xor_515 ^ pyc_or_495); -assign pyc_and_517 = (pyc_xor_508 & pyc_extract_514); -assign pyc_and_518 = (pyc_xor_508 & pyc_or_495); -assign pyc_or_519 = (pyc_and_517 | pyc_and_518); -assign pyc_and_520 = (pyc_extract_514 & pyc_or_495); -assign pyc_or_521 = (pyc_or_519 | pyc_and_520); -assign pyc_extract_522 = PE_INT_WALLACE_DOT8_TREE_W16_in4[14]; -assign pyc_extract_523 = PE_INT_WALLACE_DOT8_TREE_W16_in5[14]; -assign pyc_extract_524 = PE_INT_WALLACE_DOT8_TREE_W16_in6[14]; -assign pyc_xor_525 = (pyc_extract_522 ^ pyc_extract_523); -assign pyc_xor_526 = (pyc_xor_525 ^ pyc_extract_524); -assign pyc_and_527 = (pyc_extract_522 & pyc_extract_523); -assign pyc_and_528 = (pyc_extract_522 & pyc_extract_524); -assign pyc_or_529 = (pyc_and_527 | pyc_and_528); -assign pyc_and_530 = (pyc_extract_523 & pyc_extract_524); -assign pyc_or_531 = (pyc_or_529 | pyc_and_530); -assign pyc_extract_532 = PE_INT_WALLACE_DOT8_TREE_W16_in7[14]; -assign pyc_xor_533 = (pyc_xor_526 ^ pyc_extract_532); -assign pyc_xor_534 = (pyc_xor_533 ^ pyc_or_513); -assign pyc_and_535 = (pyc_xor_526 & pyc_extract_532); -assign pyc_and_536 = (pyc_xor_526 & pyc_or_513); -assign pyc_or_537 = (pyc_and_535 | pyc_and_536); -assign pyc_and_538 = (pyc_extract_532 & pyc_or_513); -assign pyc_or_539 = (pyc_or_537 | pyc_and_538); -assign pyc_extract_540 = PE_INT_WALLACE_DOT8_TREE_W16_in4[15]; -assign pyc_extract_541 = PE_INT_WALLACE_DOT8_TREE_W16_in5[15]; -assign pyc_extract_542 = PE_INT_WALLACE_DOT8_TREE_W16_in6[15]; -assign pyc_xor_543 = (pyc_extract_540 ^ pyc_extract_541); -assign pyc_xor_544 = (pyc_xor_543 ^ pyc_extract_542); -assign pyc_extract_545 = PE_INT_WALLACE_DOT8_TREE_W16_in7[15]; -assign pyc_xor_546 = (pyc_xor_544 ^ pyc_extract_545); -assign pyc_xor_547 = (pyc_xor_546 ^ pyc_or_531); -assign pyc_xor_548 = (pyc_xor_13 ^ pyc_xor_286); -assign pyc_and_549 = (pyc_xor_13 & pyc_xor_286); -assign pyc_xor_550 = (pyc_xor_27 ^ pyc_and_14); -assign pyc_xor_551 = (pyc_xor_550 ^ pyc_xor_300); -assign pyc_and_552 = (pyc_xor_27 & pyc_and_14); -assign pyc_and_553 = (pyc_xor_27 & pyc_xor_300); -assign pyc_or_554 = (pyc_and_552 | pyc_and_553); -assign pyc_and_555 = (pyc_and_14 & pyc_xor_300); -assign pyc_or_556 = (pyc_or_554 | pyc_and_555); -assign pyc_xor_557 = (pyc_xor_551 ^ pyc_and_287); -assign pyc_xor_558 = (pyc_xor_557 ^ pyc_and_549); -assign pyc_and_559 = (pyc_xor_551 & pyc_and_287); -assign pyc_and_560 = (pyc_xor_551 & pyc_and_549); -assign pyc_or_561 = (pyc_and_559 | pyc_and_560); -assign pyc_and_562 = (pyc_and_287 & pyc_and_549); -assign pyc_or_563 = (pyc_or_561 | pyc_and_562); -assign pyc_xor_564 = (pyc_xor_45 ^ pyc_or_32); -assign pyc_xor_565 = (pyc_xor_564 ^ pyc_xor_318); -assign pyc_and_566 = (pyc_xor_45 & pyc_or_32); -assign pyc_and_567 = (pyc_xor_45 & pyc_xor_318); -assign pyc_or_568 = (pyc_and_566 | pyc_and_567); -assign pyc_and_569 = (pyc_or_32 & pyc_xor_318); -assign pyc_or_570 = (pyc_or_568 | pyc_and_569); -assign pyc_xor_571 = (pyc_xor_565 ^ pyc_or_305); -assign pyc_xor_572 = (pyc_xor_571 ^ pyc_or_556); -assign pyc_and_573 = (pyc_xor_565 & pyc_or_305); -assign pyc_and_574 = (pyc_xor_565 & pyc_or_556); -assign pyc_or_575 = (pyc_and_573 | pyc_and_574); -assign pyc_and_576 = (pyc_or_305 & pyc_or_556); -assign pyc_or_577 = (pyc_or_575 | pyc_and_576); -assign pyc_xor_578 = (pyc_xor_63 ^ pyc_or_50); -assign pyc_xor_579 = (pyc_xor_578 ^ pyc_xor_336); -assign pyc_and_580 = (pyc_xor_63 & pyc_or_50); -assign pyc_and_581 = (pyc_xor_63 & pyc_xor_336); -assign pyc_or_582 = (pyc_and_580 | pyc_and_581); -assign pyc_and_583 = (pyc_or_50 & pyc_xor_336); -assign pyc_or_584 = (pyc_or_582 | pyc_and_583); -assign pyc_xor_585 = (pyc_xor_579 ^ pyc_or_323); -assign pyc_xor_586 = (pyc_xor_585 ^ pyc_or_570); -assign pyc_and_587 = (pyc_xor_579 & pyc_or_323); -assign pyc_and_588 = (pyc_xor_579 & pyc_or_570); -assign pyc_or_589 = (pyc_and_587 | pyc_and_588); -assign pyc_and_590 = (pyc_or_323 & pyc_or_570); -assign pyc_or_591 = (pyc_or_589 | pyc_and_590); -assign pyc_xor_592 = (pyc_xor_81 ^ pyc_or_68); -assign pyc_xor_593 = (pyc_xor_592 ^ pyc_xor_354); -assign pyc_and_594 = (pyc_xor_81 & pyc_or_68); -assign pyc_and_595 = (pyc_xor_81 & pyc_xor_354); -assign pyc_or_596 = (pyc_and_594 | pyc_and_595); -assign pyc_and_597 = (pyc_or_68 & pyc_xor_354); -assign pyc_or_598 = (pyc_or_596 | pyc_and_597); -assign pyc_xor_599 = (pyc_xor_593 ^ pyc_or_341); -assign pyc_xor_600 = (pyc_xor_599 ^ pyc_or_584); -assign pyc_and_601 = (pyc_xor_593 & pyc_or_341); -assign pyc_and_602 = (pyc_xor_593 & pyc_or_584); -assign pyc_or_603 = (pyc_and_601 | pyc_and_602); -assign pyc_and_604 = (pyc_or_341 & pyc_or_584); -assign pyc_or_605 = (pyc_or_603 | pyc_and_604); -assign pyc_xor_606 = (pyc_xor_99 ^ pyc_or_86); -assign pyc_xor_607 = (pyc_xor_606 ^ pyc_xor_372); -assign pyc_and_608 = (pyc_xor_99 & pyc_or_86); -assign pyc_and_609 = (pyc_xor_99 & pyc_xor_372); -assign pyc_or_610 = (pyc_and_608 | pyc_and_609); -assign pyc_and_611 = (pyc_or_86 & pyc_xor_372); -assign pyc_or_612 = (pyc_or_610 | pyc_and_611); -assign pyc_xor_613 = (pyc_xor_607 ^ pyc_or_359); -assign pyc_xor_614 = (pyc_xor_613 ^ pyc_or_598); -assign pyc_and_615 = (pyc_xor_607 & pyc_or_359); -assign pyc_and_616 = (pyc_xor_607 & pyc_or_598); -assign pyc_or_617 = (pyc_and_615 | pyc_and_616); -assign pyc_and_618 = (pyc_or_359 & pyc_or_598); -assign pyc_or_619 = (pyc_or_617 | pyc_and_618); -assign pyc_xor_620 = (pyc_xor_117 ^ pyc_or_104); -assign pyc_xor_621 = (pyc_xor_620 ^ pyc_xor_390); -assign pyc_and_622 = (pyc_xor_117 & pyc_or_104); -assign pyc_and_623 = (pyc_xor_117 & pyc_xor_390); -assign pyc_or_624 = (pyc_and_622 | pyc_and_623); -assign pyc_and_625 = (pyc_or_104 & pyc_xor_390); -assign pyc_or_626 = (pyc_or_624 | pyc_and_625); -assign pyc_xor_627 = (pyc_xor_621 ^ pyc_or_377); -assign pyc_xor_628 = (pyc_xor_627 ^ pyc_or_612); -assign pyc_and_629 = (pyc_xor_621 & pyc_or_377); -assign pyc_and_630 = (pyc_xor_621 & pyc_or_612); -assign pyc_or_631 = (pyc_and_629 | pyc_and_630); -assign pyc_and_632 = (pyc_or_377 & pyc_or_612); -assign pyc_or_633 = (pyc_or_631 | pyc_and_632); -assign pyc_xor_634 = (pyc_xor_135 ^ pyc_or_122); -assign pyc_xor_635 = (pyc_xor_634 ^ pyc_xor_408); -assign pyc_and_636 = (pyc_xor_135 & pyc_or_122); -assign pyc_and_637 = (pyc_xor_135 & pyc_xor_408); -assign pyc_or_638 = (pyc_and_636 | pyc_and_637); -assign pyc_and_639 = (pyc_or_122 & pyc_xor_408); -assign pyc_or_640 = (pyc_or_638 | pyc_and_639); -assign pyc_xor_641 = (pyc_xor_635 ^ pyc_or_395); -assign pyc_xor_642 = (pyc_xor_641 ^ pyc_or_626); -assign pyc_and_643 = (pyc_xor_635 & pyc_or_395); -assign pyc_and_644 = (pyc_xor_635 & pyc_or_626); -assign pyc_or_645 = (pyc_and_643 | pyc_and_644); -assign pyc_and_646 = (pyc_or_395 & pyc_or_626); -assign pyc_or_647 = (pyc_or_645 | pyc_and_646); -assign pyc_xor_648 = (pyc_xor_153 ^ pyc_or_140); -assign pyc_xor_649 = (pyc_xor_648 ^ pyc_xor_426); -assign pyc_and_650 = (pyc_xor_153 & pyc_or_140); -assign pyc_and_651 = (pyc_xor_153 & pyc_xor_426); -assign pyc_or_652 = (pyc_and_650 | pyc_and_651); -assign pyc_and_653 = (pyc_or_140 & pyc_xor_426); -assign pyc_or_654 = (pyc_or_652 | pyc_and_653); -assign pyc_xor_655 = (pyc_xor_649 ^ pyc_or_413); -assign pyc_xor_656 = (pyc_xor_655 ^ pyc_or_640); -assign pyc_and_657 = (pyc_xor_649 & pyc_or_413); -assign pyc_and_658 = (pyc_xor_649 & pyc_or_640); -assign pyc_or_659 = (pyc_and_657 | pyc_and_658); -assign pyc_and_660 = (pyc_or_413 & pyc_or_640); -assign pyc_or_661 = (pyc_or_659 | pyc_and_660); -assign pyc_xor_662 = (pyc_xor_171 ^ pyc_or_158); -assign pyc_xor_663 = (pyc_xor_662 ^ pyc_xor_444); -assign pyc_and_664 = (pyc_xor_171 & pyc_or_158); -assign pyc_and_665 = (pyc_xor_171 & pyc_xor_444); -assign pyc_or_666 = (pyc_and_664 | pyc_and_665); -assign pyc_and_667 = (pyc_or_158 & pyc_xor_444); -assign pyc_or_668 = (pyc_or_666 | pyc_and_667); -assign pyc_xor_669 = (pyc_xor_663 ^ pyc_or_431); -assign pyc_xor_670 = (pyc_xor_669 ^ pyc_or_654); -assign pyc_and_671 = (pyc_xor_663 & pyc_or_431); -assign pyc_and_672 = (pyc_xor_663 & pyc_or_654); -assign pyc_or_673 = (pyc_and_671 | pyc_and_672); -assign pyc_and_674 = (pyc_or_431 & pyc_or_654); -assign pyc_or_675 = (pyc_or_673 | pyc_and_674); -assign pyc_xor_676 = (pyc_xor_189 ^ pyc_or_176); -assign pyc_xor_677 = (pyc_xor_676 ^ pyc_xor_462); -assign pyc_and_678 = (pyc_xor_189 & pyc_or_176); -assign pyc_and_679 = (pyc_xor_189 & pyc_xor_462); -assign pyc_or_680 = (pyc_and_678 | pyc_and_679); -assign pyc_and_681 = (pyc_or_176 & pyc_xor_462); -assign pyc_or_682 = (pyc_or_680 | pyc_and_681); -assign pyc_xor_683 = (pyc_xor_677 ^ pyc_or_449); -assign pyc_xor_684 = (pyc_xor_683 ^ pyc_or_668); -assign pyc_and_685 = (pyc_xor_677 & pyc_or_449); -assign pyc_and_686 = (pyc_xor_677 & pyc_or_668); -assign pyc_or_687 = (pyc_and_685 | pyc_and_686); -assign pyc_and_688 = (pyc_or_449 & pyc_or_668); -assign pyc_or_689 = (pyc_or_687 | pyc_and_688); -assign pyc_xor_690 = (pyc_xor_207 ^ pyc_or_194); -assign pyc_xor_691 = (pyc_xor_690 ^ pyc_xor_480); -assign pyc_and_692 = (pyc_xor_207 & pyc_or_194); -assign pyc_and_693 = (pyc_xor_207 & pyc_xor_480); -assign pyc_or_694 = (pyc_and_692 | pyc_and_693); -assign pyc_and_695 = (pyc_or_194 & pyc_xor_480); -assign pyc_or_696 = (pyc_or_694 | pyc_and_695); -assign pyc_xor_697 = (pyc_xor_691 ^ pyc_or_467); -assign pyc_xor_698 = (pyc_xor_697 ^ pyc_or_682); -assign pyc_and_699 = (pyc_xor_691 & pyc_or_467); -assign pyc_and_700 = (pyc_xor_691 & pyc_or_682); -assign pyc_or_701 = (pyc_and_699 | pyc_and_700); -assign pyc_and_702 = (pyc_or_467 & pyc_or_682); -assign pyc_or_703 = (pyc_or_701 | pyc_and_702); -assign pyc_xor_704 = (pyc_xor_225 ^ pyc_or_212); -assign pyc_xor_705 = (pyc_xor_704 ^ pyc_xor_498); -assign pyc_and_706 = (pyc_xor_225 & pyc_or_212); -assign pyc_and_707 = (pyc_xor_225 & pyc_xor_498); -assign pyc_or_708 = (pyc_and_706 | pyc_and_707); -assign pyc_and_709 = (pyc_or_212 & pyc_xor_498); -assign pyc_or_710 = (pyc_or_708 | pyc_and_709); -assign pyc_xor_711 = (pyc_xor_705 ^ pyc_or_485); -assign pyc_xor_712 = (pyc_xor_711 ^ pyc_or_696); -assign pyc_and_713 = (pyc_xor_705 & pyc_or_485); -assign pyc_and_714 = (pyc_xor_705 & pyc_or_696); -assign pyc_or_715 = (pyc_and_713 | pyc_and_714); -assign pyc_and_716 = (pyc_or_485 & pyc_or_696); -assign pyc_or_717 = (pyc_or_715 | pyc_and_716); -assign pyc_xor_718 = (pyc_xor_243 ^ pyc_or_230); -assign pyc_xor_719 = (pyc_xor_718 ^ pyc_xor_516); -assign pyc_and_720 = (pyc_xor_243 & pyc_or_230); -assign pyc_and_721 = (pyc_xor_243 & pyc_xor_516); -assign pyc_or_722 = (pyc_and_720 | pyc_and_721); -assign pyc_and_723 = (pyc_or_230 & pyc_xor_516); -assign pyc_or_724 = (pyc_or_722 | pyc_and_723); -assign pyc_xor_725 = (pyc_xor_719 ^ pyc_or_503); -assign pyc_xor_726 = (pyc_xor_725 ^ pyc_or_710); -assign pyc_and_727 = (pyc_xor_719 & pyc_or_503); -assign pyc_and_728 = (pyc_xor_719 & pyc_or_710); -assign pyc_or_729 = (pyc_and_727 | pyc_and_728); -assign pyc_and_730 = (pyc_or_503 & pyc_or_710); -assign pyc_or_731 = (pyc_or_729 | pyc_and_730); -assign pyc_xor_732 = (pyc_xor_261 ^ pyc_or_248); -assign pyc_xor_733 = (pyc_xor_732 ^ pyc_xor_534); -assign pyc_and_734 = (pyc_xor_261 & pyc_or_248); -assign pyc_and_735 = (pyc_xor_261 & pyc_xor_534); -assign pyc_or_736 = (pyc_and_734 | pyc_and_735); -assign pyc_and_737 = (pyc_or_248 & pyc_xor_534); -assign pyc_or_738 = (pyc_or_736 | pyc_and_737); -assign pyc_xor_739 = (pyc_xor_733 ^ pyc_or_521); -assign pyc_xor_740 = (pyc_xor_739 ^ pyc_or_724); -assign pyc_and_741 = (pyc_xor_733 & pyc_or_521); -assign pyc_and_742 = (pyc_xor_733 & pyc_or_724); -assign pyc_or_743 = (pyc_and_741 | pyc_and_742); -assign pyc_and_744 = (pyc_or_521 & pyc_or_724); -assign pyc_or_745 = (pyc_or_743 | pyc_and_744); -assign pyc_xor_746 = (pyc_xor_274 ^ pyc_or_266); -assign pyc_xor_747 = (pyc_xor_746 ^ pyc_xor_547); -assign pyc_xor_748 = (pyc_xor_747 ^ pyc_or_539); -assign pyc_xor_749 = (pyc_xor_748 ^ pyc_or_738); -assign pyc_concat_750 = {pyc_xor_749, pyc_xor_740, pyc_xor_726, pyc_xor_712, pyc_xor_698, pyc_xor_684, pyc_xor_670, pyc_xor_656, pyc_xor_642, pyc_xor_628, pyc_xor_614, pyc_xor_600, pyc_xor_586, pyc_xor_572, pyc_xor_558, pyc_xor_548}; -assign pyc_concat_751 = {pyc_or_745, pyc_or_731, pyc_or_717, pyc_or_703, pyc_or_689, pyc_or_675, pyc_or_661, pyc_or_647, pyc_or_633, pyc_or_619, pyc_or_605, pyc_or_591, pyc_or_577, pyc_or_563, pyc_constant_1, pyc_constant_1}; -assign pyc_add_752 = (pyc_concat_750 + pyc_concat_751); -assign pyc_comb_753 = pyc_add_752; +assign pyc_extract_1 = PE_INT_WALLACE_DOT8_TREE_W16_in0[0]; +assign pyc_extract_2 = PE_INT_WALLACE_DOT8_TREE_W16_in1[0]; +assign pyc_extract_3 = PE_INT_WALLACE_DOT8_TREE_W16_in2[0]; +assign pyc_xor_4 = (pyc_extract_1 ^ pyc_extract_2); +assign pyc_xor_5 = (pyc_xor_4 ^ pyc_extract_3); +assign pyc_and_6 = (pyc_extract_1 & pyc_extract_2); +assign pyc_and_7 = (pyc_extract_1 & pyc_extract_3); +assign pyc_or_8 = (pyc_and_6 | pyc_and_7); +assign pyc_and_9 = (pyc_extract_2 & pyc_extract_3); +assign pyc_or_10 = (pyc_or_8 | pyc_and_9); +assign pyc_extract_11 = PE_INT_WALLACE_DOT8_TREE_W16_in3[0]; +assign pyc_xor_12 = (pyc_xor_5 ^ pyc_extract_11); +assign pyc_and_13 = (pyc_xor_5 & pyc_extract_11); +assign pyc_extract_14 = PE_INT_WALLACE_DOT8_TREE_W16_in0[1]; +assign pyc_extract_15 = PE_INT_WALLACE_DOT8_TREE_W16_in1[1]; +assign pyc_extract_16 = PE_INT_WALLACE_DOT8_TREE_W16_in2[1]; +assign pyc_xor_17 = (pyc_extract_14 ^ pyc_extract_15); +assign pyc_xor_18 = (pyc_xor_17 ^ pyc_extract_16); +assign pyc_and_19 = (pyc_extract_14 & pyc_extract_15); +assign pyc_and_20 = (pyc_extract_14 & pyc_extract_16); +assign pyc_or_21 = (pyc_and_19 | pyc_and_20); +assign pyc_and_22 = (pyc_extract_15 & pyc_extract_16); +assign pyc_or_23 = (pyc_or_21 | pyc_and_22); +assign pyc_extract_24 = PE_INT_WALLACE_DOT8_TREE_W16_in3[1]; +assign pyc_xor_25 = (pyc_xor_18 ^ pyc_extract_24); +assign pyc_xor_26 = (pyc_xor_25 ^ pyc_or_10); +assign pyc_and_27 = (pyc_xor_18 & pyc_extract_24); +assign pyc_and_28 = (pyc_xor_18 & pyc_or_10); +assign pyc_or_29 = (pyc_and_27 | pyc_and_28); +assign pyc_and_30 = (pyc_extract_24 & pyc_or_10); +assign pyc_or_31 = (pyc_or_29 | pyc_and_30); +assign pyc_extract_32 = PE_INT_WALLACE_DOT8_TREE_W16_in0[2]; +assign pyc_extract_33 = PE_INT_WALLACE_DOT8_TREE_W16_in1[2]; +assign pyc_extract_34 = PE_INT_WALLACE_DOT8_TREE_W16_in2[2]; +assign pyc_xor_35 = (pyc_extract_32 ^ pyc_extract_33); +assign pyc_xor_36 = (pyc_xor_35 ^ pyc_extract_34); +assign pyc_and_37 = (pyc_extract_32 & pyc_extract_33); +assign pyc_and_38 = (pyc_extract_32 & pyc_extract_34); +assign pyc_or_39 = (pyc_and_37 | pyc_and_38); +assign pyc_and_40 = (pyc_extract_33 & pyc_extract_34); +assign pyc_or_41 = (pyc_or_39 | pyc_and_40); +assign pyc_extract_42 = PE_INT_WALLACE_DOT8_TREE_W16_in3[2]; +assign pyc_xor_43 = (pyc_xor_36 ^ pyc_extract_42); +assign pyc_xor_44 = (pyc_xor_43 ^ pyc_or_23); +assign pyc_and_45 = (pyc_xor_36 & pyc_extract_42); +assign pyc_and_46 = (pyc_xor_36 & pyc_or_23); +assign pyc_or_47 = (pyc_and_45 | pyc_and_46); +assign pyc_and_48 = (pyc_extract_42 & pyc_or_23); +assign pyc_or_49 = (pyc_or_47 | pyc_and_48); +assign pyc_extract_50 = PE_INT_WALLACE_DOT8_TREE_W16_in0[3]; +assign pyc_extract_51 = PE_INT_WALLACE_DOT8_TREE_W16_in1[3]; +assign pyc_extract_52 = PE_INT_WALLACE_DOT8_TREE_W16_in2[3]; +assign pyc_xor_53 = (pyc_extract_50 ^ pyc_extract_51); +assign pyc_xor_54 = (pyc_xor_53 ^ pyc_extract_52); +assign pyc_and_55 = (pyc_extract_50 & pyc_extract_51); +assign pyc_and_56 = (pyc_extract_50 & pyc_extract_52); +assign pyc_or_57 = (pyc_and_55 | pyc_and_56); +assign pyc_and_58 = (pyc_extract_51 & pyc_extract_52); +assign pyc_or_59 = (pyc_or_57 | pyc_and_58); +assign pyc_extract_60 = PE_INT_WALLACE_DOT8_TREE_W16_in3[3]; +assign pyc_xor_61 = (pyc_xor_54 ^ pyc_extract_60); +assign pyc_xor_62 = (pyc_xor_61 ^ pyc_or_41); +assign pyc_and_63 = (pyc_xor_54 & pyc_extract_60); +assign pyc_and_64 = (pyc_xor_54 & pyc_or_41); +assign pyc_or_65 = (pyc_and_63 | pyc_and_64); +assign pyc_and_66 = (pyc_extract_60 & pyc_or_41); +assign pyc_or_67 = (pyc_or_65 | pyc_and_66); +assign pyc_extract_68 = PE_INT_WALLACE_DOT8_TREE_W16_in0[4]; +assign pyc_extract_69 = PE_INT_WALLACE_DOT8_TREE_W16_in1[4]; +assign pyc_extract_70 = PE_INT_WALLACE_DOT8_TREE_W16_in2[4]; +assign pyc_xor_71 = (pyc_extract_68 ^ pyc_extract_69); +assign pyc_xor_72 = (pyc_xor_71 ^ pyc_extract_70); +assign pyc_and_73 = (pyc_extract_68 & pyc_extract_69); +assign pyc_and_74 = (pyc_extract_68 & pyc_extract_70); +assign pyc_or_75 = (pyc_and_73 | pyc_and_74); +assign pyc_and_76 = (pyc_extract_69 & pyc_extract_70); +assign pyc_or_77 = (pyc_or_75 | pyc_and_76); +assign pyc_extract_78 = PE_INT_WALLACE_DOT8_TREE_W16_in3[4]; +assign pyc_xor_79 = (pyc_xor_72 ^ pyc_extract_78); +assign pyc_xor_80 = (pyc_xor_79 ^ pyc_or_59); +assign pyc_and_81 = (pyc_xor_72 & pyc_extract_78); +assign pyc_and_82 = (pyc_xor_72 & pyc_or_59); +assign pyc_or_83 = (pyc_and_81 | pyc_and_82); +assign pyc_and_84 = (pyc_extract_78 & pyc_or_59); +assign pyc_or_85 = (pyc_or_83 | pyc_and_84); +assign pyc_extract_86 = PE_INT_WALLACE_DOT8_TREE_W16_in0[5]; +assign pyc_extract_87 = PE_INT_WALLACE_DOT8_TREE_W16_in1[5]; +assign pyc_extract_88 = PE_INT_WALLACE_DOT8_TREE_W16_in2[5]; +assign pyc_xor_89 = (pyc_extract_86 ^ pyc_extract_87); +assign pyc_xor_90 = (pyc_xor_89 ^ pyc_extract_88); +assign pyc_and_91 = (pyc_extract_86 & pyc_extract_87); +assign pyc_and_92 = (pyc_extract_86 & pyc_extract_88); +assign pyc_or_93 = (pyc_and_91 | pyc_and_92); +assign pyc_and_94 = (pyc_extract_87 & pyc_extract_88); +assign pyc_or_95 = (pyc_or_93 | pyc_and_94); +assign pyc_extract_96 = PE_INT_WALLACE_DOT8_TREE_W16_in3[5]; +assign pyc_xor_97 = (pyc_xor_90 ^ pyc_extract_96); +assign pyc_xor_98 = (pyc_xor_97 ^ pyc_or_77); +assign pyc_and_99 = (pyc_xor_90 & pyc_extract_96); +assign pyc_and_100 = (pyc_xor_90 & pyc_or_77); +assign pyc_or_101 = (pyc_and_99 | pyc_and_100); +assign pyc_and_102 = (pyc_extract_96 & pyc_or_77); +assign pyc_or_103 = (pyc_or_101 | pyc_and_102); +assign pyc_extract_104 = PE_INT_WALLACE_DOT8_TREE_W16_in0[6]; +assign pyc_extract_105 = PE_INT_WALLACE_DOT8_TREE_W16_in1[6]; +assign pyc_extract_106 = PE_INT_WALLACE_DOT8_TREE_W16_in2[6]; +assign pyc_xor_107 = (pyc_extract_104 ^ pyc_extract_105); +assign pyc_xor_108 = (pyc_xor_107 ^ pyc_extract_106); +assign pyc_and_109 = (pyc_extract_104 & pyc_extract_105); +assign pyc_and_110 = (pyc_extract_104 & pyc_extract_106); +assign pyc_or_111 = (pyc_and_109 | pyc_and_110); +assign pyc_and_112 = (pyc_extract_105 & pyc_extract_106); +assign pyc_or_113 = (pyc_or_111 | pyc_and_112); +assign pyc_extract_114 = PE_INT_WALLACE_DOT8_TREE_W16_in3[6]; +assign pyc_xor_115 = (pyc_xor_108 ^ pyc_extract_114); +assign pyc_xor_116 = (pyc_xor_115 ^ pyc_or_95); +assign pyc_and_117 = (pyc_xor_108 & pyc_extract_114); +assign pyc_and_118 = (pyc_xor_108 & pyc_or_95); +assign pyc_or_119 = (pyc_and_117 | pyc_and_118); +assign pyc_and_120 = (pyc_extract_114 & pyc_or_95); +assign pyc_or_121 = (pyc_or_119 | pyc_and_120); +assign pyc_extract_122 = PE_INT_WALLACE_DOT8_TREE_W16_in0[7]; +assign pyc_extract_123 = PE_INT_WALLACE_DOT8_TREE_W16_in1[7]; +assign pyc_extract_124 = PE_INT_WALLACE_DOT8_TREE_W16_in2[7]; +assign pyc_xor_125 = (pyc_extract_122 ^ pyc_extract_123); +assign pyc_xor_126 = (pyc_xor_125 ^ pyc_extract_124); +assign pyc_and_127 = (pyc_extract_122 & pyc_extract_123); +assign pyc_and_128 = (pyc_extract_122 & pyc_extract_124); +assign pyc_or_129 = (pyc_and_127 | pyc_and_128); +assign pyc_and_130 = (pyc_extract_123 & pyc_extract_124); +assign pyc_or_131 = (pyc_or_129 | pyc_and_130); +assign pyc_extract_132 = PE_INT_WALLACE_DOT8_TREE_W16_in3[7]; +assign pyc_xor_133 = (pyc_xor_126 ^ pyc_extract_132); +assign pyc_xor_134 = (pyc_xor_133 ^ pyc_or_113); +assign pyc_and_135 = (pyc_xor_126 & pyc_extract_132); +assign pyc_and_136 = (pyc_xor_126 & pyc_or_113); +assign pyc_or_137 = (pyc_and_135 | pyc_and_136); +assign pyc_and_138 = (pyc_extract_132 & pyc_or_113); +assign pyc_or_139 = (pyc_or_137 | pyc_and_138); +assign pyc_extract_140 = PE_INT_WALLACE_DOT8_TREE_W16_in0[8]; +assign pyc_extract_141 = PE_INT_WALLACE_DOT8_TREE_W16_in1[8]; +assign pyc_extract_142 = PE_INT_WALLACE_DOT8_TREE_W16_in2[8]; +assign pyc_xor_143 = (pyc_extract_140 ^ pyc_extract_141); +assign pyc_xor_144 = (pyc_xor_143 ^ pyc_extract_142); +assign pyc_and_145 = (pyc_extract_140 & pyc_extract_141); +assign pyc_and_146 = (pyc_extract_140 & pyc_extract_142); +assign pyc_or_147 = (pyc_and_145 | pyc_and_146); +assign pyc_and_148 = (pyc_extract_141 & pyc_extract_142); +assign pyc_or_149 = (pyc_or_147 | pyc_and_148); +assign pyc_extract_150 = PE_INT_WALLACE_DOT8_TREE_W16_in3[8]; +assign pyc_xor_151 = (pyc_xor_144 ^ pyc_extract_150); +assign pyc_xor_152 = (pyc_xor_151 ^ pyc_or_131); +assign pyc_and_153 = (pyc_xor_144 & pyc_extract_150); +assign pyc_and_154 = (pyc_xor_144 & pyc_or_131); +assign pyc_or_155 = (pyc_and_153 | pyc_and_154); +assign pyc_and_156 = (pyc_extract_150 & pyc_or_131); +assign pyc_or_157 = (pyc_or_155 | pyc_and_156); +assign pyc_extract_158 = PE_INT_WALLACE_DOT8_TREE_W16_in0[9]; +assign pyc_extract_159 = PE_INT_WALLACE_DOT8_TREE_W16_in1[9]; +assign pyc_extract_160 = PE_INT_WALLACE_DOT8_TREE_W16_in2[9]; +assign pyc_xor_161 = (pyc_extract_158 ^ pyc_extract_159); +assign pyc_xor_162 = (pyc_xor_161 ^ pyc_extract_160); +assign pyc_and_163 = (pyc_extract_158 & pyc_extract_159); +assign pyc_and_164 = (pyc_extract_158 & pyc_extract_160); +assign pyc_or_165 = (pyc_and_163 | pyc_and_164); +assign pyc_and_166 = (pyc_extract_159 & pyc_extract_160); +assign pyc_or_167 = (pyc_or_165 | pyc_and_166); +assign pyc_extract_168 = PE_INT_WALLACE_DOT8_TREE_W16_in3[9]; +assign pyc_xor_169 = (pyc_xor_162 ^ pyc_extract_168); +assign pyc_xor_170 = (pyc_xor_169 ^ pyc_or_149); +assign pyc_and_171 = (pyc_xor_162 & pyc_extract_168); +assign pyc_and_172 = (pyc_xor_162 & pyc_or_149); +assign pyc_or_173 = (pyc_and_171 | pyc_and_172); +assign pyc_and_174 = (pyc_extract_168 & pyc_or_149); +assign pyc_or_175 = (pyc_or_173 | pyc_and_174); +assign pyc_extract_176 = PE_INT_WALLACE_DOT8_TREE_W16_in0[10]; +assign pyc_extract_177 = PE_INT_WALLACE_DOT8_TREE_W16_in1[10]; +assign pyc_extract_178 = PE_INT_WALLACE_DOT8_TREE_W16_in2[10]; +assign pyc_xor_179 = (pyc_extract_176 ^ pyc_extract_177); +assign pyc_xor_180 = (pyc_xor_179 ^ pyc_extract_178); +assign pyc_and_181 = (pyc_extract_176 & pyc_extract_177); +assign pyc_and_182 = (pyc_extract_176 & pyc_extract_178); +assign pyc_or_183 = (pyc_and_181 | pyc_and_182); +assign pyc_and_184 = (pyc_extract_177 & pyc_extract_178); +assign pyc_or_185 = (pyc_or_183 | pyc_and_184); +assign pyc_extract_186 = PE_INT_WALLACE_DOT8_TREE_W16_in3[10]; +assign pyc_xor_187 = (pyc_xor_180 ^ pyc_extract_186); +assign pyc_xor_188 = (pyc_xor_187 ^ pyc_or_167); +assign pyc_and_189 = (pyc_xor_180 & pyc_extract_186); +assign pyc_and_190 = (pyc_xor_180 & pyc_or_167); +assign pyc_or_191 = (pyc_and_189 | pyc_and_190); +assign pyc_and_192 = (pyc_extract_186 & pyc_or_167); +assign pyc_or_193 = (pyc_or_191 | pyc_and_192); +assign pyc_extract_194 = PE_INT_WALLACE_DOT8_TREE_W16_in0[11]; +assign pyc_extract_195 = PE_INT_WALLACE_DOT8_TREE_W16_in1[11]; +assign pyc_extract_196 = PE_INT_WALLACE_DOT8_TREE_W16_in2[11]; +assign pyc_xor_197 = (pyc_extract_194 ^ pyc_extract_195); +assign pyc_xor_198 = (pyc_xor_197 ^ pyc_extract_196); +assign pyc_and_199 = (pyc_extract_194 & pyc_extract_195); +assign pyc_and_200 = (pyc_extract_194 & pyc_extract_196); +assign pyc_or_201 = (pyc_and_199 | pyc_and_200); +assign pyc_and_202 = (pyc_extract_195 & pyc_extract_196); +assign pyc_or_203 = (pyc_or_201 | pyc_and_202); +assign pyc_extract_204 = PE_INT_WALLACE_DOT8_TREE_W16_in3[11]; +assign pyc_xor_205 = (pyc_xor_198 ^ pyc_extract_204); +assign pyc_xor_206 = (pyc_xor_205 ^ pyc_or_185); +assign pyc_and_207 = (pyc_xor_198 & pyc_extract_204); +assign pyc_and_208 = (pyc_xor_198 & pyc_or_185); +assign pyc_or_209 = (pyc_and_207 | pyc_and_208); +assign pyc_and_210 = (pyc_extract_204 & pyc_or_185); +assign pyc_or_211 = (pyc_or_209 | pyc_and_210); +assign pyc_extract_212 = PE_INT_WALLACE_DOT8_TREE_W16_in0[12]; +assign pyc_extract_213 = PE_INT_WALLACE_DOT8_TREE_W16_in1[12]; +assign pyc_extract_214 = PE_INT_WALLACE_DOT8_TREE_W16_in2[12]; +assign pyc_xor_215 = (pyc_extract_212 ^ pyc_extract_213); +assign pyc_xor_216 = (pyc_xor_215 ^ pyc_extract_214); +assign pyc_and_217 = (pyc_extract_212 & pyc_extract_213); +assign pyc_and_218 = (pyc_extract_212 & pyc_extract_214); +assign pyc_or_219 = (pyc_and_217 | pyc_and_218); +assign pyc_and_220 = (pyc_extract_213 & pyc_extract_214); +assign pyc_or_221 = (pyc_or_219 | pyc_and_220); +assign pyc_extract_222 = PE_INT_WALLACE_DOT8_TREE_W16_in3[12]; +assign pyc_xor_223 = (pyc_xor_216 ^ pyc_extract_222); +assign pyc_xor_224 = (pyc_xor_223 ^ pyc_or_203); +assign pyc_and_225 = (pyc_xor_216 & pyc_extract_222); +assign pyc_and_226 = (pyc_xor_216 & pyc_or_203); +assign pyc_or_227 = (pyc_and_225 | pyc_and_226); +assign pyc_and_228 = (pyc_extract_222 & pyc_or_203); +assign pyc_or_229 = (pyc_or_227 | pyc_and_228); +assign pyc_extract_230 = PE_INT_WALLACE_DOT8_TREE_W16_in0[13]; +assign pyc_extract_231 = PE_INT_WALLACE_DOT8_TREE_W16_in1[13]; +assign pyc_extract_232 = PE_INT_WALLACE_DOT8_TREE_W16_in2[13]; +assign pyc_xor_233 = (pyc_extract_230 ^ pyc_extract_231); +assign pyc_xor_234 = (pyc_xor_233 ^ pyc_extract_232); +assign pyc_and_235 = (pyc_extract_230 & pyc_extract_231); +assign pyc_and_236 = (pyc_extract_230 & pyc_extract_232); +assign pyc_or_237 = (pyc_and_235 | pyc_and_236); +assign pyc_and_238 = (pyc_extract_231 & pyc_extract_232); +assign pyc_or_239 = (pyc_or_237 | pyc_and_238); +assign pyc_extract_240 = PE_INT_WALLACE_DOT8_TREE_W16_in3[13]; +assign pyc_xor_241 = (pyc_xor_234 ^ pyc_extract_240); +assign pyc_xor_242 = (pyc_xor_241 ^ pyc_or_221); +assign pyc_and_243 = (pyc_xor_234 & pyc_extract_240); +assign pyc_and_244 = (pyc_xor_234 & pyc_or_221); +assign pyc_or_245 = (pyc_and_243 | pyc_and_244); +assign pyc_and_246 = (pyc_extract_240 & pyc_or_221); +assign pyc_or_247 = (pyc_or_245 | pyc_and_246); +assign pyc_extract_248 = PE_INT_WALLACE_DOT8_TREE_W16_in0[14]; +assign pyc_extract_249 = PE_INT_WALLACE_DOT8_TREE_W16_in1[14]; +assign pyc_extract_250 = PE_INT_WALLACE_DOT8_TREE_W16_in2[14]; +assign pyc_xor_251 = (pyc_extract_248 ^ pyc_extract_249); +assign pyc_xor_252 = (pyc_xor_251 ^ pyc_extract_250); +assign pyc_and_253 = (pyc_extract_248 & pyc_extract_249); +assign pyc_and_254 = (pyc_extract_248 & pyc_extract_250); +assign pyc_or_255 = (pyc_and_253 | pyc_and_254); +assign pyc_and_256 = (pyc_extract_249 & pyc_extract_250); +assign pyc_or_257 = (pyc_or_255 | pyc_and_256); +assign pyc_extract_258 = PE_INT_WALLACE_DOT8_TREE_W16_in3[14]; +assign pyc_xor_259 = (pyc_xor_252 ^ pyc_extract_258); +assign pyc_xor_260 = (pyc_xor_259 ^ pyc_or_239); +assign pyc_and_261 = (pyc_xor_252 & pyc_extract_258); +assign pyc_and_262 = (pyc_xor_252 & pyc_or_239); +assign pyc_or_263 = (pyc_and_261 | pyc_and_262); +assign pyc_and_264 = (pyc_extract_258 & pyc_or_239); +assign pyc_or_265 = (pyc_or_263 | pyc_and_264); +assign pyc_extract_266 = PE_INT_WALLACE_DOT8_TREE_W16_in0[15]; +assign pyc_extract_267 = PE_INT_WALLACE_DOT8_TREE_W16_in1[15]; +assign pyc_extract_268 = PE_INT_WALLACE_DOT8_TREE_W16_in2[15]; +assign pyc_xor_269 = (pyc_extract_266 ^ pyc_extract_267); +assign pyc_xor_270 = (pyc_xor_269 ^ pyc_extract_268); +assign pyc_extract_271 = PE_INT_WALLACE_DOT8_TREE_W16_in3[15]; +assign pyc_xor_272 = (pyc_xor_270 ^ pyc_extract_271); +assign pyc_xor_273 = (pyc_xor_272 ^ pyc_or_257); +assign pyc_extract_274 = PE_INT_WALLACE_DOT8_TREE_W16_in4[0]; +assign pyc_extract_275 = PE_INT_WALLACE_DOT8_TREE_W16_in5[0]; +assign pyc_extract_276 = PE_INT_WALLACE_DOT8_TREE_W16_in6[0]; +assign pyc_xor_277 = (pyc_extract_274 ^ pyc_extract_275); +assign pyc_xor_278 = (pyc_xor_277 ^ pyc_extract_276); +assign pyc_and_279 = (pyc_extract_274 & pyc_extract_275); +assign pyc_and_280 = (pyc_extract_274 & pyc_extract_276); +assign pyc_or_281 = (pyc_and_279 | pyc_and_280); +assign pyc_and_282 = (pyc_extract_275 & pyc_extract_276); +assign pyc_or_283 = (pyc_or_281 | pyc_and_282); +assign pyc_extract_284 = PE_INT_WALLACE_DOT8_TREE_W16_in7[0]; +assign pyc_xor_285 = (pyc_xor_278 ^ pyc_extract_284); +assign pyc_and_286 = (pyc_xor_278 & pyc_extract_284); +assign pyc_extract_287 = PE_INT_WALLACE_DOT8_TREE_W16_in4[1]; +assign pyc_extract_288 = PE_INT_WALLACE_DOT8_TREE_W16_in5[1]; +assign pyc_extract_289 = PE_INT_WALLACE_DOT8_TREE_W16_in6[1]; +assign pyc_xor_290 = (pyc_extract_287 ^ pyc_extract_288); +assign pyc_xor_291 = (pyc_xor_290 ^ pyc_extract_289); +assign pyc_and_292 = (pyc_extract_287 & pyc_extract_288); +assign pyc_and_293 = (pyc_extract_287 & pyc_extract_289); +assign pyc_or_294 = (pyc_and_292 | pyc_and_293); +assign pyc_and_295 = (pyc_extract_288 & pyc_extract_289); +assign pyc_or_296 = (pyc_or_294 | pyc_and_295); +assign pyc_extract_297 = PE_INT_WALLACE_DOT8_TREE_W16_in7[1]; +assign pyc_xor_298 = (pyc_xor_291 ^ pyc_extract_297); +assign pyc_xor_299 = (pyc_xor_298 ^ pyc_or_283); +assign pyc_and_300 = (pyc_xor_291 & pyc_extract_297); +assign pyc_and_301 = (pyc_xor_291 & pyc_or_283); +assign pyc_or_302 = (pyc_and_300 | pyc_and_301); +assign pyc_and_303 = (pyc_extract_297 & pyc_or_283); +assign pyc_or_304 = (pyc_or_302 | pyc_and_303); +assign pyc_extract_305 = PE_INT_WALLACE_DOT8_TREE_W16_in4[2]; +assign pyc_extract_306 = PE_INT_WALLACE_DOT8_TREE_W16_in5[2]; +assign pyc_extract_307 = PE_INT_WALLACE_DOT8_TREE_W16_in6[2]; +assign pyc_xor_308 = (pyc_extract_305 ^ pyc_extract_306); +assign pyc_xor_309 = (pyc_xor_308 ^ pyc_extract_307); +assign pyc_and_310 = (pyc_extract_305 & pyc_extract_306); +assign pyc_and_311 = (pyc_extract_305 & pyc_extract_307); +assign pyc_or_312 = (pyc_and_310 | pyc_and_311); +assign pyc_and_313 = (pyc_extract_306 & pyc_extract_307); +assign pyc_or_314 = (pyc_or_312 | pyc_and_313); +assign pyc_extract_315 = PE_INT_WALLACE_DOT8_TREE_W16_in7[2]; +assign pyc_xor_316 = (pyc_xor_309 ^ pyc_extract_315); +assign pyc_xor_317 = (pyc_xor_316 ^ pyc_or_296); +assign pyc_and_318 = (pyc_xor_309 & pyc_extract_315); +assign pyc_and_319 = (pyc_xor_309 & pyc_or_296); +assign pyc_or_320 = (pyc_and_318 | pyc_and_319); +assign pyc_and_321 = (pyc_extract_315 & pyc_or_296); +assign pyc_or_322 = (pyc_or_320 | pyc_and_321); +assign pyc_extract_323 = PE_INT_WALLACE_DOT8_TREE_W16_in4[3]; +assign pyc_extract_324 = PE_INT_WALLACE_DOT8_TREE_W16_in5[3]; +assign pyc_extract_325 = PE_INT_WALLACE_DOT8_TREE_W16_in6[3]; +assign pyc_xor_326 = (pyc_extract_323 ^ pyc_extract_324); +assign pyc_xor_327 = (pyc_xor_326 ^ pyc_extract_325); +assign pyc_and_328 = (pyc_extract_323 & pyc_extract_324); +assign pyc_and_329 = (pyc_extract_323 & pyc_extract_325); +assign pyc_or_330 = (pyc_and_328 | pyc_and_329); +assign pyc_and_331 = (pyc_extract_324 & pyc_extract_325); +assign pyc_or_332 = (pyc_or_330 | pyc_and_331); +assign pyc_extract_333 = PE_INT_WALLACE_DOT8_TREE_W16_in7[3]; +assign pyc_xor_334 = (pyc_xor_327 ^ pyc_extract_333); +assign pyc_xor_335 = (pyc_xor_334 ^ pyc_or_314); +assign pyc_and_336 = (pyc_xor_327 & pyc_extract_333); +assign pyc_and_337 = (pyc_xor_327 & pyc_or_314); +assign pyc_or_338 = (pyc_and_336 | pyc_and_337); +assign pyc_and_339 = (pyc_extract_333 & pyc_or_314); +assign pyc_or_340 = (pyc_or_338 | pyc_and_339); +assign pyc_extract_341 = PE_INT_WALLACE_DOT8_TREE_W16_in4[4]; +assign pyc_extract_342 = PE_INT_WALLACE_DOT8_TREE_W16_in5[4]; +assign pyc_extract_343 = PE_INT_WALLACE_DOT8_TREE_W16_in6[4]; +assign pyc_xor_344 = (pyc_extract_341 ^ pyc_extract_342); +assign pyc_xor_345 = (pyc_xor_344 ^ pyc_extract_343); +assign pyc_and_346 = (pyc_extract_341 & pyc_extract_342); +assign pyc_and_347 = (pyc_extract_341 & pyc_extract_343); +assign pyc_or_348 = (pyc_and_346 | pyc_and_347); +assign pyc_and_349 = (pyc_extract_342 & pyc_extract_343); +assign pyc_or_350 = (pyc_or_348 | pyc_and_349); +assign pyc_extract_351 = PE_INT_WALLACE_DOT8_TREE_W16_in7[4]; +assign pyc_xor_352 = (pyc_xor_345 ^ pyc_extract_351); +assign pyc_xor_353 = (pyc_xor_352 ^ pyc_or_332); +assign pyc_and_354 = (pyc_xor_345 & pyc_extract_351); +assign pyc_and_355 = (pyc_xor_345 & pyc_or_332); +assign pyc_or_356 = (pyc_and_354 | pyc_and_355); +assign pyc_and_357 = (pyc_extract_351 & pyc_or_332); +assign pyc_or_358 = (pyc_or_356 | pyc_and_357); +assign pyc_extract_359 = PE_INT_WALLACE_DOT8_TREE_W16_in4[5]; +assign pyc_extract_360 = PE_INT_WALLACE_DOT8_TREE_W16_in5[5]; +assign pyc_extract_361 = PE_INT_WALLACE_DOT8_TREE_W16_in6[5]; +assign pyc_xor_362 = (pyc_extract_359 ^ pyc_extract_360); +assign pyc_xor_363 = (pyc_xor_362 ^ pyc_extract_361); +assign pyc_and_364 = (pyc_extract_359 & pyc_extract_360); +assign pyc_and_365 = (pyc_extract_359 & pyc_extract_361); +assign pyc_or_366 = (pyc_and_364 | pyc_and_365); +assign pyc_and_367 = (pyc_extract_360 & pyc_extract_361); +assign pyc_or_368 = (pyc_or_366 | pyc_and_367); +assign pyc_extract_369 = PE_INT_WALLACE_DOT8_TREE_W16_in7[5]; +assign pyc_xor_370 = (pyc_xor_363 ^ pyc_extract_369); +assign pyc_xor_371 = (pyc_xor_370 ^ pyc_or_350); +assign pyc_and_372 = (pyc_xor_363 & pyc_extract_369); +assign pyc_and_373 = (pyc_xor_363 & pyc_or_350); +assign pyc_or_374 = (pyc_and_372 | pyc_and_373); +assign pyc_and_375 = (pyc_extract_369 & pyc_or_350); +assign pyc_or_376 = (pyc_or_374 | pyc_and_375); +assign pyc_extract_377 = PE_INT_WALLACE_DOT8_TREE_W16_in4[6]; +assign pyc_extract_378 = PE_INT_WALLACE_DOT8_TREE_W16_in5[6]; +assign pyc_extract_379 = PE_INT_WALLACE_DOT8_TREE_W16_in6[6]; +assign pyc_xor_380 = (pyc_extract_377 ^ pyc_extract_378); +assign pyc_xor_381 = (pyc_xor_380 ^ pyc_extract_379); +assign pyc_and_382 = (pyc_extract_377 & pyc_extract_378); +assign pyc_and_383 = (pyc_extract_377 & pyc_extract_379); +assign pyc_or_384 = (pyc_and_382 | pyc_and_383); +assign pyc_and_385 = (pyc_extract_378 & pyc_extract_379); +assign pyc_or_386 = (pyc_or_384 | pyc_and_385); +assign pyc_extract_387 = PE_INT_WALLACE_DOT8_TREE_W16_in7[6]; +assign pyc_xor_388 = (pyc_xor_381 ^ pyc_extract_387); +assign pyc_xor_389 = (pyc_xor_388 ^ pyc_or_368); +assign pyc_and_390 = (pyc_xor_381 & pyc_extract_387); +assign pyc_and_391 = (pyc_xor_381 & pyc_or_368); +assign pyc_or_392 = (pyc_and_390 | pyc_and_391); +assign pyc_and_393 = (pyc_extract_387 & pyc_or_368); +assign pyc_or_394 = (pyc_or_392 | pyc_and_393); +assign pyc_extract_395 = PE_INT_WALLACE_DOT8_TREE_W16_in4[7]; +assign pyc_extract_396 = PE_INT_WALLACE_DOT8_TREE_W16_in5[7]; +assign pyc_extract_397 = PE_INT_WALLACE_DOT8_TREE_W16_in6[7]; +assign pyc_xor_398 = (pyc_extract_395 ^ pyc_extract_396); +assign pyc_xor_399 = (pyc_xor_398 ^ pyc_extract_397); +assign pyc_and_400 = (pyc_extract_395 & pyc_extract_396); +assign pyc_and_401 = (pyc_extract_395 & pyc_extract_397); +assign pyc_or_402 = (pyc_and_400 | pyc_and_401); +assign pyc_and_403 = (pyc_extract_396 & pyc_extract_397); +assign pyc_or_404 = (pyc_or_402 | pyc_and_403); +assign pyc_extract_405 = PE_INT_WALLACE_DOT8_TREE_W16_in7[7]; +assign pyc_xor_406 = (pyc_xor_399 ^ pyc_extract_405); +assign pyc_xor_407 = (pyc_xor_406 ^ pyc_or_386); +assign pyc_and_408 = (pyc_xor_399 & pyc_extract_405); +assign pyc_and_409 = (pyc_xor_399 & pyc_or_386); +assign pyc_or_410 = (pyc_and_408 | pyc_and_409); +assign pyc_and_411 = (pyc_extract_405 & pyc_or_386); +assign pyc_or_412 = (pyc_or_410 | pyc_and_411); +assign pyc_extract_413 = PE_INT_WALLACE_DOT8_TREE_W16_in4[8]; +assign pyc_extract_414 = PE_INT_WALLACE_DOT8_TREE_W16_in5[8]; +assign pyc_extract_415 = PE_INT_WALLACE_DOT8_TREE_W16_in6[8]; +assign pyc_xor_416 = (pyc_extract_413 ^ pyc_extract_414); +assign pyc_xor_417 = (pyc_xor_416 ^ pyc_extract_415); +assign pyc_and_418 = (pyc_extract_413 & pyc_extract_414); +assign pyc_and_419 = (pyc_extract_413 & pyc_extract_415); +assign pyc_or_420 = (pyc_and_418 | pyc_and_419); +assign pyc_and_421 = (pyc_extract_414 & pyc_extract_415); +assign pyc_or_422 = (pyc_or_420 | pyc_and_421); +assign pyc_extract_423 = PE_INT_WALLACE_DOT8_TREE_W16_in7[8]; +assign pyc_xor_424 = (pyc_xor_417 ^ pyc_extract_423); +assign pyc_xor_425 = (pyc_xor_424 ^ pyc_or_404); +assign pyc_and_426 = (pyc_xor_417 & pyc_extract_423); +assign pyc_and_427 = (pyc_xor_417 & pyc_or_404); +assign pyc_or_428 = (pyc_and_426 | pyc_and_427); +assign pyc_and_429 = (pyc_extract_423 & pyc_or_404); +assign pyc_or_430 = (pyc_or_428 | pyc_and_429); +assign pyc_extract_431 = PE_INT_WALLACE_DOT8_TREE_W16_in4[9]; +assign pyc_extract_432 = PE_INT_WALLACE_DOT8_TREE_W16_in5[9]; +assign pyc_extract_433 = PE_INT_WALLACE_DOT8_TREE_W16_in6[9]; +assign pyc_xor_434 = (pyc_extract_431 ^ pyc_extract_432); +assign pyc_xor_435 = (pyc_xor_434 ^ pyc_extract_433); +assign pyc_and_436 = (pyc_extract_431 & pyc_extract_432); +assign pyc_and_437 = (pyc_extract_431 & pyc_extract_433); +assign pyc_or_438 = (pyc_and_436 | pyc_and_437); +assign pyc_and_439 = (pyc_extract_432 & pyc_extract_433); +assign pyc_or_440 = (pyc_or_438 | pyc_and_439); +assign pyc_extract_441 = PE_INT_WALLACE_DOT8_TREE_W16_in7[9]; +assign pyc_xor_442 = (pyc_xor_435 ^ pyc_extract_441); +assign pyc_xor_443 = (pyc_xor_442 ^ pyc_or_422); +assign pyc_and_444 = (pyc_xor_435 & pyc_extract_441); +assign pyc_and_445 = (pyc_xor_435 & pyc_or_422); +assign pyc_or_446 = (pyc_and_444 | pyc_and_445); +assign pyc_and_447 = (pyc_extract_441 & pyc_or_422); +assign pyc_or_448 = (pyc_or_446 | pyc_and_447); +assign pyc_extract_449 = PE_INT_WALLACE_DOT8_TREE_W16_in4[10]; +assign pyc_extract_450 = PE_INT_WALLACE_DOT8_TREE_W16_in5[10]; +assign pyc_extract_451 = PE_INT_WALLACE_DOT8_TREE_W16_in6[10]; +assign pyc_xor_452 = (pyc_extract_449 ^ pyc_extract_450); +assign pyc_xor_453 = (pyc_xor_452 ^ pyc_extract_451); +assign pyc_and_454 = (pyc_extract_449 & pyc_extract_450); +assign pyc_and_455 = (pyc_extract_449 & pyc_extract_451); +assign pyc_or_456 = (pyc_and_454 | pyc_and_455); +assign pyc_and_457 = (pyc_extract_450 & pyc_extract_451); +assign pyc_or_458 = (pyc_or_456 | pyc_and_457); +assign pyc_extract_459 = PE_INT_WALLACE_DOT8_TREE_W16_in7[10]; +assign pyc_xor_460 = (pyc_xor_453 ^ pyc_extract_459); +assign pyc_xor_461 = (pyc_xor_460 ^ pyc_or_440); +assign pyc_and_462 = (pyc_xor_453 & pyc_extract_459); +assign pyc_and_463 = (pyc_xor_453 & pyc_or_440); +assign pyc_or_464 = (pyc_and_462 | pyc_and_463); +assign pyc_and_465 = (pyc_extract_459 & pyc_or_440); +assign pyc_or_466 = (pyc_or_464 | pyc_and_465); +assign pyc_extract_467 = PE_INT_WALLACE_DOT8_TREE_W16_in4[11]; +assign pyc_extract_468 = PE_INT_WALLACE_DOT8_TREE_W16_in5[11]; +assign pyc_extract_469 = PE_INT_WALLACE_DOT8_TREE_W16_in6[11]; +assign pyc_xor_470 = (pyc_extract_467 ^ pyc_extract_468); +assign pyc_xor_471 = (pyc_xor_470 ^ pyc_extract_469); +assign pyc_and_472 = (pyc_extract_467 & pyc_extract_468); +assign pyc_and_473 = (pyc_extract_467 & pyc_extract_469); +assign pyc_or_474 = (pyc_and_472 | pyc_and_473); +assign pyc_and_475 = (pyc_extract_468 & pyc_extract_469); +assign pyc_or_476 = (pyc_or_474 | pyc_and_475); +assign pyc_extract_477 = PE_INT_WALLACE_DOT8_TREE_W16_in7[11]; +assign pyc_xor_478 = (pyc_xor_471 ^ pyc_extract_477); +assign pyc_xor_479 = (pyc_xor_478 ^ pyc_or_458); +assign pyc_and_480 = (pyc_xor_471 & pyc_extract_477); +assign pyc_and_481 = (pyc_xor_471 & pyc_or_458); +assign pyc_or_482 = (pyc_and_480 | pyc_and_481); +assign pyc_and_483 = (pyc_extract_477 & pyc_or_458); +assign pyc_or_484 = (pyc_or_482 | pyc_and_483); +assign pyc_extract_485 = PE_INT_WALLACE_DOT8_TREE_W16_in4[12]; +assign pyc_extract_486 = PE_INT_WALLACE_DOT8_TREE_W16_in5[12]; +assign pyc_extract_487 = PE_INT_WALLACE_DOT8_TREE_W16_in6[12]; +assign pyc_xor_488 = (pyc_extract_485 ^ pyc_extract_486); +assign pyc_xor_489 = (pyc_xor_488 ^ pyc_extract_487); +assign pyc_and_490 = (pyc_extract_485 & pyc_extract_486); +assign pyc_and_491 = (pyc_extract_485 & pyc_extract_487); +assign pyc_or_492 = (pyc_and_490 | pyc_and_491); +assign pyc_and_493 = (pyc_extract_486 & pyc_extract_487); +assign pyc_or_494 = (pyc_or_492 | pyc_and_493); +assign pyc_extract_495 = PE_INT_WALLACE_DOT8_TREE_W16_in7[12]; +assign pyc_xor_496 = (pyc_xor_489 ^ pyc_extract_495); +assign pyc_xor_497 = (pyc_xor_496 ^ pyc_or_476); +assign pyc_and_498 = (pyc_xor_489 & pyc_extract_495); +assign pyc_and_499 = (pyc_xor_489 & pyc_or_476); +assign pyc_or_500 = (pyc_and_498 | pyc_and_499); +assign pyc_and_501 = (pyc_extract_495 & pyc_or_476); +assign pyc_or_502 = (pyc_or_500 | pyc_and_501); +assign pyc_extract_503 = PE_INT_WALLACE_DOT8_TREE_W16_in4[13]; +assign pyc_extract_504 = PE_INT_WALLACE_DOT8_TREE_W16_in5[13]; +assign pyc_extract_505 = PE_INT_WALLACE_DOT8_TREE_W16_in6[13]; +assign pyc_xor_506 = (pyc_extract_503 ^ pyc_extract_504); +assign pyc_xor_507 = (pyc_xor_506 ^ pyc_extract_505); +assign pyc_and_508 = (pyc_extract_503 & pyc_extract_504); +assign pyc_and_509 = (pyc_extract_503 & pyc_extract_505); +assign pyc_or_510 = (pyc_and_508 | pyc_and_509); +assign pyc_and_511 = (pyc_extract_504 & pyc_extract_505); +assign pyc_or_512 = (pyc_or_510 | pyc_and_511); +assign pyc_extract_513 = PE_INT_WALLACE_DOT8_TREE_W16_in7[13]; +assign pyc_xor_514 = (pyc_xor_507 ^ pyc_extract_513); +assign pyc_xor_515 = (pyc_xor_514 ^ pyc_or_494); +assign pyc_and_516 = (pyc_xor_507 & pyc_extract_513); +assign pyc_and_517 = (pyc_xor_507 & pyc_or_494); +assign pyc_or_518 = (pyc_and_516 | pyc_and_517); +assign pyc_and_519 = (pyc_extract_513 & pyc_or_494); +assign pyc_or_520 = (pyc_or_518 | pyc_and_519); +assign pyc_extract_521 = PE_INT_WALLACE_DOT8_TREE_W16_in4[14]; +assign pyc_extract_522 = PE_INT_WALLACE_DOT8_TREE_W16_in5[14]; +assign pyc_extract_523 = PE_INT_WALLACE_DOT8_TREE_W16_in6[14]; +assign pyc_xor_524 = (pyc_extract_521 ^ pyc_extract_522); +assign pyc_xor_525 = (pyc_xor_524 ^ pyc_extract_523); +assign pyc_and_526 = (pyc_extract_521 & pyc_extract_522); +assign pyc_and_527 = (pyc_extract_521 & pyc_extract_523); +assign pyc_or_528 = (pyc_and_526 | pyc_and_527); +assign pyc_and_529 = (pyc_extract_522 & pyc_extract_523); +assign pyc_or_530 = (pyc_or_528 | pyc_and_529); +assign pyc_extract_531 = PE_INT_WALLACE_DOT8_TREE_W16_in7[14]; +assign pyc_xor_532 = (pyc_xor_525 ^ pyc_extract_531); +assign pyc_xor_533 = (pyc_xor_532 ^ pyc_or_512); +assign pyc_and_534 = (pyc_xor_525 & pyc_extract_531); +assign pyc_and_535 = (pyc_xor_525 & pyc_or_512); +assign pyc_or_536 = (pyc_and_534 | pyc_and_535); +assign pyc_and_537 = (pyc_extract_531 & pyc_or_512); +assign pyc_or_538 = (pyc_or_536 | pyc_and_537); +assign pyc_extract_539 = PE_INT_WALLACE_DOT8_TREE_W16_in4[15]; +assign pyc_extract_540 = PE_INT_WALLACE_DOT8_TREE_W16_in5[15]; +assign pyc_extract_541 = PE_INT_WALLACE_DOT8_TREE_W16_in6[15]; +assign pyc_xor_542 = (pyc_extract_539 ^ pyc_extract_540); +assign pyc_xor_543 = (pyc_xor_542 ^ pyc_extract_541); +assign pyc_extract_544 = PE_INT_WALLACE_DOT8_TREE_W16_in7[15]; +assign pyc_xor_545 = (pyc_xor_543 ^ pyc_extract_544); +assign pyc_xor_546 = (pyc_xor_545 ^ pyc_or_530); +assign pyc_xor_547 = (pyc_xor_12 ^ pyc_xor_285); +assign pyc_and_548 = (pyc_xor_12 & pyc_xor_285); +assign pyc_xor_549 = (pyc_xor_26 ^ pyc_and_13); +assign pyc_xor_550 = (pyc_xor_549 ^ pyc_xor_299); +assign pyc_and_551 = (pyc_xor_26 & pyc_and_13); +assign pyc_and_552 = (pyc_xor_26 & pyc_xor_299); +assign pyc_or_553 = (pyc_and_551 | pyc_and_552); +assign pyc_and_554 = (pyc_and_13 & pyc_xor_299); +assign pyc_or_555 = (pyc_or_553 | pyc_and_554); +assign pyc_xor_556 = (pyc_xor_550 ^ pyc_and_286); +assign pyc_xor_557 = (pyc_xor_556 ^ pyc_and_548); +assign pyc_and_558 = (pyc_xor_550 & pyc_and_286); +assign pyc_and_559 = (pyc_xor_550 & pyc_and_548); +assign pyc_or_560 = (pyc_and_558 | pyc_and_559); +assign pyc_and_561 = (pyc_and_286 & pyc_and_548); +assign pyc_or_562 = (pyc_or_560 | pyc_and_561); +assign pyc_xor_563 = (pyc_xor_44 ^ pyc_or_31); +assign pyc_xor_564 = (pyc_xor_563 ^ pyc_xor_317); +assign pyc_and_565 = (pyc_xor_44 & pyc_or_31); +assign pyc_and_566 = (pyc_xor_44 & pyc_xor_317); +assign pyc_or_567 = (pyc_and_565 | pyc_and_566); +assign pyc_and_568 = (pyc_or_31 & pyc_xor_317); +assign pyc_or_569 = (pyc_or_567 | pyc_and_568); +assign pyc_xor_570 = (pyc_xor_564 ^ pyc_or_304); +assign pyc_xor_571 = (pyc_xor_570 ^ pyc_or_555); +assign pyc_and_572 = (pyc_xor_564 & pyc_or_304); +assign pyc_and_573 = (pyc_xor_564 & pyc_or_555); +assign pyc_or_574 = (pyc_and_572 | pyc_and_573); +assign pyc_and_575 = (pyc_or_304 & pyc_or_555); +assign pyc_or_576 = (pyc_or_574 | pyc_and_575); +assign pyc_xor_577 = (pyc_xor_62 ^ pyc_or_49); +assign pyc_xor_578 = (pyc_xor_577 ^ pyc_xor_335); +assign pyc_and_579 = (pyc_xor_62 & pyc_or_49); +assign pyc_and_580 = (pyc_xor_62 & pyc_xor_335); +assign pyc_or_581 = (pyc_and_579 | pyc_and_580); +assign pyc_and_582 = (pyc_or_49 & pyc_xor_335); +assign pyc_or_583 = (pyc_or_581 | pyc_and_582); +assign pyc_xor_584 = (pyc_xor_578 ^ pyc_or_322); +assign pyc_xor_585 = (pyc_xor_584 ^ pyc_or_569); +assign pyc_and_586 = (pyc_xor_578 & pyc_or_322); +assign pyc_and_587 = (pyc_xor_578 & pyc_or_569); +assign pyc_or_588 = (pyc_and_586 | pyc_and_587); +assign pyc_and_589 = (pyc_or_322 & pyc_or_569); +assign pyc_or_590 = (pyc_or_588 | pyc_and_589); +assign pyc_xor_591 = (pyc_xor_80 ^ pyc_or_67); +assign pyc_xor_592 = (pyc_xor_591 ^ pyc_xor_353); +assign pyc_and_593 = (pyc_xor_80 & pyc_or_67); +assign pyc_and_594 = (pyc_xor_80 & pyc_xor_353); +assign pyc_or_595 = (pyc_and_593 | pyc_and_594); +assign pyc_and_596 = (pyc_or_67 & pyc_xor_353); +assign pyc_or_597 = (pyc_or_595 | pyc_and_596); +assign pyc_xor_598 = (pyc_xor_592 ^ pyc_or_340); +assign pyc_xor_599 = (pyc_xor_598 ^ pyc_or_583); +assign pyc_and_600 = (pyc_xor_592 & pyc_or_340); +assign pyc_and_601 = (pyc_xor_592 & pyc_or_583); +assign pyc_or_602 = (pyc_and_600 | pyc_and_601); +assign pyc_and_603 = (pyc_or_340 & pyc_or_583); +assign pyc_or_604 = (pyc_or_602 | pyc_and_603); +assign pyc_xor_605 = (pyc_xor_98 ^ pyc_or_85); +assign pyc_xor_606 = (pyc_xor_605 ^ pyc_xor_371); +assign pyc_and_607 = (pyc_xor_98 & pyc_or_85); +assign pyc_and_608 = (pyc_xor_98 & pyc_xor_371); +assign pyc_or_609 = (pyc_and_607 | pyc_and_608); +assign pyc_and_610 = (pyc_or_85 & pyc_xor_371); +assign pyc_or_611 = (pyc_or_609 | pyc_and_610); +assign pyc_xor_612 = (pyc_xor_606 ^ pyc_or_358); +assign pyc_xor_613 = (pyc_xor_612 ^ pyc_or_597); +assign pyc_and_614 = (pyc_xor_606 & pyc_or_358); +assign pyc_and_615 = (pyc_xor_606 & pyc_or_597); +assign pyc_or_616 = (pyc_and_614 | pyc_and_615); +assign pyc_and_617 = (pyc_or_358 & pyc_or_597); +assign pyc_or_618 = (pyc_or_616 | pyc_and_617); +assign pyc_xor_619 = (pyc_xor_116 ^ pyc_or_103); +assign pyc_xor_620 = (pyc_xor_619 ^ pyc_xor_389); +assign pyc_and_621 = (pyc_xor_116 & pyc_or_103); +assign pyc_and_622 = (pyc_xor_116 & pyc_xor_389); +assign pyc_or_623 = (pyc_and_621 | pyc_and_622); +assign pyc_and_624 = (pyc_or_103 & pyc_xor_389); +assign pyc_or_625 = (pyc_or_623 | pyc_and_624); +assign pyc_xor_626 = (pyc_xor_620 ^ pyc_or_376); +assign pyc_xor_627 = (pyc_xor_626 ^ pyc_or_611); +assign pyc_and_628 = (pyc_xor_620 & pyc_or_376); +assign pyc_and_629 = (pyc_xor_620 & pyc_or_611); +assign pyc_or_630 = (pyc_and_628 | pyc_and_629); +assign pyc_and_631 = (pyc_or_376 & pyc_or_611); +assign pyc_or_632 = (pyc_or_630 | pyc_and_631); +assign pyc_xor_633 = (pyc_xor_134 ^ pyc_or_121); +assign pyc_xor_634 = (pyc_xor_633 ^ pyc_xor_407); +assign pyc_and_635 = (pyc_xor_134 & pyc_or_121); +assign pyc_and_636 = (pyc_xor_134 & pyc_xor_407); +assign pyc_or_637 = (pyc_and_635 | pyc_and_636); +assign pyc_and_638 = (pyc_or_121 & pyc_xor_407); +assign pyc_or_639 = (pyc_or_637 | pyc_and_638); +assign pyc_xor_640 = (pyc_xor_634 ^ pyc_or_394); +assign pyc_xor_641 = (pyc_xor_640 ^ pyc_or_625); +assign pyc_and_642 = (pyc_xor_634 & pyc_or_394); +assign pyc_and_643 = (pyc_xor_634 & pyc_or_625); +assign pyc_or_644 = (pyc_and_642 | pyc_and_643); +assign pyc_and_645 = (pyc_or_394 & pyc_or_625); +assign pyc_or_646 = (pyc_or_644 | pyc_and_645); +assign pyc_xor_647 = (pyc_xor_152 ^ pyc_or_139); +assign pyc_xor_648 = (pyc_xor_647 ^ pyc_xor_425); +assign pyc_and_649 = (pyc_xor_152 & pyc_or_139); +assign pyc_and_650 = (pyc_xor_152 & pyc_xor_425); +assign pyc_or_651 = (pyc_and_649 | pyc_and_650); +assign pyc_and_652 = (pyc_or_139 & pyc_xor_425); +assign pyc_or_653 = (pyc_or_651 | pyc_and_652); +assign pyc_xor_654 = (pyc_xor_648 ^ pyc_or_412); +assign pyc_xor_655 = (pyc_xor_654 ^ pyc_or_639); +assign pyc_and_656 = (pyc_xor_648 & pyc_or_412); +assign pyc_and_657 = (pyc_xor_648 & pyc_or_639); +assign pyc_or_658 = (pyc_and_656 | pyc_and_657); +assign pyc_and_659 = (pyc_or_412 & pyc_or_639); +assign pyc_or_660 = (pyc_or_658 | pyc_and_659); +assign pyc_xor_661 = (pyc_xor_170 ^ pyc_or_157); +assign pyc_xor_662 = (pyc_xor_661 ^ pyc_xor_443); +assign pyc_and_663 = (pyc_xor_170 & pyc_or_157); +assign pyc_and_664 = (pyc_xor_170 & pyc_xor_443); +assign pyc_or_665 = (pyc_and_663 | pyc_and_664); +assign pyc_and_666 = (pyc_or_157 & pyc_xor_443); +assign pyc_or_667 = (pyc_or_665 | pyc_and_666); +assign pyc_xor_668 = (pyc_xor_662 ^ pyc_or_430); +assign pyc_xor_669 = (pyc_xor_668 ^ pyc_or_653); +assign pyc_and_670 = (pyc_xor_662 & pyc_or_430); +assign pyc_and_671 = (pyc_xor_662 & pyc_or_653); +assign pyc_or_672 = (pyc_and_670 | pyc_and_671); +assign pyc_and_673 = (pyc_or_430 & pyc_or_653); +assign pyc_or_674 = (pyc_or_672 | pyc_and_673); +assign pyc_xor_675 = (pyc_xor_188 ^ pyc_or_175); +assign pyc_xor_676 = (pyc_xor_675 ^ pyc_xor_461); +assign pyc_and_677 = (pyc_xor_188 & pyc_or_175); +assign pyc_and_678 = (pyc_xor_188 & pyc_xor_461); +assign pyc_or_679 = (pyc_and_677 | pyc_and_678); +assign pyc_and_680 = (pyc_or_175 & pyc_xor_461); +assign pyc_or_681 = (pyc_or_679 | pyc_and_680); +assign pyc_xor_682 = (pyc_xor_676 ^ pyc_or_448); +assign pyc_xor_683 = (pyc_xor_682 ^ pyc_or_667); +assign pyc_and_684 = (pyc_xor_676 & pyc_or_448); +assign pyc_and_685 = (pyc_xor_676 & pyc_or_667); +assign pyc_or_686 = (pyc_and_684 | pyc_and_685); +assign pyc_and_687 = (pyc_or_448 & pyc_or_667); +assign pyc_or_688 = (pyc_or_686 | pyc_and_687); +assign pyc_xor_689 = (pyc_xor_206 ^ pyc_or_193); +assign pyc_xor_690 = (pyc_xor_689 ^ pyc_xor_479); +assign pyc_and_691 = (pyc_xor_206 & pyc_or_193); +assign pyc_and_692 = (pyc_xor_206 & pyc_xor_479); +assign pyc_or_693 = (pyc_and_691 | pyc_and_692); +assign pyc_and_694 = (pyc_or_193 & pyc_xor_479); +assign pyc_or_695 = (pyc_or_693 | pyc_and_694); +assign pyc_xor_696 = (pyc_xor_690 ^ pyc_or_466); +assign pyc_xor_697 = (pyc_xor_696 ^ pyc_or_681); +assign pyc_and_698 = (pyc_xor_690 & pyc_or_466); +assign pyc_and_699 = (pyc_xor_690 & pyc_or_681); +assign pyc_or_700 = (pyc_and_698 | pyc_and_699); +assign pyc_and_701 = (pyc_or_466 & pyc_or_681); +assign pyc_or_702 = (pyc_or_700 | pyc_and_701); +assign pyc_xor_703 = (pyc_xor_224 ^ pyc_or_211); +assign pyc_xor_704 = (pyc_xor_703 ^ pyc_xor_497); +assign pyc_and_705 = (pyc_xor_224 & pyc_or_211); +assign pyc_and_706 = (pyc_xor_224 & pyc_xor_497); +assign pyc_or_707 = (pyc_and_705 | pyc_and_706); +assign pyc_and_708 = (pyc_or_211 & pyc_xor_497); +assign pyc_or_709 = (pyc_or_707 | pyc_and_708); +assign pyc_xor_710 = (pyc_xor_704 ^ pyc_or_484); +assign pyc_xor_711 = (pyc_xor_710 ^ pyc_or_695); +assign pyc_and_712 = (pyc_xor_704 & pyc_or_484); +assign pyc_and_713 = (pyc_xor_704 & pyc_or_695); +assign pyc_or_714 = (pyc_and_712 | pyc_and_713); +assign pyc_and_715 = (pyc_or_484 & pyc_or_695); +assign pyc_or_716 = (pyc_or_714 | pyc_and_715); +assign pyc_xor_717 = (pyc_xor_242 ^ pyc_or_229); +assign pyc_xor_718 = (pyc_xor_717 ^ pyc_xor_515); +assign pyc_and_719 = (pyc_xor_242 & pyc_or_229); +assign pyc_and_720 = (pyc_xor_242 & pyc_xor_515); +assign pyc_or_721 = (pyc_and_719 | pyc_and_720); +assign pyc_and_722 = (pyc_or_229 & pyc_xor_515); +assign pyc_or_723 = (pyc_or_721 | pyc_and_722); +assign pyc_xor_724 = (pyc_xor_718 ^ pyc_or_502); +assign pyc_xor_725 = (pyc_xor_724 ^ pyc_or_709); +assign pyc_and_726 = (pyc_xor_718 & pyc_or_502); +assign pyc_and_727 = (pyc_xor_718 & pyc_or_709); +assign pyc_or_728 = (pyc_and_726 | pyc_and_727); +assign pyc_and_729 = (pyc_or_502 & pyc_or_709); +assign pyc_or_730 = (pyc_or_728 | pyc_and_729); +assign pyc_xor_731 = (pyc_xor_260 ^ pyc_or_247); +assign pyc_xor_732 = (pyc_xor_731 ^ pyc_xor_533); +assign pyc_and_733 = (pyc_xor_260 & pyc_or_247); +assign pyc_and_734 = (pyc_xor_260 & pyc_xor_533); +assign pyc_or_735 = (pyc_and_733 | pyc_and_734); +assign pyc_and_736 = (pyc_or_247 & pyc_xor_533); +assign pyc_or_737 = (pyc_or_735 | pyc_and_736); +assign pyc_xor_738 = (pyc_xor_732 ^ pyc_or_520); +assign pyc_xor_739 = (pyc_xor_738 ^ pyc_or_723); +assign pyc_and_740 = (pyc_xor_732 & pyc_or_520); +assign pyc_and_741 = (pyc_xor_732 & pyc_or_723); +assign pyc_or_742 = (pyc_and_740 | pyc_and_741); +assign pyc_and_743 = (pyc_or_520 & pyc_or_723); +assign pyc_or_744 = (pyc_or_742 | pyc_and_743); +assign pyc_xor_745 = (pyc_xor_273 ^ pyc_or_265); +assign pyc_xor_746 = (pyc_xor_745 ^ pyc_xor_546); +assign pyc_xor_747 = (pyc_xor_746 ^ pyc_or_538); +assign pyc_xor_748 = (pyc_xor_747 ^ pyc_or_737); +assign pyc_xor_749 = (pyc_xor_571 ^ pyc_or_562); +assign pyc_xor_750 = (pyc_xor_585 ^ pyc_or_576); +assign pyc_xor_751 = (pyc_xor_599 ^ pyc_or_590); +assign pyc_xor_752 = (pyc_xor_613 ^ pyc_or_604); +assign pyc_xor_753 = (pyc_xor_627 ^ pyc_or_618); +assign pyc_xor_754 = (pyc_xor_641 ^ pyc_or_632); +assign pyc_xor_755 = (pyc_xor_655 ^ pyc_or_646); +assign pyc_xor_756 = (pyc_xor_669 ^ pyc_or_660); +assign pyc_xor_757 = (pyc_xor_683 ^ pyc_or_674); +assign pyc_xor_758 = (pyc_xor_697 ^ pyc_or_688); +assign pyc_xor_759 = (pyc_xor_711 ^ pyc_or_702); +assign pyc_xor_760 = (pyc_xor_725 ^ pyc_or_716); +assign pyc_xor_761 = (pyc_xor_739 ^ pyc_or_730); +assign pyc_xor_762 = (pyc_xor_748 ^ pyc_or_744); +assign pyc_and_763 = (pyc_xor_571 & pyc_or_562); +assign pyc_and_764 = (pyc_xor_585 & pyc_or_576); +assign pyc_and_765 = (pyc_xor_599 & pyc_or_590); +assign pyc_and_766 = (pyc_xor_613 & pyc_or_604); +assign pyc_and_767 = (pyc_xor_627 & pyc_or_618); +assign pyc_and_768 = (pyc_xor_641 & pyc_or_632); +assign pyc_and_769 = (pyc_xor_655 & pyc_or_646); +assign pyc_and_770 = (pyc_xor_669 & pyc_or_660); +assign pyc_and_771 = (pyc_xor_683 & pyc_or_674); +assign pyc_and_772 = (pyc_xor_697 & pyc_or_688); +assign pyc_and_773 = (pyc_xor_711 & pyc_or_702); +assign pyc_and_774 = (pyc_xor_725 & pyc_or_716); +assign pyc_and_775 = (pyc_xor_739 & pyc_or_730); +assign pyc_and_776 = (pyc_xor_750 & pyc_and_763); +assign pyc_or_777 = (pyc_and_764 | pyc_and_776); +assign pyc_and_778 = (pyc_xor_752 & pyc_and_765); +assign pyc_or_779 = (pyc_and_766 | pyc_and_778); +assign pyc_and_780 = (pyc_xor_752 & pyc_xor_751); +assign pyc_and_781 = (pyc_xor_754 & pyc_and_767); +assign pyc_or_782 = (pyc_and_768 | pyc_and_781); +assign pyc_and_783 = (pyc_xor_754 & pyc_xor_753); +assign pyc_and_784 = (pyc_xor_756 & pyc_and_769); +assign pyc_or_785 = (pyc_and_770 | pyc_and_784); +assign pyc_and_786 = (pyc_xor_756 & pyc_xor_755); +assign pyc_and_787 = (pyc_xor_758 & pyc_and_771); +assign pyc_or_788 = (pyc_and_772 | pyc_and_787); +assign pyc_and_789 = (pyc_xor_758 & pyc_xor_757); +assign pyc_and_790 = (pyc_xor_760 & pyc_and_773); +assign pyc_or_791 = (pyc_and_774 | pyc_and_790); +assign pyc_and_792 = (pyc_xor_760 & pyc_xor_759); +assign pyc_and_793 = (pyc_and_783 & pyc_or_779); +assign pyc_or_794 = (pyc_or_782 | pyc_and_793); +assign pyc_and_795 = (pyc_and_783 & pyc_and_780); +assign pyc_and_796 = (pyc_and_789 & pyc_or_785); +assign pyc_or_797 = (pyc_or_788 | pyc_and_796); +assign pyc_and_798 = (pyc_and_789 & pyc_and_786); +assign pyc_and_799 = (pyc_and_795 & pyc_or_777); +assign pyc_or_800 = (pyc_or_794 | pyc_and_799); +assign pyc_and_801 = (pyc_and_798 & pyc_or_800); +assign pyc_or_802 = (pyc_or_797 | pyc_and_801); +assign pyc_and_803 = (pyc_and_780 & pyc_or_777); +assign pyc_or_804 = (pyc_or_779 | pyc_and_803); +assign pyc_and_805 = (pyc_and_786 & pyc_or_800); +assign pyc_or_806 = (pyc_or_785 | pyc_and_805); +assign pyc_and_807 = (pyc_and_792 & pyc_or_802); +assign pyc_or_808 = (pyc_or_791 | pyc_and_807); +assign pyc_and_809 = (pyc_xor_751 & pyc_or_777); +assign pyc_or_810 = (pyc_and_765 | pyc_and_809); +assign pyc_and_811 = (pyc_xor_753 & pyc_or_804); +assign pyc_or_812 = (pyc_and_767 | pyc_and_811); +assign pyc_and_813 = (pyc_xor_755 & pyc_or_800); +assign pyc_or_814 = (pyc_and_769 | pyc_and_813); +assign pyc_and_815 = (pyc_xor_757 & pyc_or_806); +assign pyc_or_816 = (pyc_and_771 | pyc_and_815); +assign pyc_and_817 = (pyc_xor_759 & pyc_or_802); +assign pyc_or_818 = (pyc_and_773 | pyc_and_817); +assign pyc_and_819 = (pyc_xor_761 & pyc_or_808); +assign pyc_or_820 = (pyc_and_775 | pyc_and_819); +assign pyc_xor_821 = (pyc_xor_750 ^ pyc_and_763); +assign pyc_xor_822 = (pyc_xor_751 ^ pyc_or_777); +assign pyc_xor_823 = (pyc_xor_752 ^ pyc_or_810); +assign pyc_xor_824 = (pyc_xor_753 ^ pyc_or_804); +assign pyc_xor_825 = (pyc_xor_754 ^ pyc_or_812); +assign pyc_xor_826 = (pyc_xor_755 ^ pyc_or_800); +assign pyc_xor_827 = (pyc_xor_756 ^ pyc_or_814); +assign pyc_xor_828 = (pyc_xor_757 ^ pyc_or_806); +assign pyc_xor_829 = (pyc_xor_758 ^ pyc_or_816); +assign pyc_xor_830 = (pyc_xor_759 ^ pyc_or_802); +assign pyc_xor_831 = (pyc_xor_760 ^ pyc_or_818); +assign pyc_xor_832 = (pyc_xor_761 ^ pyc_or_808); +assign pyc_xor_833 = (pyc_xor_762 ^ pyc_or_820); +assign pyc_concat_834 = {pyc_xor_833, pyc_xor_832, pyc_xor_831, pyc_xor_830, pyc_xor_829, pyc_xor_828, pyc_xor_827, pyc_xor_826, pyc_xor_825, pyc_xor_824, pyc_xor_823, pyc_xor_822, pyc_xor_821, pyc_xor_749, pyc_xor_557, pyc_xor_547}; +assign pyc_comb_835 = pyc_concat_834; -assign PE_INT_WALLACE_DOT8_TREE_W16_sum = pyc_comb_753; +assign PE_INT_WALLACE_DOT8_TREE_W16_sum = pyc_comb_835; endmodule diff --git a/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w19.v b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w19.v index cde85bd..601b0f9 100644 --- a/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w19.v +++ b/designs/PE_INT/rtl/build/pe_int_wallace_dot8_tree_w19.v @@ -13,1816 +13,2034 @@ module PE_INT_WALLACE_DOT8_TREE_W19 ( output [18:0] PE_INT_WALLACE_DOT8_TREE_W19_sum ); -wire [18:0] pyc_add_902; // op=pyc.add -wire pyc_and_10; // op=pyc.and wire pyc_and_100; // op=pyc.and -wire pyc_and_101; // op=pyc.and -wire pyc_and_103; // op=pyc.and +wire pyc_and_102; // op=pyc.and +wire pyc_and_109; // op=pyc.and wire pyc_and_110; // op=pyc.and -wire pyc_and_111; // op=pyc.and -wire pyc_and_113; // op=pyc.and +wire pyc_and_112; // op=pyc.and +wire pyc_and_117; // op=pyc.and wire pyc_and_118; // op=pyc.and -wire pyc_and_119; // op=pyc.and -wire pyc_and_121; // op=pyc.and +wire pyc_and_120; // op=pyc.and +wire pyc_and_127; // op=pyc.and wire pyc_and_128; // op=pyc.and -wire pyc_and_129; // op=pyc.and -wire pyc_and_131; // op=pyc.and +wire pyc_and_13; // op=pyc.and +wire pyc_and_130; // op=pyc.and +wire pyc_and_135; // op=pyc.and wire pyc_and_136; // op=pyc.and -wire pyc_and_137; // op=pyc.and -wire pyc_and_139; // op=pyc.and -wire pyc_and_14; // op=pyc.and +wire pyc_and_138; // op=pyc.and +wire pyc_and_145; // op=pyc.and wire pyc_and_146; // op=pyc.and -wire pyc_and_147; // op=pyc.and -wire pyc_and_149; // op=pyc.and +wire pyc_and_148; // op=pyc.and +wire pyc_and_153; // op=pyc.and wire pyc_and_154; // op=pyc.and -wire pyc_and_155; // op=pyc.and -wire pyc_and_157; // op=pyc.and +wire pyc_and_156; // op=pyc.and +wire pyc_and_163; // op=pyc.and wire pyc_and_164; // op=pyc.and -wire pyc_and_165; // op=pyc.and -wire pyc_and_167; // op=pyc.and +wire pyc_and_166; // op=pyc.and +wire pyc_and_171; // op=pyc.and wire pyc_and_172; // op=pyc.and -wire pyc_and_173; // op=pyc.and -wire pyc_and_175; // op=pyc.and +wire pyc_and_174; // op=pyc.and +wire pyc_and_181; // op=pyc.and wire pyc_and_182; // op=pyc.and -wire pyc_and_183; // op=pyc.and -wire pyc_and_185; // op=pyc.and +wire pyc_and_184; // op=pyc.and +wire pyc_and_189; // op=pyc.and +wire pyc_and_19; // op=pyc.and wire pyc_and_190; // op=pyc.and -wire pyc_and_191; // op=pyc.and -wire pyc_and_193; // op=pyc.and +wire pyc_and_192; // op=pyc.and +wire pyc_and_199; // op=pyc.and wire pyc_and_20; // op=pyc.and wire pyc_and_200; // op=pyc.and -wire pyc_and_201; // op=pyc.and -wire pyc_and_203; // op=pyc.and +wire pyc_and_202; // op=pyc.and +wire pyc_and_207; // op=pyc.and wire pyc_and_208; // op=pyc.and -wire pyc_and_209; // op=pyc.and -wire pyc_and_21; // op=pyc.and -wire pyc_and_211; // op=pyc.and +wire pyc_and_210; // op=pyc.and +wire pyc_and_217; // op=pyc.and wire pyc_and_218; // op=pyc.and -wire pyc_and_219; // op=pyc.and -wire pyc_and_221; // op=pyc.and +wire pyc_and_22; // op=pyc.and +wire pyc_and_220; // op=pyc.and +wire pyc_and_225; // op=pyc.and wire pyc_and_226; // op=pyc.and -wire pyc_and_227; // op=pyc.and -wire pyc_and_229; // op=pyc.and -wire pyc_and_23; // op=pyc.and +wire pyc_and_228; // op=pyc.and +wire pyc_and_235; // op=pyc.and wire pyc_and_236; // op=pyc.and -wire pyc_and_237; // op=pyc.and -wire pyc_and_239; // op=pyc.and +wire pyc_and_238; // op=pyc.and +wire pyc_and_243; // op=pyc.and wire pyc_and_244; // op=pyc.and -wire pyc_and_245; // op=pyc.and -wire pyc_and_247; // op=pyc.and +wire pyc_and_246; // op=pyc.and +wire pyc_and_253; // op=pyc.and wire pyc_and_254; // op=pyc.and -wire pyc_and_255; // op=pyc.and -wire pyc_and_257; // op=pyc.and +wire pyc_and_256; // op=pyc.and +wire pyc_and_261; // op=pyc.and wire pyc_and_262; // op=pyc.and -wire pyc_and_263; // op=pyc.and -wire pyc_and_265; // op=pyc.and +wire pyc_and_264; // op=pyc.and +wire pyc_and_27; // op=pyc.and +wire pyc_and_271; // op=pyc.and wire pyc_and_272; // op=pyc.and -wire pyc_and_273; // op=pyc.and -wire pyc_and_275; // op=pyc.and +wire pyc_and_274; // op=pyc.and +wire pyc_and_279; // op=pyc.and wire pyc_and_28; // op=pyc.and wire pyc_and_280; // op=pyc.and -wire pyc_and_281; // op=pyc.and -wire pyc_and_283; // op=pyc.and -wire pyc_and_29; // op=pyc.and +wire pyc_and_282; // op=pyc.and +wire pyc_and_289; // op=pyc.and wire pyc_and_290; // op=pyc.and -wire pyc_and_291; // op=pyc.and -wire pyc_and_293; // op=pyc.and +wire pyc_and_292; // op=pyc.and +wire pyc_and_297; // op=pyc.and wire pyc_and_298; // op=pyc.and -wire pyc_and_299; // op=pyc.and -wire pyc_and_301; // op=pyc.and +wire pyc_and_30; // op=pyc.and +wire pyc_and_300; // op=pyc.and +wire pyc_and_307; // op=pyc.and wire pyc_and_308; // op=pyc.and -wire pyc_and_309; // op=pyc.and -wire pyc_and_31; // op=pyc.and -wire pyc_and_311; // op=pyc.and +wire pyc_and_310; // op=pyc.and +wire pyc_and_315; // op=pyc.and wire pyc_and_316; // op=pyc.and -wire pyc_and_317; // op=pyc.and -wire pyc_and_319; // op=pyc.and +wire pyc_and_318; // op=pyc.and +wire pyc_and_333; // op=pyc.and wire pyc_and_334; // op=pyc.and -wire pyc_and_335; // op=pyc.and -wire pyc_and_337; // op=pyc.and -wire pyc_and_341; // op=pyc.and +wire pyc_and_336; // op=pyc.and +wire pyc_and_340; // op=pyc.and +wire pyc_and_346; // op=pyc.and wire pyc_and_347; // op=pyc.and -wire pyc_and_348; // op=pyc.and -wire pyc_and_350; // op=pyc.and +wire pyc_and_349; // op=pyc.and +wire pyc_and_354; // op=pyc.and wire pyc_and_355; // op=pyc.and -wire pyc_and_356; // op=pyc.and -wire pyc_and_358; // op=pyc.and +wire pyc_and_357; // op=pyc.and +wire pyc_and_364; // op=pyc.and wire pyc_and_365; // op=pyc.and -wire pyc_and_366; // op=pyc.and -wire pyc_and_368; // op=pyc.and +wire pyc_and_367; // op=pyc.and +wire pyc_and_37; // op=pyc.and +wire pyc_and_372; // op=pyc.and wire pyc_and_373; // op=pyc.and -wire pyc_and_374; // op=pyc.and -wire pyc_and_376; // op=pyc.and +wire pyc_and_375; // op=pyc.and wire pyc_and_38; // op=pyc.and +wire pyc_and_382; // op=pyc.and wire pyc_and_383; // op=pyc.and -wire pyc_and_384; // op=pyc.and -wire pyc_and_386; // op=pyc.and -wire pyc_and_39; // op=pyc.and +wire pyc_and_385; // op=pyc.and +wire pyc_and_390; // op=pyc.and wire pyc_and_391; // op=pyc.and -wire pyc_and_392; // op=pyc.and -wire pyc_and_394; // op=pyc.and +wire pyc_and_393; // op=pyc.and +wire pyc_and_40; // op=pyc.and +wire pyc_and_400; // op=pyc.and wire pyc_and_401; // op=pyc.and -wire pyc_and_402; // op=pyc.and -wire pyc_and_404; // op=pyc.and +wire pyc_and_403; // op=pyc.and +wire pyc_and_408; // op=pyc.and wire pyc_and_409; // op=pyc.and -wire pyc_and_41; // op=pyc.and -wire pyc_and_410; // op=pyc.and -wire pyc_and_412; // op=pyc.and +wire pyc_and_411; // op=pyc.and +wire pyc_and_418; // op=pyc.and wire pyc_and_419; // op=pyc.and -wire pyc_and_420; // op=pyc.and -wire pyc_and_422; // op=pyc.and +wire pyc_and_421; // op=pyc.and +wire pyc_and_426; // op=pyc.and wire pyc_and_427; // op=pyc.and -wire pyc_and_428; // op=pyc.and -wire pyc_and_430; // op=pyc.and +wire pyc_and_429; // op=pyc.and +wire pyc_and_436; // op=pyc.and wire pyc_and_437; // op=pyc.and -wire pyc_and_438; // op=pyc.and -wire pyc_and_440; // op=pyc.and +wire pyc_and_439; // op=pyc.and +wire pyc_and_444; // op=pyc.and wire pyc_and_445; // op=pyc.and -wire pyc_and_446; // op=pyc.and -wire pyc_and_448; // op=pyc.and +wire pyc_and_447; // op=pyc.and +wire pyc_and_45; // op=pyc.and +wire pyc_and_454; // op=pyc.and wire pyc_and_455; // op=pyc.and -wire pyc_and_456; // op=pyc.and -wire pyc_and_458; // op=pyc.and +wire pyc_and_457; // op=pyc.and wire pyc_and_46; // op=pyc.and +wire pyc_and_462; // op=pyc.and wire pyc_and_463; // op=pyc.and -wire pyc_and_464; // op=pyc.and -wire pyc_and_466; // op=pyc.and -wire pyc_and_47; // op=pyc.and +wire pyc_and_465; // op=pyc.and +wire pyc_and_472; // op=pyc.and wire pyc_and_473; // op=pyc.and -wire pyc_and_474; // op=pyc.and -wire pyc_and_476; // op=pyc.and +wire pyc_and_475; // op=pyc.and +wire pyc_and_48; // op=pyc.and +wire pyc_and_480; // op=pyc.and wire pyc_and_481; // op=pyc.and -wire pyc_and_482; // op=pyc.and -wire pyc_and_484; // op=pyc.and -wire pyc_and_49; // op=pyc.and +wire pyc_and_483; // op=pyc.and +wire pyc_and_490; // op=pyc.and wire pyc_and_491; // op=pyc.and -wire pyc_and_492; // op=pyc.and -wire pyc_and_494; // op=pyc.and +wire pyc_and_493; // op=pyc.and +wire pyc_and_498; // op=pyc.and wire pyc_and_499; // op=pyc.and -wire pyc_and_500; // op=pyc.and -wire pyc_and_502; // op=pyc.and +wire pyc_and_501; // op=pyc.and +wire pyc_and_508; // op=pyc.and wire pyc_and_509; // op=pyc.and -wire pyc_and_510; // op=pyc.and -wire pyc_and_512; // op=pyc.and +wire pyc_and_511; // op=pyc.and +wire pyc_and_516; // op=pyc.and wire pyc_and_517; // op=pyc.and -wire pyc_and_518; // op=pyc.and -wire pyc_and_520; // op=pyc.and +wire pyc_and_519; // op=pyc.and +wire pyc_and_526; // op=pyc.and wire pyc_and_527; // op=pyc.and -wire pyc_and_528; // op=pyc.and -wire pyc_and_530; // op=pyc.and +wire pyc_and_529; // op=pyc.and +wire pyc_and_534; // op=pyc.and wire pyc_and_535; // op=pyc.and -wire pyc_and_536; // op=pyc.and -wire pyc_and_538; // op=pyc.and +wire pyc_and_537; // op=pyc.and +wire pyc_and_544; // op=pyc.and wire pyc_and_545; // op=pyc.and -wire pyc_and_546; // op=pyc.and -wire pyc_and_548; // op=pyc.and +wire pyc_and_547; // op=pyc.and +wire pyc_and_55; // op=pyc.and +wire pyc_and_552; // op=pyc.and wire pyc_and_553; // op=pyc.and -wire pyc_and_554; // op=pyc.and -wire pyc_and_556; // op=pyc.and +wire pyc_and_555; // op=pyc.and wire pyc_and_56; // op=pyc.and +wire pyc_and_562; // op=pyc.and wire pyc_and_563; // op=pyc.and -wire pyc_and_564; // op=pyc.and -wire pyc_and_566; // op=pyc.and -wire pyc_and_57; // op=pyc.and +wire pyc_and_565; // op=pyc.and +wire pyc_and_570; // op=pyc.and wire pyc_and_571; // op=pyc.and -wire pyc_and_572; // op=pyc.and -wire pyc_and_574; // op=pyc.and +wire pyc_and_573; // op=pyc.and +wire pyc_and_58; // op=pyc.and +wire pyc_and_580; // op=pyc.and wire pyc_and_581; // op=pyc.and -wire pyc_and_582; // op=pyc.and -wire pyc_and_584; // op=pyc.and +wire pyc_and_583; // op=pyc.and +wire pyc_and_588; // op=pyc.and wire pyc_and_589; // op=pyc.and -wire pyc_and_59; // op=pyc.and -wire pyc_and_590; // op=pyc.and -wire pyc_and_592; // op=pyc.and +wire pyc_and_591; // op=pyc.and +wire pyc_and_598; // op=pyc.and wire pyc_and_599; // op=pyc.and -wire pyc_and_600; // op=pyc.and -wire pyc_and_602; // op=pyc.and +wire pyc_and_6; // op=pyc.and +wire pyc_and_601; // op=pyc.and +wire pyc_and_606; // op=pyc.and wire pyc_and_607; // op=pyc.and -wire pyc_and_608; // op=pyc.and -wire pyc_and_610; // op=pyc.and +wire pyc_and_609; // op=pyc.and +wire pyc_and_616; // op=pyc.and wire pyc_and_617; // op=pyc.and -wire pyc_and_618; // op=pyc.and -wire pyc_and_620; // op=pyc.and +wire pyc_and_619; // op=pyc.and +wire pyc_and_624; // op=pyc.and wire pyc_and_625; // op=pyc.and -wire pyc_and_626; // op=pyc.and -wire pyc_and_628; // op=pyc.and +wire pyc_and_627; // op=pyc.and +wire pyc_and_63; // op=pyc.and +wire pyc_and_634; // op=pyc.and wire pyc_and_635; // op=pyc.and -wire pyc_and_636; // op=pyc.and -wire pyc_and_638; // op=pyc.and +wire pyc_and_637; // op=pyc.and wire pyc_and_64; // op=pyc.and +wire pyc_and_642; // op=pyc.and wire pyc_and_643; // op=pyc.and -wire pyc_and_644; // op=pyc.and -wire pyc_and_646; // op=pyc.and -wire pyc_and_65; // op=pyc.and -wire pyc_and_657; // op=pyc.and +wire pyc_and_645; // op=pyc.and +wire pyc_and_656; // op=pyc.and +wire pyc_and_659; // op=pyc.and +wire pyc_and_66; // op=pyc.and wire pyc_and_660; // op=pyc.and -wire pyc_and_661; // op=pyc.and -wire pyc_and_663; // op=pyc.and +wire pyc_and_662; // op=pyc.and +wire pyc_and_666; // op=pyc.and wire pyc_and_667; // op=pyc.and -wire pyc_and_668; // op=pyc.and -wire pyc_and_67; // op=pyc.and -wire pyc_and_670; // op=pyc.and +wire pyc_and_669; // op=pyc.and +wire pyc_and_673; // op=pyc.and wire pyc_and_674; // op=pyc.and -wire pyc_and_675; // op=pyc.and -wire pyc_and_677; // op=pyc.and +wire pyc_and_676; // op=pyc.and +wire pyc_and_680; // op=pyc.and wire pyc_and_681; // op=pyc.and -wire pyc_and_682; // op=pyc.and -wire pyc_and_684; // op=pyc.and +wire pyc_and_683; // op=pyc.and +wire pyc_and_687; // op=pyc.and wire pyc_and_688; // op=pyc.and -wire pyc_and_689; // op=pyc.and -wire pyc_and_691; // op=pyc.and +wire pyc_and_690; // op=pyc.and +wire pyc_and_694; // op=pyc.and wire pyc_and_695; // op=pyc.and -wire pyc_and_696; // op=pyc.and -wire pyc_and_698; // op=pyc.and +wire pyc_and_697; // op=pyc.and wire pyc_and_7; // op=pyc.and +wire pyc_and_701; // op=pyc.and wire pyc_and_702; // op=pyc.and -wire pyc_and_703; // op=pyc.and -wire pyc_and_705; // op=pyc.and +wire pyc_and_704; // op=pyc.and +wire pyc_and_708; // op=pyc.and wire pyc_and_709; // op=pyc.and -wire pyc_and_710; // op=pyc.and -wire pyc_and_712; // op=pyc.and +wire pyc_and_711; // op=pyc.and +wire pyc_and_715; // op=pyc.and wire pyc_and_716; // op=pyc.and -wire pyc_and_717; // op=pyc.and -wire pyc_and_719; // op=pyc.and +wire pyc_and_718; // op=pyc.and +wire pyc_and_722; // op=pyc.and wire pyc_and_723; // op=pyc.and -wire pyc_and_724; // op=pyc.and -wire pyc_and_726; // op=pyc.and +wire pyc_and_725; // op=pyc.and +wire pyc_and_729; // op=pyc.and +wire pyc_and_73; // op=pyc.and wire pyc_and_730; // op=pyc.and -wire pyc_and_731; // op=pyc.and -wire pyc_and_733; // op=pyc.and +wire pyc_and_732; // op=pyc.and +wire pyc_and_736; // op=pyc.and wire pyc_and_737; // op=pyc.and -wire pyc_and_738; // op=pyc.and +wire pyc_and_739; // op=pyc.and wire pyc_and_74; // op=pyc.and -wire pyc_and_740; // op=pyc.and +wire pyc_and_743; // op=pyc.and wire pyc_and_744; // op=pyc.and -wire pyc_and_745; // op=pyc.and -wire pyc_and_747; // op=pyc.and -wire pyc_and_75; // op=pyc.and +wire pyc_and_746; // op=pyc.and +wire pyc_and_750; // op=pyc.and wire pyc_and_751; // op=pyc.and -wire pyc_and_752; // op=pyc.and -wire pyc_and_754; // op=pyc.and +wire pyc_and_753; // op=pyc.and +wire pyc_and_757; // op=pyc.and wire pyc_and_758; // op=pyc.and -wire pyc_and_759; // op=pyc.and -wire pyc_and_761; // op=pyc.and +wire pyc_and_76; // op=pyc.and +wire pyc_and_760; // op=pyc.and +wire pyc_and_764; // op=pyc.and wire pyc_and_765; // op=pyc.and -wire pyc_and_766; // op=pyc.and -wire pyc_and_768; // op=pyc.and -wire pyc_and_77; // op=pyc.and +wire pyc_and_767; // op=pyc.and +wire pyc_and_771; // op=pyc.and wire pyc_and_772; // op=pyc.and -wire pyc_and_773; // op=pyc.and -wire pyc_and_775; // op=pyc.and +wire pyc_and_774; // op=pyc.and +wire pyc_and_778; // op=pyc.and wire pyc_and_779; // op=pyc.and -wire pyc_and_780; // op=pyc.and -wire pyc_and_782; // op=pyc.and +wire pyc_and_781; // op=pyc.and +wire pyc_and_785; // op=pyc.and wire pyc_and_786; // op=pyc.and -wire pyc_and_787; // op=pyc.and -wire pyc_and_789; // op=pyc.and +wire pyc_and_788; // op=pyc.and +wire pyc_and_792; // op=pyc.and wire pyc_and_793; // op=pyc.and -wire pyc_and_794; // op=pyc.and -wire pyc_and_796; // op=pyc.and -wire pyc_and_8; // op=pyc.and +wire pyc_and_795; // op=pyc.and +wire pyc_and_799; // op=pyc.and wire pyc_and_800; // op=pyc.and -wire pyc_and_801; // op=pyc.and -wire pyc_and_803; // op=pyc.and +wire pyc_and_802; // op=pyc.and +wire pyc_and_806; // op=pyc.and wire pyc_and_807; // op=pyc.and -wire pyc_and_808; // op=pyc.and -wire pyc_and_810; // op=pyc.and +wire pyc_and_809; // op=pyc.and +wire pyc_and_81; // op=pyc.and +wire pyc_and_813; // op=pyc.and wire pyc_and_814; // op=pyc.and -wire pyc_and_815; // op=pyc.and -wire pyc_and_817; // op=pyc.and +wire pyc_and_816; // op=pyc.and wire pyc_and_82; // op=pyc.and +wire pyc_and_820; // op=pyc.and wire pyc_and_821; // op=pyc.and -wire pyc_and_822; // op=pyc.and -wire pyc_and_824; // op=pyc.and +wire pyc_and_823; // op=pyc.and +wire pyc_and_827; // op=pyc.and wire pyc_and_828; // op=pyc.and -wire pyc_and_829; // op=pyc.and -wire pyc_and_83; // op=pyc.and -wire pyc_and_831; // op=pyc.and +wire pyc_and_830; // op=pyc.and +wire pyc_and_834; // op=pyc.and wire pyc_and_835; // op=pyc.and -wire pyc_and_836; // op=pyc.and -wire pyc_and_838; // op=pyc.and +wire pyc_and_837; // op=pyc.and +wire pyc_and_84; // op=pyc.and +wire pyc_and_841; // op=pyc.and wire pyc_and_842; // op=pyc.and -wire pyc_and_843; // op=pyc.and -wire pyc_and_845; // op=pyc.and +wire pyc_and_844; // op=pyc.and +wire pyc_and_848; // op=pyc.and wire pyc_and_849; // op=pyc.and -wire pyc_and_85; // op=pyc.and -wire pyc_and_850; // op=pyc.and -wire pyc_and_852; // op=pyc.and +wire pyc_and_851; // op=pyc.and +wire pyc_and_855; // op=pyc.and wire pyc_and_856; // op=pyc.and -wire pyc_and_857; // op=pyc.and -wire pyc_and_859; // op=pyc.and +wire pyc_and_858; // op=pyc.and +wire pyc_and_862; // op=pyc.and wire pyc_and_863; // op=pyc.and -wire pyc_and_864; // op=pyc.and -wire pyc_and_866; // op=pyc.and +wire pyc_and_865; // op=pyc.and +wire pyc_and_869; // op=pyc.and wire pyc_and_870; // op=pyc.and -wire pyc_and_871; // op=pyc.and -wire pyc_and_873; // op=pyc.and +wire pyc_and_872; // op=pyc.and +wire pyc_and_876; // op=pyc.and wire pyc_and_877; // op=pyc.and -wire pyc_and_878; // op=pyc.and -wire pyc_and_880; // op=pyc.and +wire pyc_and_879; // op=pyc.and +wire pyc_and_883; // op=pyc.and wire pyc_and_884; // op=pyc.and -wire pyc_and_885; // op=pyc.and -wire pyc_and_887; // op=pyc.and +wire pyc_and_886; // op=pyc.and +wire pyc_and_890; // op=pyc.and wire pyc_and_891; // op=pyc.and -wire pyc_and_892; // op=pyc.and -wire pyc_and_894; // op=pyc.and +wire pyc_and_893; // op=pyc.and +wire pyc_and_9; // op=pyc.and +wire pyc_and_91; // op=pyc.and +wire pyc_and_916; // op=pyc.and +wire pyc_and_917; // op=pyc.and +wire pyc_and_918; // op=pyc.and +wire pyc_and_919; // op=pyc.and wire pyc_and_92; // op=pyc.and -wire pyc_and_93; // op=pyc.and -wire pyc_and_95; // op=pyc.and -wire [18:0] pyc_comb_903; // op=pyc.comb -wire [18:0] pyc_concat_900; // op=pyc.concat -wire [18:0] pyc_concat_901; // op=pyc.concat -wire pyc_constant_1; // op=pyc.constant +wire pyc_and_920; // op=pyc.and +wire pyc_and_921; // op=pyc.and +wire pyc_and_922; // op=pyc.and +wire pyc_and_923; // op=pyc.and +wire pyc_and_924; // op=pyc.and +wire pyc_and_925; // op=pyc.and +wire pyc_and_926; // op=pyc.and +wire pyc_and_927; // op=pyc.and +wire pyc_and_928; // op=pyc.and +wire pyc_and_929; // op=pyc.and +wire pyc_and_930; // op=pyc.and +wire pyc_and_931; // op=pyc.and +wire pyc_and_932; // op=pyc.and +wire pyc_and_934; // op=pyc.and +wire pyc_and_936; // op=pyc.and +wire pyc_and_937; // op=pyc.and +wire pyc_and_939; // op=pyc.and +wire pyc_and_94; // op=pyc.and +wire pyc_and_940; // op=pyc.and +wire pyc_and_942; // op=pyc.and +wire pyc_and_943; // op=pyc.and +wire pyc_and_945; // op=pyc.and +wire pyc_and_946; // op=pyc.and +wire pyc_and_948; // op=pyc.and +wire pyc_and_949; // op=pyc.and +wire pyc_and_951; // op=pyc.and +wire pyc_and_952; // op=pyc.and +wire pyc_and_954; // op=pyc.and +wire pyc_and_955; // op=pyc.and +wire pyc_and_957; // op=pyc.and +wire pyc_and_958; // op=pyc.and +wire pyc_and_960; // op=pyc.and +wire pyc_and_961; // op=pyc.and +wire pyc_and_963; // op=pyc.and +wire pyc_and_964; // op=pyc.and +wire pyc_and_966; // op=pyc.and +wire pyc_and_968; // op=pyc.and +wire pyc_and_969; // op=pyc.and +wire pyc_and_971; // op=pyc.and +wire pyc_and_973; // op=pyc.and +wire pyc_and_975; // op=pyc.and +wire pyc_and_977; // op=pyc.and +wire pyc_and_979; // op=pyc.and +wire pyc_and_981; // op=pyc.and +wire pyc_and_983; // op=pyc.and +wire pyc_and_985; // op=pyc.and +wire pyc_and_987; // op=pyc.and +wire pyc_and_989; // op=pyc.and +wire pyc_and_99; // op=pyc.and +wire pyc_and_991; // op=pyc.and +wire pyc_and_993; // op=pyc.and +wire [18:0] pyc_comb_1012; // op=pyc.comb +wire [18:0] pyc_concat_1011; // op=pyc.concat +wire pyc_extract_1; // op=pyc.extract +wire pyc_extract_104; // op=pyc.extract wire pyc_extract_105; // op=pyc.extract wire pyc_extract_106; // op=pyc.extract -wire pyc_extract_107; // op=pyc.extract -wire pyc_extract_115; // op=pyc.extract -wire pyc_extract_12; // op=pyc.extract +wire pyc_extract_11; // op=pyc.extract +wire pyc_extract_114; // op=pyc.extract +wire pyc_extract_122; // op=pyc.extract wire pyc_extract_123; // op=pyc.extract wire pyc_extract_124; // op=pyc.extract -wire pyc_extract_125; // op=pyc.extract -wire pyc_extract_133; // op=pyc.extract +wire pyc_extract_132; // op=pyc.extract +wire pyc_extract_14; // op=pyc.extract +wire pyc_extract_140; // op=pyc.extract wire pyc_extract_141; // op=pyc.extract wire pyc_extract_142; // op=pyc.extract -wire pyc_extract_143; // op=pyc.extract wire pyc_extract_15; // op=pyc.extract -wire pyc_extract_151; // op=pyc.extract +wire pyc_extract_150; // op=pyc.extract +wire pyc_extract_158; // op=pyc.extract wire pyc_extract_159; // op=pyc.extract wire pyc_extract_16; // op=pyc.extract wire pyc_extract_160; // op=pyc.extract -wire pyc_extract_161; // op=pyc.extract -wire pyc_extract_169; // op=pyc.extract -wire pyc_extract_17; // op=pyc.extract +wire pyc_extract_168; // op=pyc.extract +wire pyc_extract_176; // op=pyc.extract wire pyc_extract_177; // op=pyc.extract wire pyc_extract_178; // op=pyc.extract -wire pyc_extract_179; // op=pyc.extract -wire pyc_extract_187; // op=pyc.extract +wire pyc_extract_186; // op=pyc.extract +wire pyc_extract_194; // op=pyc.extract wire pyc_extract_195; // op=pyc.extract wire pyc_extract_196; // op=pyc.extract -wire pyc_extract_197; // op=pyc.extract wire pyc_extract_2; // op=pyc.extract -wire pyc_extract_205; // op=pyc.extract +wire pyc_extract_204; // op=pyc.extract +wire pyc_extract_212; // op=pyc.extract wire pyc_extract_213; // op=pyc.extract wire pyc_extract_214; // op=pyc.extract -wire pyc_extract_215; // op=pyc.extract -wire pyc_extract_223; // op=pyc.extract +wire pyc_extract_222; // op=pyc.extract +wire pyc_extract_230; // op=pyc.extract wire pyc_extract_231; // op=pyc.extract wire pyc_extract_232; // op=pyc.extract -wire pyc_extract_233; // op=pyc.extract -wire pyc_extract_241; // op=pyc.extract +wire pyc_extract_24; // op=pyc.extract +wire pyc_extract_240; // op=pyc.extract +wire pyc_extract_248; // op=pyc.extract wire pyc_extract_249; // op=pyc.extract -wire pyc_extract_25; // op=pyc.extract wire pyc_extract_250; // op=pyc.extract -wire pyc_extract_251; // op=pyc.extract -wire pyc_extract_259; // op=pyc.extract +wire pyc_extract_258; // op=pyc.extract +wire pyc_extract_266; // op=pyc.extract wire pyc_extract_267; // op=pyc.extract wire pyc_extract_268; // op=pyc.extract -wire pyc_extract_269; // op=pyc.extract -wire pyc_extract_277; // op=pyc.extract +wire pyc_extract_276; // op=pyc.extract +wire pyc_extract_284; // op=pyc.extract wire pyc_extract_285; // op=pyc.extract wire pyc_extract_286; // op=pyc.extract -wire pyc_extract_287; // op=pyc.extract -wire pyc_extract_295; // op=pyc.extract +wire pyc_extract_294; // op=pyc.extract wire pyc_extract_3; // op=pyc.extract +wire pyc_extract_302; // op=pyc.extract wire pyc_extract_303; // op=pyc.extract wire pyc_extract_304; // op=pyc.extract -wire pyc_extract_305; // op=pyc.extract -wire pyc_extract_313; // op=pyc.extract +wire pyc_extract_312; // op=pyc.extract +wire pyc_extract_32; // op=pyc.extract +wire pyc_extract_320; // op=pyc.extract wire pyc_extract_321; // op=pyc.extract wire pyc_extract_322; // op=pyc.extract -wire pyc_extract_323; // op=pyc.extract -wire pyc_extract_326; // op=pyc.extract +wire pyc_extract_325; // op=pyc.extract +wire pyc_extract_328; // op=pyc.extract wire pyc_extract_329; // op=pyc.extract wire pyc_extract_33; // op=pyc.extract wire pyc_extract_330; // op=pyc.extract -wire pyc_extract_331; // op=pyc.extract -wire pyc_extract_339; // op=pyc.extract +wire pyc_extract_338; // op=pyc.extract wire pyc_extract_34; // op=pyc.extract +wire pyc_extract_341; // op=pyc.extract wire pyc_extract_342; // op=pyc.extract wire pyc_extract_343; // op=pyc.extract -wire pyc_extract_344; // op=pyc.extract -wire pyc_extract_35; // op=pyc.extract -wire pyc_extract_352; // op=pyc.extract +wire pyc_extract_351; // op=pyc.extract +wire pyc_extract_359; // op=pyc.extract wire pyc_extract_360; // op=pyc.extract wire pyc_extract_361; // op=pyc.extract -wire pyc_extract_362; // op=pyc.extract -wire pyc_extract_370; // op=pyc.extract +wire pyc_extract_369; // op=pyc.extract +wire pyc_extract_377; // op=pyc.extract wire pyc_extract_378; // op=pyc.extract wire pyc_extract_379; // op=pyc.extract -wire pyc_extract_380; // op=pyc.extract -wire pyc_extract_388; // op=pyc.extract +wire pyc_extract_387; // op=pyc.extract +wire pyc_extract_395; // op=pyc.extract wire pyc_extract_396; // op=pyc.extract wire pyc_extract_397; // op=pyc.extract -wire pyc_extract_398; // op=pyc.extract -wire pyc_extract_4; // op=pyc.extract -wire pyc_extract_406; // op=pyc.extract +wire pyc_extract_405; // op=pyc.extract +wire pyc_extract_413; // op=pyc.extract wire pyc_extract_414; // op=pyc.extract wire pyc_extract_415; // op=pyc.extract -wire pyc_extract_416; // op=pyc.extract -wire pyc_extract_424; // op=pyc.extract -wire pyc_extract_43; // op=pyc.extract +wire pyc_extract_42; // op=pyc.extract +wire pyc_extract_423; // op=pyc.extract +wire pyc_extract_431; // op=pyc.extract wire pyc_extract_432; // op=pyc.extract wire pyc_extract_433; // op=pyc.extract -wire pyc_extract_434; // op=pyc.extract -wire pyc_extract_442; // op=pyc.extract +wire pyc_extract_441; // op=pyc.extract +wire pyc_extract_449; // op=pyc.extract wire pyc_extract_450; // op=pyc.extract wire pyc_extract_451; // op=pyc.extract -wire pyc_extract_452; // op=pyc.extract -wire pyc_extract_460; // op=pyc.extract +wire pyc_extract_459; // op=pyc.extract +wire pyc_extract_467; // op=pyc.extract wire pyc_extract_468; // op=pyc.extract wire pyc_extract_469; // op=pyc.extract -wire pyc_extract_470; // op=pyc.extract -wire pyc_extract_478; // op=pyc.extract +wire pyc_extract_477; // op=pyc.extract +wire pyc_extract_485; // op=pyc.extract wire pyc_extract_486; // op=pyc.extract wire pyc_extract_487; // op=pyc.extract -wire pyc_extract_488; // op=pyc.extract -wire pyc_extract_496; // op=pyc.extract +wire pyc_extract_495; // op=pyc.extract +wire pyc_extract_50; // op=pyc.extract +wire pyc_extract_503; // op=pyc.extract wire pyc_extract_504; // op=pyc.extract wire pyc_extract_505; // op=pyc.extract -wire pyc_extract_506; // op=pyc.extract wire pyc_extract_51; // op=pyc.extract -wire pyc_extract_514; // op=pyc.extract +wire pyc_extract_513; // op=pyc.extract wire pyc_extract_52; // op=pyc.extract +wire pyc_extract_521; // op=pyc.extract wire pyc_extract_522; // op=pyc.extract wire pyc_extract_523; // op=pyc.extract -wire pyc_extract_524; // op=pyc.extract -wire pyc_extract_53; // op=pyc.extract -wire pyc_extract_532; // op=pyc.extract +wire pyc_extract_531; // op=pyc.extract +wire pyc_extract_539; // op=pyc.extract wire pyc_extract_540; // op=pyc.extract wire pyc_extract_541; // op=pyc.extract -wire pyc_extract_542; // op=pyc.extract -wire pyc_extract_550; // op=pyc.extract +wire pyc_extract_549; // op=pyc.extract +wire pyc_extract_557; // op=pyc.extract wire pyc_extract_558; // op=pyc.extract wire pyc_extract_559; // op=pyc.extract -wire pyc_extract_560; // op=pyc.extract -wire pyc_extract_568; // op=pyc.extract +wire pyc_extract_567; // op=pyc.extract +wire pyc_extract_575; // op=pyc.extract wire pyc_extract_576; // op=pyc.extract wire pyc_extract_577; // op=pyc.extract -wire pyc_extract_578; // op=pyc.extract -wire pyc_extract_586; // op=pyc.extract +wire pyc_extract_585; // op=pyc.extract +wire pyc_extract_593; // op=pyc.extract wire pyc_extract_594; // op=pyc.extract wire pyc_extract_595; // op=pyc.extract -wire pyc_extract_596; // op=pyc.extract -wire pyc_extract_604; // op=pyc.extract -wire pyc_extract_61; // op=pyc.extract +wire pyc_extract_60; // op=pyc.extract +wire pyc_extract_603; // op=pyc.extract +wire pyc_extract_611; // op=pyc.extract wire pyc_extract_612; // op=pyc.extract wire pyc_extract_613; // op=pyc.extract -wire pyc_extract_614; // op=pyc.extract -wire pyc_extract_622; // op=pyc.extract +wire pyc_extract_621; // op=pyc.extract +wire pyc_extract_629; // op=pyc.extract wire pyc_extract_630; // op=pyc.extract wire pyc_extract_631; // op=pyc.extract -wire pyc_extract_632; // op=pyc.extract -wire pyc_extract_640; // op=pyc.extract +wire pyc_extract_639; // op=pyc.extract +wire pyc_extract_647; // op=pyc.extract wire pyc_extract_648; // op=pyc.extract wire pyc_extract_649; // op=pyc.extract -wire pyc_extract_650; // op=pyc.extract -wire pyc_extract_653; // op=pyc.extract +wire pyc_extract_652; // op=pyc.extract +wire pyc_extract_68; // op=pyc.extract wire pyc_extract_69; // op=pyc.extract wire pyc_extract_70; // op=pyc.extract -wire pyc_extract_71; // op=pyc.extract -wire pyc_extract_79; // op=pyc.extract +wire pyc_extract_78; // op=pyc.extract +wire pyc_extract_86; // op=pyc.extract wire pyc_extract_87; // op=pyc.extract wire pyc_extract_88; // op=pyc.extract -wire pyc_extract_89; // op=pyc.extract -wire pyc_extract_97; // op=pyc.extract -wire pyc_or_102; // op=pyc.or -wire pyc_or_104; // op=pyc.or -wire pyc_or_11; // op=pyc.or -wire pyc_or_112; // op=pyc.or -wire pyc_or_114; // op=pyc.or -wire pyc_or_120; // op=pyc.or -wire pyc_or_122; // op=pyc.or -wire pyc_or_130; // op=pyc.or -wire pyc_or_132; // op=pyc.or -wire pyc_or_138; // op=pyc.or -wire pyc_or_140; // op=pyc.or -wire pyc_or_148; // op=pyc.or -wire pyc_or_150; // op=pyc.or -wire pyc_or_156; // op=pyc.or -wire pyc_or_158; // op=pyc.or -wire pyc_or_166; // op=pyc.or -wire pyc_or_168; // op=pyc.or -wire pyc_or_174; // op=pyc.or -wire pyc_or_176; // op=pyc.or -wire pyc_or_184; // op=pyc.or -wire pyc_or_186; // op=pyc.or -wire pyc_or_192; // op=pyc.or -wire pyc_or_194; // op=pyc.or -wire pyc_or_202; // op=pyc.or -wire pyc_or_204; // op=pyc.or -wire pyc_or_210; // op=pyc.or -wire pyc_or_212; // op=pyc.or -wire pyc_or_22; // op=pyc.or -wire pyc_or_220; // op=pyc.or -wire pyc_or_222; // op=pyc.or -wire pyc_or_228; // op=pyc.or -wire pyc_or_230; // op=pyc.or -wire pyc_or_238; // op=pyc.or -wire pyc_or_24; // op=pyc.or -wire pyc_or_240; // op=pyc.or -wire pyc_or_246; // op=pyc.or -wire pyc_or_248; // op=pyc.or -wire pyc_or_256; // op=pyc.or -wire pyc_or_258; // op=pyc.or -wire pyc_or_264; // op=pyc.or -wire pyc_or_266; // op=pyc.or -wire pyc_or_274; // op=pyc.or -wire pyc_or_276; // op=pyc.or -wire pyc_or_282; // op=pyc.or -wire pyc_or_284; // op=pyc.or -wire pyc_or_292; // op=pyc.or -wire pyc_or_294; // op=pyc.or -wire pyc_or_30; // op=pyc.or -wire pyc_or_300; // op=pyc.or -wire pyc_or_302; // op=pyc.or -wire pyc_or_310; // op=pyc.or -wire pyc_or_312; // op=pyc.or -wire pyc_or_318; // op=pyc.or -wire pyc_or_32; // op=pyc.or -wire pyc_or_320; // op=pyc.or -wire pyc_or_336; // op=pyc.or -wire pyc_or_338; // op=pyc.or -wire pyc_or_349; // op=pyc.or -wire pyc_or_351; // op=pyc.or -wire pyc_or_357; // op=pyc.or -wire pyc_or_359; // op=pyc.or -wire pyc_or_367; // op=pyc.or -wire pyc_or_369; // op=pyc.or -wire pyc_or_375; // op=pyc.or -wire pyc_or_377; // op=pyc.or -wire pyc_or_385; // op=pyc.or -wire pyc_or_387; // op=pyc.or -wire pyc_or_393; // op=pyc.or -wire pyc_or_395; // op=pyc.or -wire pyc_or_40; // op=pyc.or -wire pyc_or_403; // op=pyc.or -wire pyc_or_405; // op=pyc.or -wire pyc_or_411; // op=pyc.or -wire pyc_or_413; // op=pyc.or -wire pyc_or_42; // op=pyc.or -wire pyc_or_421; // op=pyc.or -wire pyc_or_423; // op=pyc.or -wire pyc_or_429; // op=pyc.or -wire pyc_or_431; // op=pyc.or -wire pyc_or_439; // op=pyc.or -wire pyc_or_441; // op=pyc.or -wire pyc_or_447; // op=pyc.or -wire pyc_or_449; // op=pyc.or -wire pyc_or_457; // op=pyc.or -wire pyc_or_459; // op=pyc.or -wire pyc_or_465; // op=pyc.or -wire pyc_or_467; // op=pyc.or -wire pyc_or_475; // op=pyc.or -wire pyc_or_477; // op=pyc.or -wire pyc_or_48; // op=pyc.or -wire pyc_or_483; // op=pyc.or -wire pyc_or_485; // op=pyc.or -wire pyc_or_493; // op=pyc.or -wire pyc_or_495; // op=pyc.or -wire pyc_or_50; // op=pyc.or -wire pyc_or_501; // op=pyc.or -wire pyc_or_503; // op=pyc.or -wire pyc_or_511; // op=pyc.or -wire pyc_or_513; // op=pyc.or -wire pyc_or_519; // op=pyc.or -wire pyc_or_521; // op=pyc.or -wire pyc_or_529; // op=pyc.or -wire pyc_or_531; // op=pyc.or -wire pyc_or_537; // op=pyc.or -wire pyc_or_539; // op=pyc.or -wire pyc_or_547; // op=pyc.or -wire pyc_or_549; // op=pyc.or -wire pyc_or_555; // op=pyc.or -wire pyc_or_557; // op=pyc.or -wire pyc_or_565; // op=pyc.or -wire pyc_or_567; // op=pyc.or -wire pyc_or_573; // op=pyc.or -wire pyc_or_575; // op=pyc.or -wire pyc_or_58; // op=pyc.or -wire pyc_or_583; // op=pyc.or -wire pyc_or_585; // op=pyc.or -wire pyc_or_591; // op=pyc.or -wire pyc_or_593; // op=pyc.or -wire pyc_or_60; // op=pyc.or -wire pyc_or_601; // op=pyc.or -wire pyc_or_603; // op=pyc.or -wire pyc_or_609; // op=pyc.or -wire pyc_or_611; // op=pyc.or -wire pyc_or_619; // op=pyc.or -wire pyc_or_621; // op=pyc.or -wire pyc_or_627; // op=pyc.or -wire pyc_or_629; // op=pyc.or -wire pyc_or_637; // op=pyc.or -wire pyc_or_639; // op=pyc.or -wire pyc_or_645; // op=pyc.or -wire pyc_or_647; // op=pyc.or -wire pyc_or_66; // op=pyc.or -wire pyc_or_662; // op=pyc.or -wire pyc_or_664; // op=pyc.or -wire pyc_or_669; // op=pyc.or -wire pyc_or_671; // op=pyc.or -wire pyc_or_676; // op=pyc.or -wire pyc_or_678; // op=pyc.or -wire pyc_or_68; // op=pyc.or -wire pyc_or_683; // op=pyc.or -wire pyc_or_685; // op=pyc.or -wire pyc_or_690; // op=pyc.or -wire pyc_or_692; // op=pyc.or -wire pyc_or_697; // op=pyc.or -wire pyc_or_699; // op=pyc.or -wire pyc_or_704; // op=pyc.or -wire pyc_or_706; // op=pyc.or -wire pyc_or_711; // op=pyc.or -wire pyc_or_713; // op=pyc.or -wire pyc_or_718; // op=pyc.or -wire pyc_or_720; // op=pyc.or -wire pyc_or_725; // op=pyc.or -wire pyc_or_727; // op=pyc.or -wire pyc_or_732; // op=pyc.or -wire pyc_or_734; // op=pyc.or -wire pyc_or_739; // op=pyc.or -wire pyc_or_741; // op=pyc.or -wire pyc_or_746; // op=pyc.or -wire pyc_or_748; // op=pyc.or -wire pyc_or_753; // op=pyc.or -wire pyc_or_755; // op=pyc.or -wire pyc_or_76; // op=pyc.or -wire pyc_or_760; // op=pyc.or -wire pyc_or_762; // op=pyc.or -wire pyc_or_767; // op=pyc.or -wire pyc_or_769; // op=pyc.or -wire pyc_or_774; // op=pyc.or -wire pyc_or_776; // op=pyc.or -wire pyc_or_78; // op=pyc.or -wire pyc_or_781; // op=pyc.or -wire pyc_or_783; // op=pyc.or -wire pyc_or_788; // op=pyc.or -wire pyc_or_790; // op=pyc.or -wire pyc_or_795; // op=pyc.or -wire pyc_or_797; // op=pyc.or -wire pyc_or_802; // op=pyc.or -wire pyc_or_804; // op=pyc.or -wire pyc_or_809; // op=pyc.or -wire pyc_or_811; // op=pyc.or -wire pyc_or_816; // op=pyc.or -wire pyc_or_818; // op=pyc.or -wire pyc_or_823; // op=pyc.or -wire pyc_or_825; // op=pyc.or -wire pyc_or_830; // op=pyc.or -wire pyc_or_832; // op=pyc.or -wire pyc_or_837; // op=pyc.or -wire pyc_or_839; // op=pyc.or -wire pyc_or_84; // op=pyc.or -wire pyc_or_844; // op=pyc.or -wire pyc_or_846; // op=pyc.or -wire pyc_or_851; // op=pyc.or -wire pyc_or_853; // op=pyc.or -wire pyc_or_858; // op=pyc.or -wire pyc_or_86; // op=pyc.or -wire pyc_or_860; // op=pyc.or -wire pyc_or_865; // op=pyc.or -wire pyc_or_867; // op=pyc.or -wire pyc_or_872; // op=pyc.or -wire pyc_or_874; // op=pyc.or -wire pyc_or_879; // op=pyc.or -wire pyc_or_881; // op=pyc.or -wire pyc_or_886; // op=pyc.or -wire pyc_or_888; // op=pyc.or -wire pyc_or_893; // op=pyc.or -wire pyc_or_895; // op=pyc.or -wire pyc_or_9; // op=pyc.or -wire pyc_or_94; // op=pyc.or -wire pyc_or_96; // op=pyc.or +wire pyc_extract_96; // op=pyc.extract +wire pyc_or_10; // op=pyc.or +wire pyc_or_101; // op=pyc.or +wire pyc_or_103; // op=pyc.or +wire pyc_or_111; // op=pyc.or +wire pyc_or_113; // op=pyc.or +wire pyc_or_119; // op=pyc.or +wire pyc_or_121; // op=pyc.or +wire pyc_or_129; // op=pyc.or +wire pyc_or_131; // op=pyc.or +wire pyc_or_137; // op=pyc.or +wire pyc_or_139; // op=pyc.or +wire pyc_or_147; // op=pyc.or +wire pyc_or_149; // op=pyc.or +wire pyc_or_155; // op=pyc.or +wire pyc_or_157; // op=pyc.or +wire pyc_or_165; // op=pyc.or +wire pyc_or_167; // op=pyc.or +wire pyc_or_173; // op=pyc.or +wire pyc_or_175; // op=pyc.or +wire pyc_or_183; // op=pyc.or +wire pyc_or_185; // op=pyc.or +wire pyc_or_191; // op=pyc.or +wire pyc_or_193; // op=pyc.or +wire pyc_or_201; // op=pyc.or +wire pyc_or_203; // op=pyc.or +wire pyc_or_209; // op=pyc.or +wire pyc_or_21; // op=pyc.or +wire pyc_or_211; // op=pyc.or +wire pyc_or_219; // op=pyc.or +wire pyc_or_221; // op=pyc.or +wire pyc_or_227; // op=pyc.or +wire pyc_or_229; // op=pyc.or +wire pyc_or_23; // op=pyc.or +wire pyc_or_237; // op=pyc.or +wire pyc_or_239; // op=pyc.or +wire pyc_or_245; // op=pyc.or +wire pyc_or_247; // op=pyc.or +wire pyc_or_255; // op=pyc.or +wire pyc_or_257; // op=pyc.or +wire pyc_or_263; // op=pyc.or +wire pyc_or_265; // op=pyc.or +wire pyc_or_273; // op=pyc.or +wire pyc_or_275; // op=pyc.or +wire pyc_or_281; // op=pyc.or +wire pyc_or_283; // op=pyc.or +wire pyc_or_29; // op=pyc.or +wire pyc_or_291; // op=pyc.or +wire pyc_or_293; // op=pyc.or +wire pyc_or_299; // op=pyc.or +wire pyc_or_301; // op=pyc.or +wire pyc_or_309; // op=pyc.or +wire pyc_or_31; // op=pyc.or +wire pyc_or_311; // op=pyc.or +wire pyc_or_317; // op=pyc.or +wire pyc_or_319; // op=pyc.or +wire pyc_or_335; // op=pyc.or +wire pyc_or_337; // op=pyc.or +wire pyc_or_348; // op=pyc.or +wire pyc_or_350; // op=pyc.or +wire pyc_or_356; // op=pyc.or +wire pyc_or_358; // op=pyc.or +wire pyc_or_366; // op=pyc.or +wire pyc_or_368; // op=pyc.or +wire pyc_or_374; // op=pyc.or +wire pyc_or_376; // op=pyc.or +wire pyc_or_384; // op=pyc.or +wire pyc_or_386; // op=pyc.or +wire pyc_or_39; // op=pyc.or +wire pyc_or_392; // op=pyc.or +wire pyc_or_394; // op=pyc.or +wire pyc_or_402; // op=pyc.or +wire pyc_or_404; // op=pyc.or +wire pyc_or_41; // op=pyc.or +wire pyc_or_410; // op=pyc.or +wire pyc_or_412; // op=pyc.or +wire pyc_or_420; // op=pyc.or +wire pyc_or_422; // op=pyc.or +wire pyc_or_428; // op=pyc.or +wire pyc_or_430; // op=pyc.or +wire pyc_or_438; // op=pyc.or +wire pyc_or_440; // op=pyc.or +wire pyc_or_446; // op=pyc.or +wire pyc_or_448; // op=pyc.or +wire pyc_or_456; // op=pyc.or +wire pyc_or_458; // op=pyc.or +wire pyc_or_464; // op=pyc.or +wire pyc_or_466; // op=pyc.or +wire pyc_or_47; // op=pyc.or +wire pyc_or_474; // op=pyc.or +wire pyc_or_476; // op=pyc.or +wire pyc_or_482; // op=pyc.or +wire pyc_or_484; // op=pyc.or +wire pyc_or_49; // op=pyc.or +wire pyc_or_492; // op=pyc.or +wire pyc_or_494; // op=pyc.or +wire pyc_or_500; // op=pyc.or +wire pyc_or_502; // op=pyc.or +wire pyc_or_510; // op=pyc.or +wire pyc_or_512; // op=pyc.or +wire pyc_or_518; // op=pyc.or +wire pyc_or_520; // op=pyc.or +wire pyc_or_528; // op=pyc.or +wire pyc_or_530; // op=pyc.or +wire pyc_or_536; // op=pyc.or +wire pyc_or_538; // op=pyc.or +wire pyc_or_546; // op=pyc.or +wire pyc_or_548; // op=pyc.or +wire pyc_or_554; // op=pyc.or +wire pyc_or_556; // op=pyc.or +wire pyc_or_564; // op=pyc.or +wire pyc_or_566; // op=pyc.or +wire pyc_or_57; // op=pyc.or +wire pyc_or_572; // op=pyc.or +wire pyc_or_574; // op=pyc.or +wire pyc_or_582; // op=pyc.or +wire pyc_or_584; // op=pyc.or +wire pyc_or_59; // op=pyc.or +wire pyc_or_590; // op=pyc.or +wire pyc_or_592; // op=pyc.or +wire pyc_or_600; // op=pyc.or +wire pyc_or_602; // op=pyc.or +wire pyc_or_608; // op=pyc.or +wire pyc_or_610; // op=pyc.or +wire pyc_or_618; // op=pyc.or +wire pyc_or_620; // op=pyc.or +wire pyc_or_626; // op=pyc.or +wire pyc_or_628; // op=pyc.or +wire pyc_or_636; // op=pyc.or +wire pyc_or_638; // op=pyc.or +wire pyc_or_644; // op=pyc.or +wire pyc_or_646; // op=pyc.or +wire pyc_or_65; // op=pyc.or +wire pyc_or_661; // op=pyc.or +wire pyc_or_663; // op=pyc.or +wire pyc_or_668; // op=pyc.or +wire pyc_or_67; // op=pyc.or +wire pyc_or_670; // op=pyc.or +wire pyc_or_675; // op=pyc.or +wire pyc_or_677; // op=pyc.or +wire pyc_or_682; // op=pyc.or +wire pyc_or_684; // op=pyc.or +wire pyc_or_689; // op=pyc.or +wire pyc_or_691; // op=pyc.or +wire pyc_or_696; // op=pyc.or +wire pyc_or_698; // op=pyc.or +wire pyc_or_703; // op=pyc.or +wire pyc_or_705; // op=pyc.or +wire pyc_or_710; // op=pyc.or +wire pyc_or_712; // op=pyc.or +wire pyc_or_717; // op=pyc.or +wire pyc_or_719; // op=pyc.or +wire pyc_or_724; // op=pyc.or +wire pyc_or_726; // op=pyc.or +wire pyc_or_731; // op=pyc.or +wire pyc_or_733; // op=pyc.or +wire pyc_or_738; // op=pyc.or +wire pyc_or_740; // op=pyc.or +wire pyc_or_745; // op=pyc.or +wire pyc_or_747; // op=pyc.or +wire pyc_or_75; // op=pyc.or +wire pyc_or_752; // op=pyc.or +wire pyc_or_754; // op=pyc.or +wire pyc_or_759; // op=pyc.or +wire pyc_or_761; // op=pyc.or +wire pyc_or_766; // op=pyc.or +wire pyc_or_768; // op=pyc.or +wire pyc_or_77; // op=pyc.or +wire pyc_or_773; // op=pyc.or +wire pyc_or_775; // op=pyc.or +wire pyc_or_780; // op=pyc.or +wire pyc_or_782; // op=pyc.or +wire pyc_or_787; // op=pyc.or +wire pyc_or_789; // op=pyc.or +wire pyc_or_794; // op=pyc.or +wire pyc_or_796; // op=pyc.or +wire pyc_or_8; // op=pyc.or +wire pyc_or_801; // op=pyc.or +wire pyc_or_803; // op=pyc.or +wire pyc_or_808; // op=pyc.or +wire pyc_or_810; // op=pyc.or +wire pyc_or_815; // op=pyc.or +wire pyc_or_817; // op=pyc.or +wire pyc_or_822; // op=pyc.or +wire pyc_or_824; // op=pyc.or +wire pyc_or_829; // op=pyc.or +wire pyc_or_83; // op=pyc.or +wire pyc_or_831; // op=pyc.or +wire pyc_or_836; // op=pyc.or +wire pyc_or_838; // op=pyc.or +wire pyc_or_843; // op=pyc.or +wire pyc_or_845; // op=pyc.or +wire pyc_or_85; // op=pyc.or +wire pyc_or_850; // op=pyc.or +wire pyc_or_852; // op=pyc.or +wire pyc_or_857; // op=pyc.or +wire pyc_or_859; // op=pyc.or +wire pyc_or_864; // op=pyc.or +wire pyc_or_866; // op=pyc.or +wire pyc_or_871; // op=pyc.or +wire pyc_or_873; // op=pyc.or +wire pyc_or_878; // op=pyc.or +wire pyc_or_880; // op=pyc.or +wire pyc_or_885; // op=pyc.or +wire pyc_or_887; // op=pyc.or +wire pyc_or_892; // op=pyc.or +wire pyc_or_894; // op=pyc.or +wire pyc_or_93; // op=pyc.or +wire pyc_or_933; // op=pyc.or +wire pyc_or_935; // op=pyc.or +wire pyc_or_938; // op=pyc.or +wire pyc_or_941; // op=pyc.or +wire pyc_or_944; // op=pyc.or +wire pyc_or_947; // op=pyc.or +wire pyc_or_95; // op=pyc.or +wire pyc_or_950; // op=pyc.or +wire pyc_or_953; // op=pyc.or +wire pyc_or_956; // op=pyc.or +wire pyc_or_959; // op=pyc.or +wire pyc_or_962; // op=pyc.or +wire pyc_or_965; // op=pyc.or +wire pyc_or_967; // op=pyc.or +wire pyc_or_970; // op=pyc.or +wire pyc_or_972; // op=pyc.or +wire pyc_or_974; // op=pyc.or +wire pyc_or_976; // op=pyc.or +wire pyc_or_978; // op=pyc.or +wire pyc_or_980; // op=pyc.or +wire pyc_or_982; // op=pyc.or +wire pyc_or_984; // op=pyc.or +wire pyc_or_986; // op=pyc.or +wire pyc_or_988; // op=pyc.or +wire pyc_or_990; // op=pyc.or +wire pyc_or_992; // op=pyc.or +wire pyc_or_994; // op=pyc.or +wire pyc_xor_1000; // op=pyc.xor +wire pyc_xor_1001; // op=pyc.xor +wire pyc_xor_1002; // op=pyc.xor +wire pyc_xor_1003; // op=pyc.xor +wire pyc_xor_1004; // op=pyc.xor +wire pyc_xor_1005; // op=pyc.xor +wire pyc_xor_1006; // op=pyc.xor +wire pyc_xor_1007; // op=pyc.xor +wire pyc_xor_1008; // op=pyc.xor +wire pyc_xor_1009; // op=pyc.xor +wire pyc_xor_1010; // op=pyc.xor +wire pyc_xor_107; // op=pyc.xor wire pyc_xor_108; // op=pyc.xor -wire pyc_xor_109; // op=pyc.xor +wire pyc_xor_115; // op=pyc.xor wire pyc_xor_116; // op=pyc.xor -wire pyc_xor_117; // op=pyc.xor +wire pyc_xor_12; // op=pyc.xor +wire pyc_xor_125; // op=pyc.xor wire pyc_xor_126; // op=pyc.xor -wire pyc_xor_127; // op=pyc.xor -wire pyc_xor_13; // op=pyc.xor +wire pyc_xor_133; // op=pyc.xor wire pyc_xor_134; // op=pyc.xor -wire pyc_xor_135; // op=pyc.xor +wire pyc_xor_143; // op=pyc.xor wire pyc_xor_144; // op=pyc.xor -wire pyc_xor_145; // op=pyc.xor +wire pyc_xor_151; // op=pyc.xor wire pyc_xor_152; // op=pyc.xor -wire pyc_xor_153; // op=pyc.xor +wire pyc_xor_161; // op=pyc.xor wire pyc_xor_162; // op=pyc.xor -wire pyc_xor_163; // op=pyc.xor +wire pyc_xor_169; // op=pyc.xor +wire pyc_xor_17; // op=pyc.xor wire pyc_xor_170; // op=pyc.xor -wire pyc_xor_171; // op=pyc.xor +wire pyc_xor_179; // op=pyc.xor wire pyc_xor_18; // op=pyc.xor wire pyc_xor_180; // op=pyc.xor -wire pyc_xor_181; // op=pyc.xor +wire pyc_xor_187; // op=pyc.xor wire pyc_xor_188; // op=pyc.xor -wire pyc_xor_189; // op=pyc.xor -wire pyc_xor_19; // op=pyc.xor +wire pyc_xor_197; // op=pyc.xor wire pyc_xor_198; // op=pyc.xor -wire pyc_xor_199; // op=pyc.xor +wire pyc_xor_205; // op=pyc.xor wire pyc_xor_206; // op=pyc.xor -wire pyc_xor_207; // op=pyc.xor +wire pyc_xor_215; // op=pyc.xor wire pyc_xor_216; // op=pyc.xor -wire pyc_xor_217; // op=pyc.xor +wire pyc_xor_223; // op=pyc.xor wire pyc_xor_224; // op=pyc.xor -wire pyc_xor_225; // op=pyc.xor +wire pyc_xor_233; // op=pyc.xor wire pyc_xor_234; // op=pyc.xor -wire pyc_xor_235; // op=pyc.xor +wire pyc_xor_241; // op=pyc.xor wire pyc_xor_242; // op=pyc.xor -wire pyc_xor_243; // op=pyc.xor +wire pyc_xor_25; // op=pyc.xor +wire pyc_xor_251; // op=pyc.xor wire pyc_xor_252; // op=pyc.xor -wire pyc_xor_253; // op=pyc.xor +wire pyc_xor_259; // op=pyc.xor wire pyc_xor_26; // op=pyc.xor wire pyc_xor_260; // op=pyc.xor -wire pyc_xor_261; // op=pyc.xor -wire pyc_xor_27; // op=pyc.xor +wire pyc_xor_269; // op=pyc.xor wire pyc_xor_270; // op=pyc.xor -wire pyc_xor_271; // op=pyc.xor +wire pyc_xor_277; // op=pyc.xor wire pyc_xor_278; // op=pyc.xor -wire pyc_xor_279; // op=pyc.xor +wire pyc_xor_287; // op=pyc.xor wire pyc_xor_288; // op=pyc.xor -wire pyc_xor_289; // op=pyc.xor +wire pyc_xor_295; // op=pyc.xor wire pyc_xor_296; // op=pyc.xor -wire pyc_xor_297; // op=pyc.xor +wire pyc_xor_305; // op=pyc.xor wire pyc_xor_306; // op=pyc.xor -wire pyc_xor_307; // op=pyc.xor +wire pyc_xor_313; // op=pyc.xor wire pyc_xor_314; // op=pyc.xor -wire pyc_xor_315; // op=pyc.xor +wire pyc_xor_323; // op=pyc.xor wire pyc_xor_324; // op=pyc.xor -wire pyc_xor_325; // op=pyc.xor +wire pyc_xor_326; // op=pyc.xor wire pyc_xor_327; // op=pyc.xor -wire pyc_xor_328; // op=pyc.xor +wire pyc_xor_331; // op=pyc.xor wire pyc_xor_332; // op=pyc.xor -wire pyc_xor_333; // op=pyc.xor -wire pyc_xor_340; // op=pyc.xor +wire pyc_xor_339; // op=pyc.xor +wire pyc_xor_344; // op=pyc.xor wire pyc_xor_345; // op=pyc.xor -wire pyc_xor_346; // op=pyc.xor +wire pyc_xor_35; // op=pyc.xor +wire pyc_xor_352; // op=pyc.xor wire pyc_xor_353; // op=pyc.xor -wire pyc_xor_354; // op=pyc.xor wire pyc_xor_36; // op=pyc.xor +wire pyc_xor_362; // op=pyc.xor wire pyc_xor_363; // op=pyc.xor -wire pyc_xor_364; // op=pyc.xor -wire pyc_xor_37; // op=pyc.xor +wire pyc_xor_370; // op=pyc.xor wire pyc_xor_371; // op=pyc.xor -wire pyc_xor_372; // op=pyc.xor +wire pyc_xor_380; // op=pyc.xor wire pyc_xor_381; // op=pyc.xor -wire pyc_xor_382; // op=pyc.xor +wire pyc_xor_388; // op=pyc.xor wire pyc_xor_389; // op=pyc.xor -wire pyc_xor_390; // op=pyc.xor +wire pyc_xor_398; // op=pyc.xor wire pyc_xor_399; // op=pyc.xor -wire pyc_xor_400; // op=pyc.xor +wire pyc_xor_4; // op=pyc.xor +wire pyc_xor_406; // op=pyc.xor wire pyc_xor_407; // op=pyc.xor -wire pyc_xor_408; // op=pyc.xor +wire pyc_xor_416; // op=pyc.xor wire pyc_xor_417; // op=pyc.xor -wire pyc_xor_418; // op=pyc.xor +wire pyc_xor_424; // op=pyc.xor wire pyc_xor_425; // op=pyc.xor -wire pyc_xor_426; // op=pyc.xor +wire pyc_xor_43; // op=pyc.xor +wire pyc_xor_434; // op=pyc.xor wire pyc_xor_435; // op=pyc.xor -wire pyc_xor_436; // op=pyc.xor wire pyc_xor_44; // op=pyc.xor +wire pyc_xor_442; // op=pyc.xor wire pyc_xor_443; // op=pyc.xor -wire pyc_xor_444; // op=pyc.xor -wire pyc_xor_45; // op=pyc.xor +wire pyc_xor_452; // op=pyc.xor wire pyc_xor_453; // op=pyc.xor -wire pyc_xor_454; // op=pyc.xor +wire pyc_xor_460; // op=pyc.xor wire pyc_xor_461; // op=pyc.xor -wire pyc_xor_462; // op=pyc.xor +wire pyc_xor_470; // op=pyc.xor wire pyc_xor_471; // op=pyc.xor -wire pyc_xor_472; // op=pyc.xor +wire pyc_xor_478; // op=pyc.xor wire pyc_xor_479; // op=pyc.xor -wire pyc_xor_480; // op=pyc.xor +wire pyc_xor_488; // op=pyc.xor wire pyc_xor_489; // op=pyc.xor -wire pyc_xor_490; // op=pyc.xor +wire pyc_xor_496; // op=pyc.xor wire pyc_xor_497; // op=pyc.xor -wire pyc_xor_498; // op=pyc.xor wire pyc_xor_5; // op=pyc.xor +wire pyc_xor_506; // op=pyc.xor wire pyc_xor_507; // op=pyc.xor -wire pyc_xor_508; // op=pyc.xor +wire pyc_xor_514; // op=pyc.xor wire pyc_xor_515; // op=pyc.xor -wire pyc_xor_516; // op=pyc.xor +wire pyc_xor_524; // op=pyc.xor wire pyc_xor_525; // op=pyc.xor -wire pyc_xor_526; // op=pyc.xor +wire pyc_xor_53; // op=pyc.xor +wire pyc_xor_532; // op=pyc.xor wire pyc_xor_533; // op=pyc.xor -wire pyc_xor_534; // op=pyc.xor wire pyc_xor_54; // op=pyc.xor +wire pyc_xor_542; // op=pyc.xor wire pyc_xor_543; // op=pyc.xor -wire pyc_xor_544; // op=pyc.xor -wire pyc_xor_55; // op=pyc.xor +wire pyc_xor_550; // op=pyc.xor wire pyc_xor_551; // op=pyc.xor -wire pyc_xor_552; // op=pyc.xor +wire pyc_xor_560; // op=pyc.xor wire pyc_xor_561; // op=pyc.xor -wire pyc_xor_562; // op=pyc.xor +wire pyc_xor_568; // op=pyc.xor wire pyc_xor_569; // op=pyc.xor -wire pyc_xor_570; // op=pyc.xor +wire pyc_xor_578; // op=pyc.xor wire pyc_xor_579; // op=pyc.xor -wire pyc_xor_580; // op=pyc.xor +wire pyc_xor_586; // op=pyc.xor wire pyc_xor_587; // op=pyc.xor -wire pyc_xor_588; // op=pyc.xor +wire pyc_xor_596; // op=pyc.xor wire pyc_xor_597; // op=pyc.xor -wire pyc_xor_598; // op=pyc.xor -wire pyc_xor_6; // op=pyc.xor +wire pyc_xor_604; // op=pyc.xor wire pyc_xor_605; // op=pyc.xor -wire pyc_xor_606; // op=pyc.xor +wire pyc_xor_61; // op=pyc.xor +wire pyc_xor_614; // op=pyc.xor wire pyc_xor_615; // op=pyc.xor -wire pyc_xor_616; // op=pyc.xor wire pyc_xor_62; // op=pyc.xor +wire pyc_xor_622; // op=pyc.xor wire pyc_xor_623; // op=pyc.xor -wire pyc_xor_624; // op=pyc.xor -wire pyc_xor_63; // op=pyc.xor +wire pyc_xor_632; // op=pyc.xor wire pyc_xor_633; // op=pyc.xor -wire pyc_xor_634; // op=pyc.xor +wire pyc_xor_640; // op=pyc.xor wire pyc_xor_641; // op=pyc.xor -wire pyc_xor_642; // op=pyc.xor +wire pyc_xor_650; // op=pyc.xor wire pyc_xor_651; // op=pyc.xor -wire pyc_xor_652; // op=pyc.xor +wire pyc_xor_653; // op=pyc.xor wire pyc_xor_654; // op=pyc.xor wire pyc_xor_655; // op=pyc.xor -wire pyc_xor_656; // op=pyc.xor +wire pyc_xor_657; // op=pyc.xor wire pyc_xor_658; // op=pyc.xor -wire pyc_xor_659; // op=pyc.xor +wire pyc_xor_664; // op=pyc.xor wire pyc_xor_665; // op=pyc.xor -wire pyc_xor_666; // op=pyc.xor +wire pyc_xor_671; // op=pyc.xor wire pyc_xor_672; // op=pyc.xor -wire pyc_xor_673; // op=pyc.xor +wire pyc_xor_678; // op=pyc.xor wire pyc_xor_679; // op=pyc.xor -wire pyc_xor_680; // op=pyc.xor +wire pyc_xor_685; // op=pyc.xor wire pyc_xor_686; // op=pyc.xor -wire pyc_xor_687; // op=pyc.xor +wire pyc_xor_692; // op=pyc.xor wire pyc_xor_693; // op=pyc.xor -wire pyc_xor_694; // op=pyc.xor +wire pyc_xor_699; // op=pyc.xor wire pyc_xor_700; // op=pyc.xor -wire pyc_xor_701; // op=pyc.xor +wire pyc_xor_706; // op=pyc.xor wire pyc_xor_707; // op=pyc.xor -wire pyc_xor_708; // op=pyc.xor +wire pyc_xor_71; // op=pyc.xor +wire pyc_xor_713; // op=pyc.xor wire pyc_xor_714; // op=pyc.xor -wire pyc_xor_715; // op=pyc.xor wire pyc_xor_72; // op=pyc.xor +wire pyc_xor_720; // op=pyc.xor wire pyc_xor_721; // op=pyc.xor -wire pyc_xor_722; // op=pyc.xor +wire pyc_xor_727; // op=pyc.xor wire pyc_xor_728; // op=pyc.xor -wire pyc_xor_729; // op=pyc.xor -wire pyc_xor_73; // op=pyc.xor +wire pyc_xor_734; // op=pyc.xor wire pyc_xor_735; // op=pyc.xor -wire pyc_xor_736; // op=pyc.xor +wire pyc_xor_741; // op=pyc.xor wire pyc_xor_742; // op=pyc.xor -wire pyc_xor_743; // op=pyc.xor +wire pyc_xor_748; // op=pyc.xor wire pyc_xor_749; // op=pyc.xor -wire pyc_xor_750; // op=pyc.xor +wire pyc_xor_755; // op=pyc.xor wire pyc_xor_756; // op=pyc.xor -wire pyc_xor_757; // op=pyc.xor +wire pyc_xor_762; // op=pyc.xor wire pyc_xor_763; // op=pyc.xor -wire pyc_xor_764; // op=pyc.xor +wire pyc_xor_769; // op=pyc.xor wire pyc_xor_770; // op=pyc.xor -wire pyc_xor_771; // op=pyc.xor +wire pyc_xor_776; // op=pyc.xor wire pyc_xor_777; // op=pyc.xor -wire pyc_xor_778; // op=pyc.xor +wire pyc_xor_783; // op=pyc.xor wire pyc_xor_784; // op=pyc.xor -wire pyc_xor_785; // op=pyc.xor +wire pyc_xor_79; // op=pyc.xor +wire pyc_xor_790; // op=pyc.xor wire pyc_xor_791; // op=pyc.xor -wire pyc_xor_792; // op=pyc.xor +wire pyc_xor_797; // op=pyc.xor wire pyc_xor_798; // op=pyc.xor -wire pyc_xor_799; // op=pyc.xor wire pyc_xor_80; // op=pyc.xor +wire pyc_xor_804; // op=pyc.xor wire pyc_xor_805; // op=pyc.xor -wire pyc_xor_806; // op=pyc.xor -wire pyc_xor_81; // op=pyc.xor +wire pyc_xor_811; // op=pyc.xor wire pyc_xor_812; // op=pyc.xor -wire pyc_xor_813; // op=pyc.xor +wire pyc_xor_818; // op=pyc.xor wire pyc_xor_819; // op=pyc.xor -wire pyc_xor_820; // op=pyc.xor +wire pyc_xor_825; // op=pyc.xor wire pyc_xor_826; // op=pyc.xor -wire pyc_xor_827; // op=pyc.xor +wire pyc_xor_832; // op=pyc.xor wire pyc_xor_833; // op=pyc.xor -wire pyc_xor_834; // op=pyc.xor +wire pyc_xor_839; // op=pyc.xor wire pyc_xor_840; // op=pyc.xor -wire pyc_xor_841; // op=pyc.xor +wire pyc_xor_846; // op=pyc.xor wire pyc_xor_847; // op=pyc.xor -wire pyc_xor_848; // op=pyc.xor +wire pyc_xor_853; // op=pyc.xor wire pyc_xor_854; // op=pyc.xor -wire pyc_xor_855; // op=pyc.xor +wire pyc_xor_860; // op=pyc.xor wire pyc_xor_861; // op=pyc.xor -wire pyc_xor_862; // op=pyc.xor +wire pyc_xor_867; // op=pyc.xor wire pyc_xor_868; // op=pyc.xor -wire pyc_xor_869; // op=pyc.xor +wire pyc_xor_874; // op=pyc.xor wire pyc_xor_875; // op=pyc.xor -wire pyc_xor_876; // op=pyc.xor +wire pyc_xor_881; // op=pyc.xor wire pyc_xor_882; // op=pyc.xor -wire pyc_xor_883; // op=pyc.xor +wire pyc_xor_888; // op=pyc.xor wire pyc_xor_889; // op=pyc.xor -wire pyc_xor_890; // op=pyc.xor +wire pyc_xor_89; // op=pyc.xor +wire pyc_xor_895; // op=pyc.xor wire pyc_xor_896; // op=pyc.xor wire pyc_xor_897; // op=pyc.xor wire pyc_xor_898; // op=pyc.xor wire pyc_xor_899; // op=pyc.xor wire pyc_xor_90; // op=pyc.xor -wire pyc_xor_91; // op=pyc.xor +wire pyc_xor_900; // op=pyc.xor +wire pyc_xor_901; // op=pyc.xor +wire pyc_xor_902; // op=pyc.xor +wire pyc_xor_903; // op=pyc.xor +wire pyc_xor_904; // op=pyc.xor +wire pyc_xor_905; // op=pyc.xor +wire pyc_xor_906; // op=pyc.xor +wire pyc_xor_907; // op=pyc.xor +wire pyc_xor_908; // op=pyc.xor +wire pyc_xor_909; // op=pyc.xor +wire pyc_xor_910; // op=pyc.xor +wire pyc_xor_911; // op=pyc.xor +wire pyc_xor_912; // op=pyc.xor +wire pyc_xor_913; // op=pyc.xor +wire pyc_xor_914; // op=pyc.xor +wire pyc_xor_915; // op=pyc.xor +wire pyc_xor_97; // op=pyc.xor wire pyc_xor_98; // op=pyc.xor -wire pyc_xor_99; // op=pyc.xor +wire pyc_xor_995; // op=pyc.xor +wire pyc_xor_996; // op=pyc.xor +wire pyc_xor_997; // op=pyc.xor +wire pyc_xor_998; // op=pyc.xor +wire pyc_xor_999; // op=pyc.xor // --- Combinational (netlist) -assign pyc_constant_1 = 1'd0; -assign pyc_extract_2 = PE_INT_WALLACE_DOT8_TREE_W19_in0[0]; -assign pyc_extract_3 = PE_INT_WALLACE_DOT8_TREE_W19_in1[0]; -assign pyc_extract_4 = PE_INT_WALLACE_DOT8_TREE_W19_in2[0]; -assign pyc_xor_5 = (pyc_extract_2 ^ pyc_extract_3); -assign pyc_xor_6 = (pyc_xor_5 ^ pyc_extract_4); -assign pyc_and_7 = (pyc_extract_2 & pyc_extract_3); -assign pyc_and_8 = (pyc_extract_2 & pyc_extract_4); -assign pyc_or_9 = (pyc_and_7 | pyc_and_8); -assign pyc_and_10 = (pyc_extract_3 & pyc_extract_4); -assign pyc_or_11 = (pyc_or_9 | pyc_and_10); -assign pyc_extract_12 = PE_INT_WALLACE_DOT8_TREE_W19_in3[0]; -assign pyc_xor_13 = (pyc_xor_6 ^ pyc_extract_12); -assign pyc_and_14 = (pyc_xor_6 & pyc_extract_12); -assign pyc_extract_15 = PE_INT_WALLACE_DOT8_TREE_W19_in0[1]; -assign pyc_extract_16 = PE_INT_WALLACE_DOT8_TREE_W19_in1[1]; -assign pyc_extract_17 = PE_INT_WALLACE_DOT8_TREE_W19_in2[1]; -assign pyc_xor_18 = (pyc_extract_15 ^ pyc_extract_16); -assign pyc_xor_19 = (pyc_xor_18 ^ pyc_extract_17); -assign pyc_and_20 = (pyc_extract_15 & pyc_extract_16); -assign pyc_and_21 = (pyc_extract_15 & pyc_extract_17); -assign pyc_or_22 = (pyc_and_20 | pyc_and_21); -assign pyc_and_23 = (pyc_extract_16 & pyc_extract_17); -assign pyc_or_24 = (pyc_or_22 | pyc_and_23); -assign pyc_extract_25 = PE_INT_WALLACE_DOT8_TREE_W19_in3[1]; -assign pyc_xor_26 = (pyc_xor_19 ^ pyc_extract_25); -assign pyc_xor_27 = (pyc_xor_26 ^ pyc_or_11); -assign pyc_and_28 = (pyc_xor_19 & pyc_extract_25); -assign pyc_and_29 = (pyc_xor_19 & pyc_or_11); -assign pyc_or_30 = (pyc_and_28 | pyc_and_29); -assign pyc_and_31 = (pyc_extract_25 & pyc_or_11); -assign pyc_or_32 = (pyc_or_30 | pyc_and_31); -assign pyc_extract_33 = PE_INT_WALLACE_DOT8_TREE_W19_in0[2]; -assign pyc_extract_34 = PE_INT_WALLACE_DOT8_TREE_W19_in1[2]; -assign pyc_extract_35 = PE_INT_WALLACE_DOT8_TREE_W19_in2[2]; -assign pyc_xor_36 = (pyc_extract_33 ^ pyc_extract_34); -assign pyc_xor_37 = (pyc_xor_36 ^ pyc_extract_35); -assign pyc_and_38 = (pyc_extract_33 & pyc_extract_34); -assign pyc_and_39 = (pyc_extract_33 & pyc_extract_35); -assign pyc_or_40 = (pyc_and_38 | pyc_and_39); -assign pyc_and_41 = (pyc_extract_34 & pyc_extract_35); -assign pyc_or_42 = (pyc_or_40 | pyc_and_41); -assign pyc_extract_43 = PE_INT_WALLACE_DOT8_TREE_W19_in3[2]; -assign pyc_xor_44 = (pyc_xor_37 ^ pyc_extract_43); -assign pyc_xor_45 = (pyc_xor_44 ^ pyc_or_24); -assign pyc_and_46 = (pyc_xor_37 & pyc_extract_43); -assign pyc_and_47 = (pyc_xor_37 & pyc_or_24); -assign pyc_or_48 = (pyc_and_46 | pyc_and_47); -assign pyc_and_49 = (pyc_extract_43 & pyc_or_24); -assign pyc_or_50 = (pyc_or_48 | pyc_and_49); -assign pyc_extract_51 = PE_INT_WALLACE_DOT8_TREE_W19_in0[3]; -assign pyc_extract_52 = PE_INT_WALLACE_DOT8_TREE_W19_in1[3]; -assign pyc_extract_53 = PE_INT_WALLACE_DOT8_TREE_W19_in2[3]; -assign pyc_xor_54 = (pyc_extract_51 ^ pyc_extract_52); -assign pyc_xor_55 = (pyc_xor_54 ^ pyc_extract_53); -assign pyc_and_56 = (pyc_extract_51 & pyc_extract_52); -assign pyc_and_57 = (pyc_extract_51 & pyc_extract_53); -assign pyc_or_58 = (pyc_and_56 | pyc_and_57); -assign pyc_and_59 = (pyc_extract_52 & pyc_extract_53); -assign pyc_or_60 = (pyc_or_58 | pyc_and_59); -assign pyc_extract_61 = PE_INT_WALLACE_DOT8_TREE_W19_in3[3]; -assign pyc_xor_62 = (pyc_xor_55 ^ pyc_extract_61); -assign pyc_xor_63 = (pyc_xor_62 ^ pyc_or_42); -assign pyc_and_64 = (pyc_xor_55 & pyc_extract_61); -assign pyc_and_65 = (pyc_xor_55 & pyc_or_42); -assign pyc_or_66 = (pyc_and_64 | pyc_and_65); -assign pyc_and_67 = (pyc_extract_61 & pyc_or_42); -assign pyc_or_68 = (pyc_or_66 | pyc_and_67); -assign pyc_extract_69 = PE_INT_WALLACE_DOT8_TREE_W19_in0[4]; -assign pyc_extract_70 = PE_INT_WALLACE_DOT8_TREE_W19_in1[4]; -assign pyc_extract_71 = PE_INT_WALLACE_DOT8_TREE_W19_in2[4]; -assign pyc_xor_72 = (pyc_extract_69 ^ pyc_extract_70); -assign pyc_xor_73 = (pyc_xor_72 ^ pyc_extract_71); -assign pyc_and_74 = (pyc_extract_69 & pyc_extract_70); -assign pyc_and_75 = (pyc_extract_69 & pyc_extract_71); -assign pyc_or_76 = (pyc_and_74 | pyc_and_75); -assign pyc_and_77 = (pyc_extract_70 & pyc_extract_71); -assign pyc_or_78 = (pyc_or_76 | pyc_and_77); -assign pyc_extract_79 = PE_INT_WALLACE_DOT8_TREE_W19_in3[4]; -assign pyc_xor_80 = (pyc_xor_73 ^ pyc_extract_79); -assign pyc_xor_81 = (pyc_xor_80 ^ pyc_or_60); -assign pyc_and_82 = (pyc_xor_73 & pyc_extract_79); -assign pyc_and_83 = (pyc_xor_73 & pyc_or_60); -assign pyc_or_84 = (pyc_and_82 | pyc_and_83); -assign pyc_and_85 = (pyc_extract_79 & pyc_or_60); -assign pyc_or_86 = (pyc_or_84 | pyc_and_85); -assign pyc_extract_87 = PE_INT_WALLACE_DOT8_TREE_W19_in0[5]; -assign pyc_extract_88 = PE_INT_WALLACE_DOT8_TREE_W19_in1[5]; -assign pyc_extract_89 = PE_INT_WALLACE_DOT8_TREE_W19_in2[5]; -assign pyc_xor_90 = (pyc_extract_87 ^ pyc_extract_88); -assign pyc_xor_91 = (pyc_xor_90 ^ pyc_extract_89); -assign pyc_and_92 = (pyc_extract_87 & pyc_extract_88); -assign pyc_and_93 = (pyc_extract_87 & pyc_extract_89); -assign pyc_or_94 = (pyc_and_92 | pyc_and_93); -assign pyc_and_95 = (pyc_extract_88 & pyc_extract_89); -assign pyc_or_96 = (pyc_or_94 | pyc_and_95); -assign pyc_extract_97 = PE_INT_WALLACE_DOT8_TREE_W19_in3[5]; -assign pyc_xor_98 = (pyc_xor_91 ^ pyc_extract_97); -assign pyc_xor_99 = (pyc_xor_98 ^ pyc_or_78); -assign pyc_and_100 = (pyc_xor_91 & pyc_extract_97); -assign pyc_and_101 = (pyc_xor_91 & pyc_or_78); -assign pyc_or_102 = (pyc_and_100 | pyc_and_101); -assign pyc_and_103 = (pyc_extract_97 & pyc_or_78); -assign pyc_or_104 = (pyc_or_102 | pyc_and_103); -assign pyc_extract_105 = PE_INT_WALLACE_DOT8_TREE_W19_in0[6]; -assign pyc_extract_106 = PE_INT_WALLACE_DOT8_TREE_W19_in1[6]; -assign pyc_extract_107 = PE_INT_WALLACE_DOT8_TREE_W19_in2[6]; -assign pyc_xor_108 = (pyc_extract_105 ^ pyc_extract_106); -assign pyc_xor_109 = (pyc_xor_108 ^ pyc_extract_107); -assign pyc_and_110 = (pyc_extract_105 & pyc_extract_106); -assign pyc_and_111 = (pyc_extract_105 & pyc_extract_107); -assign pyc_or_112 = (pyc_and_110 | pyc_and_111); -assign pyc_and_113 = (pyc_extract_106 & pyc_extract_107); -assign pyc_or_114 = (pyc_or_112 | pyc_and_113); -assign pyc_extract_115 = PE_INT_WALLACE_DOT8_TREE_W19_in3[6]; -assign pyc_xor_116 = (pyc_xor_109 ^ pyc_extract_115); -assign pyc_xor_117 = (pyc_xor_116 ^ pyc_or_96); -assign pyc_and_118 = (pyc_xor_109 & pyc_extract_115); -assign pyc_and_119 = (pyc_xor_109 & pyc_or_96); -assign pyc_or_120 = (pyc_and_118 | pyc_and_119); -assign pyc_and_121 = (pyc_extract_115 & pyc_or_96); -assign pyc_or_122 = (pyc_or_120 | pyc_and_121); -assign pyc_extract_123 = PE_INT_WALLACE_DOT8_TREE_W19_in0[7]; -assign pyc_extract_124 = PE_INT_WALLACE_DOT8_TREE_W19_in1[7]; -assign pyc_extract_125 = PE_INT_WALLACE_DOT8_TREE_W19_in2[7]; -assign pyc_xor_126 = (pyc_extract_123 ^ pyc_extract_124); -assign pyc_xor_127 = (pyc_xor_126 ^ pyc_extract_125); -assign pyc_and_128 = (pyc_extract_123 & pyc_extract_124); -assign pyc_and_129 = (pyc_extract_123 & pyc_extract_125); -assign pyc_or_130 = (pyc_and_128 | pyc_and_129); -assign pyc_and_131 = (pyc_extract_124 & pyc_extract_125); -assign pyc_or_132 = (pyc_or_130 | pyc_and_131); -assign pyc_extract_133 = PE_INT_WALLACE_DOT8_TREE_W19_in3[7]; -assign pyc_xor_134 = (pyc_xor_127 ^ pyc_extract_133); -assign pyc_xor_135 = (pyc_xor_134 ^ pyc_or_114); -assign pyc_and_136 = (pyc_xor_127 & pyc_extract_133); -assign pyc_and_137 = (pyc_xor_127 & pyc_or_114); -assign pyc_or_138 = (pyc_and_136 | pyc_and_137); -assign pyc_and_139 = (pyc_extract_133 & pyc_or_114); -assign pyc_or_140 = (pyc_or_138 | pyc_and_139); -assign pyc_extract_141 = PE_INT_WALLACE_DOT8_TREE_W19_in0[8]; -assign pyc_extract_142 = PE_INT_WALLACE_DOT8_TREE_W19_in1[8]; -assign pyc_extract_143 = PE_INT_WALLACE_DOT8_TREE_W19_in2[8]; -assign pyc_xor_144 = (pyc_extract_141 ^ pyc_extract_142); -assign pyc_xor_145 = (pyc_xor_144 ^ pyc_extract_143); -assign pyc_and_146 = (pyc_extract_141 & pyc_extract_142); -assign pyc_and_147 = (pyc_extract_141 & pyc_extract_143); -assign pyc_or_148 = (pyc_and_146 | pyc_and_147); -assign pyc_and_149 = (pyc_extract_142 & pyc_extract_143); -assign pyc_or_150 = (pyc_or_148 | pyc_and_149); -assign pyc_extract_151 = PE_INT_WALLACE_DOT8_TREE_W19_in3[8]; -assign pyc_xor_152 = (pyc_xor_145 ^ pyc_extract_151); -assign pyc_xor_153 = (pyc_xor_152 ^ pyc_or_132); -assign pyc_and_154 = (pyc_xor_145 & pyc_extract_151); -assign pyc_and_155 = (pyc_xor_145 & pyc_or_132); -assign pyc_or_156 = (pyc_and_154 | pyc_and_155); -assign pyc_and_157 = (pyc_extract_151 & pyc_or_132); -assign pyc_or_158 = (pyc_or_156 | pyc_and_157); -assign pyc_extract_159 = PE_INT_WALLACE_DOT8_TREE_W19_in0[9]; -assign pyc_extract_160 = PE_INT_WALLACE_DOT8_TREE_W19_in1[9]; -assign pyc_extract_161 = PE_INT_WALLACE_DOT8_TREE_W19_in2[9]; -assign pyc_xor_162 = (pyc_extract_159 ^ pyc_extract_160); -assign pyc_xor_163 = (pyc_xor_162 ^ pyc_extract_161); -assign pyc_and_164 = (pyc_extract_159 & pyc_extract_160); -assign pyc_and_165 = (pyc_extract_159 & pyc_extract_161); -assign pyc_or_166 = (pyc_and_164 | pyc_and_165); -assign pyc_and_167 = (pyc_extract_160 & pyc_extract_161); -assign pyc_or_168 = (pyc_or_166 | pyc_and_167); -assign pyc_extract_169 = PE_INT_WALLACE_DOT8_TREE_W19_in3[9]; -assign pyc_xor_170 = (pyc_xor_163 ^ pyc_extract_169); -assign pyc_xor_171 = (pyc_xor_170 ^ pyc_or_150); -assign pyc_and_172 = (pyc_xor_163 & pyc_extract_169); -assign pyc_and_173 = (pyc_xor_163 & pyc_or_150); -assign pyc_or_174 = (pyc_and_172 | pyc_and_173); -assign pyc_and_175 = (pyc_extract_169 & pyc_or_150); -assign pyc_or_176 = (pyc_or_174 | pyc_and_175); -assign pyc_extract_177 = PE_INT_WALLACE_DOT8_TREE_W19_in0[10]; -assign pyc_extract_178 = PE_INT_WALLACE_DOT8_TREE_W19_in1[10]; -assign pyc_extract_179 = PE_INT_WALLACE_DOT8_TREE_W19_in2[10]; -assign pyc_xor_180 = (pyc_extract_177 ^ pyc_extract_178); -assign pyc_xor_181 = (pyc_xor_180 ^ pyc_extract_179); -assign pyc_and_182 = (pyc_extract_177 & pyc_extract_178); -assign pyc_and_183 = (pyc_extract_177 & pyc_extract_179); -assign pyc_or_184 = (pyc_and_182 | pyc_and_183); -assign pyc_and_185 = (pyc_extract_178 & pyc_extract_179); -assign pyc_or_186 = (pyc_or_184 | pyc_and_185); -assign pyc_extract_187 = PE_INT_WALLACE_DOT8_TREE_W19_in3[10]; -assign pyc_xor_188 = (pyc_xor_181 ^ pyc_extract_187); -assign pyc_xor_189 = (pyc_xor_188 ^ pyc_or_168); -assign pyc_and_190 = (pyc_xor_181 & pyc_extract_187); -assign pyc_and_191 = (pyc_xor_181 & pyc_or_168); -assign pyc_or_192 = (pyc_and_190 | pyc_and_191); -assign pyc_and_193 = (pyc_extract_187 & pyc_or_168); -assign pyc_or_194 = (pyc_or_192 | pyc_and_193); -assign pyc_extract_195 = PE_INT_WALLACE_DOT8_TREE_W19_in0[11]; -assign pyc_extract_196 = PE_INT_WALLACE_DOT8_TREE_W19_in1[11]; -assign pyc_extract_197 = PE_INT_WALLACE_DOT8_TREE_W19_in2[11]; -assign pyc_xor_198 = (pyc_extract_195 ^ pyc_extract_196); -assign pyc_xor_199 = (pyc_xor_198 ^ pyc_extract_197); -assign pyc_and_200 = (pyc_extract_195 & pyc_extract_196); -assign pyc_and_201 = (pyc_extract_195 & pyc_extract_197); -assign pyc_or_202 = (pyc_and_200 | pyc_and_201); -assign pyc_and_203 = (pyc_extract_196 & pyc_extract_197); -assign pyc_or_204 = (pyc_or_202 | pyc_and_203); -assign pyc_extract_205 = PE_INT_WALLACE_DOT8_TREE_W19_in3[11]; -assign pyc_xor_206 = (pyc_xor_199 ^ pyc_extract_205); -assign pyc_xor_207 = (pyc_xor_206 ^ pyc_or_186); -assign pyc_and_208 = (pyc_xor_199 & pyc_extract_205); -assign pyc_and_209 = (pyc_xor_199 & pyc_or_186); -assign pyc_or_210 = (pyc_and_208 | pyc_and_209); -assign pyc_and_211 = (pyc_extract_205 & pyc_or_186); -assign pyc_or_212 = (pyc_or_210 | pyc_and_211); -assign pyc_extract_213 = PE_INT_WALLACE_DOT8_TREE_W19_in0[12]; -assign pyc_extract_214 = PE_INT_WALLACE_DOT8_TREE_W19_in1[12]; -assign pyc_extract_215 = PE_INT_WALLACE_DOT8_TREE_W19_in2[12]; -assign pyc_xor_216 = (pyc_extract_213 ^ pyc_extract_214); -assign pyc_xor_217 = (pyc_xor_216 ^ pyc_extract_215); -assign pyc_and_218 = (pyc_extract_213 & pyc_extract_214); -assign pyc_and_219 = (pyc_extract_213 & pyc_extract_215); -assign pyc_or_220 = (pyc_and_218 | pyc_and_219); -assign pyc_and_221 = (pyc_extract_214 & pyc_extract_215); -assign pyc_or_222 = (pyc_or_220 | pyc_and_221); -assign pyc_extract_223 = PE_INT_WALLACE_DOT8_TREE_W19_in3[12]; -assign pyc_xor_224 = (pyc_xor_217 ^ pyc_extract_223); -assign pyc_xor_225 = (pyc_xor_224 ^ pyc_or_204); -assign pyc_and_226 = (pyc_xor_217 & pyc_extract_223); -assign pyc_and_227 = (pyc_xor_217 & pyc_or_204); -assign pyc_or_228 = (pyc_and_226 | pyc_and_227); -assign pyc_and_229 = (pyc_extract_223 & pyc_or_204); -assign pyc_or_230 = (pyc_or_228 | pyc_and_229); -assign pyc_extract_231 = PE_INT_WALLACE_DOT8_TREE_W19_in0[13]; -assign pyc_extract_232 = PE_INT_WALLACE_DOT8_TREE_W19_in1[13]; -assign pyc_extract_233 = PE_INT_WALLACE_DOT8_TREE_W19_in2[13]; -assign pyc_xor_234 = (pyc_extract_231 ^ pyc_extract_232); -assign pyc_xor_235 = (pyc_xor_234 ^ pyc_extract_233); -assign pyc_and_236 = (pyc_extract_231 & pyc_extract_232); -assign pyc_and_237 = (pyc_extract_231 & pyc_extract_233); -assign pyc_or_238 = (pyc_and_236 | pyc_and_237); -assign pyc_and_239 = (pyc_extract_232 & pyc_extract_233); -assign pyc_or_240 = (pyc_or_238 | pyc_and_239); -assign pyc_extract_241 = PE_INT_WALLACE_DOT8_TREE_W19_in3[13]; -assign pyc_xor_242 = (pyc_xor_235 ^ pyc_extract_241); -assign pyc_xor_243 = (pyc_xor_242 ^ pyc_or_222); -assign pyc_and_244 = (pyc_xor_235 & pyc_extract_241); -assign pyc_and_245 = (pyc_xor_235 & pyc_or_222); -assign pyc_or_246 = (pyc_and_244 | pyc_and_245); -assign pyc_and_247 = (pyc_extract_241 & pyc_or_222); -assign pyc_or_248 = (pyc_or_246 | pyc_and_247); -assign pyc_extract_249 = PE_INT_WALLACE_DOT8_TREE_W19_in0[14]; -assign pyc_extract_250 = PE_INT_WALLACE_DOT8_TREE_W19_in1[14]; -assign pyc_extract_251 = PE_INT_WALLACE_DOT8_TREE_W19_in2[14]; -assign pyc_xor_252 = (pyc_extract_249 ^ pyc_extract_250); -assign pyc_xor_253 = (pyc_xor_252 ^ pyc_extract_251); -assign pyc_and_254 = (pyc_extract_249 & pyc_extract_250); -assign pyc_and_255 = (pyc_extract_249 & pyc_extract_251); -assign pyc_or_256 = (pyc_and_254 | pyc_and_255); -assign pyc_and_257 = (pyc_extract_250 & pyc_extract_251); -assign pyc_or_258 = (pyc_or_256 | pyc_and_257); -assign pyc_extract_259 = PE_INT_WALLACE_DOT8_TREE_W19_in3[14]; -assign pyc_xor_260 = (pyc_xor_253 ^ pyc_extract_259); -assign pyc_xor_261 = (pyc_xor_260 ^ pyc_or_240); -assign pyc_and_262 = (pyc_xor_253 & pyc_extract_259); -assign pyc_and_263 = (pyc_xor_253 & pyc_or_240); -assign pyc_or_264 = (pyc_and_262 | pyc_and_263); -assign pyc_and_265 = (pyc_extract_259 & pyc_or_240); -assign pyc_or_266 = (pyc_or_264 | pyc_and_265); -assign pyc_extract_267 = PE_INT_WALLACE_DOT8_TREE_W19_in0[15]; -assign pyc_extract_268 = PE_INT_WALLACE_DOT8_TREE_W19_in1[15]; -assign pyc_extract_269 = PE_INT_WALLACE_DOT8_TREE_W19_in2[15]; -assign pyc_xor_270 = (pyc_extract_267 ^ pyc_extract_268); -assign pyc_xor_271 = (pyc_xor_270 ^ pyc_extract_269); -assign pyc_and_272 = (pyc_extract_267 & pyc_extract_268); -assign pyc_and_273 = (pyc_extract_267 & pyc_extract_269); -assign pyc_or_274 = (pyc_and_272 | pyc_and_273); -assign pyc_and_275 = (pyc_extract_268 & pyc_extract_269); -assign pyc_or_276 = (pyc_or_274 | pyc_and_275); -assign pyc_extract_277 = PE_INT_WALLACE_DOT8_TREE_W19_in3[15]; -assign pyc_xor_278 = (pyc_xor_271 ^ pyc_extract_277); -assign pyc_xor_279 = (pyc_xor_278 ^ pyc_or_258); -assign pyc_and_280 = (pyc_xor_271 & pyc_extract_277); -assign pyc_and_281 = (pyc_xor_271 & pyc_or_258); -assign pyc_or_282 = (pyc_and_280 | pyc_and_281); -assign pyc_and_283 = (pyc_extract_277 & pyc_or_258); -assign pyc_or_284 = (pyc_or_282 | pyc_and_283); -assign pyc_extract_285 = PE_INT_WALLACE_DOT8_TREE_W19_in0[16]; -assign pyc_extract_286 = PE_INT_WALLACE_DOT8_TREE_W19_in1[16]; -assign pyc_extract_287 = PE_INT_WALLACE_DOT8_TREE_W19_in2[16]; -assign pyc_xor_288 = (pyc_extract_285 ^ pyc_extract_286); -assign pyc_xor_289 = (pyc_xor_288 ^ pyc_extract_287); -assign pyc_and_290 = (pyc_extract_285 & pyc_extract_286); -assign pyc_and_291 = (pyc_extract_285 & pyc_extract_287); -assign pyc_or_292 = (pyc_and_290 | pyc_and_291); -assign pyc_and_293 = (pyc_extract_286 & pyc_extract_287); -assign pyc_or_294 = (pyc_or_292 | pyc_and_293); -assign pyc_extract_295 = PE_INT_WALLACE_DOT8_TREE_W19_in3[16]; -assign pyc_xor_296 = (pyc_xor_289 ^ pyc_extract_295); -assign pyc_xor_297 = (pyc_xor_296 ^ pyc_or_276); -assign pyc_and_298 = (pyc_xor_289 & pyc_extract_295); -assign pyc_and_299 = (pyc_xor_289 & pyc_or_276); -assign pyc_or_300 = (pyc_and_298 | pyc_and_299); -assign pyc_and_301 = (pyc_extract_295 & pyc_or_276); -assign pyc_or_302 = (pyc_or_300 | pyc_and_301); -assign pyc_extract_303 = PE_INT_WALLACE_DOT8_TREE_W19_in0[17]; -assign pyc_extract_304 = PE_INT_WALLACE_DOT8_TREE_W19_in1[17]; -assign pyc_extract_305 = PE_INT_WALLACE_DOT8_TREE_W19_in2[17]; -assign pyc_xor_306 = (pyc_extract_303 ^ pyc_extract_304); -assign pyc_xor_307 = (pyc_xor_306 ^ pyc_extract_305); -assign pyc_and_308 = (pyc_extract_303 & pyc_extract_304); -assign pyc_and_309 = (pyc_extract_303 & pyc_extract_305); -assign pyc_or_310 = (pyc_and_308 | pyc_and_309); -assign pyc_and_311 = (pyc_extract_304 & pyc_extract_305); -assign pyc_or_312 = (pyc_or_310 | pyc_and_311); -assign pyc_extract_313 = PE_INT_WALLACE_DOT8_TREE_W19_in3[17]; -assign pyc_xor_314 = (pyc_xor_307 ^ pyc_extract_313); -assign pyc_xor_315 = (pyc_xor_314 ^ pyc_or_294); -assign pyc_and_316 = (pyc_xor_307 & pyc_extract_313); -assign pyc_and_317 = (pyc_xor_307 & pyc_or_294); -assign pyc_or_318 = (pyc_and_316 | pyc_and_317); -assign pyc_and_319 = (pyc_extract_313 & pyc_or_294); -assign pyc_or_320 = (pyc_or_318 | pyc_and_319); -assign pyc_extract_321 = PE_INT_WALLACE_DOT8_TREE_W19_in0[18]; -assign pyc_extract_322 = PE_INT_WALLACE_DOT8_TREE_W19_in1[18]; -assign pyc_extract_323 = PE_INT_WALLACE_DOT8_TREE_W19_in2[18]; -assign pyc_xor_324 = (pyc_extract_321 ^ pyc_extract_322); -assign pyc_xor_325 = (pyc_xor_324 ^ pyc_extract_323); -assign pyc_extract_326 = PE_INT_WALLACE_DOT8_TREE_W19_in3[18]; -assign pyc_xor_327 = (pyc_xor_325 ^ pyc_extract_326); -assign pyc_xor_328 = (pyc_xor_327 ^ pyc_or_312); -assign pyc_extract_329 = PE_INT_WALLACE_DOT8_TREE_W19_in4[0]; -assign pyc_extract_330 = PE_INT_WALLACE_DOT8_TREE_W19_in5[0]; -assign pyc_extract_331 = PE_INT_WALLACE_DOT8_TREE_W19_in6[0]; -assign pyc_xor_332 = (pyc_extract_329 ^ pyc_extract_330); -assign pyc_xor_333 = (pyc_xor_332 ^ pyc_extract_331); -assign pyc_and_334 = (pyc_extract_329 & pyc_extract_330); -assign pyc_and_335 = (pyc_extract_329 & pyc_extract_331); -assign pyc_or_336 = (pyc_and_334 | pyc_and_335); -assign pyc_and_337 = (pyc_extract_330 & pyc_extract_331); -assign pyc_or_338 = (pyc_or_336 | pyc_and_337); -assign pyc_extract_339 = PE_INT_WALLACE_DOT8_TREE_W19_in7[0]; -assign pyc_xor_340 = (pyc_xor_333 ^ pyc_extract_339); -assign pyc_and_341 = (pyc_xor_333 & pyc_extract_339); -assign pyc_extract_342 = PE_INT_WALLACE_DOT8_TREE_W19_in4[1]; -assign pyc_extract_343 = PE_INT_WALLACE_DOT8_TREE_W19_in5[1]; -assign pyc_extract_344 = PE_INT_WALLACE_DOT8_TREE_W19_in6[1]; -assign pyc_xor_345 = (pyc_extract_342 ^ pyc_extract_343); -assign pyc_xor_346 = (pyc_xor_345 ^ pyc_extract_344); -assign pyc_and_347 = (pyc_extract_342 & pyc_extract_343); -assign pyc_and_348 = (pyc_extract_342 & pyc_extract_344); -assign pyc_or_349 = (pyc_and_347 | pyc_and_348); -assign pyc_and_350 = (pyc_extract_343 & pyc_extract_344); -assign pyc_or_351 = (pyc_or_349 | pyc_and_350); -assign pyc_extract_352 = PE_INT_WALLACE_DOT8_TREE_W19_in7[1]; -assign pyc_xor_353 = (pyc_xor_346 ^ pyc_extract_352); -assign pyc_xor_354 = (pyc_xor_353 ^ pyc_or_338); -assign pyc_and_355 = (pyc_xor_346 & pyc_extract_352); -assign pyc_and_356 = (pyc_xor_346 & pyc_or_338); -assign pyc_or_357 = (pyc_and_355 | pyc_and_356); -assign pyc_and_358 = (pyc_extract_352 & pyc_or_338); -assign pyc_or_359 = (pyc_or_357 | pyc_and_358); -assign pyc_extract_360 = PE_INT_WALLACE_DOT8_TREE_W19_in4[2]; -assign pyc_extract_361 = PE_INT_WALLACE_DOT8_TREE_W19_in5[2]; -assign pyc_extract_362 = PE_INT_WALLACE_DOT8_TREE_W19_in6[2]; -assign pyc_xor_363 = (pyc_extract_360 ^ pyc_extract_361); -assign pyc_xor_364 = (pyc_xor_363 ^ pyc_extract_362); -assign pyc_and_365 = (pyc_extract_360 & pyc_extract_361); -assign pyc_and_366 = (pyc_extract_360 & pyc_extract_362); -assign pyc_or_367 = (pyc_and_365 | pyc_and_366); -assign pyc_and_368 = (pyc_extract_361 & pyc_extract_362); -assign pyc_or_369 = (pyc_or_367 | pyc_and_368); -assign pyc_extract_370 = PE_INT_WALLACE_DOT8_TREE_W19_in7[2]; -assign pyc_xor_371 = (pyc_xor_364 ^ pyc_extract_370); -assign pyc_xor_372 = (pyc_xor_371 ^ pyc_or_351); -assign pyc_and_373 = (pyc_xor_364 & pyc_extract_370); -assign pyc_and_374 = (pyc_xor_364 & pyc_or_351); -assign pyc_or_375 = (pyc_and_373 | pyc_and_374); -assign pyc_and_376 = (pyc_extract_370 & pyc_or_351); -assign pyc_or_377 = (pyc_or_375 | pyc_and_376); -assign pyc_extract_378 = PE_INT_WALLACE_DOT8_TREE_W19_in4[3]; -assign pyc_extract_379 = PE_INT_WALLACE_DOT8_TREE_W19_in5[3]; -assign pyc_extract_380 = PE_INT_WALLACE_DOT8_TREE_W19_in6[3]; -assign pyc_xor_381 = (pyc_extract_378 ^ pyc_extract_379); -assign pyc_xor_382 = (pyc_xor_381 ^ pyc_extract_380); -assign pyc_and_383 = (pyc_extract_378 & pyc_extract_379); -assign pyc_and_384 = (pyc_extract_378 & pyc_extract_380); -assign pyc_or_385 = (pyc_and_383 | pyc_and_384); -assign pyc_and_386 = (pyc_extract_379 & pyc_extract_380); -assign pyc_or_387 = (pyc_or_385 | pyc_and_386); -assign pyc_extract_388 = PE_INT_WALLACE_DOT8_TREE_W19_in7[3]; -assign pyc_xor_389 = (pyc_xor_382 ^ pyc_extract_388); -assign pyc_xor_390 = (pyc_xor_389 ^ pyc_or_369); -assign pyc_and_391 = (pyc_xor_382 & pyc_extract_388); -assign pyc_and_392 = (pyc_xor_382 & pyc_or_369); -assign pyc_or_393 = (pyc_and_391 | pyc_and_392); -assign pyc_and_394 = (pyc_extract_388 & pyc_or_369); -assign pyc_or_395 = (pyc_or_393 | pyc_and_394); -assign pyc_extract_396 = PE_INT_WALLACE_DOT8_TREE_W19_in4[4]; -assign pyc_extract_397 = PE_INT_WALLACE_DOT8_TREE_W19_in5[4]; -assign pyc_extract_398 = PE_INT_WALLACE_DOT8_TREE_W19_in6[4]; -assign pyc_xor_399 = (pyc_extract_396 ^ pyc_extract_397); -assign pyc_xor_400 = (pyc_xor_399 ^ pyc_extract_398); -assign pyc_and_401 = (pyc_extract_396 & pyc_extract_397); -assign pyc_and_402 = (pyc_extract_396 & pyc_extract_398); -assign pyc_or_403 = (pyc_and_401 | pyc_and_402); -assign pyc_and_404 = (pyc_extract_397 & pyc_extract_398); -assign pyc_or_405 = (pyc_or_403 | pyc_and_404); -assign pyc_extract_406 = PE_INT_WALLACE_DOT8_TREE_W19_in7[4]; -assign pyc_xor_407 = (pyc_xor_400 ^ pyc_extract_406); -assign pyc_xor_408 = (pyc_xor_407 ^ pyc_or_387); -assign pyc_and_409 = (pyc_xor_400 & pyc_extract_406); -assign pyc_and_410 = (pyc_xor_400 & pyc_or_387); -assign pyc_or_411 = (pyc_and_409 | pyc_and_410); -assign pyc_and_412 = (pyc_extract_406 & pyc_or_387); -assign pyc_or_413 = (pyc_or_411 | pyc_and_412); -assign pyc_extract_414 = PE_INT_WALLACE_DOT8_TREE_W19_in4[5]; -assign pyc_extract_415 = PE_INT_WALLACE_DOT8_TREE_W19_in5[5]; -assign pyc_extract_416 = PE_INT_WALLACE_DOT8_TREE_W19_in6[5]; -assign pyc_xor_417 = (pyc_extract_414 ^ pyc_extract_415); -assign pyc_xor_418 = (pyc_xor_417 ^ pyc_extract_416); -assign pyc_and_419 = (pyc_extract_414 & pyc_extract_415); -assign pyc_and_420 = (pyc_extract_414 & pyc_extract_416); -assign pyc_or_421 = (pyc_and_419 | pyc_and_420); -assign pyc_and_422 = (pyc_extract_415 & pyc_extract_416); -assign pyc_or_423 = (pyc_or_421 | pyc_and_422); -assign pyc_extract_424 = PE_INT_WALLACE_DOT8_TREE_W19_in7[5]; -assign pyc_xor_425 = (pyc_xor_418 ^ pyc_extract_424); -assign pyc_xor_426 = (pyc_xor_425 ^ pyc_or_405); -assign pyc_and_427 = (pyc_xor_418 & pyc_extract_424); -assign pyc_and_428 = (pyc_xor_418 & pyc_or_405); -assign pyc_or_429 = (pyc_and_427 | pyc_and_428); -assign pyc_and_430 = (pyc_extract_424 & pyc_or_405); -assign pyc_or_431 = (pyc_or_429 | pyc_and_430); -assign pyc_extract_432 = PE_INT_WALLACE_DOT8_TREE_W19_in4[6]; -assign pyc_extract_433 = PE_INT_WALLACE_DOT8_TREE_W19_in5[6]; -assign pyc_extract_434 = PE_INT_WALLACE_DOT8_TREE_W19_in6[6]; -assign pyc_xor_435 = (pyc_extract_432 ^ pyc_extract_433); -assign pyc_xor_436 = (pyc_xor_435 ^ pyc_extract_434); -assign pyc_and_437 = (pyc_extract_432 & pyc_extract_433); -assign pyc_and_438 = (pyc_extract_432 & pyc_extract_434); -assign pyc_or_439 = (pyc_and_437 | pyc_and_438); -assign pyc_and_440 = (pyc_extract_433 & pyc_extract_434); -assign pyc_or_441 = (pyc_or_439 | pyc_and_440); -assign pyc_extract_442 = PE_INT_WALLACE_DOT8_TREE_W19_in7[6]; -assign pyc_xor_443 = (pyc_xor_436 ^ pyc_extract_442); -assign pyc_xor_444 = (pyc_xor_443 ^ pyc_or_423); -assign pyc_and_445 = (pyc_xor_436 & pyc_extract_442); -assign pyc_and_446 = (pyc_xor_436 & pyc_or_423); -assign pyc_or_447 = (pyc_and_445 | pyc_and_446); -assign pyc_and_448 = (pyc_extract_442 & pyc_or_423); -assign pyc_or_449 = (pyc_or_447 | pyc_and_448); -assign pyc_extract_450 = PE_INT_WALLACE_DOT8_TREE_W19_in4[7]; -assign pyc_extract_451 = PE_INT_WALLACE_DOT8_TREE_W19_in5[7]; -assign pyc_extract_452 = PE_INT_WALLACE_DOT8_TREE_W19_in6[7]; -assign pyc_xor_453 = (pyc_extract_450 ^ pyc_extract_451); -assign pyc_xor_454 = (pyc_xor_453 ^ pyc_extract_452); -assign pyc_and_455 = (pyc_extract_450 & pyc_extract_451); -assign pyc_and_456 = (pyc_extract_450 & pyc_extract_452); -assign pyc_or_457 = (pyc_and_455 | pyc_and_456); -assign pyc_and_458 = (pyc_extract_451 & pyc_extract_452); -assign pyc_or_459 = (pyc_or_457 | pyc_and_458); -assign pyc_extract_460 = PE_INT_WALLACE_DOT8_TREE_W19_in7[7]; -assign pyc_xor_461 = (pyc_xor_454 ^ pyc_extract_460); -assign pyc_xor_462 = (pyc_xor_461 ^ pyc_or_441); -assign pyc_and_463 = (pyc_xor_454 & pyc_extract_460); -assign pyc_and_464 = (pyc_xor_454 & pyc_or_441); -assign pyc_or_465 = (pyc_and_463 | pyc_and_464); -assign pyc_and_466 = (pyc_extract_460 & pyc_or_441); -assign pyc_or_467 = (pyc_or_465 | pyc_and_466); -assign pyc_extract_468 = PE_INT_WALLACE_DOT8_TREE_W19_in4[8]; -assign pyc_extract_469 = PE_INT_WALLACE_DOT8_TREE_W19_in5[8]; -assign pyc_extract_470 = PE_INT_WALLACE_DOT8_TREE_W19_in6[8]; -assign pyc_xor_471 = (pyc_extract_468 ^ pyc_extract_469); -assign pyc_xor_472 = (pyc_xor_471 ^ pyc_extract_470); -assign pyc_and_473 = (pyc_extract_468 & pyc_extract_469); -assign pyc_and_474 = (pyc_extract_468 & pyc_extract_470); -assign pyc_or_475 = (pyc_and_473 | pyc_and_474); -assign pyc_and_476 = (pyc_extract_469 & pyc_extract_470); -assign pyc_or_477 = (pyc_or_475 | pyc_and_476); -assign pyc_extract_478 = PE_INT_WALLACE_DOT8_TREE_W19_in7[8]; -assign pyc_xor_479 = (pyc_xor_472 ^ pyc_extract_478); -assign pyc_xor_480 = (pyc_xor_479 ^ pyc_or_459); -assign pyc_and_481 = (pyc_xor_472 & pyc_extract_478); -assign pyc_and_482 = (pyc_xor_472 & pyc_or_459); -assign pyc_or_483 = (pyc_and_481 | pyc_and_482); -assign pyc_and_484 = (pyc_extract_478 & pyc_or_459); -assign pyc_or_485 = (pyc_or_483 | pyc_and_484); -assign pyc_extract_486 = PE_INT_WALLACE_DOT8_TREE_W19_in4[9]; -assign pyc_extract_487 = PE_INT_WALLACE_DOT8_TREE_W19_in5[9]; -assign pyc_extract_488 = PE_INT_WALLACE_DOT8_TREE_W19_in6[9]; -assign pyc_xor_489 = (pyc_extract_486 ^ pyc_extract_487); -assign pyc_xor_490 = (pyc_xor_489 ^ pyc_extract_488); -assign pyc_and_491 = (pyc_extract_486 & pyc_extract_487); -assign pyc_and_492 = (pyc_extract_486 & pyc_extract_488); -assign pyc_or_493 = (pyc_and_491 | pyc_and_492); -assign pyc_and_494 = (pyc_extract_487 & pyc_extract_488); -assign pyc_or_495 = (pyc_or_493 | pyc_and_494); -assign pyc_extract_496 = PE_INT_WALLACE_DOT8_TREE_W19_in7[9]; -assign pyc_xor_497 = (pyc_xor_490 ^ pyc_extract_496); -assign pyc_xor_498 = (pyc_xor_497 ^ pyc_or_477); -assign pyc_and_499 = (pyc_xor_490 & pyc_extract_496); -assign pyc_and_500 = (pyc_xor_490 & pyc_or_477); -assign pyc_or_501 = (pyc_and_499 | pyc_and_500); -assign pyc_and_502 = (pyc_extract_496 & pyc_or_477); -assign pyc_or_503 = (pyc_or_501 | pyc_and_502); -assign pyc_extract_504 = PE_INT_WALLACE_DOT8_TREE_W19_in4[10]; -assign pyc_extract_505 = PE_INT_WALLACE_DOT8_TREE_W19_in5[10]; -assign pyc_extract_506 = PE_INT_WALLACE_DOT8_TREE_W19_in6[10]; -assign pyc_xor_507 = (pyc_extract_504 ^ pyc_extract_505); -assign pyc_xor_508 = (pyc_xor_507 ^ pyc_extract_506); -assign pyc_and_509 = (pyc_extract_504 & pyc_extract_505); -assign pyc_and_510 = (pyc_extract_504 & pyc_extract_506); -assign pyc_or_511 = (pyc_and_509 | pyc_and_510); -assign pyc_and_512 = (pyc_extract_505 & pyc_extract_506); -assign pyc_or_513 = (pyc_or_511 | pyc_and_512); -assign pyc_extract_514 = PE_INT_WALLACE_DOT8_TREE_W19_in7[10]; -assign pyc_xor_515 = (pyc_xor_508 ^ pyc_extract_514); -assign pyc_xor_516 = (pyc_xor_515 ^ pyc_or_495); -assign pyc_and_517 = (pyc_xor_508 & pyc_extract_514); -assign pyc_and_518 = (pyc_xor_508 & pyc_or_495); -assign pyc_or_519 = (pyc_and_517 | pyc_and_518); -assign pyc_and_520 = (pyc_extract_514 & pyc_or_495); -assign pyc_or_521 = (pyc_or_519 | pyc_and_520); -assign pyc_extract_522 = PE_INT_WALLACE_DOT8_TREE_W19_in4[11]; -assign pyc_extract_523 = PE_INT_WALLACE_DOT8_TREE_W19_in5[11]; -assign pyc_extract_524 = PE_INT_WALLACE_DOT8_TREE_W19_in6[11]; -assign pyc_xor_525 = (pyc_extract_522 ^ pyc_extract_523); -assign pyc_xor_526 = (pyc_xor_525 ^ pyc_extract_524); -assign pyc_and_527 = (pyc_extract_522 & pyc_extract_523); -assign pyc_and_528 = (pyc_extract_522 & pyc_extract_524); -assign pyc_or_529 = (pyc_and_527 | pyc_and_528); -assign pyc_and_530 = (pyc_extract_523 & pyc_extract_524); -assign pyc_or_531 = (pyc_or_529 | pyc_and_530); -assign pyc_extract_532 = PE_INT_WALLACE_DOT8_TREE_W19_in7[11]; -assign pyc_xor_533 = (pyc_xor_526 ^ pyc_extract_532); -assign pyc_xor_534 = (pyc_xor_533 ^ pyc_or_513); -assign pyc_and_535 = (pyc_xor_526 & pyc_extract_532); -assign pyc_and_536 = (pyc_xor_526 & pyc_or_513); -assign pyc_or_537 = (pyc_and_535 | pyc_and_536); -assign pyc_and_538 = (pyc_extract_532 & pyc_or_513); -assign pyc_or_539 = (pyc_or_537 | pyc_and_538); -assign pyc_extract_540 = PE_INT_WALLACE_DOT8_TREE_W19_in4[12]; -assign pyc_extract_541 = PE_INT_WALLACE_DOT8_TREE_W19_in5[12]; -assign pyc_extract_542 = PE_INT_WALLACE_DOT8_TREE_W19_in6[12]; -assign pyc_xor_543 = (pyc_extract_540 ^ pyc_extract_541); -assign pyc_xor_544 = (pyc_xor_543 ^ pyc_extract_542); -assign pyc_and_545 = (pyc_extract_540 & pyc_extract_541); -assign pyc_and_546 = (pyc_extract_540 & pyc_extract_542); -assign pyc_or_547 = (pyc_and_545 | pyc_and_546); -assign pyc_and_548 = (pyc_extract_541 & pyc_extract_542); -assign pyc_or_549 = (pyc_or_547 | pyc_and_548); -assign pyc_extract_550 = PE_INT_WALLACE_DOT8_TREE_W19_in7[12]; -assign pyc_xor_551 = (pyc_xor_544 ^ pyc_extract_550); -assign pyc_xor_552 = (pyc_xor_551 ^ pyc_or_531); -assign pyc_and_553 = (pyc_xor_544 & pyc_extract_550); -assign pyc_and_554 = (pyc_xor_544 & pyc_or_531); -assign pyc_or_555 = (pyc_and_553 | pyc_and_554); -assign pyc_and_556 = (pyc_extract_550 & pyc_or_531); -assign pyc_or_557 = (pyc_or_555 | pyc_and_556); -assign pyc_extract_558 = PE_INT_WALLACE_DOT8_TREE_W19_in4[13]; -assign pyc_extract_559 = PE_INT_WALLACE_DOT8_TREE_W19_in5[13]; -assign pyc_extract_560 = PE_INT_WALLACE_DOT8_TREE_W19_in6[13]; -assign pyc_xor_561 = (pyc_extract_558 ^ pyc_extract_559); -assign pyc_xor_562 = (pyc_xor_561 ^ pyc_extract_560); -assign pyc_and_563 = (pyc_extract_558 & pyc_extract_559); -assign pyc_and_564 = (pyc_extract_558 & pyc_extract_560); -assign pyc_or_565 = (pyc_and_563 | pyc_and_564); -assign pyc_and_566 = (pyc_extract_559 & pyc_extract_560); -assign pyc_or_567 = (pyc_or_565 | pyc_and_566); -assign pyc_extract_568 = PE_INT_WALLACE_DOT8_TREE_W19_in7[13]; -assign pyc_xor_569 = (pyc_xor_562 ^ pyc_extract_568); -assign pyc_xor_570 = (pyc_xor_569 ^ pyc_or_549); -assign pyc_and_571 = (pyc_xor_562 & pyc_extract_568); -assign pyc_and_572 = (pyc_xor_562 & pyc_or_549); -assign pyc_or_573 = (pyc_and_571 | pyc_and_572); -assign pyc_and_574 = (pyc_extract_568 & pyc_or_549); -assign pyc_or_575 = (pyc_or_573 | pyc_and_574); -assign pyc_extract_576 = PE_INT_WALLACE_DOT8_TREE_W19_in4[14]; -assign pyc_extract_577 = PE_INT_WALLACE_DOT8_TREE_W19_in5[14]; -assign pyc_extract_578 = PE_INT_WALLACE_DOT8_TREE_W19_in6[14]; -assign pyc_xor_579 = (pyc_extract_576 ^ pyc_extract_577); -assign pyc_xor_580 = (pyc_xor_579 ^ pyc_extract_578); -assign pyc_and_581 = (pyc_extract_576 & pyc_extract_577); -assign pyc_and_582 = (pyc_extract_576 & pyc_extract_578); -assign pyc_or_583 = (pyc_and_581 | pyc_and_582); -assign pyc_and_584 = (pyc_extract_577 & pyc_extract_578); -assign pyc_or_585 = (pyc_or_583 | pyc_and_584); -assign pyc_extract_586 = PE_INT_WALLACE_DOT8_TREE_W19_in7[14]; -assign pyc_xor_587 = (pyc_xor_580 ^ pyc_extract_586); -assign pyc_xor_588 = (pyc_xor_587 ^ pyc_or_567); -assign pyc_and_589 = (pyc_xor_580 & pyc_extract_586); -assign pyc_and_590 = (pyc_xor_580 & pyc_or_567); -assign pyc_or_591 = (pyc_and_589 | pyc_and_590); -assign pyc_and_592 = (pyc_extract_586 & pyc_or_567); -assign pyc_or_593 = (pyc_or_591 | pyc_and_592); -assign pyc_extract_594 = PE_INT_WALLACE_DOT8_TREE_W19_in4[15]; -assign pyc_extract_595 = PE_INT_WALLACE_DOT8_TREE_W19_in5[15]; -assign pyc_extract_596 = PE_INT_WALLACE_DOT8_TREE_W19_in6[15]; -assign pyc_xor_597 = (pyc_extract_594 ^ pyc_extract_595); -assign pyc_xor_598 = (pyc_xor_597 ^ pyc_extract_596); -assign pyc_and_599 = (pyc_extract_594 & pyc_extract_595); -assign pyc_and_600 = (pyc_extract_594 & pyc_extract_596); -assign pyc_or_601 = (pyc_and_599 | pyc_and_600); -assign pyc_and_602 = (pyc_extract_595 & pyc_extract_596); -assign pyc_or_603 = (pyc_or_601 | pyc_and_602); -assign pyc_extract_604 = PE_INT_WALLACE_DOT8_TREE_W19_in7[15]; -assign pyc_xor_605 = (pyc_xor_598 ^ pyc_extract_604); -assign pyc_xor_606 = (pyc_xor_605 ^ pyc_or_585); -assign pyc_and_607 = (pyc_xor_598 & pyc_extract_604); -assign pyc_and_608 = (pyc_xor_598 & pyc_or_585); -assign pyc_or_609 = (pyc_and_607 | pyc_and_608); -assign pyc_and_610 = (pyc_extract_604 & pyc_or_585); -assign pyc_or_611 = (pyc_or_609 | pyc_and_610); -assign pyc_extract_612 = PE_INT_WALLACE_DOT8_TREE_W19_in4[16]; -assign pyc_extract_613 = PE_INT_WALLACE_DOT8_TREE_W19_in5[16]; -assign pyc_extract_614 = PE_INT_WALLACE_DOT8_TREE_W19_in6[16]; -assign pyc_xor_615 = (pyc_extract_612 ^ pyc_extract_613); -assign pyc_xor_616 = (pyc_xor_615 ^ pyc_extract_614); -assign pyc_and_617 = (pyc_extract_612 & pyc_extract_613); -assign pyc_and_618 = (pyc_extract_612 & pyc_extract_614); -assign pyc_or_619 = (pyc_and_617 | pyc_and_618); -assign pyc_and_620 = (pyc_extract_613 & pyc_extract_614); -assign pyc_or_621 = (pyc_or_619 | pyc_and_620); -assign pyc_extract_622 = PE_INT_WALLACE_DOT8_TREE_W19_in7[16]; -assign pyc_xor_623 = (pyc_xor_616 ^ pyc_extract_622); -assign pyc_xor_624 = (pyc_xor_623 ^ pyc_or_603); -assign pyc_and_625 = (pyc_xor_616 & pyc_extract_622); -assign pyc_and_626 = (pyc_xor_616 & pyc_or_603); -assign pyc_or_627 = (pyc_and_625 | pyc_and_626); -assign pyc_and_628 = (pyc_extract_622 & pyc_or_603); -assign pyc_or_629 = (pyc_or_627 | pyc_and_628); -assign pyc_extract_630 = PE_INT_WALLACE_DOT8_TREE_W19_in4[17]; -assign pyc_extract_631 = PE_INT_WALLACE_DOT8_TREE_W19_in5[17]; -assign pyc_extract_632 = PE_INT_WALLACE_DOT8_TREE_W19_in6[17]; -assign pyc_xor_633 = (pyc_extract_630 ^ pyc_extract_631); -assign pyc_xor_634 = (pyc_xor_633 ^ pyc_extract_632); -assign pyc_and_635 = (pyc_extract_630 & pyc_extract_631); -assign pyc_and_636 = (pyc_extract_630 & pyc_extract_632); -assign pyc_or_637 = (pyc_and_635 | pyc_and_636); -assign pyc_and_638 = (pyc_extract_631 & pyc_extract_632); -assign pyc_or_639 = (pyc_or_637 | pyc_and_638); -assign pyc_extract_640 = PE_INT_WALLACE_DOT8_TREE_W19_in7[17]; -assign pyc_xor_641 = (pyc_xor_634 ^ pyc_extract_640); -assign pyc_xor_642 = (pyc_xor_641 ^ pyc_or_621); -assign pyc_and_643 = (pyc_xor_634 & pyc_extract_640); -assign pyc_and_644 = (pyc_xor_634 & pyc_or_621); -assign pyc_or_645 = (pyc_and_643 | pyc_and_644); -assign pyc_and_646 = (pyc_extract_640 & pyc_or_621); -assign pyc_or_647 = (pyc_or_645 | pyc_and_646); -assign pyc_extract_648 = PE_INT_WALLACE_DOT8_TREE_W19_in4[18]; -assign pyc_extract_649 = PE_INT_WALLACE_DOT8_TREE_W19_in5[18]; -assign pyc_extract_650 = PE_INT_WALLACE_DOT8_TREE_W19_in6[18]; -assign pyc_xor_651 = (pyc_extract_648 ^ pyc_extract_649); -assign pyc_xor_652 = (pyc_xor_651 ^ pyc_extract_650); -assign pyc_extract_653 = PE_INT_WALLACE_DOT8_TREE_W19_in7[18]; -assign pyc_xor_654 = (pyc_xor_652 ^ pyc_extract_653); -assign pyc_xor_655 = (pyc_xor_654 ^ pyc_or_639); -assign pyc_xor_656 = (pyc_xor_13 ^ pyc_xor_340); -assign pyc_and_657 = (pyc_xor_13 & pyc_xor_340); -assign pyc_xor_658 = (pyc_xor_27 ^ pyc_and_14); -assign pyc_xor_659 = (pyc_xor_658 ^ pyc_xor_354); -assign pyc_and_660 = (pyc_xor_27 & pyc_and_14); -assign pyc_and_661 = (pyc_xor_27 & pyc_xor_354); -assign pyc_or_662 = (pyc_and_660 | pyc_and_661); -assign pyc_and_663 = (pyc_and_14 & pyc_xor_354); -assign pyc_or_664 = (pyc_or_662 | pyc_and_663); -assign pyc_xor_665 = (pyc_xor_659 ^ pyc_and_341); -assign pyc_xor_666 = (pyc_xor_665 ^ pyc_and_657); -assign pyc_and_667 = (pyc_xor_659 & pyc_and_341); -assign pyc_and_668 = (pyc_xor_659 & pyc_and_657); -assign pyc_or_669 = (pyc_and_667 | pyc_and_668); -assign pyc_and_670 = (pyc_and_341 & pyc_and_657); -assign pyc_or_671 = (pyc_or_669 | pyc_and_670); -assign pyc_xor_672 = (pyc_xor_45 ^ pyc_or_32); -assign pyc_xor_673 = (pyc_xor_672 ^ pyc_xor_372); -assign pyc_and_674 = (pyc_xor_45 & pyc_or_32); -assign pyc_and_675 = (pyc_xor_45 & pyc_xor_372); -assign pyc_or_676 = (pyc_and_674 | pyc_and_675); -assign pyc_and_677 = (pyc_or_32 & pyc_xor_372); -assign pyc_or_678 = (pyc_or_676 | pyc_and_677); -assign pyc_xor_679 = (pyc_xor_673 ^ pyc_or_359); -assign pyc_xor_680 = (pyc_xor_679 ^ pyc_or_664); -assign pyc_and_681 = (pyc_xor_673 & pyc_or_359); -assign pyc_and_682 = (pyc_xor_673 & pyc_or_664); -assign pyc_or_683 = (pyc_and_681 | pyc_and_682); -assign pyc_and_684 = (pyc_or_359 & pyc_or_664); -assign pyc_or_685 = (pyc_or_683 | pyc_and_684); -assign pyc_xor_686 = (pyc_xor_63 ^ pyc_or_50); -assign pyc_xor_687 = (pyc_xor_686 ^ pyc_xor_390); -assign pyc_and_688 = (pyc_xor_63 & pyc_or_50); -assign pyc_and_689 = (pyc_xor_63 & pyc_xor_390); -assign pyc_or_690 = (pyc_and_688 | pyc_and_689); -assign pyc_and_691 = (pyc_or_50 & pyc_xor_390); -assign pyc_or_692 = (pyc_or_690 | pyc_and_691); -assign pyc_xor_693 = (pyc_xor_687 ^ pyc_or_377); -assign pyc_xor_694 = (pyc_xor_693 ^ pyc_or_678); -assign pyc_and_695 = (pyc_xor_687 & pyc_or_377); -assign pyc_and_696 = (pyc_xor_687 & pyc_or_678); -assign pyc_or_697 = (pyc_and_695 | pyc_and_696); -assign pyc_and_698 = (pyc_or_377 & pyc_or_678); -assign pyc_or_699 = (pyc_or_697 | pyc_and_698); -assign pyc_xor_700 = (pyc_xor_81 ^ pyc_or_68); -assign pyc_xor_701 = (pyc_xor_700 ^ pyc_xor_408); -assign pyc_and_702 = (pyc_xor_81 & pyc_or_68); -assign pyc_and_703 = (pyc_xor_81 & pyc_xor_408); -assign pyc_or_704 = (pyc_and_702 | pyc_and_703); -assign pyc_and_705 = (pyc_or_68 & pyc_xor_408); -assign pyc_or_706 = (pyc_or_704 | pyc_and_705); -assign pyc_xor_707 = (pyc_xor_701 ^ pyc_or_395); -assign pyc_xor_708 = (pyc_xor_707 ^ pyc_or_692); -assign pyc_and_709 = (pyc_xor_701 & pyc_or_395); -assign pyc_and_710 = (pyc_xor_701 & pyc_or_692); -assign pyc_or_711 = (pyc_and_709 | pyc_and_710); -assign pyc_and_712 = (pyc_or_395 & pyc_or_692); -assign pyc_or_713 = (pyc_or_711 | pyc_and_712); -assign pyc_xor_714 = (pyc_xor_99 ^ pyc_or_86); -assign pyc_xor_715 = (pyc_xor_714 ^ pyc_xor_426); -assign pyc_and_716 = (pyc_xor_99 & pyc_or_86); -assign pyc_and_717 = (pyc_xor_99 & pyc_xor_426); -assign pyc_or_718 = (pyc_and_716 | pyc_and_717); -assign pyc_and_719 = (pyc_or_86 & pyc_xor_426); -assign pyc_or_720 = (pyc_or_718 | pyc_and_719); -assign pyc_xor_721 = (pyc_xor_715 ^ pyc_or_413); -assign pyc_xor_722 = (pyc_xor_721 ^ pyc_or_706); -assign pyc_and_723 = (pyc_xor_715 & pyc_or_413); -assign pyc_and_724 = (pyc_xor_715 & pyc_or_706); -assign pyc_or_725 = (pyc_and_723 | pyc_and_724); -assign pyc_and_726 = (pyc_or_413 & pyc_or_706); -assign pyc_or_727 = (pyc_or_725 | pyc_and_726); -assign pyc_xor_728 = (pyc_xor_117 ^ pyc_or_104); -assign pyc_xor_729 = (pyc_xor_728 ^ pyc_xor_444); -assign pyc_and_730 = (pyc_xor_117 & pyc_or_104); -assign pyc_and_731 = (pyc_xor_117 & pyc_xor_444); -assign pyc_or_732 = (pyc_and_730 | pyc_and_731); -assign pyc_and_733 = (pyc_or_104 & pyc_xor_444); -assign pyc_or_734 = (pyc_or_732 | pyc_and_733); -assign pyc_xor_735 = (pyc_xor_729 ^ pyc_or_431); -assign pyc_xor_736 = (pyc_xor_735 ^ pyc_or_720); -assign pyc_and_737 = (pyc_xor_729 & pyc_or_431); -assign pyc_and_738 = (pyc_xor_729 & pyc_or_720); -assign pyc_or_739 = (pyc_and_737 | pyc_and_738); -assign pyc_and_740 = (pyc_or_431 & pyc_or_720); -assign pyc_or_741 = (pyc_or_739 | pyc_and_740); -assign pyc_xor_742 = (pyc_xor_135 ^ pyc_or_122); -assign pyc_xor_743 = (pyc_xor_742 ^ pyc_xor_462); -assign pyc_and_744 = (pyc_xor_135 & pyc_or_122); -assign pyc_and_745 = (pyc_xor_135 & pyc_xor_462); -assign pyc_or_746 = (pyc_and_744 | pyc_and_745); -assign pyc_and_747 = (pyc_or_122 & pyc_xor_462); -assign pyc_or_748 = (pyc_or_746 | pyc_and_747); -assign pyc_xor_749 = (pyc_xor_743 ^ pyc_or_449); -assign pyc_xor_750 = (pyc_xor_749 ^ pyc_or_734); -assign pyc_and_751 = (pyc_xor_743 & pyc_or_449); -assign pyc_and_752 = (pyc_xor_743 & pyc_or_734); -assign pyc_or_753 = (pyc_and_751 | pyc_and_752); -assign pyc_and_754 = (pyc_or_449 & pyc_or_734); -assign pyc_or_755 = (pyc_or_753 | pyc_and_754); -assign pyc_xor_756 = (pyc_xor_153 ^ pyc_or_140); -assign pyc_xor_757 = (pyc_xor_756 ^ pyc_xor_480); -assign pyc_and_758 = (pyc_xor_153 & pyc_or_140); -assign pyc_and_759 = (pyc_xor_153 & pyc_xor_480); -assign pyc_or_760 = (pyc_and_758 | pyc_and_759); -assign pyc_and_761 = (pyc_or_140 & pyc_xor_480); -assign pyc_or_762 = (pyc_or_760 | pyc_and_761); -assign pyc_xor_763 = (pyc_xor_757 ^ pyc_or_467); -assign pyc_xor_764 = (pyc_xor_763 ^ pyc_or_748); -assign pyc_and_765 = (pyc_xor_757 & pyc_or_467); -assign pyc_and_766 = (pyc_xor_757 & pyc_or_748); -assign pyc_or_767 = (pyc_and_765 | pyc_and_766); -assign pyc_and_768 = (pyc_or_467 & pyc_or_748); -assign pyc_or_769 = (pyc_or_767 | pyc_and_768); -assign pyc_xor_770 = (pyc_xor_171 ^ pyc_or_158); -assign pyc_xor_771 = (pyc_xor_770 ^ pyc_xor_498); -assign pyc_and_772 = (pyc_xor_171 & pyc_or_158); -assign pyc_and_773 = (pyc_xor_171 & pyc_xor_498); -assign pyc_or_774 = (pyc_and_772 | pyc_and_773); -assign pyc_and_775 = (pyc_or_158 & pyc_xor_498); -assign pyc_or_776 = (pyc_or_774 | pyc_and_775); -assign pyc_xor_777 = (pyc_xor_771 ^ pyc_or_485); -assign pyc_xor_778 = (pyc_xor_777 ^ pyc_or_762); -assign pyc_and_779 = (pyc_xor_771 & pyc_or_485); -assign pyc_and_780 = (pyc_xor_771 & pyc_or_762); -assign pyc_or_781 = (pyc_and_779 | pyc_and_780); -assign pyc_and_782 = (pyc_or_485 & pyc_or_762); -assign pyc_or_783 = (pyc_or_781 | pyc_and_782); -assign pyc_xor_784 = (pyc_xor_189 ^ pyc_or_176); -assign pyc_xor_785 = (pyc_xor_784 ^ pyc_xor_516); -assign pyc_and_786 = (pyc_xor_189 & pyc_or_176); -assign pyc_and_787 = (pyc_xor_189 & pyc_xor_516); -assign pyc_or_788 = (pyc_and_786 | pyc_and_787); -assign pyc_and_789 = (pyc_or_176 & pyc_xor_516); -assign pyc_or_790 = (pyc_or_788 | pyc_and_789); -assign pyc_xor_791 = (pyc_xor_785 ^ pyc_or_503); -assign pyc_xor_792 = (pyc_xor_791 ^ pyc_or_776); -assign pyc_and_793 = (pyc_xor_785 & pyc_or_503); -assign pyc_and_794 = (pyc_xor_785 & pyc_or_776); -assign pyc_or_795 = (pyc_and_793 | pyc_and_794); -assign pyc_and_796 = (pyc_or_503 & pyc_or_776); -assign pyc_or_797 = (pyc_or_795 | pyc_and_796); -assign pyc_xor_798 = (pyc_xor_207 ^ pyc_or_194); -assign pyc_xor_799 = (pyc_xor_798 ^ pyc_xor_534); -assign pyc_and_800 = (pyc_xor_207 & pyc_or_194); -assign pyc_and_801 = (pyc_xor_207 & pyc_xor_534); -assign pyc_or_802 = (pyc_and_800 | pyc_and_801); -assign pyc_and_803 = (pyc_or_194 & pyc_xor_534); -assign pyc_or_804 = (pyc_or_802 | pyc_and_803); -assign pyc_xor_805 = (pyc_xor_799 ^ pyc_or_521); -assign pyc_xor_806 = (pyc_xor_805 ^ pyc_or_790); -assign pyc_and_807 = (pyc_xor_799 & pyc_or_521); -assign pyc_and_808 = (pyc_xor_799 & pyc_or_790); -assign pyc_or_809 = (pyc_and_807 | pyc_and_808); -assign pyc_and_810 = (pyc_or_521 & pyc_or_790); -assign pyc_or_811 = (pyc_or_809 | pyc_and_810); -assign pyc_xor_812 = (pyc_xor_225 ^ pyc_or_212); -assign pyc_xor_813 = (pyc_xor_812 ^ pyc_xor_552); -assign pyc_and_814 = (pyc_xor_225 & pyc_or_212); -assign pyc_and_815 = (pyc_xor_225 & pyc_xor_552); -assign pyc_or_816 = (pyc_and_814 | pyc_and_815); -assign pyc_and_817 = (pyc_or_212 & pyc_xor_552); -assign pyc_or_818 = (pyc_or_816 | pyc_and_817); -assign pyc_xor_819 = (pyc_xor_813 ^ pyc_or_539); -assign pyc_xor_820 = (pyc_xor_819 ^ pyc_or_804); -assign pyc_and_821 = (pyc_xor_813 & pyc_or_539); -assign pyc_and_822 = (pyc_xor_813 & pyc_or_804); -assign pyc_or_823 = (pyc_and_821 | pyc_and_822); -assign pyc_and_824 = (pyc_or_539 & pyc_or_804); -assign pyc_or_825 = (pyc_or_823 | pyc_and_824); -assign pyc_xor_826 = (pyc_xor_243 ^ pyc_or_230); -assign pyc_xor_827 = (pyc_xor_826 ^ pyc_xor_570); -assign pyc_and_828 = (pyc_xor_243 & pyc_or_230); -assign pyc_and_829 = (pyc_xor_243 & pyc_xor_570); -assign pyc_or_830 = (pyc_and_828 | pyc_and_829); -assign pyc_and_831 = (pyc_or_230 & pyc_xor_570); -assign pyc_or_832 = (pyc_or_830 | pyc_and_831); -assign pyc_xor_833 = (pyc_xor_827 ^ pyc_or_557); -assign pyc_xor_834 = (pyc_xor_833 ^ pyc_or_818); -assign pyc_and_835 = (pyc_xor_827 & pyc_or_557); -assign pyc_and_836 = (pyc_xor_827 & pyc_or_818); -assign pyc_or_837 = (pyc_and_835 | pyc_and_836); -assign pyc_and_838 = (pyc_or_557 & pyc_or_818); -assign pyc_or_839 = (pyc_or_837 | pyc_and_838); -assign pyc_xor_840 = (pyc_xor_261 ^ pyc_or_248); -assign pyc_xor_841 = (pyc_xor_840 ^ pyc_xor_588); -assign pyc_and_842 = (pyc_xor_261 & pyc_or_248); -assign pyc_and_843 = (pyc_xor_261 & pyc_xor_588); -assign pyc_or_844 = (pyc_and_842 | pyc_and_843); -assign pyc_and_845 = (pyc_or_248 & pyc_xor_588); -assign pyc_or_846 = (pyc_or_844 | pyc_and_845); -assign pyc_xor_847 = (pyc_xor_841 ^ pyc_or_575); -assign pyc_xor_848 = (pyc_xor_847 ^ pyc_or_832); -assign pyc_and_849 = (pyc_xor_841 & pyc_or_575); -assign pyc_and_850 = (pyc_xor_841 & pyc_or_832); -assign pyc_or_851 = (pyc_and_849 | pyc_and_850); -assign pyc_and_852 = (pyc_or_575 & pyc_or_832); -assign pyc_or_853 = (pyc_or_851 | pyc_and_852); -assign pyc_xor_854 = (pyc_xor_279 ^ pyc_or_266); -assign pyc_xor_855 = (pyc_xor_854 ^ pyc_xor_606); -assign pyc_and_856 = (pyc_xor_279 & pyc_or_266); -assign pyc_and_857 = (pyc_xor_279 & pyc_xor_606); -assign pyc_or_858 = (pyc_and_856 | pyc_and_857); -assign pyc_and_859 = (pyc_or_266 & pyc_xor_606); -assign pyc_or_860 = (pyc_or_858 | pyc_and_859); -assign pyc_xor_861 = (pyc_xor_855 ^ pyc_or_593); -assign pyc_xor_862 = (pyc_xor_861 ^ pyc_or_846); -assign pyc_and_863 = (pyc_xor_855 & pyc_or_593); -assign pyc_and_864 = (pyc_xor_855 & pyc_or_846); -assign pyc_or_865 = (pyc_and_863 | pyc_and_864); -assign pyc_and_866 = (pyc_or_593 & pyc_or_846); -assign pyc_or_867 = (pyc_or_865 | pyc_and_866); -assign pyc_xor_868 = (pyc_xor_297 ^ pyc_or_284); -assign pyc_xor_869 = (pyc_xor_868 ^ pyc_xor_624); -assign pyc_and_870 = (pyc_xor_297 & pyc_or_284); -assign pyc_and_871 = (pyc_xor_297 & pyc_xor_624); -assign pyc_or_872 = (pyc_and_870 | pyc_and_871); -assign pyc_and_873 = (pyc_or_284 & pyc_xor_624); -assign pyc_or_874 = (pyc_or_872 | pyc_and_873); -assign pyc_xor_875 = (pyc_xor_869 ^ pyc_or_611); -assign pyc_xor_876 = (pyc_xor_875 ^ pyc_or_860); -assign pyc_and_877 = (pyc_xor_869 & pyc_or_611); -assign pyc_and_878 = (pyc_xor_869 & pyc_or_860); -assign pyc_or_879 = (pyc_and_877 | pyc_and_878); -assign pyc_and_880 = (pyc_or_611 & pyc_or_860); -assign pyc_or_881 = (pyc_or_879 | pyc_and_880); -assign pyc_xor_882 = (pyc_xor_315 ^ pyc_or_302); -assign pyc_xor_883 = (pyc_xor_882 ^ pyc_xor_642); -assign pyc_and_884 = (pyc_xor_315 & pyc_or_302); -assign pyc_and_885 = (pyc_xor_315 & pyc_xor_642); -assign pyc_or_886 = (pyc_and_884 | pyc_and_885); -assign pyc_and_887 = (pyc_or_302 & pyc_xor_642); -assign pyc_or_888 = (pyc_or_886 | pyc_and_887); -assign pyc_xor_889 = (pyc_xor_883 ^ pyc_or_629); -assign pyc_xor_890 = (pyc_xor_889 ^ pyc_or_874); -assign pyc_and_891 = (pyc_xor_883 & pyc_or_629); -assign pyc_and_892 = (pyc_xor_883 & pyc_or_874); -assign pyc_or_893 = (pyc_and_891 | pyc_and_892); -assign pyc_and_894 = (pyc_or_629 & pyc_or_874); -assign pyc_or_895 = (pyc_or_893 | pyc_and_894); -assign pyc_xor_896 = (pyc_xor_328 ^ pyc_or_320); -assign pyc_xor_897 = (pyc_xor_896 ^ pyc_xor_655); -assign pyc_xor_898 = (pyc_xor_897 ^ pyc_or_647); -assign pyc_xor_899 = (pyc_xor_898 ^ pyc_or_888); -assign pyc_concat_900 = {pyc_xor_899, pyc_xor_890, pyc_xor_876, pyc_xor_862, pyc_xor_848, pyc_xor_834, pyc_xor_820, pyc_xor_806, pyc_xor_792, pyc_xor_778, pyc_xor_764, pyc_xor_750, pyc_xor_736, pyc_xor_722, pyc_xor_708, pyc_xor_694, pyc_xor_680, pyc_xor_666, pyc_xor_656}; -assign pyc_concat_901 = {pyc_or_895, pyc_or_881, pyc_or_867, pyc_or_853, pyc_or_839, pyc_or_825, pyc_or_811, pyc_or_797, pyc_or_783, pyc_or_769, pyc_or_755, pyc_or_741, pyc_or_727, pyc_or_713, pyc_or_699, pyc_or_685, pyc_or_671, pyc_constant_1, pyc_constant_1}; -assign pyc_add_902 = (pyc_concat_900 + pyc_concat_901); -assign pyc_comb_903 = pyc_add_902; +assign pyc_extract_1 = PE_INT_WALLACE_DOT8_TREE_W19_in0[0]; +assign pyc_extract_2 = PE_INT_WALLACE_DOT8_TREE_W19_in1[0]; +assign pyc_extract_3 = PE_INT_WALLACE_DOT8_TREE_W19_in2[0]; +assign pyc_xor_4 = (pyc_extract_1 ^ pyc_extract_2); +assign pyc_xor_5 = (pyc_xor_4 ^ pyc_extract_3); +assign pyc_and_6 = (pyc_extract_1 & pyc_extract_2); +assign pyc_and_7 = (pyc_extract_1 & pyc_extract_3); +assign pyc_or_8 = (pyc_and_6 | pyc_and_7); +assign pyc_and_9 = (pyc_extract_2 & pyc_extract_3); +assign pyc_or_10 = (pyc_or_8 | pyc_and_9); +assign pyc_extract_11 = PE_INT_WALLACE_DOT8_TREE_W19_in3[0]; +assign pyc_xor_12 = (pyc_xor_5 ^ pyc_extract_11); +assign pyc_and_13 = (pyc_xor_5 & pyc_extract_11); +assign pyc_extract_14 = PE_INT_WALLACE_DOT8_TREE_W19_in0[1]; +assign pyc_extract_15 = PE_INT_WALLACE_DOT8_TREE_W19_in1[1]; +assign pyc_extract_16 = PE_INT_WALLACE_DOT8_TREE_W19_in2[1]; +assign pyc_xor_17 = (pyc_extract_14 ^ pyc_extract_15); +assign pyc_xor_18 = (pyc_xor_17 ^ pyc_extract_16); +assign pyc_and_19 = (pyc_extract_14 & pyc_extract_15); +assign pyc_and_20 = (pyc_extract_14 & pyc_extract_16); +assign pyc_or_21 = (pyc_and_19 | pyc_and_20); +assign pyc_and_22 = (pyc_extract_15 & pyc_extract_16); +assign pyc_or_23 = (pyc_or_21 | pyc_and_22); +assign pyc_extract_24 = PE_INT_WALLACE_DOT8_TREE_W19_in3[1]; +assign pyc_xor_25 = (pyc_xor_18 ^ pyc_extract_24); +assign pyc_xor_26 = (pyc_xor_25 ^ pyc_or_10); +assign pyc_and_27 = (pyc_xor_18 & pyc_extract_24); +assign pyc_and_28 = (pyc_xor_18 & pyc_or_10); +assign pyc_or_29 = (pyc_and_27 | pyc_and_28); +assign pyc_and_30 = (pyc_extract_24 & pyc_or_10); +assign pyc_or_31 = (pyc_or_29 | pyc_and_30); +assign pyc_extract_32 = PE_INT_WALLACE_DOT8_TREE_W19_in0[2]; +assign pyc_extract_33 = PE_INT_WALLACE_DOT8_TREE_W19_in1[2]; +assign pyc_extract_34 = PE_INT_WALLACE_DOT8_TREE_W19_in2[2]; +assign pyc_xor_35 = (pyc_extract_32 ^ pyc_extract_33); +assign pyc_xor_36 = (pyc_xor_35 ^ pyc_extract_34); +assign pyc_and_37 = (pyc_extract_32 & pyc_extract_33); +assign pyc_and_38 = (pyc_extract_32 & pyc_extract_34); +assign pyc_or_39 = (pyc_and_37 | pyc_and_38); +assign pyc_and_40 = (pyc_extract_33 & pyc_extract_34); +assign pyc_or_41 = (pyc_or_39 | pyc_and_40); +assign pyc_extract_42 = PE_INT_WALLACE_DOT8_TREE_W19_in3[2]; +assign pyc_xor_43 = (pyc_xor_36 ^ pyc_extract_42); +assign pyc_xor_44 = (pyc_xor_43 ^ pyc_or_23); +assign pyc_and_45 = (pyc_xor_36 & pyc_extract_42); +assign pyc_and_46 = (pyc_xor_36 & pyc_or_23); +assign pyc_or_47 = (pyc_and_45 | pyc_and_46); +assign pyc_and_48 = (pyc_extract_42 & pyc_or_23); +assign pyc_or_49 = (pyc_or_47 | pyc_and_48); +assign pyc_extract_50 = PE_INT_WALLACE_DOT8_TREE_W19_in0[3]; +assign pyc_extract_51 = PE_INT_WALLACE_DOT8_TREE_W19_in1[3]; +assign pyc_extract_52 = PE_INT_WALLACE_DOT8_TREE_W19_in2[3]; +assign pyc_xor_53 = (pyc_extract_50 ^ pyc_extract_51); +assign pyc_xor_54 = (pyc_xor_53 ^ pyc_extract_52); +assign pyc_and_55 = (pyc_extract_50 & pyc_extract_51); +assign pyc_and_56 = (pyc_extract_50 & pyc_extract_52); +assign pyc_or_57 = (pyc_and_55 | pyc_and_56); +assign pyc_and_58 = (pyc_extract_51 & pyc_extract_52); +assign pyc_or_59 = (pyc_or_57 | pyc_and_58); +assign pyc_extract_60 = PE_INT_WALLACE_DOT8_TREE_W19_in3[3]; +assign pyc_xor_61 = (pyc_xor_54 ^ pyc_extract_60); +assign pyc_xor_62 = (pyc_xor_61 ^ pyc_or_41); +assign pyc_and_63 = (pyc_xor_54 & pyc_extract_60); +assign pyc_and_64 = (pyc_xor_54 & pyc_or_41); +assign pyc_or_65 = (pyc_and_63 | pyc_and_64); +assign pyc_and_66 = (pyc_extract_60 & pyc_or_41); +assign pyc_or_67 = (pyc_or_65 | pyc_and_66); +assign pyc_extract_68 = PE_INT_WALLACE_DOT8_TREE_W19_in0[4]; +assign pyc_extract_69 = PE_INT_WALLACE_DOT8_TREE_W19_in1[4]; +assign pyc_extract_70 = PE_INT_WALLACE_DOT8_TREE_W19_in2[4]; +assign pyc_xor_71 = (pyc_extract_68 ^ pyc_extract_69); +assign pyc_xor_72 = (pyc_xor_71 ^ pyc_extract_70); +assign pyc_and_73 = (pyc_extract_68 & pyc_extract_69); +assign pyc_and_74 = (pyc_extract_68 & pyc_extract_70); +assign pyc_or_75 = (pyc_and_73 | pyc_and_74); +assign pyc_and_76 = (pyc_extract_69 & pyc_extract_70); +assign pyc_or_77 = (pyc_or_75 | pyc_and_76); +assign pyc_extract_78 = PE_INT_WALLACE_DOT8_TREE_W19_in3[4]; +assign pyc_xor_79 = (pyc_xor_72 ^ pyc_extract_78); +assign pyc_xor_80 = (pyc_xor_79 ^ pyc_or_59); +assign pyc_and_81 = (pyc_xor_72 & pyc_extract_78); +assign pyc_and_82 = (pyc_xor_72 & pyc_or_59); +assign pyc_or_83 = (pyc_and_81 | pyc_and_82); +assign pyc_and_84 = (pyc_extract_78 & pyc_or_59); +assign pyc_or_85 = (pyc_or_83 | pyc_and_84); +assign pyc_extract_86 = PE_INT_WALLACE_DOT8_TREE_W19_in0[5]; +assign pyc_extract_87 = PE_INT_WALLACE_DOT8_TREE_W19_in1[5]; +assign pyc_extract_88 = PE_INT_WALLACE_DOT8_TREE_W19_in2[5]; +assign pyc_xor_89 = (pyc_extract_86 ^ pyc_extract_87); +assign pyc_xor_90 = (pyc_xor_89 ^ pyc_extract_88); +assign pyc_and_91 = (pyc_extract_86 & pyc_extract_87); +assign pyc_and_92 = (pyc_extract_86 & pyc_extract_88); +assign pyc_or_93 = (pyc_and_91 | pyc_and_92); +assign pyc_and_94 = (pyc_extract_87 & pyc_extract_88); +assign pyc_or_95 = (pyc_or_93 | pyc_and_94); +assign pyc_extract_96 = PE_INT_WALLACE_DOT8_TREE_W19_in3[5]; +assign pyc_xor_97 = (pyc_xor_90 ^ pyc_extract_96); +assign pyc_xor_98 = (pyc_xor_97 ^ pyc_or_77); +assign pyc_and_99 = (pyc_xor_90 & pyc_extract_96); +assign pyc_and_100 = (pyc_xor_90 & pyc_or_77); +assign pyc_or_101 = (pyc_and_99 | pyc_and_100); +assign pyc_and_102 = (pyc_extract_96 & pyc_or_77); +assign pyc_or_103 = (pyc_or_101 | pyc_and_102); +assign pyc_extract_104 = PE_INT_WALLACE_DOT8_TREE_W19_in0[6]; +assign pyc_extract_105 = PE_INT_WALLACE_DOT8_TREE_W19_in1[6]; +assign pyc_extract_106 = PE_INT_WALLACE_DOT8_TREE_W19_in2[6]; +assign pyc_xor_107 = (pyc_extract_104 ^ pyc_extract_105); +assign pyc_xor_108 = (pyc_xor_107 ^ pyc_extract_106); +assign pyc_and_109 = (pyc_extract_104 & pyc_extract_105); +assign pyc_and_110 = (pyc_extract_104 & pyc_extract_106); +assign pyc_or_111 = (pyc_and_109 | pyc_and_110); +assign pyc_and_112 = (pyc_extract_105 & pyc_extract_106); +assign pyc_or_113 = (pyc_or_111 | pyc_and_112); +assign pyc_extract_114 = PE_INT_WALLACE_DOT8_TREE_W19_in3[6]; +assign pyc_xor_115 = (pyc_xor_108 ^ pyc_extract_114); +assign pyc_xor_116 = (pyc_xor_115 ^ pyc_or_95); +assign pyc_and_117 = (pyc_xor_108 & pyc_extract_114); +assign pyc_and_118 = (pyc_xor_108 & pyc_or_95); +assign pyc_or_119 = (pyc_and_117 | pyc_and_118); +assign pyc_and_120 = (pyc_extract_114 & pyc_or_95); +assign pyc_or_121 = (pyc_or_119 | pyc_and_120); +assign pyc_extract_122 = PE_INT_WALLACE_DOT8_TREE_W19_in0[7]; +assign pyc_extract_123 = PE_INT_WALLACE_DOT8_TREE_W19_in1[7]; +assign pyc_extract_124 = PE_INT_WALLACE_DOT8_TREE_W19_in2[7]; +assign pyc_xor_125 = (pyc_extract_122 ^ pyc_extract_123); +assign pyc_xor_126 = (pyc_xor_125 ^ pyc_extract_124); +assign pyc_and_127 = (pyc_extract_122 & pyc_extract_123); +assign pyc_and_128 = (pyc_extract_122 & pyc_extract_124); +assign pyc_or_129 = (pyc_and_127 | pyc_and_128); +assign pyc_and_130 = (pyc_extract_123 & pyc_extract_124); +assign pyc_or_131 = (pyc_or_129 | pyc_and_130); +assign pyc_extract_132 = PE_INT_WALLACE_DOT8_TREE_W19_in3[7]; +assign pyc_xor_133 = (pyc_xor_126 ^ pyc_extract_132); +assign pyc_xor_134 = (pyc_xor_133 ^ pyc_or_113); +assign pyc_and_135 = (pyc_xor_126 & pyc_extract_132); +assign pyc_and_136 = (pyc_xor_126 & pyc_or_113); +assign pyc_or_137 = (pyc_and_135 | pyc_and_136); +assign pyc_and_138 = (pyc_extract_132 & pyc_or_113); +assign pyc_or_139 = (pyc_or_137 | pyc_and_138); +assign pyc_extract_140 = PE_INT_WALLACE_DOT8_TREE_W19_in0[8]; +assign pyc_extract_141 = PE_INT_WALLACE_DOT8_TREE_W19_in1[8]; +assign pyc_extract_142 = PE_INT_WALLACE_DOT8_TREE_W19_in2[8]; +assign pyc_xor_143 = (pyc_extract_140 ^ pyc_extract_141); +assign pyc_xor_144 = (pyc_xor_143 ^ pyc_extract_142); +assign pyc_and_145 = (pyc_extract_140 & pyc_extract_141); +assign pyc_and_146 = (pyc_extract_140 & pyc_extract_142); +assign pyc_or_147 = (pyc_and_145 | pyc_and_146); +assign pyc_and_148 = (pyc_extract_141 & pyc_extract_142); +assign pyc_or_149 = (pyc_or_147 | pyc_and_148); +assign pyc_extract_150 = PE_INT_WALLACE_DOT8_TREE_W19_in3[8]; +assign pyc_xor_151 = (pyc_xor_144 ^ pyc_extract_150); +assign pyc_xor_152 = (pyc_xor_151 ^ pyc_or_131); +assign pyc_and_153 = (pyc_xor_144 & pyc_extract_150); +assign pyc_and_154 = (pyc_xor_144 & pyc_or_131); +assign pyc_or_155 = (pyc_and_153 | pyc_and_154); +assign pyc_and_156 = (pyc_extract_150 & pyc_or_131); +assign pyc_or_157 = (pyc_or_155 | pyc_and_156); +assign pyc_extract_158 = PE_INT_WALLACE_DOT8_TREE_W19_in0[9]; +assign pyc_extract_159 = PE_INT_WALLACE_DOT8_TREE_W19_in1[9]; +assign pyc_extract_160 = PE_INT_WALLACE_DOT8_TREE_W19_in2[9]; +assign pyc_xor_161 = (pyc_extract_158 ^ pyc_extract_159); +assign pyc_xor_162 = (pyc_xor_161 ^ pyc_extract_160); +assign pyc_and_163 = (pyc_extract_158 & pyc_extract_159); +assign pyc_and_164 = (pyc_extract_158 & pyc_extract_160); +assign pyc_or_165 = (pyc_and_163 | pyc_and_164); +assign pyc_and_166 = (pyc_extract_159 & pyc_extract_160); +assign pyc_or_167 = (pyc_or_165 | pyc_and_166); +assign pyc_extract_168 = PE_INT_WALLACE_DOT8_TREE_W19_in3[9]; +assign pyc_xor_169 = (pyc_xor_162 ^ pyc_extract_168); +assign pyc_xor_170 = (pyc_xor_169 ^ pyc_or_149); +assign pyc_and_171 = (pyc_xor_162 & pyc_extract_168); +assign pyc_and_172 = (pyc_xor_162 & pyc_or_149); +assign pyc_or_173 = (pyc_and_171 | pyc_and_172); +assign pyc_and_174 = (pyc_extract_168 & pyc_or_149); +assign pyc_or_175 = (pyc_or_173 | pyc_and_174); +assign pyc_extract_176 = PE_INT_WALLACE_DOT8_TREE_W19_in0[10]; +assign pyc_extract_177 = PE_INT_WALLACE_DOT8_TREE_W19_in1[10]; +assign pyc_extract_178 = PE_INT_WALLACE_DOT8_TREE_W19_in2[10]; +assign pyc_xor_179 = (pyc_extract_176 ^ pyc_extract_177); +assign pyc_xor_180 = (pyc_xor_179 ^ pyc_extract_178); +assign pyc_and_181 = (pyc_extract_176 & pyc_extract_177); +assign pyc_and_182 = (pyc_extract_176 & pyc_extract_178); +assign pyc_or_183 = (pyc_and_181 | pyc_and_182); +assign pyc_and_184 = (pyc_extract_177 & pyc_extract_178); +assign pyc_or_185 = (pyc_or_183 | pyc_and_184); +assign pyc_extract_186 = PE_INT_WALLACE_DOT8_TREE_W19_in3[10]; +assign pyc_xor_187 = (pyc_xor_180 ^ pyc_extract_186); +assign pyc_xor_188 = (pyc_xor_187 ^ pyc_or_167); +assign pyc_and_189 = (pyc_xor_180 & pyc_extract_186); +assign pyc_and_190 = (pyc_xor_180 & pyc_or_167); +assign pyc_or_191 = (pyc_and_189 | pyc_and_190); +assign pyc_and_192 = (pyc_extract_186 & pyc_or_167); +assign pyc_or_193 = (pyc_or_191 | pyc_and_192); +assign pyc_extract_194 = PE_INT_WALLACE_DOT8_TREE_W19_in0[11]; +assign pyc_extract_195 = PE_INT_WALLACE_DOT8_TREE_W19_in1[11]; +assign pyc_extract_196 = PE_INT_WALLACE_DOT8_TREE_W19_in2[11]; +assign pyc_xor_197 = (pyc_extract_194 ^ pyc_extract_195); +assign pyc_xor_198 = (pyc_xor_197 ^ pyc_extract_196); +assign pyc_and_199 = (pyc_extract_194 & pyc_extract_195); +assign pyc_and_200 = (pyc_extract_194 & pyc_extract_196); +assign pyc_or_201 = (pyc_and_199 | pyc_and_200); +assign pyc_and_202 = (pyc_extract_195 & pyc_extract_196); +assign pyc_or_203 = (pyc_or_201 | pyc_and_202); +assign pyc_extract_204 = PE_INT_WALLACE_DOT8_TREE_W19_in3[11]; +assign pyc_xor_205 = (pyc_xor_198 ^ pyc_extract_204); +assign pyc_xor_206 = (pyc_xor_205 ^ pyc_or_185); +assign pyc_and_207 = (pyc_xor_198 & pyc_extract_204); +assign pyc_and_208 = (pyc_xor_198 & pyc_or_185); +assign pyc_or_209 = (pyc_and_207 | pyc_and_208); +assign pyc_and_210 = (pyc_extract_204 & pyc_or_185); +assign pyc_or_211 = (pyc_or_209 | pyc_and_210); +assign pyc_extract_212 = PE_INT_WALLACE_DOT8_TREE_W19_in0[12]; +assign pyc_extract_213 = PE_INT_WALLACE_DOT8_TREE_W19_in1[12]; +assign pyc_extract_214 = PE_INT_WALLACE_DOT8_TREE_W19_in2[12]; +assign pyc_xor_215 = (pyc_extract_212 ^ pyc_extract_213); +assign pyc_xor_216 = (pyc_xor_215 ^ pyc_extract_214); +assign pyc_and_217 = (pyc_extract_212 & pyc_extract_213); +assign pyc_and_218 = (pyc_extract_212 & pyc_extract_214); +assign pyc_or_219 = (pyc_and_217 | pyc_and_218); +assign pyc_and_220 = (pyc_extract_213 & pyc_extract_214); +assign pyc_or_221 = (pyc_or_219 | pyc_and_220); +assign pyc_extract_222 = PE_INT_WALLACE_DOT8_TREE_W19_in3[12]; +assign pyc_xor_223 = (pyc_xor_216 ^ pyc_extract_222); +assign pyc_xor_224 = (pyc_xor_223 ^ pyc_or_203); +assign pyc_and_225 = (pyc_xor_216 & pyc_extract_222); +assign pyc_and_226 = (pyc_xor_216 & pyc_or_203); +assign pyc_or_227 = (pyc_and_225 | pyc_and_226); +assign pyc_and_228 = (pyc_extract_222 & pyc_or_203); +assign pyc_or_229 = (pyc_or_227 | pyc_and_228); +assign pyc_extract_230 = PE_INT_WALLACE_DOT8_TREE_W19_in0[13]; +assign pyc_extract_231 = PE_INT_WALLACE_DOT8_TREE_W19_in1[13]; +assign pyc_extract_232 = PE_INT_WALLACE_DOT8_TREE_W19_in2[13]; +assign pyc_xor_233 = (pyc_extract_230 ^ pyc_extract_231); +assign pyc_xor_234 = (pyc_xor_233 ^ pyc_extract_232); +assign pyc_and_235 = (pyc_extract_230 & pyc_extract_231); +assign pyc_and_236 = (pyc_extract_230 & pyc_extract_232); +assign pyc_or_237 = (pyc_and_235 | pyc_and_236); +assign pyc_and_238 = (pyc_extract_231 & pyc_extract_232); +assign pyc_or_239 = (pyc_or_237 | pyc_and_238); +assign pyc_extract_240 = PE_INT_WALLACE_DOT8_TREE_W19_in3[13]; +assign pyc_xor_241 = (pyc_xor_234 ^ pyc_extract_240); +assign pyc_xor_242 = (pyc_xor_241 ^ pyc_or_221); +assign pyc_and_243 = (pyc_xor_234 & pyc_extract_240); +assign pyc_and_244 = (pyc_xor_234 & pyc_or_221); +assign pyc_or_245 = (pyc_and_243 | pyc_and_244); +assign pyc_and_246 = (pyc_extract_240 & pyc_or_221); +assign pyc_or_247 = (pyc_or_245 | pyc_and_246); +assign pyc_extract_248 = PE_INT_WALLACE_DOT8_TREE_W19_in0[14]; +assign pyc_extract_249 = PE_INT_WALLACE_DOT8_TREE_W19_in1[14]; +assign pyc_extract_250 = PE_INT_WALLACE_DOT8_TREE_W19_in2[14]; +assign pyc_xor_251 = (pyc_extract_248 ^ pyc_extract_249); +assign pyc_xor_252 = (pyc_xor_251 ^ pyc_extract_250); +assign pyc_and_253 = (pyc_extract_248 & pyc_extract_249); +assign pyc_and_254 = (pyc_extract_248 & pyc_extract_250); +assign pyc_or_255 = (pyc_and_253 | pyc_and_254); +assign pyc_and_256 = (pyc_extract_249 & pyc_extract_250); +assign pyc_or_257 = (pyc_or_255 | pyc_and_256); +assign pyc_extract_258 = PE_INT_WALLACE_DOT8_TREE_W19_in3[14]; +assign pyc_xor_259 = (pyc_xor_252 ^ pyc_extract_258); +assign pyc_xor_260 = (pyc_xor_259 ^ pyc_or_239); +assign pyc_and_261 = (pyc_xor_252 & pyc_extract_258); +assign pyc_and_262 = (pyc_xor_252 & pyc_or_239); +assign pyc_or_263 = (pyc_and_261 | pyc_and_262); +assign pyc_and_264 = (pyc_extract_258 & pyc_or_239); +assign pyc_or_265 = (pyc_or_263 | pyc_and_264); +assign pyc_extract_266 = PE_INT_WALLACE_DOT8_TREE_W19_in0[15]; +assign pyc_extract_267 = PE_INT_WALLACE_DOT8_TREE_W19_in1[15]; +assign pyc_extract_268 = PE_INT_WALLACE_DOT8_TREE_W19_in2[15]; +assign pyc_xor_269 = (pyc_extract_266 ^ pyc_extract_267); +assign pyc_xor_270 = (pyc_xor_269 ^ pyc_extract_268); +assign pyc_and_271 = (pyc_extract_266 & pyc_extract_267); +assign pyc_and_272 = (pyc_extract_266 & pyc_extract_268); +assign pyc_or_273 = (pyc_and_271 | pyc_and_272); +assign pyc_and_274 = (pyc_extract_267 & pyc_extract_268); +assign pyc_or_275 = (pyc_or_273 | pyc_and_274); +assign pyc_extract_276 = PE_INT_WALLACE_DOT8_TREE_W19_in3[15]; +assign pyc_xor_277 = (pyc_xor_270 ^ pyc_extract_276); +assign pyc_xor_278 = (pyc_xor_277 ^ pyc_or_257); +assign pyc_and_279 = (pyc_xor_270 & pyc_extract_276); +assign pyc_and_280 = (pyc_xor_270 & pyc_or_257); +assign pyc_or_281 = (pyc_and_279 | pyc_and_280); +assign pyc_and_282 = (pyc_extract_276 & pyc_or_257); +assign pyc_or_283 = (pyc_or_281 | pyc_and_282); +assign pyc_extract_284 = PE_INT_WALLACE_DOT8_TREE_W19_in0[16]; +assign pyc_extract_285 = PE_INT_WALLACE_DOT8_TREE_W19_in1[16]; +assign pyc_extract_286 = PE_INT_WALLACE_DOT8_TREE_W19_in2[16]; +assign pyc_xor_287 = (pyc_extract_284 ^ pyc_extract_285); +assign pyc_xor_288 = (pyc_xor_287 ^ pyc_extract_286); +assign pyc_and_289 = (pyc_extract_284 & pyc_extract_285); +assign pyc_and_290 = (pyc_extract_284 & pyc_extract_286); +assign pyc_or_291 = (pyc_and_289 | pyc_and_290); +assign pyc_and_292 = (pyc_extract_285 & pyc_extract_286); +assign pyc_or_293 = (pyc_or_291 | pyc_and_292); +assign pyc_extract_294 = PE_INT_WALLACE_DOT8_TREE_W19_in3[16]; +assign pyc_xor_295 = (pyc_xor_288 ^ pyc_extract_294); +assign pyc_xor_296 = (pyc_xor_295 ^ pyc_or_275); +assign pyc_and_297 = (pyc_xor_288 & pyc_extract_294); +assign pyc_and_298 = (pyc_xor_288 & pyc_or_275); +assign pyc_or_299 = (pyc_and_297 | pyc_and_298); +assign pyc_and_300 = (pyc_extract_294 & pyc_or_275); +assign pyc_or_301 = (pyc_or_299 | pyc_and_300); +assign pyc_extract_302 = PE_INT_WALLACE_DOT8_TREE_W19_in0[17]; +assign pyc_extract_303 = PE_INT_WALLACE_DOT8_TREE_W19_in1[17]; +assign pyc_extract_304 = PE_INT_WALLACE_DOT8_TREE_W19_in2[17]; +assign pyc_xor_305 = (pyc_extract_302 ^ pyc_extract_303); +assign pyc_xor_306 = (pyc_xor_305 ^ pyc_extract_304); +assign pyc_and_307 = (pyc_extract_302 & pyc_extract_303); +assign pyc_and_308 = (pyc_extract_302 & pyc_extract_304); +assign pyc_or_309 = (pyc_and_307 | pyc_and_308); +assign pyc_and_310 = (pyc_extract_303 & pyc_extract_304); +assign pyc_or_311 = (pyc_or_309 | pyc_and_310); +assign pyc_extract_312 = PE_INT_WALLACE_DOT8_TREE_W19_in3[17]; +assign pyc_xor_313 = (pyc_xor_306 ^ pyc_extract_312); +assign pyc_xor_314 = (pyc_xor_313 ^ pyc_or_293); +assign pyc_and_315 = (pyc_xor_306 & pyc_extract_312); +assign pyc_and_316 = (pyc_xor_306 & pyc_or_293); +assign pyc_or_317 = (pyc_and_315 | pyc_and_316); +assign pyc_and_318 = (pyc_extract_312 & pyc_or_293); +assign pyc_or_319 = (pyc_or_317 | pyc_and_318); +assign pyc_extract_320 = PE_INT_WALLACE_DOT8_TREE_W19_in0[18]; +assign pyc_extract_321 = PE_INT_WALLACE_DOT8_TREE_W19_in1[18]; +assign pyc_extract_322 = PE_INT_WALLACE_DOT8_TREE_W19_in2[18]; +assign pyc_xor_323 = (pyc_extract_320 ^ pyc_extract_321); +assign pyc_xor_324 = (pyc_xor_323 ^ pyc_extract_322); +assign pyc_extract_325 = PE_INT_WALLACE_DOT8_TREE_W19_in3[18]; +assign pyc_xor_326 = (pyc_xor_324 ^ pyc_extract_325); +assign pyc_xor_327 = (pyc_xor_326 ^ pyc_or_311); +assign pyc_extract_328 = PE_INT_WALLACE_DOT8_TREE_W19_in4[0]; +assign pyc_extract_329 = PE_INT_WALLACE_DOT8_TREE_W19_in5[0]; +assign pyc_extract_330 = PE_INT_WALLACE_DOT8_TREE_W19_in6[0]; +assign pyc_xor_331 = (pyc_extract_328 ^ pyc_extract_329); +assign pyc_xor_332 = (pyc_xor_331 ^ pyc_extract_330); +assign pyc_and_333 = (pyc_extract_328 & pyc_extract_329); +assign pyc_and_334 = (pyc_extract_328 & pyc_extract_330); +assign pyc_or_335 = (pyc_and_333 | pyc_and_334); +assign pyc_and_336 = (pyc_extract_329 & pyc_extract_330); +assign pyc_or_337 = (pyc_or_335 | pyc_and_336); +assign pyc_extract_338 = PE_INT_WALLACE_DOT8_TREE_W19_in7[0]; +assign pyc_xor_339 = (pyc_xor_332 ^ pyc_extract_338); +assign pyc_and_340 = (pyc_xor_332 & pyc_extract_338); +assign pyc_extract_341 = PE_INT_WALLACE_DOT8_TREE_W19_in4[1]; +assign pyc_extract_342 = PE_INT_WALLACE_DOT8_TREE_W19_in5[1]; +assign pyc_extract_343 = PE_INT_WALLACE_DOT8_TREE_W19_in6[1]; +assign pyc_xor_344 = (pyc_extract_341 ^ pyc_extract_342); +assign pyc_xor_345 = (pyc_xor_344 ^ pyc_extract_343); +assign pyc_and_346 = (pyc_extract_341 & pyc_extract_342); +assign pyc_and_347 = (pyc_extract_341 & pyc_extract_343); +assign pyc_or_348 = (pyc_and_346 | pyc_and_347); +assign pyc_and_349 = (pyc_extract_342 & pyc_extract_343); +assign pyc_or_350 = (pyc_or_348 | pyc_and_349); +assign pyc_extract_351 = PE_INT_WALLACE_DOT8_TREE_W19_in7[1]; +assign pyc_xor_352 = (pyc_xor_345 ^ pyc_extract_351); +assign pyc_xor_353 = (pyc_xor_352 ^ pyc_or_337); +assign pyc_and_354 = (pyc_xor_345 & pyc_extract_351); +assign pyc_and_355 = (pyc_xor_345 & pyc_or_337); +assign pyc_or_356 = (pyc_and_354 | pyc_and_355); +assign pyc_and_357 = (pyc_extract_351 & pyc_or_337); +assign pyc_or_358 = (pyc_or_356 | pyc_and_357); +assign pyc_extract_359 = PE_INT_WALLACE_DOT8_TREE_W19_in4[2]; +assign pyc_extract_360 = PE_INT_WALLACE_DOT8_TREE_W19_in5[2]; +assign pyc_extract_361 = PE_INT_WALLACE_DOT8_TREE_W19_in6[2]; +assign pyc_xor_362 = (pyc_extract_359 ^ pyc_extract_360); +assign pyc_xor_363 = (pyc_xor_362 ^ pyc_extract_361); +assign pyc_and_364 = (pyc_extract_359 & pyc_extract_360); +assign pyc_and_365 = (pyc_extract_359 & pyc_extract_361); +assign pyc_or_366 = (pyc_and_364 | pyc_and_365); +assign pyc_and_367 = (pyc_extract_360 & pyc_extract_361); +assign pyc_or_368 = (pyc_or_366 | pyc_and_367); +assign pyc_extract_369 = PE_INT_WALLACE_DOT8_TREE_W19_in7[2]; +assign pyc_xor_370 = (pyc_xor_363 ^ pyc_extract_369); +assign pyc_xor_371 = (pyc_xor_370 ^ pyc_or_350); +assign pyc_and_372 = (pyc_xor_363 & pyc_extract_369); +assign pyc_and_373 = (pyc_xor_363 & pyc_or_350); +assign pyc_or_374 = (pyc_and_372 | pyc_and_373); +assign pyc_and_375 = (pyc_extract_369 & pyc_or_350); +assign pyc_or_376 = (pyc_or_374 | pyc_and_375); +assign pyc_extract_377 = PE_INT_WALLACE_DOT8_TREE_W19_in4[3]; +assign pyc_extract_378 = PE_INT_WALLACE_DOT8_TREE_W19_in5[3]; +assign pyc_extract_379 = PE_INT_WALLACE_DOT8_TREE_W19_in6[3]; +assign pyc_xor_380 = (pyc_extract_377 ^ pyc_extract_378); +assign pyc_xor_381 = (pyc_xor_380 ^ pyc_extract_379); +assign pyc_and_382 = (pyc_extract_377 & pyc_extract_378); +assign pyc_and_383 = (pyc_extract_377 & pyc_extract_379); +assign pyc_or_384 = (pyc_and_382 | pyc_and_383); +assign pyc_and_385 = (pyc_extract_378 & pyc_extract_379); +assign pyc_or_386 = (pyc_or_384 | pyc_and_385); +assign pyc_extract_387 = PE_INT_WALLACE_DOT8_TREE_W19_in7[3]; +assign pyc_xor_388 = (pyc_xor_381 ^ pyc_extract_387); +assign pyc_xor_389 = (pyc_xor_388 ^ pyc_or_368); +assign pyc_and_390 = (pyc_xor_381 & pyc_extract_387); +assign pyc_and_391 = (pyc_xor_381 & pyc_or_368); +assign pyc_or_392 = (pyc_and_390 | pyc_and_391); +assign pyc_and_393 = (pyc_extract_387 & pyc_or_368); +assign pyc_or_394 = (pyc_or_392 | pyc_and_393); +assign pyc_extract_395 = PE_INT_WALLACE_DOT8_TREE_W19_in4[4]; +assign pyc_extract_396 = PE_INT_WALLACE_DOT8_TREE_W19_in5[4]; +assign pyc_extract_397 = PE_INT_WALLACE_DOT8_TREE_W19_in6[4]; +assign pyc_xor_398 = (pyc_extract_395 ^ pyc_extract_396); +assign pyc_xor_399 = (pyc_xor_398 ^ pyc_extract_397); +assign pyc_and_400 = (pyc_extract_395 & pyc_extract_396); +assign pyc_and_401 = (pyc_extract_395 & pyc_extract_397); +assign pyc_or_402 = (pyc_and_400 | pyc_and_401); +assign pyc_and_403 = (pyc_extract_396 & pyc_extract_397); +assign pyc_or_404 = (pyc_or_402 | pyc_and_403); +assign pyc_extract_405 = PE_INT_WALLACE_DOT8_TREE_W19_in7[4]; +assign pyc_xor_406 = (pyc_xor_399 ^ pyc_extract_405); +assign pyc_xor_407 = (pyc_xor_406 ^ pyc_or_386); +assign pyc_and_408 = (pyc_xor_399 & pyc_extract_405); +assign pyc_and_409 = (pyc_xor_399 & pyc_or_386); +assign pyc_or_410 = (pyc_and_408 | pyc_and_409); +assign pyc_and_411 = (pyc_extract_405 & pyc_or_386); +assign pyc_or_412 = (pyc_or_410 | pyc_and_411); +assign pyc_extract_413 = PE_INT_WALLACE_DOT8_TREE_W19_in4[5]; +assign pyc_extract_414 = PE_INT_WALLACE_DOT8_TREE_W19_in5[5]; +assign pyc_extract_415 = PE_INT_WALLACE_DOT8_TREE_W19_in6[5]; +assign pyc_xor_416 = (pyc_extract_413 ^ pyc_extract_414); +assign pyc_xor_417 = (pyc_xor_416 ^ pyc_extract_415); +assign pyc_and_418 = (pyc_extract_413 & pyc_extract_414); +assign pyc_and_419 = (pyc_extract_413 & pyc_extract_415); +assign pyc_or_420 = (pyc_and_418 | pyc_and_419); +assign pyc_and_421 = (pyc_extract_414 & pyc_extract_415); +assign pyc_or_422 = (pyc_or_420 | pyc_and_421); +assign pyc_extract_423 = PE_INT_WALLACE_DOT8_TREE_W19_in7[5]; +assign pyc_xor_424 = (pyc_xor_417 ^ pyc_extract_423); +assign pyc_xor_425 = (pyc_xor_424 ^ pyc_or_404); +assign pyc_and_426 = (pyc_xor_417 & pyc_extract_423); +assign pyc_and_427 = (pyc_xor_417 & pyc_or_404); +assign pyc_or_428 = (pyc_and_426 | pyc_and_427); +assign pyc_and_429 = (pyc_extract_423 & pyc_or_404); +assign pyc_or_430 = (pyc_or_428 | pyc_and_429); +assign pyc_extract_431 = PE_INT_WALLACE_DOT8_TREE_W19_in4[6]; +assign pyc_extract_432 = PE_INT_WALLACE_DOT8_TREE_W19_in5[6]; +assign pyc_extract_433 = PE_INT_WALLACE_DOT8_TREE_W19_in6[6]; +assign pyc_xor_434 = (pyc_extract_431 ^ pyc_extract_432); +assign pyc_xor_435 = (pyc_xor_434 ^ pyc_extract_433); +assign pyc_and_436 = (pyc_extract_431 & pyc_extract_432); +assign pyc_and_437 = (pyc_extract_431 & pyc_extract_433); +assign pyc_or_438 = (pyc_and_436 | pyc_and_437); +assign pyc_and_439 = (pyc_extract_432 & pyc_extract_433); +assign pyc_or_440 = (pyc_or_438 | pyc_and_439); +assign pyc_extract_441 = PE_INT_WALLACE_DOT8_TREE_W19_in7[6]; +assign pyc_xor_442 = (pyc_xor_435 ^ pyc_extract_441); +assign pyc_xor_443 = (pyc_xor_442 ^ pyc_or_422); +assign pyc_and_444 = (pyc_xor_435 & pyc_extract_441); +assign pyc_and_445 = (pyc_xor_435 & pyc_or_422); +assign pyc_or_446 = (pyc_and_444 | pyc_and_445); +assign pyc_and_447 = (pyc_extract_441 & pyc_or_422); +assign pyc_or_448 = (pyc_or_446 | pyc_and_447); +assign pyc_extract_449 = PE_INT_WALLACE_DOT8_TREE_W19_in4[7]; +assign pyc_extract_450 = PE_INT_WALLACE_DOT8_TREE_W19_in5[7]; +assign pyc_extract_451 = PE_INT_WALLACE_DOT8_TREE_W19_in6[7]; +assign pyc_xor_452 = (pyc_extract_449 ^ pyc_extract_450); +assign pyc_xor_453 = (pyc_xor_452 ^ pyc_extract_451); +assign pyc_and_454 = (pyc_extract_449 & pyc_extract_450); +assign pyc_and_455 = (pyc_extract_449 & pyc_extract_451); +assign pyc_or_456 = (pyc_and_454 | pyc_and_455); +assign pyc_and_457 = (pyc_extract_450 & pyc_extract_451); +assign pyc_or_458 = (pyc_or_456 | pyc_and_457); +assign pyc_extract_459 = PE_INT_WALLACE_DOT8_TREE_W19_in7[7]; +assign pyc_xor_460 = (pyc_xor_453 ^ pyc_extract_459); +assign pyc_xor_461 = (pyc_xor_460 ^ pyc_or_440); +assign pyc_and_462 = (pyc_xor_453 & pyc_extract_459); +assign pyc_and_463 = (pyc_xor_453 & pyc_or_440); +assign pyc_or_464 = (pyc_and_462 | pyc_and_463); +assign pyc_and_465 = (pyc_extract_459 & pyc_or_440); +assign pyc_or_466 = (pyc_or_464 | pyc_and_465); +assign pyc_extract_467 = PE_INT_WALLACE_DOT8_TREE_W19_in4[8]; +assign pyc_extract_468 = PE_INT_WALLACE_DOT8_TREE_W19_in5[8]; +assign pyc_extract_469 = PE_INT_WALLACE_DOT8_TREE_W19_in6[8]; +assign pyc_xor_470 = (pyc_extract_467 ^ pyc_extract_468); +assign pyc_xor_471 = (pyc_xor_470 ^ pyc_extract_469); +assign pyc_and_472 = (pyc_extract_467 & pyc_extract_468); +assign pyc_and_473 = (pyc_extract_467 & pyc_extract_469); +assign pyc_or_474 = (pyc_and_472 | pyc_and_473); +assign pyc_and_475 = (pyc_extract_468 & pyc_extract_469); +assign pyc_or_476 = (pyc_or_474 | pyc_and_475); +assign pyc_extract_477 = PE_INT_WALLACE_DOT8_TREE_W19_in7[8]; +assign pyc_xor_478 = (pyc_xor_471 ^ pyc_extract_477); +assign pyc_xor_479 = (pyc_xor_478 ^ pyc_or_458); +assign pyc_and_480 = (pyc_xor_471 & pyc_extract_477); +assign pyc_and_481 = (pyc_xor_471 & pyc_or_458); +assign pyc_or_482 = (pyc_and_480 | pyc_and_481); +assign pyc_and_483 = (pyc_extract_477 & pyc_or_458); +assign pyc_or_484 = (pyc_or_482 | pyc_and_483); +assign pyc_extract_485 = PE_INT_WALLACE_DOT8_TREE_W19_in4[9]; +assign pyc_extract_486 = PE_INT_WALLACE_DOT8_TREE_W19_in5[9]; +assign pyc_extract_487 = PE_INT_WALLACE_DOT8_TREE_W19_in6[9]; +assign pyc_xor_488 = (pyc_extract_485 ^ pyc_extract_486); +assign pyc_xor_489 = (pyc_xor_488 ^ pyc_extract_487); +assign pyc_and_490 = (pyc_extract_485 & pyc_extract_486); +assign pyc_and_491 = (pyc_extract_485 & pyc_extract_487); +assign pyc_or_492 = (pyc_and_490 | pyc_and_491); +assign pyc_and_493 = (pyc_extract_486 & pyc_extract_487); +assign pyc_or_494 = (pyc_or_492 | pyc_and_493); +assign pyc_extract_495 = PE_INT_WALLACE_DOT8_TREE_W19_in7[9]; +assign pyc_xor_496 = (pyc_xor_489 ^ pyc_extract_495); +assign pyc_xor_497 = (pyc_xor_496 ^ pyc_or_476); +assign pyc_and_498 = (pyc_xor_489 & pyc_extract_495); +assign pyc_and_499 = (pyc_xor_489 & pyc_or_476); +assign pyc_or_500 = (pyc_and_498 | pyc_and_499); +assign pyc_and_501 = (pyc_extract_495 & pyc_or_476); +assign pyc_or_502 = (pyc_or_500 | pyc_and_501); +assign pyc_extract_503 = PE_INT_WALLACE_DOT8_TREE_W19_in4[10]; +assign pyc_extract_504 = PE_INT_WALLACE_DOT8_TREE_W19_in5[10]; +assign pyc_extract_505 = PE_INT_WALLACE_DOT8_TREE_W19_in6[10]; +assign pyc_xor_506 = (pyc_extract_503 ^ pyc_extract_504); +assign pyc_xor_507 = (pyc_xor_506 ^ pyc_extract_505); +assign pyc_and_508 = (pyc_extract_503 & pyc_extract_504); +assign pyc_and_509 = (pyc_extract_503 & pyc_extract_505); +assign pyc_or_510 = (pyc_and_508 | pyc_and_509); +assign pyc_and_511 = (pyc_extract_504 & pyc_extract_505); +assign pyc_or_512 = (pyc_or_510 | pyc_and_511); +assign pyc_extract_513 = PE_INT_WALLACE_DOT8_TREE_W19_in7[10]; +assign pyc_xor_514 = (pyc_xor_507 ^ pyc_extract_513); +assign pyc_xor_515 = (pyc_xor_514 ^ pyc_or_494); +assign pyc_and_516 = (pyc_xor_507 & pyc_extract_513); +assign pyc_and_517 = (pyc_xor_507 & pyc_or_494); +assign pyc_or_518 = (pyc_and_516 | pyc_and_517); +assign pyc_and_519 = (pyc_extract_513 & pyc_or_494); +assign pyc_or_520 = (pyc_or_518 | pyc_and_519); +assign pyc_extract_521 = PE_INT_WALLACE_DOT8_TREE_W19_in4[11]; +assign pyc_extract_522 = PE_INT_WALLACE_DOT8_TREE_W19_in5[11]; +assign pyc_extract_523 = PE_INT_WALLACE_DOT8_TREE_W19_in6[11]; +assign pyc_xor_524 = (pyc_extract_521 ^ pyc_extract_522); +assign pyc_xor_525 = (pyc_xor_524 ^ pyc_extract_523); +assign pyc_and_526 = (pyc_extract_521 & pyc_extract_522); +assign pyc_and_527 = (pyc_extract_521 & pyc_extract_523); +assign pyc_or_528 = (pyc_and_526 | pyc_and_527); +assign pyc_and_529 = (pyc_extract_522 & pyc_extract_523); +assign pyc_or_530 = (pyc_or_528 | pyc_and_529); +assign pyc_extract_531 = PE_INT_WALLACE_DOT8_TREE_W19_in7[11]; +assign pyc_xor_532 = (pyc_xor_525 ^ pyc_extract_531); +assign pyc_xor_533 = (pyc_xor_532 ^ pyc_or_512); +assign pyc_and_534 = (pyc_xor_525 & pyc_extract_531); +assign pyc_and_535 = (pyc_xor_525 & pyc_or_512); +assign pyc_or_536 = (pyc_and_534 | pyc_and_535); +assign pyc_and_537 = (pyc_extract_531 & pyc_or_512); +assign pyc_or_538 = (pyc_or_536 | pyc_and_537); +assign pyc_extract_539 = PE_INT_WALLACE_DOT8_TREE_W19_in4[12]; +assign pyc_extract_540 = PE_INT_WALLACE_DOT8_TREE_W19_in5[12]; +assign pyc_extract_541 = PE_INT_WALLACE_DOT8_TREE_W19_in6[12]; +assign pyc_xor_542 = (pyc_extract_539 ^ pyc_extract_540); +assign pyc_xor_543 = (pyc_xor_542 ^ pyc_extract_541); +assign pyc_and_544 = (pyc_extract_539 & pyc_extract_540); +assign pyc_and_545 = (pyc_extract_539 & pyc_extract_541); +assign pyc_or_546 = (pyc_and_544 | pyc_and_545); +assign pyc_and_547 = (pyc_extract_540 & pyc_extract_541); +assign pyc_or_548 = (pyc_or_546 | pyc_and_547); +assign pyc_extract_549 = PE_INT_WALLACE_DOT8_TREE_W19_in7[12]; +assign pyc_xor_550 = (pyc_xor_543 ^ pyc_extract_549); +assign pyc_xor_551 = (pyc_xor_550 ^ pyc_or_530); +assign pyc_and_552 = (pyc_xor_543 & pyc_extract_549); +assign pyc_and_553 = (pyc_xor_543 & pyc_or_530); +assign pyc_or_554 = (pyc_and_552 | pyc_and_553); +assign pyc_and_555 = (pyc_extract_549 & pyc_or_530); +assign pyc_or_556 = (pyc_or_554 | pyc_and_555); +assign pyc_extract_557 = PE_INT_WALLACE_DOT8_TREE_W19_in4[13]; +assign pyc_extract_558 = PE_INT_WALLACE_DOT8_TREE_W19_in5[13]; +assign pyc_extract_559 = PE_INT_WALLACE_DOT8_TREE_W19_in6[13]; +assign pyc_xor_560 = (pyc_extract_557 ^ pyc_extract_558); +assign pyc_xor_561 = (pyc_xor_560 ^ pyc_extract_559); +assign pyc_and_562 = (pyc_extract_557 & pyc_extract_558); +assign pyc_and_563 = (pyc_extract_557 & pyc_extract_559); +assign pyc_or_564 = (pyc_and_562 | pyc_and_563); +assign pyc_and_565 = (pyc_extract_558 & pyc_extract_559); +assign pyc_or_566 = (pyc_or_564 | pyc_and_565); +assign pyc_extract_567 = PE_INT_WALLACE_DOT8_TREE_W19_in7[13]; +assign pyc_xor_568 = (pyc_xor_561 ^ pyc_extract_567); +assign pyc_xor_569 = (pyc_xor_568 ^ pyc_or_548); +assign pyc_and_570 = (pyc_xor_561 & pyc_extract_567); +assign pyc_and_571 = (pyc_xor_561 & pyc_or_548); +assign pyc_or_572 = (pyc_and_570 | pyc_and_571); +assign pyc_and_573 = (pyc_extract_567 & pyc_or_548); +assign pyc_or_574 = (pyc_or_572 | pyc_and_573); +assign pyc_extract_575 = PE_INT_WALLACE_DOT8_TREE_W19_in4[14]; +assign pyc_extract_576 = PE_INT_WALLACE_DOT8_TREE_W19_in5[14]; +assign pyc_extract_577 = PE_INT_WALLACE_DOT8_TREE_W19_in6[14]; +assign pyc_xor_578 = (pyc_extract_575 ^ pyc_extract_576); +assign pyc_xor_579 = (pyc_xor_578 ^ pyc_extract_577); +assign pyc_and_580 = (pyc_extract_575 & pyc_extract_576); +assign pyc_and_581 = (pyc_extract_575 & pyc_extract_577); +assign pyc_or_582 = (pyc_and_580 | pyc_and_581); +assign pyc_and_583 = (pyc_extract_576 & pyc_extract_577); +assign pyc_or_584 = (pyc_or_582 | pyc_and_583); +assign pyc_extract_585 = PE_INT_WALLACE_DOT8_TREE_W19_in7[14]; +assign pyc_xor_586 = (pyc_xor_579 ^ pyc_extract_585); +assign pyc_xor_587 = (pyc_xor_586 ^ pyc_or_566); +assign pyc_and_588 = (pyc_xor_579 & pyc_extract_585); +assign pyc_and_589 = (pyc_xor_579 & pyc_or_566); +assign pyc_or_590 = (pyc_and_588 | pyc_and_589); +assign pyc_and_591 = (pyc_extract_585 & pyc_or_566); +assign pyc_or_592 = (pyc_or_590 | pyc_and_591); +assign pyc_extract_593 = PE_INT_WALLACE_DOT8_TREE_W19_in4[15]; +assign pyc_extract_594 = PE_INT_WALLACE_DOT8_TREE_W19_in5[15]; +assign pyc_extract_595 = PE_INT_WALLACE_DOT8_TREE_W19_in6[15]; +assign pyc_xor_596 = (pyc_extract_593 ^ pyc_extract_594); +assign pyc_xor_597 = (pyc_xor_596 ^ pyc_extract_595); +assign pyc_and_598 = (pyc_extract_593 & pyc_extract_594); +assign pyc_and_599 = (pyc_extract_593 & pyc_extract_595); +assign pyc_or_600 = (pyc_and_598 | pyc_and_599); +assign pyc_and_601 = (pyc_extract_594 & pyc_extract_595); +assign pyc_or_602 = (pyc_or_600 | pyc_and_601); +assign pyc_extract_603 = PE_INT_WALLACE_DOT8_TREE_W19_in7[15]; +assign pyc_xor_604 = (pyc_xor_597 ^ pyc_extract_603); +assign pyc_xor_605 = (pyc_xor_604 ^ pyc_or_584); +assign pyc_and_606 = (pyc_xor_597 & pyc_extract_603); +assign pyc_and_607 = (pyc_xor_597 & pyc_or_584); +assign pyc_or_608 = (pyc_and_606 | pyc_and_607); +assign pyc_and_609 = (pyc_extract_603 & pyc_or_584); +assign pyc_or_610 = (pyc_or_608 | pyc_and_609); +assign pyc_extract_611 = PE_INT_WALLACE_DOT8_TREE_W19_in4[16]; +assign pyc_extract_612 = PE_INT_WALLACE_DOT8_TREE_W19_in5[16]; +assign pyc_extract_613 = PE_INT_WALLACE_DOT8_TREE_W19_in6[16]; +assign pyc_xor_614 = (pyc_extract_611 ^ pyc_extract_612); +assign pyc_xor_615 = (pyc_xor_614 ^ pyc_extract_613); +assign pyc_and_616 = (pyc_extract_611 & pyc_extract_612); +assign pyc_and_617 = (pyc_extract_611 & pyc_extract_613); +assign pyc_or_618 = (pyc_and_616 | pyc_and_617); +assign pyc_and_619 = (pyc_extract_612 & pyc_extract_613); +assign pyc_or_620 = (pyc_or_618 | pyc_and_619); +assign pyc_extract_621 = PE_INT_WALLACE_DOT8_TREE_W19_in7[16]; +assign pyc_xor_622 = (pyc_xor_615 ^ pyc_extract_621); +assign pyc_xor_623 = (pyc_xor_622 ^ pyc_or_602); +assign pyc_and_624 = (pyc_xor_615 & pyc_extract_621); +assign pyc_and_625 = (pyc_xor_615 & pyc_or_602); +assign pyc_or_626 = (pyc_and_624 | pyc_and_625); +assign pyc_and_627 = (pyc_extract_621 & pyc_or_602); +assign pyc_or_628 = (pyc_or_626 | pyc_and_627); +assign pyc_extract_629 = PE_INT_WALLACE_DOT8_TREE_W19_in4[17]; +assign pyc_extract_630 = PE_INT_WALLACE_DOT8_TREE_W19_in5[17]; +assign pyc_extract_631 = PE_INT_WALLACE_DOT8_TREE_W19_in6[17]; +assign pyc_xor_632 = (pyc_extract_629 ^ pyc_extract_630); +assign pyc_xor_633 = (pyc_xor_632 ^ pyc_extract_631); +assign pyc_and_634 = (pyc_extract_629 & pyc_extract_630); +assign pyc_and_635 = (pyc_extract_629 & pyc_extract_631); +assign pyc_or_636 = (pyc_and_634 | pyc_and_635); +assign pyc_and_637 = (pyc_extract_630 & pyc_extract_631); +assign pyc_or_638 = (pyc_or_636 | pyc_and_637); +assign pyc_extract_639 = PE_INT_WALLACE_DOT8_TREE_W19_in7[17]; +assign pyc_xor_640 = (pyc_xor_633 ^ pyc_extract_639); +assign pyc_xor_641 = (pyc_xor_640 ^ pyc_or_620); +assign pyc_and_642 = (pyc_xor_633 & pyc_extract_639); +assign pyc_and_643 = (pyc_xor_633 & pyc_or_620); +assign pyc_or_644 = (pyc_and_642 | pyc_and_643); +assign pyc_and_645 = (pyc_extract_639 & pyc_or_620); +assign pyc_or_646 = (pyc_or_644 | pyc_and_645); +assign pyc_extract_647 = PE_INT_WALLACE_DOT8_TREE_W19_in4[18]; +assign pyc_extract_648 = PE_INT_WALLACE_DOT8_TREE_W19_in5[18]; +assign pyc_extract_649 = PE_INT_WALLACE_DOT8_TREE_W19_in6[18]; +assign pyc_xor_650 = (pyc_extract_647 ^ pyc_extract_648); +assign pyc_xor_651 = (pyc_xor_650 ^ pyc_extract_649); +assign pyc_extract_652 = PE_INT_WALLACE_DOT8_TREE_W19_in7[18]; +assign pyc_xor_653 = (pyc_xor_651 ^ pyc_extract_652); +assign pyc_xor_654 = (pyc_xor_653 ^ pyc_or_638); +assign pyc_xor_655 = (pyc_xor_12 ^ pyc_xor_339); +assign pyc_and_656 = (pyc_xor_12 & pyc_xor_339); +assign pyc_xor_657 = (pyc_xor_26 ^ pyc_and_13); +assign pyc_xor_658 = (pyc_xor_657 ^ pyc_xor_353); +assign pyc_and_659 = (pyc_xor_26 & pyc_and_13); +assign pyc_and_660 = (pyc_xor_26 & pyc_xor_353); +assign pyc_or_661 = (pyc_and_659 | pyc_and_660); +assign pyc_and_662 = (pyc_and_13 & pyc_xor_353); +assign pyc_or_663 = (pyc_or_661 | pyc_and_662); +assign pyc_xor_664 = (pyc_xor_658 ^ pyc_and_340); +assign pyc_xor_665 = (pyc_xor_664 ^ pyc_and_656); +assign pyc_and_666 = (pyc_xor_658 & pyc_and_340); +assign pyc_and_667 = (pyc_xor_658 & pyc_and_656); +assign pyc_or_668 = (pyc_and_666 | pyc_and_667); +assign pyc_and_669 = (pyc_and_340 & pyc_and_656); +assign pyc_or_670 = (pyc_or_668 | pyc_and_669); +assign pyc_xor_671 = (pyc_xor_44 ^ pyc_or_31); +assign pyc_xor_672 = (pyc_xor_671 ^ pyc_xor_371); +assign pyc_and_673 = (pyc_xor_44 & pyc_or_31); +assign pyc_and_674 = (pyc_xor_44 & pyc_xor_371); +assign pyc_or_675 = (pyc_and_673 | pyc_and_674); +assign pyc_and_676 = (pyc_or_31 & pyc_xor_371); +assign pyc_or_677 = (pyc_or_675 | pyc_and_676); +assign pyc_xor_678 = (pyc_xor_672 ^ pyc_or_358); +assign pyc_xor_679 = (pyc_xor_678 ^ pyc_or_663); +assign pyc_and_680 = (pyc_xor_672 & pyc_or_358); +assign pyc_and_681 = (pyc_xor_672 & pyc_or_663); +assign pyc_or_682 = (pyc_and_680 | pyc_and_681); +assign pyc_and_683 = (pyc_or_358 & pyc_or_663); +assign pyc_or_684 = (pyc_or_682 | pyc_and_683); +assign pyc_xor_685 = (pyc_xor_62 ^ pyc_or_49); +assign pyc_xor_686 = (pyc_xor_685 ^ pyc_xor_389); +assign pyc_and_687 = (pyc_xor_62 & pyc_or_49); +assign pyc_and_688 = (pyc_xor_62 & pyc_xor_389); +assign pyc_or_689 = (pyc_and_687 | pyc_and_688); +assign pyc_and_690 = (pyc_or_49 & pyc_xor_389); +assign pyc_or_691 = (pyc_or_689 | pyc_and_690); +assign pyc_xor_692 = (pyc_xor_686 ^ pyc_or_376); +assign pyc_xor_693 = (pyc_xor_692 ^ pyc_or_677); +assign pyc_and_694 = (pyc_xor_686 & pyc_or_376); +assign pyc_and_695 = (pyc_xor_686 & pyc_or_677); +assign pyc_or_696 = (pyc_and_694 | pyc_and_695); +assign pyc_and_697 = (pyc_or_376 & pyc_or_677); +assign pyc_or_698 = (pyc_or_696 | pyc_and_697); +assign pyc_xor_699 = (pyc_xor_80 ^ pyc_or_67); +assign pyc_xor_700 = (pyc_xor_699 ^ pyc_xor_407); +assign pyc_and_701 = (pyc_xor_80 & pyc_or_67); +assign pyc_and_702 = (pyc_xor_80 & pyc_xor_407); +assign pyc_or_703 = (pyc_and_701 | pyc_and_702); +assign pyc_and_704 = (pyc_or_67 & pyc_xor_407); +assign pyc_or_705 = (pyc_or_703 | pyc_and_704); +assign pyc_xor_706 = (pyc_xor_700 ^ pyc_or_394); +assign pyc_xor_707 = (pyc_xor_706 ^ pyc_or_691); +assign pyc_and_708 = (pyc_xor_700 & pyc_or_394); +assign pyc_and_709 = (pyc_xor_700 & pyc_or_691); +assign pyc_or_710 = (pyc_and_708 | pyc_and_709); +assign pyc_and_711 = (pyc_or_394 & pyc_or_691); +assign pyc_or_712 = (pyc_or_710 | pyc_and_711); +assign pyc_xor_713 = (pyc_xor_98 ^ pyc_or_85); +assign pyc_xor_714 = (pyc_xor_713 ^ pyc_xor_425); +assign pyc_and_715 = (pyc_xor_98 & pyc_or_85); +assign pyc_and_716 = (pyc_xor_98 & pyc_xor_425); +assign pyc_or_717 = (pyc_and_715 | pyc_and_716); +assign pyc_and_718 = (pyc_or_85 & pyc_xor_425); +assign pyc_or_719 = (pyc_or_717 | pyc_and_718); +assign pyc_xor_720 = (pyc_xor_714 ^ pyc_or_412); +assign pyc_xor_721 = (pyc_xor_720 ^ pyc_or_705); +assign pyc_and_722 = (pyc_xor_714 & pyc_or_412); +assign pyc_and_723 = (pyc_xor_714 & pyc_or_705); +assign pyc_or_724 = (pyc_and_722 | pyc_and_723); +assign pyc_and_725 = (pyc_or_412 & pyc_or_705); +assign pyc_or_726 = (pyc_or_724 | pyc_and_725); +assign pyc_xor_727 = (pyc_xor_116 ^ pyc_or_103); +assign pyc_xor_728 = (pyc_xor_727 ^ pyc_xor_443); +assign pyc_and_729 = (pyc_xor_116 & pyc_or_103); +assign pyc_and_730 = (pyc_xor_116 & pyc_xor_443); +assign pyc_or_731 = (pyc_and_729 | pyc_and_730); +assign pyc_and_732 = (pyc_or_103 & pyc_xor_443); +assign pyc_or_733 = (pyc_or_731 | pyc_and_732); +assign pyc_xor_734 = (pyc_xor_728 ^ pyc_or_430); +assign pyc_xor_735 = (pyc_xor_734 ^ pyc_or_719); +assign pyc_and_736 = (pyc_xor_728 & pyc_or_430); +assign pyc_and_737 = (pyc_xor_728 & pyc_or_719); +assign pyc_or_738 = (pyc_and_736 | pyc_and_737); +assign pyc_and_739 = (pyc_or_430 & pyc_or_719); +assign pyc_or_740 = (pyc_or_738 | pyc_and_739); +assign pyc_xor_741 = (pyc_xor_134 ^ pyc_or_121); +assign pyc_xor_742 = (pyc_xor_741 ^ pyc_xor_461); +assign pyc_and_743 = (pyc_xor_134 & pyc_or_121); +assign pyc_and_744 = (pyc_xor_134 & pyc_xor_461); +assign pyc_or_745 = (pyc_and_743 | pyc_and_744); +assign pyc_and_746 = (pyc_or_121 & pyc_xor_461); +assign pyc_or_747 = (pyc_or_745 | pyc_and_746); +assign pyc_xor_748 = (pyc_xor_742 ^ pyc_or_448); +assign pyc_xor_749 = (pyc_xor_748 ^ pyc_or_733); +assign pyc_and_750 = (pyc_xor_742 & pyc_or_448); +assign pyc_and_751 = (pyc_xor_742 & pyc_or_733); +assign pyc_or_752 = (pyc_and_750 | pyc_and_751); +assign pyc_and_753 = (pyc_or_448 & pyc_or_733); +assign pyc_or_754 = (pyc_or_752 | pyc_and_753); +assign pyc_xor_755 = (pyc_xor_152 ^ pyc_or_139); +assign pyc_xor_756 = (pyc_xor_755 ^ pyc_xor_479); +assign pyc_and_757 = (pyc_xor_152 & pyc_or_139); +assign pyc_and_758 = (pyc_xor_152 & pyc_xor_479); +assign pyc_or_759 = (pyc_and_757 | pyc_and_758); +assign pyc_and_760 = (pyc_or_139 & pyc_xor_479); +assign pyc_or_761 = (pyc_or_759 | pyc_and_760); +assign pyc_xor_762 = (pyc_xor_756 ^ pyc_or_466); +assign pyc_xor_763 = (pyc_xor_762 ^ pyc_or_747); +assign pyc_and_764 = (pyc_xor_756 & pyc_or_466); +assign pyc_and_765 = (pyc_xor_756 & pyc_or_747); +assign pyc_or_766 = (pyc_and_764 | pyc_and_765); +assign pyc_and_767 = (pyc_or_466 & pyc_or_747); +assign pyc_or_768 = (pyc_or_766 | pyc_and_767); +assign pyc_xor_769 = (pyc_xor_170 ^ pyc_or_157); +assign pyc_xor_770 = (pyc_xor_769 ^ pyc_xor_497); +assign pyc_and_771 = (pyc_xor_170 & pyc_or_157); +assign pyc_and_772 = (pyc_xor_170 & pyc_xor_497); +assign pyc_or_773 = (pyc_and_771 | pyc_and_772); +assign pyc_and_774 = (pyc_or_157 & pyc_xor_497); +assign pyc_or_775 = (pyc_or_773 | pyc_and_774); +assign pyc_xor_776 = (pyc_xor_770 ^ pyc_or_484); +assign pyc_xor_777 = (pyc_xor_776 ^ pyc_or_761); +assign pyc_and_778 = (pyc_xor_770 & pyc_or_484); +assign pyc_and_779 = (pyc_xor_770 & pyc_or_761); +assign pyc_or_780 = (pyc_and_778 | pyc_and_779); +assign pyc_and_781 = (pyc_or_484 & pyc_or_761); +assign pyc_or_782 = (pyc_or_780 | pyc_and_781); +assign pyc_xor_783 = (pyc_xor_188 ^ pyc_or_175); +assign pyc_xor_784 = (pyc_xor_783 ^ pyc_xor_515); +assign pyc_and_785 = (pyc_xor_188 & pyc_or_175); +assign pyc_and_786 = (pyc_xor_188 & pyc_xor_515); +assign pyc_or_787 = (pyc_and_785 | pyc_and_786); +assign pyc_and_788 = (pyc_or_175 & pyc_xor_515); +assign pyc_or_789 = (pyc_or_787 | pyc_and_788); +assign pyc_xor_790 = (pyc_xor_784 ^ pyc_or_502); +assign pyc_xor_791 = (pyc_xor_790 ^ pyc_or_775); +assign pyc_and_792 = (pyc_xor_784 & pyc_or_502); +assign pyc_and_793 = (pyc_xor_784 & pyc_or_775); +assign pyc_or_794 = (pyc_and_792 | pyc_and_793); +assign pyc_and_795 = (pyc_or_502 & pyc_or_775); +assign pyc_or_796 = (pyc_or_794 | pyc_and_795); +assign pyc_xor_797 = (pyc_xor_206 ^ pyc_or_193); +assign pyc_xor_798 = (pyc_xor_797 ^ pyc_xor_533); +assign pyc_and_799 = (pyc_xor_206 & pyc_or_193); +assign pyc_and_800 = (pyc_xor_206 & pyc_xor_533); +assign pyc_or_801 = (pyc_and_799 | pyc_and_800); +assign pyc_and_802 = (pyc_or_193 & pyc_xor_533); +assign pyc_or_803 = (pyc_or_801 | pyc_and_802); +assign pyc_xor_804 = (pyc_xor_798 ^ pyc_or_520); +assign pyc_xor_805 = (pyc_xor_804 ^ pyc_or_789); +assign pyc_and_806 = (pyc_xor_798 & pyc_or_520); +assign pyc_and_807 = (pyc_xor_798 & pyc_or_789); +assign pyc_or_808 = (pyc_and_806 | pyc_and_807); +assign pyc_and_809 = (pyc_or_520 & pyc_or_789); +assign pyc_or_810 = (pyc_or_808 | pyc_and_809); +assign pyc_xor_811 = (pyc_xor_224 ^ pyc_or_211); +assign pyc_xor_812 = (pyc_xor_811 ^ pyc_xor_551); +assign pyc_and_813 = (pyc_xor_224 & pyc_or_211); +assign pyc_and_814 = (pyc_xor_224 & pyc_xor_551); +assign pyc_or_815 = (pyc_and_813 | pyc_and_814); +assign pyc_and_816 = (pyc_or_211 & pyc_xor_551); +assign pyc_or_817 = (pyc_or_815 | pyc_and_816); +assign pyc_xor_818 = (pyc_xor_812 ^ pyc_or_538); +assign pyc_xor_819 = (pyc_xor_818 ^ pyc_or_803); +assign pyc_and_820 = (pyc_xor_812 & pyc_or_538); +assign pyc_and_821 = (pyc_xor_812 & pyc_or_803); +assign pyc_or_822 = (pyc_and_820 | pyc_and_821); +assign pyc_and_823 = (pyc_or_538 & pyc_or_803); +assign pyc_or_824 = (pyc_or_822 | pyc_and_823); +assign pyc_xor_825 = (pyc_xor_242 ^ pyc_or_229); +assign pyc_xor_826 = (pyc_xor_825 ^ pyc_xor_569); +assign pyc_and_827 = (pyc_xor_242 & pyc_or_229); +assign pyc_and_828 = (pyc_xor_242 & pyc_xor_569); +assign pyc_or_829 = (pyc_and_827 | pyc_and_828); +assign pyc_and_830 = (pyc_or_229 & pyc_xor_569); +assign pyc_or_831 = (pyc_or_829 | pyc_and_830); +assign pyc_xor_832 = (pyc_xor_826 ^ pyc_or_556); +assign pyc_xor_833 = (pyc_xor_832 ^ pyc_or_817); +assign pyc_and_834 = (pyc_xor_826 & pyc_or_556); +assign pyc_and_835 = (pyc_xor_826 & pyc_or_817); +assign pyc_or_836 = (pyc_and_834 | pyc_and_835); +assign pyc_and_837 = (pyc_or_556 & pyc_or_817); +assign pyc_or_838 = (pyc_or_836 | pyc_and_837); +assign pyc_xor_839 = (pyc_xor_260 ^ pyc_or_247); +assign pyc_xor_840 = (pyc_xor_839 ^ pyc_xor_587); +assign pyc_and_841 = (pyc_xor_260 & pyc_or_247); +assign pyc_and_842 = (pyc_xor_260 & pyc_xor_587); +assign pyc_or_843 = (pyc_and_841 | pyc_and_842); +assign pyc_and_844 = (pyc_or_247 & pyc_xor_587); +assign pyc_or_845 = (pyc_or_843 | pyc_and_844); +assign pyc_xor_846 = (pyc_xor_840 ^ pyc_or_574); +assign pyc_xor_847 = (pyc_xor_846 ^ pyc_or_831); +assign pyc_and_848 = (pyc_xor_840 & pyc_or_574); +assign pyc_and_849 = (pyc_xor_840 & pyc_or_831); +assign pyc_or_850 = (pyc_and_848 | pyc_and_849); +assign pyc_and_851 = (pyc_or_574 & pyc_or_831); +assign pyc_or_852 = (pyc_or_850 | pyc_and_851); +assign pyc_xor_853 = (pyc_xor_278 ^ pyc_or_265); +assign pyc_xor_854 = (pyc_xor_853 ^ pyc_xor_605); +assign pyc_and_855 = (pyc_xor_278 & pyc_or_265); +assign pyc_and_856 = (pyc_xor_278 & pyc_xor_605); +assign pyc_or_857 = (pyc_and_855 | pyc_and_856); +assign pyc_and_858 = (pyc_or_265 & pyc_xor_605); +assign pyc_or_859 = (pyc_or_857 | pyc_and_858); +assign pyc_xor_860 = (pyc_xor_854 ^ pyc_or_592); +assign pyc_xor_861 = (pyc_xor_860 ^ pyc_or_845); +assign pyc_and_862 = (pyc_xor_854 & pyc_or_592); +assign pyc_and_863 = (pyc_xor_854 & pyc_or_845); +assign pyc_or_864 = (pyc_and_862 | pyc_and_863); +assign pyc_and_865 = (pyc_or_592 & pyc_or_845); +assign pyc_or_866 = (pyc_or_864 | pyc_and_865); +assign pyc_xor_867 = (pyc_xor_296 ^ pyc_or_283); +assign pyc_xor_868 = (pyc_xor_867 ^ pyc_xor_623); +assign pyc_and_869 = (pyc_xor_296 & pyc_or_283); +assign pyc_and_870 = (pyc_xor_296 & pyc_xor_623); +assign pyc_or_871 = (pyc_and_869 | pyc_and_870); +assign pyc_and_872 = (pyc_or_283 & pyc_xor_623); +assign pyc_or_873 = (pyc_or_871 | pyc_and_872); +assign pyc_xor_874 = (pyc_xor_868 ^ pyc_or_610); +assign pyc_xor_875 = (pyc_xor_874 ^ pyc_or_859); +assign pyc_and_876 = (pyc_xor_868 & pyc_or_610); +assign pyc_and_877 = (pyc_xor_868 & pyc_or_859); +assign pyc_or_878 = (pyc_and_876 | pyc_and_877); +assign pyc_and_879 = (pyc_or_610 & pyc_or_859); +assign pyc_or_880 = (pyc_or_878 | pyc_and_879); +assign pyc_xor_881 = (pyc_xor_314 ^ pyc_or_301); +assign pyc_xor_882 = (pyc_xor_881 ^ pyc_xor_641); +assign pyc_and_883 = (pyc_xor_314 & pyc_or_301); +assign pyc_and_884 = (pyc_xor_314 & pyc_xor_641); +assign pyc_or_885 = (pyc_and_883 | pyc_and_884); +assign pyc_and_886 = (pyc_or_301 & pyc_xor_641); +assign pyc_or_887 = (pyc_or_885 | pyc_and_886); +assign pyc_xor_888 = (pyc_xor_882 ^ pyc_or_628); +assign pyc_xor_889 = (pyc_xor_888 ^ pyc_or_873); +assign pyc_and_890 = (pyc_xor_882 & pyc_or_628); +assign pyc_and_891 = (pyc_xor_882 & pyc_or_873); +assign pyc_or_892 = (pyc_and_890 | pyc_and_891); +assign pyc_and_893 = (pyc_or_628 & pyc_or_873); +assign pyc_or_894 = (pyc_or_892 | pyc_and_893); +assign pyc_xor_895 = (pyc_xor_327 ^ pyc_or_319); +assign pyc_xor_896 = (pyc_xor_895 ^ pyc_xor_654); +assign pyc_xor_897 = (pyc_xor_896 ^ pyc_or_646); +assign pyc_xor_898 = (pyc_xor_897 ^ pyc_or_887); +assign pyc_xor_899 = (pyc_xor_679 ^ pyc_or_670); +assign pyc_xor_900 = (pyc_xor_693 ^ pyc_or_684); +assign pyc_xor_901 = (pyc_xor_707 ^ pyc_or_698); +assign pyc_xor_902 = (pyc_xor_721 ^ pyc_or_712); +assign pyc_xor_903 = (pyc_xor_735 ^ pyc_or_726); +assign pyc_xor_904 = (pyc_xor_749 ^ pyc_or_740); +assign pyc_xor_905 = (pyc_xor_763 ^ pyc_or_754); +assign pyc_xor_906 = (pyc_xor_777 ^ pyc_or_768); +assign pyc_xor_907 = (pyc_xor_791 ^ pyc_or_782); +assign pyc_xor_908 = (pyc_xor_805 ^ pyc_or_796); +assign pyc_xor_909 = (pyc_xor_819 ^ pyc_or_810); +assign pyc_xor_910 = (pyc_xor_833 ^ pyc_or_824); +assign pyc_xor_911 = (pyc_xor_847 ^ pyc_or_838); +assign pyc_xor_912 = (pyc_xor_861 ^ pyc_or_852); +assign pyc_xor_913 = (pyc_xor_875 ^ pyc_or_866); +assign pyc_xor_914 = (pyc_xor_889 ^ pyc_or_880); +assign pyc_xor_915 = (pyc_xor_898 ^ pyc_or_894); +assign pyc_and_916 = (pyc_xor_679 & pyc_or_670); +assign pyc_and_917 = (pyc_xor_693 & pyc_or_684); +assign pyc_and_918 = (pyc_xor_707 & pyc_or_698); +assign pyc_and_919 = (pyc_xor_721 & pyc_or_712); +assign pyc_and_920 = (pyc_xor_735 & pyc_or_726); +assign pyc_and_921 = (pyc_xor_749 & pyc_or_740); +assign pyc_and_922 = (pyc_xor_763 & pyc_or_754); +assign pyc_and_923 = (pyc_xor_777 & pyc_or_768); +assign pyc_and_924 = (pyc_xor_791 & pyc_or_782); +assign pyc_and_925 = (pyc_xor_805 & pyc_or_796); +assign pyc_and_926 = (pyc_xor_819 & pyc_or_810); +assign pyc_and_927 = (pyc_xor_833 & pyc_or_824); +assign pyc_and_928 = (pyc_xor_847 & pyc_or_838); +assign pyc_and_929 = (pyc_xor_861 & pyc_or_852); +assign pyc_and_930 = (pyc_xor_875 & pyc_or_866); +assign pyc_and_931 = (pyc_xor_889 & pyc_or_880); +assign pyc_and_932 = (pyc_xor_900 & pyc_and_916); +assign pyc_or_933 = (pyc_and_917 | pyc_and_932); +assign pyc_and_934 = (pyc_xor_902 & pyc_and_918); +assign pyc_or_935 = (pyc_and_919 | pyc_and_934); +assign pyc_and_936 = (pyc_xor_902 & pyc_xor_901); +assign pyc_and_937 = (pyc_xor_904 & pyc_and_920); +assign pyc_or_938 = (pyc_and_921 | pyc_and_937); +assign pyc_and_939 = (pyc_xor_904 & pyc_xor_903); +assign pyc_and_940 = (pyc_xor_906 & pyc_and_922); +assign pyc_or_941 = (pyc_and_923 | pyc_and_940); +assign pyc_and_942 = (pyc_xor_906 & pyc_xor_905); +assign pyc_and_943 = (pyc_xor_908 & pyc_and_924); +assign pyc_or_944 = (pyc_and_925 | pyc_and_943); +assign pyc_and_945 = (pyc_xor_908 & pyc_xor_907); +assign pyc_and_946 = (pyc_xor_910 & pyc_and_926); +assign pyc_or_947 = (pyc_and_927 | pyc_and_946); +assign pyc_and_948 = (pyc_xor_910 & pyc_xor_909); +assign pyc_and_949 = (pyc_xor_912 & pyc_and_928); +assign pyc_or_950 = (pyc_and_929 | pyc_and_949); +assign pyc_and_951 = (pyc_xor_912 & pyc_xor_911); +assign pyc_and_952 = (pyc_xor_914 & pyc_and_930); +assign pyc_or_953 = (pyc_and_931 | pyc_and_952); +assign pyc_and_954 = (pyc_xor_914 & pyc_xor_913); +assign pyc_and_955 = (pyc_and_939 & pyc_or_935); +assign pyc_or_956 = (pyc_or_938 | pyc_and_955); +assign pyc_and_957 = (pyc_and_939 & pyc_and_936); +assign pyc_and_958 = (pyc_and_945 & pyc_or_941); +assign pyc_or_959 = (pyc_or_944 | pyc_and_958); +assign pyc_and_960 = (pyc_and_945 & pyc_and_942); +assign pyc_and_961 = (pyc_and_951 & pyc_or_947); +assign pyc_or_962 = (pyc_or_950 | pyc_and_961); +assign pyc_and_963 = (pyc_and_951 & pyc_and_948); +assign pyc_and_964 = (pyc_and_957 & pyc_or_933); +assign pyc_or_965 = (pyc_or_956 | pyc_and_964); +assign pyc_and_966 = (pyc_and_963 & pyc_or_959); +assign pyc_or_967 = (pyc_or_962 | pyc_and_966); +assign pyc_and_968 = (pyc_and_963 & pyc_and_960); +assign pyc_and_969 = (pyc_and_968 & pyc_or_965); +assign pyc_or_970 = (pyc_or_967 | pyc_and_969); +assign pyc_and_971 = (pyc_and_960 & pyc_or_965); +assign pyc_or_972 = (pyc_or_959 | pyc_and_971); +assign pyc_and_973 = (pyc_and_936 & pyc_or_933); +assign pyc_or_974 = (pyc_or_935 | pyc_and_973); +assign pyc_and_975 = (pyc_and_942 & pyc_or_965); +assign pyc_or_976 = (pyc_or_941 | pyc_and_975); +assign pyc_and_977 = (pyc_and_948 & pyc_or_972); +assign pyc_or_978 = (pyc_or_947 | pyc_and_977); +assign pyc_and_979 = (pyc_and_954 & pyc_or_970); +assign pyc_or_980 = (pyc_or_953 | pyc_and_979); +assign pyc_and_981 = (pyc_xor_901 & pyc_or_933); +assign pyc_or_982 = (pyc_and_918 | pyc_and_981); +assign pyc_and_983 = (pyc_xor_903 & pyc_or_974); +assign pyc_or_984 = (pyc_and_920 | pyc_and_983); +assign pyc_and_985 = (pyc_xor_905 & pyc_or_965); +assign pyc_or_986 = (pyc_and_922 | pyc_and_985); +assign pyc_and_987 = (pyc_xor_907 & pyc_or_976); +assign pyc_or_988 = (pyc_and_924 | pyc_and_987); +assign pyc_and_989 = (pyc_xor_909 & pyc_or_972); +assign pyc_or_990 = (pyc_and_926 | pyc_and_989); +assign pyc_and_991 = (pyc_xor_911 & pyc_or_978); +assign pyc_or_992 = (pyc_and_928 | pyc_and_991); +assign pyc_and_993 = (pyc_xor_913 & pyc_or_970); +assign pyc_or_994 = (pyc_and_930 | pyc_and_993); +assign pyc_xor_995 = (pyc_xor_900 ^ pyc_and_916); +assign pyc_xor_996 = (pyc_xor_901 ^ pyc_or_933); +assign pyc_xor_997 = (pyc_xor_902 ^ pyc_or_982); +assign pyc_xor_998 = (pyc_xor_903 ^ pyc_or_974); +assign pyc_xor_999 = (pyc_xor_904 ^ pyc_or_984); +assign pyc_xor_1000 = (pyc_xor_905 ^ pyc_or_965); +assign pyc_xor_1001 = (pyc_xor_906 ^ pyc_or_986); +assign pyc_xor_1002 = (pyc_xor_907 ^ pyc_or_976); +assign pyc_xor_1003 = (pyc_xor_908 ^ pyc_or_988); +assign pyc_xor_1004 = (pyc_xor_909 ^ pyc_or_972); +assign pyc_xor_1005 = (pyc_xor_910 ^ pyc_or_990); +assign pyc_xor_1006 = (pyc_xor_911 ^ pyc_or_978); +assign pyc_xor_1007 = (pyc_xor_912 ^ pyc_or_992); +assign pyc_xor_1008 = (pyc_xor_913 ^ pyc_or_970); +assign pyc_xor_1009 = (pyc_xor_914 ^ pyc_or_994); +assign pyc_xor_1010 = (pyc_xor_915 ^ pyc_or_980); +assign pyc_concat_1011 = {pyc_xor_1010, pyc_xor_1009, pyc_xor_1008, pyc_xor_1007, pyc_xor_1006, pyc_xor_1005, pyc_xor_1004, pyc_xor_1003, pyc_xor_1002, pyc_xor_1001, pyc_xor_1000, pyc_xor_999, pyc_xor_998, pyc_xor_997, pyc_xor_996, pyc_xor_995, pyc_xor_899, pyc_xor_665, pyc_xor_655}; +assign pyc_comb_1012 = pyc_concat_1011; -assign PE_INT_WALLACE_DOT8_TREE_W19_sum = pyc_comb_903; +assign PE_INT_WALLACE_DOT8_TREE_W19_sum = pyc_comb_1012; endmodule diff --git a/designs/PE_INT/sim/run_all_wsl.sh b/designs/PE_INT/sim/run_all_wsl.sh index 8be7f64..670ebbc 100644 --- a/designs/PE_INT/sim/run_all_wsl.sh +++ b/designs/PE_INT/sim/run_all_wsl.sh @@ -32,9 +32,13 @@ python3 "$MODEL_GEN_SCRIPT" CASES=( "tc_mode2a_sanity" + "tc_mode2a_sanity_rand_timing" "tc_mode2b_sanity" + "tc_mode2b_sanity_rand_timing" "tc_mode2c_sanity" + "tc_mode2c_sanity_rand_timing" "tc_mode2d_sanity" + "tc_mode2d_sanity_rand_timing" "tc_mode_switch_random" ) diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v index fb2d901..effc909 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v @@ -17,7 +17,6 @@ module tc_mode2a_sanity_rand_timing; wire vld_out; integer i; - integer got; integer err; integer exp_count; localparam integer N_TX = 1000; @@ -59,7 +58,7 @@ module tc_mode2a_sanity_rand_timing; initial begin clk = 0; rst_n = 0; vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; exp_count = 0; sb_reset(); + err = 0; exp_count = 0; sb_reset(); if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin gen_dir = "tb_rtl/case/generated"; diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v index e875895..6d86e4f 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v @@ -17,7 +17,6 @@ module tc_mode2b_sanity_rand_timing; wire vld_out; integer i; - integer got; integer err; integer exp_count; localparam integer N_TX = 1000; @@ -59,7 +58,7 @@ module tc_mode2b_sanity_rand_timing; initial begin clk = 0; rst_n = 0; vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; exp_count = 0; sb_reset(); + err = 0; exp_count = 0; sb_reset(); if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin gen_dir = "tb_rtl/case/generated"; diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v index fd008a3..e9f4975 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v @@ -17,7 +17,6 @@ module tc_mode2c_sanity_rand_timing; wire vld_out; integer i; - integer got; integer err; integer exp_count; localparam integer N_TX = 1000; @@ -59,7 +58,7 @@ module tc_mode2c_sanity_rand_timing; initial begin clk = 0; rst_n = 0; vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; exp_count = 0; sb_reset(); + err = 0; exp_count = 0; sb_reset(); if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin gen_dir = "tb_rtl/case/generated"; diff --git a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v index 54be158..b33f4df 100644 --- a/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v +++ b/designs/PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v @@ -17,7 +17,6 @@ module tc_mode2d_sanity_rand_timing; wire vld_out; integer i; - integer got; integer err; integer exp_count; localparam integer N_TX = 1000; @@ -59,7 +58,7 @@ module tc_mode2d_sanity_rand_timing; initial begin clk = 0; rst_n = 0; vld = 0; mode = 0; a = 0; b = 0; b1 = 0; e1_a = 0; e1_b0 = 0; e1_b1 = 0; - got = 0; err = 0; exp_count = 0; sb_reset(); + err = 0; exp_count = 0; sb_reset(); if (!$value$plusargs("GEN_DIR=%s", gen_dir)) begin gen_dir = "tb_rtl/case/generated"; diff --git a/designs/PE_INT/tb_rtl/tb.f b/designs/PE_INT/tb_rtl/tb.f index 7311afc..b2ac05c 100644 --- a/designs/PE_INT/tb_rtl/tb.f +++ b/designs/PE_INT/tb_rtl/tb.f @@ -1,6 +1,10 @@ -+incdir+$PE_INT/tb_rtl/case -$PE_INT/tb_rtl/case/tc_mode2a_sanity.v -$PE_INT/tb_rtl/case/tc_mode2b_sanity.v -$PE_INT/tb_rtl/case/tc_mode2c_sanity.v -$PE_INT/tb_rtl/case/tc_mode2d_sanity.v -$PE_INT/tb_rtl/case/tc_mode_switch_random.v ++incdir+$PE_INT/tb_rtl/case +$PE_INT/tb_rtl/case/tc_mode2a_sanity.v +$PE_INT/tb_rtl/case/tc_mode2a_sanity_rand_timing.v +$PE_INT/tb_rtl/case/tc_mode2b_sanity.v +$PE_INT/tb_rtl/case/tc_mode2b_sanity_rand_timing.v +$PE_INT/tb_rtl/case/tc_mode2c_sanity.v +$PE_INT/tb_rtl/case/tc_mode2c_sanity_rand_timing.v +$PE_INT/tb_rtl/case/tc_mode2d_sanity.v +$PE_INT/tb_rtl/case/tc_mode2d_sanity_rand_timing.v +$PE_INT/tb_rtl/case/tc_mode_switch_random.v From 6f06b2767da7c02e2609021914fa4ff89c00071d Mon Sep 17 00:00:00 2001 From: HenryLee Date: Thu, 7 May 2026 20:40:58 +0800 Subject: [PATCH 09/10] fix(designs): use public PE_INT APIs Keep PE_INT on public PyCircuit APIs, record the latest regression evidence, and add reviewer/scope guardrails for future PE_INT changes. Co-authored-by: Cursor --- .cursor/agents/codereviewer.md | 16 ++++++++++++++++ .../.cursor/rules/pe-int-scope-boundary.mdc | 18 ++++++++++++++++++ designs/PE_INT/docs/regression_report.md | 6 +++++- designs/PE_INT/python/pe_int/decode.py | 8 ++------ designs/PE_INT/python/pe_int/lane_mac.py | 10 +++++----- designs/PE_INT/python/pe_int/top.py | 4 ++-- 6 files changed, 48 insertions(+), 14 deletions(-) create mode 100644 .cursor/agents/codereviewer.md create mode 100644 designs/PE_INT/.cursor/rules/pe-int-scope-boundary.mdc diff --git a/.cursor/agents/codereviewer.md b/.cursor/agents/codereviewer.md new file mode 100644 index 0000000..d025193 --- /dev/null +++ b/.cursor/agents/codereviewer.md @@ -0,0 +1,16 @@ +--- +name: codereviewer +description: Strict code review for bugs, regressions, spec mismatches, and missing tests. +model: gemini-3.1-pro +readonly: true +--- + +You are a strict senior code reviewer. + +Report findings first, ordered by severity. Focus on correctness, behavioral +regressions, spec-code-model-testcase mismatches, generated RTL risks, API +boundary violations, and missing or weak tests. + +For PE_INT work, cross-check `docs/spec.md`, `docs/design_spec.md`, PyCircuit +source, generated RTL, model behavior, and testcase coverage. Treat the known +`rst_n` framework limitation as non-blocking unless the user asks to revisit it. diff --git a/designs/PE_INT/.cursor/rules/pe-int-scope-boundary.mdc b/designs/PE_INT/.cursor/rules/pe-int-scope-boundary.mdc new file mode 100644 index 0000000..ff61592 --- /dev/null +++ b/designs/PE_INT/.cursor/rules/pe-int-scope-boundary.mdc @@ -0,0 +1,18 @@ +--- +description: Require user confirmation before editing files outside designs/PE_INT +alwaysApply: true +--- + +# PE_INT Scope Boundary + +When working on PE_INT tasks, do not modify files outside `designs/PE_INT/` +unless the user explicitly confirms that cross-tree change first. + +If a PE_INT issue appears to require PyCircuit framework changes, stop and ask +the user whether to: + +- file or update a framework issue, +- make a framework patch in the same branch, or +- keep the change documented as a known limitation. + +This rule does not block read-only inspection outside `designs/PE_INT/`. diff --git a/designs/PE_INT/docs/regression_report.md b/designs/PE_INT/docs/regression_report.md index c51f855..4554405 100644 --- a/designs/PE_INT/docs/regression_report.md +++ b/designs/PE_INT/docs/regression_report.md @@ -2,7 +2,11 @@ Date: 2026-05-07 -Git HEAD at run start: `1372963` +Git HEAD at run start: `c88b634` + +Working tree at run time included the public API cleanup for PE_INT +(`sext`/`zext`/`select`), the project-level `codereviewer` model configuration, +and the PE_INT scope-boundary rule. Scope: diff --git a/designs/PE_INT/python/pe_int/decode.py b/designs/PE_INT/python/pe_int/decode.py index 518379e..5add87c 100644 --- a/designs/PE_INT/python/pe_int/decode.py +++ b/designs/PE_INT/python/pe_int/decode.py @@ -7,18 +7,14 @@ def sext(value, bits: int): if hasattr(value, "sext"): return value.sext(width=bits) raw = wire_of(value) - if hasattr(raw, "sext"): - return raw.sext(width=bits) - return raw._sext(width=bits) + return raw.sext(width=bits) def zext(value, bits: int): if hasattr(value, "zext"): return value.zext(width=bits) raw = wire_of(value) - if hasattr(raw, "zext"): - return raw.zext(width=bits) - return raw._zext(width=bits) + return raw.zext(width=bits) def lane5(word, idx: int): diff --git a/designs/PE_INT/python/pe_int/lane_mac.py b/designs/PE_INT/python/pe_int/lane_mac.py index ac6f306..f67fa99 100644 --- a/designs/PE_INT/python/pe_int/lane_mac.py +++ b/designs/PE_INT/python/pe_int/lane_mac.py @@ -208,9 +208,9 @@ def shift_scale_x1_x2_x4(value, shift2b): DS §3.3: use 2-level muxed shift (x1/x2/x4), avoid barrel shifter. """ value_w = wire_of(value) - return wire_of(shift2b == 0)._select_internal( + return wire_of(shift2b == 0).select( value_w, - wire_of(shift2b == 1)._select_internal(value_w << 1, value_w << 2), + wire_of(shift2b == 1).select(value_w << 1, value_w << 2), ) @@ -219,9 +219,9 @@ def select_one_hot4(sel0, sel1, sel2, cand0, cand1, cand2, cand3): One-hot mode selection. Use muxes instead of boolean-masked multiplication so PyCircuit does not insert balancing registers in comb3. """ - lo_pair = wire_of(sel0)._select_internal(wire_of(cand0), wire_of(cand1)) - hi_pair = wire_of(sel2)._select_internal(wire_of(cand2), wire_of(cand3)) - return wire_of(sel0 | sel1)._select_internal(lo_pair, hi_pair) + lo_pair = wire_of(sel0).select(wire_of(cand0), wire_of(cand1)) + hi_pair = wire_of(sel2).select(wire_of(cand2), wire_of(cand3)) + return wire_of(sel0 | sel1).select(lo_pair, hi_pair) def sum_shift_pair(lo, hi, e1_a, e1_b, *, width: int = REDUCE_W): diff --git a/designs/PE_INT/python/pe_int/top.py b/designs/PE_INT/python/pe_int/top.py index a51356c..2f6fd51 100644 --- a/designs/PE_INT/python/pe_int/top.py +++ b/designs/PE_INT/python/pe_int/top.py @@ -145,8 +145,8 @@ def build( # reg3/output commit: vld_out/out0/out1 from the same commit boundary. out1 = domain.state(width=OUT1_W, reset_value=0, name="pe_int_out1") - out1_commit = wire_of(s2_vld)._select_internal( - wire_of(s2_is_2a)._select_internal(wire_of(out1), wire_of(c3_out1)), + out1_commit = wire_of(s2_vld).select( + wire_of(s2_is_2a).select(wire_of(out1), wire_of(c3_out1)), wire_of(out1), ) out1.set(out1_commit) From ad07aa3dbdf2fd82ab354be30f64a665fe475306 Mon Sep 17 00:00:00 2001 From: HenryLee Date: Tue, 26 May 2026 20:01:28 +0800 Subject: [PATCH 10/10] fix(designs): bound PE_INT multiplier accumulation Define scenario-derived width contracts in the PE_INT flow and design spec, then bound the shift/add multiplier fallback accumulator to exact product width. Co-authored-by: Cursor --- .../skills/pe-int-pycircuiteval-flow/SKILL.md | 65 +++++++++++--- .../PE_INT/docs/circuit_optimizer_report.md | 13 +-- designs/PE_INT/docs/design_spec.md | 87 ++++++++++++++++--- designs/PE_INT/docs/regression_report.md | 14 +-- designs/PE_INT/python/pe_int/lane_mac.py | 5 +- 5 files changed, 147 insertions(+), 37 deletions(-) diff --git a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md index 733c2fe..639a6d1 100644 --- a/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md +++ b/designs/PE_INT/.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md @@ -67,38 +67,77 @@ Required content: 2. Define low-level module contracts for basic components such as `MUL`, `ADD`, `SHIFTER`, `MUX`, `DEMUX`, D flip-flops/registers, comparators, counters, valid/ready or backpressure blocks, and FSMs when they exist. -3. For every circuit component, state input/output bit widths, signedness, - latency/register boundary, reset behavior if stateful, and overflow/truncation - contract. Do not add arbitrary margin widths. -4. Specify intended structures/topologies, for example Booth multiplier, +3. Derive datapath widths from functional scenarios before selecting topology + or writing implementation structure. The design spec must first derive value + ranges and representation widths for every scenario/mode/transaction type, + then map those widths onto circuit resources. +4. For each functional scenario / mode / transaction type, derive the value + range and representation width of every datapath value before topology + selection: + - source input fields, decoded operands, constants, counters, addresses, + tags, masks, predicates, and control-selected data values + - operation results for arithmetic, logical, comparison, shift, concatenate, + slice, pack/unpack, encode/decode, lookup, and mux/merge operations + - chained-operation outputs, including temporary values that feed later + operations in the same cycle or across pipeline stages + - accumulation, reduction, aggregation, queue/FIFO occupancy, pointer, + index, and state-update values when applicable + - final architectural outputs, committed state, memory write data/address, + and externally visible status/control outputs +5. For each derived value, record signedness or encoding domain, legal value + range or legal value set when derivable, required bit width, and whether the + width is exact, shared-resource maximum, encoded, one-hot, pointer/index + width, or protocol-defined. +6. Build a scenario-to-resource mapping. For every shared datapath resource + such as a multiplier, adder, accumulator, reducer, shifter, mux, register, + memory port, queue counter, pointer, tag path, or pipeline stage, define the + hardware width as the maximum required width across all mapped scenarios. + Do not size shared hardware from only the first or simplest scenario. +7. Define extension and narrowing policies at every resource boundary: + sign-extension, zero-extension, alignment shift, lane packing, masking, + explicit slice, mathematically safe truncation, saturation, wrapping, + clipping, or error/overflow handling. Any truncation must be justified by + the source-spec range or by an explicit user/optimizer-approved structural + policy. +8. For every circuit component and shared datapath resource, state the + scenario-derived width contract, including input/output widths, signedness, + architecturally relevant intermediate widths, latency/register boundary, + reset behavior if stateful, and overflow/truncation contract. Do not add + arbitrary margin widths. Extra bits are allowed only when derived from value + range, term count, shift amount, shared-resource maximum width, encoding, or + a documented rounding/saturation/truncation policy. +9. Topology selection must not decide arithmetic width. Booth, Wallace, Dadda, + prefix adder, ripple adder, shift/add, or other implementation choices can + only implement the already-derived width contract. +10. Specify intended structures/topologies, for example Booth multiplier, compressor tree, carry-lookahead/prefix/ripple adder, mux tree, shifter style, pipeline register placement, and whether a block is pure combinational or stateful. -5. Describe bus routing explicitly: how buses are sliced, packed, muxed, +11. Describe bus routing explicitly: how buses are sliced, packed, muxed, demuxed, sign/zero-extended, shifted, and merged across pipeline stages. -6. For backpressure or flow-control blocks, define ready/valid behavior, stall +12. For backpressure or flow-control blocks, define ready/valid behavior, stall propagation, skid/hold behavior, and what state is allowed to update during stalls. -7. For FSMs, list states, transition conditions, outputs per state, reset state, +13. For FSMs, list states, transition conditions, outputs per state, reset state, and illegal-state handling. -8. Include typical scenario waveform diagrams showing the protocol timing, +14. Include typical scenario waveform diagrams showing the protocol timing, latency convention, valid/data alignment, reset behavior, and mode-specific output stability requirements. -9. If `docs/spec.md` does not specify a structural topology, mark that item as +15. If `docs/spec.md` does not specify a structural topology, mark that item as `Unspecified by source spec` in `design_spec.md`. Do not infer topology from prior chat history, generated RTL, existing implementation, or reviewer comments. -10. If a structural topology is required for implementation or review, require +16. If a structural topology is required for implementation or review, require either an upstream `docs/spec.md` update or an explicit user-approved structural-policy source before generating it into `design_spec.md`. A documented Circuit Optimizer pass may be used as this source, but its selections must be labeled as optimizer decisions rather than source-spec contracts. -11. For every optimizer-selected topology, include implementation status: +17. For every optimizer-selected topology, include implementation status: `Planned`, `Implemented`, `Partially implemented`, or `Deferred`. -12. For each topology status, include evidence pointers to PyCircuit symbols, +18. For each topology status, include evidence pointers to PyCircuit symbols, generated RTL modules/signals, reports, or deferred-risk notes. -13. Do not state a topology as implemented if the optimizer report or generated +19. Do not state a topology as implemented if the optimizer report or generated RTL shows it is deferred or only partially implemented. ### Step A.2: Circuit Optimizer Topology Selection diff --git a/designs/PE_INT/docs/circuit_optimizer_report.md b/designs/PE_INT/docs/circuit_optimizer_report.md index 08f1dd1..89fa13f 100644 --- a/designs/PE_INT/docs/circuit_optimizer_report.md +++ b/designs/PE_INT/docs/circuit_optimizer_report.md @@ -118,10 +118,13 @@ Inputs: ### Multiplier Deferred Note Current multiplier implementation is functionally correct and natural-width with -sign-correction behavior, but does not yet provide a fully explicit radix-4 -Booth structural realization for all S8-involved products in generated RTL. -This item is deferred to a follow-up structural iteration with synthesis-backed -evidence (`needs-synthesis / deferred structural improvement`). +sign-correction behavior. Its shift/add/sub fallback product accumulator is +bounded to the exact product width derived from each operand pair; Dot8 +term-count guard bits are added only in the reduction stage. The implementation +does not yet provide a fully explicit radix-4 Booth structural realization for +all S8-involved products in generated RTL. This item is deferred to a follow-up +structural iteration with synthesis-backed evidence (`needs-synthesis / +deferred structural improvement`). ### Rationale @@ -224,7 +227,7 @@ Keep-current evidence: | Topology Item | Status | Evidence | |---|---|---| -| Multiplier | `Partially implemented / Deferred` | PyCircuit uses natural-width signed shift/add/sub style product generation. Explicit radix-4 Booth for S8-involved products remains deferred until synthesis/timing/area evidence justifies the structural rewrite. | +| Multiplier | `Partially implemented / Deferred` | PyCircuit uses natural-width signed shift/add/sub style product generation with exact-product-width bounded fallback accumulation. Explicit radix-4 Booth for S8-involved products remains deferred until synthesis/timing/area evidence justifies the structural rewrite. | | Dot8 Wallace reducer | `Implemented` | `PE_INT_WALLACE_DOT8_TREE_W19` and `PE_INT_WALLACE_DOT8_TREE_W16` generated modules are explicit compressor/prefix gate structures; no generic `+`/`*` operator is present in the reducer modules. | | Final CPA | `Implemented` | `brent_kung_cpa_truncated()` is used for reducer final sums and mode-2c low/high merge; generated RTL shows bit-level prefix carry logic. | | Mode2c shifter/merge | `Implemented` | Generated RTL uses bounded shift-by-0/1/2 plus muxing, then explicit prefix CPA merge. | diff --git a/designs/PE_INT/docs/design_spec.md b/designs/PE_INT/docs/design_spec.md index 6a979e1..3267bdf 100644 --- a/designs/PE_INT/docs/design_spec.md +++ b/designs/PE_INT/docs/design_spec.md @@ -1,14 +1,14 @@ # PE_INT Design Spec -Version: v0.8 +Version: v0.9 Generated from: `docs/spec.md` baseline v2.0.6 Generation rule: `.cursor/skills/pe-int-pycircuiteval-flow/SKILL.md` This document is the structure-first design spec derived from `docs/spec.md`. -It describes low-level circuit contracts, widths, bus routing, pipeline -boundaries, and protocol timing. Topologies not stated by the source spec are -first marked as `Unspecified by source spec`. Concrete topology choices may then -be added in an optimizer-owned section with explicit provenance from an +It describes low-level circuit contracts, scenario-derived widths, bus routing, +pipeline boundaries, and protocol timing. Topologies not stated by the source +spec are first marked as `Unspecified by source spec`. Concrete topology choices +may then be added in an optimizer-owned section with explicit provenance from an independent Circuit Optimizer sub-agent. --- @@ -22,11 +22,13 @@ Rules: 1. Business modes (`2a/2b/2c/2d`) share one fixed-latency pipeline. 2. Circuit modules are described before mode-specific parameter mapping. -3. Widths use the minimum lossless contract derivable from `docs/spec.md`. -4. Arbitrary operand or result margin widths are forbidden. -5. Any topology not stated by `docs/spec.md` remains `Unspecified by source +3. Widths are first derived from functional scenarios and value ranges. +4. Shared datapath resources use the maximum required width across all mapped + scenarios. +5. Arbitrary operand or result margin widths are forbidden. +6. Any topology not stated by `docs/spec.md` remains `Unspecified by source spec` in source-derived sections. -6. Optimizer-selected topologies are design decisions, not source-spec +7. Optimizer-selected topologies are design decisions, not source-spec contracts, and must be labeled with sub-agent provenance, pass number, and objective. @@ -93,6 +95,62 @@ Mode DEMUX: - The mode field selects output branch results at the aligned merge stage. - All in-flight transactions preserve FIFO order. +### 3.4 Scenario-Derived Width and Resource Mapping + +Datapath widths are derived from functional scenarios before topology selection. +Topology choices only implement these width contracts; they do not decide +arithmetic width. + +Decode value ranges: + +| Value | Representation | Width | Signed | Legal Range | +|-------|----------------|-------|--------|-------------| +| `S8` | two's complement | 8 | yes | `[-128, 127]` | +| `S4` | two's complement | 4 | yes | `[-8, 7]` | +| `S5` | two's complement | 5 | yes | `[-16, 15]` | +| `E1` | unsigned scale bit | 1 | no | `{0, 1}` | + +For an `N`-bit by `M`-bit signed multiply, the exact full product width is +`N+M`. Dot8 reduction then adds the term-count guard width: + +`dot8_sum_width = product_width + ceil(log2(8)) = product_width + 3` + +Scenario-derived operation widths: + +| Scenario Value | Inputs | Derived Width | Shared Resource Contract | +|----------------|--------|---------------|--------------------------| +| `P2A` | S8*S8 | 16 | exact product width | +| `P2B0/P2B1` | S8*S4 | 12 | exact product width | +| `P2C0/P2C1` | S5*S5 | 10 | exact product width | +| `P2D0/P2D1` | S8*S5 | 13 | exact product width | +| `R2A` | 8 x P16 | 19 | out0 shared width 19 | +| `R2B0` | 8 x P12 | 15 | sign-extend into out0 shared width 19 | +| `R2B1` | 8 x P12 | 15 | sign-extend into out1 shared width 16 | +| `R2C0_LO/HI` | 8 x P10 | 13 before E1 scaling | merge into out0 shared width 19 | +| `R2C1_LO/HI` | 8 x P10 | 13 before E1 scaling | merge into out1 shared width 16 | +| `R2D0` | 8 x P13 | 16 | sign-extend into out0 shared width 19 | +| `R2D1` | 8 x P13 | 16 | out1 shared width 16 | + +Shared-resource mapping: + +| Resource | Mapped Scenarios | Hardware Width | +|----------|------------------|----------------| +| product generator | one element-pair multiply | exact product width `N+M` | +| out0 reduction / merge path | 2a, 2b0, 2c0, 2d0 | max shared width 19 | +| out1 reduction / merge path | 2b1, 2c1, 2d1 | max shared width 16 | +| output mux `out0` | 2a, 2b, 2c, 2d | 19 | +| output mux `out1` | 2b, 2c, 2d plus 2a hold | 16 | + +Resource boundary policies: + +- Narrower mode results entering a wider shared resource are sign-extended. +- The single-product generator does not include Dot8 guard bits; guard bits are + added at the reduction resource. +- Results leaving a shared resource must either preserve the required width or + use an explicitly documented, mathematically safe truncation policy. +- No arbitrary guard bits are allowed beyond the scenario-derived width or the + maximum width required by mapped shared-resource scenarios. + --- ## 4. Low-Level Circuit Components @@ -117,6 +175,11 @@ Rules: - Do not implement `S8*S8`, `S8*S4`, `S8*S5`, or `S5*S5` by first extending operands to `out0` or `out1` width. - The signed product is extended only when entering a wider reduction path. +- If a shift/add/sub multiplier is used as the current deferred topology + fallback, its partial rows, temporary product accumulator, correction rows, + and final product boundary are bounded to the exact product width `N+M`. + Any carry above `N+M` is outside the single-product contract and must not leak + into Dot8 reduction. - Multiplier topology: `Unspecified by source spec`. ### 4.2 Reduction @@ -311,7 +374,7 @@ Iteration budget: | Block | Selection | Implementation Status | Evidence Pointer | Risk / Next Evidence | Provenance | |---|---|---|---|---|---| | Pipeline placement | Fixed `input -> comb0 -> reg0 -> comb1 -> reg1 -> comb2 -> reg2 -> comb3 -> reg3/output`, `L=4`. | Implemented | `python/pe_int/top.py::build()`, generated `rtl/build/pe_int.v` register boundaries. | Confirm with RTL regression latency checks. | `Optimizer-subagent-selected, pass 0`; latency from `docs/spec.md`. | -| Signed multipliers | Natural-width signed products. Radix-4 Booth remains the S8-involved structural optimization intent, but current RTL uses signed shift/add/sub style product generation. | Partially implemented / Deferred | `python/pe_int/lane_mac.py::booth_mul_signed()`, `_mul_signed_twos_complement()`, generated multiplier add/sub chains in `rtl/build/pe_int.v`. | Explicit radix-4 Booth is deferred until synthesis/timing/area evidence justifies the structural rewrite. | `Optimizer-subagent-selected, pass 0`; post-build status audit. | +| Signed multipliers | Natural-width signed products. Radix-4 Booth remains the S8-involved structural optimization intent, but current RTL uses signed shift/add/sub style product generation. The fallback accumulator is bounded to exact product width. | Partially implemented / Deferred | `python/pe_int/lane_mac.py::booth_mul_signed()`, `_mul_signed_twos_complement()`, `_mul_unsigned_rows()`, generated multiplier add/sub chains in `rtl/build/pe_int.v`. | Explicit radix-4 Booth is deferred until synthesis/timing/area evidence justifies the structural rewrite. | `Optimizer-subagent-selected, pass 0`; post-build status audit; scenario-derived width rule. | | Dot8 reduction | Wallace-style carry-save compression tree using `CMPE42`, `FA`, and `HA`, followed by one final CPA. | Implemented | `python/pe_int/lane_mac.py::_wallace_dot8_reduce()`, `rtl/build/pe_int_wallace_dot8_tree_w16.v`, `rtl/build/pe_int_wallace_dot8_tree_w19.v`. | STA required for real timing depth. | `Optimizer-subagent-selected, pass 0`; pass 1 terminal carry policy retained. | | Final CPA | Brent-Kung-style prefix CPA for W16/W19 reductions and mode-2c low/high merge. | Implemented | `python/pe_int/lane_mac.py::brent_kung_cpa_truncated()`, `sum_shift_pair()`, generated prefix-style RTL. | Synthesis may remap; next evidence is mapped timing/netlist. | `Optimizer-subagent-selected, pass 0`; pass 1 mode-2c merge fix. | | Mode 2c shifter | Fixed shift-by-0/1/2 using wire shifts plus muxing before final CPA. | Implemented | `python/pe_int/lane_mac.py::shift_scale_x1_x2_x4()`, generated shift/mux RTL in `rtl/build/pe_int.v`. | Check comb3 timing with STA. | `Optimizer-subagent-selected, pass 0`. | @@ -392,8 +455,8 @@ collect: 4. Input-pin to first-register logic cone estimate; confirm `<= 8`. 5. Per-stage logic-depth estimate, especially multiplier stage and final CPA/mux stage. -6. Width audit for product, sign extension, shift, carry-save vectors, final - CPA, and top-level outputs. +6. Width audit for product, shift/add multiplier fallback accumulator, sign + extension, shift, carry-save vectors, final CPA, and top-level outputs. 7. Mux-depth audit for mode output selection and mode-2a `out1` hold. 8. Functional regression results for all modes and back-to-back mode switching. 9. Synthesis timing/area/power reports when available; otherwise use RTL proxy diff --git a/designs/PE_INT/docs/regression_report.md b/designs/PE_INT/docs/regression_report.md index 4554405..21187aa 100644 --- a/designs/PE_INT/docs/regression_report.md +++ b/designs/PE_INT/docs/regression_report.md @@ -1,12 +1,13 @@ # PE_INT Regression Report -Date: 2026-05-07 +Date: 2026-05-26 -Git HEAD at run start: `c88b634` +Git HEAD at run start: `6f06b27` -Working tree at run time included the public API cleanup for PE_INT -(`sext`/`zext`/`select`), the project-level `codereviewer` model configuration, -and the PE_INT scope-boundary rule. +Working tree at run time included the scenario-derived width-rule update, +formal `design_spec.md` clarification for exact-product-width bounded +shift/add multiplier fallback accumulation, and the matching PyCircuit +`_mul_unsigned_rows()` accumulator bound. Scope: @@ -23,6 +24,9 @@ Known deferred item: limitation for this run. - Explicit radix-4 Booth structural multiplier implementation for S8-involved products remains deferred pending synthesis/timing/area evidence. +- Current shift/add/sub multiplier fallback is bounded to exact product width; + Dot8 guard bits are added in reduction, not inside the single-product + generator. ## Commands diff --git a/designs/PE_INT/python/pe_int/lane_mac.py b/designs/PE_INT/python/pe_int/lane_mac.py index f67fa99..ba34a59 100644 --- a/designs/PE_INT/python/pe_int/lane_mac.py +++ b/designs/PE_INT/python/pe_int/lane_mac.py @@ -34,8 +34,9 @@ def _mul_unsigned_rows(lhs, rhs, *, width: int): acc = zero for bit_idx in range(rhs_w.width): row = wire_of(zext(lhs_w, width) << bit_idx)[0:width] - acc = acc + wire_of(rhs_w[bit_idx : bit_idx + 1]).select(row, zero) - return wire_of(acc)[0:width] + selected_row = wire_of(rhs_w[bit_idx : bit_idx + 1]).select(row, zero) + acc = wire_of(acc + selected_row)[0:width] + return acc def _mul_signed_twos_complement(lhs, rhs):