diff --git a/src/striga/x86/control.py b/src/striga/x86/control.py
index 5d58f03..c665bf0 100644
--- a/src/striga/x86/control.py
+++ b/src/striga/x86/control.py
@@ -393,6 +393,31 @@ def syscall(sem: Semantics):
     return [Successor(sem.insn.address, sem.const64(fallthrough))]
 
 
+@semantic
+def stc(sem: Semantics):
+    sem.flag_write("cf", sem.i1.constant(1))
+
+
+@semantic
+def clc(sem: Semantics):
+    sem.flag_write("cf", sem.i1.constant(0))
+
+
+@semantic
+def int_(sem: Semantics):
+    sem.ir.ret_void()
+    return []
+
+
+@semantic
+def cmc(sem: Semantics):
+    sem.flag_write("cf", bool_not(sem, sem.flag_read("cf")))
+
+
+@semantic
+def int3(sem: Semantics):
+    sem.ir.ret_void()
+    return []
 @semantic
 def nop(sem: Semantics):
     pass
@@ -401,3 +426,16 @@ def nop(sem: Semantics):
 @semantic
 def pause(sem: Semantics):
     pass
+@semantic
+def lfence(sem: Semantics):
+    pass
+
+
+@semantic
+def mfence(sem: Semantics):
+    pass
+
+
+@semantic
+def sfence(sem: Semantics):
+    pass
diff --git a/src/striga/x86/data.py b/src/striga/x86/data.py
index 99ab850..996511c 100644
--- a/src/striga/x86/data.py
+++ b/src/striga/x86/data.py
@@ -1,5 +1,5 @@
 from capstone import CS_OP_REG
-
+from llvm import lookup_intrinsic_id
 from ..semantics import FLAGS, Semantics, semantic
 
 
@@ -148,6 +148,20 @@ def cqo(sem: Semantics):
     sem.reg_write("rdx", sem.ir.ashr(rax, sem.const64(63)))
 
 
+@semantic
+def bswap(sem: Semantics):
+    op = sem.insn.operands[0]
+
+    if op.size == 2:
+        full, _, _ = sem.subregs[sem.reg_name(op.reg)]
+        value = sem.ir.trunc(sem.reg_read(full), sem.i32)
+    else:
+        value = sem.op_read(0)
+
+    intrinsic = sem.module.get_intrinsic_declaration(lookup_intrinsic_id("llvm.bswap"), [value.type])
+    result = sem.ir.call(intrinsic, [value])
+    sem.op_write(0, sem.resize_int(result, sem.i16) if op.size == 2 else result)
+
 @semantic
 def xchg(sem: Semantics):
     src = sem.op_read(1)