diff --git a/SECURITY.md b/SECURITY.md
new file mode 100644
index 000000000..034e84803
--- /dev/null
+++ b/SECURITY.md
@@ -0,0 +1,21 @@
+# Security Policy
+
+## Supported Versions
+
+Use this section to tell people about which versions of your project are
+currently being supported with security updates.
+
+| Version | Supported |
+| ------- | ------------------ |
+| 5.1.x | :white_check_mark: |
+| 5.0.x | :x: |
+| 4.0.x | :white_check_mark: |
+| < 4.0 | :x: |
+
+## Reporting a Vulnerability
+
+Use this section to tell people how to report a vulnerability.
+
+Tell them where to go, how often they can expect to get an update on a
+reported vulnerability, what to expect if the vulnerability is accepted or
+declined, etc.
diff --git a/docs/IHP_OpenPDK_eSim.md b/docs/IHP_OpenPDK_eSim.md
new file mode 100644
index 000000000..541fd0a58
--- /dev/null
+++ b/docs/IHP_OpenPDK_eSim.md
@@ -0,0 +1,52 @@
+# Integration of IHP OpenPDK with eSim
+
+## Overview
+
+This contribution demonstrates the integration of the IHP OpenPDK with eSim
+to enable CMOS circuit design and simulation using open-source EDA tools.
+
+## Objective
+
+- Integrate IHP OpenPDK MOSFET SPICE models with eSim
+- Design and simulate a CMOS inverter
+- Perform DC sweep and transient analysis
+- Validate inverter switching behavior
+
+## Tools Used
+
+- eSim (KiCad + NgSpice)
+- IHP OpenPDK
+- NgSpice
+
+## Circuit Implemented
+
+- CMOS Inverter using IHP NMOS and PMOS models
+- Supply voltage: 1.8V
+
+## Simulations Performed
+
+### Transient Analysis
+
+- `.tran 0.1ns 20ns`
+- Verified correct logical inversion
+
+### DC Sweep Analysis
+
+- `.dc VIN 0 1.8 0.01`
+- Verified voltage transfer characteristics
+
+## Results
+
+- Correct inverter operation observed
+- Threshold voltage near mid-supply
+- Stable transient and DC behavior
+
+## Notes
+
+- Absolute paths were used for SPICE model inclusion
+- Convergence issues resolved by reducing timestep
+
+## Report and Demo
+
+The detailed report and demonstration video are provided via links
+in the corresponding GitHub Pull Request.
diff --git a/library/SubcircuitLibrary/54f64/3_and-cache.lib b/library/SubcircuitLibrary/54f64/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/54f64/3_and.cir b/library/SubcircuitLibrary/54f64/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/54f64/3_and.cir.out b/library/SubcircuitLibrary/54f64/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/54f64/3_and.pro b/library/SubcircuitLibrary/54f64/3_and.pro
new file mode 100644
index 000000000..06813ca78
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 19:54:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/54f64/3_and.sch b/library/SubcircuitLibrary/54f64/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/54f64/3_and.sub b/library/SubcircuitLibrary/54f64/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/54f64/3_and_Previous_Values.xml b/library/SubcircuitLibrary/54f64/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/54f64/4_and-cache.lib b/library/SubcircuitLibrary/54f64/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/54f64/4_and-rescue.lib b/library/SubcircuitLibrary/54f64/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/54f64/4_and.cir b/library/SubcircuitLibrary/54f64/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/54f64/4_and.cir.out b/library/SubcircuitLibrary/54f64/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/54f64/4_and.pro b/library/SubcircuitLibrary/54f64/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/54f64/4_and.sch b/library/SubcircuitLibrary/54f64/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/54f64/4_and.sub b/library/SubcircuitLibrary/54f64/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/54f64/4_and_Previous_Values.xml b/library/SubcircuitLibrary/54f64/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/54f64/54f64-cache.lib b/library/SubcircuitLibrary/54f64/54f64-cache.lib
new file mode 100644
index 000000000..8c472fe4b
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/54f64-cache.lib
@@ -0,0 +1,117 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/54f64/54f64.cir b/library/SubcircuitLibrary/54f64/54f64.cir
new file mode 100644
index 000000000..5096a65ab
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/54f64.cir
@@ -0,0 +1,18 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\54f64\54f64.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/22/25 13:59:39
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U6 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U2-Pad1_ d_and
+X1 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U2-Pad2_ 3_and
+U5 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad1_ d_and
+U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_nor
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_nor
+U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad8_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT
+X2 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad1_ Net-_U4-Pad2_ 4_and
+
+.end
diff --git a/library/SubcircuitLibrary/54f64/54f64.cir.out b/library/SubcircuitLibrary/54f64/54f64.cir.out
new file mode 100644
index 000000000..61545f26c
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/54f64.cir.out
@@ -0,0 +1,36 @@
+* c:\fossee\esim\library\subcircuitlibrary\54f64\54f64.cir
+
+.include 4_and.sub
+.include 3_and.sub
+* u6 net-_u1-pad3_ net-_u1-pad2_ net-_u2-pad1_ d_and
+x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u2-pad2_ 3_and
+* u5 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad1_ d_and
+* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_nor
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_nor
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad8_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port
+x2 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad1_ net-_u4-pad2_ 4_and
+a1 [net-_u1-pad3_ net-_u1-pad2_ ] net-_u2-pad1_ u6
+a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad1_ u5
+a3 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4
+a4 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
+a5 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad8_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 250e-03 10e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/54f64/54f64.pro b/library/SubcircuitLibrary/54f64/54f64.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/54f64.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/54f64/54f64.sch b/library/SubcircuitLibrary/54f64/54f64.sch
new file mode 100644
index 000000000..6145d3bd3
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/54f64.sch
@@ -0,0 +1,366 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:54f64-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U6
+U 1 1 6857B47E
+P 3750 2450
+F 0 "U6" H 3750 2450 60 0000 C CNN
+F 1 "d_and" H 3800 2550 60 0000 C CNN
+F 2 "" H 3750 2450 60 0000 C CNN
+F 3 "" H 3750 2450 60 0000 C CNN
+ 1 3750 2450
+ 0 1 1 0
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 6857B510
+P 3100 3550
+F 0 "X1" H 3200 3500 60 0000 C CNN
+F 1 "3_and" H 3250 3700 60 0000 C CNN
+F 2 "" H 3100 3550 60 0000 C CNN
+F 3 "" H 3100 3550 60 0000 C CNN
+ 1 3100 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 6857B571
+P 5300 3400
+F 0 "U5" H 5300 3400 60 0000 C CNN
+F 1 "d_and" H 5350 3500 60 0000 C CNN
+F 2 "" H 5300 3400 60 0000 C CNN
+F 3 "" H 5300 3400 60 0000 C CNN
+ 1 5300 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L d_nor U4
+U 1 1 6857B59C
+P 4550 4300
+F 0 "U4" H 4550 4300 60 0000 C CNN
+F 1 "d_nor" H 4600 4400 60 0000 C CNN
+F 2 "" H 4550 4300 60 0000 C CNN
+F 3 "" H 4550 4300 60 0000 C CNN
+ 1 4550 4300
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U2
+U 1 1 6857B5EF
+P 3900 4300
+F 0 "U2" H 3900 4300 60 0000 C CNN
+F 1 "d_nor" H 3950 4400 60 0000 C CNN
+F 2 "" H 3900 4300 60 0000 C CNN
+F 3 "" H 3900 4300 60 0000 C CNN
+ 1 3900 4300
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U3
+U 1 1 6857B626
+P 4150 5450
+F 0 "U3" H 4150 5450 60 0000 C CNN
+F 1 "d_nor" H 4200 5550 60 0000 C CNN
+F 2 "" H 4150 5450 60 0000 C CNN
+F 3 "" H 4150 5450 60 0000 C CNN
+ 1 4150 5450
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 4850 3450 4650 3450
+Wire Wire Line
+ 4650 3450 4650 3850
+Wire Wire Line
+ 4550 2850 4550 3850
+Wire Wire Line
+ 3800 2900 4000 2900
+Wire Wire Line
+ 4000 2900 4000 3850
+Wire Wire Line
+ 3600 3500 3900 3500
+Wire Wire Line
+ 3900 3500 3900 3850
+Wire Wire Line
+ 3950 4750 3950 4950
+Wire Wire Line
+ 3950 4950 4150 4950
+Wire Wire Line
+ 4150 4950 4150 5000
+Wire Wire Line
+ 4600 4750 4600 4950
+Wire Wire Line
+ 4600 4950 4250 4950
+Wire Wire Line
+ 4250 4950 4250 5000
+$Comp
+L PORT U1
+U 1 1 6857B6DC
+P 4350 1150
+F 0 "U1" H 4400 1250 30 0000 C CNN
+F 1 "PORT" H 4350 1150 30 0000 C CNN
+F 2 "" H 4350 1150 60 0000 C CNN
+F 3 "" H 4350 1150 60 0000 C CNN
+ 1 4350 1150
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6857B85D
+P 3550 1350
+F 0 "U1" H 3600 1450 30 0000 C CNN
+F 1 "PORT" H 3550 1350 30 0000 C CNN
+F 2 "" H 3550 1350 60 0000 C CNN
+F 3 "" H 3550 1350 60 0000 C CNN
+ 2 3550 1350
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6857B8B4
+P 4000 1350
+F 0 "U1" H 4050 1450 30 0000 C CNN
+F 1 "PORT" H 4000 1350 30 0000 C CNN
+F 2 "" H 4000 1350 60 0000 C CNN
+F 3 "" H 4000 1350 60 0000 C CNN
+ 3 4000 1350
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 3550 1600 3750 1600
+Wire Wire Line
+ 3750 1600 3750 2000
+Wire Wire Line
+ 4000 1600 3850 1600
+Wire Wire Line
+ 3850 1600 3850 2000
+$Comp
+L PORT U1
+U 4 1 6857B9B4
+P 2400 3150
+F 0 "U1" H 2450 3250 30 0000 C CNN
+F 1 "PORT" H 2400 3150 30 0000 C CNN
+F 2 "" H 2400 3150 60 0000 C CNN
+F 3 "" H 2400 3150 60 0000 C CNN
+ 4 2400 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6857B9F5
+P 2400 3500
+F 0 "U1" H 2450 3600 30 0000 C CNN
+F 1 "PORT" H 2400 3500 30 0000 C CNN
+F 2 "" H 2400 3500 60 0000 C CNN
+F 3 "" H 2400 3500 60 0000 C CNN
+ 5 2400 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6857BA3C
+P 2400 3850
+F 0 "U1" H 2450 3950 30 0000 C CNN
+F 1 "PORT" H 2400 3850 30 0000 C CNN
+F 2 "" H 2400 3850 60 0000 C CNN
+F 3 "" H 2400 3850 60 0000 C CNN
+ 6 2400 3850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2650 3150 2650 3400
+Wire Wire Line
+ 2650 3400 2750 3400
+Wire Wire Line
+ 2650 3500 2750 3500
+Wire Wire Line
+ 2650 3850 2650 3600
+Wire Wire Line
+ 2650 3600 2750 3600
+$Comp
+L PORT U1
+U 8 1 6857BB79
+P 3950 6000
+F 0 "U1" H 4000 6100 30 0000 C CNN
+F 1 "PORT" H 3950 6000 30 0000 C CNN
+F 2 "" H 3950 6000 60 0000 C CNN
+F 3 "" H 3950 6000 60 0000 C CNN
+ 8 3950 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6857BC54
+P 6300 3550
+F 0 "U1" H 6350 3650 30 0000 C CNN
+F 1 "PORT" H 6300 3550 30 0000 C CNN
+F 2 "" H 6300 3550 60 0000 C CNN
+F 3 "" H 6300 3550 60 0000 C CNN
+ 9 6300 3550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6857BCA5
+P 6300 3300
+F 0 "U1" H 6350 3400 30 0000 C CNN
+F 1 "PORT" H 6300 3300 30 0000 C CNN
+F 2 "" H 6300 3300 60 0000 C CNN
+F 3 "" H 6300 3300 60 0000 C CNN
+ 10 6300 3300
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 5750 3500 5750 3550
+Wire Wire Line
+ 5750 3550 6050 3550
+Wire Wire Line
+ 5750 3400 5750 3300
+Wire Wire Line
+ 5750 3300 6050 3300
+$Comp
+L 4_and X2
+U 1 1 6857BD7B
+P 4550 2350
+F 0 "X2" H 4600 2300 60 0000 C CNN
+F 1 "4_and" H 4650 2450 60 0000 C CNN
+F 2 "" H 4550 2350 60 0000 C CNN
+F 3 "" H 4550 2350 60 0000 C CNN
+ 1 4550 2350
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6857BE36
+P 4550 1100
+F 0 "U1" H 4600 1200 30 0000 C CNN
+F 1 "PORT" H 4550 1100 30 0000 C CNN
+F 2 "" H 4550 1100 60 0000 C CNN
+F 3 "" H 4550 1100 60 0000 C CNN
+ 11 4550 1100
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6857BEAF
+P 4750 1150
+F 0 "U1" H 4800 1250 30 0000 C CNN
+F 1 "PORT" H 4750 1150 30 0000 C CNN
+F 2 "" H 4750 1150 60 0000 C CNN
+F 3 "" H 4750 1150 60 0000 C CNN
+ 12 4750 1150
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6857BEF8
+P 4950 1150
+F 0 "U1" H 5000 1250 30 0000 C CNN
+F 1 "PORT" H 4950 1150 30 0000 C CNN
+F 2 "" H 4950 1150 60 0000 C CNN
+F 3 "" H 4950 1150 60 0000 C CNN
+ 13 4950 1150
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 4350 1400 4350 1800
+Wire Wire Line
+ 4350 1800 4400 1800
+Wire Wire Line
+ 4400 1800 4400 1950
+Wire Wire Line
+ 4550 1350 4550 1600
+Wire Wire Line
+ 4550 1600 4500 1600
+Wire Wire Line
+ 4500 1600 4500 1950
+Wire Wire Line
+ 4750 1400 4750 1600
+Wire Wire Line
+ 4750 1600 4600 1600
+Wire Wire Line
+ 4600 1600 4600 1950
+Wire Wire Line
+ 4950 1400 4950 1800
+Wire Wire Line
+ 4950 1800 4700 1800
+Wire Wire Line
+ 4700 1800 4700 1950
+Wire Wire Line
+ 4200 6000 4200 5900
+Text Notes 3650 1900 0 60 ~ 0
+a2
+Text Notes 3850 1950 0 60 ~ 0
+b2
+Text Notes 4200 1500 0 60 ~ 0
+a0\n
+Text Notes 4400 1450 0 60 ~ 0
+b0\n
+Text Notes 4600 1450 0 60 ~ 0
+c0\n
+Text Notes 4800 1500 0 60 ~ 0
+d0\n
+Text Notes 2750 3200 0 60 ~ 0
+a1
+Text Notes 2700 3500 0 60 ~ 0
+b1
+Text Notes 2700 3700 0 60 ~ 0
+c1
+Text Notes 5900 3200 0 60 ~ 0
+a3
+Text Notes 5950 3700 0 60 ~ 0
+b3
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/54f64/54f64.sub b/library/SubcircuitLibrary/54f64/54f64.sub
new file mode 100644
index 000000000..aa1cb0783
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/54f64.sub
@@ -0,0 +1,30 @@
+* Subcircuit 54f64
+.subckt 54f64 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_
+* c:\fossee\esim\library\subcircuitlibrary\54f64\54f64.cir
+.include 4_and.sub
+.include 3_and.sub
+* u6 net-_u1-pad3_ net-_u1-pad2_ net-_u2-pad1_ d_and
+x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u2-pad2_ 3_and
+* u5 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad1_ d_and
+* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_nor
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_nor
+* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad8_ d_nor
+x2 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad1_ net-_u4-pad2_ 4_and
+a1 [net-_u1-pad3_ net-_u1-pad2_ ] net-_u2-pad1_ u6
+a2 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad1_ u5
+a3 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4
+a4 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
+a5 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad8_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 54f64
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/54f64/54f64_Previous_Values.xml b/library/SubcircuitLibrary/54f64/54f64_Previous_Values.xml
new file mode 100644
index 000000000..ecfdd7fd8
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/54f64_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_andd_andd_nord_nord_norC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/54f64/analysis b/library/SubcircuitLibrary/54f64/analysis
new file mode 100644
index 000000000..0a6c83b5a
--- /dev/null
+++ b/library/SubcircuitLibrary/54f64/analysis
@@ -0,0 +1 @@
+.tran 250e-03 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210-cache.lib b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210-cache.lib
new file mode 100644
index 000000000..4d3bf2d95
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210-cache.lib
@@ -0,0 +1,76 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dff
+#
+DEF dff X 0 40 Y Y 1 F N
+F0 "X" -350 -500 60 H V C CNN
+F1 "dff" -350 -400 60 H V C CNN
+F2 "" -350 -400 60 H I C CNN
+F3 "" -350 -400 60 H I C CNN
+DRAW
+S -200 150 350 -350 0 1 0 N
+X D 1 -400 50 200 R 50 50 1 1 I
+X CLK 2 -400 -150 200 R 50 50 1 1 I
+X CLR 3 50 -550 200 U 50 50 1 1 I
+X QBar 4 550 -150 200 L 50 50 1 1 O
+X Q 5 550 50 200 L 50 50 1 1 O
+X Preset 6 50 350 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir
new file mode 100644
index 000000000..ec6ef73e2
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir
@@ -0,0 +1,23 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\74AHC1G4210\74AHC1G4210.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 19:33:47
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_X1-Pad1_ /X2 ? Net-_X1-Pad1_ ? ? dff
+X2 Net-_X2-Pad1_ Net-_X1-Pad1_ ? Net-_X2-Pad1_ ? ? dff
+X3 Net-_X3-Pad1_ Net-_X2-Pad1_ ? Net-_X3-Pad1_ ? ? dff
+X4 Net-_X4-Pad1_ Net-_X3-Pad1_ ? Net-_X4-Pad1_ ? ? dff
+X5 Net-_X5-Pad1_ Net-_X4-Pad1_ ? Net-_X5-Pad1_ ? ? dff
+X6 Net-_X6-Pad1_ Net-_X5-Pad1_ ? Net-_X6-Pad1_ ? ? dff
+X7 Net-_X7-Pad1_ Net-_X6-Pad1_ ? Net-_X7-Pad1_ ? ? dff
+X8 Net-_X8-Pad1_ Net-_X7-Pad1_ ? Net-_X8-Pad1_ ? ? dff
+X9 Net-_X10-Pad2_ Net-_X8-Pad1_ ? Net-_X10-Pad2_ ? ? dff
+X10 Net-_U3-Pad1_ Net-_X10-Pad2_ ? Net-_U3-Pad1_ ? ? dff
+U3 Net-_U3-Pad1_ /Q d_inverter
+U2 /X1 /X2 d_inverter
+U1 /X1 /X2 ? /Q ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir.out b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir.out
new file mode 100644
index 000000000..c1609b894
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.cir.out
@@ -0,0 +1,31 @@
+* d:\fossee\esim\library\subcircuitlibrary\74ahc1g4210\74ahc1g4210.cir
+
+.include dff.sub
+x1 net-_x1-pad1_ /x2 ? net-_x1-pad1_ ? ? dff
+x2 net-_x2-pad1_ net-_x1-pad1_ ? net-_x2-pad1_ ? ? dff
+x3 net-_x3-pad1_ net-_x2-pad1_ ? net-_x3-pad1_ ? ? dff
+x4 net-_x4-pad1_ net-_x3-pad1_ ? net-_x4-pad1_ ? ? dff
+x5 net-_x5-pad1_ net-_x4-pad1_ ? net-_x5-pad1_ ? ? dff
+x6 net-_x6-pad1_ net-_x5-pad1_ ? net-_x6-pad1_ ? ? dff
+x7 net-_x7-pad1_ net-_x6-pad1_ ? net-_x7-pad1_ ? ? dff
+x8 net-_x8-pad1_ net-_x7-pad1_ ? net-_x8-pad1_ ? ? dff
+x9 net-_x10-pad2_ net-_x8-pad1_ ? net-_x10-pad2_ ? ? dff
+x10 net-_u3-pad1_ net-_x10-pad2_ ? net-_u3-pad1_ ? ? dff
+* u3 net-_u3-pad1_ /q d_inverter
+* u2 /x1 /x2 d_inverter
+* u1 /x1 /x2 ? /q ? port
+a1 net-_u3-pad1_ /q u3
+a2 /x1 /x2 u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.pro b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sch b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sch
new file mode 100644
index 000000000..39c882d14
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sch
@@ -0,0 +1,439 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74AHC1G4210-cache
+EELAYER 25 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L dff X1
+U 1 1 6857B3A7
+P 5100 7300
+F 0 "X1" H 4750 6800 60 0000 C CNN
+F 1 "dff" H 4750 6900 60 0000 C CNN
+F 2 "" H 4750 6900 60 0001 C CNN
+F 3 "" H 4750 6900 60 0001 C CNN
+ 1 5100 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X2
+U 1 1 6857B452
+P 6500 7300
+F 0 "X2" H 6150 6800 60 0000 C CNN
+F 1 "dff" H 6150 6900 60 0000 C CNN
+F 2 "" H 6150 6900 60 0001 C CNN
+F 3 "" H 6150 6900 60 0001 C CNN
+ 1 6500 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X3
+U 1 1 6857B4F2
+P 7800 7300
+F 0 "X3" H 7450 6800 60 0000 C CNN
+F 1 "dff" H 7450 6900 60 0000 C CNN
+F 2 "" H 7450 6900 60 0001 C CNN
+F 3 "" H 7450 6900 60 0001 C CNN
+ 1 7800 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X4
+U 1 1 6857B4F8
+P 9200 7300
+F 0 "X4" H 8850 6800 60 0000 C CNN
+F 1 "dff" H 8850 6900 60 0000 C CNN
+F 2 "" H 8850 6900 60 0001 C CNN
+F 3 "" H 8850 6900 60 0001 C CNN
+ 1 9200 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X5
+U 1 1 6857BE1A
+P 10400 7300
+F 0 "X5" H 10050 6800 60 0000 C CNN
+F 1 "dff" H 10050 6900 60 0000 C CNN
+F 2 "" H 10050 6900 60 0001 C CNN
+F 3 "" H 10050 6900 60 0001 C CNN
+ 1 10400 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X6
+U 1 1 6857BE20
+P 11800 7300
+F 0 "X6" H 11450 6800 60 0000 C CNN
+F 1 "dff" H 11450 6900 60 0000 C CNN
+F 2 "" H 11450 6900 60 0001 C CNN
+F 3 "" H 11450 6900 60 0001 C CNN
+ 1 11800 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X7
+U 1 1 6857BE26
+P 13100 7300
+F 0 "X7" H 12750 6800 60 0000 C CNN
+F 1 "dff" H 12750 6900 60 0000 C CNN
+F 2 "" H 12750 6900 60 0001 C CNN
+F 3 "" H 12750 6900 60 0001 C CNN
+ 1 13100 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X8
+U 1 1 6857BE2C
+P 14500 7300
+F 0 "X8" H 14150 6800 60 0000 C CNN
+F 1 "dff" H 14150 6900 60 0000 C CNN
+F 2 "" H 14150 6900 60 0001 C CNN
+F 3 "" H 14150 6900 60 0001 C CNN
+ 1 14500 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X9
+U 1 1 6857D2EC
+P 15700 7300
+F 0 "X9" H 15350 6800 60 0000 C CNN
+F 1 "dff" H 15350 6900 60 0000 C CNN
+F 2 "" H 15350 6900 60 0001 C CNN
+F 3 "" H 15350 6900 60 0001 C CNN
+ 1 15700 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X10
+U 1 1 6857D2F2
+P 17100 7300
+F 0 "X10" H 16750 6800 60 0000 C CNN
+F 1 "dff" H 16750 6900 60 0000 C CNN
+F 2 "" H 16750 6900 60 0001 C CNN
+F 3 "" H 16750 6900 60 0001 C CNN
+ 1 17100 7300
+ 1 0 0 -1
+$EndComp
+NoConn ~ 5150 6950
+NoConn ~ 5650 7250
+NoConn ~ 5150 7850
+NoConn ~ 6550 6950
+NoConn ~ 6550 7850
+NoConn ~ 7050 7250
+NoConn ~ 7850 6950
+NoConn ~ 7850 7850
+NoConn ~ 8350 7250
+NoConn ~ 9250 6950
+NoConn ~ 9250 7850
+NoConn ~ 9750 7250
+NoConn ~ 10450 7850
+NoConn ~ 10450 6950
+NoConn ~ 10950 7250
+NoConn ~ 11850 7850
+NoConn ~ 11850 6950
+NoConn ~ 12350 7250
+NoConn ~ 13150 6950
+NoConn ~ 13150 7850
+NoConn ~ 13650 7250
+NoConn ~ 14550 7850
+NoConn ~ 14550 6950
+NoConn ~ 15050 7250
+NoConn ~ 15750 7850
+NoConn ~ 15750 6950
+NoConn ~ 16250 7250
+NoConn ~ 17150 7850
+NoConn ~ 17150 6950
+NoConn ~ 17650 7250
+Wire Wire Line
+ 4700 7250 4500 7250
+Wire Wire Line
+ 4500 7250 4500 6600
+Wire Wire Line
+ 4500 6600 5800 6600
+Wire Wire Line
+ 5800 6600 5800 7450
+Wire Wire Line
+ 5800 7450 5650 7450
+Wire Wire Line
+ 5800 7350 6000 7350
+Wire Wire Line
+ 6000 7350 6000 7450
+Wire Wire Line
+ 6000 7450 6100 7450
+Connection ~ 5800 7350
+Wire Wire Line
+ 6100 7250 6100 6600
+Wire Wire Line
+ 6100 6600 7200 6600
+Wire Wire Line
+ 7200 6600 7200 7450
+Wire Wire Line
+ 7200 7450 7050 7450
+Wire Wire Line
+ 7200 7350 7300 7350
+Wire Wire Line
+ 7300 7350 7300 7450
+Wire Wire Line
+ 7300 7450 7400 7450
+Connection ~ 7200 7350
+Wire Wire Line
+ 7400 7250 7400 6600
+Wire Wire Line
+ 7400 6600 8500 6600
+Wire Wire Line
+ 8500 6600 8500 7450
+Wire Wire Line
+ 8500 7450 8350 7450
+Wire Wire Line
+ 8500 7350 8650 7350
+Wire Wire Line
+ 8650 7350 8650 7450
+Wire Wire Line
+ 8650 7450 8800 7450
+Connection ~ 8500 7350
+Wire Wire Line
+ 8800 7250 8800 6600
+Wire Wire Line
+ 8800 6600 9900 6600
+Wire Wire Line
+ 9900 6600 9900 7450
+Wire Wire Line
+ 9900 7450 9750 7450
+Wire Wire Line
+ 9900 7350 9950 7350
+Wire Wire Line
+ 9950 7350 9950 7450
+Wire Wire Line
+ 9950 7450 10000 7450
+Connection ~ 9900 7350
+Wire Wire Line
+ 10000 7250 10000 6600
+Wire Wire Line
+ 10000 6600 11050 6600
+Wire Wire Line
+ 11050 6600 11050 7450
+Wire Wire Line
+ 11050 7450 10950 7450
+Wire Wire Line
+ 11050 7350 11200 7350
+Wire Wire Line
+ 11200 7350 11200 7450
+Wire Wire Line
+ 11200 7450 11400 7450
+Connection ~ 11050 7350
+Wire Wire Line
+ 11400 7250 11400 6600
+Wire Wire Line
+ 11400 6600 12500 6600
+Wire Wire Line
+ 12500 6600 12500 7450
+Wire Wire Line
+ 12500 7450 12350 7450
+Wire Wire Line
+ 12500 7350 12600 7350
+Wire Wire Line
+ 12600 7350 12600 7450
+Wire Wire Line
+ 12600 7450 12700 7450
+Connection ~ 12500 7350
+Wire Wire Line
+ 12700 7250 12700 6600
+Wire Wire Line
+ 12700 6600 13800 6600
+Wire Wire Line
+ 13800 6600 13800 7450
+Wire Wire Line
+ 13800 7450 13650 7450
+Wire Wire Line
+ 13800 7300 13900 7300
+Wire Wire Line
+ 13900 7300 13900 7450
+Wire Wire Line
+ 13900 7450 14100 7450
+Connection ~ 13800 7300
+Wire Wire Line
+ 14100 7250 14100 6600
+Wire Wire Line
+ 14100 6600 15150 6600
+Wire Wire Line
+ 15150 6600 15150 7450
+Wire Wire Line
+ 15150 7450 15050 7450
+Wire Wire Line
+ 15150 7350 15200 7350
+Wire Wire Line
+ 15200 7350 15200 7450
+Wire Wire Line
+ 15200 7450 15300 7450
+Connection ~ 15150 7350
+Wire Wire Line
+ 15300 7250 15300 6600
+Wire Wire Line
+ 15300 6600 16400 6600
+Wire Wire Line
+ 16400 6600 16400 7450
+Wire Wire Line
+ 16400 7450 16250 7450
+Wire Wire Line
+ 16400 7350 16500 7350
+Wire Wire Line
+ 16500 7350 16500 7450
+Wire Wire Line
+ 16500 7450 16700 7450
+Connection ~ 16400 7350
+Wire Wire Line
+ 16700 7250 16700 6600
+Wire Wire Line
+ 16700 6600 17800 6600
+Wire Wire Line
+ 17800 6600 17800 7450
+Wire Wire Line
+ 17650 7450 17900 7450
+Connection ~ 17800 7450
+$Comp
+L d_inverter U3
+U 1 1 68580C81
+P 18200 7450
+F 0 "U3" H 18200 7350 60 0000 C CNN
+F 1 "d_inverter" H 18200 7600 60 0000 C CNN
+F 2 "" H 18250 7400 60 0000 C CNN
+F 3 "" H 18250 7400 60 0000 C CNN
+ 1 18200 7450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 18500 7450 18700 7450
+$Comp
+L d_inverter U2
+U 1 1 68585125
+P 3900 7450
+F 0 "U2" H 3900 7350 60 0000 C CNN
+F 1 "d_inverter" H 3900 7600 60 0000 C CNN
+F 2 "" H 3950 7400 60 0000 C CNN
+F 3 "" H 3950 7400 60 0000 C CNN
+ 1 3900 7450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4200 7450 4700 7450
+Wire Wire Line
+ 3600 7450 2950 7450
+Wire Wire Line
+ 4350 7450 4350 6600
+Wire Wire Line
+ 4350 6600 3000 6600
+Connection ~ 4350 7450
+Text Label 3000 6600 0 60 ~ 0
+X2
+Text Label 2950 7450 0 60 ~ 0
+X1
+Text Label 18700 7450 0 60 ~ 0
+Q
+$Comp
+L PORT U1
+U 1 1 68585EDA
+P 2700 7450
+F 0 "U1" H 2750 7550 30 0000 C CNN
+F 1 "PORT" H 2700 7450 30 0000 C CNN
+F 2 "" H 2700 7450 60 0000 C CNN
+F 3 "" H 2700 7450 60 0000 C CNN
+ 1 2700 7450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68585F37
+P 3550 8200
+F 0 "U1" H 3600 8300 30 0000 C CNN
+F 1 "PORT" H 3550 8200 30 0000 C CNN
+F 2 "" H 3550 8200 60 0000 C CNN
+F 3 "" H 3550 8200 60 0000 C CNN
+ 3 3550 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68585F7E
+P 4050 8200
+F 0 "U1" H 4100 8300 30 0000 C CNN
+F 1 "PORT" H 4050 8200 30 0000 C CNN
+F 2 "" H 4050 8200 60 0000 C CNN
+F 3 "" H 4050 8200 60 0000 C CNN
+ 5 4050 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68585FB7
+P 2750 6600
+F 0 "U1" H 2800 6700 30 0000 C CNN
+F 1 "PORT" H 2750 6600 30 0000 C CNN
+F 2 "" H 2750 6600 60 0000 C CNN
+F 3 "" H 2750 6600 60 0000 C CNN
+ 2 2750 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68585FEC
+P 18950 7450
+F 0 "U1" H 19000 7550 30 0000 C CNN
+F 1 "PORT" H 18950 7450 30 0000 C CNN
+F 2 "" H 18950 7450 60 0000 C CNN
+F 3 "" H 18950 7450 60 0000 C CNN
+ 4 18950 7450
+ -1 0 0 1
+$EndComp
+NoConn ~ 3800 8200
+NoConn ~ 4300 8200
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sub b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sub
new file mode 100644
index 000000000..27720ad38
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210.sub
@@ -0,0 +1,25 @@
+* Subcircuit 74AHC1G4210
+.subckt 74AHC1G4210 /x1 /x2 ? /q ?
+* d:\fossee\esim\library\subcircuitlibrary\74ahc1g4210\74ahc1g4210.cir
+.include dff.sub
+x1 net-_x1-pad1_ /x2 ? net-_x1-pad1_ ? ? dff
+x2 net-_x2-pad1_ net-_x1-pad1_ ? net-_x2-pad1_ ? ? dff
+x3 net-_x3-pad1_ net-_x2-pad1_ ? net-_x3-pad1_ ? ? dff
+x4 net-_x4-pad1_ net-_x3-pad1_ ? net-_x4-pad1_ ? ? dff
+x5 net-_x5-pad1_ net-_x4-pad1_ ? net-_x5-pad1_ ? ? dff
+x6 net-_x6-pad1_ net-_x5-pad1_ ? net-_x6-pad1_ ? ? dff
+x7 net-_x7-pad1_ net-_x6-pad1_ ? net-_x7-pad1_ ? ? dff
+x8 net-_x8-pad1_ net-_x7-pad1_ ? net-_x8-pad1_ ? ? dff
+x9 net-_x10-pad2_ net-_x8-pad1_ ? net-_x10-pad2_ ? ? dff
+x10 net-_u3-pad1_ net-_x10-pad2_ ? net-_u3-pad1_ ? ? dff
+* u3 net-_u3-pad1_ /q d_inverter
+* u2 /x1 /x2 d_inverter
+a1 net-_u3-pad1_ /q u3
+a2 /x1 /x2 u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74AHC1G4210
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210_Previous_Values.xml b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210_Previous_Values.xml
new file mode 100644
index 000000000..3aa4f1058
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/74AHC1G4210_Previous_Values.xml
@@ -0,0 +1 @@
+d_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dfftruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4210/analysis b/library/SubcircuitLibrary/74AHC1G4210/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff-cache.lib b/library/SubcircuitLibrary/74AHC1G4210/dff-cache.lib
new file mode 100644
index 000000000..440552005
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/dff-cache.lib
@@ -0,0 +1,92 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.cir b/library/SubcircuitLibrary/74AHC1G4210/dff.cir
new file mode 100644
index 000000000..883325a5e
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/dff.cir
@@ -0,0 +1,18 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\dff\dff.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 11:41:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_nand
+U4 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U4-Pad3_ d_nand
+U5 Net-_U2-Pad6_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_and
+U6 Net-_U4-Pad3_ Net-_U2-Pad3_ Net-_U6-Pad3_ d_and
+U7 Net-_U2-Pad4_ Net-_U5-Pad3_ Net-_U2-Pad5_ d_nand
+U8 Net-_U2-Pad5_ Net-_U6-Pad3_ Net-_U2-Pad4_ d_nand
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.cir.out b/library/SubcircuitLibrary/74AHC1G4210/dff.cir.out
new file mode 100644
index 000000000..849212938
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/dff.cir.out
@@ -0,0 +1,40 @@
+* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir
+
+* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand
+* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and
+* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand
+* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port
+a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6
+a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7
+a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8
+a7 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.pro b/library/SubcircuitLibrary/74AHC1G4210/dff.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/dff.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.sch b/library/SubcircuitLibrary/74AHC1G4210/dff.sch
new file mode 100644
index 000000000..675737646
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/dff.sch
@@ -0,0 +1,273 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nand U3
+U 1 1 6851060F
+P 3700 2300
+F 0 "U3" H 3700 2300 60 0000 C CNN
+F 1 "d_nand" H 3750 2400 60 0000 C CNN
+F 2 "" H 3700 2300 60 0000 C CNN
+F 3 "" H 3700 2300 60 0000 C CNN
+ 1 3700 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 68510656
+P 3700 3300
+F 0 "U4" H 3700 3300 60 0000 C CNN
+F 1 "d_nand" H 3750 3400 60 0000 C CNN
+F 2 "" H 3700 3300 60 0000 C CNN
+F 3 "" H 3700 3300 60 0000 C CNN
+ 1 3700 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 68510666
+P 5400 2300
+F 0 "U5" H 5400 2300 60 0000 C CNN
+F 1 "d_and" H 5450 2400 60 0000 C CNN
+F 2 "" H 5400 2300 60 0000 C CNN
+F 3 "" H 5400 2300 60 0000 C CNN
+ 1 5400 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 685106C5
+P 5400 3300
+F 0 "U6" H 5400 3300 60 0000 C CNN
+F 1 "d_and" H 5450 3400 60 0000 C CNN
+F 2 "" H 5400 3300 60 0000 C CNN
+F 3 "" H 5400 3300 60 0000 C CNN
+ 1 5400 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U7
+U 1 1 685106D1
+P 7100 2300
+F 0 "U7" H 7100 2300 60 0000 C CNN
+F 1 "d_nand" H 7150 2400 60 0000 C CNN
+F 2 "" H 7100 2300 60 0000 C CNN
+F 3 "" H 7100 2300 60 0000 C CNN
+ 1 7100 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U8
+U 1 1 68510816
+P 7150 3300
+F 0 "U8" H 7150 3300 60 0000 C CNN
+F 1 "d_nand" H 7200 3400 60 0000 C CNN
+F 2 "" H 7150 3300 60 0000 C CNN
+F 3 "" H 7150 3300 60 0000 C CNN
+ 1 7150 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5850 3250 6150 3250
+Wire Wire Line
+ 6150 3250 6150 3300
+Wire Wire Line
+ 6150 3300 6700 3300
+Wire Wire Line
+ 5850 2250 6050 2250
+Wire Wire Line
+ 6050 2250 6050 2300
+Wire Wire Line
+ 6050 2300 6650 2300
+Wire Wire Line
+ 7550 2250 8000 2250
+Wire Wire Line
+ 7600 3250 8150 3250
+Wire Wire Line
+ 4950 2200 4750 2200
+Wire Wire Line
+ 4750 2200 4750 1750
+Wire Wire Line
+ 4950 3300 4750 3300
+Wire Wire Line
+ 4750 3300 4750 3800
+Wire Wire Line
+ 4150 3250 4500 3250
+Wire Wire Line
+ 4500 3250 4500 3200
+Wire Wire Line
+ 4500 3200 4950 3200
+Wire Wire Line
+ 4150 2250 4400 2250
+Wire Wire Line
+ 4400 2250 4400 2300
+Wire Wire Line
+ 4400 2300 4950 2300
+Wire Wire Line
+ 7850 2250 7850 2600
+Wire Wire Line
+ 7850 2600 6450 2600
+Wire Wire Line
+ 6450 2600 6450 3200
+Wire Wire Line
+ 6450 3200 6700 3200
+Connection ~ 7850 2250
+Wire Wire Line
+ 7750 3250 7750 2750
+Wire Wire Line
+ 7750 2750 6250 2750
+Wire Wire Line
+ 6250 2750 6250 2200
+Wire Wire Line
+ 6250 2200 6650 2200
+Connection ~ 7750 3250
+Wire Wire Line
+ 3250 2200 2100 2200
+Wire Wire Line
+ 3250 2300 3000 2300
+Wire Wire Line
+ 3000 2300 3000 3200
+Wire Wire Line
+ 3000 3200 3250 3200
+Wire Wire Line
+ 2300 2200 2300 3300
+Connection ~ 2300 2200
+$Comp
+L d_inverter U1
+U 1 1 68510965
+P 2700 3300
+F 0 "U1" H 2700 3200 60 0000 C CNN
+F 1 "d_inverter" H 2700 3450 60 0000 C CNN
+F 2 "" H 2750 3250 60 0000 C CNN
+F 3 "" H 2750 3250 60 0000 C CNN
+ 1 2700 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3000 3300 3250 3300
+Wire Wire Line
+ 2300 3300 2400 3300
+Wire Wire Line
+ 3000 2750 1950 2750
+Wire Wire Line
+ 1950 2750 1950 3750
+Connection ~ 3000 2750
+$Comp
+L PORT U2
+U 1 1 68510A2C
+P 1850 2200
+F 0 "U2" H 1900 2300 30 0000 C CNN
+F 1 "PORT" H 1850 2200 30 0000 C CNN
+F 2 "" H 1850 2200 60 0000 C CNN
+F 3 "" H 1850 2200 60 0000 C CNN
+ 1 1850 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 2 1 68510A87
+P 1700 3750
+F 0 "U2" H 1750 3850 30 0000 C CNN
+F 1 "PORT" H 1700 3750 30 0000 C CNN
+F 2 "" H 1700 3750 60 0000 C CNN
+F 3 "" H 1700 3750 60 0000 C CNN
+ 2 1700 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 3 1 68510ACA
+P 4500 3800
+F 0 "U2" H 4550 3900 30 0000 C CNN
+F 1 "PORT" H 4500 3800 30 0000 C CNN
+F 2 "" H 4500 3800 60 0000 C CNN
+F 3 "" H 4500 3800 60 0000 C CNN
+ 3 4500 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 5 1 68510AFD
+P 8000 2500
+F 0 "U2" H 8050 2600 30 0000 C CNN
+F 1 "PORT" H 8000 2500 30 0000 C CNN
+F 2 "" H 8000 2500 60 0000 C CNN
+F 3 "" H 8000 2500 60 0000 C CNN
+ 5 8000 2500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 4 1 68510B2C
+P 8150 3500
+F 0 "U2" H 8200 3600 30 0000 C CNN
+F 1 "PORT" H 8150 3500 30 0000 C CNN
+F 2 "" H 8150 3500 60 0000 C CNN
+F 3 "" H 8150 3500 60 0000 C CNN
+ 4 8150 3500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 6 1 68510B5D
+P 4500 1750
+F 0 "U2" H 4550 1850 30 0000 C CNN
+F 1 "PORT" H 4500 1750 30 0000 C CNN
+F 2 "" H 4500 1750 60 0000 C CNN
+F 3 "" H 4500 1750 60 0000 C CNN
+ 6 4500 1750
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff.sub b/library/SubcircuitLibrary/74AHC1G4210/dff.sub
new file mode 100644
index 000000000..885e878fc
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/dff.sub
@@ -0,0 +1,34 @@
+* Subcircuit dff
+.subckt dff net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_
+* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir
+* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand
+* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and
+* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand
+* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6
+a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7
+a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8
+a7 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends dff
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4210/dff_Previous_Values.xml b/library/SubcircuitLibrary/74AHC1G4210/dff_Previous_Values.xml
new file mode 100644
index 000000000..2a57486b8
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4210/dff_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_andd_andd_nandd_nandd_inverter
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212-cache.lib b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212-cache.lib
new file mode 100644
index 000000000..4d3bf2d95
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212-cache.lib
@@ -0,0 +1,76 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dff
+#
+DEF dff X 0 40 Y Y 1 F N
+F0 "X" -350 -500 60 H V C CNN
+F1 "dff" -350 -400 60 H V C CNN
+F2 "" -350 -400 60 H I C CNN
+F3 "" -350 -400 60 H I C CNN
+DRAW
+S -200 150 350 -350 0 1 0 N
+X D 1 -400 50 200 R 50 50 1 1 I
+X CLK 2 -400 -150 200 R 50 50 1 1 I
+X CLR 3 50 -550 200 U 50 50 1 1 I
+X QBar 4 550 -150 200 L 50 50 1 1 O
+X Q 5 550 50 200 L 50 50 1 1 O
+X Preset 6 50 350 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir
new file mode 100644
index 000000000..3fe1795a7
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir
@@ -0,0 +1,25 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\74AHC1G4212\74AHC1G4212.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 19:44:41
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_X1-Pad1_ Net-_U1-Pad2_ ? Net-_X1-Pad1_ ? ? dff
+X2 Net-_X2-Pad1_ Net-_X1-Pad1_ ? Net-_X2-Pad1_ ? ? dff
+X3 Net-_X3-Pad1_ Net-_X2-Pad1_ ? Net-_X3-Pad1_ ? ? dff
+X4 Net-_X4-Pad1_ Net-_X3-Pad1_ ? Net-_X4-Pad1_ ? ? dff
+X5 ? Net-_X4-Pad1_ ? Net-_X5-Pad4_ ? Net-_X5-Pad4_ dff
+X6 Net-_X6-Pad1_ Net-_X5-Pad4_ ? Net-_X6-Pad1_ ? ? dff
+X7 Net-_X7-Pad1_ Net-_X6-Pad1_ ? Net-_X7-Pad1_ ? ? dff
+X8 Net-_X8-Pad1_ Net-_X7-Pad1_ ? Net-_X8-Pad1_ ? ? dff
+X9 Net-_X10-Pad2_ Net-_X8-Pad1_ ? Net-_X10-Pad2_ ? ? dff
+X10 Net-_X10-Pad1_ Net-_X10-Pad2_ ? Net-_X10-Pad1_ ? ? dff
+X11 Net-_X11-Pad1_ Net-_X10-Pad1_ ? Net-_X11-Pad1_ ? ? dff
+X12 Net-_U3-Pad1_ Net-_X11-Pad1_ ? Net-_U3-Pad1_ ? ? dff
+U3 Net-_U3-Pad1_ Net-_U1-Pad4_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ ? Net-_U1-Pad4_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir.out b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir.out
new file mode 100644
index 000000000..0ab970978
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.cir.out
@@ -0,0 +1,33 @@
+* d:\fossee\esim\library\subcircuitlibrary\74ahc1g4212\74ahc1g4212.cir
+
+.include dff.sub
+x1 net-_x1-pad1_ net-_u1-pad2_ ? net-_x1-pad1_ ? ? dff
+x2 net-_x2-pad1_ net-_x1-pad1_ ? net-_x2-pad1_ ? ? dff
+x3 net-_x3-pad1_ net-_x2-pad1_ ? net-_x3-pad1_ ? ? dff
+x4 net-_x4-pad1_ net-_x3-pad1_ ? net-_x4-pad1_ ? ? dff
+x5 ? net-_x4-pad1_ ? net-_x5-pad4_ ? net-_x5-pad4_ dff
+x6 net-_x6-pad1_ net-_x5-pad4_ ? net-_x6-pad1_ ? ? dff
+x7 net-_x7-pad1_ net-_x6-pad1_ ? net-_x7-pad1_ ? ? dff
+x8 net-_x8-pad1_ net-_x7-pad1_ ? net-_x8-pad1_ ? ? dff
+x9 net-_x10-pad2_ net-_x8-pad1_ ? net-_x10-pad2_ ? ? dff
+x10 net-_x10-pad1_ net-_x10-pad2_ ? net-_x10-pad1_ ? ? dff
+x11 net-_x11-pad1_ net-_x10-pad1_ ? net-_x11-pad1_ ? ? dff
+x12 net-_u3-pad1_ net-_x11-pad1_ ? net-_u3-pad1_ ? ? dff
+* u3 net-_u3-pad1_ net-_u1-pad4_ d_inverter
+* u2 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ ? net-_u1-pad4_ ? port
+a1 net-_u3-pad1_ net-_u1-pad4_ u3
+a2 net-_u1-pad1_ net-_u1-pad2_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.pro b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sch b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sch
new file mode 100644
index 000000000..4b0870536
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sch
@@ -0,0 +1,497 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74AHC1G4212-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L dff X1
+U 1 1 68693108
+P 7100 8700
+F 0 "X1" H 6750 8200 60 0000 C CNN
+F 1 "dff" H 6750 8300 60 0000 C CNN
+F 2 "" H 6750 8300 60 0001 C CNN
+F 3 "" H 6750 8300 60 0001 C CNN
+ 1 7100 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X2
+U 1 1 686931A9
+P 8850 8700
+F 0 "X2" H 8500 8200 60 0000 C CNN
+F 1 "dff" H 8500 8300 60 0000 C CNN
+F 2 "" H 8500 8300 60 0001 C CNN
+F 3 "" H 8500 8300 60 0001 C CNN
+ 1 8850 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X3
+U 1 1 68693239
+P 10600 8700
+F 0 "X3" H 10250 8200 60 0000 C CNN
+F 1 "dff" H 10250 8300 60 0000 C CNN
+F 2 "" H 10250 8300 60 0001 C CNN
+F 3 "" H 10250 8300 60 0001 C CNN
+ 1 10600 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X4
+U 1 1 6869323F
+P 12350 8700
+F 0 "X4" H 12000 8200 60 0000 C CNN
+F 1 "dff" H 12000 8300 60 0000 C CNN
+F 2 "" H 12000 8300 60 0001 C CNN
+F 3 "" H 12000 8300 60 0001 C CNN
+ 1 12350 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X5
+U 1 1 686936B9
+P 14000 8700
+F 0 "X5" H 13650 8200 60 0000 C CNN
+F 1 "dff" H 13650 8300 60 0000 C CNN
+F 2 "" H 13650 8300 60 0001 C CNN
+F 3 "" H 13650 8300 60 0001 C CNN
+ 1 14000 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X6
+U 1 1 686936BF
+P 15750 8700
+F 0 "X6" H 15400 8200 60 0000 C CNN
+F 1 "dff" H 15400 8300 60 0000 C CNN
+F 2 "" H 15400 8300 60 0001 C CNN
+F 3 "" H 15400 8300 60 0001 C CNN
+ 1 15750 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X7
+U 1 1 686936C5
+P 17500 8700
+F 0 "X7" H 17150 8200 60 0000 C CNN
+F 1 "dff" H 17150 8300 60 0000 C CNN
+F 2 "" H 17150 8300 60 0001 C CNN
+F 3 "" H 17150 8300 60 0001 C CNN
+ 1 17500 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X8
+U 1 1 686936CB
+P 19250 8700
+F 0 "X8" H 18900 8200 60 0000 C CNN
+F 1 "dff" H 18900 8300 60 0000 C CNN
+F 2 "" H 18900 8300 60 0001 C CNN
+F 3 "" H 18900 8300 60 0001 C CNN
+ 1 19250 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X9
+U 1 1 68693C01
+P 20850 8700
+F 0 "X9" H 20500 8200 60 0000 C CNN
+F 1 "dff" H 20500 8300 60 0000 C CNN
+F 2 "" H 20500 8300 60 0001 C CNN
+F 3 "" H 20500 8300 60 0001 C CNN
+ 1 20850 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X10
+U 1 1 68693C07
+P 22600 8700
+F 0 "X10" H 22250 8200 60 0000 C CNN
+F 1 "dff" H 22250 8300 60 0000 C CNN
+F 2 "" H 22250 8300 60 0001 C CNN
+F 3 "" H 22250 8300 60 0001 C CNN
+ 1 22600 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X11
+U 1 1 68693C0D
+P 24350 8700
+F 0 "X11" H 24000 8200 60 0000 C CNN
+F 1 "dff" H 24000 8300 60 0000 C CNN
+F 2 "" H 24000 8300 60 0001 C CNN
+F 3 "" H 24000 8300 60 0001 C CNN
+ 1 24350 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L dff X12
+U 1 1 68693C13
+P 26100 8700
+F 0 "X12" H 25750 8200 60 0000 C CNN
+F 1 "dff" H 25750 8300 60 0000 C CNN
+F 2 "" H 25750 8300 60 0001 C CNN
+F 3 "" H 25750 8300 60 0001 C CNN
+ 1 26100 8700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6700 8650 6650 8650
+Wire Wire Line
+ 6650 8650 6650 8100
+Wire Wire Line
+ 6650 8100 7950 8100
+Wire Wire Line
+ 7950 8100 7950 8850
+Wire Wire Line
+ 7950 8850 7650 8850
+Wire Wire Line
+ 7950 8750 8150 8750
+Wire Wire Line
+ 8150 8750 8150 8850
+Wire Wire Line
+ 8150 8850 8450 8850
+Connection ~ 7950 8750
+Wire Wire Line
+ 8450 8650 8450 8100
+Wire Wire Line
+ 8450 8100 9700 8100
+Wire Wire Line
+ 9700 8100 9700 8850
+Wire Wire Line
+ 9700 8850 9400 8850
+Wire Wire Line
+ 9700 8750 10000 8750
+Wire Wire Line
+ 10000 8750 10000 8850
+Wire Wire Line
+ 10000 8850 10200 8850
+Connection ~ 9700 8750
+Wire Wire Line
+ 10200 8650 10200 8100
+Wire Wire Line
+ 10200 8100 11550 8100
+Wire Wire Line
+ 11550 8100 11550 8850
+Wire Wire Line
+ 11550 8850 11150 8850
+Wire Wire Line
+ 11550 8750 11700 8750
+Wire Wire Line
+ 11700 8750 11700 8850
+Wire Wire Line
+ 11700 8850 11950 8850
+Connection ~ 11550 8750
+Wire Wire Line
+ 11950 8650 11950 8100
+Wire Wire Line
+ 11950 8100 13250 8100
+Wire Wire Line
+ 13250 8100 13250 8850
+Wire Wire Line
+ 13250 8850 12900 8850
+Wire Wire Line
+ 13250 8750 13400 8750
+Wire Wire Line
+ 13400 8750 13400 8850
+Wire Wire Line
+ 13400 8850 13600 8850
+Connection ~ 13250 8750
+Wire Wire Line
+ 14050 8350 14050 8150
+Wire Wire Line
+ 14050 8150 14800 8150
+Wire Wire Line
+ 14800 8150 14800 8850
+Wire Wire Line
+ 14800 8850 14550 8850
+Wire Wire Line
+ 14800 8750 15050 8750
+Wire Wire Line
+ 15050 8750 15050 8850
+Wire Wire Line
+ 15050 8850 15350 8850
+Connection ~ 14800 8750
+Wire Wire Line
+ 15350 8650 15250 8650
+Wire Wire Line
+ 15250 8650 15250 8150
+Wire Wire Line
+ 15250 8150 16600 8150
+Wire Wire Line
+ 16600 8150 16600 8850
+Wire Wire Line
+ 16600 8850 16300 8850
+Wire Wire Line
+ 16600 8750 16800 8750
+Wire Wire Line
+ 16800 8750 16800 8850
+Wire Wire Line
+ 16800 8850 17100 8850
+Connection ~ 16600 8750
+Wire Wire Line
+ 17100 8650 16950 8650
+Wire Wire Line
+ 16950 8650 16950 8200
+Wire Wire Line
+ 16950 8200 18350 8200
+Wire Wire Line
+ 18350 8200 18350 8850
+Wire Wire Line
+ 18350 8850 18050 8850
+Wire Wire Line
+ 18350 8750 18550 8750
+Wire Wire Line
+ 18550 8750 18550 8850
+Wire Wire Line
+ 18550 8850 18850 8850
+Connection ~ 18350 8750
+Wire Wire Line
+ 18850 8650 18750 8650
+Wire Wire Line
+ 18750 8650 18750 8200
+Wire Wire Line
+ 18750 8200 20000 8200
+Wire Wire Line
+ 20000 8200 20000 8850
+Wire Wire Line
+ 20000 8850 19800 8850
+Wire Wire Line
+ 20000 8750 20150 8750
+Wire Wire Line
+ 20150 8750 20150 8850
+Wire Wire Line
+ 20150 8850 20450 8850
+Connection ~ 20000 8750
+Wire Wire Line
+ 20450 8650 20300 8650
+Wire Wire Line
+ 20300 8650 20300 8200
+Wire Wire Line
+ 20300 8200 21650 8200
+Wire Wire Line
+ 21650 8200 21650 8850
+Wire Wire Line
+ 21650 8850 21400 8850
+Wire Wire Line
+ 22200 8650 22000 8650
+Wire Wire Line
+ 22000 8650 22000 8100
+Wire Wire Line
+ 22000 8100 23350 8100
+Wire Wire Line
+ 23350 8100 23350 8850
+Wire Wire Line
+ 23350 8850 23150 8850
+Wire Wire Line
+ 21650 8800 21950 8800
+Wire Wire Line
+ 21950 8800 21950 8850
+Wire Wire Line
+ 21950 8850 22200 8850
+Connection ~ 21650 8800
+Wire Wire Line
+ 23350 8750 23600 8750
+Wire Wire Line
+ 23600 8750 23600 8850
+Wire Wire Line
+ 23600 8850 23950 8850
+Connection ~ 23350 8750
+Wire Wire Line
+ 23950 8650 23750 8650
+Wire Wire Line
+ 23750 8650 23750 8100
+Wire Wire Line
+ 23750 8100 25300 8100
+Wire Wire Line
+ 25300 8100 25300 8850
+Wire Wire Line
+ 25300 8850 24900 8850
+Wire Wire Line
+ 25300 8750 25450 8750
+Wire Wire Line
+ 25450 8750 25450 8850
+Wire Wire Line
+ 25450 8850 25700 8850
+Connection ~ 25300 8750
+Wire Wire Line
+ 25700 8650 25700 8100
+Wire Wire Line
+ 25700 8100 27050 8100
+Wire Wire Line
+ 27050 8100 27050 8850
+Wire Wire Line
+ 26650 8850 27400 8850
+$Comp
+L d_inverter U3
+U 1 1 686957E9
+P 27700 8850
+F 0 "U3" H 27700 8750 60 0000 C CNN
+F 1 "d_inverter" H 27700 9000 60 0000 C CNN
+F 2 "" H 27750 8800 60 0000 C CNN
+F 3 "" H 27750 8800 60 0000 C CNN
+ 1 27700 8850
+ 1 0 0 -1
+$EndComp
+Connection ~ 27050 8850
+Wire Wire Line
+ 28000 8850 28450 8850
+$Comp
+L d_inverter U2
+U 1 1 6869621C
+P 5850 8850
+F 0 "U2" H 5850 8750 60 0000 C CNN
+F 1 "d_inverter" H 5850 9000 60 0000 C CNN
+F 2 "" H 5900 8800 60 0000 C CNN
+F 3 "" H 5900 8800 60 0000 C CNN
+ 1 5850 8850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6150 8850 6700 8850
+Wire Wire Line
+ 5550 8850 5050 8850
+Wire Wire Line
+ 5000 8250 6350 8250
+Wire Wire Line
+ 6350 8250 6350 8850
+Connection ~ 6350 8850
+NoConn ~ 7150 9250
+NoConn ~ 7150 8350
+NoConn ~ 7650 8650
+NoConn ~ 8900 8350
+NoConn ~ 8900 9250
+NoConn ~ 9400 8650
+NoConn ~ 10650 8350
+NoConn ~ 10650 9250
+NoConn ~ 11150 8650
+NoConn ~ 12400 8350
+NoConn ~ 12400 9250
+NoConn ~ 14050 9250
+NoConn ~ 15800 8350
+NoConn ~ 15800 9250
+NoConn ~ 16300 8650
+NoConn ~ 17550 9250
+NoConn ~ 17550 8350
+NoConn ~ 18050 8650
+NoConn ~ 19300 9250
+NoConn ~ 19300 8350
+NoConn ~ 19800 8650
+NoConn ~ 20900 9250
+NoConn ~ 20900 8350
+NoConn ~ 21400 8650
+NoConn ~ 24400 9250
+NoConn ~ 24400 8350
+NoConn ~ 24900 8650
+NoConn ~ 26150 9250
+NoConn ~ 26150 8350
+NoConn ~ 26650 8650
+$Comp
+L PORT U1
+U 1 1 68699175
+P 4800 8850
+F 0 "U1" H 4850 8950 30 0000 C CNN
+F 1 "PORT" H 4800 8850 30 0000 C CNN
+F 2 "" H 4800 8850 60 0000 C CNN
+F 3 "" H 4800 8850 60 0000 C CNN
+ 1 4800 8850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686991EA
+P 4750 8250
+F 0 "U1" H 4800 8350 30 0000 C CNN
+F 1 "PORT" H 4750 8250 30 0000 C CNN
+F 2 "" H 4750 8250 60 0000 C CNN
+F 3 "" H 4750 8250 60 0000 C CNN
+ 2 4750 8250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68699237
+P 6450 9700
+F 0 "U1" H 6500 9800 30 0000 C CNN
+F 1 "PORT" H 6450 9700 30 0000 C CNN
+F 2 "" H 6450 9700 60 0000 C CNN
+F 3 "" H 6450 9700 60 0000 C CNN
+ 3 6450 9700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6869927E
+P 28700 8850
+F 0 "U1" H 28750 8950 30 0000 C CNN
+F 1 "PORT" H 28700 8850 30 0000 C CNN
+F 2 "" H 28700 8850 60 0000 C CNN
+F 3 "" H 28700 8850 60 0000 C CNN
+ 4 28700 8850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686992CD
+P 7000 9850
+F 0 "U1" H 7050 9950 30 0000 C CNN
+F 1 "PORT" H 7000 9850 30 0000 C CNN
+F 2 "" H 7000 9850 60 0000 C CNN
+F 3 "" H 7000 9850 60 0000 C CNN
+ 5 7000 9850
+ 1 0 0 -1
+$EndComp
+NoConn ~ 6700 9700
+NoConn ~ 7250 9850
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sub b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sub
new file mode 100644
index 000000000..1f6ad5429
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212.sub
@@ -0,0 +1,27 @@
+* Subcircuit 74AHC1G4212
+.subckt 74AHC1G4212 net-_u1-pad1_ net-_u1-pad2_ ? net-_u1-pad4_ ?
+* d:\fossee\esim\library\subcircuitlibrary\74ahc1g4212\74ahc1g4212.cir
+.include dff.sub
+x1 net-_x1-pad1_ net-_u1-pad2_ ? net-_x1-pad1_ ? ? dff
+x2 net-_x2-pad1_ net-_x1-pad1_ ? net-_x2-pad1_ ? ? dff
+x3 net-_x3-pad1_ net-_x2-pad1_ ? net-_x3-pad1_ ? ? dff
+x4 net-_x4-pad1_ net-_x3-pad1_ ? net-_x4-pad1_ ? ? dff
+x5 ? net-_x4-pad1_ ? net-_x5-pad4_ ? net-_x5-pad4_ dff
+x6 net-_x6-pad1_ net-_x5-pad4_ ? net-_x6-pad1_ ? ? dff
+x7 net-_x7-pad1_ net-_x6-pad1_ ? net-_x7-pad1_ ? ? dff
+x8 net-_x8-pad1_ net-_x7-pad1_ ? net-_x8-pad1_ ? ? dff
+x9 net-_x10-pad2_ net-_x8-pad1_ ? net-_x10-pad2_ ? ? dff
+x10 net-_x10-pad1_ net-_x10-pad2_ ? net-_x10-pad1_ ? ? dff
+x11 net-_x11-pad1_ net-_x10-pad1_ ? net-_x11-pad1_ ? ? dff
+x12 net-_u3-pad1_ net-_x11-pad1_ ? net-_u3-pad1_ ? ? dff
+* u3 net-_u3-pad1_ net-_u1-pad4_ d_inverter
+* u2 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+a1 net-_u3-pad1_ net-_u1-pad4_ u3
+a2 net-_u1-pad1_ net-_u1-pad2_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74AHC1G4212
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212_Previous_Values.xml b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212_Previous_Values.xml
new file mode 100644
index 000000000..70969fd15
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/74AHC1G4212_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dffD:\FOSSEE\eSim\library\SubcircuitLibrary\dff
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4212/analysis b/library/SubcircuitLibrary/74AHC1G4212/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff-cache.lib b/library/SubcircuitLibrary/74AHC1G4212/dff-cache.lib
new file mode 100644
index 000000000..440552005
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/dff-cache.lib
@@ -0,0 +1,92 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.cir b/library/SubcircuitLibrary/74AHC1G4212/dff.cir
new file mode 100644
index 000000000..883325a5e
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/dff.cir
@@ -0,0 +1,18 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\dff\dff.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 11:41:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_nand
+U4 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U4-Pad3_ d_nand
+U5 Net-_U2-Pad6_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_and
+U6 Net-_U4-Pad3_ Net-_U2-Pad3_ Net-_U6-Pad3_ d_and
+U7 Net-_U2-Pad4_ Net-_U5-Pad3_ Net-_U2-Pad5_ d_nand
+U8 Net-_U2-Pad5_ Net-_U6-Pad3_ Net-_U2-Pad4_ d_nand
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.cir.out b/library/SubcircuitLibrary/74AHC1G4212/dff.cir.out
new file mode 100644
index 000000000..849212938
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/dff.cir.out
@@ -0,0 +1,40 @@
+* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir
+
+* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand
+* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and
+* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand
+* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port
+a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6
+a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7
+a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8
+a7 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.pro b/library/SubcircuitLibrary/74AHC1G4212/dff.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/dff.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.sch b/library/SubcircuitLibrary/74AHC1G4212/dff.sch
new file mode 100644
index 000000000..675737646
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/dff.sch
@@ -0,0 +1,273 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nand U3
+U 1 1 6851060F
+P 3700 2300
+F 0 "U3" H 3700 2300 60 0000 C CNN
+F 1 "d_nand" H 3750 2400 60 0000 C CNN
+F 2 "" H 3700 2300 60 0000 C CNN
+F 3 "" H 3700 2300 60 0000 C CNN
+ 1 3700 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 68510656
+P 3700 3300
+F 0 "U4" H 3700 3300 60 0000 C CNN
+F 1 "d_nand" H 3750 3400 60 0000 C CNN
+F 2 "" H 3700 3300 60 0000 C CNN
+F 3 "" H 3700 3300 60 0000 C CNN
+ 1 3700 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 68510666
+P 5400 2300
+F 0 "U5" H 5400 2300 60 0000 C CNN
+F 1 "d_and" H 5450 2400 60 0000 C CNN
+F 2 "" H 5400 2300 60 0000 C CNN
+F 3 "" H 5400 2300 60 0000 C CNN
+ 1 5400 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 685106C5
+P 5400 3300
+F 0 "U6" H 5400 3300 60 0000 C CNN
+F 1 "d_and" H 5450 3400 60 0000 C CNN
+F 2 "" H 5400 3300 60 0000 C CNN
+F 3 "" H 5400 3300 60 0000 C CNN
+ 1 5400 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U7
+U 1 1 685106D1
+P 7100 2300
+F 0 "U7" H 7100 2300 60 0000 C CNN
+F 1 "d_nand" H 7150 2400 60 0000 C CNN
+F 2 "" H 7100 2300 60 0000 C CNN
+F 3 "" H 7100 2300 60 0000 C CNN
+ 1 7100 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U8
+U 1 1 68510816
+P 7150 3300
+F 0 "U8" H 7150 3300 60 0000 C CNN
+F 1 "d_nand" H 7200 3400 60 0000 C CNN
+F 2 "" H 7150 3300 60 0000 C CNN
+F 3 "" H 7150 3300 60 0000 C CNN
+ 1 7150 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5850 3250 6150 3250
+Wire Wire Line
+ 6150 3250 6150 3300
+Wire Wire Line
+ 6150 3300 6700 3300
+Wire Wire Line
+ 5850 2250 6050 2250
+Wire Wire Line
+ 6050 2250 6050 2300
+Wire Wire Line
+ 6050 2300 6650 2300
+Wire Wire Line
+ 7550 2250 8000 2250
+Wire Wire Line
+ 7600 3250 8150 3250
+Wire Wire Line
+ 4950 2200 4750 2200
+Wire Wire Line
+ 4750 2200 4750 1750
+Wire Wire Line
+ 4950 3300 4750 3300
+Wire Wire Line
+ 4750 3300 4750 3800
+Wire Wire Line
+ 4150 3250 4500 3250
+Wire Wire Line
+ 4500 3250 4500 3200
+Wire Wire Line
+ 4500 3200 4950 3200
+Wire Wire Line
+ 4150 2250 4400 2250
+Wire Wire Line
+ 4400 2250 4400 2300
+Wire Wire Line
+ 4400 2300 4950 2300
+Wire Wire Line
+ 7850 2250 7850 2600
+Wire Wire Line
+ 7850 2600 6450 2600
+Wire Wire Line
+ 6450 2600 6450 3200
+Wire Wire Line
+ 6450 3200 6700 3200
+Connection ~ 7850 2250
+Wire Wire Line
+ 7750 3250 7750 2750
+Wire Wire Line
+ 7750 2750 6250 2750
+Wire Wire Line
+ 6250 2750 6250 2200
+Wire Wire Line
+ 6250 2200 6650 2200
+Connection ~ 7750 3250
+Wire Wire Line
+ 3250 2200 2100 2200
+Wire Wire Line
+ 3250 2300 3000 2300
+Wire Wire Line
+ 3000 2300 3000 3200
+Wire Wire Line
+ 3000 3200 3250 3200
+Wire Wire Line
+ 2300 2200 2300 3300
+Connection ~ 2300 2200
+$Comp
+L d_inverter U1
+U 1 1 68510965
+P 2700 3300
+F 0 "U1" H 2700 3200 60 0000 C CNN
+F 1 "d_inverter" H 2700 3450 60 0000 C CNN
+F 2 "" H 2750 3250 60 0000 C CNN
+F 3 "" H 2750 3250 60 0000 C CNN
+ 1 2700 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3000 3300 3250 3300
+Wire Wire Line
+ 2300 3300 2400 3300
+Wire Wire Line
+ 3000 2750 1950 2750
+Wire Wire Line
+ 1950 2750 1950 3750
+Connection ~ 3000 2750
+$Comp
+L PORT U2
+U 1 1 68510A2C
+P 1850 2200
+F 0 "U2" H 1900 2300 30 0000 C CNN
+F 1 "PORT" H 1850 2200 30 0000 C CNN
+F 2 "" H 1850 2200 60 0000 C CNN
+F 3 "" H 1850 2200 60 0000 C CNN
+ 1 1850 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 2 1 68510A87
+P 1700 3750
+F 0 "U2" H 1750 3850 30 0000 C CNN
+F 1 "PORT" H 1700 3750 30 0000 C CNN
+F 2 "" H 1700 3750 60 0000 C CNN
+F 3 "" H 1700 3750 60 0000 C CNN
+ 2 1700 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 3 1 68510ACA
+P 4500 3800
+F 0 "U2" H 4550 3900 30 0000 C CNN
+F 1 "PORT" H 4500 3800 30 0000 C CNN
+F 2 "" H 4500 3800 60 0000 C CNN
+F 3 "" H 4500 3800 60 0000 C CNN
+ 3 4500 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 5 1 68510AFD
+P 8000 2500
+F 0 "U2" H 8050 2600 30 0000 C CNN
+F 1 "PORT" H 8000 2500 30 0000 C CNN
+F 2 "" H 8000 2500 60 0000 C CNN
+F 3 "" H 8000 2500 60 0000 C CNN
+ 5 8000 2500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 4 1 68510B2C
+P 8150 3500
+F 0 "U2" H 8200 3600 30 0000 C CNN
+F 1 "PORT" H 8150 3500 30 0000 C CNN
+F 2 "" H 8150 3500 60 0000 C CNN
+F 3 "" H 8150 3500 60 0000 C CNN
+ 4 8150 3500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 6 1 68510B5D
+P 4500 1750
+F 0 "U2" H 4550 1850 30 0000 C CNN
+F 1 "PORT" H 4500 1750 30 0000 C CNN
+F 2 "" H 4500 1750 60 0000 C CNN
+F 3 "" H 4500 1750 60 0000 C CNN
+ 6 4500 1750
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff.sub b/library/SubcircuitLibrary/74AHC1G4212/dff.sub
new file mode 100644
index 000000000..885e878fc
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/dff.sub
@@ -0,0 +1,34 @@
+* Subcircuit dff
+.subckt dff net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_
+* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir
+* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand
+* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and
+* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand
+* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6
+a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7
+a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8
+a7 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends dff
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74AHC1G4212/dff_Previous_Values.xml b/library/SubcircuitLibrary/74AHC1G4212/dff_Previous_Values.xml
new file mode 100644
index 000000000..2a57486b8
--- /dev/null
+++ b/library/SubcircuitLibrary/74AHC1G4212/dff_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_andd_andd_nandd_nandd_inverter
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC563/74HC563-cache.lib b/library/SubcircuitLibrary/74HC563/74HC563-cache.lib
new file mode 100644
index 000000000..bdc2c17eb
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/74HC563-cache.lib
@@ -0,0 +1,89 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_tristate
+#
+DEF d_tristate U 0 40 Y Y 1 F N
+F0 "U" -250 250 60 H V C CNN
+F1 "d_tristate" -200 450 60 H V C CNN
+F2 "" -100 350 60 H V C CNN
+F3 "" -100 350 60 H V C CNN
+DRAW
+P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N
+X IN 1 -600 350 200 R 50 50 1 1 I
+X EN 2 -50 50 193 U 50 50 1 1 I
+X OUT 3 550 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dlatch_own
+#
+DEF dlatch_own X 0 40 Y Y 1 F N
+F0 "X" 0 -50 60 H V C CNN
+F1 "dlatch_own" 50 50 60 H V C CNN
+F2 "" 0 -50 60 H I C CNN
+F3 "" 0 -50 60 H I C CNN
+DRAW
+S -500 400 550 -550 0 1 0 N
+X D 1 -700 200 200 R 50 50 1 1 I
+X G 2 -700 -200 200 R 50 50 1 1 I
+X QBar 3 750 -200 200 L 50 50 1 1 O
+X Q 4 750 200 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC563/74HC563.cir b/library/SubcircuitLibrary/74HC563/74HC563.cir
new file mode 100644
index 000000000..58e66e0c1
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/74HC563.cir
@@ -0,0 +1,37 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\74HC563\74HC563.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/21/25 19:18:15
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U4 Net-_U4-Pad1_ Net-_U11-Pad2_ Net-_U4-Pad3_ d_tristate
+U5 Net-_U4-Pad3_ /19 d_inverter
+U1 /11 Net-_U1-Pad2_ d_inverter
+U2 /1 Net-_U11-Pad2_ d_inverter
+U8 Net-_U8-Pad1_ Net-_U11-Pad2_ Net-_U8-Pad3_ d_tristate
+U9 Net-_U8-Pad3_ /18 d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_tristate
+U12 Net-_U11-Pad3_ /17 d_inverter
+U14 Net-_U14-Pad1_ Net-_U11-Pad2_ Net-_U14-Pad3_ d_tristate
+U15 Net-_U14-Pad3_ /16 d_inverter
+U17 Net-_U17-Pad1_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_tristate
+U18 Net-_U17-Pad3_ /15 d_inverter
+U20 Net-_U20-Pad1_ Net-_U11-Pad2_ Net-_U20-Pad3_ d_tristate
+U21 Net-_U20-Pad3_ /14 d_inverter
+U23 Net-_U23-Pad1_ Net-_U11-Pad2_ Net-_U23-Pad3_ d_tristate
+U24 Net-_U23-Pad3_ /13 d_inverter
+U26 Net-_U26-Pad1_ Net-_U11-Pad2_ Net-_U26-Pad3_ d_tristate
+U27 Net-_U26-Pad3_ /12 d_inverter
+U7 /1 /2 /3 /4 /5 /6 /7 /8 /9 ? /11 /12 /13 /14 /15 /16 /17 /18 /19 ? PORT
+X1 /2 Net-_U1-Pad2_ ? Net-_U4-Pad1_ dlatch_own
+X2 /3 Net-_U1-Pad2_ ? Net-_U8-Pad1_ dlatch_own
+X3 /4 Net-_U1-Pad2_ ? Net-_U11-Pad1_ dlatch_own
+X4 /5 Net-_U1-Pad2_ ? Net-_U14-Pad1_ dlatch_own
+X5 /6 Net-_U1-Pad2_ ? Net-_U17-Pad1_ dlatch_own
+X6 /7 Net-_U1-Pad2_ ? Net-_U20-Pad1_ dlatch_own
+X7 /8 Net-_U1-Pad2_ ? Net-_U23-Pad1_ dlatch_own
+X8 /9 Net-_U1-Pad2_ ? Net-_U26-Pad1_ dlatch_own
+
+.end
diff --git a/library/SubcircuitLibrary/74HC563/74HC563.cir.out b/library/SubcircuitLibrary/74HC563/74HC563.cir.out
new file mode 100644
index 000000000..2bfd978f9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/74HC563.cir.out
@@ -0,0 +1,93 @@
+* d:\fossee\esim\library\subcircuitlibrary\74hc563\74hc563.cir
+
+.include dlatch_own.sub
+* u4 net-_u4-pad1_ net-_u11-pad2_ net-_u4-pad3_ d_tristate
+* u5 net-_u4-pad3_ /19 d_inverter
+* u1 /11 net-_u1-pad2_ d_inverter
+* u2 /1 net-_u11-pad2_ d_inverter
+* u8 net-_u8-pad1_ net-_u11-pad2_ net-_u8-pad3_ d_tristate
+* u9 net-_u8-pad3_ /18 d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_tristate
+* u12 net-_u11-pad3_ /17 d_inverter
+* u14 net-_u14-pad1_ net-_u11-pad2_ net-_u14-pad3_ d_tristate
+* u15 net-_u14-pad3_ /16 d_inverter
+* u17 net-_u17-pad1_ net-_u11-pad2_ net-_u17-pad3_ d_tristate
+* u18 net-_u17-pad3_ /15 d_inverter
+* u20 net-_u20-pad1_ net-_u11-pad2_ net-_u20-pad3_ d_tristate
+* u21 net-_u20-pad3_ /14 d_inverter
+* u23 net-_u23-pad1_ net-_u11-pad2_ net-_u23-pad3_ d_tristate
+* u24 net-_u23-pad3_ /13 d_inverter
+* u26 net-_u26-pad1_ net-_u11-pad2_ net-_u26-pad3_ d_tristate
+* u27 net-_u26-pad3_ /12 d_inverter
+* u7 /1 /2 /3 /4 /5 /6 /7 /8 /9 ? /11 /12 /13 /14 /15 /16 /17 /18 /19 ? port
+x1 /2 net-_u1-pad2_ ? net-_u4-pad1_ dlatch_own
+x2 /3 net-_u1-pad2_ ? net-_u8-pad1_ dlatch_own
+x3 /4 net-_u1-pad2_ ? net-_u11-pad1_ dlatch_own
+x4 /5 net-_u1-pad2_ ? net-_u14-pad1_ dlatch_own
+x5 /6 net-_u1-pad2_ ? net-_u17-pad1_ dlatch_own
+x6 /7 net-_u1-pad2_ ? net-_u20-pad1_ dlatch_own
+x7 /8 net-_u1-pad2_ ? net-_u23-pad1_ dlatch_own
+x8 /9 net-_u1-pad2_ ? net-_u26-pad1_ dlatch_own
+a1 net-_u4-pad1_ net-_u11-pad2_ net-_u4-pad3_ u4
+a2 net-_u4-pad3_ /19 u5
+a3 /11 net-_u1-pad2_ u1
+a4 /1 net-_u11-pad2_ u2
+a5 net-_u8-pad1_ net-_u11-pad2_ net-_u8-pad3_ u8
+a6 net-_u8-pad3_ /18 u9
+a7 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ u11
+a8 net-_u11-pad3_ /17 u12
+a9 net-_u14-pad1_ net-_u11-pad2_ net-_u14-pad3_ u14
+a10 net-_u14-pad3_ /16 u15
+a11 net-_u17-pad1_ net-_u11-pad2_ net-_u17-pad3_ u17
+a12 net-_u17-pad3_ /15 u18
+a13 net-_u20-pad1_ net-_u11-pad2_ net-_u20-pad3_ u20
+a14 net-_u20-pad3_ /14 u21
+a15 net-_u23-pad1_ net-_u11-pad2_ net-_u23-pad3_ u23
+a16 net-_u23-pad3_ /13 u24
+a17 net-_u26-pad1_ net-_u11-pad2_ net-_u26-pad3_ u26
+a18 net-_u26-pad3_ /12 u27
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC563/74HC563.pro b/library/SubcircuitLibrary/74HC563/74HC563.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/74HC563.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC563/74HC563.sch b/library/SubcircuitLibrary/74HC563/74HC563.sch
new file mode 100644
index 000000000..d100461d9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/74HC563.sch
@@ -0,0 +1,831 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74HC563-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_tristate U4
+U 1 1 6856A572
+P 7800 5900
+F 0 "U4" H 7550 6150 60 0000 C CNN
+F 1 "d_tristate" H 7600 6350 60 0000 C CNN
+F 2 "" H 7700 6250 60 0000 C CNN
+F 3 "" H 7700 6250 60 0000 C CNN
+ 1 7800 5900
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 6856A681
+P 8150 7050
+F 0 "U5" H 8150 6950 60 0000 C CNN
+F 1 "d_inverter" H 8150 7200 60 0000 C CNN
+F 2 "" H 8200 7000 60 0000 C CNN
+F 3 "" H 8200 7000 60 0000 C CNN
+ 1 8150 7050
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U1
+U 1 1 6856A7FD
+P 5650 5300
+F 0 "U1" H 5650 5200 60 0000 C CNN
+F 1 "d_inverter" H 5650 5450 60 0000 C CNN
+F 2 "" H 5700 5250 60 0000 C CNN
+F 3 "" H 5700 5250 60 0000 C CNN
+ 1 5650 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 6856A88B
+P 5700 6650
+F 0 "U2" H 5700 6550 60 0000 C CNN
+F 1 "d_inverter" H 5700 6800 60 0000 C CNN
+F 2 "" H 5750 6600 60 0000 C CNN
+F 3 "" H 5750 6600 60 0000 C CNN
+ 1 5700 6650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_tristate U8
+U 1 1 6856AEA8
+P 9850 5950
+F 0 "U8" H 9600 6200 60 0000 C CNN
+F 1 "d_tristate" H 9650 6400 60 0000 C CNN
+F 2 "" H 9750 6300 60 0000 C CNN
+F 3 "" H 9750 6300 60 0000 C CNN
+ 1 9850 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 6856AEAE
+P 10200 7100
+F 0 "U9" H 10200 7000 60 0000 C CNN
+F 1 "d_inverter" H 10200 7250 60 0000 C CNN
+F 2 "" H 10250 7050 60 0000 C CNN
+F 3 "" H 10250 7050 60 0000 C CNN
+ 1 10200 7100
+ 0 1 1 0
+$EndComp
+$Comp
+L d_tristate U11
+U 1 1 6856B40C
+P 12050 6000
+F 0 "U11" H 11800 6250 60 0000 C CNN
+F 1 "d_tristate" H 11850 6450 60 0000 C CNN
+F 2 "" H 11950 6350 60 0000 C CNN
+F 3 "" H 11950 6350 60 0000 C CNN
+ 1 12050 6000
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 6856B412
+P 12400 7150
+F 0 "U12" H 12400 7050 60 0000 C CNN
+F 1 "d_inverter" H 12400 7300 60 0000 C CNN
+F 2 "" H 12450 7100 60 0000 C CNN
+F 3 "" H 12450 7100 60 0000 C CNN
+ 1 12400 7150
+ 0 1 1 0
+$EndComp
+$Comp
+L d_tristate U14
+U 1 1 6856B422
+P 14100 6050
+F 0 "U14" H 13850 6300 60 0000 C CNN
+F 1 "d_tristate" H 13900 6500 60 0000 C CNN
+F 2 "" H 14000 6400 60 0000 C CNN
+F 3 "" H 14000 6400 60 0000 C CNN
+ 1 14100 6050
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U15
+U 1 1 6856B428
+P 14450 7200
+F 0 "U15" H 14450 7100 60 0000 C CNN
+F 1 "d_inverter" H 14450 7350 60 0000 C CNN
+F 2 "" H 14500 7150 60 0000 C CNN
+F 3 "" H 14500 7150 60 0000 C CNN
+ 1 14450 7200
+ 0 1 1 0
+$EndComp
+$Comp
+L d_tristate U17
+U 1 1 6856D4A0
+P 16250 6000
+F 0 "U17" H 16000 6250 60 0000 C CNN
+F 1 "d_tristate" H 16050 6450 60 0000 C CNN
+F 2 "" H 16150 6350 60 0000 C CNN
+F 3 "" H 16150 6350 60 0000 C CNN
+ 1 16250 6000
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U18
+U 1 1 6856D4A6
+P 16600 7250
+F 0 "U18" H 16600 7150 60 0000 C CNN
+F 1 "d_inverter" H 16600 7400 60 0000 C CNN
+F 2 "" H 16650 7200 60 0000 C CNN
+F 3 "" H 16650 7200 60 0000 C CNN
+ 1 16600 7250
+ 0 1 1 0
+$EndComp
+$Comp
+L d_tristate U20
+U 1 1 6856D4B6
+P 18300 5950
+F 0 "U20" H 18050 6200 60 0000 C CNN
+F 1 "d_tristate" H 18100 6400 60 0000 C CNN
+F 2 "" H 18200 6300 60 0000 C CNN
+F 3 "" H 18200 6300 60 0000 C CNN
+ 1 18300 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 6856D4BC
+P 18650 7300
+F 0 "U21" H 18650 7200 60 0000 C CNN
+F 1 "d_inverter" H 18650 7450 60 0000 C CNN
+F 2 "" H 18700 7250 60 0000 C CNN
+F 3 "" H 18700 7250 60 0000 C CNN
+ 1 18650 7300
+ 0 1 1 0
+$EndComp
+$Comp
+L d_tristate U23
+U 1 1 6856D4CC
+P 20500 6200
+F 0 "U23" H 20250 6450 60 0000 C CNN
+F 1 "d_tristate" H 20300 6650 60 0000 C CNN
+F 2 "" H 20400 6550 60 0000 C CNN
+F 3 "" H 20400 6550 60 0000 C CNN
+ 1 20500 6200
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U24
+U 1 1 6856D4D2
+P 20850 7350
+F 0 "U24" H 20850 7250 60 0000 C CNN
+F 1 "d_inverter" H 20850 7500 60 0000 C CNN
+F 2 "" H 20900 7300 60 0000 C CNN
+F 3 "" H 20900 7300 60 0000 C CNN
+ 1 20850 7350
+ 0 1 1 0
+$EndComp
+$Comp
+L d_tristate U26
+U 1 1 6856D4E2
+P 22550 6250
+F 0 "U26" H 22300 6500 60 0000 C CNN
+F 1 "d_tristate" H 22350 6700 60 0000 C CNN
+F 2 "" H 22450 6600 60 0000 C CNN
+F 3 "" H 22450 6600 60 0000 C CNN
+ 1 22550 6250
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U27
+U 1 1 6856D4E8
+P 22900 7400
+F 0 "U27" H 22900 7300 60 0000 C CNN
+F 1 "d_inverter" H 22900 7550 60 0000 C CNN
+F 2 "" H 22950 7350 60 0000 C CNN
+F 3 "" H 22950 7350 60 0000 C CNN
+ 1 22900 7400
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 8150 4100 8150 5300
+Wire Wire Line
+ 8150 6450 8150 6750
+Wire Wire Line
+ 8150 7350 8150 7700
+Wire Wire Line
+ 10200 4100 10200 5350
+Wire Wire Line
+ 10200 6500 10200 6800
+Wire Wire Line
+ 10200 7400 10200 7750
+Wire Wire Line
+ 12400 4150 12400 5400
+Wire Wire Line
+ 12400 6550 12400 6850
+Wire Wire Line
+ 12400 7450 12400 7800
+Wire Wire Line
+ 14450 4100 14450 5450
+Wire Wire Line
+ 14450 6600 14450 6900
+Wire Wire Line
+ 14450 7500 14450 7850
+Wire Wire Line
+ 16600 6550 16600 6950
+Wire Wire Line
+ 16600 7550 16600 7900
+Wire Wire Line
+ 18650 6500 18650 7000
+Wire Wire Line
+ 18650 7600 18650 7950
+Wire Wire Line
+ 20850 4250 20850 5600
+Wire Wire Line
+ 20850 6750 20850 7050
+Wire Wire Line
+ 20850 7650 20850 8000
+Wire Wire Line
+ 22900 4300 22900 5650
+Wire Wire Line
+ 22900 6800 22900 7100
+Wire Wire Line
+ 22900 7700 22900 8050
+Wire Wire Line
+ 6000 6650 19350 6650
+Wire Wire Line
+ 16600 4150 16600 5400
+Wire Wire Line
+ 19350 6650 19350 6900
+Wire Wire Line
+ 19350 6900 21700 6900
+Wire Wire Line
+ 21700 6900 21700 6200
+Wire Wire Line
+ 21700 6200 22600 6200
+Wire Wire Line
+ 20550 6150 20300 6150
+Wire Wire Line
+ 20300 6150 20300 6900
+Connection ~ 20300 6900
+Wire Wire Line
+ 18350 5900 17850 5900
+Wire Wire Line
+ 17850 5900 17850 6650
+Connection ~ 17850 6650
+Wire Wire Line
+ 16300 5950 15750 5950
+Wire Wire Line
+ 15750 5950 15750 6650
+Connection ~ 15750 6650
+Wire Wire Line
+ 14150 6000 13550 6000
+Wire Wire Line
+ 13550 6000 13550 6650
+Connection ~ 13550 6650
+Wire Wire Line
+ 12100 5950 11450 5950
+Wire Wire Line
+ 11450 5950 11450 6650
+Connection ~ 11450 6650
+Wire Wire Line
+ 9900 5900 9350 5900
+Wire Wire Line
+ 9350 5900 9350 6650
+Connection ~ 9350 6650
+Wire Wire Line
+ 7850 5850 7250 5850
+Wire Wire Line
+ 7250 5850 7250 6650
+Connection ~ 7250 6650
+Wire Wire Line
+ 18650 4200 18650 5350
+Wire Wire Line
+ 5950 5300 7050 5300
+Wire Wire Line
+ 7050 5300 7050 5100
+Wire Wire Line
+ 7050 5100 12800 5100
+Wire Wire Line
+ 12800 5100 12800 5250
+Wire Wire Line
+ 12800 5250 19050 5250
+Wire Wire Line
+ 19050 5250 19050 5350
+Wire Wire Line
+ 19050 5350 21000 5350
+Wire Wire Line
+ 21000 5350 21000 4700
+Wire Wire Line
+ 18800 5250 18800 4900
+Wire Wire Line
+ 18800 4900 19100 4900
+Connection ~ 18800 5250
+Wire Wire Line
+ 16700 5250 16700 4850
+Wire Wire Line
+ 16700 4850 16900 4850
+Connection ~ 16700 5250
+Wire Wire Line
+ 14600 5250 14600 4800
+Wire Wire Line
+ 14600 4800 14850 4800
+Connection ~ 14600 5250
+Wire Wire Line
+ 12500 5100 12500 4750
+Wire Wire Line
+ 12500 4750 12700 4750
+Connection ~ 12500 5100
+Wire Wire Line
+ 10350 4550 10350 5100
+Connection ~ 10350 5100
+Wire Wire Line
+ 8300 4500 8300 5100
+Connection ~ 8300 5100
+Wire Wire Line
+ 6100 4500 6100 5300
+Connection ~ 6100 5300
+Wire Wire Line
+ 5400 6650 5100 6650
+Wire Wire Line
+ 5350 5300 5050 5300
+Wire Wire Line
+ 6050 3200 6050 4100
+Wire Wire Line
+ 8300 3200 8300 4100
+Wire Wire Line
+ 10450 3200 10450 4150
+Wire Wire Line
+ 12550 4100 12800 4100
+Wire Wire Line
+ 12550 4100 12550 3150
+Wire Wire Line
+ 14650 4150 14950 4150
+Wire Wire Line
+ 14650 4150 14650 3300
+Wire Wire Line
+ 16900 4200 16750 4200
+Wire Wire Line
+ 16750 4200 16750 3300
+Wire Wire Line
+ 19100 4250 18850 4250
+Wire Wire Line
+ 18850 4250 18850 3350
+Wire Wire Line
+ 21150 4300 20950 4300
+Wire Wire Line
+ 20950 4300 20950 3400
+$Comp
+L PORT U7
+U 1 1 68589A5A
+P 4850 6650
+F 0 "U7" H 4900 6750 30 0000 C CNN
+F 1 "PORT" H 4850 6650 30 0000 C CNN
+F 2 "" H 4850 6650 60 0000 C CNN
+F 3 "" H 4850 6650 60 0000 C CNN
+ 1 4850 6650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 5 1 68589B7D
+P 12300 3150
+F 0 "U7" H 12350 3250 30 0000 C CNN
+F 1 "PORT" H 12300 3150 30 0000 C CNN
+F 2 "" H 12300 3150 60 0000 C CNN
+F 3 "" H 12300 3150 60 0000 C CNN
+ 5 12300 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 9 1 68589BCA
+P 20700 3400
+F 0 "U7" H 20750 3500 30 0000 C CNN
+F 1 "PORT" H 20700 3400 30 0000 C CNN
+F 2 "" H 20700 3400 60 0000 C CNN
+F 3 "" H 20700 3400 60 0000 C CNN
+ 9 20700 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 13 1 68589C1D
+P 20850 8250
+F 0 "U7" H 20900 8350 30 0000 C CNN
+F 1 "PORT" H 20850 8250 30 0000 C CNN
+F 2 "" H 20850 8250 60 0000 C CNN
+F 3 "" H 20850 8250 60 0000 C CNN
+ 13 20850 8250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U7
+U 17 1 68589C74
+P 12400 8050
+F 0 "U7" H 12450 8150 30 0000 C CNN
+F 1 "PORT" H 12400 8050 30 0000 C CNN
+F 2 "" H 12400 8050 60 0000 C CNN
+F 3 "" H 12400 8050 60 0000 C CNN
+ 17 12400 8050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U7
+U 2 1 68589CCB
+P 5800 3200
+F 0 "U7" H 5850 3300 30 0000 C CNN
+F 1 "PORT" H 5800 3200 30 0000 C CNN
+F 2 "" H 5800 3200 60 0000 C CNN
+F 3 "" H 5800 3200 60 0000 C CNN
+ 2 5800 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 6 1 68589D22
+P 14400 3300
+F 0 "U7" H 14450 3400 30 0000 C CNN
+F 1 "PORT" H 14400 3300 30 0000 C CNN
+F 2 "" H 14400 3300 60 0000 C CNN
+F 3 "" H 14400 3300 60 0000 C CNN
+ 6 14400 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 10 1 68589D79
+P 4550 4400
+F 0 "U7" H 4600 4500 30 0000 C CNN
+F 1 "PORT" H 4550 4400 30 0000 C CNN
+F 2 "" H 4550 4400 60 0000 C CNN
+F 3 "" H 4550 4400 60 0000 C CNN
+ 10 4550 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 14 1 68589DD2
+P 18650 8200
+F 0 "U7" H 18700 8300 30 0000 C CNN
+F 1 "PORT" H 18650 8200 30 0000 C CNN
+F 2 "" H 18650 8200 60 0000 C CNN
+F 3 "" H 18650 8200 60 0000 C CNN
+ 14 18650 8200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U7
+U 18 1 68589E33
+P 10200 8000
+F 0 "U7" H 10250 8100 30 0000 C CNN
+F 1 "PORT" H 10200 8000 30 0000 C CNN
+F 2 "" H 10200 8000 60 0000 C CNN
+F 3 "" H 10200 8000 60 0000 C CNN
+ 18 10200 8000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U7
+U 3 1 68589E94
+P 8050 3200
+F 0 "U7" H 8100 3300 30 0000 C CNN
+F 1 "PORT" H 8050 3200 30 0000 C CNN
+F 2 "" H 8050 3200 60 0000 C CNN
+F 3 "" H 8050 3200 60 0000 C CNN
+ 3 8050 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 7 1 68589EF3
+P 16500 3300
+F 0 "U7" H 16550 3400 30 0000 C CNN
+F 1 "PORT" H 16500 3300 30 0000 C CNN
+F 2 "" H 16500 3300 60 0000 C CNN
+F 3 "" H 16500 3300 60 0000 C CNN
+ 7 16500 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 11 1 68589F54
+P 4800 5300
+F 0 "U7" H 4850 5400 30 0000 C CNN
+F 1 "PORT" H 4800 5300 30 0000 C CNN
+F 2 "" H 4800 5300 60 0000 C CNN
+F 3 "" H 4800 5300 60 0000 C CNN
+ 11 4800 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 15 1 68589FBB
+P 16600 8150
+F 0 "U7" H 16650 8250 30 0000 C CNN
+F 1 "PORT" H 16600 8150 30 0000 C CNN
+F 2 "" H 16600 8150 60 0000 C CNN
+F 3 "" H 16600 8150 60 0000 C CNN
+ 15 16600 8150
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U7
+U 19 1 6858A022
+P 8150 7950
+F 0 "U7" H 8200 8050 30 0000 C CNN
+F 1 "PORT" H 8150 7950 30 0000 C CNN
+F 2 "" H 8150 7950 60 0000 C CNN
+F 3 "" H 8150 7950 60 0000 C CNN
+ 19 8150 7950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U7
+U 4 1 6858A089
+P 10200 3200
+F 0 "U7" H 10250 3300 30 0000 C CNN
+F 1 "PORT" H 10200 3200 30 0000 C CNN
+F 2 "" H 10200 3200 60 0000 C CNN
+F 3 "" H 10200 3200 60 0000 C CNN
+ 4 10200 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 8 1 6858A0F8
+P 18600 3350
+F 0 "U7" H 18650 3450 30 0000 C CNN
+F 1 "PORT" H 18600 3350 30 0000 C CNN
+F 2 "" H 18600 3350 60 0000 C CNN
+F 3 "" H 18600 3350 60 0000 C CNN
+ 8 18600 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U7
+U 12 1 6858A167
+P 22900 8300
+F 0 "U7" H 22950 8400 30 0000 C CNN
+F 1 "PORT" H 22900 8300 30 0000 C CNN
+F 2 "" H 22900 8300 60 0000 C CNN
+F 3 "" H 22900 8300 60 0000 C CNN
+ 12 22900 8300
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U7
+U 16 1 6858A1D4
+P 14450 8100
+F 0 "U7" H 14500 8200 30 0000 C CNN
+F 1 "PORT" H 14450 8100 30 0000 C CNN
+F 2 "" H 14450 8100 60 0000 C CNN
+F 3 "" H 14450 8100 60 0000 C CNN
+ 16 14450 8100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U7
+U 20 1 6858A243
+P 4550 4600
+F 0 "U7" H 4600 4700 30 0000 C CNN
+F 1 "PORT" H 4550 4600 30 0000 C CNN
+F 2 "" H 4550 4600 60 0000 C CNN
+F 3 "" H 4550 4600 60 0000 C CNN
+ 20 4550 4600
+ 1 0 0 -1
+$EndComp
+Text Label 5100 6650 0 60 ~ 0
+1
+Text Label 6050 3200 0 60 ~ 0
+2
+Text Label 8300 3200 0 60 ~ 0
+3
+Text Label 10450 3200 0 60 ~ 0
+4
+Text Label 12550 3150 0 60 ~ 0
+5
+Text Label 14650 3300 0 60 ~ 0
+6
+Text Label 16750 3300 0 60 ~ 0
+7
+Text Label 18850 3350 0 60 ~ 0
+8
+Text Label 20950 3400 0 60 ~ 0
+9
+Text Label 5050 5300 0 60 ~ 0
+11
+Text Label 22900 8050 0 60 ~ 0
+12
+Text Label 20850 8000 0 60 ~ 0
+13
+Text Label 18650 7950 0 60 ~ 0
+14
+Text Label 16600 7900 0 60 ~ 0
+15
+Text Label 14450 7850 0 60 ~ 0
+16
+Text Label 12400 7800 0 60 ~ 0
+17
+Text Label 10200 7750 0 60 ~ 0
+18
+Text Label 8150 7700 0 60 ~ 0
+19
+NoConn ~ 4800 4400
+NoConn ~ 4800 4600
+$Comp
+L dlatch_own X1
+U 1 1 6856BAE2
+P 7000 4300
+F 0 "X1" H 7000 4250 60 0000 C CNN
+F 1 "dlatch_own" H 7050 4350 60 0000 C CNN
+F 2 "" H 7000 4250 60 0001 C CNN
+F 3 "" H 7000 4250 60 0001 C CNN
+ 1 7000 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6050 4100 6300 4100
+Wire Wire Line
+ 6100 4500 6300 4500
+Wire Wire Line
+ 7750 4100 8150 4100
+NoConn ~ 7750 4500
+$Comp
+L dlatch_own X2
+U 1 1 6856C093
+P 9100 4300
+F 0 "X2" H 9100 4250 60 0000 C CNN
+F 1 "dlatch_own" H 9150 4350 60 0000 C CNN
+F 2 "" H 9100 4250 60 0001 C CNN
+F 3 "" H 9100 4250 60 0001 C CNN
+ 1 9100 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10200 4100 9850 4100
+Wire Wire Line
+ 8300 4100 8400 4100
+Wire Wire Line
+ 8300 4500 8400 4500
+NoConn ~ 9850 4500
+$Comp
+L dlatch_own X3
+U 1 1 6856CA39
+P 11300 4350
+F 0 "X3" H 11300 4300 60 0000 C CNN
+F 1 "dlatch_own" H 11350 4400 60 0000 C CNN
+F 2 "" H 11300 4300 60 0001 C CNN
+F 3 "" H 11300 4300 60 0001 C CNN
+ 1 11300 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10450 4150 10600 4150
+Wire Wire Line
+ 10350 4550 10600 4550
+NoConn ~ 12050 4550
+Wire Wire Line
+ 12050 4150 12400 4150
+$Comp
+L dlatch_own X4
+U 1 1 6856E6F1
+P 13500 4300
+F 0 "X4" H 13500 4250 60 0000 C CNN
+F 1 "dlatch_own" H 13550 4350 60 0000 C CNN
+F 2 "" H 13500 4250 60 0001 C CNN
+F 3 "" H 13500 4250 60 0001 C CNN
+ 1 13500 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 14450 4100 14250 4100
+Wire Wire Line
+ 12700 4750 12700 4500
+Wire Wire Line
+ 12700 4500 12800 4500
+NoConn ~ 14250 4500
+$Comp
+L dlatch_own X5
+U 1 1 6856E9A6
+P 15650 4350
+F 0 "X5" H 15650 4300 60 0000 C CNN
+F 1 "dlatch_own" H 15700 4400 60 0000 C CNN
+F 2 "" H 15650 4300 60 0001 C CNN
+F 3 "" H 15650 4300 60 0001 C CNN
+ 1 15650 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 14850 4800 14850 4550
+Wire Wire Line
+ 14850 4550 14950 4550
+Wire Wire Line
+ 16600 4150 16400 4150
+NoConn ~ 16400 4550
+$Comp
+L dlatch_own X6
+U 1 1 6856F59B
+P 17600 4400
+F 0 "X6" H 17600 4350 60 0000 C CNN
+F 1 "dlatch_own" H 17650 4450 60 0000 C CNN
+F 2 "" H 17600 4350 60 0001 C CNN
+F 3 "" H 17600 4350 60 0001 C CNN
+ 1 17600 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 18350 4200 18650 4200
+NoConn ~ 18350 4600
+Wire Wire Line
+ 16900 4850 16900 4750
+Wire Wire Line
+ 16900 4750 16700 4750
+Wire Wire Line
+ 16700 4750 16700 4600
+Wire Wire Line
+ 16700 4600 16900 4600
+$Comp
+L dlatch_own X7
+U 1 1 68570F1C
+P 19800 4450
+F 0 "X7" H 19800 4400 60 0000 C CNN
+F 1 "dlatch_own" H 19850 4500 60 0000 C CNN
+F 2 "" H 19800 4400 60 0001 C CNN
+F 3 "" H 19800 4400 60 0001 C CNN
+ 1 19800 4450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 20550 4250 20850 4250
+NoConn ~ 20550 4650
+Wire Wire Line
+ 19100 4900 19100 4800
+Wire Wire Line
+ 19100 4800 18850 4800
+Wire Wire Line
+ 18850 4800 18850 4650
+Wire Wire Line
+ 18850 4650 19100 4650
+$Comp
+L dlatch_own X8
+U 1 1 68571CD8
+P 21850 4500
+F 0 "X8" H 21850 4450 60 0000 C CNN
+F 1 "dlatch_own" H 21900 4550 60 0000 C CNN
+F 2 "" H 21850 4450 60 0001 C CNN
+F 3 "" H 21850 4450 60 0001 C CNN
+ 1 21850 4500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 22600 4300 22900 4300
+NoConn ~ 22600 4700
+Wire Wire Line
+ 21000 4700 21150 4700
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC563/74HC563.sub b/library/SubcircuitLibrary/74HC563/74HC563.sub
new file mode 100644
index 000000000..7c25f3637
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/74HC563.sub
@@ -0,0 +1,87 @@
+* Subcircuit 74HC563
+.subckt 74HC563 /1 /2 /3 /4 /5 /6 /7 /8 /9 ? /11 /12 /13 /14 /15 /16 /17 /18 /19 ?
+* d:\fossee\esim\library\subcircuitlibrary\74hc563\74hc563.cir
+.include dlatch_own.sub
+* u4 net-_u4-pad1_ net-_u11-pad2_ net-_u4-pad3_ d_tristate
+* u5 net-_u4-pad3_ /19 d_inverter
+* u1 /11 net-_u1-pad2_ d_inverter
+* u2 /1 net-_u11-pad2_ d_inverter
+* u8 net-_u8-pad1_ net-_u11-pad2_ net-_u8-pad3_ d_tristate
+* u9 net-_u8-pad3_ /18 d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_tristate
+* u12 net-_u11-pad3_ /17 d_inverter
+* u14 net-_u14-pad1_ net-_u11-pad2_ net-_u14-pad3_ d_tristate
+* u15 net-_u14-pad3_ /16 d_inverter
+* u17 net-_u17-pad1_ net-_u11-pad2_ net-_u17-pad3_ d_tristate
+* u18 net-_u17-pad3_ /15 d_inverter
+* u20 net-_u20-pad1_ net-_u11-pad2_ net-_u20-pad3_ d_tristate
+* u21 net-_u20-pad3_ /14 d_inverter
+* u23 net-_u23-pad1_ net-_u11-pad2_ net-_u23-pad3_ d_tristate
+* u24 net-_u23-pad3_ /13 d_inverter
+* u26 net-_u26-pad1_ net-_u11-pad2_ net-_u26-pad3_ d_tristate
+* u27 net-_u26-pad3_ /12 d_inverter
+x1 /2 net-_u1-pad2_ ? net-_u4-pad1_ dlatch_own
+x2 /3 net-_u1-pad2_ ? net-_u8-pad1_ dlatch_own
+x3 /4 net-_u1-pad2_ ? net-_u11-pad1_ dlatch_own
+x4 /5 net-_u1-pad2_ ? net-_u14-pad1_ dlatch_own
+x5 /6 net-_u1-pad2_ ? net-_u17-pad1_ dlatch_own
+x6 /7 net-_u1-pad2_ ? net-_u20-pad1_ dlatch_own
+x7 /8 net-_u1-pad2_ ? net-_u23-pad1_ dlatch_own
+x8 /9 net-_u1-pad2_ ? net-_u26-pad1_ dlatch_own
+a1 net-_u4-pad1_ net-_u11-pad2_ net-_u4-pad3_ u4
+a2 net-_u4-pad3_ /19 u5
+a3 /11 net-_u1-pad2_ u1
+a4 /1 net-_u11-pad2_ u2
+a5 net-_u8-pad1_ net-_u11-pad2_ net-_u8-pad3_ u8
+a6 net-_u8-pad3_ /18 u9
+a7 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ u11
+a8 net-_u11-pad3_ /17 u12
+a9 net-_u14-pad1_ net-_u11-pad2_ net-_u14-pad3_ u14
+a10 net-_u14-pad3_ /16 u15
+a11 net-_u17-pad1_ net-_u11-pad2_ net-_u17-pad3_ u17
+a12 net-_u17-pad3_ /15 u18
+a13 net-_u20-pad1_ net-_u11-pad2_ net-_u20-pad3_ u20
+a14 net-_u20-pad3_ /14 u21
+a15 net-_u23-pad1_ net-_u11-pad2_ net-_u23-pad3_ u23
+a16 net-_u23-pad3_ /13 u24
+a17 net-_u26-pad1_ net-_u11-pad2_ net-_u26-pad3_ u26
+a18 net-_u26-pad3_ /12 u27
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u4 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u11 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u14 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u17 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u20 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u23 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u26 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74HC563
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC563/74HC563_Previous_Values.xml b/library/SubcircuitLibrary/74HC563/74HC563_Previous_Values.xml
new file mode 100644
index 000000000..18576c0c0
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/74HC563_Previous_Values.xml
@@ -0,0 +1 @@
+d_dlatchd_tristated_inverterd_inverterd_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterd_dlatchd_tristated_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_ownD:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_owntruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC563/analysis b/library/SubcircuitLibrary/74HC563/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own-cache.lib b/library/SubcircuitLibrary/74HC563/dlatch_own-cache.lib
new file mode 100644
index 000000000..c743d042c
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/dlatch_own-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.cir b/library/SubcircuitLibrary/74HC563/dlatch_own.cir
new file mode 100644
index 000000000..f79b758d8
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/dlatch_own.cir
@@ -0,0 +1,16 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_own\dlatch_own.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/21/25 19:09:28
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_and
+U4 Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U4-Pad3_ d_and
+U5 Net-_U3-Pad3_ Net-_U2-Pad3_ Net-_U2-Pad4_ d_nor
+U6 Net-_U2-Pad4_ Net-_U4-Pad3_ Net-_U2-Pad3_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.cir.out b/library/SubcircuitLibrary/74HC563/dlatch_own.cir.out
new file mode 100644
index 000000000..5bcd05907
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/dlatch_own.cir.out
@@ -0,0 +1,32 @@
+* d:\fossee\esim\library\subcircuitlibrary\dlatch_own\dlatch_own.cir
+
+* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
+* u4 net-_u2-pad2_ net-_u1-pad1_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u2-pad3_ net-_u2-pad4_ d_nor
+* u6 net-_u2-pad4_ net-_u4-pad3_ net-_u2-pad3_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ port
+a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad1_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u2-pad3_ ] net-_u2-pad4_ u5
+a4 [net-_u2-pad4_ net-_u4-pad3_ ] net-_u2-pad3_ u6
+a5 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.pro b/library/SubcircuitLibrary/74HC563/dlatch_own.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/dlatch_own.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.sch b/library/SubcircuitLibrary/74HC563/dlatch_own.sch
new file mode 100644
index 000000000..9ed392a0c
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/dlatch_own.sch
@@ -0,0 +1,209 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U3
+U 1 1 6856B545
+P 4350 3350
+F 0 "U3" H 4350 3350 60 0000 C CNN
+F 1 "d_and" H 4400 3450 60 0000 C CNN
+F 2 "" H 4350 3350 60 0000 C CNN
+F 3 "" H 4350 3350 60 0000 C CNN
+ 1 4350 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 6856B5D2
+P 4400 4750
+F 0 "U4" H 4400 4750 60 0000 C CNN
+F 1 "d_and" H 4450 4850 60 0000 C CNN
+F 2 "" H 4400 4750 60 0000 C CNN
+F 3 "" H 4400 4750 60 0000 C CNN
+ 1 4400 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U5
+U 1 1 6856B5DC
+P 7300 3350
+F 0 "U5" H 7300 3350 60 0000 C CNN
+F 1 "d_nor" H 7350 3450 60 0000 C CNN
+F 2 "" H 7300 3350 60 0000 C CNN
+F 3 "" H 7300 3350 60 0000 C CNN
+ 1 7300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 6856B689
+P 7300 4750
+F 0 "U6" H 7300 4750 60 0000 C CNN
+F 1 "d_nor" H 7350 4850 60 0000 C CNN
+F 2 "" H 7300 4750 60 0000 C CNN
+F 3 "" H 7300 4750 60 0000 C CNN
+ 1 7300 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U1
+U 1 1 6856B986
+P 2800 3250
+F 0 "U1" H 2800 3150 60 0000 C CNN
+F 1 "d_inverter" H 2800 3400 60 0000 C CNN
+F 2 "" H 2850 3200 60 0000 C CNN
+F 3 "" H 2850 3200 60 0000 C CNN
+ 1 2800 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7750 3300 8750 3300
+Wire Wire Line
+ 7750 4700 9050 4700
+Wire Wire Line
+ 6850 4650 6500 4650
+Wire Wire Line
+ 6500 4650 6500 4300
+Wire Wire Line
+ 6500 4300 8400 4300
+Wire Wire Line
+ 8400 4300 8400 3300
+Connection ~ 8400 3300
+Wire Wire Line
+ 8250 4700 8250 3800
+Wire Wire Line
+ 8250 3800 6600 3800
+Wire Wire Line
+ 6600 3800 6600 3350
+Wire Wire Line
+ 6600 3350 6850 3350
+Connection ~ 8250 4700
+Wire Wire Line
+ 5150 4700 5150 4750
+Wire Wire Line
+ 5150 4750 6850 4750
+Wire Wire Line
+ 4850 4700 5150 4700
+Wire Wire Line
+ 4800 3300 6400 3300
+Wire Wire Line
+ 6400 3300 6400 3250
+Wire Wire Line
+ 6400 3250 6850 3250
+Wire Wire Line
+ 3900 3350 3450 3350
+Wire Wire Line
+ 3450 3350 3450 4650
+Wire Wire Line
+ 3450 4650 3950 4650
+Wire Wire Line
+ 3950 4750 2500 4750
+Wire Wire Line
+ 3100 3250 3900 3250
+Wire Wire Line
+ 2500 3250 2500 4150
+Wire Wire Line
+ 2500 4150 2800 4150
+Wire Wire Line
+ 2800 4150 2800 4750
+Connection ~ 2800 4750
+Wire Wire Line
+ 3450 3950 3200 3950
+Connection ~ 3450 3950
+$Comp
+L PORT U2
+U 1 1 6856BAF3
+P 2250 4750
+F 0 "U2" H 2300 4850 30 0000 C CNN
+F 1 "PORT" H 2250 4750 30 0000 C CNN
+F 2 "" H 2250 4750 60 0000 C CNN
+F 3 "" H 2250 4750 60 0000 C CNN
+ 1 2250 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 3 1 6856BB14
+P 9300 4700
+F 0 "U2" H 9350 4800 30 0000 C CNN
+F 1 "PORT" H 9300 4700 30 0000 C CNN
+F 2 "" H 9300 4700 60 0000 C CNN
+F 3 "" H 9300 4700 60 0000 C CNN
+ 3 9300 4700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U2
+U 2 1 6856BB59
+P 2950 3950
+F 0 "U2" H 3000 4050 30 0000 C CNN
+F 1 "PORT" H 2950 3950 30 0000 C CNN
+F 2 "" H 2950 3950 60 0000 C CNN
+F 3 "" H 2950 3950 60 0000 C CNN
+ 2 2950 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 4 1 6856BB9A
+P 9000 3300
+F 0 "U2" H 9050 3400 30 0000 C CNN
+F 1 "PORT" H 9000 3300 30 0000 C CNN
+F 2 "" H 9000 3300 60 0000 C CNN
+F 3 "" H 9000 3300 60 0000 C CNN
+ 4 9000 3300
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own.sub b/library/SubcircuitLibrary/74HC563/dlatch_own.sub
new file mode 100644
index 000000000..38e1779a5
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/dlatch_own.sub
@@ -0,0 +1,26 @@
+* Subcircuit dlatch_own
+.subckt dlatch_own net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_
+* d:\fossee\esim\library\subcircuitlibrary\dlatch_own\dlatch_own.cir
+* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
+* u4 net-_u2-pad2_ net-_u1-pad1_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u2-pad3_ net-_u2-pad4_ d_nor
+* u6 net-_u2-pad4_ net-_u4-pad3_ net-_u2-pad3_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad1_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u2-pad3_ ] net-_u2-pad4_ u5
+a4 [net-_u2-pad4_ net-_u4-pad3_ ] net-_u2-pad3_ u6
+a5 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends dlatch_own
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC563/dlatch_own_Previous_Values.xml b/library/SubcircuitLibrary/74HC563/dlatch_own_Previous_Values.xml
new file mode 100644
index 000000000..0a9ca5d55
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC563/dlatch_own_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_nord_nord_inverter
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74S182/3_and-cache.lib b/library/SubcircuitLibrary/74S182/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74S182/3_and.cir b/library/SubcircuitLibrary/74S182/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74S182/3_and.cir.out b/library/SubcircuitLibrary/74S182/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74S182/3_and.pro b/library/SubcircuitLibrary/74S182/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/74S182/3_and.sch b/library/SubcircuitLibrary/74S182/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74S182/3_and.sub b/library/SubcircuitLibrary/74S182/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74S182/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74S182/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74S182/4_OR-cache.lib b/library/SubcircuitLibrary/74S182/4_OR-cache.lib
new file mode 100644
index 000000000..155f5e601
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74S182/4_OR.cir b/library/SubcircuitLibrary/74S182/4_OR.cir
new file mode 100644
index 000000000..b338b7b5f
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74S182/4_OR.cir.out b/library/SubcircuitLibrary/74S182/4_OR.cir.out
new file mode 100644
index 000000000..adb6b01be
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74S182/4_OR.pro b/library/SubcircuitLibrary/74S182/4_OR.pro
new file mode 100644
index 000000000..881563ebd
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/74S182/4_OR.sch b/library/SubcircuitLibrary/74S182/4_OR.sch
new file mode 100644
index 000000000..118968656
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74S182/4_OR.sub b/library/SubcircuitLibrary/74S182/4_OR.sub
new file mode 100644
index 000000000..d1fd3a241
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74S182/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/74S182/4_OR_Previous_Values.xml
new file mode 100644
index 000000000..0683d9eb6
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74S182/4_and-cache.lib b/library/SubcircuitLibrary/74S182/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74S182/4_and-rescue.lib b/library/SubcircuitLibrary/74S182/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74S182/4_and.cir b/library/SubcircuitLibrary/74S182/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74S182/4_and.cir.out b/library/SubcircuitLibrary/74S182/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74S182/4_and.pro b/library/SubcircuitLibrary/74S182/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/74S182/4_and.sch b/library/SubcircuitLibrary/74S182/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74S182/4_and.sub b/library/SubcircuitLibrary/74S182/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74S182/4_and_Previous_Values.xml b/library/SubcircuitLibrary/74S182/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74S182/74S182-cache.lib b/library/SubcircuitLibrary/74S182/74S182-cache.lib
new file mode 100644
index 000000000..644604439
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/74S182-cache.lib
@@ -0,0 +1,171 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74S182/74S182.cir b/library/SubcircuitLibrary/74S182/74S182.cir
new file mode 100644
index 000000000..10f35aab7
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/74S182.cir
@@ -0,0 +1,33 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74S182\74S182.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/22/25 09:40:55
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 P3_bar P2_bar P1_bar P0_bar Net-_U1-Pad7_ 4_OR
+X4 G3_bar G2_bar G1_bar G0_bar Net-_X10-Pad1_ 4_and
+X5 P1_bar G3_bar G2_bar G1_bar Net-_X10-Pad2_ 4_and
+X6 P2_bar G3_bar G2_bar Net-_X10-Pad3_ 3_and
+U2 P3_bar G3_bar Net-_U2-Pad3_ d_and
+X7 G2_bar G1_bar G0_bar Net-_U20-Pad2_ Net-_X11-Pad1_ 4_and
+X8 P0_bar G2_bar G1_bar G0_bar Net-_X11-Pad2_ 4_and
+X9 P1_bar G2_bar G1_bar Net-_X11-Pad3_ 3_and
+U3 P2_bar G2_bar Net-_U3-Pad3_ d_and
+X2 G1_bar G0_bar Net-_U20-Pad2_ Net-_U8-Pad1_ 3_and
+X3 P0_bar G1_bar G0_bar Net-_U8-Pad2_ 3_and
+U4 P1_bar G1_bar Net-_U10-Pad2_ d_and
+U5 G0_bar Net-_U20-Pad2_ Net-_U5-Pad3_ d_and
+U6 P0_bar G0_bar Net-_U6-Pad3_ d_and
+X10 Net-_X10-Pad1_ Net-_X10-Pad2_ Net-_X10-Pad3_ Net-_U2-Pad3_ Net-_U1-Pad10_ 4_OR
+U7 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U1-Pad12_ d_nor
+X11 Net-_X11-Pad1_ Net-_X11-Pad2_ Net-_X11-Pad3_ Net-_U3-Pad3_ Net-_U9-Pad1_ 4_OR
+U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U10-Pad1_ d_or
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or
+U9 Net-_U9-Pad1_ Net-_U1-Pad9_ d_inverter
+U11 Net-_U10-Pad3_ Net-_U1-Pad11_ d_inverter
+U20 Cn Net-_U20-Pad2_ d_inverter
+U1 G1_bar P1_bar G0_bar P0_bar G3_bar P3_bar Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Cn G2_bar P2_bar PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74S182/74S182.cir.out b/library/SubcircuitLibrary/74S182/74S182.cir.out
new file mode 100644
index 000000000..160f3f6fa
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/74S182.cir.out
@@ -0,0 +1,70 @@
+* c:\fossee\esim\library\subcircuitlibrary\74s182\74s182.cir
+
+.include 4_OR.sub
+.include 4_and.sub
+.include 3_and.sub
+x1 p3_bar p2_bar p1_bar p0_bar net-_u1-pad7_ 4_OR
+x4 g3_bar g2_bar g1_bar g0_bar net-_x10-pad1_ 4_and
+x5 p1_bar g3_bar g2_bar g1_bar net-_x10-pad2_ 4_and
+x6 p2_bar g3_bar g2_bar net-_x10-pad3_ 3_and
+* u2 p3_bar g3_bar net-_u2-pad3_ d_and
+x7 g2_bar g1_bar g0_bar net-_u20-pad2_ net-_x11-pad1_ 4_and
+x8 p0_bar g2_bar g1_bar g0_bar net-_x11-pad2_ 4_and
+x9 p1_bar g2_bar g1_bar net-_x11-pad3_ 3_and
+* u3 p2_bar g2_bar net-_u3-pad3_ d_and
+x2 g1_bar g0_bar net-_u20-pad2_ net-_u8-pad1_ 3_and
+x3 p0_bar g1_bar g0_bar net-_u8-pad2_ 3_and
+* u4 p1_bar g1_bar net-_u10-pad2_ d_and
+* u5 g0_bar net-_u20-pad2_ net-_u5-pad3_ d_and
+* u6 p0_bar g0_bar net-_u6-pad3_ d_and
+x10 net-_x10-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_u2-pad3_ net-_u1-pad10_ 4_OR
+* u7 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad12_ d_nor
+x11 net-_x11-pad1_ net-_x11-pad2_ net-_x11-pad3_ net-_u3-pad3_ net-_u9-pad1_ 4_OR
+* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u10-pad1_ d_or
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
+* u9 net-_u9-pad1_ net-_u1-pad9_ d_inverter
+* u11 net-_u10-pad3_ net-_u1-pad11_ d_inverter
+* u20 cn net-_u20-pad2_ d_inverter
+* u1 g1_bar p1_bar g0_bar p0_bar g3_bar p3_bar net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ cn g2_bar p2_bar port
+a1 [p3_bar g3_bar ] net-_u2-pad3_ u2
+a2 [p2_bar g2_bar ] net-_u3-pad3_ u3
+a3 [p1_bar g1_bar ] net-_u10-pad2_ u4
+a4 [g0_bar net-_u20-pad2_ ] net-_u5-pad3_ u5
+a5 [p0_bar g0_bar ] net-_u6-pad3_ u6
+a6 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u1-pad12_ u7
+a7 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u10-pad1_ u8
+a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a9 net-_u9-pad1_ net-_u1-pad9_ u9
+a10 net-_u10-pad3_ net-_u1-pad11_ u11
+a11 cn net-_u20-pad2_ u20
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 250e-03 10e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74S182/74S182.pro b/library/SubcircuitLibrary/74S182/74S182.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/74S182.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74S182/74S182.sch b/library/SubcircuitLibrary/74S182/74S182.sch
new file mode 100644
index 000000000..bc2b9796e
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/74S182.sch
@@ -0,0 +1,733 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74S182-cache
+EELAYER 25 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4_OR X1
+U 1 1 685147D5
+P 4450 1200
+F 0 "X1" H 4600 1100 60 0000 C CNN
+F 1 "4_OR" H 4600 1300 60 0000 C CNN
+F 2 "" H 4450 1200 60 0000 C CNN
+F 3 "" H 4450 1200 60 0000 C CNN
+ 1 4450 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X4
+U 1 1 6851483A
+P 4500 2350
+F 0 "X4" H 4550 2300 60 0000 C CNN
+F 1 "4_and" H 4600 2450 60 0000 C CNN
+F 2 "" H 4500 2350 60 0000 C CNN
+F 3 "" H 4500 2350 60 0000 C CNN
+ 1 4500 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X5
+U 1 1 68514869
+P 4500 2850
+F 0 "X5" H 4550 2800 60 0000 C CNN
+F 1 "4_and" H 4600 2950 60 0000 C CNN
+F 2 "" H 4500 2850 60 0000 C CNN
+F 3 "" H 4500 2850 60 0000 C CNN
+ 1 4500 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X6
+U 1 1 6851489F
+P 4500 3350
+F 0 "X6" H 4600 3300 60 0000 C CNN
+F 1 "3_and" H 4650 3500 60 0000 C CNN
+F 2 "" H 4500 3350 60 0000 C CNN
+F 3 "" H 4500 3350 60 0000 C CNN
+ 1 4500 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 685148D0
+P 4550 3750
+F 0 "U2" H 4550 3750 60 0000 C CNN
+F 1 "d_and" H 4600 3850 60 0000 C CNN
+F 2 "" H 4550 3750 60 0000 C CNN
+F 3 "" H 4550 3750 60 0000 C CNN
+ 1 4550 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X7
+U 1 1 68514AF5
+P 4500 4700
+F 0 "X7" H 4550 4650 60 0000 C CNN
+F 1 "4_and" H 4600 4800 60 0000 C CNN
+F 2 "" H 4500 4700 60 0000 C CNN
+F 3 "" H 4500 4700 60 0000 C CNN
+ 1 4500 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X8
+U 1 1 68514AFB
+P 4500 5200
+F 0 "X8" H 4550 5150 60 0000 C CNN
+F 1 "4_and" H 4600 5300 60 0000 C CNN
+F 2 "" H 4500 5200 60 0000 C CNN
+F 3 "" H 4500 5200 60 0000 C CNN
+ 1 4500 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X9
+U 1 1 68514B01
+P 4500 5700
+F 0 "X9" H 4600 5650 60 0000 C CNN
+F 1 "3_and" H 4650 5850 60 0000 C CNN
+F 2 "" H 4500 5700 60 0000 C CNN
+F 3 "" H 4500 5700 60 0000 C CNN
+ 1 4500 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 68514B07
+P 4550 6100
+F 0 "U3" H 4550 6100 60 0000 C CNN
+F 1 "d_and" H 4600 6200 60 0000 C CNN
+F 2 "" H 4550 6100 60 0000 C CNN
+F 3 "" H 4550 6100 60 0000 C CNN
+ 1 4550 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 68514BBA
+P 4450 7100
+F 0 "X2" H 4550 7050 60 0000 C CNN
+F 1 "3_and" H 4600 7250 60 0000 C CNN
+F 2 "" H 4450 7100 60 0000 C CNN
+F 3 "" H 4450 7100 60 0000 C CNN
+ 1 4450 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X3
+U 1 1 68514C43
+P 4450 7600
+F 0 "X3" H 4550 7550 60 0000 C CNN
+F 1 "3_and" H 4600 7750 60 0000 C CNN
+F 2 "" H 4450 7600 60 0000 C CNN
+F 3 "" H 4450 7600 60 0000 C CNN
+ 1 4450 7600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 68514C86
+P 4550 8050
+F 0 "U4" H 4550 8050 60 0000 C CNN
+F 1 "d_and" H 4600 8150 60 0000 C CNN
+F 2 "" H 4550 8050 60 0000 C CNN
+F 3 "" H 4550 8050 60 0000 C CNN
+ 1 4550 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 68514D0F
+P 4550 8900
+F 0 "U5" H 4550 8900 60 0000 C CNN
+F 1 "d_and" H 4600 9000 60 0000 C CNN
+F 2 "" H 4550 8900 60 0000 C CNN
+F 3 "" H 4550 8900 60 0000 C CNN
+ 1 4550 8900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 68514D9A
+P 4550 9300
+F 0 "U6" H 4550 9300 60 0000 C CNN
+F 1 "d_and" H 4600 9400 60 0000 C CNN
+F 2 "" H 4550 9300 60 0000 C CNN
+F 3 "" H 4550 9300 60 0000 C CNN
+ 1 4550 9300
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X10
+U 1 1 68514E70
+P 6400 3000
+F 0 "X10" H 6550 2900 60 0000 C CNN
+F 1 "4_OR" H 6550 3100 60 0000 C CNN
+F 2 "" H 6400 3000 60 0000 C CNN
+F 3 "" H 6400 3000 60 0000 C CNN
+ 1 6400 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 68515194
+P 6400 9000
+F 0 "U7" H 6400 9000 60 0000 C CNN
+F 1 "d_nor" H 6450 9100 60 0000 C CNN
+F 2 "" H 6400 9000 60 0000 C CNN
+F 3 "" H 6400 9000 60 0000 C CNN
+ 1 6400 9000
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X11
+U 1 1 68515632
+P 6400 5200
+F 0 "X11" H 6550 5100 60 0000 C CNN
+F 1 "4_OR" H 6550 5300 60 0000 C CNN
+F 2 "" H 6400 5200 60 0000 C CNN
+F 3 "" H 6400 5200 60 0000 C CNN
+ 1 6400 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U8
+U 1 1 685156A8
+P 6650 7300
+F 0 "U8" H 6650 7300 60 0000 C CNN
+F 1 "d_or" H 6650 7400 60 0000 C CNN
+F 2 "" H 6650 7300 60 0000 C CNN
+F 3 "" H 6650 7300 60 0000 C CNN
+ 1 6650 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U10
+U 1 1 685156FD
+P 7750 7700
+F 0 "U10" H 7750 7700 60 0000 C CNN
+F 1 "d_or" H 7750 7800 60 0000 C CNN
+F 2 "" H 7750 7700 60 0000 C CNN
+F 3 "" H 7750 7700 60 0000 C CNN
+ 1 7750 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 6851575A
+P 7550 5200
+F 0 "U9" H 7550 5100 60 0000 C CNN
+F 1 "d_inverter" H 7550 5350 60 0000 C CNN
+F 2 "" H 7600 5150 60 0000 C CNN
+F 3 "" H 7600 5150 60 0000 C CNN
+ 1 7550 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U11
+U 1 1 6851589D
+P 9100 7650
+F 0 "U11" H 9100 7550 60 0000 C CNN
+F 1 "d_inverter" H 9100 7800 60 0000 C CNN
+F 2 "" H 9150 7600 60 0000 C CNN
+F 3 "" H 9150 7600 60 0000 C CNN
+ 1 9100 7650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U20
+U 1 1 6851594F
+P 3050 9800
+F 0 "U20" H 3050 9700 60 0000 C CNN
+F 1 "d_inverter" H 3050 9950 60 0000 C CNN
+F 2 "" H 3100 9750 60 0000 C CNN
+F 3 "" H 3100 9750 60 0000 C CNN
+ 1 3050 9800
+ 1 0 0 -1
+$EndComp
+Text GLabel 2250 9800 0 60 Input ~ 0
+Cn
+Text GLabel 2250 9200 0 60 Input ~ 0
+P0_bar
+Text GLabel 2250 9450 0 60 Input ~ 0
+G0_bar
+Text GLabel 2300 8150 0 60 Input ~ 0
+G1_bar
+Text GLabel 2300 7950 0 60 Input ~ 0
+P1_bar
+Text GLabel 2350 6250 0 60 Input ~ 0
+G2_bar
+Text GLabel 2350 6000 0 60 Input ~ 0
+P2_bar
+Text GLabel 2450 4050 0 60 Input ~ 0
+G3_bar
+Wire Wire Line
+ 2250 9800 2750 9800
+Wire Wire Line
+ 3950 9800 3350 9800
+Wire Wire Line
+ 3950 4850 3950 9800
+Wire Wire Line
+ 3950 8900 4100 8900
+Wire Wire Line
+ 2250 9450 4050 9450
+Wire Wire Line
+ 4050 9450 4050 9300
+Wire Wire Line
+ 4050 9300 4100 9300
+Wire Wire Line
+ 2250 9200 4100 9200
+Wire Wire Line
+ 4100 8800 3850 8800
+Wire Wire Line
+ 3850 2500 3850 9450
+Connection ~ 3850 9450
+Wire Wire Line
+ 2300 8150 4050 8150
+Wire Wire Line
+ 4050 8150 4050 8050
+Wire Wire Line
+ 4050 8050 4100 8050
+Wire Wire Line
+ 2300 7950 4100 7950
+Wire Wire Line
+ 4100 7650 3850 7650
+Connection ~ 3850 8800
+Wire Wire Line
+ 4100 7550 3750 7550
+Wire Wire Line
+ 3750 2400 3750 8150
+Connection ~ 3750 8150
+Wire Wire Line
+ 4100 7450 3650 7450
+Wire Wire Line
+ 3650 7450 3650 9200
+Connection ~ 3650 9200
+Wire Wire Line
+ 3950 7150 4100 7150
+Connection ~ 3950 8900
+Wire Wire Line
+ 4100 7050 3850 7050
+Connection ~ 3850 7650
+Wire Wire Line
+ 4100 6950 3750 6950
+Connection ~ 3750 7550
+Wire Wire Line
+ 2350 6250 4000 6250
+Wire Wire Line
+ 4000 6250 4000 6100
+Wire Wire Line
+ 4000 6100 4100 6100
+Wire Wire Line
+ 2350 6000 4100 6000
+Wire Wire Line
+ 4150 5750 3750 5750
+Connection ~ 3750 6950
+Wire Wire Line
+ 4150 5650 3650 5650
+Wire Wire Line
+ 3650 2300 3650 6250
+Connection ~ 3650 6250
+Wire Wire Line
+ 4150 5550 3500 5550
+Wire Wire Line
+ 3500 1250 3500 7950
+Connection ~ 3500 7950
+Wire Wire Line
+ 4100 5350 3850 5350
+Connection ~ 3850 7050
+Wire Wire Line
+ 4100 5250 3750 5250
+Connection ~ 3750 5750
+Wire Wire Line
+ 4100 5150 3650 5150
+Connection ~ 3650 5650
+Wire Wire Line
+ 4100 5050 3400 5050
+Wire Wire Line
+ 3400 1350 3400 9200
+Connection ~ 3400 9200
+Wire Wire Line
+ 3950 4850 4100 4850
+Connection ~ 3950 7150
+Wire Wire Line
+ 3850 4750 4100 4750
+Connection ~ 3850 5350
+Wire Wire Line
+ 4100 4650 3750 4650
+Connection ~ 3750 5250
+Wire Wire Line
+ 4100 4550 3650 4550
+Connection ~ 3650 5150
+Wire Wire Line
+ 2450 4050 4000 4050
+Wire Wire Line
+ 4000 4050 4000 3750
+Wire Wire Line
+ 4000 3750 4100 3750
+Wire Wire Line
+ 3650 3400 4150 3400
+Connection ~ 3650 4550
+Wire Wire Line
+ 4150 3300 3200 3300
+Wire Wire Line
+ 3200 2200 3200 4050
+Connection ~ 3200 4050
+Wire Wire Line
+ 4150 3200 3100 3200
+Wire Wire Line
+ 3100 1150 3100 6000
+Connection ~ 3100 6000
+Wire Wire Line
+ 3750 3000 4100 3000
+Connection ~ 3750 4650
+Wire Wire Line
+ 4100 2900 3650 2900
+Connection ~ 3650 3400
+Wire Wire Line
+ 4100 2800 3200 2800
+Connection ~ 3200 3300
+Wire Wire Line
+ 3500 2700 4100 2700
+Connection ~ 3500 5550
+Wire Wire Line
+ 4100 2500 3850 2500
+Connection ~ 3850 4750
+Wire Wire Line
+ 4100 2400 3750 2400
+Connection ~ 3750 3000
+Wire Wire Line
+ 4100 2300 3650 2300
+Connection ~ 3650 2900
+Wire Wire Line
+ 4100 2200 3200 2200
+Connection ~ 3200 2800
+Wire Wire Line
+ 3400 1350 4100 1350
+Connection ~ 3400 5050
+Wire Wire Line
+ 3500 1250 4100 1250
+Connection ~ 3500 2700
+Wire Wire Line
+ 3100 1150 4100 1150
+Connection ~ 3100 3200
+Wire Wire Line
+ 4100 1050 3000 1050
+Wire Wire Line
+ 3000 1050 3000 3650
+Connection ~ 3000 3650
+Wire Wire Line
+ 5000 8850 5900 8850
+Wire Wire Line
+ 5900 8850 5900 8900
+Wire Wire Line
+ 5900 8900 5950 8900
+Wire Wire Line
+ 5000 9250 5000 9000
+Wire Wire Line
+ 5000 9000 5950 9000
+Wire Wire Line
+ 4950 7050 6200 7050
+Wire Wire Line
+ 6200 7050 6200 7200
+Wire Wire Line
+ 4950 7550 6200 7550
+Wire Wire Line
+ 6200 7550 6200 7300
+Wire Wire Line
+ 5000 8000 7300 8000
+Wire Wire Line
+ 7300 8000 7300 7700
+Wire Wire Line
+ 7100 7250 7300 7250
+Wire Wire Line
+ 7300 7250 7300 7600
+Wire Wire Line
+ 8200 7650 8800 7650
+Wire Wire Line
+ 5000 4700 6050 4700
+Wire Wire Line
+ 6050 4700 6050 5050
+Wire Wire Line
+ 5000 5200 5000 5150
+Wire Wire Line
+ 5000 5150 6050 5150
+Wire Wire Line
+ 5000 5650 5050 5650
+Wire Wire Line
+ 5050 5650 5050 5250
+Wire Wire Line
+ 5050 5250 6050 5250
+Wire Wire Line
+ 5000 6050 5150 6050
+Wire Wire Line
+ 5150 6050 5150 5350
+Wire Wire Line
+ 5150 5350 6050 5350
+Wire Wire Line
+ 6950 5200 7250 5200
+Wire Wire Line
+ 5000 3700 6050 3700
+Wire Wire Line
+ 6050 3700 6050 3150
+Wire Wire Line
+ 5000 3300 5950 3300
+Wire Wire Line
+ 5950 3300 5950 3050
+Wire Wire Line
+ 5950 3050 6050 3050
+Wire Wire Line
+ 5000 2850 5000 2950
+Wire Wire Line
+ 5000 2950 6050 2950
+Wire Wire Line
+ 5000 2350 6050 2350
+Wire Wire Line
+ 6050 2350 6050 2850
+$Comp
+L PORT U1
+U 1 1 6851A559
+P 2600 8500
+F 0 "U1" H 2650 8600 30 0000 C CNN
+F 1 "PORT" H 2600 8500 30 0000 C CNN
+F 2 "" H 2600 8500 60 0000 C CNN
+F 3 "" H 2600 8500 60 0000 C CNN
+ 1 2600 8500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6851A8EA
+P 2600 7550
+F 0 "U1" H 2650 7650 30 0000 C CNN
+F 1 "PORT" H 2600 7550 30 0000 C CNN
+F 2 "" H 2600 7550 60 0000 C CNN
+F 3 "" H 2600 7550 60 0000 C CNN
+ 2 2600 7550
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6851A9AF
+P 3000 8900
+F 0 "U1" H 3050 9000 30 0000 C CNN
+F 1 "PORT" H 3000 8900 30 0000 C CNN
+F 2 "" H 3000 8900 60 0000 C CNN
+F 3 "" H 3000 8900 60 0000 C CNN
+ 3 3000 8900
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6851AA0C
+P 2700 8900
+F 0 "U1" H 2750 9000 30 0000 C CNN
+F 1 "PORT" H 2700 8900 30 0000 C CNN
+F 2 "" H 2700 8900 60 0000 C CNN
+F 3 "" H 2700 8900 60 0000 C CNN
+ 4 2700 8900
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6851AAB3
+P 2750 4450
+F 0 "U1" H 2800 4550 30 0000 C CNN
+F 1 "PORT" H 2750 4450 30 0000 C CNN
+F 2 "" H 2750 4450 60 0000 C CNN
+F 3 "" H 2750 4450 60 0000 C CNN
+ 5 2750 4450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6851AC68
+P 2750 3300
+F 0 "U1" H 2800 3400 30 0000 C CNN
+F 1 "PORT" H 2750 3300 30 0000 C CNN
+F 2 "" H 2750 3300 60 0000 C CNN
+F 3 "" H 2750 3300 60 0000 C CNN
+ 6 2750 3300
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6851ADB1
+P 5950 1200
+F 0 "U1" H 6000 1300 30 0000 C CNN
+F 1 "PORT" H 5950 1200 30 0000 C CNN
+F 2 "" H 5950 1200 60 0000 C CNN
+F 3 "" H 5950 1200 60 0000 C CNN
+ 7 5950 1200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6851AEAF
+P 8650 5200
+F 0 "U1" H 8700 5300 30 0000 C CNN
+F 1 "PORT" H 8650 5200 30 0000 C CNN
+F 2 "" H 8650 5200 60 0000 C CNN
+F 3 "" H 8650 5200 60 0000 C CNN
+ 9 8650 5200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6851B080
+P 8100 3000
+F 0 "U1" H 8150 3100 30 0000 C CNN
+F 1 "PORT" H 8100 3000 30 0000 C CNN
+F 2 "" H 8100 3000 60 0000 C CNN
+F 3 "" H 8100 3000 60 0000 C CNN
+ 10 8100 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6851B267
+P 10450 7650
+F 0 "U1" H 10500 7750 30 0000 C CNN
+F 1 "PORT" H 10450 7650 30 0000 C CNN
+F 2 "" H 10450 7650 60 0000 C CNN
+F 3 "" H 10450 7650 60 0000 C CNN
+ 11 10450 7650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6851B415
+P 7750 8950
+F 0 "U1" H 7800 9050 30 0000 C CNN
+F 1 "PORT" H 7750 8950 30 0000 C CNN
+F 2 "" H 7750 8950 60 0000 C CNN
+F 3 "" H 7750 8950 60 0000 C CNN
+ 12 7750 8950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6851B85C
+P 2550 10250
+F 0 "U1" H 2600 10350 30 0000 C CNN
+F 1 "PORT" H 2550 10250 30 0000 C CNN
+F 2 "" H 2550 10250 60 0000 C CNN
+F 3 "" H 2550 10250 60 0000 C CNN
+ 13 2550 10250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6851C350
+P 2750 6650
+F 0 "U1" H 2800 6750 30 0000 C CNN
+F 1 "PORT" H 2750 6650 30 0000 C CNN
+F 2 "" H 2750 6650 60 0000 C CNN
+F 3 "" H 2750 6650 60 0000 C CNN
+ 14 2750 6650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 15 1 6851C41F
+P 2700 5600
+F 0 "U1" H 2750 5700 30 0000 C CNN
+F 1 "PORT" H 2700 5600 30 0000 C CNN
+F 2 "" H 2700 5600 60 0000 C CNN
+F 3 "" H 2700 5600 60 0000 C CNN
+ 15 2700 5600
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 5000 1200 5700 1200
+Wire Wire Line
+ 6950 3000 7850 3000
+Wire Wire Line
+ 2750 3550 2750 3650
+Connection ~ 2750 3650
+Wire Wire Line
+ 2750 4200 2750 4050
+Connection ~ 2750 4050
+Wire Wire Line
+ 2700 5850 2700 6000
+Connection ~ 2700 6000
+Wire Wire Line
+ 2750 6400 2750 6250
+Connection ~ 2750 6250
+Wire Wire Line
+ 7850 5200 8400 5200
+Wire Wire Line
+ 2600 7800 2600 7950
+Connection ~ 2600 7950
+Wire Wire Line
+ 2600 8250 2600 8150
+Connection ~ 2600 8150
+Wire Wire Line
+ 2700 9150 2700 9200
+Connection ~ 2700 9200
+Wire Wire Line
+ 3000 9150 3000 9450
+Connection ~ 3000 9450
+Wire Wire Line
+ 2550 10000 2550 9800
+Connection ~ 2550 9800
+Wire Wire Line
+ 10200 7650 9400 7650
+Wire Wire Line
+ 6850 8950 7500 8950
+Wire Wire Line
+ 2450 3650 4100 3650
+Text GLabel 2450 3650 0 60 Input ~ 0
+P3_bar
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74S182/74S182.sub b/library/SubcircuitLibrary/74S182/74S182.sub
new file mode 100644
index 000000000..d82544930
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/74S182.sub
@@ -0,0 +1,64 @@
+* Subcircuit 74S182
+.subckt 74S182 g1_bar p1_bar g0_bar p0_bar g3_bar p3_bar net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ cn g2_bar p2_bar
+* c:\fossee\esim\library\subcircuitlibrary\74s182\74s182.cir
+.include 4_OR.sub
+.include 4_and.sub
+.include 3_and.sub
+x1 p3_bar p2_bar p1_bar p0_bar net-_u1-pad7_ 4_OR
+x4 g3_bar g2_bar g1_bar g0_bar net-_x10-pad1_ 4_and
+x5 p1_bar g3_bar g2_bar g1_bar net-_x10-pad2_ 4_and
+x6 p2_bar g3_bar g2_bar net-_x10-pad3_ 3_and
+* u2 p3_bar g3_bar net-_u2-pad3_ d_and
+x7 g2_bar g1_bar g0_bar net-_u20-pad2_ net-_x11-pad1_ 4_and
+x8 p0_bar g2_bar g1_bar g0_bar net-_x11-pad2_ 4_and
+x9 p1_bar g2_bar g1_bar net-_x11-pad3_ 3_and
+* u3 p2_bar g2_bar net-_u3-pad3_ d_and
+x2 g1_bar g0_bar net-_u20-pad2_ net-_u8-pad1_ 3_and
+x3 p0_bar g1_bar g0_bar net-_u8-pad2_ 3_and
+* u4 p1_bar g1_bar net-_u10-pad2_ d_and
+* u5 g0_bar net-_u20-pad2_ net-_u5-pad3_ d_and
+* u6 p0_bar g0_bar net-_u6-pad3_ d_and
+x10 net-_x10-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_u2-pad3_ net-_u1-pad10_ 4_OR
+* u7 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad12_ d_nor
+x11 net-_x11-pad1_ net-_x11-pad2_ net-_x11-pad3_ net-_u3-pad3_ net-_u9-pad1_ 4_OR
+* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u10-pad1_ d_or
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
+* u9 net-_u9-pad1_ net-_u1-pad9_ d_inverter
+* u11 net-_u10-pad3_ net-_u1-pad11_ d_inverter
+* u20 cn net-_u20-pad2_ d_inverter
+a1 [p3_bar g3_bar ] net-_u2-pad3_ u2
+a2 [p2_bar g2_bar ] net-_u3-pad3_ u3
+a3 [p1_bar g1_bar ] net-_u10-pad2_ u4
+a4 [g0_bar net-_u20-pad2_ ] net-_u5-pad3_ u5
+a5 [p0_bar g0_bar ] net-_u6-pad3_ u6
+a6 [net-_u5-pad3_ net-_u6-pad3_ ] net-_u1-pad12_ u7
+a7 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u10-pad1_ u8
+a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a9 net-_u9-pad1_ net-_u1-pad9_ u9
+a10 net-_u10-pad3_ net-_u1-pad11_ u11
+a11 cn net-_u20-pad2_ u20
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends 74S182
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74S182/74S182_Previous_Values.xml b/library/SubcircuitLibrary/74S182/74S182_Previous_Values.xml
new file mode 100644
index 000000000..724f2c757
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/74S182_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andd_andd_andd_andd_nord_ord_ord_inverterd_inverterd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmsms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/74S182/analysis b/library/SubcircuitLibrary/74S182/analysis
new file mode 100644
index 000000000..6bbeaba60
--- /dev/null
+++ b/library/SubcircuitLibrary/74S182/analysis
@@ -0,0 +1 @@
+.tran 250e-03 10e-03 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B-cache.lib b/library/SubcircuitLibrary/CD4017B/CD4017B-cache.lib
new file mode 100644
index 000000000..93027b16b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4017B/CD4017B-cache.lib
@@ -0,0 +1,143 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.bak b/library/SubcircuitLibrary/CD4017B/CD4017B.bak
new file mode 100644
index 000000000..f00f56a04
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4017B/CD4017B.bak
@@ -0,0 +1,1203 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4017B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U13
+U 1 1 68664336
+P 10050 13000
+F 0 "U13" H 10050 13000 60 0000 C CNN
+F 1 "d_dff" H 10050 13150 60 0000 C CNN
+F 2 "" H 10050 13000 60 0000 C CNN
+F 3 "" H 10050 13000 60 0000 C CNN
+ 1 10050 13000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U30
+U 1 1 6866447A
+P 17900 12800
+F 0 "U30" H 17900 12800 60 0000 C CNN
+F 1 "d_dff" H 17900 12950 60 0000 C CNN
+F 2 "" H 17900 12800 60 0000 C CNN
+F 3 "" H 17900 12800 60 0000 C CNN
+ 1 17900 12800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U47
+U 1 1 686645F8
+P 26450 12550
+F 0 "U47" H 26450 12550 60 0000 C CNN
+F 1 "d_dff" H 26450 12700 60 0000 C CNN
+F 2 "" H 26450 12550 60 0000 C CNN
+F 3 "" H 26450 12550 60 0000 C CNN
+ 1 26450 12550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U3
+U 1 1 686647DD
+P 5100 21550
+F 0 "U3" H 5100 21500 60 0000 C CNN
+F 1 "d_buffer" H 5100 21600 60 0000 C CNN
+F 2 "" H 5100 21550 60 0000 C CNN
+F 3 "" H 5100 21550 60 0000 C CNN
+ 1 5100 21550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68664852
+P 6550 21550
+F 0 "U6" H 6550 21450 60 0000 C CNN
+F 1 "d_inverter" H 6550 21700 60 0000 C CNN
+F 2 "" H 6600 21500 60 0000 C CNN
+F 3 "" H 6600 21500 60 0000 C CNN
+ 1 6550 21550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 686648C7
+P 7650 21550
+F 0 "U8" H 7650 21450 60 0000 C CNN
+F 1 "d_inverter" H 7650 21700 60 0000 C CNN
+F 2 "" H 7700 21500 60 0000 C CNN
+F 3 "" H 7700 21500 60 0000 C CNN
+ 1 7650 21550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U12
+U 1 1 68664946
+P 8850 21550
+F 0 "U12" H 8850 21500 60 0000 C CNN
+F 1 "d_buffer" H 8850 21600 60 0000 C CNN
+F 2 "" H 8850 21550 60 0000 C CNN
+F 3 "" H 8850 21550 60 0000 C CNN
+ 1 8850 21550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U14
+U 1 1 68664AE0
+P 10150 20700
+F 0 "U14" H 10150 20700 60 0000 C CNN
+F 1 "d_nor" H 10200 20800 60 0000 C CNN
+F 2 "" H 10150 20700 60 0000 C CNN
+F 3 "" H 10150 20700 60 0000 C CNN
+ 1 10150 20700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U2
+U 1 1 686655EB
+P 4250 13950
+F 0 "U2" H 4250 13900 60 0000 C CNN
+F 1 "d_buffer" H 4250 14000 60 0000 C CNN
+F 2 "" H 4250 13950 60 0000 C CNN
+F 3 "" H 4250 13950 60 0000 C CNN
+ 1 4250 13950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 68665755
+P 5600 13950
+F 0 "U4" H 5600 13850 60 0000 C CNN
+F 1 "d_inverter" H 5600 14100 60 0000 C CNN
+F 2 "" H 5650 13900 60 0000 C CNN
+F 3 "" H 5650 13900 60 0000 C CNN
+ 1 5600 13950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 68665840
+P 6450 13950
+F 0 "U5" H 6450 13850 60 0000 C CNN
+F 1 "d_inverter" H 6450 14100 60 0000 C CNN
+F 2 "" H 6500 13900 60 0000 C CNN
+F 3 "" H 6500 13900 60 0000 C CNN
+ 1 6450 13950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U7
+U 1 1 68665887
+P 7500 13950
+F 0 "U7" H 7500 13900 60 0000 C CNN
+F 1 "d_buffer" H 7500 14000 60 0000 C CNN
+F 2 "" H 7500 13950 60 0000 C CNN
+F 3 "" H 7500 13950 60 0000 C CNN
+ 1 7500 13950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U11
+U 1 1 68666477
+P 8300 4500
+F 0 "U11" H 8300 4500 60 0000 C CNN
+F 1 "d_nand" H 8350 4600 60 0000 C CNN
+F 2 "" H 8300 4500 60 0000 C CNN
+F 3 "" H 8300 4500 60 0000 C CNN
+ 1 8300 4500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U17
+U 1 1 686665F7
+P 10300 4500
+F 0 "U17" H 10300 4500 60 0000 C CNN
+F 1 "d_nand" H 10350 4600 60 0000 C CNN
+F 2 "" H 10300 4500 60 0000 C CNN
+F 3 "" H 10300 4500 60 0000 C CNN
+ 1 10300 4500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U20
+U 1 1 686666A4
+P 12250 4450
+F 0 "U20" H 12250 4450 60 0000 C CNN
+F 1 "d_nand" H 12300 4550 60 0000 C CNN
+F 2 "" H 12250 4450 60 0000 C CNN
+F 3 "" H 12250 4450 60 0000 C CNN
+ 1 12250 4450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U25
+U 1 1 686667BA
+P 13950 4500
+F 0 "U25" H 13950 4500 60 0000 C CNN
+F 1 "d_nand" H 14000 4600 60 0000 C CNN
+F 2 "" H 13950 4500 60 0000 C CNN
+F 3 "" H 13950 4500 60 0000 C CNN
+ 1 13950 4500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U29
+U 1 1 68666843
+P 15800 4500
+F 0 "U29" H 15800 4500 60 0000 C CNN
+F 1 "d_nand" H 15850 4600 60 0000 C CNN
+F 2 "" H 15800 4500 60 0000 C CNN
+F 3 "" H 15800 4500 60 0000 C CNN
+ 1 15800 4500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U33
+U 1 1 686668C6
+P 17950 4500
+F 0 "U33" H 17950 4500 60 0000 C CNN
+F 1 "d_nand" H 18000 4600 60 0000 C CNN
+F 2 "" H 17950 4500 60 0000 C CNN
+F 3 "" H 17950 4500 60 0000 C CNN
+ 1 17950 4500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U36
+U 1 1 686669C1
+P 20050 4450
+F 0 "U36" H 20050 4450 60 0000 C CNN
+F 1 "d_nand" H 20100 4550 60 0000 C CNN
+F 2 "" H 20050 4450 60 0000 C CNN
+F 3 "" H 20050 4450 60 0000 C CNN
+ 1 20050 4450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U40
+U 1 1 68666A5C
+P 21950 4450
+F 0 "U40" H 21950 4450 60 0000 C CNN
+F 1 "d_nand" H 22000 4550 60 0000 C CNN
+F 2 "" H 21950 4450 60 0000 C CNN
+F 3 "" H 21950 4450 60 0000 C CNN
+ 1 21950 4450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U43
+U 1 1 68666BA5
+P 23650 4450
+F 0 "U43" H 23650 4450 60 0000 C CNN
+F 1 "d_nand" H 23700 4550 60 0000 C CNN
+F 2 "" H 23650 4450 60 0000 C CNN
+F 3 "" H 23650 4450 60 0000 C CNN
+ 1 23650 4450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U46
+U 1 1 68666C44
+P 25300 4450
+F 0 "U46" H 25300 4450 60 0000 C CNN
+F 1 "d_nand" H 25350 4550 60 0000 C CNN
+F 2 "" H 25300 4450 60 0000 C CNN
+F 3 "" H 25300 4450 60 0000 C CNN
+ 1 25300 4450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_and U21
+U 1 1 6866E2FD
+P 13950 16200
+F 0 "U21" H 13950 16200 60 0000 C CNN
+F 1 "d_and" H 14000 16300 60 0000 C CNN
+F 2 "" H 13950 16200 60 0000 C CNN
+F 3 "" H 13950 16200 60 0000 C CNN
+ 1 13950 16200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U26
+U 1 1 6866E390
+P 15800 15650
+F 0 "U26" H 15800 15650 60 0000 C CNN
+F 1 "d_nor" H 15850 15750 60 0000 C CNN
+F 2 "" H 15800 15650 60 0000 C CNN
+F 3 "" H 15800 15650 60 0000 C CNN
+ 1 15800 15650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U53
+U 1 1 686742A7
+P 27900 8600
+F 0 "U53" H 27900 8550 60 0000 C CNN
+F 1 "d_buffer" H 27900 8650 60 0000 C CNN
+F 2 "" H 27900 8600 60 0000 C CNN
+F 3 "" H 27900 8600 60 0000 C CNN
+ 1 27900 8600
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U52
+U 1 1 68674360
+P 27900 7250
+F 0 "U52" H 27900 7150 60 0000 C CNN
+F 1 "d_inverter" H 27900 7400 60 0000 C CNN
+F 2 "" H 27950 7200 60 0000 C CNN
+F 3 "" H 27950 7200 60 0000 C CNN
+ 1 27900 7250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U51
+U 1 1 686743E3
+P 27900 5950
+F 0 "U51" H 27900 5850 60 0000 C CNN
+F 1 "d_inverter" H 27900 6100 60 0000 C CNN
+F 2 "" H 27950 5900 60 0000 C CNN
+F 3 "" H 27950 5900 60 0000 C CNN
+ 1 27900 5950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U50
+U 1 1 68674539
+P 27900 4800
+F 0 "U50" H 27900 4750 60 0000 C CNN
+F 1 "d_buffer" H 27900 4850 60 0000 C CNN
+F 2 "" H 27900 4800 60 0000 C CNN
+F 3 "" H 27900 4800 60 0000 C CNN
+ 1 27900 4800
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U49
+U 1 1 686745C8
+P 27900 3100
+F 0 "U49" H 27900 3050 60 0000 C CNN
+F 1 "d_buffer" H 27900 3150 60 0000 C CNN
+F 2 "" H 27900 3100 60 0000 C CNN
+F 3 "" H 27900 3100 60 0000 C CNN
+ 1 27900 3100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U48
+U 1 1 68674685
+P 27900 1700
+F 0 "U48" H 27900 1600 60 0000 C CNN
+F 1 "d_inverter" H 27900 1850 60 0000 C CNN
+F 2 "" H 27950 1650 60 0000 C CNN
+F 3 "" H 27950 1650 60 0000 C CNN
+ 1 27900 1700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 686757F7
+P 8250 2650
+F 0 "U10" H 8250 2550 60 0000 C CNN
+F 1 "d_inverter" H 8250 2800 60 0000 C CNN
+F 2 "" H 8300 2600 60 0000 C CNN
+F 3 "" H 8300 2600 60 0000 C CNN
+ 1 8250 2650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U9
+U 1 1 686758E8
+P 8250 1100
+F 0 "U9" H 8250 1050 60 0000 C CNN
+F 1 "d_buffer" H 8250 1150 60 0000 C CNN
+F 2 "" H 8250 1100 60 0000 C CNN
+F 3 "" H 8250 1100 60 0000 C CNN
+ 1 8250 1100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 68675D57
+P 10150 2650
+F 0 "U16" H 10150 2550 60 0000 C CNN
+F 1 "d_inverter" H 10150 2800 60 0000 C CNN
+F 2 "" H 10200 2600 60 0000 C CNN
+F 3 "" H 10200 2600 60 0000 C CNN
+ 1 10150 2650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U15
+U 1 1 68675D5D
+P 10150 1100
+F 0 "U15" H 10150 1050 60 0000 C CNN
+F 1 "d_buffer" H 10150 1150 60 0000 C CNN
+F 2 "" H 10150 1100 60 0000 C CNN
+F 3 "" H 10150 1100 60 0000 C CNN
+ 1 10150 1100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U19
+U 1 1 68676262
+P 12150 2750
+F 0 "U19" H 12150 2650 60 0000 C CNN
+F 1 "d_inverter" H 12150 2900 60 0000 C CNN
+F 2 "" H 12200 2700 60 0000 C CNN
+F 3 "" H 12200 2700 60 0000 C CNN
+ 1 12150 2750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U18
+U 1 1 68676268
+P 12150 1200
+F 0 "U18" H 12150 1150 60 0000 C CNN
+F 1 "d_buffer" H 12150 1250 60 0000 C CNN
+F 2 "" H 12150 1200 60 0000 C CNN
+F 3 "" H 12150 1200 60 0000 C CNN
+ 1 12150 1200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U24
+U 1 1 6867626F
+P 13900 2750
+F 0 "U24" H 13900 2650 60 0000 C CNN
+F 1 "d_inverter" H 13900 2900 60 0000 C CNN
+F 2 "" H 13950 2700 60 0000 C CNN
+F 3 "" H 13950 2700 60 0000 C CNN
+ 1 13900 2750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U23
+U 1 1 68676275
+P 13900 1200
+F 0 "U23" H 13900 1150 60 0000 C CNN
+F 1 "d_buffer" H 13900 1250 60 0000 C CNN
+F 2 "" H 13900 1200 60 0000 C CNN
+F 3 "" H 13900 1200 60 0000 C CNN
+ 1 13900 1200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U28
+U 1 1 6867676C
+P 15750 2850
+F 0 "U28" H 15750 2750 60 0000 C CNN
+F 1 "d_inverter" H 15750 3000 60 0000 C CNN
+F 2 "" H 15800 2800 60 0000 C CNN
+F 3 "" H 15800 2800 60 0000 C CNN
+ 1 15750 2850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U27
+U 1 1 68676772
+P 15750 1300
+F 0 "U27" H 15750 1250 60 0000 C CNN
+F 1 "d_buffer" H 15750 1350 60 0000 C CNN
+F 2 "" H 15750 1300 60 0000 C CNN
+F 3 "" H 15750 1300 60 0000 C CNN
+ 1 15750 1300
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U32
+U 1 1 68676779
+P 17900 2900
+F 0 "U32" H 17900 2800 60 0000 C CNN
+F 1 "d_inverter" H 17900 3050 60 0000 C CNN
+F 2 "" H 17950 2850 60 0000 C CNN
+F 3 "" H 17950 2850 60 0000 C CNN
+ 1 17900 2900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U31
+U 1 1 6867677F
+P 17900 1350
+F 0 "U31" H 17900 1300 60 0000 C CNN
+F 1 "d_buffer" H 17900 1400 60 0000 C CNN
+F 2 "" H 17900 1350 60 0000 C CNN
+F 3 "" H 17900 1350 60 0000 C CNN
+ 1 17900 1350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U35
+U 1 1 68676786
+P 20000 2950
+F 0 "U35" H 20000 2850 60 0000 C CNN
+F 1 "d_inverter" H 20000 3100 60 0000 C CNN
+F 2 "" H 20050 2900 60 0000 C CNN
+F 3 "" H 20050 2900 60 0000 C CNN
+ 1 20000 2950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U34
+U 1 1 6867678C
+P 20000 1400
+F 0 "U34" H 20000 1350 60 0000 C CNN
+F 1 "d_buffer" H 20000 1450 60 0000 C CNN
+F 2 "" H 20000 1400 60 0000 C CNN
+F 3 "" H 20000 1400 60 0000 C CNN
+ 1 20000 1400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U38
+U 1 1 68676793
+P 21400 2950
+F 0 "U38" H 21400 2850 60 0000 C CNN
+F 1 "d_inverter" H 21400 3100 60 0000 C CNN
+F 2 "" H 21450 2900 60 0000 C CNN
+F 3 "" H 21450 2900 60 0000 C CNN
+ 1 21400 2950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U37
+U 1 1 68676799
+P 21400 1400
+F 0 "U37" H 21400 1350 60 0000 C CNN
+F 1 "d_buffer" H 21400 1450 60 0000 C CNN
+F 2 "" H 21400 1400 60 0000 C CNN
+F 3 "" H 21400 1400 60 0000 C CNN
+ 1 21400 1400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U42
+U 1 1 68676C38
+P 23600 2950
+F 0 "U42" H 23600 2850 60 0000 C CNN
+F 1 "d_inverter" H 23600 3100 60 0000 C CNN
+F 2 "" H 23650 2900 60 0000 C CNN
+F 3 "" H 23650 2900 60 0000 C CNN
+ 1 23600 2950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U41
+U 1 1 68676C3E
+P 23600 1400
+F 0 "U41" H 23600 1350 60 0000 C CNN
+F 1 "d_buffer" H 23600 1450 60 0000 C CNN
+F 2 "" H 23600 1400 60 0000 C CNN
+F 3 "" H 23600 1400 60 0000 C CNN
+ 1 23600 1400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U45
+U 1 1 68676C45
+P 25250 2950
+F 0 "U45" H 25250 2850 60 0000 C CNN
+F 1 "d_inverter" H 25250 3100 60 0000 C CNN
+F 2 "" H 25300 2900 60 0000 C CNN
+F 3 "" H 25300 2900 60 0000 C CNN
+ 1 25250 2950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U44
+U 1 1 68676C4B
+P 25250 1400
+F 0 "U44" H 25250 1350 60 0000 C CNN
+F 1 "d_buffer" H 25250 1450 60 0000 C CNN
+F 2 "" H 25250 1400 60 0000 C CNN
+F 3 "" H 25250 1400 60 0000 C CNN
+ 1 25250 1400
+ 0 -1 -1 0
+$EndComp
+NoConn ~ 10050 12350
+NoConn ~ 14100 12250
+NoConn ~ 22050 12050
+NoConn ~ 26450 11900
+$Comp
+L PORT U1
+U 15 1 6867C073
+P 2400 13950
+F 0 "U1" H 2450 14050 30 0000 C CNN
+F 1 "PORT" H 2400 13950 30 0000 C CNN
+F 2 "" H 2400 13950 60 0000 C CNN
+F 3 "" H 2400 13950 60 0000 C CNN
+ 15 2400 13950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6867C485
+P 4150 20550
+F 0 "U1" H 4200 20650 30 0000 C CNN
+F 1 "PORT" H 4150 20550 30 0000 C CNN
+F 2 "" H 4150 20550 60 0000 C CNN
+F 3 "" H 4150 20550 60 0000 C CNN
+ 14 4150 20550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6867C98A
+P 4150 21550
+F 0 "U1" H 4200 21650 30 0000 C CNN
+F 1 "PORT" H 4150 21550 30 0000 C CNN
+F 2 "" H 4150 21550 60 0000 C CNN
+F 3 "" H 4150 21550 60 0000 C CNN
+ 13 4150 21550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6867CA21
+P 8000 -200
+F 0 "U1" H 8050 -100 30 0000 C CNN
+F 1 "PORT" H 8000 -200 30 0000 C CNN
+F 2 "" H 8000 -200 60 0000 C CNN
+F 3 "" H 8000 -200 60 0000 C CNN
+ 3 8000 -200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6867D1A2
+P 9900 -250
+F 0 "U1" H 9950 -150 30 0000 C CNN
+F 1 "PORT" H 9900 -250 30 0000 C CNN
+F 2 "" H 9900 -250 60 0000 C CNN
+F 3 "" H 9900 -250 60 0000 C CNN
+ 2 9900 -250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6867D490
+P 11900 -300
+F 0 "U1" H 11950 -200 30 0000 C CNN
+F 1 "PORT" H 11900 -300 30 0000 C CNN
+F 2 "" H 11900 -300 60 0000 C CNN
+F 3 "" H 11900 -300 60 0000 C CNN
+ 4 11900 -300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6867D78D
+P 13650 -400
+F 0 "U1" H 13700 -300 30 0000 C CNN
+F 1 "PORT" H 13650 -400 30 0000 C CNN
+F 2 "" H 13650 -400 60 0000 C CNN
+F 3 "" H 13650 -400 60 0000 C CNN
+ 7 13650 -400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6867DA81
+P 15500 -450
+F 0 "U1" H 15550 -350 30 0000 C CNN
+F 1 "PORT" H 15500 -450 30 0000 C CNN
+F 2 "" H 15500 -450 60 0000 C CNN
+F 3 "" H 15500 -450 60 0000 C CNN
+ 10 15500 -450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6867DCF8
+P 17650 -450
+F 0 "U1" H 17700 -350 30 0000 C CNN
+F 1 "PORT" H 17650 -450 30 0000 C CNN
+F 2 "" H 17650 -450 60 0000 C CNN
+F 3 "" H 17650 -450 60 0000 C CNN
+ 1 17650 -450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6867E1B9
+P 19700 -500
+F 0 "U1" H 19750 -400 30 0000 C CNN
+F 1 "PORT" H 19700 -500 30 0000 C CNN
+F 2 "" H 19700 -500 60 0000 C CNN
+F 3 "" H 19700 -500 60 0000 C CNN
+ 5 19700 -500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6867E540
+P 21150 -500
+F 0 "U1" H 21200 -400 30 0000 C CNN
+F 1 "PORT" H 21150 -500 30 0000 C CNN
+F 2 "" H 21150 -500 60 0000 C CNN
+F 3 "" H 21150 -500 60 0000 C CNN
+ 6 21150 -500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6867E783
+P 23300 -500
+F 0 "U1" H 23350 -400 30 0000 C CNN
+F 1 "PORT" H 23300 -500 30 0000 C CNN
+F 2 "" H 23300 -500 60 0000 C CNN
+F 3 "" H 23300 -500 60 0000 C CNN
+ 9 23300 -500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6867ECB8
+P 25000 -550
+F 0 "U1" H 25050 -450 30 0000 C CNN
+F 1 "PORT" H 25000 -550 30 0000 C CNN
+F 2 "" H 25000 -550 60 0000 C CNN
+F 3 "" H 25000 -550 60 0000 C CNN
+ 11 25000 -550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6867F09D
+P 27650 950
+F 0 "U1" H 27700 1050 30 0000 C CNN
+F 1 "PORT" H 27650 950 30 0000 C CNN
+F 2 "" H 27650 950 60 0000 C CNN
+F 3 "" H 27650 950 60 0000 C CNN
+ 12 27650 950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U22
+U 1 1 68665BE0
+P 14100 12900
+F 0 "U22" H 14100 12900 60 0000 C CNN
+F 1 "d_dff" H 14100 13050 60 0000 C CNN
+F 2 "" H 14100 12900 60 0000 C CNN
+F 3 "" H 14100 12900 60 0000 C CNN
+ 1 14100 12900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U56
+U 1 1 686689C2
+P 23100 13000
+F 0 "U56" H 23100 12950 60 0000 C CNN
+F 1 "d_buffer" H 23100 13050 60 0000 C CNN
+F 2 "" H 23100 13000 60 0000 C CNN
+F 3 "" H 23100 13000 60 0000 C CNN
+ 1 23100 13000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U55
+U 1 1 68669858
+P 19250 13100
+F 0 "U55" H 19250 13050 60 0000 C CNN
+F 1 "d_buffer" H 19250 13150 60 0000 C CNN
+F 2 "" H 19250 13100 60 0000 C CNN
+F 3 "" H 19250 13100 60 0000 C CNN
+ 1 19250 13100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U57
+U 1 1 6866BF79
+P 27650 12850
+F 0 "U57" H 27650 12800 60 0000 C CNN
+F 1 "d_buffer" H 27650 12900 60 0000 C CNN
+F 2 "" H 27650 12850 60 0000 C CNN
+F 3 "" H 27650 12850 60 0000 C CNN
+ 1 27650 12850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U58
+U 1 1 6866E83D
+P 11250 13300
+F 0 "U58" H 11250 13250 60 0000 C CNN
+F 1 "d_buffer" H 11250 13350 60 0000 C CNN
+F 2 "" H 11250 13300 60 0000 C CNN
+F 3 "" H 11250 13300 60 0000 C CNN
+ 1 11250 13300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U54
+U 1 1 6866DC5D
+P 15350 13200
+F 0 "U54" H 15350 13150 60 0000 C CNN
+F 1 "d_buffer" H 15350 13250 60 0000 C CNN
+F 2 "" H 15350 13200 60 0000 C CNN
+F 3 "" H 15350 13200 60 0000 C CNN
+ 1 15350 13200
+ 1 0 0 -1
+$EndComp
+Text Label 8250 250 0 60 ~ 0
+0
+Text Label 10150 100 0 60 ~ 0
+1
+Text Label 12150 150 0 60 ~ 0
+2
+Text Label 13900 -50 0 60 ~ 0
+3
+Text Label 15800 -100 0 60 ~ 0
+4
+Text Label 17900 -50 0 60 ~ 0
+5
+Text Label 20000 -100 0 60 ~ 0
+6
+Text Label 21400 -200 0 60 ~ 0
+7
+Text Label 23600 -150 0 60 ~ 0
+8
+Text Label 25250 -150 0 60 ~ 0
+9
+Wire Wire Line
+ 14850 13200 14650 13200
+Wire Wire Line
+ 19900 13100 20600 13100
+Wire Wire Line
+ 4400 20600 9700 20600
+Wire Wire Line
+ 10600 13300 10750 13300
+Wire Wire Line
+ 27150 12850 27000 12850
+Wire Wire Line
+ 28400 12850 28300 12850
+Wire Wire Line
+ 23750 12600 23750 13000
+Wire Wire Line
+ 3750 13950 2650 13950
+Wire Wire Line
+ 25250 750 25250 -550
+Wire Wire Line
+ 23600 -500 23550 -500
+Wire Wire Line
+ 23600 750 23600 -500
+Wire Wire Line
+ 21400 750 21400 -500
+Wire Wire Line
+ 20000 -500 19950 -500
+Wire Wire Line
+ 20000 750 20000 -500
+Wire Wire Line
+ 17900 700 17900 -450
+Wire Wire Line
+ 15800 -450 15750 -450
+Wire Wire Line
+ 15800 650 15800 -450
+Wire Wire Line
+ 15800 650 15750 650
+Wire Wire Line
+ 13900 550 13900 -400
+Wire Wire Line
+ 12150 550 12150 -300
+Wire Wire Line
+ 10150 450 10150 -250
+Wire Wire Line
+ 8250 450 8250 -200
+Wire Wire Line
+ 25250 4000 25250 3250
+Wire Wire Line
+ 23600 4000 23600 3250
+Wire Wire Line
+ 21900 3250 21400 3250
+Wire Wire Line
+ 21900 4000 21900 3250
+Wire Wire Line
+ 20000 4000 20000 3250
+Wire Wire Line
+ 17900 4050 17900 3200
+Wire Wire Line
+ 15750 4050 15750 3150
+Wire Wire Line
+ 13900 3050 13900 4050
+Wire Wire Line
+ 12200 3050 12150 3050
+Wire Wire Line
+ 12200 4000 12200 3050
+Wire Wire Line
+ 10250 2950 10150 2950
+Wire Wire Line
+ 10250 2950 10250 4050
+Wire Wire Line
+ 8250 2950 8250 4050
+Wire Wire Line
+ 25250 1900 25250 2650
+Wire Wire Line
+ 23600 1900 23600 2650
+Wire Wire Line
+ 21400 1900 21400 2650
+Wire Wire Line
+ 20000 1900 20000 2650
+Wire Wire Line
+ 17900 1850 17900 2600
+Wire Wire Line
+ 15750 1800 15750 2550
+Wire Wire Line
+ 13900 1700 13900 2450
+Wire Wire Line
+ 12150 1700 12150 2450
+Wire Wire Line
+ 10150 1600 10150 2350
+Wire Wire Line
+ 8250 1600 8250 2350
+Wire Wire Line
+ 27900 1400 27900 950
+Wire Wire Line
+ 27900 2450 27900 2000
+Wire Wire Line
+ 27900 4150 27900 3600
+Wire Wire Line
+ 27900 5650 27900 5300
+Wire Wire Line
+ 27900 6950 27900 6250
+Wire Wire Line
+ 27900 7550 27900 7950
+Connection ~ 27900 9400
+Wire Wire Line
+ 27900 9100 27900 12200
+Wire Wire Line
+ 27900 12200 27000 12200
+Wire Wire Line
+ 25550 12200 25900 12200
+Wire Wire Line
+ 25550 12350 25550 12200
+Wire Wire Line
+ 16800 12450 17350 12450
+Wire Wire Line
+ 16800 15600 16800 12450
+Wire Wire Line
+ 16250 15600 16800 15600
+Wire Wire Line
+ 15150 15550 15350 15550
+Wire Wire Line
+ 14750 15650 15350 15650
+Wire Wire Line
+ 14750 16150 14750 15650
+Wire Wire Line
+ 14400 16150 14750 16150
+Wire Wire Line
+ 12600 16100 13500 16100
+Wire Wire Line
+ 12200 16200 13500 16200
+Wire Wire Line
+ 28400 11600 28400 12850
+Connection ~ 10050 13950
+Wire Wire Line
+ 10050 13600 10050 13950
+Connection ~ 14100 13950
+Wire Wire Line
+ 14100 13950 14100 13500
+Connection ~ 17850 13950
+Wire Wire Line
+ 17850 13950 17850 13400
+Connection ~ 22050 13950
+Wire Wire Line
+ 22050 13950 22050 13300
+Wire Wire Line
+ 26450 13950 26450 13150
+Wire Wire Line
+ 8150 13950 26450 13950
+Wire Wire Line
+ 5300 13950 4900 13950
+Wire Wire Line
+ 5900 13950 6150 13950
+Wire Wire Line
+ 7000 13950 6750 13950
+Connection ~ 21250 14350
+Wire Wire Line
+ 25700 14350 25700 12850
+Wire Wire Line
+ 25700 12850 25900 12850
+Connection ~ 17200 14350
+Wire Wire Line
+ 21250 14350 21250 13000
+Wire Wire Line
+ 21250 13000 21500 13000
+Connection ~ 13550 14350
+Wire Wire Line
+ 17200 14350 17200 13100
+Wire Wire Line
+ 17200 13100 17350 13100
+Connection ~ 8950 14350
+Wire Wire Line
+ 8950 14350 25700 14350
+Wire Wire Line
+ 13550 13200 13550 14350
+Wire Wire Line
+ 8950 13300 9500 13300
+Wire Wire Line
+ 8950 13300 8950 17650
+Wire Wire Line
+ 8950 17650 11350 17650
+Wire Wire Line
+ 11350 17650 11350 20650
+Wire Wire Line
+ 11350 20650 10600 20650
+Wire Wire Line
+ 4600 21550 4400 21550
+Wire Wire Line
+ 4400 20600 4400 20550
+Wire Wire Line
+ 9600 20700 9700 20700
+Wire Wire Line
+ 9600 21550 9600 20700
+Wire Wire Line
+ 9500 21550 9600 21550
+Wire Wire Line
+ 6250 21550 5750 21550
+Wire Wire Line
+ 7350 21550 6850 21550
+Wire Wire Line
+ 8350 21550 7950 21550
+Wire Wire Line
+ 15150 15550 15150 13650
+Wire Wire Line
+ 15150 13650 16150 13650
+Wire Wire Line
+ 16150 13650 16150 9050
+Wire Wire Line
+ 8300 4950 8300 6800
+Wire Wire Line
+ 8250 10100 19950 10100
+Wire Wire Line
+ 19950 10100 19950 4900
+Wire Wire Line
+ 10200 4950 10200 9850
+Wire Wire Line
+ 10200 9850 17850 9850
+Wire Wire Line
+ 17850 9850 17850 4950
+Wire Wire Line
+ 21850 9050 21850 4900
+Wire Wire Line
+ 10300 9050 21850 9050
+Wire Wire Line
+ 10300 9050 10300 4950
+Wire Wire Line
+ 8250 10100 8250 6800
+Wire Wire Line
+ 8250 6800 8300 6800
+Wire Wire Line
+ 12150 4900 12150 8850
+Wire Wire Line
+ 12150 8850 20050 8850
+Wire Wire Line
+ 20050 8850 20050 4900
+Wire Wire Line
+ 12250 4900 12250 8500
+Wire Wire Line
+ 12250 8450 23550 8450
+Wire Wire Line
+ 23550 8450 23550 4900
+Wire Wire Line
+ 13850 4950 13850 7650
+Wire Wire Line
+ 13850 7650 21950 7650
+Wire Wire Line
+ 21950 7650 21950 4900
+Wire Wire Line
+ 25200 7150 25200 4900
+Wire Wire Line
+ 13950 7150 25200 7150
+Wire Wire Line
+ 13950 7150 13950 4950
+Wire Wire Line
+ 23650 4900 23650 6600
+Wire Wire Line
+ 23650 6600 15700 6600
+Wire Wire Line
+ 15700 6600 15700 4950
+Wire Wire Line
+ 17950 4950 17950 5600
+Wire Wire Line
+ 17950 5600 25300 5600
+Wire Wire Line
+ 25300 4900 25300 9400
+Wire Wire Line
+ 7950 12650 9500 12650
+Wire Wire Line
+ 7950 5250 7950 12650
+Wire Wire Line
+ 7950 5250 8200 5250
+Wire Wire Line
+ 8200 5250 8200 4950
+Wire Wire Line
+ 15800 4950 15800 11600
+Wire Wire Line
+ 15800 5650 7950 5650
+Connection ~ 7950 5650
+Wire Wire Line
+ 12200 10100 12200 16200
+Wire Wire Line
+ 12200 13300 11900 13300
+Connection ~ 12200 10100
+Connection ~ 12200 13300
+Connection ~ 16150 9050
+Wire Wire Line
+ 16000 13200 16150 13200
+Connection ~ 16150 13200
+Wire Wire Line
+ 20550 8450 20550 12950
+Wire Wire Line
+ 20550 12950 20600 12950
+Wire Wire Line
+ 20600 12950 20600 13100
+Connection ~ 20550 8450
+Wire Wire Line
+ 12600 16100 12600 8500
+Wire Wire Line
+ 12600 8500 12250 8500
+Connection ~ 12250 8450
+Wire Wire Line
+ 24100 7150 24100 12600
+Wire Wire Line
+ 24100 12600 23750 12600
+Connection ~ 24100 7150
+Wire Wire Line
+ 15800 11600 28400 11600
+Connection ~ 15800 5650
+Wire Wire Line
+ 10600 12550 13550 12550
+Wire Wire Line
+ 10600 12550 10600 12650
+Wire Wire Line
+ 11200 12550 11200 9850
+Connection ~ 11200 9850
+Connection ~ 11200 12550
+Wire Wire Line
+ 14650 12550 15050 12550
+Wire Wire Line
+ 15050 12550 15050 8850
+Connection ~ 15050 8850
+Wire Wire Line
+ 19300 7650 19300 12450
+Connection ~ 19300 7650
+Connection ~ 19300 12450
+Wire Wire Line
+ 25550 12350 22600 12350
+Wire Wire Line
+ 23000 6600 23000 12350
+Connection ~ 23000 12350
+Connection ~ 23000 6600
+Wire Wire Line
+ 25300 9400 27900 9400
+Connection ~ 25300 5600
+Wire Wire Line
+ 18750 13100 18450 13100
+Wire Wire Line
+ 17850 13400 17900 13400
+NoConn ~ 17900 12150
+$Comp
+L d_dff U39
+U 1 1 686644FF
+P 22050 12700
+F 0 "U39" H 22050 12700 60 0000 C CNN
+F 1 "d_dff" H 22050 12850 60 0000 C CNN
+F 2 "" H 22050 12700 60 0000 C CNN
+F 3 "" H 22050 12700 60 0000 C CNN
+ 1 22050 12700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 18450 12450 21500 12450
+Wire Wire Line
+ 21500 12450 21500 12350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.cir b/library/SubcircuitLibrary/CD4017B/CD4017B.cir
new file mode 100644
index 000000000..0ab310773
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4017B/CD4017B.cir
@@ -0,0 +1,68 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4017B\CD4017B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/03/25 20:36:42
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U13 Net-_U11-Pad1_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U13-Pad5_ Net-_U13-Pad6_ d_dff
+U30 Net-_U26-Pad3_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U25-Pad1_ Net-_U30-Pad6_ d_dff
+U47 Net-_U29-Pad1_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U33-Pad2_ Net-_U47-Pad6_ d_dff
+U3 Net-_U1-Pad13_ Net-_U3-Pad2_ d_buffer
+U6 Net-_U3-Pad2_ Net-_U6-Pad2_ d_inverter
+U8 Net-_U6-Pad2_ Net-_U12-Pad1_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_buffer
+U14 Net-_U1-Pad14_ Net-_U12-Pad2_ Net-_U13-Pad2_ d_nor
+U2 Net-_U1-Pad15_ Net-_U2-Pad2_ d_buffer
+U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter
+U5 Net-_U4-Pad2_ Net-_U5-Pad2_ d_inverter
+U7 Net-_U5-Pad2_ Net-_U13-Pad4_ d_buffer
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad1_ d_nand
+U17 Net-_U13-Pad5_ Net-_U17-Pad2_ Net-_U16-Pad1_ d_nand
+U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U19-Pad1_ d_nand
+U25 Net-_U25-Pad1_ Net-_U25-Pad2_ Net-_U24-Pad1_ d_nand
+U29 Net-_U29-Pad1_ Net-_U11-Pad1_ Net-_U28-Pad1_ d_nand
+U33 Net-_U13-Pad5_ Net-_U33-Pad2_ Net-_U32-Pad1_ d_nand
+U36 Net-_U11-Pad2_ Net-_U20-Pad1_ Net-_U35-Pad1_ d_nand
+U40 Net-_U17-Pad2_ Net-_U25-Pad1_ Net-_U38-Pad1_ d_nand
+U43 Net-_U20-Pad2_ Net-_U29-Pad1_ Net-_U42-Pad1_ d_nand
+U46 Net-_U25-Pad2_ Net-_U33-Pad2_ Net-_U45-Pad1_ d_nand
+U21 Net-_U20-Pad2_ Net-_U11-Pad2_ Net-_U21-Pad3_ d_and
+U26 Net-_U17-Pad2_ Net-_U21-Pad3_ Net-_U26-Pad3_ d_nor
+U53 Net-_U33-Pad2_ Net-_U52-Pad1_ d_buffer
+U52 Net-_U52-Pad1_ Net-_U51-Pad1_ d_inverter
+U51 Net-_U51-Pad1_ Net-_U50-Pad1_ d_inverter
+U50 Net-_U50-Pad1_ Net-_U49-Pad1_ d_buffer
+U49 Net-_U49-Pad1_ Net-_U48-Pad1_ d_buffer
+U48 Net-_U48-Pad1_ Net-_U1-Pad12_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U9 Net-_U10-Pad2_ /0 d_buffer
+U16 Net-_U16-Pad1_ Net-_U15-Pad1_ d_inverter
+U15 Net-_U15-Pad1_ /1 d_buffer
+U19 Net-_U19-Pad1_ Net-_U18-Pad1_ d_inverter
+U18 Net-_U18-Pad1_ /2 d_buffer
+U24 Net-_U24-Pad1_ Net-_U23-Pad1_ d_inverter
+U23 Net-_U23-Pad1_ /3 d_buffer
+U28 Net-_U28-Pad1_ Net-_U27-Pad1_ d_inverter
+U27 Net-_U27-Pad1_ /4 d_buffer
+U32 Net-_U32-Pad1_ Net-_U31-Pad1_ d_inverter
+U31 Net-_U31-Pad1_ /5 d_buffer
+U35 Net-_U35-Pad1_ Net-_U34-Pad1_ d_inverter
+U34 Net-_U34-Pad1_ /6 d_buffer
+U38 Net-_U38-Pad1_ Net-_U37-Pad1_ d_inverter
+U37 Net-_U37-Pad1_ /7 d_buffer
+U42 Net-_U42-Pad1_ Net-_U41-Pad1_ d_inverter
+U41 Net-_U41-Pad1_ /8 d_buffer
+U45 Net-_U45-Pad1_ Net-_U44-Pad1_ d_inverter
+U44 Net-_U44-Pad1_ /9 d_buffer
+U1 /5 /1 /0 /2 /6 /7 /3 /8 /4 /9 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT
+U22 Net-_U13-Pad5_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U20-Pad1_ Net-_U22-Pad6_ d_dff
+U56 Net-_U39-Pad6_ Net-_U25-Pad2_ d_buffer
+U55 Net-_U30-Pad6_ Net-_U20-Pad2_ d_buffer
+U57 Net-_U47-Pad6_ Net-_U11-Pad1_ d_buffer
+U58 Net-_U13-Pad6_ Net-_U11-Pad2_ d_buffer
+U54 Net-_U22-Pad6_ Net-_U17-Pad2_ d_buffer
+U39 Net-_U25-Pad1_ Net-_U13-Pad2_ ? Net-_U13-Pad4_ Net-_U29-Pad1_ Net-_U39-Pad6_ d_dff
+
+.end
diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.cir.out b/library/SubcircuitLibrary/CD4017B/CD4017B.cir.out
new file mode 100644
index 000000000..ff224cae0
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4017B/CD4017B.cir.out
@@ -0,0 +1,240 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4017b\cd4017b.cir
+
+* u13 net-_u11-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u13-pad5_ net-_u13-pad6_ d_dff
+* u30 net-_u26-pad3_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u25-pad1_ net-_u30-pad6_ d_dff
+* u47 net-_u29-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u33-pad2_ net-_u47-pad6_ d_dff
+* u3 net-_u1-pad13_ net-_u3-pad2_ d_buffer
+* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter
+* u8 net-_u6-pad2_ net-_u12-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer
+* u14 net-_u1-pad14_ net-_u12-pad2_ net-_u13-pad2_ d_nor
+* u2 net-_u1-pad15_ net-_u2-pad2_ d_buffer
+* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter
+* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter
+* u7 net-_u5-pad2_ net-_u13-pad4_ d_buffer
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad1_ d_nand
+* u17 net-_u13-pad5_ net-_u17-pad2_ net-_u16-pad1_ d_nand
+* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u19-pad1_ d_nand
+* u25 net-_u25-pad1_ net-_u25-pad2_ net-_u24-pad1_ d_nand
+* u29 net-_u29-pad1_ net-_u11-pad1_ net-_u28-pad1_ d_nand
+* u33 net-_u13-pad5_ net-_u33-pad2_ net-_u32-pad1_ d_nand
+* u36 net-_u11-pad2_ net-_u20-pad1_ net-_u35-pad1_ d_nand
+* u40 net-_u17-pad2_ net-_u25-pad1_ net-_u38-pad1_ d_nand
+* u43 net-_u20-pad2_ net-_u29-pad1_ net-_u42-pad1_ d_nand
+* u46 net-_u25-pad2_ net-_u33-pad2_ net-_u45-pad1_ d_nand
+* u21 net-_u20-pad2_ net-_u11-pad2_ net-_u21-pad3_ d_and
+* u26 net-_u17-pad2_ net-_u21-pad3_ net-_u26-pad3_ d_nor
+* u53 net-_u33-pad2_ net-_u52-pad1_ d_buffer
+* u52 net-_u52-pad1_ net-_u51-pad1_ d_inverter
+* u51 net-_u51-pad1_ net-_u50-pad1_ d_inverter
+* u50 net-_u50-pad1_ net-_u49-pad1_ d_buffer
+* u49 net-_u49-pad1_ net-_u48-pad1_ d_buffer
+* u48 net-_u48-pad1_ net-_u1-pad12_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u9 net-_u10-pad2_ /0 d_buffer
+* u16 net-_u16-pad1_ net-_u15-pad1_ d_inverter
+* u15 net-_u15-pad1_ /1 d_buffer
+* u19 net-_u19-pad1_ net-_u18-pad1_ d_inverter
+* u18 net-_u18-pad1_ /2 d_buffer
+* u24 net-_u24-pad1_ net-_u23-pad1_ d_inverter
+* u23 net-_u23-pad1_ /3 d_buffer
+* u28 net-_u28-pad1_ net-_u27-pad1_ d_inverter
+* u27 net-_u27-pad1_ /4 d_buffer
+* u32 net-_u32-pad1_ net-_u31-pad1_ d_inverter
+* u31 net-_u31-pad1_ /5 d_buffer
+* u35 net-_u35-pad1_ net-_u34-pad1_ d_inverter
+* u34 net-_u34-pad1_ /6 d_buffer
+* u38 net-_u38-pad1_ net-_u37-pad1_ d_inverter
+* u37 net-_u37-pad1_ /7 d_buffer
+* u42 net-_u42-pad1_ net-_u41-pad1_ d_inverter
+* u41 net-_u41-pad1_ /8 d_buffer
+* u45 net-_u45-pad1_ net-_u44-pad1_ d_inverter
+* u44 net-_u44-pad1_ /9 d_buffer
+* u1 /5 /1 /0 /2 /6 /7 /3 /8 /4 /9 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port
+* u22 net-_u13-pad5_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u20-pad1_ net-_u22-pad6_ d_dff
+* u56 net-_u39-pad6_ net-_u25-pad2_ d_buffer
+* u55 net-_u30-pad6_ net-_u20-pad2_ d_buffer
+* u57 net-_u47-pad6_ net-_u11-pad1_ d_buffer
+* u58 net-_u13-pad6_ net-_u11-pad2_ d_buffer
+* u54 net-_u22-pad6_ net-_u17-pad2_ d_buffer
+* u39 net-_u25-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u29-pad1_ net-_u39-pad6_ d_dff
+a1 net-_u11-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u13-pad5_ net-_u13-pad6_ u13
+a2 net-_u26-pad3_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u25-pad1_ net-_u30-pad6_ u30
+a3 net-_u29-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u33-pad2_ net-_u47-pad6_ u47
+a4 net-_u1-pad13_ net-_u3-pad2_ u3
+a5 net-_u3-pad2_ net-_u6-pad2_ u6
+a6 net-_u6-pad2_ net-_u12-pad1_ u8
+a7 net-_u12-pad1_ net-_u12-pad2_ u12
+a8 [net-_u1-pad14_ net-_u12-pad2_ ] net-_u13-pad2_ u14
+a9 net-_u1-pad15_ net-_u2-pad2_ u2
+a10 net-_u2-pad2_ net-_u4-pad2_ u4
+a11 net-_u4-pad2_ net-_u5-pad2_ u5
+a12 net-_u5-pad2_ net-_u13-pad4_ u7
+a13 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad1_ u11
+a14 [net-_u13-pad5_ net-_u17-pad2_ ] net-_u16-pad1_ u17
+a15 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u19-pad1_ u20
+a16 [net-_u25-pad1_ net-_u25-pad2_ ] net-_u24-pad1_ u25
+a17 [net-_u29-pad1_ net-_u11-pad1_ ] net-_u28-pad1_ u29
+a18 [net-_u13-pad5_ net-_u33-pad2_ ] net-_u32-pad1_ u33
+a19 [net-_u11-pad2_ net-_u20-pad1_ ] net-_u35-pad1_ u36
+a20 [net-_u17-pad2_ net-_u25-pad1_ ] net-_u38-pad1_ u40
+a21 [net-_u20-pad2_ net-_u29-pad1_ ] net-_u42-pad1_ u43
+a22 [net-_u25-pad2_ net-_u33-pad2_ ] net-_u45-pad1_ u46
+a23 [net-_u20-pad2_ net-_u11-pad2_ ] net-_u21-pad3_ u21
+a24 [net-_u17-pad2_ net-_u21-pad3_ ] net-_u26-pad3_ u26
+a25 net-_u33-pad2_ net-_u52-pad1_ u53
+a26 net-_u52-pad1_ net-_u51-pad1_ u52
+a27 net-_u51-pad1_ net-_u50-pad1_ u51
+a28 net-_u50-pad1_ net-_u49-pad1_ u50
+a29 net-_u49-pad1_ net-_u48-pad1_ u49
+a30 net-_u48-pad1_ net-_u1-pad12_ u48
+a31 net-_u10-pad1_ net-_u10-pad2_ u10
+a32 net-_u10-pad2_ /0 u9
+a33 net-_u16-pad1_ net-_u15-pad1_ u16
+a34 net-_u15-pad1_ /1 u15
+a35 net-_u19-pad1_ net-_u18-pad1_ u19
+a36 net-_u18-pad1_ /2 u18
+a37 net-_u24-pad1_ net-_u23-pad1_ u24
+a38 net-_u23-pad1_ /3 u23
+a39 net-_u28-pad1_ net-_u27-pad1_ u28
+a40 net-_u27-pad1_ /4 u27
+a41 net-_u32-pad1_ net-_u31-pad1_ u32
+a42 net-_u31-pad1_ /5 u31
+a43 net-_u35-pad1_ net-_u34-pad1_ u35
+a44 net-_u34-pad1_ /6 u34
+a45 net-_u38-pad1_ net-_u37-pad1_ u38
+a46 net-_u37-pad1_ /7 u37
+a47 net-_u42-pad1_ net-_u41-pad1_ u42
+a48 net-_u41-pad1_ /8 u41
+a49 net-_u45-pad1_ net-_u44-pad1_ u45
+a50 net-_u44-pad1_ /9 u44
+a51 net-_u13-pad5_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u20-pad1_ net-_u22-pad6_ u22
+a52 net-_u39-pad6_ net-_u25-pad2_ u56
+a53 net-_u30-pad6_ net-_u20-pad2_ u55
+a54 net-_u47-pad6_ net-_u11-pad1_ u57
+a55 net-_u13-pad6_ net-_u11-pad2_ u58
+a56 net-_u22-pad6_ net-_u17-pad2_ u54
+a57 net-_u25-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u29-pad1_ net-_u39-pad6_ u39
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u47 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u53 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u50 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u49 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u15 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u34 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u37 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u41 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u56 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u55 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u57 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u58 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u54 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u39 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.pro b/library/SubcircuitLibrary/CD4017B/CD4017B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4017B/CD4017B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.sch b/library/SubcircuitLibrary/CD4017B/CD4017B.sch
new file mode 100644
index 000000000..5b9828289
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4017B/CD4017B.sch
@@ -0,0 +1,1203 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4017B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A0 46811 33110
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U13
+U 1 1 68664336
+P 18600 19250
+F 0 "U13" H 18600 19250 60 0000 C CNN
+F 1 "d_dff" H 18600 19400 60 0000 C CNN
+F 2 "" H 18600 19250 60 0000 C CNN
+F 3 "" H 18600 19250 60 0000 C CNN
+ 1 18600 19250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U30
+U 1 1 6866447A
+P 26450 19050
+F 0 "U30" H 26450 19050 60 0000 C CNN
+F 1 "d_dff" H 26450 19200 60 0000 C CNN
+F 2 "" H 26450 19050 60 0000 C CNN
+F 3 "" H 26450 19050 60 0000 C CNN
+ 1 26450 19050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U47
+U 1 1 686645F8
+P 35000 18800
+F 0 "U47" H 35000 18800 60 0000 C CNN
+F 1 "d_dff" H 35000 18950 60 0000 C CNN
+F 2 "" H 35000 18800 60 0000 C CNN
+F 3 "" H 35000 18800 60 0000 C CNN
+ 1 35000 18800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U3
+U 1 1 686647DD
+P 13650 27800
+F 0 "U3" H 13650 27750 60 0000 C CNN
+F 1 "d_buffer" H 13650 27850 60 0000 C CNN
+F 2 "" H 13650 27800 60 0000 C CNN
+F 3 "" H 13650 27800 60 0000 C CNN
+ 1 13650 27800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68664852
+P 15100 27800
+F 0 "U6" H 15100 27700 60 0000 C CNN
+F 1 "d_inverter" H 15100 27950 60 0000 C CNN
+F 2 "" H 15150 27750 60 0000 C CNN
+F 3 "" H 15150 27750 60 0000 C CNN
+ 1 15100 27800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 686648C7
+P 16200 27800
+F 0 "U8" H 16200 27700 60 0000 C CNN
+F 1 "d_inverter" H 16200 27950 60 0000 C CNN
+F 2 "" H 16250 27750 60 0000 C CNN
+F 3 "" H 16250 27750 60 0000 C CNN
+ 1 16200 27800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U12
+U 1 1 68664946
+P 17400 27800
+F 0 "U12" H 17400 27750 60 0000 C CNN
+F 1 "d_buffer" H 17400 27850 60 0000 C CNN
+F 2 "" H 17400 27800 60 0000 C CNN
+F 3 "" H 17400 27800 60 0000 C CNN
+ 1 17400 27800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U14
+U 1 1 68664AE0
+P 18700 26950
+F 0 "U14" H 18700 26950 60 0000 C CNN
+F 1 "d_nor" H 18750 27050 60 0000 C CNN
+F 2 "" H 18700 26950 60 0000 C CNN
+F 3 "" H 18700 26950 60 0000 C CNN
+ 1 18700 26950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U2
+U 1 1 686655EB
+P 12800 20200
+F 0 "U2" H 12800 20150 60 0000 C CNN
+F 1 "d_buffer" H 12800 20250 60 0000 C CNN
+F 2 "" H 12800 20200 60 0000 C CNN
+F 3 "" H 12800 20200 60 0000 C CNN
+ 1 12800 20200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 68665755
+P 14150 20200
+F 0 "U4" H 14150 20100 60 0000 C CNN
+F 1 "d_inverter" H 14150 20350 60 0000 C CNN
+F 2 "" H 14200 20150 60 0000 C CNN
+F 3 "" H 14200 20150 60 0000 C CNN
+ 1 14150 20200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 68665840
+P 15000 20200
+F 0 "U5" H 15000 20100 60 0000 C CNN
+F 1 "d_inverter" H 15000 20350 60 0000 C CNN
+F 2 "" H 15050 20150 60 0000 C CNN
+F 3 "" H 15050 20150 60 0000 C CNN
+ 1 15000 20200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U7
+U 1 1 68665887
+P 16050 20200
+F 0 "U7" H 16050 20150 60 0000 C CNN
+F 1 "d_buffer" H 16050 20250 60 0000 C CNN
+F 2 "" H 16050 20200 60 0000 C CNN
+F 3 "" H 16050 20200 60 0000 C CNN
+ 1 16050 20200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U11
+U 1 1 68666477
+P 16850 10750
+F 0 "U11" H 16850 10750 60 0000 C CNN
+F 1 "d_nand" H 16900 10850 60 0000 C CNN
+F 2 "" H 16850 10750 60 0000 C CNN
+F 3 "" H 16850 10750 60 0000 C CNN
+ 1 16850 10750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U17
+U 1 1 686665F7
+P 18850 10750
+F 0 "U17" H 18850 10750 60 0000 C CNN
+F 1 "d_nand" H 18900 10850 60 0000 C CNN
+F 2 "" H 18850 10750 60 0000 C CNN
+F 3 "" H 18850 10750 60 0000 C CNN
+ 1 18850 10750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U20
+U 1 1 686666A4
+P 20800 10700
+F 0 "U20" H 20800 10700 60 0000 C CNN
+F 1 "d_nand" H 20850 10800 60 0000 C CNN
+F 2 "" H 20800 10700 60 0000 C CNN
+F 3 "" H 20800 10700 60 0000 C CNN
+ 1 20800 10700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U25
+U 1 1 686667BA
+P 22500 10750
+F 0 "U25" H 22500 10750 60 0000 C CNN
+F 1 "d_nand" H 22550 10850 60 0000 C CNN
+F 2 "" H 22500 10750 60 0000 C CNN
+F 3 "" H 22500 10750 60 0000 C CNN
+ 1 22500 10750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U29
+U 1 1 68666843
+P 24350 10750
+F 0 "U29" H 24350 10750 60 0000 C CNN
+F 1 "d_nand" H 24400 10850 60 0000 C CNN
+F 2 "" H 24350 10750 60 0000 C CNN
+F 3 "" H 24350 10750 60 0000 C CNN
+ 1 24350 10750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U33
+U 1 1 686668C6
+P 26500 10750
+F 0 "U33" H 26500 10750 60 0000 C CNN
+F 1 "d_nand" H 26550 10850 60 0000 C CNN
+F 2 "" H 26500 10750 60 0000 C CNN
+F 3 "" H 26500 10750 60 0000 C CNN
+ 1 26500 10750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U36
+U 1 1 686669C1
+P 28600 10700
+F 0 "U36" H 28600 10700 60 0000 C CNN
+F 1 "d_nand" H 28650 10800 60 0000 C CNN
+F 2 "" H 28600 10700 60 0000 C CNN
+F 3 "" H 28600 10700 60 0000 C CNN
+ 1 28600 10700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U40
+U 1 1 68666A5C
+P 30500 10700
+F 0 "U40" H 30500 10700 60 0000 C CNN
+F 1 "d_nand" H 30550 10800 60 0000 C CNN
+F 2 "" H 30500 10700 60 0000 C CNN
+F 3 "" H 30500 10700 60 0000 C CNN
+ 1 30500 10700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U43
+U 1 1 68666BA5
+P 32200 10700
+F 0 "U43" H 32200 10700 60 0000 C CNN
+F 1 "d_nand" H 32250 10800 60 0000 C CNN
+F 2 "" H 32200 10700 60 0000 C CNN
+F 3 "" H 32200 10700 60 0000 C CNN
+ 1 32200 10700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_nand U46
+U 1 1 68666C44
+P 33850 10700
+F 0 "U46" H 33850 10700 60 0000 C CNN
+F 1 "d_nand" H 33900 10800 60 0000 C CNN
+F 2 "" H 33850 10700 60 0000 C CNN
+F 3 "" H 33850 10700 60 0000 C CNN
+ 1 33850 10700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_and U21
+U 1 1 6866E2FD
+P 22500 22450
+F 0 "U21" H 22500 22450 60 0000 C CNN
+F 1 "d_and" H 22550 22550 60 0000 C CNN
+F 2 "" H 22500 22450 60 0000 C CNN
+F 3 "" H 22500 22450 60 0000 C CNN
+ 1 22500 22450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U26
+U 1 1 6866E390
+P 24350 21900
+F 0 "U26" H 24350 21900 60 0000 C CNN
+F 1 "d_nor" H 24400 22000 60 0000 C CNN
+F 2 "" H 24350 21900 60 0000 C CNN
+F 3 "" H 24350 21900 60 0000 C CNN
+ 1 24350 21900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U53
+U 1 1 686742A7
+P 36450 14850
+F 0 "U53" H 36450 14800 60 0000 C CNN
+F 1 "d_buffer" H 36450 14900 60 0000 C CNN
+F 2 "" H 36450 14850 60 0000 C CNN
+F 3 "" H 36450 14850 60 0000 C CNN
+ 1 36450 14850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U52
+U 1 1 68674360
+P 36450 13500
+F 0 "U52" H 36450 13400 60 0000 C CNN
+F 1 "d_inverter" H 36450 13650 60 0000 C CNN
+F 2 "" H 36500 13450 60 0000 C CNN
+F 3 "" H 36500 13450 60 0000 C CNN
+ 1 36450 13500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U51
+U 1 1 686743E3
+P 36450 12200
+F 0 "U51" H 36450 12100 60 0000 C CNN
+F 1 "d_inverter" H 36450 12350 60 0000 C CNN
+F 2 "" H 36500 12150 60 0000 C CNN
+F 3 "" H 36500 12150 60 0000 C CNN
+ 1 36450 12200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U50
+U 1 1 68674539
+P 36450 11050
+F 0 "U50" H 36450 11000 60 0000 C CNN
+F 1 "d_buffer" H 36450 11100 60 0000 C CNN
+F 2 "" H 36450 11050 60 0000 C CNN
+F 3 "" H 36450 11050 60 0000 C CNN
+ 1 36450 11050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U49
+U 1 1 686745C8
+P 36450 9350
+F 0 "U49" H 36450 9300 60 0000 C CNN
+F 1 "d_buffer" H 36450 9400 60 0000 C CNN
+F 2 "" H 36450 9350 60 0000 C CNN
+F 3 "" H 36450 9350 60 0000 C CNN
+ 1 36450 9350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U48
+U 1 1 68674685
+P 36450 7950
+F 0 "U48" H 36450 7850 60 0000 C CNN
+F 1 "d_inverter" H 36450 8100 60 0000 C CNN
+F 2 "" H 36500 7900 60 0000 C CNN
+F 3 "" H 36500 7900 60 0000 C CNN
+ 1 36450 7950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 686757F7
+P 16800 8900
+F 0 "U10" H 16800 8800 60 0000 C CNN
+F 1 "d_inverter" H 16800 9050 60 0000 C CNN
+F 2 "" H 16850 8850 60 0000 C CNN
+F 3 "" H 16850 8850 60 0000 C CNN
+ 1 16800 8900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U9
+U 1 1 686758E8
+P 16800 7350
+F 0 "U9" H 16800 7300 60 0000 C CNN
+F 1 "d_buffer" H 16800 7400 60 0000 C CNN
+F 2 "" H 16800 7350 60 0000 C CNN
+F 3 "" H 16800 7350 60 0000 C CNN
+ 1 16800 7350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 68675D57
+P 18700 8900
+F 0 "U16" H 18700 8800 60 0000 C CNN
+F 1 "d_inverter" H 18700 9050 60 0000 C CNN
+F 2 "" H 18750 8850 60 0000 C CNN
+F 3 "" H 18750 8850 60 0000 C CNN
+ 1 18700 8900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U15
+U 1 1 68675D5D
+P 18700 7350
+F 0 "U15" H 18700 7300 60 0000 C CNN
+F 1 "d_buffer" H 18700 7400 60 0000 C CNN
+F 2 "" H 18700 7350 60 0000 C CNN
+F 3 "" H 18700 7350 60 0000 C CNN
+ 1 18700 7350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U19
+U 1 1 68676262
+P 20700 9000
+F 0 "U19" H 20700 8900 60 0000 C CNN
+F 1 "d_inverter" H 20700 9150 60 0000 C CNN
+F 2 "" H 20750 8950 60 0000 C CNN
+F 3 "" H 20750 8950 60 0000 C CNN
+ 1 20700 9000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U18
+U 1 1 68676268
+P 20700 7450
+F 0 "U18" H 20700 7400 60 0000 C CNN
+F 1 "d_buffer" H 20700 7500 60 0000 C CNN
+F 2 "" H 20700 7450 60 0000 C CNN
+F 3 "" H 20700 7450 60 0000 C CNN
+ 1 20700 7450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U24
+U 1 1 6867626F
+P 22450 9000
+F 0 "U24" H 22450 8900 60 0000 C CNN
+F 1 "d_inverter" H 22450 9150 60 0000 C CNN
+F 2 "" H 22500 8950 60 0000 C CNN
+F 3 "" H 22500 8950 60 0000 C CNN
+ 1 22450 9000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U23
+U 1 1 68676275
+P 22450 7450
+F 0 "U23" H 22450 7400 60 0000 C CNN
+F 1 "d_buffer" H 22450 7500 60 0000 C CNN
+F 2 "" H 22450 7450 60 0000 C CNN
+F 3 "" H 22450 7450 60 0000 C CNN
+ 1 22450 7450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U28
+U 1 1 6867676C
+P 24300 9100
+F 0 "U28" H 24300 9000 60 0000 C CNN
+F 1 "d_inverter" H 24300 9250 60 0000 C CNN
+F 2 "" H 24350 9050 60 0000 C CNN
+F 3 "" H 24350 9050 60 0000 C CNN
+ 1 24300 9100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U27
+U 1 1 68676772
+P 24300 7550
+F 0 "U27" H 24300 7500 60 0000 C CNN
+F 1 "d_buffer" H 24300 7600 60 0000 C CNN
+F 2 "" H 24300 7550 60 0000 C CNN
+F 3 "" H 24300 7550 60 0000 C CNN
+ 1 24300 7550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U32
+U 1 1 68676779
+P 26450 9150
+F 0 "U32" H 26450 9050 60 0000 C CNN
+F 1 "d_inverter" H 26450 9300 60 0000 C CNN
+F 2 "" H 26500 9100 60 0000 C CNN
+F 3 "" H 26500 9100 60 0000 C CNN
+ 1 26450 9150
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U31
+U 1 1 6867677F
+P 26450 7600
+F 0 "U31" H 26450 7550 60 0000 C CNN
+F 1 "d_buffer" H 26450 7650 60 0000 C CNN
+F 2 "" H 26450 7600 60 0000 C CNN
+F 3 "" H 26450 7600 60 0000 C CNN
+ 1 26450 7600
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U35
+U 1 1 68676786
+P 28550 9200
+F 0 "U35" H 28550 9100 60 0000 C CNN
+F 1 "d_inverter" H 28550 9350 60 0000 C CNN
+F 2 "" H 28600 9150 60 0000 C CNN
+F 3 "" H 28600 9150 60 0000 C CNN
+ 1 28550 9200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U34
+U 1 1 6867678C
+P 28550 7650
+F 0 "U34" H 28550 7600 60 0000 C CNN
+F 1 "d_buffer" H 28550 7700 60 0000 C CNN
+F 2 "" H 28550 7650 60 0000 C CNN
+F 3 "" H 28550 7650 60 0000 C CNN
+ 1 28550 7650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U38
+U 1 1 68676793
+P 29950 9200
+F 0 "U38" H 29950 9100 60 0000 C CNN
+F 1 "d_inverter" H 29950 9350 60 0000 C CNN
+F 2 "" H 30000 9150 60 0000 C CNN
+F 3 "" H 30000 9150 60 0000 C CNN
+ 1 29950 9200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U37
+U 1 1 68676799
+P 29950 7650
+F 0 "U37" H 29950 7600 60 0000 C CNN
+F 1 "d_buffer" H 29950 7700 60 0000 C CNN
+F 2 "" H 29950 7650 60 0000 C CNN
+F 3 "" H 29950 7650 60 0000 C CNN
+ 1 29950 7650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U42
+U 1 1 68676C38
+P 32150 9200
+F 0 "U42" H 32150 9100 60 0000 C CNN
+F 1 "d_inverter" H 32150 9350 60 0000 C CNN
+F 2 "" H 32200 9150 60 0000 C CNN
+F 3 "" H 32200 9150 60 0000 C CNN
+ 1 32150 9200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U41
+U 1 1 68676C3E
+P 32150 7650
+F 0 "U41" H 32150 7600 60 0000 C CNN
+F 1 "d_buffer" H 32150 7700 60 0000 C CNN
+F 2 "" H 32150 7650 60 0000 C CNN
+F 3 "" H 32150 7650 60 0000 C CNN
+ 1 32150 7650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_inverter U45
+U 1 1 68676C45
+P 33800 9200
+F 0 "U45" H 33800 9100 60 0000 C CNN
+F 1 "d_inverter" H 33800 9350 60 0000 C CNN
+F 2 "" H 33850 9150 60 0000 C CNN
+F 3 "" H 33850 9150 60 0000 C CNN
+ 1 33800 9200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L d_buffer U44
+U 1 1 68676C4B
+P 33800 7650
+F 0 "U44" H 33800 7600 60 0000 C CNN
+F 1 "d_buffer" H 33800 7700 60 0000 C CNN
+F 2 "" H 33800 7650 60 0000 C CNN
+F 3 "" H 33800 7650 60 0000 C CNN
+ 1 33800 7650
+ 0 -1 -1 0
+$EndComp
+NoConn ~ 18600 18600
+NoConn ~ 22650 18500
+NoConn ~ 30600 18300
+NoConn ~ 35000 18150
+$Comp
+L PORT U1
+U 15 1 6867C073
+P 10950 20200
+F 0 "U1" H 11000 20300 30 0000 C CNN
+F 1 "PORT" H 10950 20200 30 0000 C CNN
+F 2 "" H 10950 20200 60 0000 C CNN
+F 3 "" H 10950 20200 60 0000 C CNN
+ 15 10950 20200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6867C485
+P 12700 26800
+F 0 "U1" H 12750 26900 30 0000 C CNN
+F 1 "PORT" H 12700 26800 30 0000 C CNN
+F 2 "" H 12700 26800 60 0000 C CNN
+F 3 "" H 12700 26800 60 0000 C CNN
+ 14 12700 26800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6867C98A
+P 12700 27800
+F 0 "U1" H 12750 27900 30 0000 C CNN
+F 1 "PORT" H 12700 27800 30 0000 C CNN
+F 2 "" H 12700 27800 60 0000 C CNN
+F 3 "" H 12700 27800 60 0000 C CNN
+ 13 12700 27800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6867CA21
+P 16550 6050
+F 0 "U1" H 16600 6150 30 0000 C CNN
+F 1 "PORT" H 16550 6050 30 0000 C CNN
+F 2 "" H 16550 6050 60 0000 C CNN
+F 3 "" H 16550 6050 60 0000 C CNN
+ 3 16550 6050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6867D1A2
+P 18450 6000
+F 0 "U1" H 18500 6100 30 0000 C CNN
+F 1 "PORT" H 18450 6000 30 0000 C CNN
+F 2 "" H 18450 6000 60 0000 C CNN
+F 3 "" H 18450 6000 60 0000 C CNN
+ 2 18450 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6867D490
+P 20450 5950
+F 0 "U1" H 20500 6050 30 0000 C CNN
+F 1 "PORT" H 20450 5950 30 0000 C CNN
+F 2 "" H 20450 5950 60 0000 C CNN
+F 3 "" H 20450 5950 60 0000 C CNN
+ 4 20450 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6867D78D
+P 22200 5850
+F 0 "U1" H 22250 5950 30 0000 C CNN
+F 1 "PORT" H 22200 5850 30 0000 C CNN
+F 2 "" H 22200 5850 60 0000 C CNN
+F 3 "" H 22200 5850 60 0000 C CNN
+ 7 22200 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6867DA81
+P 24050 5800
+F 0 "U1" H 24100 5900 30 0000 C CNN
+F 1 "PORT" H 24050 5800 30 0000 C CNN
+F 2 "" H 24050 5800 60 0000 C CNN
+F 3 "" H 24050 5800 60 0000 C CNN
+ 10 24050 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6867DCF8
+P 26200 5800
+F 0 "U1" H 26250 5900 30 0000 C CNN
+F 1 "PORT" H 26200 5800 30 0000 C CNN
+F 2 "" H 26200 5800 60 0000 C CNN
+F 3 "" H 26200 5800 60 0000 C CNN
+ 1 26200 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6867E1B9
+P 28250 5750
+F 0 "U1" H 28300 5850 30 0000 C CNN
+F 1 "PORT" H 28250 5750 30 0000 C CNN
+F 2 "" H 28250 5750 60 0000 C CNN
+F 3 "" H 28250 5750 60 0000 C CNN
+ 5 28250 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6867E540
+P 29700 5750
+F 0 "U1" H 29750 5850 30 0000 C CNN
+F 1 "PORT" H 29700 5750 30 0000 C CNN
+F 2 "" H 29700 5750 60 0000 C CNN
+F 3 "" H 29700 5750 60 0000 C CNN
+ 6 29700 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6867E783
+P 31850 5750
+F 0 "U1" H 31900 5850 30 0000 C CNN
+F 1 "PORT" H 31850 5750 30 0000 C CNN
+F 2 "" H 31850 5750 60 0000 C CNN
+F 3 "" H 31850 5750 60 0000 C CNN
+ 9 31850 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6867ECB8
+P 33550 5700
+F 0 "U1" H 33600 5800 30 0000 C CNN
+F 1 "PORT" H 33550 5700 30 0000 C CNN
+F 2 "" H 33550 5700 60 0000 C CNN
+F 3 "" H 33550 5700 60 0000 C CNN
+ 11 33550 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6867F09D
+P 36200 7200
+F 0 "U1" H 36250 7300 30 0000 C CNN
+F 1 "PORT" H 36200 7200 30 0000 C CNN
+F 2 "" H 36200 7200 60 0000 C CNN
+F 3 "" H 36200 7200 60 0000 C CNN
+ 12 36200 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U22
+U 1 1 68665BE0
+P 22650 19150
+F 0 "U22" H 22650 19150 60 0000 C CNN
+F 1 "d_dff" H 22650 19300 60 0000 C CNN
+F 2 "" H 22650 19150 60 0000 C CNN
+F 3 "" H 22650 19150 60 0000 C CNN
+ 1 22650 19150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U56
+U 1 1 686689C2
+P 31650 19250
+F 0 "U56" H 31650 19200 60 0000 C CNN
+F 1 "d_buffer" H 31650 19300 60 0000 C CNN
+F 2 "" H 31650 19250 60 0000 C CNN
+F 3 "" H 31650 19250 60 0000 C CNN
+ 1 31650 19250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U55
+U 1 1 68669858
+P 27800 19350
+F 0 "U55" H 27800 19300 60 0000 C CNN
+F 1 "d_buffer" H 27800 19400 60 0000 C CNN
+F 2 "" H 27800 19350 60 0000 C CNN
+F 3 "" H 27800 19350 60 0000 C CNN
+ 1 27800 19350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U57
+U 1 1 6866BF79
+P 36200 19100
+F 0 "U57" H 36200 19050 60 0000 C CNN
+F 1 "d_buffer" H 36200 19150 60 0000 C CNN
+F 2 "" H 36200 19100 60 0000 C CNN
+F 3 "" H 36200 19100 60 0000 C CNN
+ 1 36200 19100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U58
+U 1 1 6866E83D
+P 19800 19550
+F 0 "U58" H 19800 19500 60 0000 C CNN
+F 1 "d_buffer" H 19800 19600 60 0000 C CNN
+F 2 "" H 19800 19550 60 0000 C CNN
+F 3 "" H 19800 19550 60 0000 C CNN
+ 1 19800 19550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U54
+U 1 1 6866DC5D
+P 23900 19450
+F 0 "U54" H 23900 19400 60 0000 C CNN
+F 1 "d_buffer" H 23900 19500 60 0000 C CNN
+F 2 "" H 23900 19450 60 0000 C CNN
+F 3 "" H 23900 19450 60 0000 C CNN
+ 1 23900 19450
+ 1 0 0 -1
+$EndComp
+Text Label 16800 6500 0 60 ~ 0
+0
+Text Label 18700 6350 0 60 ~ 0
+1
+Text Label 20700 6400 0 60 ~ 0
+2
+Text Label 22450 6200 0 60 ~ 0
+3
+Text Label 24350 6150 0 60 ~ 0
+4
+Text Label 26450 6200 0 60 ~ 0
+5
+Text Label 28550 6150 0 60 ~ 0
+6
+Text Label 29950 6050 0 60 ~ 0
+7
+Text Label 32150 6100 0 60 ~ 0
+8
+Text Label 33800 6100 0 60 ~ 0
+9
+Wire Wire Line
+ 23400 19450 23200 19450
+Wire Wire Line
+ 28450 19350 29150 19350
+Wire Wire Line
+ 12950 26850 18250 26850
+Wire Wire Line
+ 19150 19550 19300 19550
+Wire Wire Line
+ 35700 19100 35550 19100
+Wire Wire Line
+ 36950 19100 36850 19100
+Wire Wire Line
+ 32300 18850 32300 19250
+Wire Wire Line
+ 12300 20200 11200 20200
+Wire Wire Line
+ 33800 7000 33800 5700
+Wire Wire Line
+ 32150 5750 32100 5750
+Wire Wire Line
+ 32150 7000 32150 5750
+Wire Wire Line
+ 29950 7000 29950 5750
+Wire Wire Line
+ 28550 5750 28500 5750
+Wire Wire Line
+ 28550 7000 28550 5750
+Wire Wire Line
+ 26450 6950 26450 5800
+Wire Wire Line
+ 24350 5800 24300 5800
+Wire Wire Line
+ 24350 6900 24350 5800
+Wire Wire Line
+ 24350 6900 24300 6900
+Wire Wire Line
+ 22450 6800 22450 5850
+Wire Wire Line
+ 20700 6800 20700 5950
+Wire Wire Line
+ 18700 6700 18700 6000
+Wire Wire Line
+ 16800 6700 16800 6050
+Wire Wire Line
+ 33800 10250 33800 9500
+Wire Wire Line
+ 32150 10250 32150 9500
+Wire Wire Line
+ 30450 9500 29950 9500
+Wire Wire Line
+ 30450 10250 30450 9500
+Wire Wire Line
+ 28550 10250 28550 9500
+Wire Wire Line
+ 26450 10300 26450 9450
+Wire Wire Line
+ 24300 10300 24300 9400
+Wire Wire Line
+ 22450 9300 22450 10300
+Wire Wire Line
+ 20750 9300 20700 9300
+Wire Wire Line
+ 20750 10250 20750 9300
+Wire Wire Line
+ 18800 9200 18700 9200
+Wire Wire Line
+ 18800 9200 18800 10300
+Wire Wire Line
+ 16800 9200 16800 10300
+Wire Wire Line
+ 33800 8150 33800 8900
+Wire Wire Line
+ 32150 8150 32150 8900
+Wire Wire Line
+ 29950 8150 29950 8900
+Wire Wire Line
+ 28550 8150 28550 8900
+Wire Wire Line
+ 26450 8100 26450 8850
+Wire Wire Line
+ 24300 8050 24300 8800
+Wire Wire Line
+ 22450 7950 22450 8700
+Wire Wire Line
+ 20700 7950 20700 8700
+Wire Wire Line
+ 18700 7850 18700 8600
+Wire Wire Line
+ 16800 7850 16800 8600
+Wire Wire Line
+ 36450 7650 36450 7200
+Wire Wire Line
+ 36450 8700 36450 8250
+Wire Wire Line
+ 36450 10400 36450 9850
+Wire Wire Line
+ 36450 11900 36450 11550
+Wire Wire Line
+ 36450 13200 36450 12500
+Wire Wire Line
+ 36450 13800 36450 14200
+Connection ~ 36450 15650
+Wire Wire Line
+ 36450 15350 36450 18450
+Wire Wire Line
+ 36450 18450 35550 18450
+Wire Wire Line
+ 34100 18450 34450 18450
+Wire Wire Line
+ 34100 18600 34100 18450
+Wire Wire Line
+ 25350 18700 25900 18700
+Wire Wire Line
+ 25350 21850 25350 18700
+Wire Wire Line
+ 24800 21850 25350 21850
+Wire Wire Line
+ 23700 21800 23900 21800
+Wire Wire Line
+ 23300 21900 23900 21900
+Wire Wire Line
+ 23300 22400 23300 21900
+Wire Wire Line
+ 22950 22400 23300 22400
+Wire Wire Line
+ 21150 22350 22050 22350
+Wire Wire Line
+ 20750 22450 22050 22450
+Wire Wire Line
+ 36950 17850 36950 19100
+Connection ~ 18600 20200
+Wire Wire Line
+ 18600 19850 18600 20200
+Connection ~ 22650 20200
+Wire Wire Line
+ 22650 20200 22650 19750
+Connection ~ 26400 20200
+Wire Wire Line
+ 26400 20200 26400 19650
+Connection ~ 30600 20200
+Wire Wire Line
+ 30600 20200 30600 19550
+Wire Wire Line
+ 35000 20200 35000 19400
+Wire Wire Line
+ 16700 20200 35000 20200
+Wire Wire Line
+ 13850 20200 13450 20200
+Wire Wire Line
+ 14450 20200 14700 20200
+Wire Wire Line
+ 15550 20200 15300 20200
+Connection ~ 29800 20600
+Wire Wire Line
+ 34250 20600 34250 19100
+Wire Wire Line
+ 34250 19100 34450 19100
+Connection ~ 25750 20600
+Wire Wire Line
+ 29800 20600 29800 19250
+Wire Wire Line
+ 29800 19250 30050 19250
+Connection ~ 22100 20600
+Wire Wire Line
+ 25750 20600 25750 19350
+Wire Wire Line
+ 25750 19350 25900 19350
+Connection ~ 17500 20600
+Wire Wire Line
+ 17500 20600 34250 20600
+Wire Wire Line
+ 22100 19450 22100 20600
+Wire Wire Line
+ 17500 19550 18050 19550
+Wire Wire Line
+ 17500 19550 17500 23900
+Wire Wire Line
+ 17500 23900 19900 23900
+Wire Wire Line
+ 19900 23900 19900 26900
+Wire Wire Line
+ 19900 26900 19150 26900
+Wire Wire Line
+ 13150 27800 12950 27800
+Wire Wire Line
+ 12950 26850 12950 26800
+Wire Wire Line
+ 18150 26950 18250 26950
+Wire Wire Line
+ 18150 27800 18150 26950
+Wire Wire Line
+ 18050 27800 18150 27800
+Wire Wire Line
+ 14800 27800 14300 27800
+Wire Wire Line
+ 15900 27800 15400 27800
+Wire Wire Line
+ 16900 27800 16500 27800
+Wire Wire Line
+ 23700 21800 23700 19900
+Wire Wire Line
+ 23700 19900 24700 19900
+Wire Wire Line
+ 24700 19900 24700 15300
+Wire Wire Line
+ 16850 11200 16850 13050
+Wire Wire Line
+ 16800 16350 28500 16350
+Wire Wire Line
+ 28500 16350 28500 11150
+Wire Wire Line
+ 18750 11200 18750 16100
+Wire Wire Line
+ 18750 16100 26400 16100
+Wire Wire Line
+ 26400 16100 26400 11200
+Wire Wire Line
+ 30400 15300 30400 11150
+Wire Wire Line
+ 18850 15300 30400 15300
+Wire Wire Line
+ 18850 15300 18850 11200
+Wire Wire Line
+ 16800 16350 16800 13050
+Wire Wire Line
+ 16800 13050 16850 13050
+Wire Wire Line
+ 20700 11150 20700 15100
+Wire Wire Line
+ 20700 15100 28600 15100
+Wire Wire Line
+ 28600 15100 28600 11150
+Wire Wire Line
+ 20800 11150 20800 14750
+Wire Wire Line
+ 20800 14700 32100 14700
+Wire Wire Line
+ 32100 14700 32100 11150
+Wire Wire Line
+ 22400 11200 22400 13900
+Wire Wire Line
+ 22400 13900 30500 13900
+Wire Wire Line
+ 30500 13900 30500 11150
+Wire Wire Line
+ 33750 13400 33750 11150
+Wire Wire Line
+ 22500 13400 33750 13400
+Wire Wire Line
+ 22500 13400 22500 11200
+Wire Wire Line
+ 32200 11150 32200 12850
+Wire Wire Line
+ 32200 12850 24250 12850
+Wire Wire Line
+ 24250 12850 24250 11200
+Wire Wire Line
+ 26500 11200 26500 11850
+Wire Wire Line
+ 26500 11850 33850 11850
+Wire Wire Line
+ 33850 11150 33850 15650
+Wire Wire Line
+ 16500 18900 18050 18900
+Wire Wire Line
+ 16500 11500 16500 18900
+Wire Wire Line
+ 16500 11500 16750 11500
+Wire Wire Line
+ 16750 11500 16750 11200
+Wire Wire Line
+ 24350 11200 24350 17850
+Wire Wire Line
+ 24350 11900 16500 11900
+Connection ~ 16500 11900
+Wire Wire Line
+ 20750 16350 20750 22450
+Wire Wire Line
+ 20750 19550 20450 19550
+Connection ~ 20750 16350
+Connection ~ 20750 19550
+Connection ~ 24700 15300
+Wire Wire Line
+ 24550 19450 24700 19450
+Connection ~ 24700 19450
+Wire Wire Line
+ 29100 14700 29100 19200
+Wire Wire Line
+ 29100 19200 29150 19200
+Wire Wire Line
+ 29150 19200 29150 19350
+Connection ~ 29100 14700
+Wire Wire Line
+ 21150 22350 21150 14750
+Wire Wire Line
+ 21150 14750 20800 14750
+Connection ~ 20800 14700
+Wire Wire Line
+ 32650 13400 32650 18850
+Wire Wire Line
+ 32650 18850 32300 18850
+Connection ~ 32650 13400
+Wire Wire Line
+ 24350 17850 36950 17850
+Connection ~ 24350 11900
+Wire Wire Line
+ 19150 18800 22100 18800
+Wire Wire Line
+ 19150 18800 19150 18900
+Wire Wire Line
+ 19750 18800 19750 16100
+Connection ~ 19750 16100
+Connection ~ 19750 18800
+Wire Wire Line
+ 23200 18800 23600 18800
+Wire Wire Line
+ 23600 18800 23600 15100
+Connection ~ 23600 15100
+Wire Wire Line
+ 27850 13900 27850 18700
+Connection ~ 27850 13900
+Connection ~ 27850 18700
+Wire Wire Line
+ 34100 18600 31150 18600
+Wire Wire Line
+ 31550 12850 31550 18600
+Connection ~ 31550 18600
+Connection ~ 31550 12850
+Wire Wire Line
+ 33850 15650 36450 15650
+Connection ~ 33850 11850
+Wire Wire Line
+ 27300 19350 27000 19350
+Wire Wire Line
+ 26400 19650 26450 19650
+NoConn ~ 26450 18400
+$Comp
+L d_dff U39
+U 1 1 686644FF
+P 30600 18950
+F 0 "U39" H 30600 18950 60 0000 C CNN
+F 1 "d_dff" H 30600 19100 60 0000 C CNN
+F 2 "" H 30600 18950 60 0000 C CNN
+F 3 "" H 30600 18950 60 0000 C CNN
+ 1 30600 18950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 27000 18700 30050 18700
+Wire Wire Line
+ 30050 18700 30050 18600
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B.sub b/library/SubcircuitLibrary/CD4017B/CD4017B.sub
new file mode 100644
index 000000000..aed72980e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4017B/CD4017B.sub
@@ -0,0 +1,234 @@
+* Subcircuit CD4017B
+.subckt CD4017B /5 /1 /0 /2 /6 /7 /3 /8 /4 /9 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_
+* c:\fossee\esim\library\subcircuitlibrary\cd4017b\cd4017b.cir
+* u13 net-_u11-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u13-pad5_ net-_u13-pad6_ d_dff
+* u30 net-_u26-pad3_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u25-pad1_ net-_u30-pad6_ d_dff
+* u47 net-_u29-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u33-pad2_ net-_u47-pad6_ d_dff
+* u3 net-_u1-pad13_ net-_u3-pad2_ d_buffer
+* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter
+* u8 net-_u6-pad2_ net-_u12-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_buffer
+* u14 net-_u1-pad14_ net-_u12-pad2_ net-_u13-pad2_ d_nor
+* u2 net-_u1-pad15_ net-_u2-pad2_ d_buffer
+* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter
+* u5 net-_u4-pad2_ net-_u5-pad2_ d_inverter
+* u7 net-_u5-pad2_ net-_u13-pad4_ d_buffer
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad1_ d_nand
+* u17 net-_u13-pad5_ net-_u17-pad2_ net-_u16-pad1_ d_nand
+* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u19-pad1_ d_nand
+* u25 net-_u25-pad1_ net-_u25-pad2_ net-_u24-pad1_ d_nand
+* u29 net-_u29-pad1_ net-_u11-pad1_ net-_u28-pad1_ d_nand
+* u33 net-_u13-pad5_ net-_u33-pad2_ net-_u32-pad1_ d_nand
+* u36 net-_u11-pad2_ net-_u20-pad1_ net-_u35-pad1_ d_nand
+* u40 net-_u17-pad2_ net-_u25-pad1_ net-_u38-pad1_ d_nand
+* u43 net-_u20-pad2_ net-_u29-pad1_ net-_u42-pad1_ d_nand
+* u46 net-_u25-pad2_ net-_u33-pad2_ net-_u45-pad1_ d_nand
+* u21 net-_u20-pad2_ net-_u11-pad2_ net-_u21-pad3_ d_and
+* u26 net-_u17-pad2_ net-_u21-pad3_ net-_u26-pad3_ d_nor
+* u53 net-_u33-pad2_ net-_u52-pad1_ d_buffer
+* u52 net-_u52-pad1_ net-_u51-pad1_ d_inverter
+* u51 net-_u51-pad1_ net-_u50-pad1_ d_inverter
+* u50 net-_u50-pad1_ net-_u49-pad1_ d_buffer
+* u49 net-_u49-pad1_ net-_u48-pad1_ d_buffer
+* u48 net-_u48-pad1_ net-_u1-pad12_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u9 net-_u10-pad2_ /0 d_buffer
+* u16 net-_u16-pad1_ net-_u15-pad1_ d_inverter
+* u15 net-_u15-pad1_ /1 d_buffer
+* u19 net-_u19-pad1_ net-_u18-pad1_ d_inverter
+* u18 net-_u18-pad1_ /2 d_buffer
+* u24 net-_u24-pad1_ net-_u23-pad1_ d_inverter
+* u23 net-_u23-pad1_ /3 d_buffer
+* u28 net-_u28-pad1_ net-_u27-pad1_ d_inverter
+* u27 net-_u27-pad1_ /4 d_buffer
+* u32 net-_u32-pad1_ net-_u31-pad1_ d_inverter
+* u31 net-_u31-pad1_ /5 d_buffer
+* u35 net-_u35-pad1_ net-_u34-pad1_ d_inverter
+* u34 net-_u34-pad1_ /6 d_buffer
+* u38 net-_u38-pad1_ net-_u37-pad1_ d_inverter
+* u37 net-_u37-pad1_ /7 d_buffer
+* u42 net-_u42-pad1_ net-_u41-pad1_ d_inverter
+* u41 net-_u41-pad1_ /8 d_buffer
+* u45 net-_u45-pad1_ net-_u44-pad1_ d_inverter
+* u44 net-_u44-pad1_ /9 d_buffer
+* u22 net-_u13-pad5_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u20-pad1_ net-_u22-pad6_ d_dff
+* u56 net-_u39-pad6_ net-_u25-pad2_ d_buffer
+* u55 net-_u30-pad6_ net-_u20-pad2_ d_buffer
+* u57 net-_u47-pad6_ net-_u11-pad1_ d_buffer
+* u58 net-_u13-pad6_ net-_u11-pad2_ d_buffer
+* u54 net-_u22-pad6_ net-_u17-pad2_ d_buffer
+* u39 net-_u25-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u29-pad1_ net-_u39-pad6_ d_dff
+a1 net-_u11-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u13-pad5_ net-_u13-pad6_ u13
+a2 net-_u26-pad3_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u25-pad1_ net-_u30-pad6_ u30
+a3 net-_u29-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u33-pad2_ net-_u47-pad6_ u47
+a4 net-_u1-pad13_ net-_u3-pad2_ u3
+a5 net-_u3-pad2_ net-_u6-pad2_ u6
+a6 net-_u6-pad2_ net-_u12-pad1_ u8
+a7 net-_u12-pad1_ net-_u12-pad2_ u12
+a8 [net-_u1-pad14_ net-_u12-pad2_ ] net-_u13-pad2_ u14
+a9 net-_u1-pad15_ net-_u2-pad2_ u2
+a10 net-_u2-pad2_ net-_u4-pad2_ u4
+a11 net-_u4-pad2_ net-_u5-pad2_ u5
+a12 net-_u5-pad2_ net-_u13-pad4_ u7
+a13 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad1_ u11
+a14 [net-_u13-pad5_ net-_u17-pad2_ ] net-_u16-pad1_ u17
+a15 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u19-pad1_ u20
+a16 [net-_u25-pad1_ net-_u25-pad2_ ] net-_u24-pad1_ u25
+a17 [net-_u29-pad1_ net-_u11-pad1_ ] net-_u28-pad1_ u29
+a18 [net-_u13-pad5_ net-_u33-pad2_ ] net-_u32-pad1_ u33
+a19 [net-_u11-pad2_ net-_u20-pad1_ ] net-_u35-pad1_ u36
+a20 [net-_u17-pad2_ net-_u25-pad1_ ] net-_u38-pad1_ u40
+a21 [net-_u20-pad2_ net-_u29-pad1_ ] net-_u42-pad1_ u43
+a22 [net-_u25-pad2_ net-_u33-pad2_ ] net-_u45-pad1_ u46
+a23 [net-_u20-pad2_ net-_u11-pad2_ ] net-_u21-pad3_ u21
+a24 [net-_u17-pad2_ net-_u21-pad3_ ] net-_u26-pad3_ u26
+a25 net-_u33-pad2_ net-_u52-pad1_ u53
+a26 net-_u52-pad1_ net-_u51-pad1_ u52
+a27 net-_u51-pad1_ net-_u50-pad1_ u51
+a28 net-_u50-pad1_ net-_u49-pad1_ u50
+a29 net-_u49-pad1_ net-_u48-pad1_ u49
+a30 net-_u48-pad1_ net-_u1-pad12_ u48
+a31 net-_u10-pad1_ net-_u10-pad2_ u10
+a32 net-_u10-pad2_ /0 u9
+a33 net-_u16-pad1_ net-_u15-pad1_ u16
+a34 net-_u15-pad1_ /1 u15
+a35 net-_u19-pad1_ net-_u18-pad1_ u19
+a36 net-_u18-pad1_ /2 u18
+a37 net-_u24-pad1_ net-_u23-pad1_ u24
+a38 net-_u23-pad1_ /3 u23
+a39 net-_u28-pad1_ net-_u27-pad1_ u28
+a40 net-_u27-pad1_ /4 u27
+a41 net-_u32-pad1_ net-_u31-pad1_ u32
+a42 net-_u31-pad1_ /5 u31
+a43 net-_u35-pad1_ net-_u34-pad1_ u35
+a44 net-_u34-pad1_ /6 u34
+a45 net-_u38-pad1_ net-_u37-pad1_ u38
+a46 net-_u37-pad1_ /7 u37
+a47 net-_u42-pad1_ net-_u41-pad1_ u42
+a48 net-_u41-pad1_ /8 u41
+a49 net-_u45-pad1_ net-_u44-pad1_ u45
+a50 net-_u44-pad1_ /9 u44
+a51 net-_u13-pad5_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u20-pad1_ net-_u22-pad6_ u22
+a52 net-_u39-pad6_ net-_u25-pad2_ u56
+a53 net-_u30-pad6_ net-_u20-pad2_ u55
+a54 net-_u47-pad6_ net-_u11-pad1_ u57
+a55 net-_u13-pad6_ net-_u11-pad2_ u58
+a56 net-_u22-pad6_ net-_u17-pad2_ u54
+a57 net-_u25-pad1_ net-_u13-pad2_ ? net-_u13-pad4_ net-_u29-pad1_ net-_u39-pad6_ u39
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u13 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u47 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u12 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u53 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u50 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u49 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u15 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u23 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u34 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u37 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u41 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u22 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u56 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u55 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u57 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u58 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u54 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u39 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends CD4017B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4017B/CD4017B_Previous_Values.xml b/library/SubcircuitLibrary/CD4017B/CD4017B_Previous_Values.xml
new file mode 100644
index 000000000..3d9e27235
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4017B/CD4017B_Previous_Values.xml
@@ -0,0 +1 @@
+d_dffd_dffd_dffd_dffd_dffd_bufferd_inverterd_inverterd_bufferd_nord_bufferd_inverterd_inverterd_bufferd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_nandd_andd_nord_bufferd_inverterd_inverterd_bufferd_bufferd_inverterd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_inverterd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_bufferd_inverterd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4017B/analysis b/library/SubcircuitLibrary/CD4017B/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4017B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030/CD4030-cache.lib b/library/SubcircuitLibrary/CD4030/CD4030-cache.lib
new file mode 100644
index 000000000..6c512720e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.cir b/library/SubcircuitLibrary/CD4030/CD4030.cir
new file mode 100644
index 000000000..59d9f0115
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.cir
@@ -0,0 +1,55 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4030\CD4030.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 12:06:45
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M3 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M6 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M10-Pad2_ Net-_M11-Pad3_ eSim_MOS_P
+M8 Net-_M8-Pad1_ Net-_M2-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M11 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M9 Net-_M8-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad3_ eSim_MOS_P
+M7 Net-_M10-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M1-Pad3_ eSim_MOS_N
+M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M5 Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ eSim_MOS_N
+M4 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M14 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M17 Net-_M12-Pad1_ Net-_M13-Pad2_ Net-_M16-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M19 Net-_M19-Pad1_ Net-_M13-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M22 Net-_M21-Pad1_ Net-_M16-Pad3_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M20 Net-_M19-Pad1_ Net-_M12-Pad1_ Net-_M16-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M21 Net-_M21-Pad1_ Net-_M16-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M12 Net-_M12-Pad1_ Net-_M12-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M16 Net-_M12-Pad1_ Net-_M13-Pad1_ Net-_M16-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M15 Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M13 Net-_M13-Pad1_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M25 Net-_M23-Pad1_ Net-_M23-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M28 Net-_M23-Pad1_ Net-_M24-Pad2_ Net-_M27-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M30 Net-_M30-Pad1_ Net-_M24-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M33 Net-_M32-Pad1_ Net-_M27-Pad3_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M31 Net-_M30-Pad1_ Net-_M23-Pad1_ Net-_M27-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M29 Net-_M27-Pad3_ Net-_M23-Pad1_ Net-_M24-Pad1_ Net-_M1-Pad3_ eSim_MOS_N
+M32 Net-_M32-Pad1_ Net-_M27-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M23 Net-_M23-Pad1_ Net-_M23-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M27 Net-_M23-Pad1_ Net-_M24-Pad1_ Net-_M27-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M26 Net-_M24-Pad1_ Net-_M24-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M24 Net-_M24-Pad1_ Net-_M24-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M36 Net-_M34-Pad1_ Net-_M34-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M39 Net-_M34-Pad1_ Net-_M35-Pad2_ Net-_M38-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M41 Net-_M41-Pad1_ Net-_M35-Pad1_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M44 Net-_M43-Pad1_ Net-_M38-Pad3_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M42 Net-_M41-Pad1_ Net-_M34-Pad1_ Net-_M38-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M40 Net-_M38-Pad3_ Net-_M34-Pad1_ Net-_M35-Pad1_ Net-_M1-Pad3_ eSim_MOS_N
+M43 Net-_M43-Pad1_ Net-_M38-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M34 Net-_M34-Pad1_ Net-_M34-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M38 Net-_M34-Pad1_ Net-_M35-Pad1_ Net-_M38-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M37 Net-_M35-Pad1_ Net-_M35-Pad2_ Net-_M11-Pad3_ Net-_M11-Pad3_ eSim_MOS_P
+M35 Net-_M35-Pad1_ Net-_M35-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+U1 Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M21-Pad1_ Net-_M12-Pad2_ Net-_M13-Pad2_ Net-_M1-Pad3_ Net-_M24-Pad2_ Net-_M23-Pad2_ Net-_M32-Pad1_ Net-_M43-Pad1_ Net-_M34-Pad2_ Net-_M35-Pad2_ Net-_M11-Pad3_ PORT
+M18 Net-_M16-Pad3_ Net-_M12-Pad1_ Net-_M13-Pad1_ Net-_M1-Pad3_ eSim_MOS_N
+
+.end
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.cir.out b/library/SubcircuitLibrary/CD4030/CD4030.cir.out
new file mode 100644
index 000000000..aa0777a60
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.cir.out
@@ -0,0 +1,58 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4030\cd4030.cir
+
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m8 net-_m8-pad1_ net-_m2-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m11 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m9 net-_m8-pad1_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m7 net-_m10-pad2_ net-_m1-pad1_ net-_m2-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m4 net-_m2-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m14 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m17 net-_m12-pad1_ net-_m13-pad2_ net-_m16-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m13-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m22 net-_m21-pad1_ net-_m16-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m20 net-_m19-pad1_ net-_m12-pad1_ net-_m16-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m21 net-_m21-pad1_ net-_m16-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m12 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m16 net-_m12-pad1_ net-_m13-pad1_ net-_m16-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m15 net-_m13-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m25 net-_m23-pad1_ net-_m23-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m28 net-_m23-pad1_ net-_m24-pad2_ net-_m27-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m30 net-_m30-pad1_ net-_m24-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m33 net-_m32-pad1_ net-_m27-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m31 net-_m30-pad1_ net-_m23-pad1_ net-_m27-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m29 net-_m27-pad3_ net-_m23-pad1_ net-_m24-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m32 net-_m32-pad1_ net-_m27-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m23 net-_m23-pad1_ net-_m23-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m27 net-_m23-pad1_ net-_m24-pad1_ net-_m27-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m26 net-_m24-pad1_ net-_m24-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m24 net-_m24-pad1_ net-_m24-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m36 net-_m34-pad1_ net-_m34-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m39 net-_m34-pad1_ net-_m35-pad2_ net-_m38-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m41 net-_m41-pad1_ net-_m35-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m44 net-_m43-pad1_ net-_m38-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m42 net-_m41-pad1_ net-_m34-pad1_ net-_m38-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m40 net-_m38-pad3_ net-_m34-pad1_ net-_m35-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m43 net-_m43-pad1_ net-_m38-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m34 net-_m34-pad1_ net-_m34-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m38 net-_m34-pad1_ net-_m35-pad1_ net-_m38-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m37 net-_m35-pad1_ net-_m35-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m35 net-_m35-pad1_ net-_m35-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+* u1 net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m21-pad1_ net-_m12-pad2_ net-_m13-pad2_ net-_m1-pad3_ net-_m24-pad2_ net-_m23-pad2_ net-_m32-pad1_ net-_m43-pad1_ net-_m34-pad2_ net-_m35-pad2_ net-_m11-pad3_ port
+m18 net-_m16-pad3_ net-_m12-pad1_ net-_m13-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.pro b/library/SubcircuitLibrary/CD4030/CD4030.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.proj b/library/SubcircuitLibrary/CD4030/CD4030.proj
new file mode 100644
index 000000000..9d102c1a3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.proj
@@ -0,0 +1 @@
+schematicFile CD4030.sch
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.sch b/library/SubcircuitLibrary/CD4030/CD4030.sch
new file mode 100644
index 000000000..308f59cce
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.sch
@@ -0,0 +1,1381 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4030-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M3
+U 1 1 6836E298
+P -8100 750
+F 0 "M3" H -8150 800 50 0000 R CNN
+F 1 "eSim_MOS_P" H -8050 900 50 0000 R CNN
+F 2 "" H -7850 850 29 0000 C CNN
+F 3 "" H -8050 750 60 0000 C CNN
+ 1 -8100 750
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M6
+U 1 1 6836E2E0
+P -6200 1700
+F 0 "M6" H -6250 1750 50 0000 R CNN
+F 1 "eSim_MOS_P" H -6150 1850 50 0000 R CNN
+F 2 "" H -5950 1800 29 0000 C CNN
+F 3 "" H -6150 1700 60 0000 C CNN
+ 1 -6200 1700
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M8
+U 1 1 6836E2FA
+P -5350 700
+F 0 "M8" H -5400 750 50 0000 R CNN
+F 1 "eSim_MOS_P" H -5300 850 50 0000 R CNN
+F 2 "" H -5100 800 29 0000 C CNN
+F 3 "" H -5300 700 60 0000 C CNN
+ 1 -5350 700
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M11
+U 1 1 6836E319
+P -4400 1150
+F 0 "M11" H -4450 1200 50 0000 R CNN
+F 1 "eSim_MOS_P" H -4350 1300 50 0000 R CNN
+F 2 "" H -4150 1250 29 0000 C CNN
+F 3 "" H -4350 1150 60 0000 C CNN
+ 1 -4400 1150
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M9
+U 1 1 6836E345
+P -5350 1350
+F 0 "M9" H -5400 1400 50 0000 R CNN
+F 1 "eSim_MOS_P" H -5300 1500 50 0000 R CNN
+F 2 "" H -5100 1450 29 0000 C CNN
+F 3 "" H -5300 1350 60 0000 C CNN
+ 1 -5350 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M7
+U 1 1 6836E367
+P -5400 1750
+F 0 "M7" H -5400 1600 50 0000 R CNN
+F 1 "eSim_MOS_N" H -5300 1700 50 0000 R CNN
+F 2 "" H -5100 1450 29 0000 C CNN
+F 3 "" H -5300 1550 60 0000 C CNN
+ 1 -5400 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 6836E3A0
+P -4450 1650
+F 0 "M10" H -4450 1500 50 0000 R CNN
+F 1 "eSim_MOS_N" H -4350 1600 50 0000 R CNN
+F 2 "" H -4150 1350 29 0000 C CNN
+F 3 "" H -4350 1450 60 0000 C CNN
+ 1 -4450 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M1
+U 1 1 6836E3CB
+P -8150 1200
+F 0 "M1" H -8150 1050 50 0000 R CNN
+F 1 "eSim_MOS_N" H -8050 1150 50 0000 R CNN
+F 2 "" H -7850 900 29 0000 C CNN
+F 3 "" H -8050 1000 60 0000 C CNN
+ 1 -8150 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 6836E3FD
+P -7000 1500
+F 0 "M5" H -7000 1350 50 0000 R CNN
+F 1 "eSim_MOS_N" H -6900 1450 50 0000 R CNN
+F 2 "" H -6700 1200 29 0000 C CNN
+F 3 "" H -6900 1300 60 0000 C CNN
+ 1 -7000 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 6836EAA8
+P -8100 2700
+F 0 "M4" H -8150 2750 50 0000 R CNN
+F 1 "eSim_MOS_P" H -8050 2850 50 0000 R CNN
+F 2 "" H -7850 2800 29 0000 C CNN
+F 3 "" H -8050 2700 60 0000 C CNN
+ 1 -8100 2700
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 6836EAAE
+P -8150 3150
+F 0 "M2" H -8150 3000 50 0000 R CNN
+F 1 "eSim_MOS_N" H -8050 3100 50 0000 R CNN
+F 2 "" H -7850 2850 29 0000 C CNN
+F 3 "" H -8050 2950 60 0000 C CNN
+ 1 -8150 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M14
+U 1 1 68374D4A
+P -3000 700
+F 0 "M14" H -3050 750 50 0000 R CNN
+F 1 "eSim_MOS_P" H -2950 850 50 0000 R CNN
+F 2 "" H -2750 800 29 0000 C CNN
+F 3 "" H -2950 700 60 0000 C CNN
+ 1 -3000 700
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M17
+U 1 1 68374D50
+P -1100 1650
+F 0 "M17" H -1150 1700 50 0000 R CNN
+F 1 "eSim_MOS_P" H -1050 1800 50 0000 R CNN
+F 2 "" H -850 1750 29 0000 C CNN
+F 3 "" H -1050 1650 60 0000 C CNN
+ 1 -1100 1650
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M19
+U 1 1 68374D56
+P -100 650
+F 0 "M19" H -150 700 50 0000 R CNN
+F 1 "eSim_MOS_P" H -50 800 50 0000 R CNN
+F 2 "" H 150 750 29 0000 C CNN
+F 3 "" H -50 650 60 0000 C CNN
+ 1 -100 650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M22
+U 1 1 68374D5C
+P 700 1100
+F 0 "M22" H 650 1150 50 0000 R CNN
+F 1 "eSim_MOS_P" H 750 1250 50 0000 R CNN
+F 2 "" H 950 1200 29 0000 C CNN
+F 3 "" H 750 1100 60 0000 C CNN
+ 1 700 1100
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M20
+U 1 1 68374D62
+P -50 1300
+F 0 "M20" H -100 1350 50 0000 R CNN
+F 1 "eSim_MOS_P" H 0 1450 50 0000 R CNN
+F 2 "" H 200 1400 29 0000 C CNN
+F 3 "" H 0 1300 60 0000 C CNN
+ 1 -50 1300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M21
+U 1 1 68374D6E
+P 650 1600
+F 0 "M21" H 650 1450 50 0000 R CNN
+F 1 "eSim_MOS_N" H 750 1550 50 0000 R CNN
+F 2 "" H 950 1300 29 0000 C CNN
+F 3 "" H 750 1400 60 0000 C CNN
+ 1 650 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M12
+U 1 1 68374D74
+P -3050 1150
+F 0 "M12" H -3050 1000 50 0000 R CNN
+F 1 "eSim_MOS_N" H -2950 1100 50 0000 R CNN
+F 2 "" H -2750 850 29 0000 C CNN
+F 3 "" H -2950 950 60 0000 C CNN
+ 1 -3050 1150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M16
+U 1 1 68374D7A
+P -1900 1450
+F 0 "M16" H -1900 1300 50 0000 R CNN
+F 1 "eSim_MOS_N" H -1800 1400 50 0000 R CNN
+F 2 "" H -1600 1150 29 0000 C CNN
+F 3 "" H -1800 1250 60 0000 C CNN
+ 1 -1900 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M15
+U 1 1 68374D8C
+P -3000 2650
+F 0 "M15" H -3050 2700 50 0000 R CNN
+F 1 "eSim_MOS_P" H -2950 2800 50 0000 R CNN
+F 2 "" H -2750 2750 29 0000 C CNN
+F 3 "" H -2950 2650 60 0000 C CNN
+ 1 -3000 2650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M13
+U 1 1 68374D92
+P -3050 3100
+F 0 "M13" H -3050 2950 50 0000 R CNN
+F 1 "eSim_MOS_N" H -2950 3050 50 0000 R CNN
+F 2 "" H -2750 2800 29 0000 C CNN
+F 3 "" H -2950 2900 60 0000 C CNN
+ 1 -3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M25
+U 1 1 68378186
+P 2450 750
+F 0 "M25" H 2400 800 50 0000 R CNN
+F 1 "eSim_MOS_P" H 2500 900 50 0000 R CNN
+F 2 "" H 2700 850 29 0000 C CNN
+F 3 "" H 2500 750 60 0000 C CNN
+ 1 2450 750
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M28
+U 1 1 6837818C
+P 4350 1700
+F 0 "M28" H 4300 1750 50 0000 R CNN
+F 1 "eSim_MOS_P" H 4400 1850 50 0000 R CNN
+F 2 "" H 4600 1800 29 0000 C CNN
+F 3 "" H 4400 1700 60 0000 C CNN
+ 1 4350 1700
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M30
+U 1 1 68378192
+P 5200 700
+F 0 "M30" H 5150 750 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5250 850 50 0000 R CNN
+F 2 "" H 5450 800 29 0000 C CNN
+F 3 "" H 5250 700 60 0000 C CNN
+ 1 5200 700
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M33
+U 1 1 68378198
+P 6150 1150
+F 0 "M33" H 6100 1200 50 0000 R CNN
+F 1 "eSim_MOS_P" H 6200 1300 50 0000 R CNN
+F 2 "" H 6400 1250 29 0000 C CNN
+F 3 "" H 6200 1150 60 0000 C CNN
+ 1 6150 1150
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M31
+U 1 1 6837819E
+P 5200 1350
+F 0 "M31" H 5150 1400 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5250 1500 50 0000 R CNN
+F 2 "" H 5450 1450 29 0000 C CNN
+F 3 "" H 5250 1350 60 0000 C CNN
+ 1 5200 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M29
+U 1 1 683781A4
+P 5150 1750
+F 0 "M29" H 5150 1600 50 0000 R CNN
+F 1 "eSim_MOS_N" H 5250 1700 50 0000 R CNN
+F 2 "" H 5450 1450 29 0000 C CNN
+F 3 "" H 5250 1550 60 0000 C CNN
+ 1 5150 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M32
+U 1 1 683781AA
+P 6100 1650
+F 0 "M32" H 6100 1500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6200 1600 50 0000 R CNN
+F 2 "" H 6400 1350 29 0000 C CNN
+F 3 "" H 6200 1450 60 0000 C CNN
+ 1 6100 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M23
+U 1 1 683781B0
+P 2400 1200
+F 0 "M23" H 2400 1050 50 0000 R CNN
+F 1 "eSim_MOS_N" H 2500 1150 50 0000 R CNN
+F 2 "" H 2700 900 29 0000 C CNN
+F 3 "" H 2500 1000 60 0000 C CNN
+ 1 2400 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M27
+U 1 1 683781B6
+P 3550 1500
+F 0 "M27" H 3550 1350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 3650 1450 50 0000 R CNN
+F 2 "" H 3850 1200 29 0000 C CNN
+F 3 "" H 3650 1300 60 0000 C CNN
+ 1 3550 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M26
+U 1 1 683781C8
+P 2450 2700
+F 0 "M26" H 2400 2750 50 0000 R CNN
+F 1 "eSim_MOS_P" H 2500 2850 50 0000 R CNN
+F 2 "" H 2700 2800 29 0000 C CNN
+F 3 "" H 2500 2700 60 0000 C CNN
+ 1 2450 2700
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M24
+U 1 1 683781CE
+P 2400 3150
+F 0 "M24" H 2400 3000 50 0000 R CNN
+F 1 "eSim_MOS_N" H 2500 3100 50 0000 R CNN
+F 2 "" H 2700 2850 29 0000 C CNN
+F 3 "" H 2500 2950 60 0000 C CNN
+ 1 2400 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M36
+U 1 1 68389404
+P 7700 700
+F 0 "M36" H 7650 750 50 0000 R CNN
+F 1 "eSim_MOS_P" H 7750 850 50 0000 R CNN
+F 2 "" H 7950 800 29 0000 C CNN
+F 3 "" H 7750 700 60 0000 C CNN
+ 1 7700 700
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M39
+U 1 1 6838940A
+P 9600 1650
+F 0 "M39" H 9550 1700 50 0000 R CNN
+F 1 "eSim_MOS_P" H 9650 1800 50 0000 R CNN
+F 2 "" H 9850 1750 29 0000 C CNN
+F 3 "" H 9650 1650 60 0000 C CNN
+ 1 9600 1650
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M41
+U 1 1 68389410
+P 10450 650
+F 0 "M41" H 10400 700 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10500 800 50 0000 R CNN
+F 2 "" H 10700 750 29 0000 C CNN
+F 3 "" H 10500 650 60 0000 C CNN
+ 1 10450 650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M44
+U 1 1 68389416
+P 11400 1100
+F 0 "M44" H 11350 1150 50 0000 R CNN
+F 1 "eSim_MOS_P" H 11450 1250 50 0000 R CNN
+F 2 "" H 11650 1200 29 0000 C CNN
+F 3 "" H 11450 1100 60 0000 C CNN
+ 1 11400 1100
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M42
+U 1 1 6838941C
+P 10450 1300
+F 0 "M42" H 10400 1350 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10500 1450 50 0000 R CNN
+F 2 "" H 10700 1400 29 0000 C CNN
+F 3 "" H 10500 1300 60 0000 C CNN
+ 1 10450 1300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M40
+U 1 1 68389422
+P 10400 1700
+F 0 "M40" H 10400 1550 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10500 1650 50 0000 R CNN
+F 2 "" H 10700 1400 29 0000 C CNN
+F 3 "" H 10500 1500 60 0000 C CNN
+ 1 10400 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M43
+U 1 1 68389428
+P 11350 1600
+F 0 "M43" H 11350 1450 50 0000 R CNN
+F 1 "eSim_MOS_N" H 11450 1550 50 0000 R CNN
+F 2 "" H 11650 1300 29 0000 C CNN
+F 3 "" H 11450 1400 60 0000 C CNN
+ 1 11350 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M34
+U 1 1 6838942E
+P 7650 1150
+F 0 "M34" H 7650 1000 50 0000 R CNN
+F 1 "eSim_MOS_N" H 7750 1100 50 0000 R CNN
+F 2 "" H 7950 850 29 0000 C CNN
+F 3 "" H 7750 950 60 0000 C CNN
+ 1 7650 1150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M38
+U 1 1 68389434
+P 8800 1450
+F 0 "M38" H 8800 1300 50 0000 R CNN
+F 1 "eSim_MOS_N" H 8900 1400 50 0000 R CNN
+F 2 "" H 9100 1150 29 0000 C CNN
+F 3 "" H 8900 1250 60 0000 C CNN
+ 1 8800 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M37
+U 1 1 68389446
+P 7700 2650
+F 0 "M37" H 7650 2700 50 0000 R CNN
+F 1 "eSim_MOS_P" H 7750 2800 50 0000 R CNN
+F 2 "" H 7950 2750 29 0000 C CNN
+F 3 "" H 7750 2650 60 0000 C CNN
+ 1 7700 2650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M35
+U 1 1 6838944C
+P 7650 3100
+F 0 "M35" H 7650 2950 50 0000 R CNN
+F 1 "eSim_MOS_N" H 7750 3050 50 0000 R CNN
+F 2 "" H 7950 2800 29 0000 C CNN
+F 3 "" H 7750 2900 60 0000 C CNN
+ 1 7650 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6839C484
+P -8950 1100
+F 0 "U1" H -8900 1200 30 0000 C CNN
+F 1 "PORT" H -8950 1100 30 0000 C CNN
+F 2 "" H -8950 1100 60 0000 C CNN
+F 3 "" H -8950 1100 60 0000 C CNN
+ 2 -8950 1100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6839D631
+P -9100 3050
+F 0 "U1" H -9050 3150 30 0000 C CNN
+F 1 "PORT" H -9100 3050 30 0000 C CNN
+F 2 "" H -9100 3050 60 0000 C CNN
+F 3 "" H -9100 3050 60 0000 C CNN
+ 1 -9100 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6839EB6F
+P -3700 1000
+F 0 "U1" H -3650 1100 30 0000 C CNN
+F 1 "PORT" H -3700 1000 30 0000 C CNN
+F 2 "" H -3700 1000 60 0000 C CNN
+F 3 "" H -3700 1000 60 0000 C CNN
+ 5 -3700 1000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 683A27F1
+P -3750 3000
+F 0 "U1" H -3700 3100 30 0000 C CNN
+F 1 "PORT" H -3750 3000 30 0000 C CNN
+F 2 "" H -3750 3000 60 0000 C CNN
+F 3 "" H -3750 3000 60 0000 C CNN
+ 6 -3750 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 683A552B
+P -8450 4000
+F 0 "U1" H -8400 4100 30 0000 C CNN
+F 1 "PORT" H -8450 4000 30 0000 C CNN
+F 2 "" H -8450 4000 60 0000 C CNN
+F 3 "" H -8450 4000 60 0000 C CNN
+ 7 -8450 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 683B72DB
+P 1450 3050
+F 0 "U1" H 1500 3150 30 0000 C CNN
+F 1 "PORT" H 1450 3050 30 0000 C CNN
+F 2 "" H 1450 3050 60 0000 C CNN
+F 3 "" H 1450 3050 60 0000 C CNN
+ 8 1450 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 683B90D4
+P 1600 1100
+F 0 "U1" H 1650 1200 30 0000 C CNN
+F 1 "PORT" H 1600 1100 30 0000 C CNN
+F 2 "" H 1600 1100 60 0000 C CNN
+F 3 "" H 1600 1100 60 0000 C CNN
+ 9 1600 1100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 683BA364
+P 6800 1450
+F 0 "U1" H 6850 1550 30 0000 C CNN
+F 1 "PORT" H 6800 1450 30 0000 C CNN
+F 2 "" H 6800 1450 60 0000 C CNN
+F 3 "" H 6800 1450 60 0000 C CNN
+ 10 6800 1450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 683BB3CC
+P 12000 1450
+F 0 "U1" H 12050 1550 30 0000 C CNN
+F 1 "PORT" H 12000 1450 30 0000 C CNN
+F 2 "" H 12000 1450 60 0000 C CNN
+F 3 "" H 12000 1450 60 0000 C CNN
+ 11 12000 1450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 683BCBE1
+P -7800 -350
+F 0 "U1" H -7750 -250 30 0000 C CNN
+F 1 "PORT" H -7800 -350 30 0000 C CNN
+F 2 "" H -7800 -350 60 0000 C CNN
+F 3 "" H -7800 -350 60 0000 C CNN
+ 14 -7800 -350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 683BDE13
+P 6850 2950
+F 0 "U1" H 6900 3050 30 0000 C CNN
+F 1 "PORT" H 6850 2950 30 0000 C CNN
+F 2 "" H 6850 2950 60 0000 C CNN
+F 3 "" H 6850 2950 60 0000 C CNN
+ 13 6850 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 683BF62B
+P 6900 1050
+F 0 "U1" H 6950 1150 30 0000 C CNN
+F 1 "PORT" H 6900 1050 30 0000 C CNN
+F 2 "" H 6900 1050 60 0000 C CNN
+F 3 "" H 6900 1050 60 0000 C CNN
+ 12 6900 1050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 683E5A89
+P -3850 1500
+F 0 "U1" H -3800 1600 30 0000 C CNN
+F 1 "PORT" H -3850 1500 30 0000 C CNN
+F 2 "" H -3850 1500 60 0000 C CNN
+F 3 "" H -3850 1500 60 0000 C CNN
+ 3 -3850 1500
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 683E70F9
+P 1300 1450
+F 0 "U1" H 1350 1550 30 0000 C CNN
+F 1 "PORT" H 1300 1450 30 0000 C CNN
+F 2 "" H 1300 1450 60 0000 C CNN
+F 3 "" H 1300 1450 60 0000 C CNN
+ 4 1300 1450
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ -7950 550 -7850 550
+Wire Wire Line
+ -7850 550 -7850 600
+Wire Wire Line
+ -7950 950 -7950 1200
+Connection ~ -7900 550
+Wire Wire Line
+ -7950 1600 -7850 1600
+Wire Wire Line
+ -7850 1600 -7850 1550
+Wire Wire Line
+ -7900 1600 -7900 1700
+Connection ~ -7900 1600
+Wire Wire Line
+ -8250 750 -8250 1400
+Wire Wire Line
+ -7950 2500 -7850 2500
+Wire Wire Line
+ -7850 2500 -7850 2550
+Wire Wire Line
+ -7950 2900 -7950 3150
+Connection ~ -7900 2500
+Wire Wire Line
+ -7950 3550 -7850 3550
+Wire Wire Line
+ -7850 3550 -7850 3500
+Wire Wire Line
+ -8250 2700 -8250 3350
+Wire Wire Line
+ -6800 1500 -6350 1500
+Wire Wire Line
+ -6800 1900 -6350 1900
+Wire Wire Line
+ -6700 1850 -6700 3850
+Wire Wire Line
+ -6450 1850 -6450 350
+Wire Wire Line
+ -6600 1500 -6600 1050
+Wire Wire Line
+ -7950 1050 -5950 1050
+Connection ~ -7950 1050
+Connection ~ -6600 1500
+Wire Wire Line
+ -7950 3050 -5200 3050
+Wire Wire Line
+ -7100 3050 -7100 1700
+Connection ~ -7950 3050
+Wire Wire Line
+ -5200 500 -5000 500
+Wire Wire Line
+ -5100 500 -5100 550
+Wire Wire Line
+ -6450 350 -7900 350
+Connection ~ -7900 350
+Wire Wire Line
+ -5150 500 -5150 100
+Wire Wire Line
+ -7900 100 -2800 100
+Connection ~ -7900 100
+Connection ~ -5150 500
+Wire Wire Line
+ -5500 700 -5850 700
+Wire Wire Line
+ -5850 700 -5850 3050
+Connection ~ -7100 3050
+Wire Wire Line
+ -5200 900 -5200 1150
+Connection ~ -7900 3550
+Wire Wire Line
+ -2800 3850 -7900 3850
+Connection ~ -7900 3850
+Wire Wire Line
+ -5200 1550 -5200 1750
+Wire Wire Line
+ -5500 1350 -5500 1950
+Wire Wire Line
+ -5500 1650 -5950 1650
+Wire Wire Line
+ -5950 1650 -5950 1050
+Connection ~ -6600 1050
+Connection ~ -5500 1650
+Wire Wire Line
+ -5100 3850 -5100 2100
+Connection ~ -6700 3850
+Wire Wire Line
+ -5200 3050 -5200 2150
+Connection ~ -5850 3050
+Wire Wire Line
+ -4250 950 -4150 950
+Wire Wire Line
+ -4150 950 -4150 1000
+Wire Wire Line
+ -4200 100 -4200 950
+Connection ~ -4200 950
+Connection ~ -5150 100
+Wire Wire Line
+ -4550 1150 -4550 1850
+Wire Wire Line
+ -5200 1650 -4550 1650
+Wire Wire Line
+ -4550 1650 -4550 1550
+Connection ~ -4550 1550
+Connection ~ -5200 1650
+Wire Wire Line
+ -4250 2050 -4150 2050
+Wire Wire Line
+ -4150 2050 -4150 2000
+Wire Wire Line
+ -4200 3850 -4200 2050
+Connection ~ -4200 2050
+Connection ~ -5100 3850
+Wire Wire Line
+ -4250 1350 -4250 1650
+Wire Wire Line
+ -2850 500 -2750 500
+Wire Wire Line
+ -2750 500 -2750 550
+Wire Wire Line
+ -2850 900 -2850 1150
+Connection ~ -2800 500
+Wire Wire Line
+ -2850 1550 -2750 1550
+Wire Wire Line
+ -2750 1550 -2750 1500
+Wire Wire Line
+ -2800 1550 -2800 1800
+Connection ~ -2800 1550
+Wire Wire Line
+ -3150 700 -3150 1350
+Wire Wire Line
+ -2850 2450 -2750 2450
+Wire Wire Line
+ -2750 2450 -2750 2500
+Wire Wire Line
+ -2850 2850 -2850 3100
+Connection ~ -2800 2450
+Wire Wire Line
+ -2850 3500 -2750 3500
+Wire Wire Line
+ -2750 3500 -2750 3450
+Wire Wire Line
+ -3150 2650 -3150 3300
+Wire Wire Line
+ -1700 1450 -1250 1450
+Wire Wire Line
+ -1700 1850 -1250 1850
+Wire Wire Line
+ -1600 1800 -1600 3800
+Wire Wire Line
+ -1500 1450 -1500 1000
+Wire Wire Line
+ -2850 1000 -850 1000
+Connection ~ -2850 1000
+Connection ~ -1500 1450
+Wire Wire Line
+ -2850 3000 50 3000
+Wire Wire Line
+ -2000 3000 -2000 1650
+Connection ~ -2850 3000
+Wire Wire Line
+ -1350 300 -2800 300
+Connection ~ -2800 300
+Wire Wire Line
+ -2800 50 2650 50
+Wire Wire Line
+ -750 650 -250 650
+Wire Wire Line
+ -750 3000 -750 650
+Connection ~ -2000 3000
+Wire Wire Line
+ -100 850 -100 1100
+Connection ~ -2800 3500
+Wire Wire Line
+ -2800 3800 2650 3800
+Connection ~ -2800 3800
+Wire Wire Line
+ -100 1500 -100 1700
+Wire Wire Line
+ -400 1300 -400 1900
+Wire Wire Line
+ -400 1600 -850 1600
+Wire Wire Line
+ -850 1600 -850 1000
+Connection ~ -1500 1000
+Connection ~ -400 1600
+Wire Wire Line
+ 0 3800 0 2050
+Connection ~ -1600 3800
+Wire Wire Line
+ 850 900 950 900
+Wire Wire Line
+ 950 900 950 950
+Wire Wire Line
+ 900 50 900 900
+Connection ~ 900 900
+Wire Wire Line
+ 550 1100 550 1800
+Wire Wire Line
+ -100 1600 550 1600
+Wire Wire Line
+ 550 1600 550 1500
+Connection ~ 550 1500
+Connection ~ -100 1600
+Wire Wire Line
+ 850 2000 950 2000
+Wire Wire Line
+ 950 2000 950 1950
+Wire Wire Line
+ 900 3800 900 2000
+Connection ~ 900 2000
+Connection ~ 0 3800
+Wire Wire Line
+ 850 1300 850 1600
+Wire Wire Line
+ 2600 550 2700 550
+Wire Wire Line
+ 2700 550 2700 600
+Wire Wire Line
+ 2600 950 2600 1200
+Connection ~ 2650 550
+Wire Wire Line
+ 2600 1600 2700 1600
+Wire Wire Line
+ 2700 1600 2700 1550
+Wire Wire Line
+ 2650 1600 2650 1700
+Connection ~ 2650 1600
+Wire Wire Line
+ 2300 750 2300 1400
+Wire Wire Line
+ 2600 2500 2700 2500
+Wire Wire Line
+ 2700 2500 2700 2550
+Wire Wire Line
+ 2600 2900 2600 3150
+Connection ~ 2650 2500
+Wire Wire Line
+ 2600 3550 2700 3550
+Wire Wire Line
+ 2700 3550 2700 3500
+Wire Wire Line
+ 2300 2700 2300 3350
+Wire Wire Line
+ 3750 1500 4200 1500
+Wire Wire Line
+ 3750 1900 4200 1900
+Wire Wire Line
+ 3850 1850 3850 3850
+Wire Wire Line
+ 4100 1850 4100 350
+Wire Wire Line
+ 3950 1500 3950 1050
+Wire Wire Line
+ 2600 1050 4600 1050
+Connection ~ 2600 1050
+Connection ~ 3950 1500
+Wire Wire Line
+ 2600 3050 5350 3050
+Wire Wire Line
+ 3450 3050 3450 1700
+Connection ~ 2600 3050
+Wire Wire Line
+ 5350 500 5650 500
+Wire Wire Line
+ 5450 500 5450 550
+Wire Wire Line
+ 4100 350 2650 350
+Connection ~ 2650 350
+Wire Wire Line
+ 5400 100 5400 500
+Wire Wire Line
+ 2650 100 7900 100
+Connection ~ 5400 500
+Wire Wire Line
+ 5050 700 4700 700
+Wire Wire Line
+ 4700 700 4700 3050
+Connection ~ 3450 3050
+Wire Wire Line
+ 5350 900 5350 1150
+Connection ~ 2650 3550
+Wire Wire Line
+ 7900 3850 2650 3850
+Wire Wire Line
+ 5350 1550 5350 1750
+Wire Wire Line
+ 5050 1350 5050 1950
+Wire Wire Line
+ 5050 1650 4600 1650
+Wire Wire Line
+ 4600 1650 4600 1050
+Connection ~ 3950 1050
+Connection ~ 5050 1650
+Wire Wire Line
+ 5450 3850 5450 2100
+Connection ~ 3850 3850
+Wire Wire Line
+ 5350 3050 5350 2150
+Connection ~ 4700 3050
+Wire Wire Line
+ 6300 950 6400 950
+Wire Wire Line
+ 6400 950 6400 1000
+Wire Wire Line
+ 6350 100 6350 950
+Connection ~ 6350 950
+Connection ~ 5400 100
+Wire Wire Line
+ 6000 1150 6000 1850
+Wire Wire Line
+ 5350 1650 6000 1650
+Wire Wire Line
+ 6000 1650 6000 1550
+Connection ~ 6000 1550
+Connection ~ 5350 1650
+Wire Wire Line
+ 6300 2050 6400 2050
+Wire Wire Line
+ 6400 2050 6400 2000
+Wire Wire Line
+ 6350 3850 6350 2050
+Connection ~ 6350 2050
+Connection ~ 5450 3850
+Wire Wire Line
+ 6300 1350 6300 1650
+Wire Wire Line
+ -2800 2450 -2800 2000
+Wire Wire Line
+ -2800 2000 -2400 2000
+Wire Wire Line
+ -2400 2000 -2400 50
+Connection ~ -2400 50
+Wire Wire Line
+ 7850 500 7950 500
+Wire Wire Line
+ 7950 500 7950 550
+Wire Wire Line
+ 7850 900 7850 1150
+Connection ~ 7900 500
+Wire Wire Line
+ 7850 1550 7950 1550
+Wire Wire Line
+ 7950 1550 7950 1500
+Wire Wire Line
+ 7900 1550 7900 1650
+Connection ~ 7900 1550
+Wire Wire Line
+ 7550 700 7550 1350
+Wire Wire Line
+ 7850 2450 7950 2450
+Wire Wire Line
+ 7950 2450 7950 2500
+Wire Wire Line
+ 7850 2850 7850 3100
+Connection ~ 7900 2450
+Wire Wire Line
+ 7850 3500 7950 3500
+Wire Wire Line
+ 7950 3500 7950 3450
+Wire Wire Line
+ 7550 2650 7550 3300
+Wire Wire Line
+ 9000 1450 9450 1450
+Wire Wire Line
+ 9000 1850 9450 1850
+Wire Wire Line
+ 9100 1800 9100 3800
+Wire Wire Line
+ 9350 1800 9350 300
+Wire Wire Line
+ 9200 1450 9200 1000
+Wire Wire Line
+ 7850 1000 9850 1000
+Connection ~ 7850 1000
+Connection ~ 9200 1450
+Wire Wire Line
+ 7850 3000 10600 3000
+Wire Wire Line
+ 8700 3000 8700 1650
+Connection ~ 7850 3000
+Wire Wire Line
+ 10600 450 10850 450
+Wire Wire Line
+ 10700 450 10700 500
+Wire Wire Line
+ 9350 300 7900 300
+Connection ~ 7900 300
+Wire Wire Line
+ 10650 50 10650 450
+Wire Wire Line
+ 7900 50 11600 50
+Connection ~ 10650 450
+Wire Wire Line
+ 10300 650 9950 650
+Wire Wire Line
+ 9950 650 9950 3000
+Connection ~ 8700 3000
+Wire Wire Line
+ 10600 850 10600 1100
+Connection ~ 7900 3500
+Wire Wire Line
+ 7900 3800 11600 3800
+Connection ~ 7900 3800
+Wire Wire Line
+ 10600 1500 10600 1700
+Wire Wire Line
+ 10300 1300 10300 1900
+Wire Wire Line
+ 10300 1600 9850 1600
+Wire Wire Line
+ 9850 1600 9850 1000
+Connection ~ 9200 1000
+Connection ~ 10300 1600
+Wire Wire Line
+ 10700 3800 10700 2050
+Connection ~ 9100 3800
+Wire Wire Line
+ 10600 3000 10600 2100
+Connection ~ 9950 3000
+Wire Wire Line
+ 11550 900 11650 900
+Wire Wire Line
+ 11650 900 11650 950
+Wire Wire Line
+ 11600 50 11600 900
+Connection ~ 11600 900
+Connection ~ 10650 50
+Wire Wire Line
+ 11250 1100 11250 1800
+Wire Wire Line
+ 10600 1600 11250 1600
+Wire Wire Line
+ 11250 1600 11250 1500
+Connection ~ 11250 1500
+Connection ~ 10600 1600
+Wire Wire Line
+ 11550 2000 11650 2000
+Wire Wire Line
+ 11650 2000 11650 1950
+Wire Wire Line
+ 11600 3800 11600 2000
+Connection ~ 11600 2000
+Connection ~ 10700 3800
+Wire Wire Line
+ 11550 1300 11550 1600
+Wire Wire Line
+ 2650 50 2650 100
+Connection ~ 900 50
+Wire Wire Line
+ 7900 100 7900 50
+Connection ~ 6350 100
+Connection ~ 6350 3850
+Wire Wire Line
+ 2650 3850 2650 3550
+Connection ~ 900 3800
+Wire Wire Line
+ -2800 3500 -2800 3850
+Connection ~ -4200 3850
+Wire Wire Line
+ 2650 2500 2650 2100
+Wire Wire Line
+ 2650 2100 3100 2100
+Wire Wire Line
+ 3100 2100 3100 100
+Connection ~ 3100 100
+Wire Wire Line
+ 7900 2450 7900 1950
+Wire Wire Line
+ 7900 1950 8200 1950
+Wire Wire Line
+ 8200 1950 8200 50
+Connection ~ 8200 50
+Wire Wire Line
+ -2800 100 -2800 50
+Connection ~ -4200 100
+Connection ~ -8250 1100
+Connection ~ -8250 3050
+Wire Wire Line
+ -4250 1500 -4100 1500
+Connection ~ -4250 1500
+Wire Wire Line
+ -8850 3050 -8250 3050
+Wire Wire Line
+ -3450 1000 -3150 1000
+Connection ~ -3150 1000
+Wire Wire Line
+ -3500 3000 -3150 3000
+Connection ~ -3150 3000
+Wire Wire Line
+ -6050 1700 -6050 2050
+Wire Wire Line
+ -6050 2050 -8500 2050
+Wire Wire Line
+ -8500 2050 -8500 3050
+Connection ~ -8500 3050
+Wire Wire Line
+ -950 1650 -950 2150
+Wire Wire Line
+ -950 2150 -3300 2150
+Wire Wire Line
+ -3300 2150 -3300 3000
+Connection ~ -3300 3000
+Wire Wire Line
+ 4500 1700 4500 2350
+Wire Wire Line
+ 4500 2350 2000 2350
+Wire Wire Line
+ 2000 2350 2000 3050
+Wire Wire Line
+ 1700 3050 2300 3050
+Connection ~ 2300 3050
+Wire Wire Line
+ 9750 1650 9750 2150
+Wire Wire Line
+ 9750 2150 7350 2150
+Wire Wire Line
+ 7350 2150 7350 2950
+Wire Wire Line
+ 7100 2950 7550 2950
+Connection ~ 7550 2950
+Wire Wire Line
+ 850 1450 1050 1450
+Connection ~ 850 1450
+Connection ~ 2000 3050
+Wire Wire Line
+ 1850 1100 2300 1100
+Connection ~ 2300 1100
+Wire Wire Line
+ 6300 1450 6550 1450
+Connection ~ 6300 1450
+Wire Wire Line
+ 11550 1450 11750 1450
+Connection ~ 11550 1450
+Wire Wire Line
+ 7150 1050 7550 1050
+Connection ~ 7550 1050
+Connection ~ 7350 2950
+Connection ~ 2650 3800
+Wire Wire Line
+ 7900 3500 7900 3850
+Wire Wire Line
+ -8050 50 -7900 50
+Connection ~ -7900 50
+Wire Wire Line
+ -8200 4000 -7900 4000
+Connection ~ -7900 4000
+Wire Wire Line
+ -5100 1500 -5000 1500
+Wire Wire Line
+ -5000 1500 -5000 500
+Connection ~ -5100 500
+Wire Wire Line
+ -2800 150 -2800 500
+Wire Wire Line
+ -2800 150 -2650 150
+Wire Wire Line
+ -2650 150 -2650 50
+Connection ~ -2650 50
+Wire Wire Line
+ 5450 1500 5650 1500
+Wire Wire Line
+ 5650 1500 5650 500
+Connection ~ 5450 500
+Wire Wire Line
+ 10700 1450 10850 1450
+Wire Wire Line
+ 10850 1450 10850 450
+Connection ~ 10700 450
+Wire Wire Line
+ 2650 200 2650 550
+Wire Wire Line
+ 2650 200 2800 200
+Wire Wire Line
+ 2800 200 2800 100
+Connection ~ 2800 100
+Wire Wire Line
+ 7900 200 7900 500
+Wire Wire Line
+ 7900 200 8000 200
+Wire Wire Line
+ 8000 200 8000 50
+Connection ~ 8000 50
+Wire Wire Line
+ -1350 300 -1350 1800
+Wire Wire Line
+ -400 1300 -200 1300
+Wire Wire Line
+ -100 1500 100 1500
+Wire Wire Line
+ -100 1100 100 1100
+Wire Wire Line
+ 50 450 200 450
+Wire Wire Line
+ 150 50 150 500
+Wire Wire Line
+ 200 450 200 1450
+Connection ~ 150 450
+Wire Wire Line
+ -400 1900 -250 1900
+Wire Wire Line
+ -250 1900 -250 1950
+$Comp
+L eSim_MOS_N M18
+U 1 1 68374D68
+P -150 1750
+F 0 "M18" H -150 1600 50 0000 R CNN
+F 1 "eSim_MOS_N" H -50 1700 50 0000 R CNN
+F 2 "" H 150 1450 29 0000 C CNN
+F 3 "" H -50 1550 60 0000 C CNN
+ 1 -150 1750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 50 3000 50 2150
+Connection ~ -750 3000
+Wire Wire Line
+ 150 2100 150 3800
+Wire Wire Line
+ 150 3800 100 3800
+Connection ~ 100 3800
+Wire Wire Line
+ -100 1700 50 1700
+Wire Wire Line
+ 50 1700 50 1750
+Wire Wire Line
+ -100 850 50 850
+Wire Wire Line
+ -7900 2500 -7900 2200
+Wire Wire Line
+ -7900 2200 -7450 2200
+Wire Wire Line
+ -7450 2200 -7450 100
+Connection ~ -7450 100
+Wire Wire Line
+ 150 50 200 50
+Connection ~ 200 50
+Wire Wire Line
+ -7900 50 -7900 550
+Wire Wire Line
+ -7900 4000 -7900 3550
+Wire Wire Line
+ -8700 1100 -8250 1100
+Wire Wire Line
+ -8050 -350 -8050 50
+Wire Wire Line
+ -2800 1800 -4000 1800
+Wire Wire Line
+ -4000 1800 -4000 3850
+Connection ~ -4000 3850
+Wire Wire Line
+ -7900 1700 -7650 1700
+Wire Wire Line
+ -7650 1700 -7650 3850
+Connection ~ -7650 3850
+Wire Wire Line
+ 2650 1700 3050 1700
+Wire Wire Line
+ 3050 1700 3050 3850
+Connection ~ 3050 3850
+Wire Wire Line
+ 7900 1650 8100 1650
+Wire Wire Line
+ 8100 1650 8100 3800
+Connection ~ 8100 3800
+Wire Wire Line
+ 9250 1850 9250 3400
+Connection ~ 9250 1850
+Wire Wire Line
+ 9250 3400 10950 3400
+Wire Wire Line
+ 10950 3400 10950 1600
+Connection ~ 10950 1600
+Wire Wire Line
+ 3950 1900 3950 3600
+Wire Wire Line
+ 3950 3600 5650 3600
+Wire Wire Line
+ 5650 3600 5650 1650
+Connection ~ 5650 1650
+Connection ~ 3950 1900
+Wire Wire Line
+ -1500 1850 -1500 2850
+Wire Wire Line
+ -1500 2850 250 2850
+Wire Wire Line
+ 250 2850 250 1600
+Connection ~ 250 1600
+Connection ~ -1500 1850
+Wire Wire Line
+ -6550 1900 -6550 2650
+Wire Wire Line
+ -6550 2650 -4900 2650
+Wire Wire Line
+ -4900 2650 -4900 1650
+Connection ~ -4900 1650
+Connection ~ -6550 1900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4030/CD4030.sub b/library/SubcircuitLibrary/CD4030/CD4030.sub
new file mode 100644
index 000000000..6db18def6
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030.sub
@@ -0,0 +1,52 @@
+* Subcircuit CD4030
+.subckt CD4030 net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m21-pad1_ net-_m12-pad2_ net-_m13-pad2_ net-_m1-pad3_ net-_m24-pad2_ net-_m23-pad2_ net-_m32-pad1_ net-_m43-pad1_ net-_m34-pad2_ net-_m35-pad2_ net-_m11-pad3_
+* c:\fossee\esim\library\subcircuitlibrary\cd4030\cd4030.cir
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m8 net-_m8-pad1_ net-_m2-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m11 net-_m10-pad1_ net-_m10-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m9 net-_m8-pad1_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m7 net-_m10-pad2_ net-_m1-pad1_ net-_m2-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m4 net-_m2-pad1_ net-_m2-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m14 net-_m12-pad1_ net-_m12-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m17 net-_m12-pad1_ net-_m13-pad2_ net-_m16-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m13-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m22 net-_m21-pad1_ net-_m16-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m20 net-_m19-pad1_ net-_m12-pad1_ net-_m16-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m21 net-_m21-pad1_ net-_m16-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m12 net-_m12-pad1_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m16 net-_m12-pad1_ net-_m13-pad1_ net-_m16-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m15 net-_m13-pad1_ net-_m13-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m13-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m25 net-_m23-pad1_ net-_m23-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m28 net-_m23-pad1_ net-_m24-pad2_ net-_m27-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m30 net-_m30-pad1_ net-_m24-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m33 net-_m32-pad1_ net-_m27-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m31 net-_m30-pad1_ net-_m23-pad1_ net-_m27-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m29 net-_m27-pad3_ net-_m23-pad1_ net-_m24-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m32 net-_m32-pad1_ net-_m27-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m23 net-_m23-pad1_ net-_m23-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m27 net-_m23-pad1_ net-_m24-pad1_ net-_m27-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m26 net-_m24-pad1_ net-_m24-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m24 net-_m24-pad1_ net-_m24-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m36 net-_m34-pad1_ net-_m34-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m39 net-_m34-pad1_ net-_m35-pad2_ net-_m38-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m41 net-_m41-pad1_ net-_m35-pad1_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m44 net-_m43-pad1_ net-_m38-pad3_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m42 net-_m41-pad1_ net-_m34-pad1_ net-_m38-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m40 net-_m38-pad3_ net-_m34-pad1_ net-_m35-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m43 net-_m43-pad1_ net-_m38-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m34 net-_m34-pad1_ net-_m34-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m38 net-_m34-pad1_ net-_m35-pad1_ net-_m38-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m37 net-_m35-pad1_ net-_m35-pad2_ net-_m11-pad3_ net-_m11-pad3_ mos_p W=100u L=100u M=1
+m35 net-_m35-pad1_ net-_m35-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m18 net-_m16-pad3_ net-_m12-pad1_ net-_m13-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+* Control Statements
+
+.ends CD4030
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030/CD4030_Previous_Values.xml b/library/SubcircuitLibrary/CD4030/CD4030_Previous_Values.xml
new file mode 100644
index 000000000..275563399
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/CD4030_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030/NMOS-5um.lib b/library/SubcircuitLibrary/CD4030/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/CD4030/PMOS-5um.lib b/library/SubcircuitLibrary/CD4030/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/CD4030/analysis b/library/SubcircuitLibrary/CD4030/analysis
new file mode 100644
index 000000000..6783e70d4
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/analysis
@@ -0,0 +1 @@
+.tran 10e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030/xor_test-cache.lib b/library/SubcircuitLibrary/CD4030/xor_test-cache.lib
new file mode 100644
index 000000000..3366a5975
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test-cache.lib
@@ -0,0 +1,96 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CD4030
+#
+DEF CD4030 X 0 40 Y Y 1 F N
+F0 "X" 0 -650 60 H V C CNN
+F1 "CD4030" 0 350 60 H V C CNN
+F2 "" 0 350 60 H I C CNN
+F3 "" 0 350 60 H I C CNN
+DRAW
+S -250 250 250 -550 0 1 0 N
+X A 1 -450 150 200 R 50 50 1 1 I
+X B 2 -450 50 200 R 50 50 1 1 I
+X J 3 -450 -50 200 R 50 50 1 1 O
+X K 4 -450 -150 200 R 50 50 1 1 O
+X C 5 -450 -250 200 R 50 50 1 1 I
+X D 6 -450 -350 200 R 50 50 1 1 I
+X VSS 7 -450 -450 200 R 50 50 1 1 I
+X E 8 450 -450 200 L 50 50 1 1 I
+X F 9 450 -350 200 L 50 50 1 1 I
+X L 10 450 -250 200 L 50 50 1 1 O
+X M 11 450 -150 200 L 50 50 1 1 O
+X G 12 450 -50 200 L 50 50 1 1 I
+X H 13 450 50 200 L 50 50 1 1 I
+X VDD 14 450 150 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.cir b/library/SubcircuitLibrary/CD4030/xor_test.cir
new file mode 100644
index 000000000..3bff35fc3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.cir
@@ -0,0 +1,17 @@
+* C:\Users\pavithra\eSim-Workspace\xor_test\xor_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 12:14:05
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v1 A GND pulse
+v2 B GND pulse
+U4 J plot_v1
+v9 Net-_X1-Pad14_ GND DC
+U1 A plot_v1
+U2 B plot_v1
+X1 A B J ? ? ? GND ? ? ? ? ? ? Net-_X1-Pad14_ CD4030
+
+.end
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.cir.out b/library/SubcircuitLibrary/CD4030/xor_test.cir.out
new file mode 100644
index 000000000..252d284e1
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.cir.out
@@ -0,0 +1,20 @@
+* c:\users\pavithra\esim-workspace\xor_test\xor_test.cir
+
+.include CD4030.sub
+v1 a gnd pulse(0 5 2m 0.1n 0.1n 1m 2m)
+v2 b gnd pulse(0 5 4m 0.1n 0.1n 2m 4m)
+* u4 j plot_v1
+v9 net-_x1-pad14_ gnd dc 5
+* u1 a plot_v1
+* u2 b plot_v1
+x1 a b j ? ? ? gnd ? ? ? ? ? ? net-_x1-pad14_ CD4030
+.tran 10e-06 10e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(j)+6v(a)+12v(b)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.pro b/library/SubcircuitLibrary/CD4030/xor_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.proj b/library/SubcircuitLibrary/CD4030/xor_test.proj
new file mode 100644
index 000000000..6ff11795c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.proj
@@ -0,0 +1 @@
+schematicFile xor_test.sch
diff --git a/library/SubcircuitLibrary/CD4030/xor_test.sch b/library/SubcircuitLibrary/CD4030/xor_test.sch
new file mode 100644
index 000000000..63b84e400
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test.sch
@@ -0,0 +1,248 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:xor_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L pulse v1
+U 1 1 683745BA
+P 2100 3850
+F 0 "v1" H 1900 3950 60 0000 C CNN
+F 1 "pulse" H 1900 3800 60 0000 C CNN
+F 2 "R1" H 1800 3850 60 0000 C CNN
+F 3 "" H 2100 3850 60 0000 C CNN
+ 1 2100 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v2
+U 1 1 68374A0F
+P 2400 4050
+F 0 "v2" H 2200 4150 60 0000 C CNN
+F 1 "pulse" H 2200 4000 60 0000 C CNN
+F 2 "R1" H 2100 4050 60 0000 C CNN
+F 3 "" H 2400 4050 60 0000 C CNN
+ 1 2400 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 68374AF4
+P 2100 4550
+F 0 "#PWR01" H 2100 4300 50 0001 C CNN
+F 1 "eSim_GND" H 2100 4400 50 0000 C CNN
+F 2 "" H 2100 4550 50 0001 C CNN
+F 3 "" H 2100 4550 50 0001 C CNN
+ 1 2100 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 68374B3B
+P 2400 4650
+F 0 "#PWR02" H 2400 4400 50 0001 C CNN
+F 1 "eSim_GND" H 2400 4500 50 0000 C CNN
+F 2 "" H 2400 4650 50 0001 C CNN
+F 3 "" H 2400 4650 50 0001 C CNN
+ 1 2400 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 68377A71
+P 5050 5550
+F 0 "U4" H 5050 6050 60 0000 C CNN
+F 1 "plot_v1" H 5250 5900 60 0000 C CNN
+F 2 "" H 5050 5550 60 0000 C CNN
+F 3 "" H 5050 5550 60 0000 C CNN
+ 1 5050 5550
+ 1 0 0 -1
+$EndComp
+Text GLabel 4850 5500 0 60 Input ~ 0
+J
+$Comp
+L eSim_GND #PWR03
+U 1 1 68375687
+P 5000 3750
+F 0 "#PWR03" H 5000 3500 50 0001 C CNN
+F 1 "eSim_GND" H 5000 3600 50 0000 C CNN
+F 2 "" H 5000 3750 50 0001 C CNN
+F 3 "" H 5000 3750 50 0001 C CNN
+ 1 5000 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v9
+U 1 1 683757DD
+P 6150 2650
+F 0 "v9" H 5950 2750 60 0000 C CNN
+F 1 "DC" H 5950 2600 60 0000 C CNN
+F 2 "R1" H 5850 2650 60 0000 C CNN
+F 3 "" H 6150 2650 60 0000 C CNN
+ 1 6150 2650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_GND #PWR04
+U 1 1 683758F0
+P 6300 2200
+F 0 "#PWR04" H 6300 1950 50 0001 C CNN
+F 1 "eSim_GND" H 6300 2050 50 0000 C CNN
+F 2 "" H 6300 2200 50 0001 C CNN
+F 3 "" H 6300 2200 50 0001 C CNN
+ 1 6300 2200
+ 1 0 0 -1
+$EndComp
+NoConn ~ 6000 3200
+NoConn ~ 6000 3300
+NoConn ~ 6000 3400
+NoConn ~ 6000 3500
+NoConn ~ 6000 3600
+NoConn ~ 6000 3700
+NoConn ~ 5100 3600
+NoConn ~ 5100 3500
+NoConn ~ 5100 3400
+$Comp
+L plot_v1 U1
+U 1 1 683808AA
+P 3000 3300
+F 0 "U1" H 3000 3800 60 0000 C CNN
+F 1 "plot_v1" H 3200 3650 60 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 1 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U2
+U 1 1 6838092D
+P 3050 3950
+F 0 "U2" H 3050 4450 60 0000 C CNN
+F 1 "plot_v1" H 3250 4300 60 0000 C CNN
+F 2 "" H 3050 3950 60 0000 C CNN
+F 3 "" H 3050 3950 60 0000 C CNN
+ 1 3050 3950
+ 1 0 0 -1
+$EndComp
+Text GLabel 2700 3150 0 60 Input ~ 0
+A
+Wire Wire Line
+ 2100 3400 2100 3250
+Wire Wire Line
+ 2100 3250 4400 3250
+Wire Wire Line
+ 2400 3600 2400 3350
+Wire Wire Line
+ 2400 3350 4450 3350
+Wire Wire Line
+ 2100 4300 2100 4550
+Wire Wire Line
+ 2400 4500 2400 4650
+Wire Wire Line
+ 4700 3300 4700 5350
+Wire Wire Line
+ 4700 5350 5050 5350
+Wire Wire Line
+ 4850 5500 4900 5500
+Wire Wire Line
+ 4900 5500 4900 5350
+Connection ~ 4900 5350
+Wire Wire Line
+ 6000 3100 6150 3100
+Wire Wire Line
+ 6150 2200 6300 2200
+Wire Wire Line
+ 4400 3250 4400 3100
+Wire Wire Line
+ 4400 3100 5100 3100
+Wire Wire Line
+ 4450 3350 4450 3200
+Wire Wire Line
+ 4450 3200 5100 3200
+Wire Wire Line
+ 5000 3750 5000 3700
+Wire Wire Line
+ 5000 3700 5100 3700
+Wire Wire Line
+ 4700 3300 5100 3300
+Wire Wire Line
+ 3000 3100 3000 3250
+Connection ~ 3000 3250
+Wire Wire Line
+ 3050 3750 3550 3750
+Wire Wire Line
+ 3550 3750 3550 3350
+Connection ~ 3550 3350
+Wire Wire Line
+ 2700 3150 3000 3150
+Connection ~ 3000 3150
+Text GLabel 3200 3950 0 60 Input ~ 0
+B
+Wire Wire Line
+ 3200 3950 3350 3950
+Wire Wire Line
+ 3350 3950 3350 3750
+Connection ~ 3350 3750
+$Comp
+L CD4030 X1
+U 1 1 68380AFF
+P 5550 3250
+F 0 "X1" H 5550 2600 60 0000 C CNN
+F 1 "CD4030" H 5550 3600 60 0000 C CNN
+F 2 "" H 5550 3600 60 0001 C CNN
+F 3 "" H 5550 3600 60 0001 C CNN
+ 1 5550 3250
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4030/xor_test_Previous_Values.xml b/library/SubcircuitLibrary/CD4030/xor_test_Previous_Values.xml
new file mode 100644
index 000000000..2a955c48a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030/xor_test_Previous_Values.xml
@@ -0,0 +1 @@
+pulse052m0.1n0.1n1m2mpulse054m0.1n0.1n2m4mpulse052m0.1n0.1n1m2mpulse052m0.1n0.1n1m2mpulse052m0.1n0.1n1m2mpulse052m0.1n0.1n1m2mpulse052m0.1n0.1n1m2mpulse052m0.1n0.1n1m2mdc5adc_bridgeadc_bridgedac_bridgedac_bridgeC:\FOSSEE\eSim\library\SubcircuitLibrary\CD4030truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01010msusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B-cache.lib b/library/SubcircuitLibrary/CD4030B/CD4030B-cache.lib
new file mode 100644
index 000000000..348446c2e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/CD4030B-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.bak b/library/SubcircuitLibrary/CD4030B/CD4030B.bak
new file mode 100644
index 000000000..3b3857f06
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/CD4030B.bak
@@ -0,0 +1,56 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.cir b/library/SubcircuitLibrary/CD4030B/CD4030B.cir
new file mode 100644
index 000000000..0199aa42b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/CD4030B.cir
@@ -0,0 +1,55 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4030B\CD4030B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/04/25 22:40:03
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M3 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M4 Net-_M13-Pad3_ Net-_M11-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M2 Net-_M13-Pad3_ Net-_M11-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M9 Net-_M1-Pad1_ Net-_M13-Pad3_ Net-_M11-Pad1_ Net-_M1-Pad3_ eSim_MOS_N
+M11 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M1-Pad1_ Net-_M11-Pad4_ eSim_MOS_P
+M14 Net-_M14-Pad1_ Net-_M13-Pad3_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M15 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M14-Pad1_ Net-_M11-Pad4_ eSim_MOS_P
+M13 Net-_M11-Pad1_ Net-_M1-Pad1_ Net-_M13-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M20 Net-_M19-Pad1_ Net-_M11-Pad1_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M19 Net-_M19-Pad1_ Net-_M11-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+U1 Net-_M1-Pad2_ Net-_M11-Pad2_ Net-_M19-Pad1_ Net-_M41-Pad1_ Net-_M23-Pad2_ Net-_M24-Pad2_ Net-_M1-Pad3_ Net-_M5-Pad2_ Net-_M12-Pad2_ Net-_M21-Pad1_ Net-_M43-Pad1_ Net-_M27-Pad2_ Net-_M28-Pad2_ Net-_M11-Pad4_ PORT
+M25 Net-_M23-Pad1_ Net-_M23-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M23 Net-_M23-Pad1_ Net-_M23-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M26 Net-_M24-Pad1_ Net-_M24-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M24 Net-_M24-Pad1_ Net-_M24-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M31 Net-_M23-Pad1_ Net-_M24-Pad1_ Net-_M31-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M33 Net-_M31-Pad3_ Net-_M24-Pad2_ Net-_M23-Pad1_ Net-_M11-Pad4_ eSim_MOS_P
+M36 Net-_M36-Pad1_ Net-_M24-Pad1_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M37 Net-_M31-Pad3_ Net-_M23-Pad1_ Net-_M36-Pad1_ Net-_M11-Pad4_ eSim_MOS_P
+M35 Net-_M31-Pad3_ Net-_M23-Pad1_ Net-_M24-Pad1_ Net-_M1-Pad3_ eSim_MOS_N
+M42 Net-_M41-Pad1_ Net-_M31-Pad3_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M41 Net-_M41-Pad1_ Net-_M31-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M7 Net-_M10-Pad1_ Net-_M5-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M5 Net-_M10-Pad1_ Net-_M5-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M8 Net-_M10-Pad2_ Net-_M12-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M6 Net-_M10-Pad2_ Net-_M12-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M12 Net-_M10-Pad3_ Net-_M12-Pad2_ Net-_M10-Pad1_ Net-_M11-Pad4_ eSim_MOS_P
+M17 Net-_M17-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M18 Net-_M10-Pad3_ Net-_M10-Pad1_ Net-_M17-Pad1_ Net-_M11-Pad4_ eSim_MOS_P
+M16 Net-_M10-Pad3_ Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ eSim_MOS_N
+M22 Net-_M21-Pad1_ Net-_M10-Pad3_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M21 Net-_M21-Pad1_ Net-_M10-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M29 Net-_M27-Pad1_ Net-_M27-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M27 Net-_M27-Pad1_ Net-_M27-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M30 Net-_M28-Pad1_ Net-_M28-Pad2_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M28 Net-_M28-Pad1_ Net-_M28-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M32 Net-_M27-Pad1_ Net-_M28-Pad1_ Net-_M32-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M34 Net-_M32-Pad3_ Net-_M28-Pad2_ Net-_M27-Pad1_ Net-_M11-Pad4_ eSim_MOS_P
+M39 Net-_M39-Pad1_ Net-_M28-Pad1_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M40 Net-_M32-Pad3_ Net-_M27-Pad1_ Net-_M39-Pad1_ Net-_M11-Pad4_ eSim_MOS_P
+M38 Net-_M32-Pad3_ Net-_M27-Pad1_ Net-_M28-Pad1_ Net-_M1-Pad3_ eSim_MOS_N
+M44 Net-_M43-Pad1_ Net-_M32-Pad3_ Net-_M11-Pad4_ Net-_M11-Pad4_ eSim_MOS_P
+M43 Net-_M43-Pad1_ Net-_M32-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+
+.end
diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.cir.out b/library/SubcircuitLibrary/CD4030B/CD4030B.cir.out
new file mode 100644
index 000000000..137822064
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/CD4030B.cir.out
@@ -0,0 +1,58 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4030b\cd4030b.cir
+
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m4 net-_m13-pad3_ net-_m11-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m2 net-_m13-pad3_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m9 net-_m1-pad1_ net-_m13-pad3_ net-_m11-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m14 net-_m14-pad1_ net-_m13-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m15 net-_m11-pad1_ net-_m1-pad1_ net-_m14-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m13 net-_m11-pad1_ net-_m1-pad1_ net-_m13-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m20 net-_m19-pad1_ net-_m11-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m19 net-_m19-pad1_ net-_m11-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+* u1 net-_m1-pad2_ net-_m11-pad2_ net-_m19-pad1_ net-_m41-pad1_ net-_m23-pad2_ net-_m24-pad2_ net-_m1-pad3_ net-_m5-pad2_ net-_m12-pad2_ net-_m21-pad1_ net-_m43-pad1_ net-_m27-pad2_ net-_m28-pad2_ net-_m11-pad4_ port
+m25 net-_m23-pad1_ net-_m23-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m23 net-_m23-pad1_ net-_m23-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m26 net-_m24-pad1_ net-_m24-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m24 net-_m24-pad1_ net-_m24-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m31 net-_m23-pad1_ net-_m24-pad1_ net-_m31-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m33 net-_m31-pad3_ net-_m24-pad2_ net-_m23-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m36 net-_m36-pad1_ net-_m24-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m37 net-_m31-pad3_ net-_m23-pad1_ net-_m36-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m35 net-_m31-pad3_ net-_m23-pad1_ net-_m24-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m42 net-_m41-pad1_ net-_m31-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m41 net-_m41-pad1_ net-_m31-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m7 net-_m10-pad1_ net-_m5-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m5 net-_m10-pad1_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m8 net-_m10-pad2_ net-_m12-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m6 net-_m10-pad2_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m12 net-_m10-pad3_ net-_m12-pad2_ net-_m10-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m17 net-_m17-pad1_ net-_m10-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m18 net-_m10-pad3_ net-_m10-pad1_ net-_m17-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m16 net-_m10-pad3_ net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m22 net-_m21-pad1_ net-_m10-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m21 net-_m21-pad1_ net-_m10-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m29 net-_m27-pad1_ net-_m27-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m27 net-_m27-pad1_ net-_m27-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m30 net-_m28-pad1_ net-_m28-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m28 net-_m28-pad1_ net-_m28-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m32 net-_m27-pad1_ net-_m28-pad1_ net-_m32-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m34 net-_m32-pad3_ net-_m28-pad2_ net-_m27-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m39 net-_m39-pad1_ net-_m28-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m40 net-_m32-pad3_ net-_m27-pad1_ net-_m39-pad1_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m38 net-_m32-pad3_ net-_m27-pad1_ net-_m28-pad1_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m44 net-_m43-pad1_ net-_m32-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=100u L=100u M=1
+m43 net-_m43-pad1_ net-_m32-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.pro b/library/SubcircuitLibrary/CD4030B/CD4030B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/CD4030B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.sch b/library/SubcircuitLibrary/CD4030B/CD4030B.sch
new file mode 100644
index 000000000..d5b5ac21f
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/CD4030B.sch
@@ -0,0 +1,1437 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:EXOR_S-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M3
+U 1 1 6868098D
+P 5150 3150
+F 0 "M3" H 5100 3200 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5200 3300 50 0000 R CNN
+F 2 "" H 5400 3250 29 0000 C CNN
+F 3 "" H 5200 3150 60 0000 C CNN
+ 1 5150 3150
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M1
+U 1 1 6868098E
+P 5100 3850
+F 0 "M1" H 5100 3700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 5200 3800 50 0000 R CNN
+F 2 "" H 5400 3550 29 0000 C CNN
+F 3 "" H 5200 3650 60 0000 C CNN
+ 1 5100 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 6868098F
+P 5150 5200
+F 0 "M4" H 5100 5250 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5200 5350 50 0000 R CNN
+F 2 "" H 5400 5300 29 0000 C CNN
+F 3 "" H 5200 5200 60 0000 C CNN
+ 1 5150 5200
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 68680990
+P 5100 5900
+F 0 "M2" H 5100 5750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 5200 5850 50 0000 R CNN
+F 2 "" H 5400 5600 29 0000 C CNN
+F 3 "" H 5200 5700 60 0000 C CNN
+ 1 5100 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M9
+U 1 1 68680991
+P 7350 4400
+F 0 "M9" H 7350 4250 50 0000 R CNN
+F 1 "eSim_MOS_N" H 7450 4350 50 0000 R CNN
+F 2 "" H 7650 4100 29 0000 C CNN
+F 3 "" H 7450 4200 60 0000 C CNN
+ 1 7350 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M11
+U 1 1 68680992
+P 8500 4600
+F 0 "M11" H 8450 4650 50 0000 R CNN
+F 1 "eSim_MOS_P" H 8550 4750 50 0000 R CNN
+F 2 "" H 8750 4700 29 0000 C CNN
+F 3 "" H 8550 4600 60 0000 C CNN
+ 1 8500 4600
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M14
+U 1 1 68680993
+P 10600 3000
+F 0 "M14" H 10550 3050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10650 3150 50 0000 R CNN
+F 2 "" H 10850 3100 29 0000 C CNN
+F 3 "" H 10650 3000 60 0000 C CNN
+ 1 10600 3000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M15
+U 1 1 68680994
+P 10600 3950
+F 0 "M15" H 10550 4000 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10650 4100 50 0000 R CNN
+F 2 "" H 10850 4050 29 0000 C CNN
+F 3 "" H 10650 3950 60 0000 C CNN
+ 1 10600 3950
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M13
+U 1 1 68680995
+P 10550 4850
+F 0 "M13" H 10550 4700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10650 4800 50 0000 R CNN
+F 2 "" H 10850 4550 29 0000 C CNN
+F 3 "" H 10650 4650 60 0000 C CNN
+ 1 10550 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M20
+U 1 1 68680996
+P 12300 4250
+F 0 "M20" H 12250 4300 50 0000 R CNN
+F 1 "eSim_MOS_P" H 12350 4400 50 0000 R CNN
+F 2 "" H 12550 4350 29 0000 C CNN
+F 3 "" H 12350 4250 60 0000 C CNN
+ 1 12300 4250
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M19
+U 1 1 68680997
+P 12250 4950
+F 0 "M19" H 12250 4800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 12350 4900 50 0000 R CNN
+F 2 "" H 12550 4650 29 0000 C CNN
+F 3 "" H 12350 4750 60 0000 C CNN
+ 1 12250 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68680998
+P 3300 5650
+F 0 "U1" H 3350 5750 30 0000 C CNN
+F 1 "PORT" H 3300 5650 30 0000 C CNN
+F 2 "" H 3300 5650 60 0000 C CNN
+F 3 "" H 3300 5650 60 0000 C CNN
+ 2 3300 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68680999
+P 3400 3600
+F 0 "U1" H 3450 3700 30 0000 C CNN
+F 1 "PORT" H 3400 3600 30 0000 C CNN
+F 2 "" H 3400 3600 60 0000 C CNN
+F 3 "" H 3400 3600 60 0000 C CNN
+ 1 3400 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6868099A
+P 13200 4700
+F 0 "U1" H 13250 4800 30 0000 C CNN
+F 1 "PORT" H 13200 4700 30 0000 C CNN
+F 2 "" H 13200 4700 60 0000 C CNN
+F 3 "" H 13200 4700 60 0000 C CNN
+ 3 13200 4700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6868099B
+P 8500 1650
+F 0 "U1" H 8550 1750 30 0000 C CNN
+F 1 "PORT" H 8500 1650 30 0000 C CNN
+F 2 "" H 8500 1650 60 0000 C CNN
+F 3 "" H 8500 1650 60 0000 C CNN
+ 14 8500 1650
+ 1 0 0 -1
+$EndComp
+Connection ~ 8750 1950
+Wire Wire Line
+ 8750 1650 8750 1950
+Connection ~ 12450 7650
+Wire Wire Line
+ 12550 5300 12550 7700
+Connection ~ 10850 7650
+Wire Wire Line
+ 10850 5200 10850 7650
+Connection ~ 7650 7650
+Wire Wire Line
+ 12450 7650 12450 5350
+Connection ~ 8250 1950
+Wire Wire Line
+ 8250 4450 8250 1950
+Connection ~ 5600 7650
+Wire Wire Line
+ 5600 4500 5600 7650
+Wire Wire Line
+ 5400 4500 5600 4500
+Wire Wire Line
+ 5400 4200 5400 4500
+Connection ~ 5550 7650
+Wire Wire Line
+ 5550 4550 5550 7650
+Wire Wire Line
+ 5300 4550 5550 4550
+Wire Wire Line
+ 5300 4250 5300 4550
+Connection ~ 5400 7650
+Wire Wire Line
+ 2350 7650 12550 7650
+Wire Wire Line
+ 7650 7650 7650 4750
+Wire Wire Line
+ 5400 6250 5400 7650
+Wire Wire Line
+ 5300 6300 5300 7650
+Connection ~ 5950 1950
+Wire Wire Line
+ 5950 4900 5950 1950
+Wire Wire Line
+ 5400 4900 5950 4900
+Wire Wire Line
+ 5400 5050 5400 4900
+Connection ~ 5800 1950
+Wire Wire Line
+ 5800 4800 5800 1950
+Wire Wire Line
+ 5300 4800 5800 4800
+Wire Wire Line
+ 5300 5000 5300 4800
+Connection ~ 5400 1950
+Wire Wire Line
+ 5400 3000 5400 1950
+Connection ~ 12450 2600
+Wire Wire Line
+ 12550 2600 12550 4100
+Connection ~ 11000 2600
+Wire Wire Line
+ 11000 3500 11000 2600
+Wire Wire Line
+ 10850 3500 11000 3500
+Wire Wire Line
+ 10850 3800 10850 3500
+Connection ~ 10850 2600
+Wire Wire Line
+ 10850 2850 10850 2600
+Connection ~ 10750 2600
+Wire Wire Line
+ 5300 1950 10750 1950
+Wire Wire Line
+ 5300 2950 5300 1950
+Connection ~ 4650 3600
+Wire Wire Line
+ 4650 3600 3650 3600
+Wire Wire Line
+ 4650 4050 5000 4050
+Wire Wire Line
+ 4650 3150 4650 4050
+Wire Wire Line
+ 5000 3150 4650 3150
+Connection ~ 12450 4700
+Wire Wire Line
+ 12450 4700 12950 4700
+Wire Wire Line
+ 12450 4950 12450 4450
+Wire Wire Line
+ 10750 1950 10750 2800
+Wire Wire Line
+ 10750 2600 12550 2600
+Wire Wire Line
+ 12450 4050 12450 2600
+Wire Wire Line
+ 10750 3200 10750 3750
+Connection ~ 9700 5650
+Wire Wire Line
+ 9700 3000 9700 5650
+Wire Wire Line
+ 10450 3000 9700 3000
+Connection ~ 7950 5100
+Connection ~ 11350 4600
+Wire Wire Line
+ 11350 6100 11350 4600
+Wire Wire Line
+ 7950 6100 11350 6100
+Wire Wire Line
+ 7950 5100 7950 6100
+Connection ~ 10750 4600
+Connection ~ 11900 4600
+Wire Wire Line
+ 10750 4600 11900 4600
+Wire Wire Line
+ 11900 5150 12150 5150
+Wire Wire Line
+ 11900 4250 11900 5150
+Wire Wire Line
+ 12150 4250 11900 4250
+Wire Wire Line
+ 10750 4150 10750 4850
+Connection ~ 4250 5650
+Wire Wire Line
+ 8900 4600 8650 4600
+Wire Wire Line
+ 8900 6500 8900 4600
+Wire Wire Line
+ 4250 6500 8900 6500
+Wire Wire Line
+ 4250 5650 4250 6500
+Connection ~ 4600 5650
+Wire Wire Line
+ 4600 5650 3550 5650
+Wire Wire Line
+ 4600 6100 5000 6100
+Wire Wire Line
+ 4600 5200 4600 6100
+Wire Wire Line
+ 5000 5200 4600 5200
+Connection ~ 6700 5650
+Wire Wire Line
+ 6700 4600 6700 5650
+Wire Wire Line
+ 7250 4600 6700 4600
+Connection ~ 5300 5650
+Wire Wire Line
+ 10750 5650 5300 5650
+Wire Wire Line
+ 10750 5250 10750 5650
+Wire Wire Line
+ 5300 5400 5300 5900
+Wire Wire Line
+ 8350 5100 8350 4800
+Wire Wire Line
+ 7550 5100 8350 5100
+Wire Wire Line
+ 7550 4800 7550 5100
+Connection ~ 7950 4250
+Connection ~ 7950 3600
+Wire Wire Line
+ 7950 4250 7950 3600
+Connection ~ 10150 4500
+Connection ~ 5300 3600
+Wire Wire Line
+ 9300 3600 5300 3600
+Wire Wire Line
+ 9300 4500 9300 3600
+Wire Wire Line
+ 10150 4500 9300 4500
+Wire Wire Line
+ 10150 5050 10450 5050
+Wire Wire Line
+ 10150 3950 10150 5050
+Wire Wire Line
+ 10450 3950 10150 3950
+Wire Wire Line
+ 8350 4250 8350 4400
+Wire Wire Line
+ 7550 4250 8350 4250
+Wire Wire Line
+ 7550 4400 7550 4250
+Wire Wire Line
+ 5300 3350 5300 3850
+$Comp
+L eSim_MOS_P M25
+U 1 1 68681092
+P 17600 3200
+F 0 "M25" H 17550 3250 50 0000 R CNN
+F 1 "eSim_MOS_P" H 17650 3350 50 0000 R CNN
+F 2 "" H 17850 3300 29 0000 C CNN
+F 3 "" H 17650 3200 60 0000 C CNN
+ 1 17600 3200
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M23
+U 1 1 68681098
+P 17550 3900
+F 0 "M23" H 17550 3750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 17650 3850 50 0000 R CNN
+F 2 "" H 17850 3600 29 0000 C CNN
+F 3 "" H 17650 3700 60 0000 C CNN
+ 1 17550 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M26
+U 1 1 6868109E
+P 17600 5250
+F 0 "M26" H 17550 5300 50 0000 R CNN
+F 1 "eSim_MOS_P" H 17650 5400 50 0000 R CNN
+F 2 "" H 17850 5350 29 0000 C CNN
+F 3 "" H 17650 5250 60 0000 C CNN
+ 1 17600 5250
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M24
+U 1 1 686810A4
+P 17550 5950
+F 0 "M24" H 17550 5800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 17650 5900 50 0000 R CNN
+F 2 "" H 17850 5650 29 0000 C CNN
+F 3 "" H 17650 5750 60 0000 C CNN
+ 1 17550 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M31
+U 1 1 686810AA
+P 19800 4450
+F 0 "M31" H 19800 4300 50 0000 R CNN
+F 1 "eSim_MOS_N" H 19900 4400 50 0000 R CNN
+F 2 "" H 20100 4150 29 0000 C CNN
+F 3 "" H 19900 4250 60 0000 C CNN
+ 1 19800 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M33
+U 1 1 686810B0
+P 20950 4650
+F 0 "M33" H 20900 4700 50 0000 R CNN
+F 1 "eSim_MOS_P" H 21000 4800 50 0000 R CNN
+F 2 "" H 21200 4750 29 0000 C CNN
+F 3 "" H 21000 4650 60 0000 C CNN
+ 1 20950 4650
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M36
+U 1 1 686810B6
+P 23050 3050
+F 0 "M36" H 23000 3100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 23100 3200 50 0000 R CNN
+F 2 "" H 23300 3150 29 0000 C CNN
+F 3 "" H 23100 3050 60 0000 C CNN
+ 1 23050 3050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M37
+U 1 1 686810BC
+P 23050 4000
+F 0 "M37" H 23000 4050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 23100 4150 50 0000 R CNN
+F 2 "" H 23300 4100 29 0000 C CNN
+F 3 "" H 23100 4000 60 0000 C CNN
+ 1 23050 4000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M35
+U 1 1 686810C2
+P 23000 4900
+F 0 "M35" H 23000 4750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 23100 4850 50 0000 R CNN
+F 2 "" H 23300 4600 29 0000 C CNN
+F 3 "" H 23100 4700 60 0000 C CNN
+ 1 23000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M42
+U 1 1 686810C8
+P 24750 4300
+F 0 "M42" H 24700 4350 50 0000 R CNN
+F 1 "eSim_MOS_P" H 24800 4450 50 0000 R CNN
+F 2 "" H 25000 4400 29 0000 C CNN
+F 3 "" H 24800 4300 60 0000 C CNN
+ 1 24750 4300
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M41
+U 1 1 686810CE
+P 24700 5000
+F 0 "M41" H 24700 4850 50 0000 R CNN
+F 1 "eSim_MOS_N" H 24800 4950 50 0000 R CNN
+F 2 "" H 25000 4700 29 0000 C CNN
+F 3 "" H 24800 4800 60 0000 C CNN
+ 1 24700 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686810D4
+P 15750 5700
+F 0 "U1" H 15800 5800 30 0000 C CNN
+F 1 "PORT" H 15750 5700 30 0000 C CNN
+F 2 "" H 15750 5700 60 0000 C CNN
+F 3 "" H 15750 5700 60 0000 C CNN
+ 6 15750 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686810DA
+P 15850 3650
+F 0 "U1" H 15900 3750 30 0000 C CNN
+F 1 "PORT" H 15850 3650 30 0000 C CNN
+F 2 "" H 15850 3650 60 0000 C CNN
+F 3 "" H 15850 3650 60 0000 C CNN
+ 5 15850 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686810E0
+P 25650 4750
+F 0 "U1" H 25700 4850 30 0000 C CNN
+F 1 "PORT" H 25650 4750 30 0000 C CNN
+F 2 "" H 25650 4750 60 0000 C CNN
+F 3 "" H 25650 4750 60 0000 C CNN
+ 4 25650 4750
+ -1 0 0 1
+$EndComp
+Connection ~ 24900 7700
+Wire Wire Line
+ 25000 7700 25000 5350
+Connection ~ 23300 7700
+Wire Wire Line
+ 23300 5250 23300 7700
+Connection ~ 20100 7700
+Wire Wire Line
+ 24900 7700 24900 5400
+Connection ~ 20700 2000
+Wire Wire Line
+ 20700 4500 20700 2000
+Connection ~ 18050 7700
+Wire Wire Line
+ 18050 4550 18050 7700
+Wire Wire Line
+ 17850 4550 18050 4550
+Wire Wire Line
+ 17850 4250 17850 4550
+Connection ~ 18000 7700
+Wire Wire Line
+ 18000 4600 18000 7700
+Wire Wire Line
+ 17750 4600 18000 4600
+Wire Wire Line
+ 17750 4300 17750 4600
+Connection ~ 17850 7700
+Wire Wire Line
+ 12550 7700 25000 7700
+Wire Wire Line
+ 20100 7700 20100 4800
+Wire Wire Line
+ 17850 6300 17850 7700
+Wire Wire Line
+ 17750 6350 17750 7700
+Connection ~ 18400 2000
+Wire Wire Line
+ 18400 4950 18400 2000
+Wire Wire Line
+ 17850 4950 18400 4950
+Wire Wire Line
+ 17850 5100 17850 4950
+Connection ~ 18250 2000
+Wire Wire Line
+ 18250 4850 18250 2000
+Wire Wire Line
+ 17750 4850 18250 4850
+Wire Wire Line
+ 17750 5050 17750 4850
+Connection ~ 17850 2000
+Wire Wire Line
+ 17850 3050 17850 2000
+Connection ~ 24900 2650
+Wire Wire Line
+ 25000 2650 25000 4150
+Connection ~ 23450 2650
+Wire Wire Line
+ 23450 3550 23450 2650
+Wire Wire Line
+ 23300 3550 23450 3550
+Wire Wire Line
+ 23300 3850 23300 3550
+Connection ~ 23300 2650
+Wire Wire Line
+ 23300 2900 23300 2650
+Connection ~ 23200 2650
+Wire Wire Line
+ 10750 2000 29150 2000
+Wire Wire Line
+ 17750 3000 17750 2000
+Connection ~ 17100 3650
+Wire Wire Line
+ 17100 3650 16100 3650
+Wire Wire Line
+ 17100 4100 17450 4100
+Wire Wire Line
+ 17100 3200 17100 4100
+Wire Wire Line
+ 17450 3200 17100 3200
+Connection ~ 24900 4750
+Wire Wire Line
+ 24900 4750 25400 4750
+Wire Wire Line
+ 24900 5000 24900 4500
+Wire Wire Line
+ 23200 2000 23200 2850
+Wire Wire Line
+ 23200 2650 25000 2650
+Wire Wire Line
+ 24900 4100 24900 2650
+Wire Wire Line
+ 23200 3250 23200 3800
+Connection ~ 22150 5700
+Wire Wire Line
+ 22150 3050 22150 5700
+Wire Wire Line
+ 22900 3050 22150 3050
+Connection ~ 20400 5150
+Connection ~ 23800 4650
+Wire Wire Line
+ 23800 6150 23800 4650
+Wire Wire Line
+ 20400 6150 23800 6150
+Wire Wire Line
+ 20400 5150 20400 6150
+Connection ~ 23200 4650
+Connection ~ 24350 4650
+Wire Wire Line
+ 23200 4650 24350 4650
+Wire Wire Line
+ 24350 5200 24600 5200
+Wire Wire Line
+ 24350 4300 24350 5200
+Wire Wire Line
+ 24600 4300 24350 4300
+Wire Wire Line
+ 23200 4200 23200 4900
+Connection ~ 16700 5700
+Wire Wire Line
+ 21350 4650 21100 4650
+Wire Wire Line
+ 21350 6550 21350 4650
+Wire Wire Line
+ 16700 6550 21350 6550
+Wire Wire Line
+ 16700 5700 16700 6550
+Connection ~ 17050 5700
+Wire Wire Line
+ 17050 5700 16000 5700
+Wire Wire Line
+ 17050 6150 17450 6150
+Wire Wire Line
+ 17050 5250 17050 6150
+Wire Wire Line
+ 17450 5250 17050 5250
+Connection ~ 19150 5700
+Wire Wire Line
+ 19150 4650 19150 5700
+Wire Wire Line
+ 19700 4650 19150 4650
+Connection ~ 17750 5700
+Wire Wire Line
+ 23200 5700 17750 5700
+Wire Wire Line
+ 23200 5300 23200 5700
+Wire Wire Line
+ 17750 5450 17750 5950
+Wire Wire Line
+ 20800 5150 20800 4850
+Wire Wire Line
+ 20000 5150 20800 5150
+Wire Wire Line
+ 20000 4850 20000 5150
+Connection ~ 20400 4300
+Connection ~ 20400 3650
+Wire Wire Line
+ 20400 4300 20400 3650
+Connection ~ 22600 4550
+Connection ~ 17750 3650
+Wire Wire Line
+ 21750 3650 17750 3650
+Wire Wire Line
+ 21750 4550 21750 3650
+Wire Wire Line
+ 22600 4550 21750 4550
+Wire Wire Line
+ 22600 5100 22900 5100
+Wire Wire Line
+ 22600 4000 22600 5100
+Wire Wire Line
+ 22900 4000 22600 4000
+Wire Wire Line
+ 20800 4300 20800 4450
+Wire Wire Line
+ 20000 4300 20800 4300
+Wire Wire Line
+ 20000 4450 20000 4300
+Wire Wire Line
+ 17750 3400 17750 3900
+$Comp
+L eSim_MOS_P M7
+U 1 1 68681638
+P 5850 11950
+F 0 "M7" H 5800 12000 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5900 12100 50 0000 R CNN
+F 2 "" H 6100 12050 29 0000 C CNN
+F 3 "" H 5900 11950 60 0000 C CNN
+ 1 5850 11950
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 6868163E
+P 5800 12650
+F 0 "M5" H 5800 12500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 5900 12600 50 0000 R CNN
+F 2 "" H 6100 12350 29 0000 C CNN
+F 3 "" H 5900 12450 60 0000 C CNN
+ 1 5800 12650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M8
+U 1 1 68681644
+P 5850 14000
+F 0 "M8" H 5800 14050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5900 14150 50 0000 R CNN
+F 2 "" H 6100 14100 29 0000 C CNN
+F 3 "" H 5900 14000 60 0000 C CNN
+ 1 5850 14000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M6
+U 1 1 6868164A
+P 5800 14700
+F 0 "M6" H 5800 14550 50 0000 R CNN
+F 1 "eSim_MOS_N" H 5900 14650 50 0000 R CNN
+F 2 "" H 6100 14400 29 0000 C CNN
+F 3 "" H 5900 14500 60 0000 C CNN
+ 1 5800 14700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 68681650
+P 8050 13200
+F 0 "M10" H 8050 13050 50 0000 R CNN
+F 1 "eSim_MOS_N" H 8150 13150 50 0000 R CNN
+F 2 "" H 8350 12900 29 0000 C CNN
+F 3 "" H 8150 13000 60 0000 C CNN
+ 1 8050 13200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M12
+U 1 1 68681656
+P 9200 13400
+F 0 "M12" H 9150 13450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 9250 13550 50 0000 R CNN
+F 2 "" H 9450 13500 29 0000 C CNN
+F 3 "" H 9250 13400 60 0000 C CNN
+ 1 9200 13400
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M17
+U 1 1 6868165C
+P 11300 11800
+F 0 "M17" H 11250 11850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 11350 11950 50 0000 R CNN
+F 2 "" H 11550 11900 29 0000 C CNN
+F 3 "" H 11350 11800 60 0000 C CNN
+ 1 11300 11800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M18
+U 1 1 68681662
+P 11300 12750
+F 0 "M18" H 11250 12800 50 0000 R CNN
+F 1 "eSim_MOS_P" H 11350 12900 50 0000 R CNN
+F 2 "" H 11550 12850 29 0000 C CNN
+F 3 "" H 11350 12750 60 0000 C CNN
+ 1 11300 12750
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M16
+U 1 1 68681668
+P 11250 13650
+F 0 "M16" H 11250 13500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 11350 13600 50 0000 R CNN
+F 2 "" H 11550 13350 29 0000 C CNN
+F 3 "" H 11350 13450 60 0000 C CNN
+ 1 11250 13650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M22
+U 1 1 6868166E
+P 13000 13050
+F 0 "M22" H 12950 13100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 13050 13200 50 0000 R CNN
+F 2 "" H 13250 13150 29 0000 C CNN
+F 3 "" H 13050 13050 60 0000 C CNN
+ 1 13000 13050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M21
+U 1 1 68681674
+P 12950 13750
+F 0 "M21" H 12950 13600 50 0000 R CNN
+F 1 "eSim_MOS_N" H 13050 13700 50 0000 R CNN
+F 2 "" H 13250 13450 29 0000 C CNN
+F 3 "" H 13050 13550 60 0000 C CNN
+ 1 12950 13750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6868167A
+P 4000 14450
+F 0 "U1" H 4050 14550 30 0000 C CNN
+F 1 "PORT" H 4000 14450 30 0000 C CNN
+F 2 "" H 4000 14450 60 0000 C CNN
+F 3 "" H 4000 14450 60 0000 C CNN
+ 9 4000 14450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68681680
+P 4100 12400
+F 0 "U1" H 4150 12500 30 0000 C CNN
+F 1 "PORT" H 4100 12400 30 0000 C CNN
+F 2 "" H 4100 12400 60 0000 C CNN
+F 3 "" H 4100 12400 60 0000 C CNN
+ 8 4100 12400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 68681686
+P 13900 13500
+F 0 "U1" H 13950 13600 30 0000 C CNN
+F 1 "PORT" H 13900 13500 30 0000 C CNN
+F 2 "" H 13900 13500 60 0000 C CNN
+F 3 "" H 13900 13500 60 0000 C CNN
+ 10 13900 13500
+ -1 0 0 1
+$EndComp
+Connection ~ 13150 16450
+Wire Wire Line
+ 13250 16450 13250 14100
+Connection ~ 11550 16450
+Wire Wire Line
+ 11550 14000 11550 16450
+Connection ~ 8350 16450
+Wire Wire Line
+ 13150 16450 13150 14150
+Connection ~ 8950 10750
+Wire Wire Line
+ 8950 13250 8950 10750
+Connection ~ 6300 16450
+Wire Wire Line
+ 6300 13300 6300 16450
+Wire Wire Line
+ 6100 13300 6300 13300
+Wire Wire Line
+ 6100 13000 6100 13300
+Connection ~ 6250 16450
+Wire Wire Line
+ 6250 13350 6250 16450
+Wire Wire Line
+ 6000 13350 6250 13350
+Wire Wire Line
+ 6000 13050 6000 13350
+Connection ~ 6100 16450
+Wire Wire Line
+ 2350 16450 18200 16450
+Wire Wire Line
+ 8350 16450 8350 13550
+Wire Wire Line
+ 6100 15050 6100 16450
+Wire Wire Line
+ 6000 15100 6000 16450
+Connection ~ 6650 10750
+Wire Wire Line
+ 6650 13700 6650 10750
+Wire Wire Line
+ 6100 13700 6650 13700
+Wire Wire Line
+ 6100 13850 6100 13700
+Connection ~ 6500 10750
+Wire Wire Line
+ 6500 13600 6500 10750
+Wire Wire Line
+ 6000 13600 6500 13600
+Wire Wire Line
+ 6000 13800 6000 13600
+Connection ~ 6100 10750
+Wire Wire Line
+ 6100 11800 6100 10750
+Connection ~ 13150 11400
+Wire Wire Line
+ 13250 11400 13250 12900
+Connection ~ 11700 11400
+Wire Wire Line
+ 11700 12300 11700 11400
+Wire Wire Line
+ 11550 12300 11700 12300
+Wire Wire Line
+ 11550 12600 11550 12300
+Connection ~ 11550 11400
+Wire Wire Line
+ 11550 11650 11550 11400
+Connection ~ 11450 11400
+Wire Wire Line
+ 6000 10750 18450 10750
+Wire Wire Line
+ 6000 11750 6000 10750
+Connection ~ 5350 12400
+Wire Wire Line
+ 5350 12400 4350 12400
+Wire Wire Line
+ 5350 12850 5700 12850
+Wire Wire Line
+ 5350 11950 5350 12850
+Wire Wire Line
+ 5700 11950 5350 11950
+Connection ~ 13150 13500
+Wire Wire Line
+ 13150 13500 13650 13500
+Wire Wire Line
+ 13150 13750 13150 13250
+Wire Wire Line
+ 11450 10750 11450 11600
+Wire Wire Line
+ 11450 11400 13250 11400
+Wire Wire Line
+ 13150 12850 13150 11400
+Wire Wire Line
+ 11450 12000 11450 12550
+Connection ~ 10400 14450
+Wire Wire Line
+ 10400 11800 10400 14450
+Wire Wire Line
+ 11150 11800 10400 11800
+Connection ~ 8650 13900
+Connection ~ 12050 13400
+Wire Wire Line
+ 12050 14900 12050 13400
+Wire Wire Line
+ 8650 14900 12050 14900
+Wire Wire Line
+ 8650 13900 8650 14900
+Connection ~ 11450 13400
+Connection ~ 12600 13400
+Wire Wire Line
+ 11450 13400 12600 13400
+Wire Wire Line
+ 12600 13950 12850 13950
+Wire Wire Line
+ 12600 13050 12600 13950
+Wire Wire Line
+ 12850 13050 12600 13050
+Wire Wire Line
+ 11450 12950 11450 13650
+Connection ~ 4950 14450
+Wire Wire Line
+ 9600 13400 9350 13400
+Wire Wire Line
+ 9600 15300 9600 13400
+Wire Wire Line
+ 4950 15300 9600 15300
+Wire Wire Line
+ 4950 14450 4950 15300
+Connection ~ 5300 14450
+Wire Wire Line
+ 5300 14450 4250 14450
+Wire Wire Line
+ 5300 14900 5700 14900
+Wire Wire Line
+ 5300 14000 5300 14900
+Wire Wire Line
+ 5700 14000 5300 14000
+Connection ~ 7400 14450
+Wire Wire Line
+ 7400 13400 7400 14450
+Wire Wire Line
+ 7950 13400 7400 13400
+Connection ~ 6000 14450
+Wire Wire Line
+ 11450 14450 6000 14450
+Wire Wire Line
+ 11450 14050 11450 14450
+Wire Wire Line
+ 6000 14200 6000 14700
+Wire Wire Line
+ 9050 13900 9050 13600
+Wire Wire Line
+ 8250 13900 9050 13900
+Wire Wire Line
+ 8250 13600 8250 13900
+Connection ~ 8650 13050
+Connection ~ 8650 12400
+Wire Wire Line
+ 8650 13050 8650 12400
+Connection ~ 10850 13300
+Connection ~ 6000 12400
+Wire Wire Line
+ 10000 12400 6000 12400
+Wire Wire Line
+ 10000 13300 10000 12400
+Wire Wire Line
+ 10850 13300 10000 13300
+Wire Wire Line
+ 10850 13850 11150 13850
+Wire Wire Line
+ 10850 12750 10850 13850
+Wire Wire Line
+ 11150 12750 10850 12750
+Wire Wire Line
+ 9050 13050 9050 13200
+Wire Wire Line
+ 8250 13050 9050 13050
+Wire Wire Line
+ 8250 13200 8250 13050
+Wire Wire Line
+ 6000 12150 6000 12650
+$Comp
+L eSim_MOS_P M29
+U 1 1 68681704
+P 18300 12000
+F 0 "M29" H 18250 12050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 18350 12150 50 0000 R CNN
+F 2 "" H 18550 12100 29 0000 C CNN
+F 3 "" H 18350 12000 60 0000 C CNN
+ 1 18300 12000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M27
+U 1 1 6868170A
+P 18250 12700
+F 0 "M27" H 18250 12550 50 0000 R CNN
+F 1 "eSim_MOS_N" H 18350 12650 50 0000 R CNN
+F 2 "" H 18550 12400 29 0000 C CNN
+F 3 "" H 18350 12500 60 0000 C CNN
+ 1 18250 12700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M30
+U 1 1 68681710
+P 18300 14050
+F 0 "M30" H 18250 14100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 18350 14200 50 0000 R CNN
+F 2 "" H 18550 14150 29 0000 C CNN
+F 3 "" H 18350 14050 60 0000 C CNN
+ 1 18300 14050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M28
+U 1 1 68681716
+P 18250 14750
+F 0 "M28" H 18250 14600 50 0000 R CNN
+F 1 "eSim_MOS_N" H 18350 14700 50 0000 R CNN
+F 2 "" H 18550 14450 29 0000 C CNN
+F 3 "" H 18350 14550 60 0000 C CNN
+ 1 18250 14750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M32
+U 1 1 6868171C
+P 20500 13250
+F 0 "M32" H 20500 13100 50 0000 R CNN
+F 1 "eSim_MOS_N" H 20600 13200 50 0000 R CNN
+F 2 "" H 20800 12950 29 0000 C CNN
+F 3 "" H 20600 13050 60 0000 C CNN
+ 1 20500 13250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M34
+U 1 1 68681722
+P 21650 13450
+F 0 "M34" H 21600 13500 50 0000 R CNN
+F 1 "eSim_MOS_P" H 21700 13600 50 0000 R CNN
+F 2 "" H 21900 13550 29 0000 C CNN
+F 3 "" H 21700 13450 60 0000 C CNN
+ 1 21650 13450
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M39
+U 1 1 68681728
+P 23750 11850
+F 0 "M39" H 23700 11900 50 0000 R CNN
+F 1 "eSim_MOS_P" H 23800 12000 50 0000 R CNN
+F 2 "" H 24000 11950 29 0000 C CNN
+F 3 "" H 23800 11850 60 0000 C CNN
+ 1 23750 11850
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M40
+U 1 1 6868172E
+P 23750 12800
+F 0 "M40" H 23700 12850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 23800 12950 50 0000 R CNN
+F 2 "" H 24000 12900 29 0000 C CNN
+F 3 "" H 23800 12800 60 0000 C CNN
+ 1 23750 12800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M38
+U 1 1 68681734
+P 23700 13700
+F 0 "M38" H 23700 13550 50 0000 R CNN
+F 1 "eSim_MOS_N" H 23800 13650 50 0000 R CNN
+F 2 "" H 24000 13400 29 0000 C CNN
+F 3 "" H 23800 13500 60 0000 C CNN
+ 1 23700 13700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M44
+U 1 1 6868173A
+P 25450 13100
+F 0 "M44" H 25400 13150 50 0000 R CNN
+F 1 "eSim_MOS_P" H 25500 13250 50 0000 R CNN
+F 2 "" H 25700 13200 29 0000 C CNN
+F 3 "" H 25500 13100 60 0000 C CNN
+ 1 25450 13100
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M43
+U 1 1 68681740
+P 25400 13800
+F 0 "M43" H 25400 13650 50 0000 R CNN
+F 1 "eSim_MOS_N" H 25500 13750 50 0000 R CNN
+F 2 "" H 25700 13500 29 0000 C CNN
+F 3 "" H 25500 13600 60 0000 C CNN
+ 1 25400 13800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68681746
+P 16450 14500
+F 0 "U1" H 16500 14600 30 0000 C CNN
+F 1 "PORT" H 16450 14500 30 0000 C CNN
+F 2 "" H 16450 14500 60 0000 C CNN
+F 3 "" H 16450 14500 60 0000 C CNN
+ 13 16450 14500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6868174C
+P 16550 12450
+F 0 "U1" H 16600 12550 30 0000 C CNN
+F 1 "PORT" H 16550 12450 30 0000 C CNN
+F 2 "" H 16550 12450 60 0000 C CNN
+F 3 "" H 16550 12450 60 0000 C CNN
+ 12 16550 12450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68681752
+P 26350 13550
+F 0 "U1" H 26400 13650 30 0000 C CNN
+F 1 "PORT" H 26350 13550 30 0000 C CNN
+F 2 "" H 26350 13550 60 0000 C CNN
+F 3 "" H 26350 13550 60 0000 C CNN
+ 11 26350 13550
+ -1 0 0 1
+$EndComp
+Connection ~ 25600 16500
+Wire Wire Line
+ 25700 16500 25700 14150
+Connection ~ 24000 16500
+Wire Wire Line
+ 24000 14050 24000 16500
+Connection ~ 20800 16500
+Wire Wire Line
+ 25600 16500 25600 14200
+Connection ~ 21400 10800
+Wire Wire Line
+ 21400 13300 21400 10800
+Connection ~ 18750 16500
+Wire Wire Line
+ 18750 13350 18750 16500
+Wire Wire Line
+ 18550 13350 18750 13350
+Wire Wire Line
+ 18550 13050 18550 13350
+Connection ~ 18700 16500
+Wire Wire Line
+ 18700 13400 18700 16500
+Wire Wire Line
+ 18450 13400 18700 13400
+Wire Wire Line
+ 18450 13100 18450 13400
+Connection ~ 18550 16500
+Wire Wire Line
+ 18200 16500 25700 16500
+Wire Wire Line
+ 20800 16500 20800 13600
+Wire Wire Line
+ 18550 15100 18550 16500
+Wire Wire Line
+ 18450 15150 18450 16500
+Connection ~ 19100 10800
+Wire Wire Line
+ 19100 13750 19100 10800
+Wire Wire Line
+ 18550 13750 19100 13750
+Wire Wire Line
+ 18550 13900 18550 13750
+Connection ~ 18950 10800
+Wire Wire Line
+ 18950 13650 18950 10800
+Wire Wire Line
+ 18450 13650 18950 13650
+Wire Wire Line
+ 18450 13850 18450 13650
+Connection ~ 18550 10800
+Wire Wire Line
+ 18550 11850 18550 10800
+Connection ~ 25600 11450
+Wire Wire Line
+ 25700 11450 25700 12950
+Connection ~ 24150 11450
+Wire Wire Line
+ 24150 12350 24150 11450
+Wire Wire Line
+ 24000 12350 24150 12350
+Wire Wire Line
+ 24000 12650 24000 12350
+Connection ~ 24000 11450
+Wire Wire Line
+ 24000 11700 24000 11450
+Connection ~ 23900 11450
+Wire Wire Line
+ 18450 10800 29150 10800
+Wire Wire Line
+ 18450 10750 18450 11800
+Connection ~ 17800 12450
+Wire Wire Line
+ 17800 12450 16800 12450
+Wire Wire Line
+ 17800 12900 18150 12900
+Wire Wire Line
+ 17800 12000 17800 12900
+Wire Wire Line
+ 18150 12000 17800 12000
+Connection ~ 25600 13550
+Wire Wire Line
+ 25600 13550 26100 13550
+Wire Wire Line
+ 25600 13800 25600 13300
+Wire Wire Line
+ 23900 10800 23900 11650
+Wire Wire Line
+ 23900 11450 25700 11450
+Wire Wire Line
+ 25600 12900 25600 11450
+Wire Wire Line
+ 23900 12050 23900 12600
+Connection ~ 22850 14500
+Wire Wire Line
+ 22850 11850 22850 14500
+Wire Wire Line
+ 23600 11850 22850 11850
+Connection ~ 21100 13950
+Connection ~ 24500 13450
+Wire Wire Line
+ 24500 14950 24500 13450
+Wire Wire Line
+ 21100 14950 24500 14950
+Wire Wire Line
+ 21100 13950 21100 14950
+Connection ~ 23900 13450
+Connection ~ 25050 13450
+Wire Wire Line
+ 23900 13450 25050 13450
+Wire Wire Line
+ 25050 14000 25300 14000
+Wire Wire Line
+ 25050 13100 25050 14000
+Wire Wire Line
+ 25300 13100 25050 13100
+Wire Wire Line
+ 23900 13000 23900 13700
+Connection ~ 17400 14500
+Wire Wire Line
+ 22050 13450 21800 13450
+Wire Wire Line
+ 22050 15350 22050 13450
+Wire Wire Line
+ 17400 15350 22050 15350
+Wire Wire Line
+ 17400 14500 17400 15350
+Connection ~ 17750 14500
+Wire Wire Line
+ 17750 14500 16700 14500
+Wire Wire Line
+ 17750 14950 18150 14950
+Wire Wire Line
+ 17750 14050 17750 14950
+Wire Wire Line
+ 18150 14050 17750 14050
+Connection ~ 19850 14500
+Wire Wire Line
+ 19850 13450 19850 14500
+Wire Wire Line
+ 20400 13450 19850 13450
+Connection ~ 18450 14500
+Wire Wire Line
+ 23900 14500 18450 14500
+Wire Wire Line
+ 23900 14100 23900 14500
+Wire Wire Line
+ 18450 14250 18450 14750
+Wire Wire Line
+ 21500 13950 21500 13650
+Wire Wire Line
+ 20700 13950 21500 13950
+Wire Wire Line
+ 20700 13650 20700 13950
+Connection ~ 21100 13100
+Connection ~ 21100 12450
+Wire Wire Line
+ 21100 13100 21100 12450
+Connection ~ 23300 13350
+Connection ~ 18450 12450
+Wire Wire Line
+ 22450 12450 18450 12450
+Wire Wire Line
+ 22450 13350 22450 12450
+Wire Wire Line
+ 23300 13350 22450 13350
+Wire Wire Line
+ 23300 13900 23600 13900
+Wire Wire Line
+ 23300 12800 23300 13900
+Wire Wire Line
+ 23600 12800 23300 12800
+Wire Wire Line
+ 21500 13100 21500 13250
+Wire Wire Line
+ 20700 13100 21500 13100
+Wire Wire Line
+ 20700 13250 20700 13100
+Wire Wire Line
+ 18450 12200 18450 12700
+Wire Wire Line
+ 18200 16450 18200 16500
+Connection ~ 18450 16500
+Connection ~ 13250 16450
+Wire Wire Line
+ 2350 7650 2350 16450
+Connection ~ 6000 16450
+Connection ~ 5300 7650
+Connection ~ 12550 7650
+Connection ~ 17750 7700
+Connection ~ 18450 10800
+Connection ~ 11450 10750
+Wire Wire Line
+ 29150 10800 29150 2000
+Connection ~ 23200 2000
+Connection ~ 23900 10800
+Connection ~ 10750 2000
+Connection ~ 17750 2000
+Wire Wire Line
+ 2350 12400 1900 12400
+Wire Wire Line
+ 1900 12400 1900 12350
+Connection ~ 2350 12400
+$Comp
+L PORT U1
+U 7 1 6868755F
+P 1650 12350
+F 0 "U1" H 1700 12450 30 0000 C CNN
+F 1 "PORT" H 1650 12350 30 0000 C CNN
+F 2 "" H 1650 12350 60 0000 C CNN
+F 3 "" H 1650 12350 60 0000 C CNN
+ 7 1650 12350
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B.sub b/library/SubcircuitLibrary/CD4030B/CD4030B.sub
new file mode 100644
index 000000000..54f53f3d5
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/CD4030B.sub
@@ -0,0 +1,52 @@
+* Subcircuit CD4030B
+.subckt CD4030B net-_m1-pad2_ net-_m11-pad2_ net-_m19-pad1_ net-_m41-pad1_ net-_m23-pad2_ net-_m24-pad2_ net-_m1-pad3_ net-_m5-pad2_ net-_m12-pad2_ net-_m21-pad1_ net-_m43-pad1_ net-_m27-pad2_ net-_m28-pad2_ net-_m11-pad4_
+* c:\fossee\esim\library\subcircuitlibrary\cd4030b\cd4030b.cir
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m4 net-_m13-pad3_ net-_m11-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m2 net-_m13-pad3_ net-_m11-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m9 net-_m1-pad1_ net-_m13-pad3_ net-_m11-pad1_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m11 net-_m11-pad1_ net-_m11-pad2_ net-_m1-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m14 net-_m14-pad1_ net-_m13-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m15 net-_m11-pad1_ net-_m1-pad1_ net-_m14-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m13 net-_m11-pad1_ net-_m1-pad1_ net-_m13-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m20 net-_m19-pad1_ net-_m11-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m19 net-_m19-pad1_ net-_m11-pad1_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m25 net-_m23-pad1_ net-_m23-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m23 net-_m23-pad1_ net-_m23-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m26 net-_m24-pad1_ net-_m24-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m24 net-_m24-pad1_ net-_m24-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m31 net-_m23-pad1_ net-_m24-pad1_ net-_m31-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m33 net-_m31-pad3_ net-_m24-pad2_ net-_m23-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m36 net-_m36-pad1_ net-_m24-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m37 net-_m31-pad3_ net-_m23-pad1_ net-_m36-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m35 net-_m31-pad3_ net-_m23-pad1_ net-_m24-pad1_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m42 net-_m41-pad1_ net-_m31-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m41 net-_m41-pad1_ net-_m31-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m7 net-_m10-pad1_ net-_m5-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m5 net-_m10-pad1_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m8 net-_m10-pad2_ net-_m12-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m6 net-_m10-pad2_ net-_m12-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m10-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m12 net-_m10-pad3_ net-_m12-pad2_ net-_m10-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m17 net-_m17-pad1_ net-_m10-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m18 net-_m10-pad3_ net-_m10-pad1_ net-_m17-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m16 net-_m10-pad3_ net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m22 net-_m21-pad1_ net-_m10-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m21 net-_m21-pad1_ net-_m10-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m29 net-_m27-pad1_ net-_m27-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m27 net-_m27-pad1_ net-_m27-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m30 net-_m28-pad1_ net-_m28-pad2_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m28 net-_m28-pad1_ net-_m28-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m32 net-_m27-pad1_ net-_m28-pad1_ net-_m32-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m34 net-_m32-pad3_ net-_m28-pad2_ net-_m27-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m39 net-_m39-pad1_ net-_m28-pad1_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m40 net-_m32-pad3_ net-_m27-pad1_ net-_m39-pad1_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m38 net-_m32-pad3_ net-_m27-pad1_ net-_m28-pad1_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+m44 net-_m43-pad1_ net-_m32-pad3_ net-_m11-pad4_ net-_m11-pad4_ mos_p W=40u L=5u M=8
+m43 net-_m43-pad1_ net-_m32-pad3_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=20u L=5u M=4
+* Control Statements
+
+.ends CD4030B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030B/CD4030B_Previous_Values.xml b/library/SubcircuitLibrary/CD4030B/CD4030B_Previous_Values.xml
new file mode 100644
index 000000000..6bffbd3a1
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/CD4030B_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4030B/NMOS-5um.lib b/library/SubcircuitLibrary/CD4030B/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/CD4030B/PMOS-5um.lib b/library/SubcircuitLibrary/CD4030B/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/CD4030B/analysis b/library/SubcircuitLibrary/CD4030B/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4030B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4042B/CD4042B-cache.lib b/library/SubcircuitLibrary/CD4042B/CD4042B-cache.lib
new file mode 100644
index 000000000..4d2471e33
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CD4042B-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# Quad_D_FF
+#
+DEF Quad_D_FF X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "Quad_D_FF" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -450 450 450 -450 0 1 0 N
+X D1 1 -650 250 200 R 50 50 1 1 I
+X En 2 -650 150 200 R 50 50 1 1 I
+X D2 3 -650 0 200 R 50 50 1 1 I
+X D3 4 -650 -150 200 R 50 50 1 1 I
+X D4 5 -650 -250 200 R 50 50 1 1 I
+X Gnd 6 -650 -350 200 R 50 50 1 1 I
+X Vdd 7 -650 350 200 R 50 50 1 1 I
+X out1 8 650 400 200 L 50 50 1 1 O
+X out2 9 650 300 200 L 50 50 1 1 O
+X out3 10 650 200 200 L 50 50 1 1 O
+X out4 11 650 100 200 L 50 50 1 1 O
+X out1Bar 12 650 -100 200 L 50 50 1 1 O
+X out2Bar 13 650 -200 200 L 50 50 1 1 O
+X out3Bar 14 650 -300 200 L 50 50 1 1 O
+X out4Bar 15 650 -400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# TG_D_Latch_ctrl
+#
+DEF TG_D_Latch_ctrl X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "TG_D_Latch_ctrl" -50 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -400 300 700 -350 0 1 0 N
+X clock 1 -600 200 200 R 50 50 1 1 I
+X polarity 2 -600 -250 200 R 50 50 1 1 I
+X Vdd 3 100 500 200 D 50 50 1 1 I
+X Gnd 4 100 -550 200 U 50 50 1 1 I
+X clock_out 5 900 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4042B/CD4042B.bak b/library/SubcircuitLibrary/CD4042B/CD4042B.bak
new file mode 100644
index 000000000..aee1a4a64
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CD4042B.bak
@@ -0,0 +1,310 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4042B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 6858406E
+P 8500 2650
+F 0 "scmode1" H 8500 2800 98 0000 C CNB
+F 1 "SKY130mode" H 8500 2550 118 0000 C CNB
+F 2 "" H 8500 2800 60 0001 C CNN
+F 3 "" H 8500 2800 60 0001 C CNN
+ 1 8500 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L Quad_D_FF X2
+U 1 1 685A4DC5
+P 5850 3150
+F 0 "X2" H 5850 3050 60 0000 C CNN
+F 1 "Quad_D_FF" H 5850 3150 60 0000 C CNN
+F 2 "" H 5850 3150 60 0001 C CNN
+F 3 "" H 5850 3150 60 0001 C CNN
+ 1 5850 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L TG_D_Latch_ctrl X1
+U 1 1 685A4EBA
+P 3800 3000
+F 0 "X1" H 3800 2900 60 0000 C CNN
+F 1 "TG_D_Latch_ctrl" H 3750 3000 60 0000 C CNN
+F 2 "" H 3800 3000 60 0001 C CNN
+F 3 "" H 3800 3000 60 0001 C CNN
+ 1 3800 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685A4FC2
+P 4700 2900
+F 0 "U1" H 4750 3000 30 0000 C CNN
+F 1 "PORT" H 4700 2900 30 0000 C CNN
+F 2 "" H 4700 2900 60 0000 C CNN
+F 3 "" H 4700 2900 60 0000 C CNN
+ 3 4700 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A5045
+P 4700 3150
+F 0 "U1" H 4750 3250 30 0000 C CNN
+F 1 "PORT" H 4700 3150 30 0000 C CNN
+F 2 "" H 4700 3150 60 0000 C CNN
+F 3 "" H 4700 3150 60 0000 C CNN
+ 4 4700 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685A5126
+P 4700 3300
+F 0 "U1" H 4750 3400 30 0000 C CNN
+F 1 "PORT" H 4700 3300 30 0000 C CNN
+F 2 "" H 4700 3300 60 0000 C CNN
+F 3 "" H 4700 3300 60 0000 C CNN
+ 5 4700 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685A52B7
+P 4700 3400
+F 0 "U1" H 4750 3500 30 0000 C CNN
+F 1 "PORT" H 4700 3400 30 0000 C CNN
+F 2 "" H 4700 3400 60 0000 C CNN
+F 3 "" H 4700 3400 60 0000 C CNN
+ 6 4700 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A5304
+P 2850 2800
+F 0 "U1" H 2900 2900 30 0000 C CNN
+F 1 "PORT" H 2850 2800 30 0000 C CNN
+F 2 "" H 2850 2800 60 0000 C CNN
+F 3 "" H 2850 2800 60 0000 C CNN
+ 1 2850 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685A5355
+P 2850 3250
+F 0 "U1" H 2900 3350 30 0000 C CNN
+F 1 "PORT" H 2850 3250 30 0000 C CNN
+F 2 "" H 2850 3250 60 0000 C CNN
+F 3 "" H 2850 3250 60 0000 C CNN
+ 2 2850 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685A53C8
+P 6850 2750
+F 0 "U1" H 6900 2850 30 0000 C CNN
+F 1 "PORT" H 6850 2750 30 0000 C CNN
+F 2 "" H 6850 2750 60 0000 C CNN
+F 3 "" H 6850 2750 60 0000 C CNN
+ 9 6850 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685A5409
+P 6850 2850
+F 0 "U1" H 6900 2950 30 0000 C CNN
+F 1 "PORT" H 6850 2850 30 0000 C CNN
+F 2 "" H 6850 2850 60 0000 C CNN
+F 3 "" H 6850 2850 60 0000 C CNN
+ 10 6850 2850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685A5480
+P 6850 2950
+F 0 "U1" H 6900 3050 30 0000 C CNN
+F 1 "PORT" H 6850 2950 30 0000 C CNN
+F 2 "" H 6850 2950 60 0000 C CNN
+F 3 "" H 6850 2950 60 0000 C CNN
+ 11 6850 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685A54E5
+P 6850 3050
+F 0 "U1" H 6900 3150 30 0000 C CNN
+F 1 "PORT" H 6850 3050 30 0000 C CNN
+F 2 "" H 6850 3050 60 0000 C CNN
+F 3 "" H 6850 3050 60 0000 C CNN
+ 12 6850 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685A5546
+P 6850 3250
+F 0 "U1" H 6900 3350 30 0000 C CNN
+F 1 "PORT" H 6850 3250 30 0000 C CNN
+F 2 "" H 6850 3250 60 0000 C CNN
+F 3 "" H 6850 3250 60 0000 C CNN
+ 13 6850 3250
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685A55BB
+P 6850 3350
+F 0 "U1" H 6900 3450 30 0000 C CNN
+F 1 "PORT" H 6850 3350 30 0000 C CNN
+F 2 "" H 6850 3350 60 0000 C CNN
+F 3 "" H 6850 3350 60 0000 C CNN
+ 14 6850 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 685A5620
+P 6850 3450
+F 0 "U1" H 6900 3550 30 0000 C CNN
+F 1 "PORT" H 6850 3450 30 0000 C CNN
+F 2 "" H 6850 3450 60 0000 C CNN
+F 3 "" H 6850 3450 60 0000 C CNN
+ 15 6850 3450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 685A569F
+P 6850 3550
+F 0 "U1" H 6900 3650 30 0000 C CNN
+F 1 "PORT" H 6850 3550 30 0000 C CNN
+F 2 "" H 6850 3550 60 0000 C CNN
+F 3 "" H 6850 3550 60 0000 C CNN
+ 16 6850 3550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685A5732
+P 5500 2650
+F 0 "U1" H 5550 2750 30 0000 C CNN
+F 1 "PORT" H 5500 2650 30 0000 C CNN
+F 2 "" H 5500 2650 60 0000 C CNN
+F 3 "" H 5500 2650 60 0000 C CNN
+ 7 5500 2650
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685A57C3
+P 5500 3650
+F 0 "U1" H 5550 3750 30 0000 C CNN
+F 1 "PORT" H 5500 3650 30 0000 C CNN
+F 2 "" H 5500 3650 60 0000 C CNN
+F 3 "" H 5500 3650 60 0000 C CNN
+ 8 5500 3650
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3900 2500 5200 2500
+Wire Wire Line
+ 5200 2500 5200 2800
+Wire Wire Line
+ 5250 2650 5200 2650
+Connection ~ 5200 2650
+Wire Wire Line
+ 3900 3550 5250 3550
+Wire Wire Line
+ 5200 3550 5200 3500
+Wire Wire Line
+ 5250 3550 5250 3650
+Connection ~ 5200 3550
+Wire Wire Line
+ 3100 3250 3200 3250
+Wire Wire Line
+ 3100 2800 3200 2800
+Wire Wire Line
+ 4700 3000 5200 3000
+Wire Wire Line
+ 4950 2900 5200 2900
+Wire Wire Line
+ 4950 3150 5200 3150
+Wire Wire Line
+ 4950 3300 5200 3300
+Wire Wire Line
+ 4950 3400 5200 3400
+Wire Wire Line
+ 6500 2750 6600 2750
+Wire Wire Line
+ 6500 2850 6600 2850
+Wire Wire Line
+ 6500 2950 6600 2950
+Wire Wire Line
+ 6500 3050 6600 3050
+Wire Wire Line
+ 6500 3250 6600 3250
+Wire Wire Line
+ 6500 3350 6600 3350
+Wire Wire Line
+ 6500 3450 6600 3450
+Wire Wire Line
+ 6500 3550 6600 3550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/CD4042B.cir b/library/SubcircuitLibrary/CD4042B/CD4042B.cir
new file mode 100644
index 000000000..bba6d2c0e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CD4042B.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CD4042B/CD4042B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 24 12:19:45 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+scmode1 SKY130mode
+X2 Net-_U1-Pad3_ Net-_X1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Quad_D_FF
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_X1-Pad5_ TG_D_Latch_ctrl
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/CD4042B.cir.out b/library/SubcircuitLibrary/CD4042B/CD4042B.cir.out
new file mode 100644
index 000000000..bfffe2325
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CD4042B.cir.out
@@ -0,0 +1,19 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cd4042b/cd4042b.cir
+
+.include Quad_D_FF.sub
+.include TG_D_Latch_ctrl.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* s c m o d e
+x2 net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ Quad_D_FF
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad8_ net-_x1-pad5_ TG_D_Latch_ctrl
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/CD4042B.pro b/library/SubcircuitLibrary/CD4042B/CD4042B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CD4042B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4042B/CD4042B.sch b/library/SubcircuitLibrary/CD4042B/CD4042B.sch
new file mode 100644
index 000000000..5caabd205
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CD4042B.sch
@@ -0,0 +1,310 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4042B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 6858406E
+P 4550 4100
+F 0 "scmode1" H 4550 4250 98 0000 C CNB
+F 1 "SKY130mode" H 4550 4000 118 0000 C CNB
+F 2 "" H 4550 4250 60 0001 C CNN
+F 3 "" H 4550 4250 60 0001 C CNN
+ 1 4550 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Quad_D_FF X2
+U 1 1 685A4DC5
+P 5850 3150
+F 0 "X2" H 5850 3050 60 0000 C CNN
+F 1 "Quad_D_FF" H 5850 3150 60 0000 C CNN
+F 2 "" H 5850 3150 60 0001 C CNN
+F 3 "" H 5850 3150 60 0001 C CNN
+ 1 5850 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L TG_D_Latch_ctrl X1
+U 1 1 685A4EBA
+P 3800 3000
+F 0 "X1" H 3800 2900 60 0000 C CNN
+F 1 "TG_D_Latch_ctrl" H 3750 3000 60 0000 C CNN
+F 2 "" H 3800 3000 60 0001 C CNN
+F 3 "" H 3800 3000 60 0001 C CNN
+ 1 3800 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685A4FC2
+P 4700 2900
+F 0 "U1" H 4750 3000 30 0000 C CNN
+F 1 "PORT" H 4700 2900 30 0000 C CNN
+F 2 "" H 4700 2900 60 0000 C CNN
+F 3 "" H 4700 2900 60 0000 C CNN
+ 3 4700 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A5045
+P 4700 3150
+F 0 "U1" H 4750 3250 30 0000 C CNN
+F 1 "PORT" H 4700 3150 30 0000 C CNN
+F 2 "" H 4700 3150 60 0000 C CNN
+F 3 "" H 4700 3150 60 0000 C CNN
+ 4 4700 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685A5126
+P 4700 3300
+F 0 "U1" H 4750 3400 30 0000 C CNN
+F 1 "PORT" H 4700 3300 30 0000 C CNN
+F 2 "" H 4700 3300 60 0000 C CNN
+F 3 "" H 4700 3300 60 0000 C CNN
+ 5 4700 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685A52B7
+P 4700 3400
+F 0 "U1" H 4750 3500 30 0000 C CNN
+F 1 "PORT" H 4700 3400 30 0000 C CNN
+F 2 "" H 4700 3400 60 0000 C CNN
+F 3 "" H 4700 3400 60 0000 C CNN
+ 6 4700 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A5304
+P 2850 2800
+F 0 "U1" H 2900 2900 30 0000 C CNN
+F 1 "PORT" H 2850 2800 30 0000 C CNN
+F 2 "" H 2850 2800 60 0000 C CNN
+F 3 "" H 2850 2800 60 0000 C CNN
+ 1 2850 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685A5355
+P 2850 3250
+F 0 "U1" H 2900 3350 30 0000 C CNN
+F 1 "PORT" H 2850 3250 30 0000 C CNN
+F 2 "" H 2850 3250 60 0000 C CNN
+F 3 "" H 2850 3250 60 0000 C CNN
+ 2 2850 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685A53C8
+P 6850 2750
+F 0 "U1" H 6900 2850 30 0000 C CNN
+F 1 "PORT" H 6850 2750 30 0000 C CNN
+F 2 "" H 6850 2750 60 0000 C CNN
+F 3 "" H 6850 2750 60 0000 C CNN
+ 9 6850 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685A5409
+P 6850 2850
+F 0 "U1" H 6900 2950 30 0000 C CNN
+F 1 "PORT" H 6850 2850 30 0000 C CNN
+F 2 "" H 6850 2850 60 0000 C CNN
+F 3 "" H 6850 2850 60 0000 C CNN
+ 10 6850 2850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685A5480
+P 6850 2950
+F 0 "U1" H 6900 3050 30 0000 C CNN
+F 1 "PORT" H 6850 2950 30 0000 C CNN
+F 2 "" H 6850 2950 60 0000 C CNN
+F 3 "" H 6850 2950 60 0000 C CNN
+ 11 6850 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685A54E5
+P 6850 3050
+F 0 "U1" H 6900 3150 30 0000 C CNN
+F 1 "PORT" H 6850 3050 30 0000 C CNN
+F 2 "" H 6850 3050 60 0000 C CNN
+F 3 "" H 6850 3050 60 0000 C CNN
+ 12 6850 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685A5546
+P 6850 3250
+F 0 "U1" H 6900 3350 30 0000 C CNN
+F 1 "PORT" H 6850 3250 30 0000 C CNN
+F 2 "" H 6850 3250 60 0000 C CNN
+F 3 "" H 6850 3250 60 0000 C CNN
+ 13 6850 3250
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685A55BB
+P 6850 3350
+F 0 "U1" H 6900 3450 30 0000 C CNN
+F 1 "PORT" H 6850 3350 30 0000 C CNN
+F 2 "" H 6850 3350 60 0000 C CNN
+F 3 "" H 6850 3350 60 0000 C CNN
+ 14 6850 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 685A5620
+P 6850 3450
+F 0 "U1" H 6900 3550 30 0000 C CNN
+F 1 "PORT" H 6850 3450 30 0000 C CNN
+F 2 "" H 6850 3450 60 0000 C CNN
+F 3 "" H 6850 3450 60 0000 C CNN
+ 15 6850 3450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 685A569F
+P 6850 3550
+F 0 "U1" H 6900 3650 30 0000 C CNN
+F 1 "PORT" H 6850 3550 30 0000 C CNN
+F 2 "" H 6850 3550 60 0000 C CNN
+F 3 "" H 6850 3550 60 0000 C CNN
+ 16 6850 3550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685A5732
+P 5500 2650
+F 0 "U1" H 5550 2750 30 0000 C CNN
+F 1 "PORT" H 5500 2650 30 0000 C CNN
+F 2 "" H 5500 2650 60 0000 C CNN
+F 3 "" H 5500 2650 60 0000 C CNN
+ 7 5500 2650
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685A57C3
+P 5500 3650
+F 0 "U1" H 5550 3750 30 0000 C CNN
+F 1 "PORT" H 5500 3650 30 0000 C CNN
+F 2 "" H 5500 3650 60 0000 C CNN
+F 3 "" H 5500 3650 60 0000 C CNN
+ 8 5500 3650
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3900 2500 5200 2500
+Wire Wire Line
+ 5200 2500 5200 2800
+Wire Wire Line
+ 5250 2650 5200 2650
+Connection ~ 5200 2650
+Wire Wire Line
+ 3900 3550 5250 3550
+Wire Wire Line
+ 5200 3550 5200 3500
+Wire Wire Line
+ 5250 3550 5250 3650
+Connection ~ 5200 3550
+Wire Wire Line
+ 3100 3250 3200 3250
+Wire Wire Line
+ 3100 2800 3200 2800
+Wire Wire Line
+ 4700 3000 5200 3000
+Wire Wire Line
+ 4950 2900 5200 2900
+Wire Wire Line
+ 4950 3150 5200 3150
+Wire Wire Line
+ 4950 3300 5200 3300
+Wire Wire Line
+ 4950 3400 5200 3400
+Wire Wire Line
+ 6500 2750 6600 2750
+Wire Wire Line
+ 6500 2850 6600 2850
+Wire Wire Line
+ 6500 2950 6600 2950
+Wire Wire Line
+ 6500 3050 6600 3050
+Wire Wire Line
+ 6500 3250 6600 3250
+Wire Wire Line
+ 6500 3350 6600 3350
+Wire Wire Line
+ 6500 3450 6600 3450
+Wire Wire Line
+ 6500 3550 6600 3550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/CD4042B.sub b/library/SubcircuitLibrary/CD4042B/CD4042B.sub
new file mode 100644
index 000000000..122ce9940
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CD4042B.sub
@@ -0,0 +1,13 @@
+* Subcircuit CD4042B
+.subckt CD4042B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cd4042b/cd4042b.cir
+.include Quad_D_FF.sub
+.include TG_D_Latch_ctrl.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* s c m o d e
+x2 net-_u1-pad3_ net-_x1-pad5_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ Quad_D_FF
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad8_ net-_x1-pad5_ TG_D_Latch_ctrl
+* Control Statements
+
+.ends CD4042B
diff --git a/library/SubcircuitLibrary/CD4042B/CD4042B_Previous_Values.xml b/library/SubcircuitLibrary/CD4042B/CD4042B_Previous_Values.xml
new file mode 100644
index 000000000..cb3fbc0d4
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CD4042B_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Quad_D_FF/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/TG_D_Latch_ctrltruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4042B/CMOS_INVTR-cache.lib b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.cir b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.cir
new file mode 100644
index 000000000..d2199ddbb
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/CMOS_INVTR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 13 08:49:20 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.cir.out b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.cir.out
new file mode 100644
index 000000000..dec1c5fa5
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.pro b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.sch b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.sch
new file mode 100644
index 000000000..aa7a7ee81
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.sch
@@ -0,0 +1,161 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 684B982F
+P 5350 2950
+F 0 "SC1" H 5400 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 3037 50 0000 R CNN
+F 2 "" H 5350 1450 50 0001 C CNN
+F 3 "" H 5350 2950 50 0001 C CNN
+ 1 5350 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684B9856
+P 5350 3800
+F 0 "SC2" H 5400 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5650 3887 50 0000 R CNN
+F 2 "" H 5350 2300 50 0001 C CNN
+F 3 "" H 5350 3800 50 0001 C CNN
+ 1 5350 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B98AD
+P 4550 3300
+F 0 "U1" H 4600 3400 30 0000 C CNN
+F 1 "PORT" H 4550 3300 30 0000 C CNN
+F 2 "" H 4550 3300 60 0000 C CNN
+F 3 "" H 4550 3300 60 0000 C CNN
+ 1 4550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B98D8
+P 6300 3350
+F 0 "U1" H 6350 3450 30 0000 C CNN
+F 1 "PORT" H 6300 3350 30 0000 C CNN
+F 2 "" H 6300 3350 60 0000 C CNN
+F 3 "" H 6300 3350 60 0000 C CNN
+ 4 6300 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B9935
+P 5300 4350
+F 0 "U1" H 5350 4450 30 0000 C CNN
+F 1 "PORT" H 5300 4350 30 0000 C CNN
+F 2 "" H 5300 4350 60 0000 C CNN
+F 3 "" H 5300 4350 60 0000 C CNN
+ 3 5300 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B999A
+P 5300 2350
+F 0 "U1" H 5350 2450 30 0000 C CNN
+F 1 "PORT" H 5300 2350 30 0000 C CNN
+F 2 "" H 5300 2350 60 0000 C CNN
+F 3 "" H 5300 2350 60 0000 C CNN
+ 2 5300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B99CD
+P 7950 3000
+F 0 "scmode1" H 7950 3150 98 0000 C CNB
+F 1 "SKY130mode" H 7950 2900 118 0000 C CNB
+F 2 "" H 7950 3150 60 0001 C CNN
+F 3 "" H 7950 3150 60 0001 C CNN
+ 1 7950 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 2650 5550 2350
+Wire Wire Line
+ 5450 2950 5600 2950
+Wire Wire Line
+ 5600 2950 5600 2550
+Wire Wire Line
+ 5600 2550 5550 2550
+Connection ~ 5550 2550
+Wire Wire Line
+ 5550 3250 5550 3500
+Wire Wire Line
+ 6050 3350 5550 3350
+Connection ~ 5550 3350
+Wire Wire Line
+ 5050 2950 5050 3800
+Wire Wire Line
+ 4800 3300 5050 3300
+Connection ~ 5050 3300
+Wire Wire Line
+ 5450 3800 5600 3800
+Wire Wire Line
+ 5600 3800 5600 4150
+Wire Wire Line
+ 5600 4150 5550 4150
+Wire Wire Line
+ 5550 4100 5550 4350
+Connection ~ 5550 4150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.sub b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.sub
new file mode 100644
index 000000000..8283bca86
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR.sub
@@ -0,0 +1,11 @@
+* Subcircuit CMOS_INVTR
+.subckt CMOS_INVTR net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends CMOS_INVTR
diff --git a/library/SubcircuitLibrary/CD4042B/CMOS_INVTR_Previous_Values.xml b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR_Previous_Values.xml
new file mode 100644
index 000000000..d17c4f93e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/CMOS_INVTR_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3, l=0.15w=1, l=0.15
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4042B/D_FF-cache.lib b/library/SubcircuitLibrary/CD4042B/D_FF-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/D_FF-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4042B/D_FF.bak b/library/SubcircuitLibrary/CD4042B/D_FF.bak
new file mode 100644
index 000000000..61b02ff48
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/D_FF.bak
@@ -0,0 +1,246 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode?
+U 1 1 685A3E76
+P 9400 3200
+F 0 "scmode?" H 9400 3350 98 0000 C CNB
+F 1 "SKY130mode" H 9400 3100 118 0000 C CNB
+F 2 "" H 9400 3350 60 0001 C CNN
+F 3 "" H 9400 3350 60 0001 C CNN
+ 1 9400 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC?
+U 1 1 685A3EBD
+P 4000 3300
+F 0 "SC?" H 4050 3600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 3387 50 0000 R CNN
+F 2 "" H 4000 1800 50 0001 C CNN
+F 3 "" H 4000 3300 50 0001 C CNN
+ 1 4000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3EFC
+P 4000 4100
+F 0 "SC?" H 4050 4400 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4187 50 0000 R CNN
+F 2 "" H 4000 2600 50 0001 C CNN
+F 3 "" H 4000 4100 50 0001 C CNN
+ 1 4000 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3F47
+P 4000 4900
+F 0 "SC?" H 4050 5200 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4987 50 0000 R CNN
+F 2 "" H 4000 3400 50 0001 C CNN
+F 3 "" H 4000 4900 50 0001 C CNN
+ 1 4000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC?
+U 1 1 685A3F7A
+P 4950 3700
+F 0 "SC?" H 5000 4000 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5250 3787 50 0000 R CNN
+F 2 "" H 4950 2200 50 0001 C CNN
+F 3 "" H 4950 3700 50 0001 C CNN
+ 1 4950 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3FCF
+P 4950 4500
+F 0 "SC?" H 5000 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5250 4587 50 0000 R CNN
+F 2 "" H 4950 3000 50 0001 C CNN
+F 3 "" H 4950 4500 50 0001 C CNN
+ 1 4950 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 1 1 685A401A
+P 3250 3550
+F 0 "U?" H 3300 3650 30 0000 C CNN
+F 1 "PORT" H 3250 3550 30 0000 C CNN
+F 2 "" H 3250 3550 60 0000 C CNN
+F 3 "" H 3250 3550 60 0000 C CNN
+ 1 3250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 2 1 685A40FF
+P 3250 4100
+F 0 "U?" H 3300 4200 30 0000 C CNN
+F 1 "PORT" H 3250 4100 30 0000 C CNN
+F 2 "" H 3250 4100 60 0000 C CNN
+F 3 "" H 3250 4100 60 0000 C CNN
+ 2 3250 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 3 1 685A4132
+P 3950 2750
+F 0 "U?" H 4000 2850 30 0000 C CNN
+F 1 "PORT" H 3950 2750 30 0000 C CNN
+F 2 "" H 3950 2750 60 0000 C CNN
+F 3 "" H 3950 2750 60 0000 C CNN
+ 3 3950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 4 1 685A41B1
+P 3950 5350
+F 0 "U?" H 4000 5450 30 0000 C CNN
+F 1 "PORT" H 3950 5350 30 0000 C CNN
+F 2 "" H 3950 5350 60 0000 C CNN
+F 3 "" H 3950 5350 60 0000 C CNN
+ 4 3950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 5 1 685A4206
+P 5700 4100
+F 0 "U?" H 5750 4200 30 0000 C CNN
+F 1 "PORT" H 5700 4100 30 0000 C CNN
+F 2 "" H 5700 4100 60 0000 C CNN
+F 3 "" H 5700 4100 60 0000 C CNN
+ 5 5700 4100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4200 3600 4200 3800
+Wire Wire Line
+ 3700 3300 3600 3300
+Wire Wire Line
+ 3600 3300 3600 4900
+Wire Wire Line
+ 3600 4900 3700 4900
+Wire Wire Line
+ 3500 3550 3600 3550
+Connection ~ 3600 3550
+Wire Wire Line
+ 3500 4100 3700 4100
+Wire Wire Line
+ 4200 2750 4200 3000
+Wire Wire Line
+ 4650 3700 4200 3700
+Connection ~ 4200 3700
+Wire Wire Line
+ 4200 4400 4200 4600
+Wire Wire Line
+ 4650 4500 4200 4500
+Connection ~ 4200 4500
+Wire Wire Line
+ 5150 4000 5150 4200
+Wire Wire Line
+ 5450 4100 5150 4100
+Connection ~ 5150 4100
+Wire Wire Line
+ 4200 5200 4200 5350
+Wire Wire Line
+ 4100 4900 4250 4900
+Wire Wire Line
+ 4250 4900 4250 5250
+Wire Wire Line
+ 4200 5250 5150 5250
+Connection ~ 4200 5250
+Wire Wire Line
+ 5150 5250 5150 4800
+Connection ~ 4250 5250
+Wire Wire Line
+ 5050 4500 5200 4500
+Wire Wire Line
+ 5200 4500 5200 4850
+Wire Wire Line
+ 5200 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 4100 4100 4250 4100
+Wire Wire Line
+ 4250 4100 4250 4500
+Connection ~ 4250 4500
+Wire Wire Line
+ 4100 3300 4250 3300
+Wire Wire Line
+ 4250 3300 4250 2950
+Wire Wire Line
+ 4200 2950 5150 2950
+Connection ~ 4200 2950
+Wire Wire Line
+ 5150 2950 5150 3400
+Connection ~ 4250 2950
+Wire Wire Line
+ 5050 3700 5200 3700
+Wire Wire Line
+ 5200 3700 5200 3350
+Wire Wire Line
+ 5200 3350 5150 3350
+Connection ~ 5150 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/D_FF.cir b/library/SubcircuitLibrary/CD4042B/D_FF.cir
new file mode 100644
index 000000000..63d882276
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/D_FF.cir
@@ -0,0 +1,17 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_FF/D_FF.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 24 11:33:09 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+scmode1 SKY130mode
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+SC3 Net-_SC2-Pad3_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC4-Pad1_ Net-_SC1-Pad1_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC5 Net-_SC4-Pad1_ Net-_SC2-Pad3_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC3-Pad3_ Net-_SC4-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/D_FF.cir.out b/library/SubcircuitLibrary/CD4042B/D_FF.cir.out
new file mode 100644
index 000000000..ea0830808
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/D_FF.cir.out
@@ -0,0 +1,20 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/d_ff/d_ff.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* s c m o d e
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc2-pad3_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc4-pad1_ net-_sc2-pad3_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc4-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/D_FF.pro b/library/SubcircuitLibrary/CD4042B/D_FF.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/D_FF.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4042B/D_FF.sch b/library/SubcircuitLibrary/CD4042B/D_FF.sch
new file mode 100644
index 000000000..722069493
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/D_FF.sch
@@ -0,0 +1,246 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 685A3E76
+P 9400 3200
+F 0 "scmode1" H 9400 3350 98 0000 C CNB
+F 1 "SKY130mode" H 9400 3100 118 0000 C CNB
+F 2 "" H 9400 3350 60 0001 C CNN
+F 3 "" H 9400 3350 60 0001 C CNN
+ 1 9400 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 685A3EBD
+P 4000 3300
+F 0 "SC1" H 4050 3600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 3387 50 0000 R CNN
+F 2 "" H 4000 1800 50 0001 C CNN
+F 3 "" H 4000 3300 50 0001 C CNN
+ 1 4000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 685A3EFC
+P 4000 4100
+F 0 "SC2" H 4050 4400 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4187 50 0000 R CNN
+F 2 "" H 4000 2600 50 0001 C CNN
+F 3 "" H 4000 4100 50 0001 C CNN
+ 1 4000 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 685A3F47
+P 4000 4900
+F 0 "SC3" H 4050 5200 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4987 50 0000 R CNN
+F 2 "" H 4000 3400 50 0001 C CNN
+F 3 "" H 4000 4900 50 0001 C CNN
+ 1 4000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 685A3F7A
+P 4950 3700
+F 0 "SC4" H 5000 4000 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5250 3787 50 0000 R CNN
+F 2 "" H 4950 2200 50 0001 C CNN
+F 3 "" H 4950 3700 50 0001 C CNN
+ 1 4950 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 685A3FCF
+P 4950 4500
+F 0 "SC5" H 5000 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5250 4587 50 0000 R CNN
+F 2 "" H 4950 3000 50 0001 C CNN
+F 3 "" H 4950 4500 50 0001 C CNN
+ 1 4950 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A401A
+P 3250 3550
+F 0 "U1" H 3300 3650 30 0000 C CNN
+F 1 "PORT" H 3250 3550 30 0000 C CNN
+F 2 "" H 3250 3550 60 0000 C CNN
+F 3 "" H 3250 3550 60 0000 C CNN
+ 1 3250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685A40FF
+P 3250 4100
+F 0 "U1" H 3300 4200 30 0000 C CNN
+F 1 "PORT" H 3250 4100 30 0000 C CNN
+F 2 "" H 3250 4100 60 0000 C CNN
+F 3 "" H 3250 4100 60 0000 C CNN
+ 2 3250 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685A4132
+P 3950 2750
+F 0 "U1" H 4000 2850 30 0000 C CNN
+F 1 "PORT" H 3950 2750 30 0000 C CNN
+F 2 "" H 3950 2750 60 0000 C CNN
+F 3 "" H 3950 2750 60 0000 C CNN
+ 3 3950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A41B1
+P 3950 5350
+F 0 "U1" H 4000 5450 30 0000 C CNN
+F 1 "PORT" H 3950 5350 30 0000 C CNN
+F 2 "" H 3950 5350 60 0000 C CNN
+F 3 "" H 3950 5350 60 0000 C CNN
+ 4 3950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685A4206
+P 5700 4100
+F 0 "U1" H 5750 4200 30 0000 C CNN
+F 1 "PORT" H 5700 4100 30 0000 C CNN
+F 2 "" H 5700 4100 60 0000 C CNN
+F 3 "" H 5700 4100 60 0000 C CNN
+ 5 5700 4100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4200 3600 4200 3800
+Wire Wire Line
+ 3700 3300 3600 3300
+Wire Wire Line
+ 3600 3300 3600 4900
+Wire Wire Line
+ 3600 4900 3700 4900
+Wire Wire Line
+ 3500 3550 3600 3550
+Connection ~ 3600 3550
+Wire Wire Line
+ 3500 4100 3700 4100
+Wire Wire Line
+ 4200 2750 4200 3000
+Wire Wire Line
+ 4650 3700 4200 3700
+Connection ~ 4200 3700
+Wire Wire Line
+ 4200 4400 4200 4600
+Wire Wire Line
+ 4650 4500 4200 4500
+Connection ~ 4200 4500
+Wire Wire Line
+ 5150 4000 5150 4200
+Wire Wire Line
+ 5450 4100 5150 4100
+Connection ~ 5150 4100
+Wire Wire Line
+ 4200 5200 4200 5350
+Wire Wire Line
+ 4100 4900 4250 4900
+Wire Wire Line
+ 4250 4900 4250 5250
+Wire Wire Line
+ 4200 5250 5150 5250
+Connection ~ 4200 5250
+Wire Wire Line
+ 5150 5250 5150 4800
+Connection ~ 4250 5250
+Wire Wire Line
+ 5050 4500 5200 4500
+Wire Wire Line
+ 5200 4500 5200 4850
+Wire Wire Line
+ 5200 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 4100 4100 4250 4100
+Wire Wire Line
+ 4250 4100 4250 4500
+Connection ~ 4250 4500
+Wire Wire Line
+ 4100 3300 4250 3300
+Wire Wire Line
+ 4250 3300 4250 2950
+Wire Wire Line
+ 4200 2950 5150 2950
+Connection ~ 4200 2950
+Wire Wire Line
+ 5150 2950 5150 3400
+Connection ~ 4250 2950
+Wire Wire Line
+ 5050 3700 5200 3700
+Wire Wire Line
+ 5200 3700 5200 3350
+Wire Wire Line
+ 5200 3350 5150 3350
+Connection ~ 5150 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/D_FF.sub b/library/SubcircuitLibrary/CD4042B/D_FF.sub
new file mode 100644
index 000000000..80c6b5838
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/D_FF.sub
@@ -0,0 +1,15 @@
+* Subcircuit D_FF
+.subckt D_FF net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc4-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/d_ff/d_ff.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* s c m o d e
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc2-pad3_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc4-pad1_ net-_sc2-pad3_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends D_FF
diff --git a/library/SubcircuitLibrary/CD4042B/D_FF_Previous_Values.xml b/library/SubcircuitLibrary/CD4042B/D_FF_Previous_Values.xml
new file mode 100644
index 000000000..47ed32dc1
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/D_FF_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=1 l=0.15
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4042B/Quad_D_FF-cache.lib b/library/SubcircuitLibrary/CD4042B/Quad_D_FF-cache.lib
new file mode 100644
index 000000000..551ed8796
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/Quad_D_FF-cache.lib
@@ -0,0 +1,91 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 100 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -450 250 500 0 N
+P 3 0 1 0 -450 250 -450 -250 500 0 N
+X IN 1 -650 0 200 R 50 50 1 1 I
+X VDD 2 -650 150 200 R 50 50 1 1 I
+X GND 3 -650 -150 200 R 50 50 1 1 I
+X OUT 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# D_FF
+#
+DEF D_FF X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "D_FF" -150 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -250 250 250 -250 0 1 0 N
+X D 1 -450 150 200 R 50 50 1 1 I
+X En 2 -450 -150 200 R 50 50 1 1 I
+X Vdd 3 0 450 200 D 50 50 1 1 I
+X Gnd 4 0 -450 200 U 50 50 1 1 I
+X Out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4042B/Quad_D_FF.bak b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.bak
new file mode 100644
index 000000000..2cc300534
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.bak
@@ -0,0 +1,426 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L D_FF X1
+U 1 1 685A4330
+P 5000 2000
+F 0 "X1" H 5000 2000 60 0000 C CNN
+F 1 "D_FF" H 4850 2000 60 0000 C CNN
+F 2 "" H 5000 2000 60 0001 C CNN
+F 3 "" H 5000 2000 60 0001 C CNN
+ 1 5000 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X2
+U 1 1 685A43B2
+P 5000 3100
+F 0 "X2" H 5000 3100 60 0000 C CNN
+F 1 "D_FF" H 4850 3100 60 0000 C CNN
+F 2 "" H 5000 3100 60 0001 C CNN
+F 3 "" H 5000 3100 60 0001 C CNN
+ 1 5000 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X3
+U 1 1 685A442D
+P 5000 4150
+F 0 "X3" H 5000 4150 60 0000 C CNN
+F 1 "D_FF" H 4850 4150 60 0000 C CNN
+F 2 "" H 5000 4150 60 0001 C CNN
+F 3 "" H 5000 4150 60 0001 C CNN
+ 1 5000 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X4
+U 1 1 685A44A2
+P 5000 5250
+F 0 "X4" H 5000 5250 60 0000 C CNN
+F 1 "D_FF" H 4850 5250 60 0000 C CNN
+F 2 "" H 5000 5250 60 0001 C CNN
+F 3 "" H 5000 5250 60 0001 C CNN
+ 1 5000 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X5
+U 1 1 685A4627
+P 6250 2550
+F 0 "X5" H 6250 2550 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6350 2300 60 0000 C CNN
+F 2 "" H 6250 2550 60 0001 C CNN
+F 3 "" H 6250 2550 60 0001 C CNN
+ 1 6250 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X6
+U 1 1 685A4674
+P 6250 3650
+F 0 "X6" H 6250 3650 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6350 3400 60 0000 C CNN
+F 2 "" H 6250 3650 60 0001 C CNN
+F 3 "" H 6250 3650 60 0001 C CNN
+ 1 6250 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X7
+U 1 1 685A4791
+P 6250 4700
+F 0 "X7" H 6250 4700 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6350 4450 60 0000 C CNN
+F 2 "" H 6250 4700 60 0001 C CNN
+F 3 "" H 6250 4700 60 0001 C CNN
+ 1 6250 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X8
+U 1 1 685A47E6
+P 6250 5800
+F 0 "X8" H 6250 5800 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6350 5550 60 0000 C CNN
+F 2 "" H 6250 5800 60 0001 C CNN
+F 3 "" H 6250 5800 60 0001 C CNN
+ 1 6250 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A4895
+P 3850 1850
+F 0 "U1" H 3900 1950 30 0000 C CNN
+F 1 "PORT" H 3850 1850 30 0000 C CNN
+F 2 "" H 3850 1850 60 0000 C CNN
+F 3 "" H 3850 1850 60 0000 C CNN
+ 1 3850 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685A492A
+P 3850 2950
+F 0 "U1" H 3900 3050 30 0000 C CNN
+F 1 "PORT" H 3850 2950 30 0000 C CNN
+F 2 "" H 3850 2950 60 0000 C CNN
+F 3 "" H 3850 2950 60 0000 C CNN
+ 3 3850 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A4A37
+P 3850 4000
+F 0 "U1" H 3900 4100 30 0000 C CNN
+F 1 "PORT" H 3850 4000 30 0000 C CNN
+F 2 "" H 3850 4000 60 0000 C CNN
+F 3 "" H 3850 4000 60 0000 C CNN
+ 4 3850 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685A4B10
+P 3850 5100
+F 0 "U1" H 3900 5200 30 0000 C CNN
+F 1 "PORT" H 3850 5100 30 0000 C CNN
+F 2 "" H 3850 5100 60 0000 C CNN
+F 3 "" H 3850 5100 60 0000 C CNN
+ 5 3850 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685A4BE5
+P 6050 2000
+F 0 "U1" H 6100 2100 30 0000 C CNN
+F 1 "PORT" H 6050 2000 30 0000 C CNN
+F 2 "" H 6050 2000 60 0000 C CNN
+F 3 "" H 6050 2000 60 0000 C CNN
+ 8 6050 2000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685A4CBA
+P 7350 2550
+F 0 "U1" H 7400 2650 30 0000 C CNN
+F 1 "PORT" H 7350 2550 30 0000 C CNN
+F 2 "" H 7350 2550 60 0000 C CNN
+F 3 "" H 7350 2550 60 0000 C CNN
+ 12 7350 2550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685A4D33
+P 6050 3100
+F 0 "U1" H 6100 3200 30 0000 C CNN
+F 1 "PORT" H 6050 3100 30 0000 C CNN
+F 2 "" H 6050 3100 60 0000 C CNN
+F 3 "" H 6050 3100 60 0000 C CNN
+ 9 6050 3100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685A4DBE
+P 7400 3650
+F 0 "U1" H 7450 3750 30 0000 C CNN
+F 1 "PORT" H 7400 3650 30 0000 C CNN
+F 2 "" H 7400 3650 60 0000 C CNN
+F 3 "" H 7400 3650 60 0000 C CNN
+ 13 7400 3650
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685A4EC7
+P 6050 4150
+F 0 "U1" H 6100 4250 30 0000 C CNN
+F 1 "PORT" H 6050 4150 30 0000 C CNN
+F 2 "" H 6050 4150 60 0000 C CNN
+F 3 "" H 6050 4150 60 0000 C CNN
+ 10 6050 4150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685A4F44
+P 7400 4700
+F 0 "U1" H 7450 4800 30 0000 C CNN
+F 1 "PORT" H 7400 4700 30 0000 C CNN
+F 2 "" H 7400 4700 60 0000 C CNN
+F 3 "" H 7400 4700 60 0000 C CNN
+ 14 7400 4700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685A5115
+P 6050 5250
+F 0 "U1" H 6100 5350 30 0000 C CNN
+F 1 "PORT" H 6050 5250 30 0000 C CNN
+F 2 "" H 6050 5250 60 0000 C CNN
+F 3 "" H 6050 5250 60 0000 C CNN
+ 11 6050 5250
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 685A52B2
+P 7400 5800
+F 0 "U1" H 7450 5900 30 0000 C CNN
+F 1 "PORT" H 7400 5800 30 0000 C CNN
+F 2 "" H 7400 5800 60 0000 C CNN
+F 3 "" H 7400 5800 60 0000 C CNN
+ 15 7400 5800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685A53F3
+P 4750 1350
+F 0 "U1" H 4800 1450 30 0000 C CNN
+F 1 "PORT" H 4750 1350 30 0000 C CNN
+F 2 "" H 4750 1350 60 0000 C CNN
+F 3 "" H 4750 1350 60 0000 C CNN
+ 7 4750 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685A5583
+P 4700 5950
+F 0 "U1" H 4750 6050 30 0000 C CNN
+F 1 "PORT" H 4700 5950 30 0000 C CNN
+F 2 "" H 4700 5950 60 0000 C CNN
+F 3 "" H 4700 5950 60 0000 C CNN
+ 6 4700 5950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 1350 5000 1550
+Wire Wire Line
+ 5000 1500 5200 1500
+Wire Wire Line
+ 5200 1500 5200 5650
+Wire Wire Line
+ 5200 5650 5600 5650
+Wire Wire Line
+ 5000 4800 5200 4800
+Connection ~ 5200 4800
+Wire Wire Line
+ 5600 4550 5200 4550
+Connection ~ 5200 4550
+Wire Wire Line
+ 5000 3700 5200 3700
+Connection ~ 5200 3700
+Wire Wire Line
+ 5600 3500 5200 3500
+Connection ~ 5200 3500
+Wire Wire Line
+ 5000 2650 5200 2650
+Connection ~ 5200 2650
+Wire Wire Line
+ 5600 2400 5200 2400
+Connection ~ 5200 2400
+Connection ~ 5000 1500
+Wire Wire Line
+ 4950 5950 5600 5950
+Wire Wire Line
+ 5150 5950 5150 2450
+Wire Wire Line
+ 5150 2450 5000 2450
+Wire Wire Line
+ 5600 2700 5150 2700
+Connection ~ 5150 2700
+Wire Wire Line
+ 5000 3550 5150 3550
+Connection ~ 5150 3550
+Wire Wire Line
+ 5600 3800 5150 3800
+Connection ~ 5150 3800
+Wire Wire Line
+ 5000 4600 5150 4600
+Connection ~ 5150 4600
+Wire Wire Line
+ 5600 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 5000 5700 5150 5700
+Connection ~ 5150 5700
+Connection ~ 5150 5950
+Wire Wire Line
+ 5450 5250 5450 5800
+Wire Wire Line
+ 5450 5800 5600 5800
+Wire Wire Line
+ 5800 5250 5800 5350
+Wire Wire Line
+ 5800 5350 5450 5350
+Connection ~ 5450 5350
+Wire Wire Line
+ 5450 4150 5450 4700
+Wire Wire Line
+ 5450 4700 5600 4700
+Wire Wire Line
+ 5800 4150 5800 4250
+Wire Wire Line
+ 5800 4250 5450 4250
+Connection ~ 5450 4250
+Wire Wire Line
+ 5450 3100 5450 3650
+Wire Wire Line
+ 5450 3650 5600 3650
+Wire Wire Line
+ 5800 3100 5800 3200
+Wire Wire Line
+ 5800 3200 5450 3200
+Connection ~ 5450 3200
+Wire Wire Line
+ 5450 2000 5450 2550
+Wire Wire Line
+ 5450 2550 5600 2550
+Wire Wire Line
+ 5800 2000 5800 2100
+Wire Wire Line
+ 5800 2100 5450 2100
+Connection ~ 5450 2100
+Wire Wire Line
+ 7050 2550 7100 2550
+Wire Wire Line
+ 7050 3650 7150 3650
+Wire Wire Line
+ 7050 4700 7150 4700
+Wire Wire Line
+ 7050 5800 7150 5800
+Wire Wire Line
+ 4100 5100 4550 5100
+Wire Wire Line
+ 4100 4000 4550 4000
+Wire Wire Line
+ 4100 2950 4550 2950
+Wire Wire Line
+ 4100 1850 4550 1850
+Wire Wire Line
+ 4100 2150 4550 2150
+Wire Wire Line
+ 4350 2150 4350 5400
+Wire Wire Line
+ 4350 5400 4550 5400
+Wire Wire Line
+ 4550 4300 4350 4300
+Connection ~ 4350 4300
+Wire Wire Line
+ 4550 3250 4350 3250
+Connection ~ 4350 3250
+Connection ~ 4350 2150
+$Comp
+L PORT U1
+U 2 1 685A7447
+P 3850 2150
+F 0 "U1" H 3900 2250 30 0000 C CNN
+F 1 "PORT" H 3850 2150 30 0000 C CNN
+F 2 "" H 3850 2150 60 0000 C CNN
+F 3 "" H 3850 2150 60 0000 C CNN
+ 2 3850 2150
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/Quad_D_FF.cir b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.cir
new file mode 100644
index 000000000..37c80e10b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.cir
@@ -0,0 +1,20 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Quad_D_FF/Quad_D_FF.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jun 24 11:58:14 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad8_ D_FF
+X2 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad9_ D_FF
+X3 Net-_U1-Pad4_ Net-_U1-Pad2_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad10_ D_FF
+X4 Net-_U1-Pad5_ Net-_U1-Pad2_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad11_ D_FF
+X5 Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad12_ CMOS_INVTR
+X6 Net-_U1-Pad9_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad13_ CMOS_INVTR
+X7 Net-_U1-Pad10_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad14_ CMOS_INVTR
+X8 Net-_U1-Pad11_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad15_ CMOS_INVTR
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/Quad_D_FF.cir.out b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.cir.out
new file mode 100644
index 000000000..1a896a200
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.cir.out
@@ -0,0 +1,25 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/quad_d_ff/quad_d_ff.cir
+
+.include D_FF.sub
+.include CMOS_INVTR.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad8_ D_FF
+x2 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad9_ D_FF
+x3 net-_u1-pad4_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad10_ D_FF
+x4 net-_u1-pad5_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad11_ D_FF
+x5 net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad12_ CMOS_INVTR
+x6 net-_u1-pad9_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ CMOS_INVTR
+x7 net-_u1-pad10_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad14_ CMOS_INVTR
+x8 net-_u1-pad11_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad15_ CMOS_INVTR
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/Quad_D_FF.pro b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4042B/Quad_D_FF.sch b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.sch
new file mode 100644
index 000000000..b11037c25
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.sch
@@ -0,0 +1,437 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L D_FF X1
+U 1 1 685A4330
+P 5000 2000
+F 0 "X1" H 5000 2000 60 0000 C CNN
+F 1 "D_FF" H 4850 2000 60 0000 C CNN
+F 2 "" H 5000 2000 60 0001 C CNN
+F 3 "" H 5000 2000 60 0001 C CNN
+ 1 5000 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X2
+U 1 1 685A43B2
+P 5000 3100
+F 0 "X2" H 5000 3100 60 0000 C CNN
+F 1 "D_FF" H 4850 3100 60 0000 C CNN
+F 2 "" H 5000 3100 60 0001 C CNN
+F 3 "" H 5000 3100 60 0001 C CNN
+ 1 5000 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X3
+U 1 1 685A442D
+P 5000 4150
+F 0 "X3" H 5000 4150 60 0000 C CNN
+F 1 "D_FF" H 4850 4150 60 0000 C CNN
+F 2 "" H 5000 4150 60 0001 C CNN
+F 3 "" H 5000 4150 60 0001 C CNN
+ 1 5000 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X4
+U 1 1 685A44A2
+P 5000 5250
+F 0 "X4" H 5000 5250 60 0000 C CNN
+F 1 "D_FF" H 4850 5250 60 0000 C CNN
+F 2 "" H 5000 5250 60 0001 C CNN
+F 3 "" H 5000 5250 60 0001 C CNN
+ 1 5000 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X5
+U 1 1 685A4627
+P 6250 2550
+F 0 "X5" H 6250 2550 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6350 2300 60 0000 C CNN
+F 2 "" H 6250 2550 60 0001 C CNN
+F 3 "" H 6250 2550 60 0001 C CNN
+ 1 6250 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X6
+U 1 1 685A4674
+P 6250 3650
+F 0 "X6" H 6250 3650 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6350 3400 60 0000 C CNN
+F 2 "" H 6250 3650 60 0001 C CNN
+F 3 "" H 6250 3650 60 0001 C CNN
+ 1 6250 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X7
+U 1 1 685A4791
+P 6250 4700
+F 0 "X7" H 6250 4700 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6350 4450 60 0000 C CNN
+F 2 "" H 6250 4700 60 0001 C CNN
+F 3 "" H 6250 4700 60 0001 C CNN
+ 1 6250 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X8
+U 1 1 685A47E6
+P 6250 5800
+F 0 "X8" H 6250 5800 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6350 5550 60 0000 C CNN
+F 2 "" H 6250 5800 60 0001 C CNN
+F 3 "" H 6250 5800 60 0001 C CNN
+ 1 6250 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A4895
+P 3850 1850
+F 0 "U1" H 3900 1950 30 0000 C CNN
+F 1 "PORT" H 3850 1850 30 0000 C CNN
+F 2 "" H 3850 1850 60 0000 C CNN
+F 3 "" H 3850 1850 60 0000 C CNN
+ 1 3850 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685A492A
+P 3850 2950
+F 0 "U1" H 3900 3050 30 0000 C CNN
+F 1 "PORT" H 3850 2950 30 0000 C CNN
+F 2 "" H 3850 2950 60 0000 C CNN
+F 3 "" H 3850 2950 60 0000 C CNN
+ 3 3850 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A4A37
+P 3850 4000
+F 0 "U1" H 3900 4100 30 0000 C CNN
+F 1 "PORT" H 3850 4000 30 0000 C CNN
+F 2 "" H 3850 4000 60 0000 C CNN
+F 3 "" H 3850 4000 60 0000 C CNN
+ 4 3850 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685A4B10
+P 3850 5100
+F 0 "U1" H 3900 5200 30 0000 C CNN
+F 1 "PORT" H 3850 5100 30 0000 C CNN
+F 2 "" H 3850 5100 60 0000 C CNN
+F 3 "" H 3850 5100 60 0000 C CNN
+ 5 3850 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685A4BE5
+P 6050 2000
+F 0 "U1" H 6100 2100 30 0000 C CNN
+F 1 "PORT" H 6050 2000 30 0000 C CNN
+F 2 "" H 6050 2000 60 0000 C CNN
+F 3 "" H 6050 2000 60 0000 C CNN
+ 8 6050 2000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685A4CBA
+P 7350 2550
+F 0 "U1" H 7400 2650 30 0000 C CNN
+F 1 "PORT" H 7350 2550 30 0000 C CNN
+F 2 "" H 7350 2550 60 0000 C CNN
+F 3 "" H 7350 2550 60 0000 C CNN
+ 12 7350 2550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685A4D33
+P 6050 3100
+F 0 "U1" H 6100 3200 30 0000 C CNN
+F 1 "PORT" H 6050 3100 30 0000 C CNN
+F 2 "" H 6050 3100 60 0000 C CNN
+F 3 "" H 6050 3100 60 0000 C CNN
+ 9 6050 3100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685A4DBE
+P 7400 3650
+F 0 "U1" H 7450 3750 30 0000 C CNN
+F 1 "PORT" H 7400 3650 30 0000 C CNN
+F 2 "" H 7400 3650 60 0000 C CNN
+F 3 "" H 7400 3650 60 0000 C CNN
+ 13 7400 3650
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685A4EC7
+P 6050 4150
+F 0 "U1" H 6100 4250 30 0000 C CNN
+F 1 "PORT" H 6050 4150 30 0000 C CNN
+F 2 "" H 6050 4150 60 0000 C CNN
+F 3 "" H 6050 4150 60 0000 C CNN
+ 10 6050 4150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685A4F44
+P 7400 4700
+F 0 "U1" H 7450 4800 30 0000 C CNN
+F 1 "PORT" H 7400 4700 30 0000 C CNN
+F 2 "" H 7400 4700 60 0000 C CNN
+F 3 "" H 7400 4700 60 0000 C CNN
+ 14 7400 4700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685A5115
+P 6050 5250
+F 0 "U1" H 6100 5350 30 0000 C CNN
+F 1 "PORT" H 6050 5250 30 0000 C CNN
+F 2 "" H 6050 5250 60 0000 C CNN
+F 3 "" H 6050 5250 60 0000 C CNN
+ 11 6050 5250
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 685A52B2
+P 7400 5800
+F 0 "U1" H 7450 5900 30 0000 C CNN
+F 1 "PORT" H 7400 5800 30 0000 C CNN
+F 2 "" H 7400 5800 60 0000 C CNN
+F 3 "" H 7400 5800 60 0000 C CNN
+ 15 7400 5800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685A53F3
+P 4750 1350
+F 0 "U1" H 4800 1450 30 0000 C CNN
+F 1 "PORT" H 4750 1350 30 0000 C CNN
+F 2 "" H 4750 1350 60 0000 C CNN
+F 3 "" H 4750 1350 60 0000 C CNN
+ 7 4750 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685A5583
+P 4700 5950
+F 0 "U1" H 4750 6050 30 0000 C CNN
+F 1 "PORT" H 4700 5950 30 0000 C CNN
+F 2 "" H 4700 5950 60 0000 C CNN
+F 3 "" H 4700 5950 60 0000 C CNN
+ 6 4700 5950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 1350 5000 1550
+Wire Wire Line
+ 5000 1500 5200 1500
+Wire Wire Line
+ 5200 1500 5200 5650
+Wire Wire Line
+ 5200 5650 5600 5650
+Wire Wire Line
+ 5000 4800 5200 4800
+Connection ~ 5200 4800
+Wire Wire Line
+ 5600 4550 5200 4550
+Connection ~ 5200 4550
+Wire Wire Line
+ 5000 3700 5200 3700
+Connection ~ 5200 3700
+Wire Wire Line
+ 5600 3500 5200 3500
+Connection ~ 5200 3500
+Wire Wire Line
+ 5000 2650 5200 2650
+Connection ~ 5200 2650
+Wire Wire Line
+ 5600 2400 5200 2400
+Connection ~ 5200 2400
+Connection ~ 5000 1500
+Wire Wire Line
+ 4950 5950 5600 5950
+Wire Wire Line
+ 5150 5950 5150 2450
+Wire Wire Line
+ 5150 2450 5000 2450
+Wire Wire Line
+ 5600 2700 5150 2700
+Connection ~ 5150 2700
+Wire Wire Line
+ 5000 3550 5150 3550
+Connection ~ 5150 3550
+Wire Wire Line
+ 5600 3800 5150 3800
+Connection ~ 5150 3800
+Wire Wire Line
+ 5000 4600 5150 4600
+Connection ~ 5150 4600
+Wire Wire Line
+ 5600 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 5000 5700 5150 5700
+Connection ~ 5150 5700
+Connection ~ 5150 5950
+Wire Wire Line
+ 5450 5250 5450 5800
+Wire Wire Line
+ 5450 5800 5600 5800
+Wire Wire Line
+ 5800 5250 5800 5350
+Wire Wire Line
+ 5800 5350 5450 5350
+Connection ~ 5450 5350
+Wire Wire Line
+ 5450 4150 5450 4700
+Wire Wire Line
+ 5450 4700 5600 4700
+Wire Wire Line
+ 5800 4150 5800 4250
+Wire Wire Line
+ 5800 4250 5450 4250
+Connection ~ 5450 4250
+Wire Wire Line
+ 5450 3100 5450 3650
+Wire Wire Line
+ 5450 3650 5600 3650
+Wire Wire Line
+ 5800 3100 5800 3200
+Wire Wire Line
+ 5800 3200 5450 3200
+Connection ~ 5450 3200
+Wire Wire Line
+ 5450 2000 5450 2550
+Wire Wire Line
+ 5450 2550 5600 2550
+Wire Wire Line
+ 5800 2000 5800 2100
+Wire Wire Line
+ 5800 2100 5450 2100
+Connection ~ 5450 2100
+Wire Wire Line
+ 7050 2550 7100 2550
+Wire Wire Line
+ 7050 3650 7150 3650
+Wire Wire Line
+ 7050 4700 7150 4700
+Wire Wire Line
+ 7050 5800 7150 5800
+Wire Wire Line
+ 4100 5100 4550 5100
+Wire Wire Line
+ 4100 4000 4550 4000
+Wire Wire Line
+ 4100 2950 4550 2950
+Wire Wire Line
+ 4100 1850 4550 1850
+Wire Wire Line
+ 4100 2150 4550 2150
+Wire Wire Line
+ 4350 2150 4350 5400
+Wire Wire Line
+ 4350 5400 4550 5400
+Wire Wire Line
+ 4550 4300 4350 4300
+Connection ~ 4350 4300
+Wire Wire Line
+ 4550 3250 4350 3250
+Connection ~ 4350 3250
+Connection ~ 4350 2150
+$Comp
+L PORT U1
+U 2 1 685A7447
+P 3850 2150
+F 0 "U1" H 3900 2250 30 0000 C CNN
+F 1 "PORT" H 3850 2150 30 0000 C CNN
+F 2 "" H 3850 2150 60 0000 C CNN
+F 3 "" H 3850 2150 60 0000 C CNN
+ 2 3850 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 685A7733
+P 8100 2350
+F 0 "scmode1" H 8100 2500 98 0000 C CNB
+F 1 "SKY130mode" H 8100 2250 118 0000 C CNB
+F 2 "" H 8100 2500 60 0001 C CNN
+F 3 "" H 8100 2500 60 0001 C CNN
+ 1 8100 2350
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/Quad_D_FF.sub b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.sub
new file mode 100644
index 000000000..06850c2e5
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/Quad_D_FF.sub
@@ -0,0 +1,19 @@
+* Subcircuit Quad_D_FF
+.subckt Quad_D_FF net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/quad_d_ff/quad_d_ff.cir
+.include D_FF.sub
+.include CMOS_INVTR.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad8_ D_FF
+x2 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad9_ D_FF
+x3 net-_u1-pad4_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad10_ D_FF
+x4 net-_u1-pad5_ net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad11_ D_FF
+x5 net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad12_ CMOS_INVTR
+x6 net-_u1-pad9_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ CMOS_INVTR
+x7 net-_u1-pad10_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad14_ CMOS_INVTR
+x8 net-_u1-pad11_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad15_ CMOS_INVTR
+* s c m o d e
+* Control Statements
+
+.ends Quad_D_FF
diff --git a/library/SubcircuitLibrary/CD4042B/Quad_D_FF_Previous_Values.xml b/library/SubcircuitLibrary/CD4042B/Quad_D_FF_Previous_Values.xml
new file mode 100644
index 000000000..bd9e78df3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/Quad_D_FF_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_FF/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_FF/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_FF/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_FF/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch-cache.lib b/library/SubcircuitLibrary/CD4042B/TG_D_Latch-cache.lib
new file mode 100644
index 000000000..80dcddf3a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 100 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -450 250 500 0 N
+P 3 0 1 0 -450 250 -450 -250 500 0 N
+X IN 1 -650 0 200 R 50 50 1 1 I
+X VDD 2 -650 150 200 R 50 50 1 1 I
+X GND 3 -650 -150 200 R 50 50 1 1 I
+X OUT 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch.bak b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.bak
new file mode 100644
index 000000000..e176827e0
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.bak
@@ -0,0 +1,363 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 6858190E
+P 4050 1900
+F 0 "SC1" H 4100 2200 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4350 1987 50 0000 R CNN
+F 2 "" H 4050 400 50 0001 C CNN
+F 3 "" H 4050 1900 50 0001 C CNN
+ 1 4050 1900
+ 0 1 1 0
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 68581A3F
+P 4050 2600
+F 0 "SC2" H 4100 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4350 2687 50 0000 R CNN
+F 2 "" H 4050 1100 50 0001 C CNN
+F 3 "" H 4050 2600 50 0001 C CNN
+ 1 4050 2600
+ 0 -1 -1 0
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 68581A7C
+P 4800 3350
+F 0 "SC3" H 4850 3650 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5100 3437 50 0000 R CNN
+F 2 "" H 4800 1850 50 0001 C CNN
+F 3 "" H 4800 3350 50 0001 C CNN
+ 1 4800 3350
+ 0 1 1 0
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 68581B09
+P 4800 4000
+F 0 "SC4" H 4850 4300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5100 4087 50 0000 R CNN
+F 2 "" H 4800 2500 50 0001 C CNN
+F 3 "" H 4800 4000 50 0001 C CNN
+ 1 4800 4000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 68581D3A
+P 6100 2300
+F 0 "X2" H 6100 2300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6200 2050 60 0000 C CNN
+F 2 "" H 6100 2300 60 0001 C CNN
+F 3 "" H 6100 2300 60 0001 C CNN
+ 1 6100 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X4
+U 1 1 68581DAF
+P 8300 2300
+F 0 "X4" H 8300 2300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 8400 2050 60 0000 C CNN
+F 2 "" H 8300 2300 60 0001 C CNN
+F 3 "" H 8300 2300 60 0001 C CNN
+ 1 8300 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X3
+U 1 1 68581E36
+P 7250 3400
+F 0 "X3" H 7250 3400 60 0000 C CNN
+F 1 "CMOS_INVTR" H 7350 3150 60 0000 C CNN
+F 2 "" H 7250 3400 60 0001 C CNN
+F 3 "" H 7250 3400 60 0001 C CNN
+ 1 7250 3400
+ 0 1 1 0
+$EndComp
+$Comp
+L CMOS_INVTR X5
+U 1 1 68581EF3
+P 8300 4200
+F 0 "X5" H 8300 4200 60 0000 C CNN
+F 1 "CMOS_INVTR" H 8400 3950 60 0000 C CNN
+F 2 "" H 8300 4200 60 0001 C CNN
+F 3 "" H 8300 4200 60 0001 C CNN
+ 1 8300 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68581F84
+P 3150 2250
+F 0 "U1" H 3200 2350 30 0000 C CNN
+F 1 "PORT" H 3150 2250 30 0000 C CNN
+F 2 "" H 3150 2250 60 0000 C CNN
+F 3 "" H 3150 2250 60 0000 C CNN
+ 1 3150 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68581FCD
+P 3150 2800
+F 0 "U1" H 3200 2900 30 0000 C CNN
+F 1 "PORT" H 3150 2800 30 0000 C CNN
+F 2 "" H 3150 2800 60 0000 C CNN
+F 3 "" H 3150 2800 60 0000 C CNN
+ 2 3150 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685820FF
+P 9600 2300
+F 0 "U1" H 9650 2400 30 0000 C CNN
+F 1 "PORT" H 9600 2300 30 0000 C CNN
+F 2 "" H 9600 2300 60 0000 C CNN
+F 3 "" H 9600 2300 60 0000 C CNN
+ 5 9600 2300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685821BE
+P 9600 4200
+F 0 "U1" H 9650 4300 30 0000 C CNN
+F 1 "PORT" H 9600 4200 30 0000 C CNN
+F 2 "" H 9600 4200 60 0000 C CNN
+F 3 "" H 9600 4200 60 0000 C CNN
+ 6 9600 4200
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3750 2100 3750 2400
+Wire Wire Line
+ 3400 2250 3750 2250
+Connection ~ 3750 2250
+Wire Wire Line
+ 4350 2100 4350 2400
+Wire Wire Line
+ 4050 2000 4050 2200
+Wire Wire Line
+ 4050 2500 4050 2300
+Wire Wire Line
+ 6900 2300 7650 2300
+Wire Wire Line
+ 7250 2750 7250 2300
+Connection ~ 7250 2300
+Wire Wire Line
+ 9100 2300 9350 2300
+Wire Wire Line
+ 9100 4200 9350 4200
+Wire Wire Line
+ 7250 4200 7650 4200
+Wire Wire Line
+ 4500 3550 4500 3800
+Wire Wire Line
+ 5100 3550 5100 3800
+Wire Wire Line
+ 4800 3450 4800 3600
+Wire Wire Line
+ 4800 3900 4800 3750
+Wire Wire Line
+ 4400 2300 4400 3700
+Wire Wire Line
+ 4400 3700 4500 3700
+Connection ~ 4500 3700
+Connection ~ 4400 2300
+Wire Wire Line
+ 5100 3650 6650 3650
+Wire Wire Line
+ 6650 3650 6650 4250
+Wire Wire Line
+ 6650 4250 7400 4250
+Wire Wire Line
+ 7400 4250 7400 4200
+Connection ~ 7400 4200
+Connection ~ 5100 3650
+Wire Wire Line
+ 4050 1600 3500 1600
+Wire Wire Line
+ 3500 1600 3500 4350
+Wire Wire Line
+ 4050 2900 4050 3050
+Wire Wire Line
+ 4050 3050 4800 3050
+Connection ~ 4050 3000
+Wire Wire Line
+ 5450 2450 5450 2750
+Wire Wire Line
+ 3650 2750 7100 2750
+Wire Wire Line
+ 7650 2450 7000 2450
+Wire Wire Line
+ 7000 2450 7000 4350
+Connection ~ 7000 2750
+Wire Wire Line
+ 5450 1850 5450 2150
+Wire Wire Line
+ 5300 2000 7650 2000
+Wire Wire Line
+ 7650 2000 7650 2150
+Wire Wire Line
+ 7400 2750 7400 2000
+Connection ~ 7400 2000
+Wire Wire Line
+ 7650 4050 7650 2750
+Wire Wire Line
+ 7650 2750 7400 2750
+Wire Wire Line
+ 7000 4350 7650 4350
+$Comp
+L CMOS_INVTR X1
+U 1 1 68582D21
+P 3800 3500
+F 0 "X1" H 3800 3500 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3900 3250 60 0000 C CNN
+F 2 "" H 3800 3500 60 0001 C CNN
+F 3 "" H 3800 3500 60 0001 C CNN
+ 1 3800 3500
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 3850 3000 4050 3000
+Wire Wire Line
+ 3850 2800 3850 3000
+Wire Wire Line
+ 3850 2850 3800 2850
+Wire Wire Line
+ 3500 4350 4800 4350
+Wire Wire Line
+ 4800 4350 4800 4300
+Wire Wire Line
+ 3800 4300 3800 4350
+Connection ~ 3800 4350
+Wire Wire Line
+ 4350 2300 5450 2300
+Connection ~ 4350 2300
+Wire Wire Line
+ 4050 2300 4100 2300
+Wire Wire Line
+ 4100 2300 4100 3600
+Wire Wire Line
+ 4100 3600 4800 3600
+Wire Wire Line
+ 3650 2850 3650 2750
+Connection ~ 4100 2750
+Wire Wire Line
+ 4050 2200 4150 2200
+Wire Wire Line
+ 4150 2200 4150 4100
+Wire Wire Line
+ 4150 4100 4900 4100
+Wire Wire Line
+ 4900 4100 4900 3750
+Wire Wire Line
+ 4900 3750 4800 3750
+Wire Wire Line
+ 3950 2850 5300 2850
+Connection ~ 4150 2850
+Wire Wire Line
+ 5300 2850 5300 2000
+Connection ~ 5450 2000
+Connection ~ 5450 2750
+$Comp
+L PORT U1
+U 4 1 685836DB
+P 5200 1850
+F 0 "U1" H 5250 1950 30 0000 C CNN
+F 1 "PORT" H 5200 1850 30 0000 C CNN
+F 2 "" H 5200 1850 60 0000 C CNN
+F 3 "" H 5200 1850 60 0000 C CNN
+ 4 5200 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6858373C
+P 4950 2550
+F 0 "U1" H 5000 2650 30 0000 C CNN
+F 1 "PORT" H 4950 2550 30 0000 C CNN
+F 2 "" H 4950 2550 60 0000 C CNN
+F 3 "" H 4950 2550 60 0000 C CNN
+ 3 4950 2550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5200 2550 5450 2550
+Connection ~ 5450 2550
+Text Label 3750 2250 0 60 ~ 0
+D
+Text Label 3550 2800 0 60 ~ 0
+clk
+Wire Wire Line
+ 3850 2800 3400 2800
+Connection ~ 3850 2850
+$Comp
+L SKY130mode scmode1
+U 1 1 68583D91
+P 2350 2200
+F 0 "scmode1" H 2350 2350 98 0000 C CNB
+F 1 "SKY130mode" H 2350 2100 118 0000 C CNB
+F 2 "" H 2350 2350 60 0001 C CNN
+F 3 "" H 2350 2350 60 0001 C CNN
+ 1 2350 2200
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch.cir b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.cir
new file mode 100644
index 000000000..b7ab4cd1b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.cir
@@ -0,0 +1,19 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/TG_D_Latch/TG_D_Latch.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 23 11:13:51 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 /D Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad4_ sky130_fd_pr__pfet_01v8
+SC2 /D /clk Net-_SC1-Pad3_ Net-_SC2-Pad4_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC3-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad4_ sky130_fd_pr__pfet_01v8
+U1 /D /clk Net-_SC2-Pad4_ Net-_SC1-Pad4_ Net-_U1-Pad5_ Net-_SC1-Pad3_ PORT
+scmode1 SKY130mode
+SC3 Net-_SC3-Pad1_ /clk Net-_SC1-Pad3_ Net-_SC2-Pad4_ sky130_fd_pr__nfet_01v8
+X1 /clk Net-_SC1-Pad4_ Net-_SC2-Pad4_ Net-_SC1-Pad2_ CMOS_INVTR
+X2 Net-_SC1-Pad3_ Net-_SC1-Pad4_ Net-_SC2-Pad4_ Net-_U1-Pad5_ CMOS_INVTR
+X3 Net-_U1-Pad5_ Net-_SC1-Pad4_ Net-_SC2-Pad4_ Net-_SC3-Pad1_ CMOS_INVTR
+
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch.cir.out b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.cir.out
new file mode 100644
index 000000000..a2955e89a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.cir.out
@@ -0,0 +1,23 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tg_d_latch/tg_d_latch.cir
+
+.include CMOS_INVTR.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc1 /d net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad4_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 /d /clk net-_sc1-pad3_ net-_sc2-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad4_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+* u1 /d /clk net-_sc2-pad4_ net-_sc1-pad4_ net-_u1-pad5_ net-_sc1-pad3_ port
+* s c m o d e
+xsc3 net-_sc3-pad1_ /clk net-_sc1-pad3_ net-_sc2-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+x1 /clk net-_sc1-pad4_ net-_sc2-pad4_ net-_sc1-pad2_ CMOS_INVTR
+x2 net-_sc1-pad3_ net-_sc1-pad4_ net-_sc2-pad4_ net-_u1-pad5_ CMOS_INVTR
+x3 net-_u1-pad5_ net-_sc1-pad4_ net-_sc2-pad4_ net-_sc3-pad1_ CMOS_INVTR
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch.pro b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch.sch b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.sch
new file mode 100644
index 000000000..1399e871f
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.sch
@@ -0,0 +1,340 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:TG_D_Latch-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 6858190E
+P 4050 1900
+F 0 "SC1" H 4100 2200 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4350 1987 50 0000 R CNN
+F 2 "" H 4050 400 50 0001 C CNN
+F 3 "" H 4050 1900 50 0001 C CNN
+ 1 4050 1900
+ 0 1 1 0
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 68581A3F
+P 4050 2600
+F 0 "SC2" H 4100 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4350 2687 50 0000 R CNN
+F 2 "" H 4050 1100 50 0001 C CNN
+F 3 "" H 4050 2600 50 0001 C CNN
+ 1 4050 2600
+ 0 -1 -1 0
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 68581B09
+P 6150 3800
+F 0 "SC4" H 6200 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6450 3887 50 0000 R CNN
+F 2 "" H 6150 2300 50 0001 C CNN
+F 3 "" H 6150 3800 50 0001 C CNN
+ 1 6150 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68581F84
+P 3150 2250
+F 0 "U1" H 3200 2350 30 0000 C CNN
+F 1 "PORT" H 3150 2250 30 0000 C CNN
+F 2 "" H 3150 2250 60 0000 C CNN
+F 3 "" H 3150 2250 60 0000 C CNN
+ 1 3150 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68581FCD
+P 3150 2800
+F 0 "U1" H 3200 2900 30 0000 C CNN
+F 1 "PORT" H 3150 2800 30 0000 C CNN
+F 2 "" H 3150 2800 60 0000 C CNN
+F 3 "" H 3150 2800 60 0000 C CNN
+ 2 3150 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685820FF
+P 9600 2300
+F 0 "U1" H 9650 2400 30 0000 C CNN
+F 1 "PORT" H 9600 2300 30 0000 C CNN
+F 2 "" H 9600 2300 60 0000 C CNN
+F 3 "" H 9600 2300 60 0000 C CNN
+ 5 9600 2300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685821BE
+P 7050 1650
+F 0 "U1" H 7100 1750 30 0000 C CNN
+F 1 "PORT" H 7050 1650 30 0000 C CNN
+F 2 "" H 7050 1650 60 0000 C CNN
+F 3 "" H 7050 1650 60 0000 C CNN
+ 6 7050 1650
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3750 2100 3750 2400
+Wire Wire Line
+ 3400 2250 3750 2250
+Connection ~ 3750 2250
+Wire Wire Line
+ 4350 2100 4350 2400
+Wire Wire Line
+ 8250 2300 9350 2300
+Wire Wire Line
+ 6600 3500 6350 3500
+Wire Wire Line
+ 6600 4100 6350 4100
+Wire Wire Line
+ 6450 3400 6450 3500
+Connection ~ 6450 3500
+Connection ~ 6500 4100
+Wire Wire Line
+ 4050 2900 4050 3800
+Connection ~ 4050 3000
+Wire Wire Line
+ 3850 3000 7100 3000
+Wire Wire Line
+ 3850 2800 3850 3000
+Wire Wire Line
+ 5650 3800 5850 3800
+$Comp
+L PORT U1
+U 4 1 685836DB
+P 5200 1850
+F 0 "U1" H 5250 1950 30 0000 C CNN
+F 1 "PORT" H 5200 1850 30 0000 C CNN
+F 2 "" H 5200 1850 60 0000 C CNN
+F 3 "" H 5200 1850 60 0000 C CNN
+ 4 5200 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6858373C
+P 4950 2550
+F 0 "U1" H 5000 2650 30 0000 C CNN
+F 1 "PORT" H 4950 2550 30 0000 C CNN
+F 2 "" H 4950 2550 60 0000 C CNN
+F 3 "" H 4950 2550 60 0000 C CNN
+ 3 4950 2550
+ 1 0 0 -1
+$EndComp
+Text Label 3750 2250 0 60 ~ 0
+D
+Text Label 3550 2800 0 60 ~ 0
+clk
+Wire Wire Line
+ 3850 2800 3400 2800
+$Comp
+L SKY130mode scmode1
+U 1 1 68583D91
+P 2350 2200
+F 0 "scmode1" H 2350 2350 98 0000 C CNB
+F 1 "SKY130mode" H 2350 2100 118 0000 C CNB
+F 2 "" H 2350 2350 60 0001 C CNN
+F 3 "" H 2350 2350 60 0001 C CNN
+ 1 2350 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 68581A7C
+P 6800 3800
+F 0 "SC3" H 6850 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 7100 3887 50 0000 R CNN
+F 2 "" H 6800 2300 50 0001 C CNN
+F 3 "" H 6800 3800 50 0001 C CNN
+ 1 6800 3800
+ -1 0 0 1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 6858EB8D
+P 4850 3800
+F 0 "X1" H 4850 3800 60 0000 C CNN
+F 1 "CMOS_INVTR" H 4950 3550 60 0000 C CNN
+F 2 "" H 4850 3800 60 0001 C CNN
+F 3 "" H 4850 3800 60 0001 C CNN
+ 1 4850 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 6858ECAA
+P 7300 2300
+F 0 "X2" H 7300 2300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 7400 2050 60 0000 C CNN
+F 2 "" H 7300 2300 60 0001 C CNN
+F 3 "" H 7300 2300 60 0001 C CNN
+ 1 7300 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X3
+U 1 1 6858ED25
+P 7400 4750
+F 0 "X3" H 7400 4750 60 0000 C CNN
+F 1 "CMOS_INVTR" H 7500 4500 60 0000 C CNN
+F 2 "" H 7400 4750 60 0001 C CNN
+F 3 "" H 7400 4750 60 0001 C CNN
+ 1 7400 4750
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4050 3800 4200 3800
+Wire Wire Line
+ 4050 1600 5750 1600
+Wire Wire Line
+ 5750 1600 5750 3800
+Connection ~ 5750 3800
+Wire Wire Line
+ 7100 3000 7100 3800
+Wire Wire Line
+ 6650 2300 4350 2300
+Connection ~ 4350 2300
+Wire Wire Line
+ 8100 2300 8100 4750
+Wire Wire Line
+ 8100 4750 8050 4750
+Wire Wire Line
+ 8250 2300 8250 2550
+Wire Wire Line
+ 8250 2550 8100 2550
+Connection ~ 8100 2550
+Wire Wire Line
+ 6400 1650 6400 3400
+Wire Wire Line
+ 6400 1650 6800 1650
+Connection ~ 6400 2300
+Wire Wire Line
+ 6500 4100 6500 4750
+Wire Wire Line
+ 6500 4750 6600 4750
+Wire Wire Line
+ 6400 3400 6450 3400
+Wire Wire Line
+ 5450 1850 6250 1850
+Wire Wire Line
+ 6250 1850 6250 2150
+Wire Wire Line
+ 6250 2150 6650 2150
+Wire Wire Line
+ 5200 2550 6650 2550
+Wire Wire Line
+ 6650 2550 6650 2450
+Wire Wire Line
+ 4050 2000 4050 2200
+Wire Wire Line
+ 4050 2200 5550 2200
+Wire Wire Line
+ 5550 2200 5550 1850
+Connection ~ 5550 1850
+Wire Wire Line
+ 4050 2500 5400 2500
+Wire Wire Line
+ 5400 2500 5400 3250
+Connection ~ 5400 2550
+Wire Wire Line
+ 4200 3650 4200 2750
+Wire Wire Line
+ 4200 2750 4650 2750
+Wire Wire Line
+ 4650 2750 4650 2200
+Connection ~ 4650 2200
+Wire Wire Line
+ 4200 3950 4150 3950
+Wire Wire Line
+ 4150 3950 4150 3250
+Wire Wire Line
+ 4150 3250 5400 3250
+Wire Wire Line
+ 8050 4600 8050 2850
+Wire Wire Line
+ 8050 2850 5900 2850
+Wire Wire Line
+ 5900 2850 5900 1850
+Connection ~ 5900 1850
+Wire Wire Line
+ 8050 4900 8050 5150
+Wire Wire Line
+ 8050 5150 4100 5150
+Wire Wire Line
+ 4100 5150 4100 3900
+Wire Wire Line
+ 4100 3900 4150 3900
+Connection ~ 4150 3900
+Wire Wire Line
+ 6250 3800 6250 3700
+Wire Wire Line
+ 6250 3700 8050 3700
+Connection ~ 8050 3700
+Wire Wire Line
+ 6700 3800 6450 3800
+Wire Wire Line
+ 6450 3800 6450 3900
+Wire Wire Line
+ 6450 3900 6050 3900
+Wire Wire Line
+ 6050 3900 6050 5150
+Connection ~ 6050 5150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch.sub b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.sub
new file mode 100644
index 000000000..7f190ea3c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch.sub
@@ -0,0 +1,17 @@
+* Subcircuit TG_D_Latch
+.subckt TG_D_Latch /d /clk net-_sc2-pad4_ net-_sc1-pad4_ net-_u1-pad5_ net-_sc1-pad3_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tg_d_latch/tg_d_latch.cir
+.include CMOS_INVTR.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc1 /d net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad4_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 /d /clk net-_sc1-pad3_ net-_sc2-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad4_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+* s c m o d e
+xsc3 net-_sc3-pad1_ /clk net-_sc1-pad3_ net-_sc2-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+x1 /clk net-_sc1-pad4_ net-_sc2-pad4_ net-_sc1-pad2_ CMOS_INVTR
+x2 net-_sc1-pad3_ net-_sc1-pad4_ net-_sc2-pad4_ net-_u1-pad5_ CMOS_INVTR
+x3 net-_u1-pad5_ net-_sc1-pad4_ net-_sc2-pad4_ net-_sc3-pad1_ CMOS_INVTR
+* Control Statements
+
+.ends TG_D_Latch
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch_Previous_Values.xml b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_Previous_Values.xml
new file mode 100644
index 000000000..2fd740063
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=3 l=0.15w=1 l=0.15/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl-cache.lib b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.bak b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.bak
new file mode 100644
index 000000000..612d217bf
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.bak
@@ -0,0 +1,336 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 68582578
+P 4000 2050
+F 0 "SC1" H 4050 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 2137 50 0000 R CNN
+F 2 "" H 4000 550 50 0001 C CNN
+F 3 "" H 4000 2050 50 0001 C CNN
+ 1 4000 2050
+ 0 1 1 0
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 685825B9
+P 4000 2800
+F 0 "SC2" H 4050 3100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 2887 50 0000 R CNN
+F 2 "" H 4000 1300 50 0001 C CNN
+F 3 "" H 4000 2800 50 0001 C CNN
+ 1 4000 2800
+ 0 -1 -1 0
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 685825F4
+P 4000 3800
+F 0 "SC3" H 4050 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 3887 50 0000 R CNN
+F 2 "" H 4000 2300 50 0001 C CNN
+F 3 "" H 4000 3800 50 0001 C CNN
+ 1 4000 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 6858276D
+P 4000 4500
+F 0 "SC4" H 4050 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 4587 50 0000 R CNN
+F 2 "" H 4000 3000 50 0001 C CNN
+F 3 "" H 4000 4500 50 0001 C CNN
+ 1 4000 4500
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 3700 2250 3700 2600
+Wire Wire Line
+ 4300 2250 4300 2600
+Wire Wire Line
+ 4000 3100 4000 3500
+Wire Wire Line
+ 3700 4000 3700 4300
+Wire Wire Line
+ 4300 4000 4300 4300
+Wire Wire Line
+ 4000 1750 4000 1650
+Wire Wire Line
+ 4000 1650 3500 1650
+Wire Wire Line
+ 3500 1650 3500 4900
+Wire Wire Line
+ 3400 4900 4000 4900
+Wire Wire Line
+ 4000 4900 4000 4800
+$Comp
+L CMOS_INVTR X1
+U 1 1 685828D6
+P 2500 2400
+F 0 "X1" H 2500 2400 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2600 2150 60 0000 C CNN
+F 2 "" H 2500 2400 60 0001 C CNN
+F 3 "" H 2500 2400 60 0001 C CNN
+ 1 2500 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X4
+U 1 1 68582953
+P 5550 2400
+F 0 "X4" H 5550 2400 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5650 2150 60 0000 C CNN
+F 2 "" H 5550 2400 60 0001 C CNN
+F 3 "" H 5550 2400 60 0001 C CNN
+ 1 5550 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X5
+U 1 1 685829C8
+P 7300 2400
+F 0 "X5" H 7300 2400 60 0000 C CNN
+F 1 "CMOS_INVTR" H 7400 2150 60 0000 C CNN
+F 2 "" H 7300 2400 60 0001 C CNN
+F 3 "" H 7300 2400 60 0001 C CNN
+ 1 7300 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 68582A57
+P 2500 5700
+F 0 "X2" H 2500 5700 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2600 5450 60 0000 C CNN
+F 2 "" H 2500 5700 60 0001 C CNN
+F 3 "" H 2500 5700 60 0001 C CNN
+ 1 2500 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X3
+U 1 1 68582AF8
+P 4200 5700
+F 0 "X3" H 4200 5700 60 0000 C CNN
+F 1 "CMOS_INVTR" H 4300 5450 60 0000 C CNN
+F 2 "" H 4200 5700 60 0001 C CNN
+F 3 "" H 4200 5700 60 0001 C CNN
+ 1 4200 5700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1850 2250 1850 2000
+Wire Wire Line
+ 1650 2000 6650 2000
+Wire Wire Line
+ 6650 2000 6650 2250
+Wire Wire Line
+ 1850 2550 1850 2800
+Wire Wire Line
+ 1850 2800 6650 2800
+Wire Wire Line
+ 6650 2800 6650 2550
+Wire Wire Line
+ 4900 2550 4900 2800
+Connection ~ 4900 2800
+Wire Wire Line
+ 4900 2250 4900 2000
+Connection ~ 4900 2000
+Wire Wire Line
+ 6350 2400 6650 2400
+Wire Wire Line
+ 3300 2400 3700 2400
+Connection ~ 3700 2400
+Wire Wire Line
+ 4900 2400 4300 2400
+Connection ~ 4300 2400
+Wire Wire Line
+ 4000 2150 3850 2150
+Wire Wire Line
+ 3850 2150 3850 2000
+Connection ~ 3850 2000
+Wire Wire Line
+ 4000 2700 3800 2700
+Wire Wire Line
+ 3800 2700 3800 2800
+Connection ~ 3800 2800
+Wire Wire Line
+ 1850 5550 1850 3100
+Wire Wire Line
+ 1850 3100 1650 3100
+Wire Wire Line
+ 1650 3100 1650 2000
+Connection ~ 1850 2000
+Wire Wire Line
+ 4000 4400 4000 4500
+Wire Wire Line
+ 4000 4500 1850 4500
+Connection ~ 1850 4500
+Wire Wire Line
+ 3550 5550 3550 4500
+Connection ~ 3550 4500
+Wire Wire Line
+ 1850 5850 1850 6000
+Wire Wire Line
+ 1850 6000 3550 6000
+Wire Wire Line
+ 3550 6000 3550 5850
+Wire Wire Line
+ 2850 2800 2850 6000
+Connection ~ 2850 6000
+Connection ~ 2850 2800
+Wire Wire Line
+ 4000 3900 4000 3800
+Wire Wire Line
+ 4000 3800 3500 3800
+Connection ~ 3500 3800
+Wire Wire Line
+ 3300 5700 3550 5700
+Wire Wire Line
+ 3400 4900 3400 5700
+Connection ~ 3400 5700
+Connection ~ 3500 4900
+Wire Wire Line
+ 4000 3300 5000 3300
+Wire Wire Line
+ 5000 3300 5000 5700
+Connection ~ 4000 3300
+$Comp
+L PORT U1
+U 1 1 6858317A
+P 1250 2400
+F 0 "U1" H 1300 2500 30 0000 C CNN
+F 1 "PORT" H 1250 2400 30 0000 C CNN
+F 2 "" H 1250 2400 60 0000 C CNN
+F 3 "" H 1250 2400 60 0000 C CNN
+ 1 1250 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685831F1
+P 1400 5700
+F 0 "U1" H 1450 5800 30 0000 C CNN
+F 1 "PORT" H 1400 5700 30 0000 C CNN
+F 2 "" H 1400 5700 60 0000 C CNN
+F 3 "" H 1400 5700 60 0000 C CNN
+ 2 1400 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68583299
+P 8550 2400
+F 0 "U1" H 8600 2500 30 0000 C CNN
+F 1 "PORT" H 8550 2400 30 0000 C CNN
+F 2 "" H 8550 2400 60 0000 C CNN
+F 3 "" H 8550 2400 60 0000 C CNN
+ 5 8550 2400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68583330
+P 6750 3050
+F 0 "U1" H 6800 3150 30 0000 C CNN
+F 1 "PORT" H 6750 3050 30 0000 C CNN
+F 2 "" H 6750 3050 60 0000 C CNN
+F 3 "" H 6750 3050 60 0000 C CNN
+ 4 6750 3050
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685833C1
+P 6200 1800
+F 0 "U1" H 6250 1900 30 0000 C CNN
+F 1 "PORT" H 6200 1800 30 0000 C CNN
+F 2 "" H 6200 1800 60 0000 C CNN
+F 3 "" H 6200 1800 60 0000 C CNN
+ 3 6200 1800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1500 2400 1850 2400
+Wire Wire Line
+ 6450 1800 6450 2000
+Connection ~ 6450 2000
+Wire Wire Line
+ 6500 3050 6500 2800
+Connection ~ 6500 2800
+Wire Wire Line
+ 8100 2400 8300 2400
+Wire Wire Line
+ 1650 5700 1850 5700
+Text Label 1550 2400 0 60 ~ 0
+clock
+Text Label 1750 5700 1 60 ~ 0
+polarity
+Text Label 8150 2400 0 60 ~ 0
+clock
+$Comp
+L SKY130mode scmode1
+U 1 1 68583B39
+P 8050 3950
+F 0 "scmode1" H 8050 4100 98 0000 C CNB
+F 1 "SKY130mode" H 8050 3850 118 0000 C CNB
+F 2 "" H 8050 4100 60 0001 C CNN
+F 3 "" H 8050 4100 60 0001 C CNN
+ 1 8050 3950
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.cir b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.cir
new file mode 100644
index 000000000..135a5112c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.cir
@@ -0,0 +1,34 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/TG_D_Latch_ctrl/TG_D_Latch_ctrl.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 23 11:40:14 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 /clock /polarity /Vdd /Gnd /Out PORT
+scmode1 SKY130mode
+SC5 Net-_SC10-Pad1_ Net-_SC1-Pad1_ /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC10 Net-_SC10-Pad1_ /clock /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ /polarity /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC13 Net-_SC13-Pad1_ Net-_SC10-Pad1_ /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ /polarity /Gnd /Gnd sky130_fd_pr__nfet_01v8
+SC7 Net-_SC10-Pad1_ Net-_SC1-Pad1_ Net-_SC7-Pad3_ Net-_SC7-Pad3_ sky130_fd_pr__nfet_01v8
+SC9 Net-_SC7-Pad3_ /clock /Gnd /Gnd sky130_fd_pr__nfet_01v8
+SC14 Net-_SC13-Pad1_ Net-_SC10-Pad1_ /Gnd /Gnd sky130_fd_pr__nfet_01v8
+SC6 Net-_SC12-Pad1_ Net-_SC3-Pad1_ /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC12 Net-_SC12-Pad1_ /polarity /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC3 Net-_SC3-Pad1_ /clock /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC15 Net-_SC15-Pad1_ Net-_SC12-Pad1_ /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC4 Net-_SC3-Pad1_ /clock /Gnd /Gnd sky130_fd_pr__nfet_01v8
+SC8 Net-_SC12-Pad1_ Net-_SC3-Pad1_ Net-_SC11-Pad1_ Net-_SC11-Pad1_ sky130_fd_pr__nfet_01v8
+SC11 Net-_SC11-Pad1_ /polarity /Gnd /Gnd sky130_fd_pr__nfet_01v8
+SC16 Net-_SC15-Pad1_ Net-_SC12-Pad1_ /Gnd /Gnd sky130_fd_pr__nfet_01v8
+SC18 Net-_SC18-Pad1_ Net-_SC13-Pad1_ /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC19 Net-_SC17-Pad1_ Net-_SC15-Pad1_ Net-_SC18-Pad1_ Net-_SC18-Pad1_ sky130_fd_pr__pfet_01v8
+SC21 /Out Net-_SC17-Pad1_ /Vdd /Vdd sky130_fd_pr__pfet_01v8
+SC17 Net-_SC17-Pad1_ Net-_SC13-Pad1_ /Gnd /Gnd sky130_fd_pr__nfet_01v8
+SC20 Net-_SC17-Pad1_ Net-_SC15-Pad1_ /Gnd /Gnd sky130_fd_pr__nfet_01v8
+SC22 /Out Net-_SC17-Pad1_ /Gnd /Gnd sky130_fd_pr__nfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.cir.out b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.cir.out
new file mode 100644
index 000000000..34cfb755f
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.cir.out
@@ -0,0 +1,37 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tg_d_latch_ctrl/tg_d_latch_ctrl.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* u1 /clock /polarity /vdd /gnd /out port
+* s c m o d e
+xsc5 net-_sc10-pad1_ net-_sc1-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc10 net-_sc10-pad1_ /clock /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ /polarity /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc13 net-_sc13-pad1_ net-_sc10-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ /polarity /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc10-pad1_ net-_sc1-pad1_ net-_sc7-pad3_ net-_sc7-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc9 net-_sc7-pad3_ /clock /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc14 net-_sc13-pad1_ net-_sc10-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc12-pad1_ net-_sc3-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc12 net-_sc12-pad1_ /polarity /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc3-pad1_ /clock /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc15 net-_sc15-pad1_ net-_sc12-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc3-pad1_ /clock /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc8 net-_sc12-pad1_ net-_sc3-pad1_ net-_sc11-pad1_ net-_sc11-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc11 net-_sc11-pad1_ /polarity /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc16 net-_sc15-pad1_ net-_sc12-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc18 net-_sc18-pad1_ net-_sc13-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc19 net-_sc17-pad1_ net-_sc15-pad1_ net-_sc18-pad1_ net-_sc18-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc21 /out net-_sc17-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc17 net-_sc17-pad1_ net-_sc13-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc20 net-_sc17-pad1_ net-_sc15-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc22 /out net-_sc17-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.pro b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.sch b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.sch
new file mode 100644
index 000000000..faaff3081
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.sch
@@ -0,0 +1,700 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:TG_D_Latch_ctrl-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L PORT U1
+U 1 1 6858317A
+P 3300 2750
+F 0 "U1" H 3350 2850 30 0000 C CNN
+F 1 "PORT" H 3300 2750 30 0000 C CNN
+F 2 "" H 3300 2750 60 0000 C CNN
+F 3 "" H 3300 2750 60 0000 C CNN
+ 1 3300 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685831F1
+P 1150 2200
+F 0 "U1" H 1200 2300 30 0000 C CNN
+F 1 "PORT" H 1150 2200 30 0000 C CNN
+F 2 "" H 1150 2200 60 0000 C CNN
+F 3 "" H 1150 2200 60 0000 C CNN
+ 2 1150 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68583299
+P 8250 3550
+F 0 "U1" H 8300 3650 30 0000 C CNN
+F 1 "PORT" H 8250 3550 30 0000 C CNN
+F 2 "" H 8250 3550 60 0000 C CNN
+F 3 "" H 8250 3550 60 0000 C CNN
+ 5 8250 3550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68583330
+P 4800 3900
+F 0 "U1" H 4850 4000 30 0000 C CNN
+F 1 "PORT" H 4800 3900 30 0000 C CNN
+F 2 "" H 4800 3900 60 0000 C CNN
+F 3 "" H 4800 3900 60 0000 C CNN
+ 4 4800 3900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685833C1
+P 3650 1000
+F 0 "U1" H 3700 1100 30 0000 C CNN
+F 1 "PORT" H 3650 1000 30 0000 C CNN
+F 2 "" H 3650 1000 60 0000 C CNN
+F 3 "" H 3650 1000 60 0000 C CNN
+ 3 3650 1000
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68583B39
+P 10650 2400
+F 0 "scmode1" H 10650 2550 98 0000 C CNB
+F 1 "SKY130mode" H 10650 2300 118 0000 C CNB
+F 2 "" H 10650 2550 60 0001 C CNN
+F 3 "" H 10650 2550 60 0001 C CNN
+ 1 10650 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC5
+U 1 1 6858F184
+P 2700 1750
+F 0 "SC5" H 2750 2050 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 3000 1837 50 0000 R CNN
+F 2 "" H 2700 250 50 0001 C CNN
+F 3 "" H 2700 1750 50 0001 C CNN
+ 1 2700 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC10
+U 1 1 6858F1CD
+P 3350 1750
+F 0 "SC10" H 3400 2050 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 3650 1837 50 0000 R CNN
+F 2 "" H 3350 250 50 0001 C CNN
+F 3 "" H 3350 1750 50 0001 C CNN
+ 1 3350 1750
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 6858F56C
+P 1950 1750
+F 0 "SC1" H 2000 2050 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 2250 1837 50 0000 R CNN
+F 2 "" H 1950 250 50 0001 C CNN
+F 3 "" H 1950 1750 50 0001 C CNN
+ 1 1950 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC13
+U 1 1 6858F728
+P 4300 1750
+F 0 "SC13" H 4350 2050 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4600 1837 50 0000 R CNN
+F 2 "" H 4300 250 50 0001 C CNN
+F 3 "" H 4300 1750 50 0001 C CNN
+ 1 4300 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 6858F78D
+P 1950 2600
+F 0 "SC2" H 2000 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 2250 2687 50 0000 R CNN
+F 2 "" H 1950 1100 50 0001 C CNN
+F 3 "" H 1950 2600 50 0001 C CNN
+ 1 1950 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC7
+U 1 1 6858F7FC
+P 2850 2600
+F 0 "SC7" H 2900 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3150 2687 50 0000 R CNN
+F 2 "" H 2850 1100 50 0001 C CNN
+F 3 "" H 2850 2600 50 0001 C CNN
+ 1 2850 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC9
+U 1 1 6858F96B
+P 3250 3350
+F 0 "SC9" H 3300 3650 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3550 3437 50 0000 R CNN
+F 2 "" H 3250 1850 50 0001 C CNN
+F 3 "" H 3250 3350 50 0001 C CNN
+ 1 3250 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC14
+U 1 1 6858FADD
+P 4300 2550
+F 0 "SC14" H 4350 2850 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4600 2637 50 0000 R CNN
+F 2 "" H 4300 1050 50 0001 C CNN
+F 3 "" H 4300 2550 50 0001 C CNN
+ 1 4300 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC6
+U 1 1 68590EC2
+P 2800 5000
+F 0 "SC6" H 2850 5300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 3100 5087 50 0000 R CNN
+F 2 "" H 2800 3500 50 0001 C CNN
+F 3 "" H 2800 5000 50 0001 C CNN
+ 1 2800 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC12
+U 1 1 68590EC9
+P 3450 5000
+F 0 "SC12" H 3500 5300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 3750 5087 50 0000 R CNN
+F 2 "" H 3450 3500 50 0001 C CNN
+F 3 "" H 3450 5000 50 0001 C CNN
+ 1 3450 5000
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 68590ED0
+P 2050 5000
+F 0 "SC3" H 2100 5300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 2350 5087 50 0000 R CNN
+F 2 "" H 2050 3500 50 0001 C CNN
+F 3 "" H 2050 5000 50 0001 C CNN
+ 1 2050 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC15
+U 1 1 68590ED7
+P 4400 5000
+F 0 "SC15" H 4450 5300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4700 5087 50 0000 R CNN
+F 2 "" H 4400 3500 50 0001 C CNN
+F 3 "" H 4400 5000 50 0001 C CNN
+ 1 4400 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 68590EDE
+P 2050 5850
+F 0 "SC4" H 2100 6150 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 2350 5937 50 0000 R CNN
+F 2 "" H 2050 4350 50 0001 C CNN
+F 3 "" H 2050 5850 50 0001 C CNN
+ 1 2050 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC8
+U 1 1 68590EE5
+P 2950 5850
+F 0 "SC8" H 3000 6150 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3250 5937 50 0000 R CNN
+F 2 "" H 2950 4350 50 0001 C CNN
+F 3 "" H 2950 5850 50 0001 C CNN
+ 1 2950 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC11
+U 1 1 68590EEC
+P 3350 6600
+F 0 "SC11" H 3400 6900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3650 6687 50 0000 R CNN
+F 2 "" H 3350 5100 50 0001 C CNN
+F 3 "" H 3350 6600 50 0001 C CNN
+ 1 3350 6600
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC16
+U 1 1 68590EF3
+P 4400 5800
+F 0 "SC16" H 4450 6100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4700 5887 50 0000 R CNN
+F 2 "" H 4400 4300 50 0001 C CNN
+F 3 "" H 4400 5800 50 0001 C CNN
+ 1 4400 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC18
+U 1 1 6859119B
+P 6150 2500
+F 0 "SC18" H 6200 2800 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6450 2587 50 0000 R CNN
+F 2 "" H 6150 1000 50 0001 C CNN
+F 3 "" H 6150 2500 50 0001 C CNN
+ 1 6150 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC19
+U 1 1 68591314
+P 6550 3200
+F 0 "SC19" H 6600 3500 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6850 3287 50 0000 R CNN
+F 2 "" H 6550 1700 50 0001 C CNN
+F 3 "" H 6550 3200 50 0001 C CNN
+ 1 6550 3200
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC21
+U 1 1 68591481
+P 7700 3200
+F 0 "SC21" H 7750 3500 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 8000 3287 50 0000 R CNN
+F 2 "" H 7700 1700 50 0001 C CNN
+F 3 "" H 7700 3200 50 0001 C CNN
+ 1 7700 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC17
+U 1 1 6859153C
+P 6000 3950
+F 0 "SC17" H 6050 4250 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6300 4037 50 0000 R CNN
+F 2 "" H 6000 2450 50 0001 C CNN
+F 3 "" H 6000 3950 50 0001 C CNN
+ 1 6000 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC20
+U 1 1 685918B6
+P 6700 3950
+F 0 "SC20" H 6750 4250 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 7000 4037 50 0000 R CNN
+F 2 "" H 6700 2450 50 0001 C CNN
+F 3 "" H 6700 3950 50 0001 C CNN
+ 1 6700 3950
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC22
+U 1 1 6859198A
+P 7700 3950
+F 0 "SC22" H 7750 4250 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 8000 4037 50 0000 R CNN
+F 2 "" H 7700 2450 50 0001 C CNN
+F 3 "" H 7700 3950 50 0001 C CNN
+ 1 7700 3950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2150 1450 2150 1350
+Wire Wire Line
+ 2150 1350 5550 1350
+Wire Wire Line
+ 4500 1350 4500 1450
+Wire Wire Line
+ 2900 1450 2900 1350
+Connection ~ 2900 1350
+Wire Wire Line
+ 3150 1450 3150 1350
+Connection ~ 3150 1350
+Wire Wire Line
+ 2800 1750 2950 1750
+Wire Wire Line
+ 2950 1750 2950 1350
+Connection ~ 2950 1350
+Wire Wire Line
+ 3250 1750 3100 1750
+Wire Wire Line
+ 3100 1750 3100 1350
+Connection ~ 3100 1350
+Wire Wire Line
+ 2050 1750 2200 1750
+Wire Wire Line
+ 2200 1750 2200 1350
+Connection ~ 2200 1350
+Wire Wire Line
+ 4400 1750 4550 1750
+Wire Wire Line
+ 4550 1750 4550 1350
+Connection ~ 4500 1350
+Wire Wire Line
+ 2900 2050 3150 2050
+Wire Wire Line
+ 3050 2300 3050 2050
+Connection ~ 3050 2050
+Wire Wire Line
+ 2150 2050 2150 2300
+Wire Wire Line
+ 2400 1750 2400 2600
+Wire Wire Line
+ 2400 2600 2550 2600
+Wire Wire Line
+ 2150 2200 2400 2200
+Connection ~ 2400 2200
+Connection ~ 2150 2200
+Wire Wire Line
+ 3650 1750 3650 3350
+Wire Wire Line
+ 3650 3350 3550 3350
+Wire Wire Line
+ 3050 2900 3050 3050
+Wire Wire Line
+ 2950 2600 3100 2600
+Wire Wire Line
+ 3100 2600 3100 2950
+Wire Wire Line
+ 3100 2950 3050 2950
+Connection ~ 3050 2950
+Wire Wire Line
+ 3150 3350 3000 3350
+Wire Wire Line
+ 3000 3350 3000 3700
+Wire Wire Line
+ 2200 3700 5500 3700
+Wire Wire Line
+ 3050 3700 3050 3650
+Wire Wire Line
+ 4000 1750 4000 2550
+Wire Wire Line
+ 3050 2150 4000 2150
+Connection ~ 4000 2150
+Connection ~ 3050 2150
+Wire Wire Line
+ 4500 2050 4500 2250
+Wire Wire Line
+ 1650 1750 1650 2600
+Wire Wire Line
+ 4400 2550 4550 2550
+Wire Wire Line
+ 4550 2550 4550 3900
+Wire Wire Line
+ 4550 2850 4500 2850
+Wire Wire Line
+ 2050 2600 2200 2600
+Wire Wire Line
+ 2200 2600 2200 3700
+Wire Wire Line
+ 2200 2900 2150 2900
+Wire Wire Line
+ 2250 4700 2250 4600
+Wire Wire Line
+ 2250 4600 4650 4600
+Wire Wire Line
+ 4600 4600 4600 4700
+Wire Wire Line
+ 3000 4700 3000 4600
+Connection ~ 3000 4600
+Wire Wire Line
+ 3250 4700 3250 4600
+Connection ~ 3250 4600
+Wire Wire Line
+ 2900 5000 3050 5000
+Wire Wire Line
+ 3050 5000 3050 4600
+Connection ~ 3050 4600
+Wire Wire Line
+ 3350 5000 3200 5000
+Wire Wire Line
+ 3200 5000 3200 4600
+Connection ~ 3200 4600
+Wire Wire Line
+ 2150 5000 2300 5000
+Wire Wire Line
+ 2300 5000 2300 4600
+Connection ~ 2300 4600
+Wire Wire Line
+ 4500 5000 4650 5000
+Wire Wire Line
+ 4650 5000 4650 4600
+Connection ~ 4600 4600
+Wire Wire Line
+ 3000 5300 3250 5300
+Wire Wire Line
+ 3150 5550 3150 5300
+Connection ~ 3150 5300
+Wire Wire Line
+ 2250 5300 2250 5550
+Wire Wire Line
+ 2500 5000 2500 5850
+Wire Wire Line
+ 2500 5850 2650 5850
+Wire Wire Line
+ 2250 5450 2500 5450
+Connection ~ 2500 5450
+Connection ~ 2250 5450
+Wire Wire Line
+ 3750 5000 3750 6600
+Wire Wire Line
+ 3750 6600 3650 6600
+Wire Wire Line
+ 3150 6150 3150 6300
+Wire Wire Line
+ 3050 5850 3200 5850
+Wire Wire Line
+ 3200 5850 3200 6200
+Wire Wire Line
+ 3200 6200 3150 6200
+Connection ~ 3150 6200
+Wire Wire Line
+ 3250 6600 3100 6600
+Wire Wire Line
+ 3100 6600 3100 6950
+Wire Wire Line
+ 4650 6950 2300 6950
+Wire Wire Line
+ 3150 6950 3150 6900
+Wire Wire Line
+ 4100 5000 4100 5800
+Wire Wire Line
+ 3150 5400 4100 5400
+Connection ~ 4100 5400
+Connection ~ 3150 5400
+Wire Wire Line
+ 4600 5300 4600 5500
+Wire Wire Line
+ 1750 5000 1750 5850
+Wire Wire Line
+ 4500 5800 4650 5800
+Wire Wire Line
+ 4650 5800 4650 6950
+Wire Wire Line
+ 4650 6100 4600 6100
+Wire Wire Line
+ 2150 5850 2300 5850
+Wire Wire Line
+ 2300 5850 2300 6950
+Wire Wire Line
+ 2300 6150 2250 6150
+Wire Wire Line
+ 6350 2800 6350 2900
+Wire Wire Line
+ 6350 2200 7900 2200
+Wire Wire Line
+ 7900 2200 7900 2900
+Wire Wire Line
+ 6250 2500 6400 2500
+Wire Wire Line
+ 6400 2500 6400 2200
+Connection ~ 6400 2200
+Wire Wire Line
+ 7800 3200 7950 3200
+Wire Wire Line
+ 7950 3200 7950 2800
+Wire Wire Line
+ 7950 2800 7900 2800
+Connection ~ 7900 2800
+Wire Wire Line
+ 6200 3650 6500 3650
+Wire Wire Line
+ 6350 3500 6350 3650
+Connection ~ 6350 3650
+Wire Wire Line
+ 7400 3200 7400 3950
+Wire Wire Line
+ 6350 3600 7400 3600
+Connection ~ 7400 3600
+Connection ~ 6350 3600
+Wire Wire Line
+ 7900 3500 7900 3650
+Wire Wire Line
+ 6200 4250 6200 4300
+Wire Wire Line
+ 5500 4300 8000 4300
+Wire Wire Line
+ 7900 4300 7900 4250
+Wire Wire Line
+ 6500 4250 6500 4300
+Connection ~ 6500 4300
+Wire Wire Line
+ 6600 3950 6450 3950
+Wire Wire Line
+ 6450 3950 6450 4300
+Connection ~ 6450 4300
+Wire Wire Line
+ 6100 3950 6250 3950
+Wire Wire Line
+ 6250 3950 6250 4300
+Connection ~ 6250 4300
+Wire Wire Line
+ 6850 3200 7000 3200
+Wire Wire Line
+ 7000 3200 7000 3950
+Wire Wire Line
+ 5850 2500 5700 2500
+Wire Wire Line
+ 5700 2500 5700 3950
+Wire Wire Line
+ 6450 3200 6300 3200
+Wire Wire Line
+ 6300 3200 6300 2850
+Wire Wire Line
+ 6300 2850 6350 2850
+Connection ~ 6350 2850
+Wire Wire Line
+ 3550 2750 3900 2750
+Connection ~ 3650 2750
+Wire Wire Line
+ 3900 2750 3900 4350
+Wire Wire Line
+ 3900 4350 1650 4350
+Wire Wire Line
+ 1650 4350 1650 5450
+Wire Wire Line
+ 1650 5450 1750 5450
+Connection ~ 1750 5450
+Wire Wire Line
+ 1400 2200 1650 2200
+Connection ~ 1650 2200
+Wire Wire Line
+ 1500 2200 1500 4250
+Wire Wire Line
+ 1500 4250 3850 4250
+Wire Wire Line
+ 3850 4250 3850 5700
+Wire Wire Line
+ 3850 5700 3750 5700
+Connection ~ 3750 5700
+Connection ~ 1500 2200
+Wire Wire Line
+ 4500 2150 5700 2150
+Wire Wire Line
+ 5700 2150 5700 2550
+Connection ~ 5700 2550
+Connection ~ 4500 2150
+Wire Wire Line
+ 4600 5400 7100 5400
+Wire Wire Line
+ 7100 5400 7100 3700
+Wire Wire Line
+ 7100 3700 7000 3700
+Connection ~ 7000 3700
+Connection ~ 4600 5400
+Wire Wire Line
+ 4350 4600 4350 3450
+Wire Wire Line
+ 4350 3450 5550 3450
+Wire Wire Line
+ 5550 3450 5550 1350
+Wire Wire Line
+ 5550 1950 7050 1950
+Wire Wire Line
+ 7050 1950 7050 2200
+Connection ~ 7050 2200
+Connection ~ 4350 4600
+Connection ~ 5550 1950
+Connection ~ 4550 1350
+Wire Wire Line
+ 3900 1000 3900 1350
+Connection ~ 3900 1350
+Connection ~ 3000 3700
+Connection ~ 2200 2900
+Connection ~ 3050 3700
+Connection ~ 4550 2850
+Wire Wire Line
+ 5500 3700 5500 6200
+Connection ~ 6200 4300
+Connection ~ 4550 3700
+Connection ~ 3100 6950
+Connection ~ 2300 6150
+Connection ~ 3150 6950
+Connection ~ 4650 6100
+Wire Wire Line
+ 5500 6200 4650 6200
+Connection ~ 4650 6200
+Connection ~ 5500 4300
+Wire Wire Line
+ 8000 3550 7900 3550
+Connection ~ 7900 3550
+Text Label 3650 2750 0 60 ~ 0
+clock
+Text Label 1500 2200 0 60 ~ 0
+polarity
+Text Label 3900 1350 0 60 ~ 0
+Vdd
+Text Label 4550 3700 0 60 ~ 0
+Gnd
+Text Label 7900 3550 2 60 ~ 0
+Out
+Wire Wire Line
+ 7800 3950 8000 3950
+Wire Wire Line
+ 8000 3950 8000 4300
+Connection ~ 7900 4300
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.sub b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.sub
new file mode 100644
index 000000000..f359cdf7c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl.sub
@@ -0,0 +1,31 @@
+* Subcircuit TG_D_Latch_ctrl
+.subckt TG_D_Latch_ctrl /clock /polarity /vdd /gnd /out
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tg_d_latch_ctrl/tg_d_latch_ctrl.cir
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* s c m o d e
+xsc5 net-_sc10-pad1_ net-_sc1-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc10 net-_sc10-pad1_ /clock /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ /polarity /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc13 net-_sc13-pad1_ net-_sc10-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ /polarity /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc10-pad1_ net-_sc1-pad1_ net-_sc7-pad3_ net-_sc7-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc9 net-_sc7-pad3_ /clock /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc14 net-_sc13-pad1_ net-_sc10-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc12-pad1_ net-_sc3-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc12 net-_sc12-pad1_ /polarity /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc3-pad1_ /clock /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc15 net-_sc15-pad1_ net-_sc12-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc3-pad1_ /clock /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc8 net-_sc12-pad1_ net-_sc3-pad1_ net-_sc11-pad1_ net-_sc11-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc11 net-_sc11-pad1_ /polarity /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc16 net-_sc15-pad1_ net-_sc12-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc18 net-_sc18-pad1_ net-_sc13-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc19 net-_sc17-pad1_ net-_sc15-pad1_ net-_sc18-pad1_ net-_sc18-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc21 /out net-_sc17-pad1_ /vdd /vdd sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc17 net-_sc17-pad1_ net-_sc13-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc20 net-_sc17-pad1_ net-_sc15-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc22 /out net-_sc17-pad1_ /gnd /gnd sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends TG_D_Latch_ctrl
diff --git a/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl_Previous_Values.xml b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl_Previous_Values.xml
new file mode 100644
index 000000000..cb5bd44f4
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/TG_D_Latch_ctrl_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4042B/analysis b/library/SubcircuitLibrary/CD4042B/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4042B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4044BMS/CD4044BMS-cache.lib b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS-cache.lib
new file mode 100644
index 000000000..d9cac1d73
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS-cache.lib
@@ -0,0 +1,74 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# SR_Latch_with_Enable
+#
+DEF SR_Latch_with_Enable X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "SR_Latch_with_Enable" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -700 200 700 -250 0 1 0 N
+X Vdd 1 150 400 200 D 50 50 1 1 I
+X E 2 -900 0 200 R 50 50 1 1 I
+X Gnd 3 150 -450 200 U 50 50 1 1 I
+X S 4 -900 100 200 R 50 50 1 1 I
+X R 5 -900 -100 200 R 50 50 1 1 I
+X Q 6 900 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.bak b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.bak
new file mode 100644
index 000000000..9f31ea680
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.bak
@@ -0,0 +1,347 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SR_Latch_with_Enable X1
+U 1 1 684D0CC7
+P 4800 2250
+F 0 "X1" H 4800 2150 60 0000 C CNN
+F 1 "SR_Latch_with_Enable" H 4800 2250 60 0000 C CNN
+F 2 "" H 4800 2250 60 0001 C CNN
+F 3 "" H 4800 2250 60 0001 C CNN
+ 1 4800 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L SR_Latch_with_Enable X3
+U 1 1 684D0D13
+P 4900 3350
+F 0 "X3" H 4900 3250 60 0000 C CNN
+F 1 "SR_Latch_with_Enable" H 4900 3350 60 0000 C CNN
+F 2 "" H 4900 3350 60 0001 C CNN
+F 3 "" H 4900 3350 60 0001 C CNN
+ 1 4900 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SR_Latch_with_Enable X2
+U 1 1 684D0E52
+P 4800 4400
+F 0 "X2" H 4800 4300 60 0000 C CNN
+F 1 "SR_Latch_with_Enable" H 4800 4400 60 0000 C CNN
+F 2 "" H 4800 4400 60 0001 C CNN
+F 3 "" H 4800 4400 60 0001 C CNN
+ 1 4800 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L SR_Latch_with_Enable X4
+U 1 1 684D0EC6
+P 4900 5450
+F 0 "X4" H 4900 5350 60 0000 C CNN
+F 1 "SR_Latch_with_Enable" H 4900 5450 60 0000 C CNN
+F 2 "" H 4900 5450 60 0001 C CNN
+F 3 "" H 4900 5450 60 0001 C CNN
+ 1 4900 5450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 1850 4950 1800
+Wire Wire Line
+ 4800 1800 5250 1800
+Wire Wire Line
+ 4950 4000 5250 4000
+Wire Wire Line
+ 5050 5050 5250 5050
+Wire Wire Line
+ 5250 5050 5250 1800
+Wire Wire Line
+ 4950 2700 4850 2700
+Wire Wire Line
+ 4850 2700 4850 5900
+Wire Wire Line
+ 4750 5900 5050 5900
+Wire Wire Line
+ 5050 2950 5250 2950
+Connection ~ 5250 2950
+Connection ~ 5250 4000
+Wire Wire Line
+ 5050 3800 4850 3800
+Connection ~ 4850 3800
+Wire Wire Line
+ 4950 4850 4850 4850
+Connection ~ 4850 4850
+Wire Wire Line
+ 3500 2250 3900 2250
+Wire Wire Line
+ 3750 2250 3750 5450
+Wire Wire Line
+ 3750 5450 4000 5450
+Wire Wire Line
+ 4000 3350 3750 3350
+Connection ~ 3750 3350
+Wire Wire Line
+ 3900 4400 3750 4400
+Connection ~ 3750 4400
+$Comp
+L PORT U1
+U 1 1 684D11E5
+P 3250 2100
+F 0 "U1" H 3300 2200 30 0000 C CNN
+F 1 "PORT" H 3250 2100 30 0000 C CNN
+F 2 "" H 3250 2100 60 0000 C CNN
+F 3 "" H 3250 2100 60 0000 C CNN
+ 1 3250 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684D127E
+P 3250 2250
+F 0 "U1" H 3300 2350 30 0000 C CNN
+F 1 "PORT" H 3250 2250 30 0000 C CNN
+F 2 "" H 3250 2250 60 0000 C CNN
+F 3 "" H 3250 2250 60 0000 C CNN
+ 2 3250 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684D12F5
+P 3250 2400
+F 0 "U1" H 3300 2500 30 0000 C CNN
+F 1 "PORT" H 3250 2400 30 0000 C CNN
+F 2 "" H 3250 2400 60 0000 C CNN
+F 3 "" H 3250 2400 60 0000 C CNN
+ 3 3250 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684D137C
+P 3250 3250
+F 0 "U1" H 3300 3350 30 0000 C CNN
+F 1 "PORT" H 3250 3250 30 0000 C CNN
+F 2 "" H 3250 3250 60 0000 C CNN
+F 3 "" H 3250 3250 60 0000 C CNN
+ 4 3250 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684D13ED
+P 3250 3500
+F 0 "U1" H 3300 3600 30 0000 C CNN
+F 1 "PORT" H 3250 3500 30 0000 C CNN
+F 2 "" H 3250 3500 60 0000 C CNN
+F 3 "" H 3250 3500 60 0000 C CNN
+ 5 3250 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684D146A
+P 3250 4300
+F 0 "U1" H 3300 4400 30 0000 C CNN
+F 1 "PORT" H 3250 4300 30 0000 C CNN
+F 2 "" H 3250 4300 60 0000 C CNN
+F 3 "" H 3250 4300 60 0000 C CNN
+ 6 3250 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684D14DB
+P 3250 4500
+F 0 "U1" H 3300 4600 30 0000 C CNN
+F 1 "PORT" H 3250 4500 30 0000 C CNN
+F 2 "" H 3250 4500 60 0000 C CNN
+F 3 "" H 3250 4500 60 0000 C CNN
+ 7 3250 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 684D1556
+P 3250 5350
+F 0 "U1" H 3300 5450 30 0000 C CNN
+F 1 "PORT" H 3250 5350 30 0000 C CNN
+F 2 "" H 3250 5350 60 0000 C CNN
+F 3 "" H 3250 5350 60 0000 C CNN
+ 8 3250 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684D15BD
+P 3250 5550
+F 0 "U1" H 3300 5650 30 0000 C CNN
+F 1 "PORT" H 3250 5550 30 0000 C CNN
+F 2 "" H 3250 5550 60 0000 C CNN
+F 3 "" H 3250 5550 60 0000 C CNN
+ 9 3250 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 684D1863
+P 4550 1800
+F 0 "U1" H 4600 1900 30 0000 C CNN
+F 1 "PORT" H 4550 1800 30 0000 C CNN
+F 2 "" H 4550 1800 60 0000 C CNN
+F 3 "" H 4550 1800 60 0000 C CNN
+ 11 4550 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684D1972
+P 4500 5900
+F 0 "U1" H 4550 6000 30 0000 C CNN
+F 1 "PORT" H 4500 5900 30 0000 C CNN
+F 2 "" H 4500 5900 60 0000 C CNN
+F 3 "" H 4500 5900 60 0000 C CNN
+ 10 4500 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 684D1A91
+P 6050 2250
+F 0 "U1" H 6100 2350 30 0000 C CNN
+F 1 "PORT" H 6050 2250 30 0000 C CNN
+F 2 "" H 6050 2250 60 0000 C CNN
+F 3 "" H 6050 2250 60 0000 C CNN
+ 12 6050 2250
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 684D1B2C
+P 6150 3350
+F 0 "U1" H 6200 3450 30 0000 C CNN
+F 1 "PORT" H 6150 3350 30 0000 C CNN
+F 2 "" H 6150 3350 60 0000 C CNN
+F 3 "" H 6150 3350 60 0000 C CNN
+ 14 6150 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 684D1BE9
+P 6100 4400
+F 0 "U1" H 6150 4500 30 0000 C CNN
+F 1 "PORT" H 6100 4400 30 0000 C CNN
+F 2 "" H 6100 4400 60 0000 C CNN
+F 3 "" H 6100 4400 60 0000 C CNN
+ 13 6100 4400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 684D1C9A
+P 6200 5450
+F 0 "U1" H 6250 5550 30 0000 C CNN
+F 1 "PORT" H 6200 5450 30 0000 C CNN
+F 2 "" H 6200 5450 60 0000 C CNN
+F 3 "" H 6200 5450 60 0000 C CNN
+ 15 6200 5450
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3500 2100 3900 2100
+Wire Wire Line
+ 3900 2100 3900 2150
+Connection ~ 3750 2250
+Wire Wire Line
+ 3500 2400 3900 2400
+Wire Wire Line
+ 3900 2400 3900 2350
+Wire Wire Line
+ 3500 3250 4000 3250
+Wire Wire Line
+ 3500 3500 4000 3500
+Wire Wire Line
+ 4000 3500 4000 3450
+Wire Wire Line
+ 3500 4300 3900 4300
+Wire Wire Line
+ 3500 4500 3900 4500
+Wire Wire Line
+ 3500 5350 4000 5350
+Wire Wire Line
+ 3500 5550 4000 5550
+Connection ~ 4850 5900
+Connection ~ 4950 1800
+Wire Wire Line
+ 5700 2250 5800 2250
+Wire Wire Line
+ 5800 3350 5900 3350
+Wire Wire Line
+ 5700 4400 5850 4400
+Wire Wire Line
+ 5800 5450 5950 5450
+$Comp
+L SKY130mode scmode1
+U 1 1 684D28ED
+P 9050 3000
+F 0 "scmode1" H 9050 3150 98 0000 C CNB
+F 1 "SKY130mode" H 9050 2900 118 0000 C CNB
+F 2 "" H 9050 3150 60 0001 C CNN
+F 3 "" H 9050 3150 60 0001 C CNN
+ 1 9050 3000
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.cir b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.cir
new file mode 100644
index 000000000..9c554bbff
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 11:29:04 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad11_ Net-_U1-Pad2_ Net-_U1-Pad10_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad12_ SR_Latch_with_Enable
+X3 Net-_U1-Pad11_ Net-_U1-Pad2_ Net-_U1-Pad10_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad14_ SR_Latch_with_Enable
+X2 Net-_U1-Pad11_ Net-_U1-Pad2_ Net-_U1-Pad10_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad13_ SR_Latch_with_Enable
+X4 Net-_U1-Pad11_ Net-_U1-Pad2_ Net-_U1-Pad10_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad15_ SR_Latch_with_Enable
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.cir.out b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.cir.out
new file mode 100644
index 000000000..82478ce73
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.cir.out
@@ -0,0 +1,20 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cd4044bms/cd4044bms.cir
+
+.include SR_Latch_with_Enable.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad11_ net-_u1-pad2_ net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad12_ SR_Latch_with_Enable
+x3 net-_u1-pad11_ net-_u1-pad2_ net-_u1-pad10_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad14_ SR_Latch_with_Enable
+x2 net-_u1-pad11_ net-_u1-pad2_ net-_u1-pad10_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad13_ SR_Latch_with_Enable
+x4 net-_u1-pad11_ net-_u1-pad2_ net-_u1-pad10_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad15_ SR_Latch_with_Enable
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.pro b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.sch b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.sch
new file mode 100644
index 000000000..0ffe75c0f
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.sch
@@ -0,0 +1,348 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4044BMS-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SR_Latch_with_Enable X1
+U 1 1 684D0CC7
+P 4800 2250
+F 0 "X1" H 4800 2150 60 0000 C CNN
+F 1 "SR_Latch_with_Enable" H 4800 2250 60 0000 C CNN
+F 2 "" H 4800 2250 60 0001 C CNN
+F 3 "" H 4800 2250 60 0001 C CNN
+ 1 4800 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L SR_Latch_with_Enable X3
+U 1 1 684D0D13
+P 4900 3350
+F 0 "X3" H 4900 3250 60 0000 C CNN
+F 1 "SR_Latch_with_Enable" H 4900 3350 60 0000 C CNN
+F 2 "" H 4900 3350 60 0001 C CNN
+F 3 "" H 4900 3350 60 0001 C CNN
+ 1 4900 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SR_Latch_with_Enable X2
+U 1 1 684D0E52
+P 4800 4400
+F 0 "X2" H 4800 4300 60 0000 C CNN
+F 1 "SR_Latch_with_Enable" H 4800 4400 60 0000 C CNN
+F 2 "" H 4800 4400 60 0001 C CNN
+F 3 "" H 4800 4400 60 0001 C CNN
+ 1 4800 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L SR_Latch_with_Enable X4
+U 1 1 684D0EC6
+P 4900 5450
+F 0 "X4" H 4900 5350 60 0000 C CNN
+F 1 "SR_Latch_with_Enable" H 4900 5450 60 0000 C CNN
+F 2 "" H 4900 5450 60 0001 C CNN
+F 3 "" H 4900 5450 60 0001 C CNN
+ 1 4900 5450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 1850 4950 1800
+Wire Wire Line
+ 4800 1800 5250 1800
+Wire Wire Line
+ 4950 4000 5250 4000
+Wire Wire Line
+ 5050 5050 5250 5050
+Wire Wire Line
+ 5250 5050 5250 1800
+Wire Wire Line
+ 4950 2700 4850 2700
+Wire Wire Line
+ 4850 2700 4850 5900
+Wire Wire Line
+ 4750 5900 5050 5900
+Wire Wire Line
+ 5050 2950 5250 2950
+Connection ~ 5250 2950
+Connection ~ 5250 4000
+Wire Wire Line
+ 5050 3800 4850 3800
+Connection ~ 4850 3800
+Wire Wire Line
+ 4950 4850 4850 4850
+Connection ~ 4850 4850
+Wire Wire Line
+ 3500 2250 3900 2250
+Wire Wire Line
+ 3750 2250 3750 5450
+Wire Wire Line
+ 3750 5450 4000 5450
+Wire Wire Line
+ 4000 3350 3750 3350
+Connection ~ 3750 3350
+Wire Wire Line
+ 3900 4400 3750 4400
+Connection ~ 3750 4400
+$Comp
+L PORT U1
+U 1 1 684D11E5
+P 3250 2100
+F 0 "U1" H 3300 2200 30 0000 C CNN
+F 1 "PORT" H 3250 2100 30 0000 C CNN
+F 2 "" H 3250 2100 60 0000 C CNN
+F 3 "" H 3250 2100 60 0000 C CNN
+ 1 3250 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684D127E
+P 3250 2250
+F 0 "U1" H 3300 2350 30 0000 C CNN
+F 1 "PORT" H 3250 2250 30 0000 C CNN
+F 2 "" H 3250 2250 60 0000 C CNN
+F 3 "" H 3250 2250 60 0000 C CNN
+ 2 3250 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684D12F5
+P 3250 2400
+F 0 "U1" H 3300 2500 30 0000 C CNN
+F 1 "PORT" H 3250 2400 30 0000 C CNN
+F 2 "" H 3250 2400 60 0000 C CNN
+F 3 "" H 3250 2400 60 0000 C CNN
+ 3 3250 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684D137C
+P 3250 3250
+F 0 "U1" H 3300 3350 30 0000 C CNN
+F 1 "PORT" H 3250 3250 30 0000 C CNN
+F 2 "" H 3250 3250 60 0000 C CNN
+F 3 "" H 3250 3250 60 0000 C CNN
+ 4 3250 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684D13ED
+P 3250 3500
+F 0 "U1" H 3300 3600 30 0000 C CNN
+F 1 "PORT" H 3250 3500 30 0000 C CNN
+F 2 "" H 3250 3500 60 0000 C CNN
+F 3 "" H 3250 3500 60 0000 C CNN
+ 5 3250 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684D146A
+P 3250 4300
+F 0 "U1" H 3300 4400 30 0000 C CNN
+F 1 "PORT" H 3250 4300 30 0000 C CNN
+F 2 "" H 3250 4300 60 0000 C CNN
+F 3 "" H 3250 4300 60 0000 C CNN
+ 6 3250 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684D14DB
+P 3250 4500
+F 0 "U1" H 3300 4600 30 0000 C CNN
+F 1 "PORT" H 3250 4500 30 0000 C CNN
+F 2 "" H 3250 4500 60 0000 C CNN
+F 3 "" H 3250 4500 60 0000 C CNN
+ 7 3250 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 684D1556
+P 3250 5350
+F 0 "U1" H 3300 5450 30 0000 C CNN
+F 1 "PORT" H 3250 5350 30 0000 C CNN
+F 2 "" H 3250 5350 60 0000 C CNN
+F 3 "" H 3250 5350 60 0000 C CNN
+ 8 3250 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684D15BD
+P 3250 5550
+F 0 "U1" H 3300 5650 30 0000 C CNN
+F 1 "PORT" H 3250 5550 30 0000 C CNN
+F 2 "" H 3250 5550 60 0000 C CNN
+F 3 "" H 3250 5550 60 0000 C CNN
+ 9 3250 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 684D1863
+P 4550 1800
+F 0 "U1" H 4600 1900 30 0000 C CNN
+F 1 "PORT" H 4550 1800 30 0000 C CNN
+F 2 "" H 4550 1800 60 0000 C CNN
+F 3 "" H 4550 1800 60 0000 C CNN
+ 11 4550 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684D1972
+P 4500 5900
+F 0 "U1" H 4550 6000 30 0000 C CNN
+F 1 "PORT" H 4500 5900 30 0000 C CNN
+F 2 "" H 4500 5900 60 0000 C CNN
+F 3 "" H 4500 5900 60 0000 C CNN
+ 10 4500 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 684D1A91
+P 6050 2250
+F 0 "U1" H 6100 2350 30 0000 C CNN
+F 1 "PORT" H 6050 2250 30 0000 C CNN
+F 2 "" H 6050 2250 60 0000 C CNN
+F 3 "" H 6050 2250 60 0000 C CNN
+ 12 6050 2250
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 684D1B2C
+P 6150 3350
+F 0 "U1" H 6200 3450 30 0000 C CNN
+F 1 "PORT" H 6150 3350 30 0000 C CNN
+F 2 "" H 6150 3350 60 0000 C CNN
+F 3 "" H 6150 3350 60 0000 C CNN
+ 14 6150 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 684D1BE9
+P 6100 4400
+F 0 "U1" H 6150 4500 30 0000 C CNN
+F 1 "PORT" H 6100 4400 30 0000 C CNN
+F 2 "" H 6100 4400 60 0000 C CNN
+F 3 "" H 6100 4400 60 0000 C CNN
+ 13 6100 4400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 684D1C9A
+P 6200 5450
+F 0 "U1" H 6250 5550 30 0000 C CNN
+F 1 "PORT" H 6200 5450 30 0000 C CNN
+F 2 "" H 6200 5450 60 0000 C CNN
+F 3 "" H 6200 5450 60 0000 C CNN
+ 15 6200 5450
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3500 2100 3900 2100
+Wire Wire Line
+ 3900 2100 3900 2150
+Connection ~ 3750 2250
+Wire Wire Line
+ 3500 2400 3900 2400
+Wire Wire Line
+ 3900 2400 3900 2350
+Wire Wire Line
+ 3500 3250 4000 3250
+Wire Wire Line
+ 3500 3500 4000 3500
+Wire Wire Line
+ 4000 3500 4000 3450
+Wire Wire Line
+ 3500 4300 3900 4300
+Wire Wire Line
+ 3500 4500 3900 4500
+Wire Wire Line
+ 3500 5350 4000 5350
+Wire Wire Line
+ 3500 5550 4000 5550
+Connection ~ 4850 5900
+Connection ~ 4950 1800
+Wire Wire Line
+ 5700 2250 5800 2250
+Wire Wire Line
+ 5800 3350 5900 3350
+Wire Wire Line
+ 5700 4400 5850 4400
+Wire Wire Line
+ 5800 5450 5950 5450
+$Comp
+L SKY130mode scmode1
+U 1 1 684D28ED
+P 6950 3850
+F 0 "scmode1" H 6950 4000 98 0000 C CNB
+F 1 "SKY130mode" H 6950 3750 118 0000 C CNB
+F 2 "" H 6950 4000 60 0001 C CNN
+F 3 "" H 6950 4000 60 0001 C CNN
+ 1 6950 3850
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.sub b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.sub
new file mode 100644
index 000000000..a7ff0dd0d
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS.sub
@@ -0,0 +1,14 @@
+* Subcircuit CD4044BMS
+.subckt CD4044BMS net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cd4044bms/cd4044bms.cir
+.include SR_Latch_with_Enable.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad11_ net-_u1-pad2_ net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad12_ SR_Latch_with_Enable
+x3 net-_u1-pad11_ net-_u1-pad2_ net-_u1-pad10_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad14_ SR_Latch_with_Enable
+x2 net-_u1-pad11_ net-_u1-pad2_ net-_u1-pad10_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad13_ SR_Latch_with_Enable
+x4 net-_u1-pad11_ net-_u1-pad2_ net-_u1-pad10_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad15_ SR_Latch_with_Enable
+* s c m o d e
+* Control Statements
+
+.ends CD4044BMS
diff --git a/library/SubcircuitLibrary/CD4044BMS/CD4044BMS_Previous_Values.xml b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS_Previous_Values.xml
new file mode 100644
index 000000000..4e264fc18
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CD4044BMS_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SR_Latch_with_Enable/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SR_Latch_with_Enable/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SR_Latch_with_Enable/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SR_Latch_with_Enable
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR-cache.lib b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.cir b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.cir
new file mode 100644
index 000000000..d2199ddbb
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/CMOS_INVTR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 13 08:49:20 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.cir.out b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.cir.out
new file mode 100644
index 000000000..dec1c5fa5
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.pro b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.sch b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.sch
new file mode 100644
index 000000000..aa7a7ee81
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.sch
@@ -0,0 +1,161 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 684B982F
+P 5350 2950
+F 0 "SC1" H 5400 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 3037 50 0000 R CNN
+F 2 "" H 5350 1450 50 0001 C CNN
+F 3 "" H 5350 2950 50 0001 C CNN
+ 1 5350 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684B9856
+P 5350 3800
+F 0 "SC2" H 5400 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5650 3887 50 0000 R CNN
+F 2 "" H 5350 2300 50 0001 C CNN
+F 3 "" H 5350 3800 50 0001 C CNN
+ 1 5350 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B98AD
+P 4550 3300
+F 0 "U1" H 4600 3400 30 0000 C CNN
+F 1 "PORT" H 4550 3300 30 0000 C CNN
+F 2 "" H 4550 3300 60 0000 C CNN
+F 3 "" H 4550 3300 60 0000 C CNN
+ 1 4550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B98D8
+P 6300 3350
+F 0 "U1" H 6350 3450 30 0000 C CNN
+F 1 "PORT" H 6300 3350 30 0000 C CNN
+F 2 "" H 6300 3350 60 0000 C CNN
+F 3 "" H 6300 3350 60 0000 C CNN
+ 4 6300 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B9935
+P 5300 4350
+F 0 "U1" H 5350 4450 30 0000 C CNN
+F 1 "PORT" H 5300 4350 30 0000 C CNN
+F 2 "" H 5300 4350 60 0000 C CNN
+F 3 "" H 5300 4350 60 0000 C CNN
+ 3 5300 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B999A
+P 5300 2350
+F 0 "U1" H 5350 2450 30 0000 C CNN
+F 1 "PORT" H 5300 2350 30 0000 C CNN
+F 2 "" H 5300 2350 60 0000 C CNN
+F 3 "" H 5300 2350 60 0000 C CNN
+ 2 5300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B99CD
+P 7950 3000
+F 0 "scmode1" H 7950 3150 98 0000 C CNB
+F 1 "SKY130mode" H 7950 2900 118 0000 C CNB
+F 2 "" H 7950 3150 60 0001 C CNN
+F 3 "" H 7950 3150 60 0001 C CNN
+ 1 7950 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 2650 5550 2350
+Wire Wire Line
+ 5450 2950 5600 2950
+Wire Wire Line
+ 5600 2950 5600 2550
+Wire Wire Line
+ 5600 2550 5550 2550
+Connection ~ 5550 2550
+Wire Wire Line
+ 5550 3250 5550 3500
+Wire Wire Line
+ 6050 3350 5550 3350
+Connection ~ 5550 3350
+Wire Wire Line
+ 5050 2950 5050 3800
+Wire Wire Line
+ 4800 3300 5050 3300
+Connection ~ 5050 3300
+Wire Wire Line
+ 5450 3800 5600 3800
+Wire Wire Line
+ 5600 3800 5600 4150
+Wire Wire Line
+ 5600 4150 5550 4150
+Wire Wire Line
+ 5550 4100 5550 4350
+Connection ~ 5550 4150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.sub b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.sub
new file mode 100644
index 000000000..8283bca86
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR.sub
@@ -0,0 +1,11 @@
+* Subcircuit CMOS_INVTR
+.subckt CMOS_INVTR net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends CMOS_INVTR
diff --git a/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR_Previous_Values.xml b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR_Previous_Values.xml
new file mode 100644
index 000000000..d17c4f93e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/CMOS_INVTR_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3, l=0.15w=1, l=0.15
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_2-cache.lib b/library/SubcircuitLibrary/CD4044BMS/NAND_2-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_2-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_2.bak b/library/SubcircuitLibrary/CD4044BMS/NAND_2.bak
new file mode 100644
index 000000000..ad9819396
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_2.bak
@@ -0,0 +1,221 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684AF0E9
+P 4750 2050
+F 0 "SC2" H 4800 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5050 2137 50 0000 R CNN
+F 2 "" H 4750 550 50 0001 C CNN
+F 3 "" H 4750 2050 50 0001 C CNN
+ 1 4750 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF14C
+P 5150 2750
+F 0 "SC3" H 5200 3050 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 2837 50 0000 R CNN
+F 2 "" H 5150 1250 50 0001 C CNN
+F 3 "" H 5150 2750 50 0001 C CNN
+ 1 5150 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF1CF
+P 4200 3600
+F 0 "SC1" H 4250 3900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4500 3687 50 0000 R CNN
+F 2 "" H 4200 2100 50 0001 C CNN
+F 3 "" H 4200 3600 50 0001 C CNN
+ 1 4200 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684AF20C
+P 5550 3600
+F 0 "SC4" H 5600 3900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5850 3687 50 0000 R CNN
+F 2 "" H 5550 2100 50 0001 C CNN
+F 3 "" H 5550 3600 50 0001 C CNN
+ 1 5550 3600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF271
+P 4650 1550
+F 0 "U1" H 4700 1650 30 0000 C CNN
+F 1 "PORT" H 4650 1550 30 0000 C CNN
+F 2 "" H 4650 1550 60 0000 C CNN
+F 3 "" H 4650 1550 60 0000 C CNN
+ 3 4650 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF336
+P 3550 2650
+F 0 "U1" H 3600 2750 30 0000 C CNN
+F 1 "PORT" H 3550 2650 30 0000 C CNN
+F 2 "" H 3550 2650 60 0000 C CNN
+F 3 "" H 3550 2650 60 0000 C CNN
+ 1 3550 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AF413
+P 6200 2750
+F 0 "U1" H 6250 2850 30 0000 C CNN
+F 1 "PORT" H 6200 2750 30 0000 C CNN
+F 2 "" H 6200 2750 60 0000 C CNN
+F 3 "" H 6200 2750 60 0000 C CNN
+ 4 6200 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF82C
+P 6200 3150
+F 0 "U1" H 6250 3250 30 0000 C CNN
+F 1 "PORT" H 6200 3150 30 0000 C CNN
+F 2 "" H 6200 3150 60 0000 C CNN
+F 3 "" H 6200 3150 60 0000 C CNN
+ 5 6200 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF895
+P 4550 4050
+F 0 "U1" H 4600 4150 30 0000 C CNN
+F 1 "PORT" H 4550 4050 30 0000 C CNN
+F 2 "" H 4550 4050 60 0000 C CNN
+F 3 "" H 4550 4050 60 0000 C CNN
+ 2 4550 4050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 3900 5350 3900
+Wire Wire Line
+ 4800 4050 4800 3900
+Connection ~ 4800 3900
+Wire Wire Line
+ 4300 3600 4450 3600
+Wire Wire Line
+ 4450 3600 4450 3900
+Connection ~ 4450 3900
+Wire Wire Line
+ 5450 3600 5300 3600
+Wire Wire Line
+ 5300 3600 5300 3900
+Connection ~ 5300 3900
+Wire Wire Line
+ 4400 3300 5350 3300
+Wire Wire Line
+ 4950 3050 4950 3300
+Connection ~ 4950 3300
+Wire Wire Line
+ 5950 3150 4950 3150
+Connection ~ 4950 3150
+Wire Wire Line
+ 5450 2750 5950 2750
+Wire Wire Line
+ 5850 2750 5850 3600
+Wire Wire Line
+ 5050 2750 4900 2750
+Wire Wire Line
+ 4900 2750 4900 2400
+Wire Wire Line
+ 4900 2400 4950 2400
+Wire Wire Line
+ 4950 2350 4950 2450
+Connection ~ 4950 2400
+Wire Wire Line
+ 4450 2050 3900 2050
+Wire Wire Line
+ 3900 2050 3900 3600
+Wire Wire Line
+ 3800 2650 3900 2650
+Connection ~ 3900 2650
+Connection ~ 5850 2750
+Wire Wire Line
+ 4850 2050 5000 2050
+Wire Wire Line
+ 5000 2050 5000 1650
+Wire Wire Line
+ 5000 1650 4950 1650
+Wire Wire Line
+ 4950 1550 4950 1750
+Wire Wire Line
+ 4900 1550 4950 1550
+Connection ~ 4950 1650
+$Comp
+L SKY130mode scmode1
+U 1 1 684AFD6B
+P 7350 2150
+F 0 "scmode1" H 7350 2300 98 0000 C CNB
+F 1 "SKY130mode" H 7350 2050 118 0000 C CNB
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2150
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_2.cir b/library/SubcircuitLibrary/CD4044BMS/NAND_2.cir
new file mode 100644
index 000000000..1fa1e05e8
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_2.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/NAND_2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 09:19:59 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC1-Pad3_ Net-_SC3-Pad2_ Net-_SC4-Pad3_ Net-_SC4-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC4-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ Net-_SC3-Pad2_ PORT
+scmode1 SKY130mode
+SC3 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_2.cir.out b/library/SubcircuitLibrary/CD4044BMS/NAND_2.cir.out
new file mode 100644
index 000000000..079b2d2c2
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_2.cir.out
@@ -0,0 +1,19 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_2/nand_2.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad3_ net-_sc3-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc4-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ net-_sc3-pad2_ port
+* s c m o d e
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_2.pro b/library/SubcircuitLibrary/CD4044BMS/NAND_2.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_2.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_2.sch b/library/SubcircuitLibrary/CD4044BMS/NAND_2.sch
new file mode 100644
index 000000000..ebef1d4c6
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_2.sch
@@ -0,0 +1,222 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:NAND_2-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684AF0E9
+P 4200 2050
+F 0 "SC2" H 4250 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4500 2137 50 0000 R CNN
+F 2 "" H 4200 550 50 0001 C CNN
+F 3 "" H 4200 2050 50 0001 C CNN
+ 1 4200 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF1CF
+P 4450 2850
+F 0 "SC1" H 4500 3150 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4750 2937 50 0000 R CNN
+F 2 "" H 4450 1350 50 0001 C CNN
+F 3 "" H 4450 2850 50 0001 C CNN
+ 1 4450 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684AF20C
+P 4850 3550
+F 0 "SC4" H 4900 3850 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5150 3637 50 0000 R CNN
+F 2 "" H 4850 2050 50 0001 C CNN
+F 3 "" H 4850 3550 50 0001 C CNN
+ 1 4850 3550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF271
+P 4350 1550
+F 0 "U1" H 4400 1650 30 0000 C CNN
+F 1 "PORT" H 4350 1550 30 0000 C CNN
+F 2 "" H 4350 1550 60 0000 C CNN
+F 3 "" H 4350 1550 60 0000 C CNN
+ 3 4350 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF336
+P 3550 2650
+F 0 "U1" H 3600 2750 30 0000 C CNN
+F 1 "PORT" H 3550 2650 30 0000 C CNN
+F 2 "" H 3550 2650 60 0000 C CNN
+F 3 "" H 3550 2650 60 0000 C CNN
+ 1 3550 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AF413
+P 5750 2450
+F 0 "U1" H 5800 2550 30 0000 C CNN
+F 1 "PORT" H 5750 2450 30 0000 C CNN
+F 2 "" H 5750 2450 60 0000 C CNN
+F 3 "" H 5750 2450 60 0000 C CNN
+ 4 5750 2450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF82C
+P 5750 3300
+F 0 "U1" H 5800 3400 30 0000 C CNN
+F 1 "PORT" H 5750 3300 30 0000 C CNN
+F 2 "" H 5750 3300 60 0000 C CNN
+F 3 "" H 5750 3300 60 0000 C CNN
+ 5 5750 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF895
+P 4400 4000
+F 0 "U1" H 4450 4100 30 0000 C CNN
+F 1 "PORT" H 4400 4000 30 0000 C CNN
+F 2 "" H 4400 4000 60 0000 C CNN
+F 3 "" H 4400 4000 60 0000 C CNN
+ 2 4400 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684AFD6B
+P 7350 2150
+F 0 "scmode1" H 7350 2300 98 0000 C CNB
+F 1 "SKY130mode" H 7350 2050 118 0000 C CNB
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684CF41D
+P 5000 2050
+F 0 "SC3" H 5050 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5300 2137 50 0000 R CNN
+F 2 "" H 5000 550 50 0001 C CNN
+F 3 "" H 5000 2050 50 0001 C CNN
+ 1 5000 2050
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 1750 4800 1750
+Wire Wire Line
+ 4600 1550 4600 1750
+Connection ~ 4600 1750
+Wire Wire Line
+ 4300 2050 4450 2050
+Wire Wire Line
+ 4450 2050 4450 1750
+Connection ~ 4450 1750
+Wire Wire Line
+ 4900 2050 4750 2050
+Wire Wire Line
+ 4750 2050 4750 1750
+Connection ~ 4750 1750
+Wire Wire Line
+ 4400 2350 4800 2350
+Wire Wire Line
+ 4650 2550 4650 2350
+Connection ~ 4650 2350
+Wire Wire Line
+ 5500 2450 4650 2450
+Connection ~ 4650 2450
+Wire Wire Line
+ 3900 2050 3900 2850
+Wire Wire Line
+ 3900 2850 4150 2850
+Wire Wire Line
+ 3800 2650 3900 2650
+Connection ~ 3900 2650
+Wire Wire Line
+ 5300 2050 5300 3550
+Wire Wire Line
+ 5300 3550 5150 3550
+Wire Wire Line
+ 5500 3300 5300 3300
+Connection ~ 5300 3300
+Wire Wire Line
+ 4550 2850 4700 2850
+Wire Wire Line
+ 4700 2850 4700 3200
+Wire Wire Line
+ 4700 3200 4650 3200
+Wire Wire Line
+ 4650 3150 4650 3250
+Connection ~ 4650 3200
+Wire Wire Line
+ 4650 3850 4650 4000
+Wire Wire Line
+ 4750 3550 4600 3550
+Wire Wire Line
+ 4600 3550 4600 3900
+Wire Wire Line
+ 4600 3900 4650 3900
+Connection ~ 4650 3900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_2.sub b/library/SubcircuitLibrary/CD4044BMS/NAND_2.sub
new file mode 100644
index 000000000..47d0bd150
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_2.sub
@@ -0,0 +1,13 @@
+* Subcircuit NAND_2
+.subckt NAND_2 net-_sc1-pad2_ net-_sc4-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ net-_sc3-pad2_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_2/nand_2.cir
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad3_ net-_sc3-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+* Control Statements
+
+.ends NAND_2
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_2_Previous_Values.xml b/library/SubcircuitLibrary/CD4044BMS/NAND_2_Previous_Values.xml
new file mode 100644
index 000000000..066d43a60
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_2_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_Latch-cache.lib b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch-cache.lib
new file mode 100644
index 000000000..b11550ee7
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch-cache.lib
@@ -0,0 +1,95 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 100 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -450 250 500 0 N
+P 3 0 1 0 -450 250 -450 -250 500 0 N
+X IN 1 -650 0 200 R 50 50 1 1 I
+X VDD 2 -650 150 200 R 50 50 1 1 I
+X GND 3 -650 -150 200 R 50 50 1 1 I
+X OUT 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NOR_2
+#
+DEF NOR_2 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "NOR_2" 250 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A -350 0 269 682 -682 0 1 0 N -250 250 -250 -250
+A 250 0 255 787 -787 0 1 0 N 300 250 300 -250
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -250 -250 300 -250 N
+P 2 0 1 0 -250 250 300 250 N
+X inA 1 -350 150 200 R 50 50 1 1 I
+X Gnd 2 100 -450 200 U 50 50 1 1 I
+X Vdd 3 100 450 200 D 50 50 1 1 I
+X inB 4 -350 -150 200 R 50 50 1 1 I
+X Out 5 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.cir b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.cir
new file mode 100644
index 000000000..94ba828a9
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_Latch/NAND_Latch.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 10:44:18 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_X1-Pad4_ CMOS_INVTR
+X2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_X2-Pad4_ CMOS_INVTR
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+X3 Net-_X1-Pad4_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_X3-Pad5_ NOR_2
+X4 Net-_X2-Pad4_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_X3-Pad5_ Net-_U1-Pad5_ NOR_2
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.cir.out b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.cir.out
new file mode 100644
index 000000000..f6273ea71
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.cir.out
@@ -0,0 +1,21 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_latch/nand_latch.cir
+
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x2-pad4_ CMOS_INVTR
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+x3 net-_x1-pad4_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad5_ net-_x3-pad5_ NOR_2
+x4 net-_x2-pad4_ net-_u1-pad4_ net-_u1-pad3_ net-_x3-pad5_ net-_u1-pad5_ NOR_2
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.pro b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.sch b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.sch
new file mode 100644
index 000000000..3fec24072
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.sch
@@ -0,0 +1,227 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CMOS_INVTR X1
+U 1 1 684D03CB
+P 2950 1900
+F 0 "X1" H 2950 1900 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3050 1650 60 0000 C CNN
+F 2 "" H 2950 1900 60 0001 C CNN
+F 3 "" H 2950 1900 60 0001 C CNN
+ 1 2950 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 684D041E
+P 2950 3450
+F 0 "X2" H 2950 3450 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3050 3200 60 0000 C CNN
+F 2 "" H 2950 3450 60 0001 C CNN
+F 3 "" H 2950 3450 60 0001 C CNN
+ 1 2950 3450
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 3750 1900 4650 1900
+Wire Wire Line
+ 3750 3450 4600 3450
+Wire Wire Line
+ 4450 2100 4650 2100
+Wire Wire Line
+ 4450 2100 4450 2650
+Wire Wire Line
+ 4450 2650 6200 2650
+Wire Wire Line
+ 6200 2650 6200 3350
+Wire Wire Line
+ 5800 3350 6500 3350
+Wire Wire Line
+ 4600 2750 6050 2750
+Wire Wire Line
+ 6050 2750 6050 2000
+Wire Wire Line
+ 5100 2450 5100 2900
+Wire Wire Line
+ 2300 1750 2300 1550
+Wire Wire Line
+ 2250 1550 5100 1550
+Wire Wire Line
+ 2300 2050 2300 3300
+Wire Wire Line
+ 5100 2700 2300 2700
+Connection ~ 2300 2700
+Connection ~ 5100 2700
+Wire Wire Line
+ 2300 3600 2300 3800
+Wire Wire Line
+ 2300 3800 5100 3800
+Wire Wire Line
+ 4300 3800 4300 1550
+Connection ~ 4300 1550
+Connection ~ 4300 3800
+Wire Wire Line
+ 2300 1900 2050 1900
+Wire Wire Line
+ 2300 3450 2050 3450
+Connection ~ 6200 3350
+$Comp
+L PORT U1
+U 3 1 684D08A2
+P 2000 1550
+F 0 "U1" H 2050 1650 30 0000 C CNN
+F 1 "PORT" H 2000 1550 30 0000 C CNN
+F 2 "" H 2000 1550 60 0000 C CNN
+F 3 "" H 2000 1550 60 0000 C CNN
+ 3 2000 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684D0939
+P 1800 1900
+F 0 "U1" H 1850 2000 30 0000 C CNN
+F 1 "PORT" H 1800 1900 30 0000 C CNN
+F 2 "" H 1800 1900 60 0000 C CNN
+F 3 "" H 1800 1900 60 0000 C CNN
+ 1 1800 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684D09DE
+P 1800 3450
+F 0 "U1" H 1850 3550 30 0000 C CNN
+F 1 "PORT" H 1800 3450 30 0000 C CNN
+F 2 "" H 1800 3450 60 0000 C CNN
+F 3 "" H 1800 3450 60 0000 C CNN
+ 2 1800 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684D0A71
+P 3150 2800
+F 0 "U1" H 3200 2900 30 0000 C CNN
+F 1 "PORT" H 3150 2800 30 0000 C CNN
+F 2 "" H 3150 2800 60 0000 C CNN
+F 3 "" H 3150 2800 60 0000 C CNN
+ 4 3150 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684D0B22
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3400 2800 3400 2700
+Connection ~ 3400 2700
+Connection ~ 2300 1550
+$Comp
+L NOR_2 X3
+U 1 1 684D0C9D
+P 5000 2000
+F 0 "X3" H 5000 2000 60 0000 C CNN
+F 1 "NOR_2" H 5250 2000 60 0000 C CNN
+F 2 "" H 5000 2000 60 0001 C CNN
+F 3 "" H 5000 2000 60 0001 C CNN
+ 1 5000 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_2 X4
+U 1 1 684D0CE7
+P 5000 3350
+F 0 "X4" H 5000 3350 60 0000 C CNN
+F 1 "NOR_2" H 5250 3350 60 0000 C CNN
+F 2 "" H 5000 3350 60 0001 C CNN
+F 3 "" H 5000 3350 60 0001 C CNN
+ 1 5000 3350
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 6050 2000 5800 2000
+Wire Wire Line
+ 4600 3450 4600 3500
+Wire Wire Line
+ 4600 3500 4650 3500
+Wire Wire Line
+ 4600 3200 4650 3200
+Wire Wire Line
+ 4600 3200 4600 2750
+Wire Wire Line
+ 4650 1900 4650 1850
+Wire Wire Line
+ 4650 2100 4650 2150
+$Comp
+L SKY130mode scmode1
+U 1 1 684D1002
+P 7050 1900
+F 0 "scmode1" H 7050 2050 98 0000 C CNB
+F 1 "SKY130mode" H 7050 1800 118 0000 C CNB
+F 2 "" H 7050 2050 60 0001 C CNN
+F 3 "" H 7050 2050 60 0001 C CNN
+ 1 7050 1900
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.sub b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.sub
new file mode 100644
index 000000000..e74e79ca2
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch.sub
@@ -0,0 +1,15 @@
+* Subcircuit NAND_Latch
+.subckt NAND_Latch net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_latch/nand_latch.cir
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_x2-pad4_ CMOS_INVTR
+x3 net-_x1-pad4_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad5_ net-_x3-pad5_ NOR_2
+x4 net-_x2-pad4_ net-_u1-pad4_ net-_u1-pad3_ net-_x3-pad5_ net-_u1-pad5_ NOR_2
+* s c m o d e
+* Control Statements
+
+.ends NAND_Latch
diff --git a/library/SubcircuitLibrary/CD4044BMS/NAND_Latch_Previous_Values.xml b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch_Previous_Values.xml
new file mode 100644
index 000000000..e72df0e2c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NAND_Latch_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_2
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4044BMS/NOR_2-cache.lib b/library/SubcircuitLibrary/CD4044BMS/NOR_2-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NOR_2-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4044BMS/NOR_2.cir b/library/SubcircuitLibrary/CD4044BMS/NOR_2.cir
new file mode 100644
index 000000000..da83808c0
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NOR_2.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_2/NOR_2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 08:53:12 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC2 Net-_SC2-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+SC3 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC2-Pad1_ Net-_SC2-Pad1_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC3-Pad2_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/NOR_2.cir.out b/library/SubcircuitLibrary/CD4044BMS/NOR_2.cir.out
new file mode 100644
index 000000000..4326af445
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NOR_2.cir.out
@@ -0,0 +1,19 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nor_2/nor_2.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc2 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad1_ net-_sc2-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/NOR_2.pro b/library/SubcircuitLibrary/CD4044BMS/NOR_2.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NOR_2.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4044BMS/NOR_2.sch b/library/SubcircuitLibrary/CD4044BMS/NOR_2.sch
new file mode 100644
index 000000000..86f7c4bc6
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NOR_2.sch
@@ -0,0 +1,219 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684CE7B8
+P 4750 2600
+F 0 "SC2" H 4800 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5050 2687 50 0000 R CNN
+F 2 "" H 4750 1100 50 0001 C CNN
+F 3 "" H 4750 2600 50 0001 C CNN
+ 1 4750 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684CE82E
+P 5150 3400
+F 0 "SC3" H 5200 3700 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 3487 50 0000 R CNN
+F 2 "" H 5150 1900 50 0001 C CNN
+F 3 "" H 5150 3400 50 0001 C CNN
+ 1 5150 3400
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684CE88F
+P 4050 4450
+F 0 "SC1" H 4100 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4350 4537 50 0000 R CNN
+F 2 "" H 4050 2950 50 0001 C CNN
+F 3 "" H 4050 4450 50 0001 C CNN
+ 1 4050 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684CE8CA
+P 5650 4450
+F 0 "SC4" H 5700 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5950 4537 50 0000 R CNN
+F 2 "" H 5650 2950 50 0001 C CNN
+F 3 "" H 5650 4450 50 0001 C CNN
+ 1 5650 4450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684CE919
+P 3100 3450
+F 0 "U1" H 3150 3550 30 0000 C CNN
+F 1 "PORT" H 3100 3450 30 0000 C CNN
+F 2 "" H 3100 3450 60 0000 C CNN
+F 3 "" H 3100 3450 60 0000 C CNN
+ 1 3100 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684CE990
+P 6350 3400
+F 0 "U1" H 6400 3500 30 0000 C CNN
+F 1 "PORT" H 6350 3400 30 0000 C CNN
+F 2 "" H 6350 3400 60 0000 C CNN
+F 3 "" H 6350 3400 60 0000 C CNN
+ 4 6350 3400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684CEA11
+P 6450 3900
+F 0 "U1" H 6500 4000 30 0000 C CNN
+F 1 "PORT" H 6450 3900 30 0000 C CNN
+F 2 "" H 6450 3900 60 0000 C CNN
+F 3 "" H 6450 3900 60 0000 C CNN
+ 5 6450 3900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684CEA84
+P 4700 2150
+F 0 "U1" H 4750 2250 30 0000 C CNN
+F 1 "PORT" H 4700 2150 30 0000 C CNN
+F 2 "" H 4700 2150 60 0000 C CNN
+F 3 "" H 4700 2150 60 0000 C CNN
+ 3 4700 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684CEB11
+P 4650 5100
+F 0 "U1" H 4700 5200 30 0000 C CNN
+F 1 "PORT" H 4650 5100 30 0000 C CNN
+F 2 "" H 4650 5100 60 0000 C CNN
+F 3 "" H 4650 5100 60 0000 C CNN
+ 2 4650 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684CEB6E
+P 8300 2900
+F 0 "scmode1" H 8300 3050 98 0000 C CNB
+F 1 "SKY130mode" H 8300 2800 118 0000 C CNB
+F 2 "" H 8300 3050 60 0001 C CNN
+F 3 "" H 8300 3050 60 0001 C CNN
+ 1 8300 2900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4250 4150 5450 4150
+Wire Wire Line
+ 4950 3700 4950 4150
+Connection ~ 4950 4150
+Wire Wire Line
+ 6200 3900 4950 3900
+Connection ~ 4950 3900
+Wire Wire Line
+ 4250 4750 5450 4750
+Wire Wire Line
+ 5550 4450 5400 4450
+Wire Wire Line
+ 5400 4450 5400 4750
+Connection ~ 5400 4750
+Wire Wire Line
+ 4150 4450 4300 4450
+Wire Wire Line
+ 4300 4450 4300 4750
+Connection ~ 4300 4750
+Wire Wire Line
+ 4900 5100 4900 4750
+Connection ~ 4900 4750
+Wire Wire Line
+ 5450 3400 6100 3400
+Wire Wire Line
+ 5950 3400 5950 4450
+Connection ~ 5950 3400
+Wire Wire Line
+ 4450 2600 3750 2600
+Wire Wire Line
+ 3750 2600 3750 4450
+Wire Wire Line
+ 3350 3450 3750 3450
+Connection ~ 3750 3450
+Wire Wire Line
+ 4950 2150 4950 2300
+Wire Wire Line
+ 4850 2600 5000 2600
+Wire Wire Line
+ 5000 2600 5000 2250
+Wire Wire Line
+ 5000 2250 4950 2250
+Connection ~ 4950 2250
+Wire Wire Line
+ 4950 2900 4950 3100
+Wire Wire Line
+ 5050 3400 4900 3400
+Wire Wire Line
+ 4900 3400 4900 3050
+Wire Wire Line
+ 4900 3050 4950 3050
+Connection ~ 4950 3050
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4044BMS/NOR_2.sub b/library/SubcircuitLibrary/CD4044BMS/NOR_2.sub
new file mode 100644
index 000000000..dd148089f
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NOR_2.sub
@@ -0,0 +1,13 @@
+* Subcircuit NOR_2
+.subckt NOR_2 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nor_2/nor_2.cir
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc2 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad1_ net-_sc2-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends NOR_2
diff --git a/library/SubcircuitLibrary/CD4044BMS/NOR_2_Previous_Values.xml b/library/SubcircuitLibrary/CD4044BMS/NOR_2_Previous_Values.xml
new file mode 100644
index 000000000..a8736d2ca
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/NOR_2_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable-cache.lib b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable-cache.lib
new file mode 100644
index 000000000..b0ad0d0ae
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable-cache.lib
@@ -0,0 +1,187 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 100 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -450 250 500 0 N
+P 3 0 1 0 -450 250 -450 -250 500 0 N
+X IN 1 -650 0 200 R 50 50 1 1 I
+X VDD 2 -650 150 200 R 50 50 1 1 I
+X GND 3 -650 -150 200 R 50 50 1 1 I
+X OUT 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NAND_2
+#
+DEF NAND_2 X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "NAND_2" 400 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 400 0 255 787 -787 0 1 0 N 450 250 450 -250
+C 700 0 0 0 1 0 N
+C 700 0 50 0 1 0 N
+P 2 0 1 0 -300 250 450 250 N
+P 3 0 1 0 -300 250 -300 -250 450 -250 N
+X inA 1 -500 100 200 R 50 50 1 1 I
+X Gnd 2 0 -450 200 U 50 50 1 1 I
+X Vdd 3 0 450 200 D 50 50 1 1 I
+X Out 4 950 0 200 L 50 50 1 1 O
+X inB 5 -500 -100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# NAND_Latch
+#
+DEF NAND_Latch X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "NAND_Latch" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 200 450 -200 0 1 0 N
+X S 1 -500 100 200 R 50 50 1 1 I
+X R 2 -500 -100 200 R 50 50 1 1 I
+X Vdd 3 100 400 200 D 50 50 1 1 I
+X Gnd 4 100 -400 200 U 50 50 1 1 I
+X Q 5 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NOR_2
+#
+DEF NOR_2 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "NOR_2" 250 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A -350 0 269 682 -682 0 1 0 N -250 250 -250 -250
+A 250 0 255 787 -787 0 1 0 N 300 250 300 -250
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -250 -250 300 -250 N
+P 2 0 1 0 -250 250 300 250 N
+X inA 1 -350 150 200 R 50 50 1 1 I
+X Gnd 2 100 -450 200 U 50 50 1 1 I
+X Vdd 3 100 450 200 D 50 50 1 1 I
+X inB 4 -350 -150 200 R 50 50 1 1 I
+X Out 5 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.bak b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.bak
new file mode 100644
index 000000000..0049e35ef
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.bak
@@ -0,0 +1,308 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NAND_Latch X?
+U 1 1 684D0904
+P 5400 2850
+F 0 "X?" H 5400 2750 60 0000 C CNN
+F 1 "NAND_Latch" H 5400 2850 60 0000 C CNN
+F 2 "" H 5400 2850 60 0001 C CNN
+F 3 "" H 5400 2850 60 0001 C CNN
+ 1 5400 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X?
+U 1 1 684D097B
+P 6700 2400
+F 0 "X?" H 6800 2400 60 0000 C CNN
+F 1 "NAND_2" H 7100 2400 60 0000 C CNN
+F 2 "" H 6700 2400 60 0001 C CNN
+F 3 "" H 6700 2400 60 0001 C CNN
+ 1 6700 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_2 X?
+U 1 1 684D09D8
+P 6600 3500
+F 0 "X?" H 6600 3500 60 0000 C CNN
+F 1 "NOR_2" H 6850 3500 60 0000 C CNN
+F 2 "" H 6600 3500 60 0001 C CNN
+F 3 "" H 6600 3500 60 0001 C CNN
+ 1 6600 3500
+ 1 0 0 1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC?
+U 1 1 684D0A0D
+P 8300 2400
+F 0 "SC?" H 8350 2700 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 8600 2487 50 0000 R CNN
+F 2 "" H 8300 900 50 0001 C CNN
+F 3 "" H 8300 2400 50 0001 C CNN
+ 1 8300 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 684D0A4E
+P 8300 3500
+F 0 "SC?" H 8350 3800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 8600 3587 50 0000 R CNN
+F 2 "" H 8300 2000 50 0001 C CNN
+F 3 "" H 8300 3500 50 0001 C CNN
+ 1 8300 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X?
+U 1 1 684D0A9A
+P 3500 2300
+F 0 "X?" H 3500 2300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3600 2050 60 0000 C CNN
+F 2 "" H 3500 2300 60 0001 C CNN
+F 3 "" H 3500 2300 60 0001 C CNN
+ 1 3500 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X?
+U 1 1 684D0B05
+P 5200 2300
+F 0 "X?" H 5200 2300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5300 2050 60 0000 C CNN
+F 2 "" H 5200 2300 60 0001 C CNN
+F 3 "" H 5200 2300 60 0001 C CNN
+ 1 5200 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 1 1 684D0BAC
+P 2250 2150
+F 0 "U?" H 2300 2250 30 0000 C CNN
+F 1 "PORT" H 2250 2150 30 0000 C CNN
+F 2 "" H 2250 2150 60 0000 C CNN
+F 3 "" H 2250 2150 60 0000 C CNN
+ 1 2250 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 2 1 684D0C11
+P 2250 2300
+F 0 "U?" H 2300 2400 30 0000 C CNN
+F 1 "PORT" H 2250 2300 30 0000 C CNN
+F 2 "" H 2250 2300 60 0000 C CNN
+F 3 "" H 2250 2300 60 0000 C CNN
+ 2 2250 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 3 1 684D0D74
+P 2250 2450
+F 0 "U?" H 2300 2550 30 0000 C CNN
+F 1 "PORT" H 2250 2450 30 0000 C CNN
+F 2 "" H 2250 2450 60 0000 C CNN
+F 3 "" H 2250 2450 60 0000 C CNN
+ 3 2250 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 4 1 684D0DD9
+P 2250 2600
+F 0 "U?" H 2300 2700 30 0000 C CNN
+F 1 "PORT" H 2250 2600 30 0000 C CNN
+F 2 "" H 2250 2600 60 0000 C CNN
+F 3 "" H 2250 2600 60 0000 C CNN
+ 4 2250 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 5 1 684D0E42
+P 2250 2750
+F 0 "U?" H 2300 2850 30 0000 C CNN
+F 1 "PORT" H 2250 2750 30 0000 C CNN
+F 2 "" H 2250 2750 60 0000 C CNN
+F 3 "" H 2250 2750 60 0000 C CNN
+ 5 2250 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 6 1 684D0EC7
+P 8900 2950
+F 0 "U?" H 8950 3050 30 0000 C CNN
+F 1 "PORT" H 8900 2950 30 0000 C CNN
+F 2 "" H 8900 2950 60 0000 C CNN
+F 3 "" H 8900 2950 60 0000 C CNN
+ 6 8900 2950
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8500 2700 8500 3200
+Wire Wire Line
+ 8650 2950 8500 2950
+Connection ~ 8500 2950
+Wire Wire Line
+ 7650 2400 8000 2400
+Wire Wire Line
+ 7400 3500 8000 3500
+Wire Wire Line
+ 2500 2150 2850 2150
+Wire Wire Line
+ 2800 1900 2800 2150
+Wire Wire Line
+ 2800 1900 8500 1900
+Wire Wire Line
+ 8500 1900 8500 2100
+Wire Wire Line
+ 6700 1950 6700 1900
+Connection ~ 6700 1900
+Wire Wire Line
+ 4550 2150 4550 1900
+Connection ~ 4550 1900
+Connection ~ 2800 2150
+Wire Wire Line
+ 2500 2300 2850 2300
+Wire Wire Line
+ 2500 2450 2850 2450
+Wire Wire Line
+ 5500 2450 5500 1900
+Connection ~ 5500 1900
+Wire Wire Line
+ 6700 3950 6800 3950
+Wire Wire Line
+ 6800 3950 6800 1900
+Connection ~ 6800 1900
+Wire Wire Line
+ 6200 2500 6200 3350
+Wire Wire Line
+ 6200 3350 6250 3350
+Wire Wire Line
+ 6050 2850 6200 2850
+Connection ~ 6200 2850
+Wire Wire Line
+ 6700 2850 6700 3050
+Wire Wire Line
+ 5500 3250 5500 3300
+Wire Wire Line
+ 4550 3300 5900 3300
+Wire Wire Line
+ 5900 3300 5900 3000
+Wire Wire Line
+ 5900 3000 7700 3000
+Connection ~ 6700 3000
+Wire Wire Line
+ 7700 3000 7700 3900
+Wire Wire Line
+ 7700 3900 8600 3900
+Wire Wire Line
+ 8500 3900 8500 3800
+Wire Wire Line
+ 8400 3500 8600 3500
+Wire Wire Line
+ 8600 3500 8600 3900
+Connection ~ 8500 3900
+Wire Wire Line
+ 8400 2400 8550 2400
+Wire Wire Line
+ 8550 2400 8550 1950
+Wire Wire Line
+ 8550 1950 8500 1950
+Connection ~ 8500 1950
+Wire Wire Line
+ 6000 2300 6200 2300
+Wire Wire Line
+ 4300 2300 4550 2300
+Wire Wire Line
+ 4400 2300 4400 3650
+Wire Wire Line
+ 4400 3650 6250 3650
+Connection ~ 4400 2300
+Wire Wire Line
+ 2800 2450 2800 2550
+Wire Wire Line
+ 2800 2550 4550 2550
+Wire Wire Line
+ 4550 2450 4550 3300
+Connection ~ 2800 2450
+Connection ~ 5500 3300
+Connection ~ 4550 2550
+Wire Wire Line
+ 2500 2600 4900 2600
+Wire Wire Line
+ 4900 2600 4900 2750
+Wire Wire Line
+ 2500 2750 2500 2950
+Wire Wire Line
+ 2500 2950 4900 2950
+$Comp
+L SKY130mode scmode?
+U 1 1 684D1874
+P 9850 1750
+F 0 "scmode?" H 9850 1900 98 0000 C CNB
+F 1 "SKY130mode" H 9850 1650 118 0000 C CNB
+F 2 "" H 9850 1900 60 0001 C CNN
+F 3 "" H 9850 1900 60 0001 C CNN
+ 1 9850 1750
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.cir b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.cir
new file mode 100644
index 000000000..ec0fbff0b
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.cir
@@ -0,0 +1,19 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SR_Latch_with_Enable/SR_Latch_with_Enable.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 11:07:47 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_X3-Pad5_ NAND_Latch
+X5 Net-_X2-Pad4_ Net-_SC2-Pad3_ Net-_SC1-Pad3_ Net-_SC1-Pad2_ Net-_X3-Pad5_ NAND_2
+X4 Net-_X1-Pad4_ Net-_SC2-Pad3_ Net-_SC1-Pad3_ Net-_X3-Pad5_ Net-_SC2-Pad2_ NOR_2
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+X1 Net-_U1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_X1-Pad4_ CMOS_INVTR
+X2 Net-_X1-Pad4_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_X2-Pad4_ CMOS_INVTR
+U1 Net-_SC1-Pad3_ Net-_U1-Pad2_ Net-_SC2-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.cir.out b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.cir.out
new file mode 100644
index 000000000..c01a00a56
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.cir.out
@@ -0,0 +1,26 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/sr_latch_with_enable/sr_latch_with_enable.cir
+
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+.include NAND_2.sub
+.include NAND_Latch.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x3 net-_u1-pad4_ net-_u1-pad5_ net-_sc1-pad3_ net-_sc2-pad3_ net-_x3-pad5_ NAND_Latch
+x5 net-_x2-pad4_ net-_sc2-pad3_ net-_sc1-pad3_ net-_sc1-pad2_ net-_x3-pad5_ NAND_2
+x4 net-_x1-pad4_ net-_sc2-pad3_ net-_sc1-pad3_ net-_x3-pad5_ net-_sc2-pad2_ NOR_2
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+x1 net-_u1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_x1-pad4_ net-_sc1-pad3_ net-_sc2-pad3_ net-_x2-pad4_ CMOS_INVTR
+* u1 net-_sc1-pad3_ net-_u1-pad2_ net-_sc2-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.pro b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.sch b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.sch
new file mode 100644
index 000000000..15ee2aa73
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.sch
@@ -0,0 +1,308 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NAND_Latch X3
+U 1 1 684D0904
+P 5400 2850
+F 0 "X3" H 5400 2750 60 0000 C CNN
+F 1 "NAND_Latch" H 5400 2850 60 0000 C CNN
+F 2 "" H 5400 2850 60 0001 C CNN
+F 3 "" H 5400 2850 60 0001 C CNN
+ 1 5400 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X5
+U 1 1 684D097B
+P 6700 2400
+F 0 "X5" H 6800 2400 60 0000 C CNN
+F 1 "NAND_2" H 7100 2400 60 0000 C CNN
+F 2 "" H 6700 2400 60 0001 C CNN
+F 3 "" H 6700 2400 60 0001 C CNN
+ 1 6700 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_2 X4
+U 1 1 684D09D8
+P 6600 3500
+F 0 "X4" H 6600 3500 60 0000 C CNN
+F 1 "NOR_2" H 6850 3500 60 0000 C CNN
+F 2 "" H 6600 3500 60 0001 C CNN
+F 3 "" H 6600 3500 60 0001 C CNN
+ 1 6600 3500
+ 1 0 0 1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 684D0A0D
+P 8300 2400
+F 0 "SC1" H 8350 2700 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 8600 2487 50 0000 R CNN
+F 2 "" H 8300 900 50 0001 C CNN
+F 3 "" H 8300 2400 50 0001 C CNN
+ 1 8300 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684D0A4E
+P 8300 3500
+F 0 "SC2" H 8350 3800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 8600 3587 50 0000 R CNN
+F 2 "" H 8300 2000 50 0001 C CNN
+F 3 "" H 8300 3500 50 0001 C CNN
+ 1 8300 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 684D0A9A
+P 3500 2300
+F 0 "X1" H 3500 2300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3600 2050 60 0000 C CNN
+F 2 "" H 3500 2300 60 0001 C CNN
+F 3 "" H 3500 2300 60 0001 C CNN
+ 1 3500 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 684D0B05
+P 5200 2300
+F 0 "X2" H 5200 2300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5300 2050 60 0000 C CNN
+F 2 "" H 5200 2300 60 0001 C CNN
+F 3 "" H 5200 2300 60 0001 C CNN
+ 1 5200 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684D0BAC
+P 2250 2150
+F 0 "U1" H 2300 2250 30 0000 C CNN
+F 1 "PORT" H 2250 2150 30 0000 C CNN
+F 2 "" H 2250 2150 60 0000 C CNN
+F 3 "" H 2250 2150 60 0000 C CNN
+ 1 2250 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684D0C11
+P 2250 2300
+F 0 "U1" H 2300 2400 30 0000 C CNN
+F 1 "PORT" H 2250 2300 30 0000 C CNN
+F 2 "" H 2250 2300 60 0000 C CNN
+F 3 "" H 2250 2300 60 0000 C CNN
+ 2 2250 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684D0D74
+P 2250 2450
+F 0 "U1" H 2300 2550 30 0000 C CNN
+F 1 "PORT" H 2250 2450 30 0000 C CNN
+F 2 "" H 2250 2450 60 0000 C CNN
+F 3 "" H 2250 2450 60 0000 C CNN
+ 3 2250 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684D0DD9
+P 2250 2600
+F 0 "U1" H 2300 2700 30 0000 C CNN
+F 1 "PORT" H 2250 2600 30 0000 C CNN
+F 2 "" H 2250 2600 60 0000 C CNN
+F 3 "" H 2250 2600 60 0000 C CNN
+ 4 2250 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684D0E42
+P 2250 2750
+F 0 "U1" H 2300 2850 30 0000 C CNN
+F 1 "PORT" H 2250 2750 30 0000 C CNN
+F 2 "" H 2250 2750 60 0000 C CNN
+F 3 "" H 2250 2750 60 0000 C CNN
+ 5 2250 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684D0EC7
+P 8900 2950
+F 0 "U1" H 8950 3050 30 0000 C CNN
+F 1 "PORT" H 8900 2950 30 0000 C CNN
+F 2 "" H 8900 2950 60 0000 C CNN
+F 3 "" H 8900 2950 60 0000 C CNN
+ 6 8900 2950
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8500 2700 8500 3200
+Wire Wire Line
+ 8650 2950 8500 2950
+Connection ~ 8500 2950
+Wire Wire Line
+ 7650 2400 8000 2400
+Wire Wire Line
+ 7400 3500 8000 3500
+Wire Wire Line
+ 2500 2150 2850 2150
+Wire Wire Line
+ 2800 1900 2800 2150
+Wire Wire Line
+ 2800 1900 8500 1900
+Wire Wire Line
+ 8500 1900 8500 2100
+Wire Wire Line
+ 6700 1950 6700 1900
+Connection ~ 6700 1900
+Wire Wire Line
+ 4550 2150 4550 1900
+Connection ~ 4550 1900
+Connection ~ 2800 2150
+Wire Wire Line
+ 2500 2300 2850 2300
+Wire Wire Line
+ 2500 2450 2850 2450
+Wire Wire Line
+ 5500 2450 5500 1900
+Connection ~ 5500 1900
+Wire Wire Line
+ 6700 3950 6800 3950
+Wire Wire Line
+ 6800 3950 6800 1900
+Connection ~ 6800 1900
+Wire Wire Line
+ 6200 2500 6200 3350
+Wire Wire Line
+ 6200 3350 6250 3350
+Wire Wire Line
+ 6050 2850 6200 2850
+Connection ~ 6200 2850
+Wire Wire Line
+ 6700 2850 6700 3050
+Wire Wire Line
+ 5500 3250 5500 3300
+Wire Wire Line
+ 4550 3300 5900 3300
+Wire Wire Line
+ 5900 3300 5900 3000
+Wire Wire Line
+ 5900 3000 7700 3000
+Connection ~ 6700 3000
+Wire Wire Line
+ 7700 3000 7700 3900
+Wire Wire Line
+ 7700 3900 8600 3900
+Wire Wire Line
+ 8500 3900 8500 3800
+Wire Wire Line
+ 8400 3500 8600 3500
+Wire Wire Line
+ 8600 3500 8600 3900
+Connection ~ 8500 3900
+Wire Wire Line
+ 8400 2400 8550 2400
+Wire Wire Line
+ 8550 2400 8550 1950
+Wire Wire Line
+ 8550 1950 8500 1950
+Connection ~ 8500 1950
+Wire Wire Line
+ 6000 2300 6200 2300
+Wire Wire Line
+ 4300 2300 4550 2300
+Wire Wire Line
+ 4400 2300 4400 3650
+Wire Wire Line
+ 4400 3650 6250 3650
+Connection ~ 4400 2300
+Wire Wire Line
+ 2800 2450 2800 2550
+Wire Wire Line
+ 2800 2550 4550 2550
+Wire Wire Line
+ 4550 2450 4550 3300
+Connection ~ 2800 2450
+Connection ~ 5500 3300
+Connection ~ 4550 2550
+Wire Wire Line
+ 2500 2600 4900 2600
+Wire Wire Line
+ 4900 2600 4900 2750
+Wire Wire Line
+ 2500 2750 2500 2950
+Wire Wire Line
+ 2500 2950 4900 2950
+$Comp
+L SKY130mode scmode1
+U 1 1 684D1874
+P 9850 1750
+F 0 "scmode1" H 9850 1900 98 0000 C CNB
+F 1 "SKY130mode" H 9850 1650 118 0000 C CNB
+F 2 "" H 9850 1900 60 0001 C CNN
+F 3 "" H 9850 1900 60 0001 C CNN
+ 1 9850 1750
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.sub b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.sub
new file mode 100644
index 000000000..b67493832
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable.sub
@@ -0,0 +1,20 @@
+* Subcircuit SR_Latch_with_Enable
+.subckt SR_Latch_with_Enable net-_sc1-pad3_ net-_u1-pad2_ net-_sc2-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/sr_latch_with_enable/sr_latch_with_enable.cir
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+.include NAND_2.sub
+.include NAND_Latch.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x3 net-_u1-pad4_ net-_u1-pad5_ net-_sc1-pad3_ net-_sc2-pad3_ net-_x3-pad5_ NAND_Latch
+x5 net-_x2-pad4_ net-_sc2-pad3_ net-_sc1-pad3_ net-_sc1-pad2_ net-_x3-pad5_ NAND_2
+x4 net-_x1-pad4_ net-_sc2-pad3_ net-_sc1-pad3_ net-_x3-pad5_ net-_sc2-pad2_ NOR_2
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+x1 net-_u1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_x1-pad4_ net-_sc1-pad3_ net-_sc2-pad3_ net-_x2-pad4_ CMOS_INVTR
+* s c m o d e
+* Control Statements
+
+.ends SR_Latch_with_Enable
diff --git a/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable_Previous_Values.xml b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable_Previous_Values.xml
new file mode 100644
index 000000000..a06c31a8d
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/SR_Latch_with_Enable_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_Latch/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4044BMS/analysis b/library/SubcircuitLibrary/CD4044BMS/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4044BMS/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4068B/CD4068B-cache.lib b/library/SubcircuitLibrary/CD4068B/CD4068B-cache.lib
new file mode 100644
index 000000000..80dcddf3a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CD4068B-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 100 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -450 250 500 0 N
+P 3 0 1 0 -450 250 -450 -250 500 0 N
+X IN 1 -650 0 200 R 50 50 1 1 I
+X VDD 2 -650 150 200 R 50 50 1 1 I
+X GND 3 -650 -150 200 R 50 50 1 1 I
+X OUT 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4068B/CD4068B.bak b/library/SubcircuitLibrary/CD4068B/CD4068B.bak
new file mode 100644
index 000000000..4e5197823
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CD4068B.bak
@@ -0,0 +1,878 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC6
+U 1 1 685AD145
+P 4100 1000
+F 0 "SC6" H 4150 1300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4400 1087 50 0000 R CNN
+F 2 "" H 4100 -500 50 0001 C CNN
+F 3 "" H 4100 1000 50 0001 C CNN
+ 1 4100 1000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC7
+U 1 1 685AD255
+P 4100 1650
+F 0 "SC7" H 4150 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4400 1737 50 0000 R CNN
+F 2 "" H 4100 150 50 0001 C CNN
+F 3 "" H 4100 1650 50 0001 C CNN
+ 1 4100 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC8
+U 1 1 685AD36A
+P 4100 2300
+F 0 "SC8" H 4150 2600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4400 2387 50 0000 R CNN
+F 2 "" H 4100 800 50 0001 C CNN
+F 3 "" H 4100 2300 50 0001 C CNN
+ 1 4100 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC9
+U 1 1 685AD3B9
+P 4100 2950
+F 0 "SC9" H 4150 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4400 3037 50 0000 R CNN
+F 2 "" H 4100 1450 50 0001 C CNN
+F 3 "" H 4100 2950 50 0001 C CNN
+ 1 4100 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC10
+U 1 1 685AD444
+P 4100 3650
+F 0 "SC10" H 4150 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4400 3737 50 0000 R CNN
+F 2 "" H 4100 2150 50 0001 C CNN
+F 3 "" H 4100 3650 50 0001 C CNN
+ 1 4100 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 685AD467
+P 3400 3650
+F 0 "SC4" H 3450 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3700 3737 50 0000 R CNN
+F 2 "" H 3400 2150 50 0001 C CNN
+F 3 "" H 3400 3650 50 0001 C CNN
+ 1 3400 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 685AD4EE
+P 2700 3650
+F 0 "SC2" H 2750 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3000 3737 50 0000 R CNN
+F 2 "" H 2700 2150 50 0001 C CNN
+F 3 "" H 2700 3650 50 0001 C CNN
+ 1 2700 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 685AD585
+P 2000 3650
+F 0 "SC1" H 2050 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 2300 3737 50 0000 R CNN
+F 2 "" H 2000 2150 50 0001 C CNN
+F 3 "" H 2000 3650 50 0001 C CNN
+ 1 2000 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC12
+U 1 1 685AE290
+P 5100 4650
+F 0 "SC12" H 5150 4950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5400 4737 50 0000 R CNN
+F 2 "" H 5100 3150 50 0001 C CNN
+F 3 "" H 5100 4650 50 0001 C CNN
+ 1 5100 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC13
+U 1 1 685AE297
+P 5100 5300
+F 0 "SC13" H 5150 5600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5400 5387 50 0000 R CNN
+F 2 "" H 5100 3800 50 0001 C CNN
+F 3 "" H 5100 5300 50 0001 C CNN
+ 1 5100 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC14
+U 1 1 685AE29E
+P 5100 5950
+F 0 "SC14" H 5150 6250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5400 6037 50 0000 R CNN
+F 2 "" H 5100 4450 50 0001 C CNN
+F 3 "" H 5100 5950 50 0001 C CNN
+ 1 5100 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC15
+U 1 1 685AE2A5
+P 5100 6600
+F 0 "SC15" H 5150 6900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5400 6687 50 0000 R CNN
+F 2 "" H 5100 5100 50 0001 C CNN
+F 3 "" H 5100 6600 50 0001 C CNN
+ 1 5100 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC16
+U 1 1 685AE2AC
+P 5100 7300
+F 0 "SC16" H 5150 7600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5400 7387 50 0000 R CNN
+F 2 "" H 5100 5800 50 0001 C CNN
+F 3 "" H 5100 7300 50 0001 C CNN
+ 1 5100 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC11
+U 1 1 685AE2B3
+P 4400 7300
+F 0 "SC11" H 4450 7600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4700 7387 50 0000 R CNN
+F 2 "" H 4400 5800 50 0001 C CNN
+F 3 "" H 4400 7300 50 0001 C CNN
+ 1 4400 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 685AE2BA
+P 3700 7300
+F 0 "SC5" H 3750 7600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4000 7387 50 0000 R CNN
+F 2 "" H 3700 5800 50 0001 C CNN
+F 3 "" H 3700 7300 50 0001 C CNN
+ 1 3700 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 685AE2C1
+P 3000 7300
+F 0 "SC3" H 3050 7600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3300 7387 50 0000 R CNN
+F 2 "" H 3000 5800 50 0001 C CNN
+F 3 "" H 3000 7300 50 0001 C CNN
+ 1 3000 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X9
+U 1 1 685AE361
+P 7850 3500
+F 0 "X9" H 7850 3500 60 0000 C CNN
+F 1 "CMOS_INVTR" H 7950 3250 60 0000 C CNN
+F 2 "" H 7850 3500 60 0001 C CNN
+F 3 "" H 7850 3500 60 0001 C CNN
+ 1 7850 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X10
+U 1 1 685AE3CE
+P 9400 3500
+F 0 "X10" H 9400 3500 60 0000 C CNN
+F 1 "CMOS_INVTR" H 9500 3250 60 0000 C CNN
+F 2 "" H 9400 3500 60 0001 C CNN
+F 3 "" H 9400 3500 60 0001 C CNN
+ 1 9400 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 685AE85A
+P 2000 850
+F 0 "X1" H 2000 850 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2100 600 60 0000 C CNN
+F 2 "" H 2000 850 60 0001 C CNN
+F 3 "" H 2000 850 60 0001 C CNN
+ 1 2000 850
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 685AE943
+P 2000 1350
+F 0 "X2" H 2000 1350 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2100 1100 60 0000 C CNN
+F 2 "" H 2000 1350 60 0001 C CNN
+F 3 "" H 2000 1350 60 0001 C CNN
+ 1 2000 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X3
+U 1 1 685AEBEB
+P 2000 1850
+F 0 "X3" H 2000 1850 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2100 1600 60 0000 C CNN
+F 2 "" H 2000 1850 60 0001 C CNN
+F 3 "" H 2000 1850 60 0001 C CNN
+ 1 2000 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X4
+U 1 1 685AED4C
+P 2000 2350
+F 0 "X4" H 2000 2350 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2100 2100 60 0000 C CNN
+F 2 "" H 2000 2350 60 0001 C CNN
+F 3 "" H 2000 2350 60 0001 C CNN
+ 1 2000 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X5
+U 1 1 685AF209
+P 3450 4600
+F 0 "X5" H 3450 4600 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3550 4350 60 0000 C CNN
+F 2 "" H 3450 4600 60 0001 C CNN
+F 3 "" H 3450 4600 60 0001 C CNN
+ 1 3450 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X6
+U 1 1 685AF210
+P 3450 5100
+F 0 "X6" H 3450 5100 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3550 4850 60 0000 C CNN
+F 2 "" H 3450 5100 60 0001 C CNN
+F 3 "" H 3450 5100 60 0001 C CNN
+ 1 3450 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X7
+U 1 1 685AF217
+P 3450 5600
+F 0 "X7" H 3450 5600 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3550 5350 60 0000 C CNN
+F 2 "" H 3450 5600 60 0001 C CNN
+F 3 "" H 3450 5600 60 0001 C CNN
+ 1 3450 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X8
+U 1 1 685AF21E
+P 3450 6100
+F 0 "X8" H 3450 6100 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3550 5850 60 0000 C CNN
+F 2 "" H 3450 6100 60 0001 C CNN
+F 3 "" H 3450 6100 60 0001 C CNN
+ 1 3450 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685AF2E4
+P 850 850
+F 0 "U1" H 900 950 30 0000 C CNN
+F 1 "PORT" H 850 850 30 0000 C CNN
+F 2 "" H 850 850 60 0000 C CNN
+F 3 "" H 850 850 60 0000 C CNN
+ 1 850 850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685AF341
+P 850 1350
+F 0 "U1" H 900 1450 30 0000 C CNN
+F 1 "PORT" H 850 1350 30 0000 C CNN
+F 2 "" H 850 1350 60 0000 C CNN
+F 3 "" H 850 1350 60 0000 C CNN
+ 2 850 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685AF3A8
+P 850 1850
+F 0 "U1" H 900 1950 30 0000 C CNN
+F 1 "PORT" H 850 1850 30 0000 C CNN
+F 2 "" H 850 1850 60 0000 C CNN
+F 3 "" H 850 1850 60 0000 C CNN
+ 3 850 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685AF403
+P 850 2350
+F 0 "U1" H 900 2450 30 0000 C CNN
+F 1 "PORT" H 850 2350 30 0000 C CNN
+F 2 "" H 850 2350 60 0000 C CNN
+F 3 "" H 850 2350 60 0000 C CNN
+ 4 850 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685AF4EA
+P 2300 4600
+F 0 "U1" H 2350 4700 30 0000 C CNN
+F 1 "PORT" H 2300 4600 30 0000 C CNN
+F 2 "" H 2300 4600 60 0000 C CNN
+F 3 "" H 2300 4600 60 0000 C CNN
+ 5 2300 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685AF571
+P 2300 5100
+F 0 "U1" H 2350 5200 30 0000 C CNN
+F 1 "PORT" H 2300 5100 30 0000 C CNN
+F 2 "" H 2300 5100 60 0000 C CNN
+F 3 "" H 2300 5100 60 0000 C CNN
+ 6 2300 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685AF624
+P 2300 5600
+F 0 "U1" H 2350 5700 30 0000 C CNN
+F 1 "PORT" H 2300 5600 30 0000 C CNN
+F 2 "" H 2300 5600 60 0000 C CNN
+F 3 "" H 2300 5600 60 0000 C CNN
+ 7 2300 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685AF6CD
+P 2300 6100
+F 0 "U1" H 2350 6200 30 0000 C CNN
+F 1 "PORT" H 2300 6100 30 0000 C CNN
+F 2 "" H 2300 6100 60 0000 C CNN
+F 3 "" H 2300 6100 60 0000 C CNN
+ 8 2300 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685AF8FA
+P 10650 3500
+F 0 "U1" H 10700 3600 30 0000 C CNN
+F 1 "PORT" H 10650 3500 30 0000 C CNN
+F 2 "" H 10650 3500 60 0000 C CNN
+F 3 "" H 10650 3500 60 0000 C CNN
+ 11 10650 3500
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685AF9B9
+P 10650 3850
+F 0 "U1" H 10700 3950 30 0000 C CNN
+F 1 "PORT" H 10650 3850 30 0000 C CNN
+F 2 "" H 10650 3850 60 0000 C CNN
+F 3 "" H 10650 3850 60 0000 C CNN
+ 12 10650 3850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685AFD96
+P 4900 600
+F 0 "U1" H 4950 700 30 0000 C CNN
+F 1 "PORT" H 4900 600 30 0000 C CNN
+F 2 "" H 4900 600 60 0000 C CNN
+F 3 "" H 4900 600 60 0000 C CNN
+ 9 4900 600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685B0001
+P 5700 7700
+F 0 "U1" H 5750 7800 30 0000 C CNN
+F 1 "PORT" H 5700 7700 30 0000 C CNN
+F 2 "" H 5700 7700 60 0000 C CNN
+F 3 "" H 5700 7700 60 0000 C CNN
+ 10 5700 7700
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC17
+U 1 1 685B0511
+P 5350 2600
+F 0 "SC17" H 5400 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 2687 50 0000 R CNN
+F 2 "" H 5350 1100 50 0001 C CNN
+F 3 "" H 5350 2600 50 0001 C CNN
+ 1 5350 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC20
+U 1 1 685B05AA
+P 6000 2600
+F 0 "SC20" H 6050 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6300 2687 50 0000 R CNN
+F 2 "" H 6000 1100 50 0001 C CNN
+F 3 "" H 6000 2600 50 0001 C CNN
+ 1 6000 2600
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC18
+U 1 1 685B066D
+P 5500 3400
+F 0 "SC18" H 5550 3700 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5800 3487 50 0000 R CNN
+F 2 "" H 5500 1900 50 0001 C CNN
+F 3 "" H 5500 3400 50 0001 C CNN
+ 1 5500 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC19
+U 1 1 685B071E
+P 5900 4050
+F 0 "SC19" H 5950 4350 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6200 4137 50 0000 R CNN
+F 2 "" H 5900 2550 50 0001 C CNN
+F 3 "" H 5900 4050 50 0001 C CNN
+ 1 5900 4050
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1100 850 1350 850
+Wire Wire Line
+ 1100 1350 1350 1350
+Wire Wire Line
+ 1100 1850 1350 1850
+Wire Wire Line
+ 1100 2350 1350 2350
+Wire Wire Line
+ 2550 4600 2800 4600
+Wire Wire Line
+ 2550 5100 2800 5100
+Wire Wire Line
+ 2550 5600 2800 5600
+Wire Wire Line
+ 2550 6100 2800 6100
+Wire Wire Line
+ 4300 1300 4300 1350
+Wire Wire Line
+ 4300 1950 4300 2000
+Wire Wire Line
+ 4300 2600 4300 2650
+Wire Wire Line
+ 4300 3350 4300 3250
+Wire Wire Line
+ 3800 2950 3800 3650
+Wire Wire Line
+ 3800 2300 3100 2300
+Wire Wire Line
+ 3100 1850 3100 3650
+Wire Wire Line
+ 3800 1650 2400 1650
+Wire Wire Line
+ 2400 1650 2400 3650
+Wire Wire Line
+ 3800 1000 1700 1000
+Wire Wire Line
+ 1700 1000 1700 3650
+Wire Wire Line
+ 2800 850 2800 1000
+Connection ~ 2800 1000
+Wire Wire Line
+ 2800 1350 2800 1650
+Connection ~ 2800 1650
+Wire Wire Line
+ 2800 1850 3100 1850
+Connection ~ 3100 2300
+Wire Wire Line
+ 2800 2350 3650 2350
+Wire Wire Line
+ 3650 2350 3650 3000
+Wire Wire Line
+ 3650 3000 3800 3000
+Connection ~ 3800 3000
+Wire Wire Line
+ 5300 4950 5300 5000
+Wire Wire Line
+ 5300 5600 5300 5650
+Wire Wire Line
+ 5300 6250 5300 6300
+Wire Wire Line
+ 5300 6900 5300 7000
+Wire Wire Line
+ 4800 6600 4800 7300
+Wire Wire Line
+ 4800 5950 4100 5950
+Wire Wire Line
+ 4100 5950 4100 7300
+Wire Wire Line
+ 4800 5300 3400 5300
+Wire Wire Line
+ 3400 5300 3400 7300
+Wire Wire Line
+ 4800 4650 2700 4650
+Wire Wire Line
+ 2700 4650 2700 7300
+Wire Wire Line
+ 4250 6100 4250 6650
+Wire Wire Line
+ 4250 6650 4800 6650
+Connection ~ 4800 6650
+Wire Wire Line
+ 4250 5600 4250 5950
+Connection ~ 4250 5950
+Wire Wire Line
+ 4250 5100 4250 5300
+Connection ~ 4250 5300
+Wire Wire Line
+ 4300 4600 4250 4600
+Wire Wire Line
+ 4300 4600 4300 4650
+Connection ~ 4300 4650
+Wire Wire Line
+ 10200 3500 10400 3500
+Wire Wire Line
+ 7050 3850 10400 3850
+Wire Wire Line
+ 7050 3000 7050 3850
+Wire Wire Line
+ 7050 3500 7200 3500
+Wire Wire Line
+ 8650 3500 8750 3500
+Wire Wire Line
+ 5550 2900 5800 2900
+Wire Wire Line
+ 5700 3100 5700 2900
+Connection ~ 5700 2900
+Wire Wire Line
+ 5700 3000 7050 3000
+Connection ~ 7050 3500
+Connection ~ 5700 3000
+Wire Wire Line
+ 5700 3750 5700 3700
+Wire Wire Line
+ 5550 2300 5800 2300
+Wire Wire Line
+ 5050 2600 5050 3400
+Wire Wire Line
+ 5050 3400 5200 3400
+Wire Wire Line
+ 2200 3300 5050 3300
+Connection ~ 5050 3300
+Connection ~ 4300 3300
+Wire Wire Line
+ 6300 2600 6300 4050
+Wire Wire Line
+ 6300 4050 6200 4050
+Wire Wire Line
+ 3200 6950 6400 6950
+Wire Wire Line
+ 6400 6950 6400 3800
+Wire Wire Line
+ 6400 3800 6300 3800
+Connection ~ 6300 3800
+Connection ~ 5300 6950
+Wire Wire Line
+ 4300 700 4450 700
+Wire Wire Line
+ 4450 550 4450 4250
+Wire Wire Line
+ 4450 4250 5450 4250
+Wire Wire Line
+ 5300 4250 5300 4350
+Wire Wire Line
+ 5450 4250 5450 6600
+Wire Wire Line
+ 5450 6600 5200 6600
+Connection ~ 5300 4250
+Wire Wire Line
+ 5200 5950 5450 5950
+Connection ~ 5450 5950
+Wire Wire Line
+ 5200 5300 5450 5300
+Connection ~ 5450 5300
+Wire Wire Line
+ 5200 4650 5450 4650
+Connection ~ 5450 4650
+Wire Wire Line
+ 4200 2950 4450 2950
+Connection ~ 4450 2950
+Wire Wire Line
+ 4200 2300 4450 2300
+Connection ~ 4450 2300
+Wire Wire Line
+ 4200 1650 8750 1650
+Connection ~ 4450 1650
+Wire Wire Line
+ 4200 1000 4450 1000
+Connection ~ 4450 1000
+Wire Wire Line
+ 2200 3300 2200 3350
+Wire Wire Line
+ 2900 3350 2900 3300
+Connection ~ 2900 3300
+Wire Wire Line
+ 3600 3350 3600 3300
+Connection ~ 3600 3300
+Wire Wire Line
+ 3200 6950 3200 7000
+Wire Wire Line
+ 3900 7000 3900 6950
+Connection ~ 3900 6950
+Wire Wire Line
+ 4600 7000 4600 6950
+Connection ~ 4600 6950
+Wire Wire Line
+ 1350 2200 1100 2200
+Wire Wire Line
+ 1100 550 1100 4450
+Wire Wire Line
+ 1100 550 4450 550
+Connection ~ 4450 700
+Wire Wire Line
+ 1350 1700 1100 1700
+Connection ~ 1100 1700
+Wire Wire Line
+ 1350 1200 1100 1200
+Connection ~ 1100 1200
+Wire Wire Line
+ 1350 700 1100 700
+Connection ~ 1100 700
+Wire Wire Line
+ 1100 4450 2800 4450
+Connection ~ 1100 2200
+Wire Wire Line
+ 2800 5950 2600 5950
+Wire Wire Line
+ 2600 5950 2600 4450
+Connection ~ 2600 4450
+Wire Wire Line
+ 2800 4950 2600 4950
+Connection ~ 2600 4950
+Wire Wire Line
+ 2800 5450 2600 5450
+Connection ~ 2600 5450
+Wire Wire Line
+ 5450 2600 5600 2600
+Wire Wire Line
+ 5600 2600 5600 2300
+Connection ~ 5600 2300
+Wire Wire Line
+ 5900 2600 5750 2600
+Wire Wire Line
+ 5750 2600 5750 2300
+Connection ~ 5750 2300
+Wire Wire Line
+ 5700 1650 5700 2300
+Connection ~ 5700 2300
+Wire Wire Line
+ 8750 1650 8750 3350
+Connection ~ 5700 1650
+Wire Wire Line
+ 7200 3350 7200 1650
+Connection ~ 7200 1650
+Wire Wire Line
+ 4650 600 4450 600
+Connection ~ 4450 600
+Wire Wire Line
+ 1350 1000 1200 1000
+Wire Wire Line
+ 1200 1000 1200 7700
+Wire Wire Line
+ 1350 1500 1200 1500
+Connection ~ 1200 1500
+Wire Wire Line
+ 1350 2000 1200 2000
+Connection ~ 1200 2000
+Wire Wire Line
+ 1350 2500 1200 2500
+Connection ~ 1200 2500
+Wire Wire Line
+ 1200 4050 5800 4050
+Wire Wire Line
+ 4300 4050 4300 3950
+Wire Wire Line
+ 4200 3650 4350 3650
+Wire Wire Line
+ 4350 3650 4350 4050
+Connection ~ 4300 4050
+Wire Wire Line
+ 3600 3950 3600 4050
+Connection ~ 3600 4050
+Wire Wire Line
+ 3500 3650 3650 3650
+Wire Wire Line
+ 3650 3650 3650 4050
+Connection ~ 3650 4050
+Wire Wire Line
+ 2900 3950 2900 4050
+Connection ~ 2900 4050
+Wire Wire Line
+ 2800 3650 2950 3650
+Wire Wire Line
+ 2950 3650 2950 4050
+Connection ~ 2950 4050
+Wire Wire Line
+ 2200 3950 2200 4050
+Connection ~ 2200 4050
+Wire Wire Line
+ 2100 3650 2250 3650
+Wire Wire Line
+ 2250 3650 2250 4050
+Connection ~ 2250 4050
+Wire Wire Line
+ 1200 7700 5450 7700
+Wire Wire Line
+ 5300 7700 5300 7600
+Connection ~ 1200 4050
+Wire Wire Line
+ 5200 7300 5350 7300
+Wire Wire Line
+ 5350 7300 5350 7700
+Connection ~ 5300 7700
+Wire Wire Line
+ 4600 7600 4600 7700
+Connection ~ 4600 7700
+Wire Wire Line
+ 4500 7300 4650 7300
+Wire Wire Line
+ 4650 7300 4650 7700
+Connection ~ 4650 7700
+Wire Wire Line
+ 3900 7600 3900 7700
+Connection ~ 3900 7700
+Wire Wire Line
+ 3800 7300 3950 7300
+Wire Wire Line
+ 3950 7300 3950 7700
+Connection ~ 3950 7700
+Wire Wire Line
+ 3200 7600 3200 7700
+Connection ~ 3200 7700
+Wire Wire Line
+ 3100 7300 3250 7300
+Wire Wire Line
+ 3250 7300 3250 7700
+Connection ~ 3250 7700
+Connection ~ 5350 7700
+Wire Wire Line
+ 2800 4750 1200 4750
+Connection ~ 1200 4750
+Wire Wire Line
+ 2800 5250 1200 5250
+Connection ~ 1200 5250
+Wire Wire Line
+ 2800 5750 1200 5750
+Connection ~ 1200 5750
+Wire Wire Line
+ 2800 6250 1200 6250
+Connection ~ 1200 6250
+Wire Wire Line
+ 5550 4050 5550 4400
+Wire Wire Line
+ 5550 4400 8750 4400
+Wire Wire Line
+ 8750 4400 8750 3650
+Connection ~ 4350 4050
+Wire Wire Line
+ 7200 3650 7200 4400
+Connection ~ 7200 4400
+Wire Wire Line
+ 5700 4350 5700 4400
+Connection ~ 5700 4400
+Connection ~ 5550 4050
+Wire Wire Line
+ 5600 3400 6000 3400
+Wire Wire Line
+ 6000 3400 6000 4400
+Connection ~ 6000 4400
+$Comp
+L SKY130mode scmode1
+U 1 1 685BA6E8
+P 8750 5150
+F 0 "scmode1" H 8750 5300 98 0000 C CNB
+F 1 "SKY130mode" H 8750 5050 118 0000 C CNB
+F 2 "" H 8750 5300 60 0001 C CNN
+F 3 "" H 8750 5300 60 0001 C CNN
+ 1 8750 5150
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4068B/CD4068B.cir b/library/SubcircuitLibrary/CD4068B/CD4068B.cir
new file mode 100644
index 000000000..8e615d3e1
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CD4068B.cir
@@ -0,0 +1,43 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CD4068B/CD4068B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 25 11:08:04 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC6 Net-_SC6-Pad1_ Net-_SC1-Pad2_ Net-_SC12-Pad3_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC7 Net-_SC7-Pad1_ Net-_SC2-Pad2_ Net-_SC6-Pad1_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC8 Net-_SC8-Pad1_ Net-_SC4-Pad2_ Net-_SC7-Pad1_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC9 Net-_SC1-Pad1_ Net-_SC10-Pad2_ Net-_SC8-Pad1_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC10 Net-_SC1-Pad1_ Net-_SC10-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC1-Pad1_ Net-_SC4-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC12 Net-_SC12-Pad1_ Net-_SC12-Pad2_ Net-_SC12-Pad3_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC13 Net-_SC13-Pad1_ Net-_SC13-Pad2_ Net-_SC12-Pad1_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC14 Net-_SC14-Pad1_ Net-_SC11-Pad2_ Net-_SC13-Pad1_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC15 Net-_SC11-Pad1_ Net-_SC15-Pad2_ Net-_SC14-Pad1_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC16 Net-_SC11-Pad1_ Net-_SC15-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC11 Net-_SC11-Pad1_ Net-_SC11-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC5 Net-_SC11-Pad1_ Net-_SC13-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC3 Net-_SC11-Pad1_ Net-_SC12-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+X9 Net-_SC17-Pad1_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_X10-Pad1_ CMOS_INVTR
+X10 Net-_X10-Pad1_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_U1-Pad11_ CMOS_INVTR
+X1 Net-_U1-Pad1_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_SC1-Pad2_ CMOS_INVTR
+X2 Net-_U1-Pad2_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_SC2-Pad2_ CMOS_INVTR
+X3 Net-_U1-Pad3_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_SC4-Pad2_ CMOS_INVTR
+X4 Net-_U1-Pad4_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_SC10-Pad2_ CMOS_INVTR
+X5 Net-_U1-Pad5_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_SC12-Pad2_ CMOS_INVTR
+X6 Net-_U1-Pad6_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_SC13-Pad2_ CMOS_INVTR
+X7 Net-_U1-Pad7_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_SC11-Pad2_ CMOS_INVTR
+X8 Net-_U1-Pad8_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_SC15-Pad2_ CMOS_INVTR
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_U1-Pad11_ Net-_U1-Pad12_ PORT
+SC17 Net-_SC17-Pad1_ Net-_SC1-Pad1_ Net-_SC12-Pad3_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC20 Net-_SC17-Pad1_ Net-_SC11-Pad1_ Net-_SC12-Pad3_ Net-_SC12-Pad3_ sky130_fd_pr__pfet_01v8
+SC18 Net-_SC17-Pad1_ Net-_SC1-Pad1_ Net-_SC18-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC19 Net-_SC18-Pad3_ Net-_SC11-Pad1_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+scmode1 SKY130mode
+X11 Net-_SC17-Pad1_ Net-_SC12-Pad3_ Net-_SC1-Pad3_ Net-_U1-Pad12_ CMOS_INVTR
+
+.end
diff --git a/library/SubcircuitLibrary/CD4068B/CD4068B.cir.out b/library/SubcircuitLibrary/CD4068B/CD4068B.cir.out
new file mode 100644
index 000000000..d515e7f4a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CD4068B.cir.out
@@ -0,0 +1,47 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cd4068b/cd4068b.cir
+
+.include CMOS_INVTR.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc6 net-_sc6-pad1_ net-_sc1-pad2_ net-_sc12-pad3_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc7 net-_sc7-pad1_ net-_sc2-pad2_ net-_sc6-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc8-pad1_ net-_sc4-pad2_ net-_sc7-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc9 net-_sc1-pad1_ net-_sc10-pad2_ net-_sc8-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc10 net-_sc1-pad1_ net-_sc10-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad1_ net-_sc4-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc12 net-_sc12-pad1_ net-_sc12-pad2_ net-_sc12-pad3_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc13 net-_sc13-pad1_ net-_sc13-pad2_ net-_sc12-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc14 net-_sc14-pad1_ net-_sc11-pad2_ net-_sc13-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc15 net-_sc11-pad1_ net-_sc15-pad2_ net-_sc14-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc16 net-_sc11-pad1_ net-_sc15-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc11 net-_sc11-pad1_ net-_sc11-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc11-pad1_ net-_sc13-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc11-pad1_ net-_sc12-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+x9 net-_sc17-pad1_ net-_sc12-pad3_ net-_sc1-pad3_ net-_x10-pad1_ CMOS_INVTR
+x10 net-_x10-pad1_ net-_sc12-pad3_ net-_sc1-pad3_ net-_u1-pad11_ CMOS_INVTR
+x1 net-_u1-pad1_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc1-pad2_ CMOS_INVTR
+x2 net-_u1-pad2_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc2-pad2_ CMOS_INVTR
+x3 net-_u1-pad3_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc4-pad2_ CMOS_INVTR
+x4 net-_u1-pad4_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc10-pad2_ CMOS_INVTR
+x5 net-_u1-pad5_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc12-pad2_ CMOS_INVTR
+x6 net-_u1-pad6_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc13-pad2_ CMOS_INVTR
+x7 net-_u1-pad7_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc11-pad2_ CMOS_INVTR
+x8 net-_u1-pad8_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc15-pad2_ CMOS_INVTR
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_sc12-pad3_ net-_sc1-pad3_ net-_u1-pad11_ net-_u1-pad12_ port
+xsc17 net-_sc17-pad1_ net-_sc1-pad1_ net-_sc12-pad3_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc20 net-_sc17-pad1_ net-_sc11-pad1_ net-_sc12-pad3_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc18 net-_sc17-pad1_ net-_sc1-pad1_ net-_sc18-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc19 net-_sc18-pad3_ net-_sc11-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+x11 net-_sc17-pad1_ net-_sc12-pad3_ net-_sc1-pad3_ net-_u1-pad12_ CMOS_INVTR
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4068B/CD4068B.pro b/library/SubcircuitLibrary/CD4068B/CD4068B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CD4068B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4068B/CD4068B.sch b/library/SubcircuitLibrary/CD4068B/CD4068B.sch
new file mode 100644
index 000000000..686cc9b6c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CD4068B.sch
@@ -0,0 +1,900 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4068B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC6
+U 1 1 685AD145
+P 4100 1000
+F 0 "SC6" H 4150 1300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4400 1087 50 0000 R CNN
+F 2 "" H 4100 -500 50 0001 C CNN
+F 3 "" H 4100 1000 50 0001 C CNN
+ 1 4100 1000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC7
+U 1 1 685AD255
+P 4100 1650
+F 0 "SC7" H 4150 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4400 1737 50 0000 R CNN
+F 2 "" H 4100 150 50 0001 C CNN
+F 3 "" H 4100 1650 50 0001 C CNN
+ 1 4100 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC8
+U 1 1 685AD36A
+P 4100 2300
+F 0 "SC8" H 4150 2600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4400 2387 50 0000 R CNN
+F 2 "" H 4100 800 50 0001 C CNN
+F 3 "" H 4100 2300 50 0001 C CNN
+ 1 4100 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC9
+U 1 1 685AD3B9
+P 4100 2950
+F 0 "SC9" H 4150 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4400 3037 50 0000 R CNN
+F 2 "" H 4100 1450 50 0001 C CNN
+F 3 "" H 4100 2950 50 0001 C CNN
+ 1 4100 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC10
+U 1 1 685AD444
+P 4100 3650
+F 0 "SC10" H 4150 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4400 3737 50 0000 R CNN
+F 2 "" H 4100 2150 50 0001 C CNN
+F 3 "" H 4100 3650 50 0001 C CNN
+ 1 4100 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 685AD467
+P 3400 3650
+F 0 "SC4" H 3450 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3700 3737 50 0000 R CNN
+F 2 "" H 3400 2150 50 0001 C CNN
+F 3 "" H 3400 3650 50 0001 C CNN
+ 1 3400 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 685AD4EE
+P 2700 3650
+F 0 "SC2" H 2750 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3000 3737 50 0000 R CNN
+F 2 "" H 2700 2150 50 0001 C CNN
+F 3 "" H 2700 3650 50 0001 C CNN
+ 1 2700 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 685AD585
+P 2000 3650
+F 0 "SC1" H 2050 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 2300 3737 50 0000 R CNN
+F 2 "" H 2000 2150 50 0001 C CNN
+F 3 "" H 2000 3650 50 0001 C CNN
+ 1 2000 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC12
+U 1 1 685AE290
+P 5100 4650
+F 0 "SC12" H 5150 4950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5400 4737 50 0000 R CNN
+F 2 "" H 5100 3150 50 0001 C CNN
+F 3 "" H 5100 4650 50 0001 C CNN
+ 1 5100 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC13
+U 1 1 685AE297
+P 5100 5300
+F 0 "SC13" H 5150 5600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5400 5387 50 0000 R CNN
+F 2 "" H 5100 3800 50 0001 C CNN
+F 3 "" H 5100 5300 50 0001 C CNN
+ 1 5100 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC14
+U 1 1 685AE29E
+P 5100 5950
+F 0 "SC14" H 5150 6250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5400 6037 50 0000 R CNN
+F 2 "" H 5100 4450 50 0001 C CNN
+F 3 "" H 5100 5950 50 0001 C CNN
+ 1 5100 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC15
+U 1 1 685AE2A5
+P 5100 6600
+F 0 "SC15" H 5150 6900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5400 6687 50 0000 R CNN
+F 2 "" H 5100 5100 50 0001 C CNN
+F 3 "" H 5100 6600 50 0001 C CNN
+ 1 5100 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC16
+U 1 1 685AE2AC
+P 5100 7300
+F 0 "SC16" H 5150 7600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5400 7387 50 0000 R CNN
+F 2 "" H 5100 5800 50 0001 C CNN
+F 3 "" H 5100 7300 50 0001 C CNN
+ 1 5100 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC11
+U 1 1 685AE2B3
+P 4400 7300
+F 0 "SC11" H 4450 7600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4700 7387 50 0000 R CNN
+F 2 "" H 4400 5800 50 0001 C CNN
+F 3 "" H 4400 7300 50 0001 C CNN
+ 1 4400 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 685AE2BA
+P 3700 7300
+F 0 "SC5" H 3750 7600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4000 7387 50 0000 R CNN
+F 2 "" H 3700 5800 50 0001 C CNN
+F 3 "" H 3700 7300 50 0001 C CNN
+ 1 3700 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 685AE2C1
+P 3000 7300
+F 0 "SC3" H 3050 7600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3300 7387 50 0000 R CNN
+F 2 "" H 3000 5800 50 0001 C CNN
+F 3 "" H 3000 7300 50 0001 C CNN
+ 1 3000 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X9
+U 1 1 685AE361
+P 7850 3500
+F 0 "X9" H 7850 3500 60 0000 C CNN
+F 1 "CMOS_INVTR" H 7950 3250 60 0000 C CNN
+F 2 "" H 7850 3500 60 0001 C CNN
+F 3 "" H 7850 3500 60 0001 C CNN
+ 1 7850 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X10
+U 1 1 685AE3CE
+P 9400 3500
+F 0 "X10" H 9400 3500 60 0000 C CNN
+F 1 "CMOS_INVTR" H 9500 3250 60 0000 C CNN
+F 2 "" H 9400 3500 60 0001 C CNN
+F 3 "" H 9400 3500 60 0001 C CNN
+ 1 9400 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 685AE85A
+P 2000 850
+F 0 "X1" H 2000 850 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2100 600 60 0000 C CNN
+F 2 "" H 2000 850 60 0001 C CNN
+F 3 "" H 2000 850 60 0001 C CNN
+ 1 2000 850
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 685AE943
+P 2000 1350
+F 0 "X2" H 2000 1350 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2100 1100 60 0000 C CNN
+F 2 "" H 2000 1350 60 0001 C CNN
+F 3 "" H 2000 1350 60 0001 C CNN
+ 1 2000 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X3
+U 1 1 685AEBEB
+P 2000 1850
+F 0 "X3" H 2000 1850 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2100 1600 60 0000 C CNN
+F 2 "" H 2000 1850 60 0001 C CNN
+F 3 "" H 2000 1850 60 0001 C CNN
+ 1 2000 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X4
+U 1 1 685AED4C
+P 2000 2350
+F 0 "X4" H 2000 2350 60 0000 C CNN
+F 1 "CMOS_INVTR" H 2100 2100 60 0000 C CNN
+F 2 "" H 2000 2350 60 0001 C CNN
+F 3 "" H 2000 2350 60 0001 C CNN
+ 1 2000 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X5
+U 1 1 685AF209
+P 3450 4600
+F 0 "X5" H 3450 4600 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3550 4350 60 0000 C CNN
+F 2 "" H 3450 4600 60 0001 C CNN
+F 3 "" H 3450 4600 60 0001 C CNN
+ 1 3450 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X6
+U 1 1 685AF210
+P 3450 5100
+F 0 "X6" H 3450 5100 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3550 4850 60 0000 C CNN
+F 2 "" H 3450 5100 60 0001 C CNN
+F 3 "" H 3450 5100 60 0001 C CNN
+ 1 3450 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X7
+U 1 1 685AF217
+P 3450 5600
+F 0 "X7" H 3450 5600 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3550 5350 60 0000 C CNN
+F 2 "" H 3450 5600 60 0001 C CNN
+F 3 "" H 3450 5600 60 0001 C CNN
+ 1 3450 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X8
+U 1 1 685AF21E
+P 3450 6100
+F 0 "X8" H 3450 6100 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3550 5850 60 0000 C CNN
+F 2 "" H 3450 6100 60 0001 C CNN
+F 3 "" H 3450 6100 60 0001 C CNN
+ 1 3450 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685AF2E4
+P 850 850
+F 0 "U1" H 900 950 30 0000 C CNN
+F 1 "PORT" H 850 850 30 0000 C CNN
+F 2 "" H 850 850 60 0000 C CNN
+F 3 "" H 850 850 60 0000 C CNN
+ 1 850 850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685AF341
+P 850 1350
+F 0 "U1" H 900 1450 30 0000 C CNN
+F 1 "PORT" H 850 1350 30 0000 C CNN
+F 2 "" H 850 1350 60 0000 C CNN
+F 3 "" H 850 1350 60 0000 C CNN
+ 2 850 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685AF3A8
+P 850 1850
+F 0 "U1" H 900 1950 30 0000 C CNN
+F 1 "PORT" H 850 1850 30 0000 C CNN
+F 2 "" H 850 1850 60 0000 C CNN
+F 3 "" H 850 1850 60 0000 C CNN
+ 3 850 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685AF403
+P 850 2350
+F 0 "U1" H 900 2450 30 0000 C CNN
+F 1 "PORT" H 850 2350 30 0000 C CNN
+F 2 "" H 850 2350 60 0000 C CNN
+F 3 "" H 850 2350 60 0000 C CNN
+ 4 850 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685AF4EA
+P 2300 4600
+F 0 "U1" H 2350 4700 30 0000 C CNN
+F 1 "PORT" H 2300 4600 30 0000 C CNN
+F 2 "" H 2300 4600 60 0000 C CNN
+F 3 "" H 2300 4600 60 0000 C CNN
+ 5 2300 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685AF571
+P 2300 5100
+F 0 "U1" H 2350 5200 30 0000 C CNN
+F 1 "PORT" H 2300 5100 30 0000 C CNN
+F 2 "" H 2300 5100 60 0000 C CNN
+F 3 "" H 2300 5100 60 0000 C CNN
+ 6 2300 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685AF624
+P 2300 5600
+F 0 "U1" H 2350 5700 30 0000 C CNN
+F 1 "PORT" H 2300 5600 30 0000 C CNN
+F 2 "" H 2300 5600 60 0000 C CNN
+F 3 "" H 2300 5600 60 0000 C CNN
+ 7 2300 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685AF6CD
+P 2300 6100
+F 0 "U1" H 2350 6200 30 0000 C CNN
+F 1 "PORT" H 2300 6100 30 0000 C CNN
+F 2 "" H 2300 6100 60 0000 C CNN
+F 3 "" H 2300 6100 60 0000 C CNN
+ 8 2300 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685AF8FA
+P 10650 3500
+F 0 "U1" H 10700 3600 30 0000 C CNN
+F 1 "PORT" H 10650 3500 30 0000 C CNN
+F 2 "" H 10650 3500 60 0000 C CNN
+F 3 "" H 10650 3500 60 0000 C CNN
+ 11 10650 3500
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685AF9B9
+P 10650 3850
+F 0 "U1" H 10700 3950 30 0000 C CNN
+F 1 "PORT" H 10650 3850 30 0000 C CNN
+F 2 "" H 10650 3850 60 0000 C CNN
+F 3 "" H 10650 3850 60 0000 C CNN
+ 12 10650 3850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685AFD96
+P 4900 600
+F 0 "U1" H 4950 700 30 0000 C CNN
+F 1 "PORT" H 4900 600 30 0000 C CNN
+F 2 "" H 4900 600 60 0000 C CNN
+F 3 "" H 4900 600 60 0000 C CNN
+ 9 4900 600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685B0001
+P 5700 7700
+F 0 "U1" H 5750 7800 30 0000 C CNN
+F 1 "PORT" H 5700 7700 30 0000 C CNN
+F 2 "" H 5700 7700 60 0000 C CNN
+F 3 "" H 5700 7700 60 0000 C CNN
+ 10 5700 7700
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC17
+U 1 1 685B0511
+P 5350 2600
+F 0 "SC17" H 5400 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 2687 50 0000 R CNN
+F 2 "" H 5350 1100 50 0001 C CNN
+F 3 "" H 5350 2600 50 0001 C CNN
+ 1 5350 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC20
+U 1 1 685B05AA
+P 6000 2600
+F 0 "SC20" H 6050 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6300 2687 50 0000 R CNN
+F 2 "" H 6000 1100 50 0001 C CNN
+F 3 "" H 6000 2600 50 0001 C CNN
+ 1 6000 2600
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC18
+U 1 1 685B066D
+P 5500 3400
+F 0 "SC18" H 5550 3700 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5800 3487 50 0000 R CNN
+F 2 "" H 5500 1900 50 0001 C CNN
+F 3 "" H 5500 3400 50 0001 C CNN
+ 1 5500 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC19
+U 1 1 685B071E
+P 5900 4050
+F 0 "SC19" H 5950 4350 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6200 4137 50 0000 R CNN
+F 2 "" H 5900 2550 50 0001 C CNN
+F 3 "" H 5900 4050 50 0001 C CNN
+ 1 5900 4050
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1100 850 1350 850
+Wire Wire Line
+ 1100 1350 1350 1350
+Wire Wire Line
+ 1100 1850 1350 1850
+Wire Wire Line
+ 1100 2350 1350 2350
+Wire Wire Line
+ 2550 4600 2800 4600
+Wire Wire Line
+ 2550 5100 2800 5100
+Wire Wire Line
+ 2550 5600 2800 5600
+Wire Wire Line
+ 2550 6100 2800 6100
+Wire Wire Line
+ 4300 1300 4300 1350
+Wire Wire Line
+ 4300 1950 4300 2000
+Wire Wire Line
+ 4300 2600 4300 2650
+Wire Wire Line
+ 4300 3350 4300 3250
+Wire Wire Line
+ 3800 2950 3800 3650
+Wire Wire Line
+ 3800 2300 3100 2300
+Wire Wire Line
+ 3100 1850 3100 3650
+Wire Wire Line
+ 3800 1650 2400 1650
+Wire Wire Line
+ 2400 1650 2400 3650
+Wire Wire Line
+ 3800 1000 1700 1000
+Wire Wire Line
+ 1700 1000 1700 3650
+Wire Wire Line
+ 2800 850 2800 1000
+Connection ~ 2800 1000
+Wire Wire Line
+ 2800 1350 2800 1650
+Connection ~ 2800 1650
+Wire Wire Line
+ 2800 1850 3100 1850
+Connection ~ 3100 2300
+Wire Wire Line
+ 2800 2350 3650 2350
+Wire Wire Line
+ 3650 2350 3650 3000
+Wire Wire Line
+ 3650 3000 3800 3000
+Connection ~ 3800 3000
+Wire Wire Line
+ 5300 4950 5300 5000
+Wire Wire Line
+ 5300 5600 5300 5650
+Wire Wire Line
+ 5300 6250 5300 6300
+Wire Wire Line
+ 5300 6900 5300 7000
+Wire Wire Line
+ 4800 6600 4800 7300
+Wire Wire Line
+ 4800 5950 4100 5950
+Wire Wire Line
+ 4100 5950 4100 7300
+Wire Wire Line
+ 4800 5300 3400 5300
+Wire Wire Line
+ 3400 5300 3400 7300
+Wire Wire Line
+ 4800 4650 2700 4650
+Wire Wire Line
+ 2700 4650 2700 7300
+Wire Wire Line
+ 4250 6100 4250 6650
+Wire Wire Line
+ 4250 6650 4800 6650
+Connection ~ 4800 6650
+Wire Wire Line
+ 4250 5600 4250 5950
+Connection ~ 4250 5950
+Wire Wire Line
+ 4250 5100 4250 5300
+Connection ~ 4250 5300
+Wire Wire Line
+ 4300 4600 4250 4600
+Wire Wire Line
+ 4300 4600 4300 4650
+Connection ~ 4300 4650
+Wire Wire Line
+ 10200 3500 10400 3500
+Wire Wire Line
+ 7050 3000 7050 4300
+Wire Wire Line
+ 7050 3500 7200 3500
+Wire Wire Line
+ 8650 3500 8750 3500
+Wire Wire Line
+ 5550 2900 5800 2900
+Wire Wire Line
+ 5700 3100 5700 2900
+Connection ~ 5700 2900
+Wire Wire Line
+ 5700 3000 7050 3000
+Connection ~ 7050 3500
+Connection ~ 5700 3000
+Wire Wire Line
+ 5700 3750 5700 3700
+Wire Wire Line
+ 5550 2300 5800 2300
+Wire Wire Line
+ 5050 2600 5050 3400
+Wire Wire Line
+ 5050 3400 5200 3400
+Wire Wire Line
+ 2200 3300 5050 3300
+Connection ~ 5050 3300
+Connection ~ 4300 3300
+Wire Wire Line
+ 6300 2600 6300 4050
+Wire Wire Line
+ 6300 4050 6200 4050
+Wire Wire Line
+ 3200 6950 6400 6950
+Wire Wire Line
+ 6400 6950 6400 3800
+Wire Wire Line
+ 6400 3800 6300 3800
+Connection ~ 6300 3800
+Connection ~ 5300 6950
+Wire Wire Line
+ 4300 700 4450 700
+Wire Wire Line
+ 4450 550 4450 4250
+Wire Wire Line
+ 4450 4250 5450 4250
+Wire Wire Line
+ 5300 4250 5300 4350
+Wire Wire Line
+ 5450 4250 5450 6600
+Wire Wire Line
+ 5450 6600 5200 6600
+Connection ~ 5300 4250
+Wire Wire Line
+ 5200 5950 5450 5950
+Connection ~ 5450 5950
+Wire Wire Line
+ 5200 5300 5450 5300
+Connection ~ 5450 5300
+Wire Wire Line
+ 5200 4650 5450 4650
+Connection ~ 5450 4650
+Wire Wire Line
+ 4200 2950 4450 2950
+Connection ~ 4450 2950
+Wire Wire Line
+ 4200 2300 4450 2300
+Connection ~ 4450 2300
+Wire Wire Line
+ 4200 1650 8750 1650
+Connection ~ 4450 1650
+Wire Wire Line
+ 4200 1000 4450 1000
+Connection ~ 4450 1000
+Wire Wire Line
+ 2200 3300 2200 3350
+Wire Wire Line
+ 2900 3350 2900 3300
+Connection ~ 2900 3300
+Wire Wire Line
+ 3600 3350 3600 3300
+Connection ~ 3600 3300
+Wire Wire Line
+ 3200 6950 3200 7000
+Wire Wire Line
+ 3900 7000 3900 6950
+Connection ~ 3900 6950
+Wire Wire Line
+ 4600 7000 4600 6950
+Connection ~ 4600 6950
+Wire Wire Line
+ 1350 2200 1100 2200
+Wire Wire Line
+ 1100 550 1100 4450
+Wire Wire Line
+ 1100 550 4450 550
+Connection ~ 4450 700
+Wire Wire Line
+ 1350 1700 1100 1700
+Connection ~ 1100 1700
+Wire Wire Line
+ 1350 1200 1100 1200
+Connection ~ 1100 1200
+Wire Wire Line
+ 1350 700 1100 700
+Connection ~ 1100 700
+Wire Wire Line
+ 1100 4450 2800 4450
+Connection ~ 1100 2200
+Wire Wire Line
+ 2800 5950 2600 5950
+Wire Wire Line
+ 2600 5950 2600 4450
+Connection ~ 2600 4450
+Wire Wire Line
+ 2800 4950 2600 4950
+Connection ~ 2600 4950
+Wire Wire Line
+ 2800 5450 2600 5450
+Connection ~ 2600 5450
+Wire Wire Line
+ 5450 2600 5600 2600
+Wire Wire Line
+ 5600 2600 5600 2300
+Connection ~ 5600 2300
+Wire Wire Line
+ 5900 2600 5750 2600
+Wire Wire Line
+ 5750 2600 5750 2300
+Connection ~ 5750 2300
+Wire Wire Line
+ 5700 1650 5700 2300
+Connection ~ 5700 2300
+Wire Wire Line
+ 8750 1650 8750 3350
+Connection ~ 5700 1650
+Wire Wire Line
+ 7200 3350 7200 1650
+Connection ~ 7200 1650
+Wire Wire Line
+ 4650 600 4450 600
+Connection ~ 4450 600
+Wire Wire Line
+ 1350 1000 1200 1000
+Wire Wire Line
+ 1200 1000 1200 7700
+Wire Wire Line
+ 1350 1500 1200 1500
+Connection ~ 1200 1500
+Wire Wire Line
+ 1350 2000 1200 2000
+Connection ~ 1200 2000
+Wire Wire Line
+ 1350 2500 1200 2500
+Connection ~ 1200 2500
+Wire Wire Line
+ 1200 4050 5800 4050
+Wire Wire Line
+ 4300 4050 4300 3950
+Wire Wire Line
+ 4200 3650 4350 3650
+Wire Wire Line
+ 4350 3650 4350 4050
+Connection ~ 4300 4050
+Wire Wire Line
+ 3600 3950 3600 4050
+Connection ~ 3600 4050
+Wire Wire Line
+ 3500 3650 3650 3650
+Wire Wire Line
+ 3650 3650 3650 4050
+Connection ~ 3650 4050
+Wire Wire Line
+ 2900 3950 2900 4050
+Connection ~ 2900 4050
+Wire Wire Line
+ 2800 3650 2950 3650
+Wire Wire Line
+ 2950 3650 2950 4050
+Connection ~ 2950 4050
+Wire Wire Line
+ 2200 3950 2200 4050
+Connection ~ 2200 4050
+Wire Wire Line
+ 2100 3650 2250 3650
+Wire Wire Line
+ 2250 3650 2250 4050
+Connection ~ 2250 4050
+Wire Wire Line
+ 1200 7700 5450 7700
+Wire Wire Line
+ 5300 7700 5300 7600
+Connection ~ 1200 4050
+Wire Wire Line
+ 5200 7300 5350 7300
+Wire Wire Line
+ 5350 7300 5350 7700
+Connection ~ 5300 7700
+Wire Wire Line
+ 4600 7600 4600 7700
+Connection ~ 4600 7700
+Wire Wire Line
+ 4500 7300 4650 7300
+Wire Wire Line
+ 4650 7300 4650 7700
+Connection ~ 4650 7700
+Wire Wire Line
+ 3900 7600 3900 7700
+Connection ~ 3900 7700
+Wire Wire Line
+ 3800 7300 3950 7300
+Wire Wire Line
+ 3950 7300 3950 7700
+Connection ~ 3950 7700
+Wire Wire Line
+ 3200 7600 3200 7700
+Connection ~ 3200 7700
+Wire Wire Line
+ 3100 7300 3250 7300
+Wire Wire Line
+ 3250 7300 3250 7700
+Connection ~ 3250 7700
+Connection ~ 5350 7700
+Wire Wire Line
+ 2800 4750 1200 4750
+Connection ~ 1200 4750
+Wire Wire Line
+ 2800 5250 1200 5250
+Connection ~ 1200 5250
+Wire Wire Line
+ 2800 5750 1200 5750
+Connection ~ 1200 5750
+Wire Wire Line
+ 2800 6250 1200 6250
+Connection ~ 1200 6250
+Wire Wire Line
+ 5550 4050 5550 4400
+Wire Wire Line
+ 5550 4400 8750 4400
+Wire Wire Line
+ 8750 4400 8750 3650
+Connection ~ 4350 4050
+Wire Wire Line
+ 7200 3650 7200 4400
+Connection ~ 7200 4400
+Wire Wire Line
+ 5700 4350 5700 4400
+Connection ~ 5700 4400
+Connection ~ 5550 4050
+Wire Wire Line
+ 5600 3400 6000 3400
+Wire Wire Line
+ 6000 3400 6000 4400
+Connection ~ 6000 4400
+$Comp
+L SKY130mode scmode1
+U 1 1 685BA6E8
+P 8750 5150
+F 0 "scmode1" H 8750 5300 98 0000 C CNB
+F 1 "SKY130mode" H 8750 5050 118 0000 C CNB
+F 2 "" H 8750 5300 60 0001 C CNN
+F 3 "" H 8750 5300 60 0001 C CNN
+ 1 8750 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X11
+U 1 1 685B8BEB
+P 8900 4300
+F 0 "X11" H 8900 4300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 9000 4050 60 0000 C CNN
+F 2 "" H 8900 4300 60 0001 C CNN
+F 3 "" H 8900 4300 60 0001 C CNN
+ 1 8900 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9700 4300 10400 4300
+Wire Wire Line
+ 10400 4300 10400 3850
+Wire Wire Line
+ 8250 4150 8250 1650
+Connection ~ 8250 1650
+Wire Wire Line
+ 7050 4300 8250 4300
+Wire Wire Line
+ 8250 4450 8250 4400
+Connection ~ 8250 4400
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4068B/CD4068B.sub b/library/SubcircuitLibrary/CD4068B/CD4068B.sub
new file mode 100644
index 000000000..ebf5fb5d2
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CD4068B.sub
@@ -0,0 +1,41 @@
+* Subcircuit CD4068B
+.subckt CD4068B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_sc12-pad3_ net-_sc1-pad3_ net-_u1-pad11_ net-_u1-pad12_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cd4068b/cd4068b.cir
+.include CMOS_INVTR.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc6 net-_sc6-pad1_ net-_sc1-pad2_ net-_sc12-pad3_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc7 net-_sc7-pad1_ net-_sc2-pad2_ net-_sc6-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc8-pad1_ net-_sc4-pad2_ net-_sc7-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc9 net-_sc1-pad1_ net-_sc10-pad2_ net-_sc8-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc10 net-_sc1-pad1_ net-_sc10-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad1_ net-_sc4-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc12 net-_sc12-pad1_ net-_sc12-pad2_ net-_sc12-pad3_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc13 net-_sc13-pad1_ net-_sc13-pad2_ net-_sc12-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc14 net-_sc14-pad1_ net-_sc11-pad2_ net-_sc13-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc15 net-_sc11-pad1_ net-_sc15-pad2_ net-_sc14-pad1_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc16 net-_sc11-pad1_ net-_sc15-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc11 net-_sc11-pad1_ net-_sc11-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc11-pad1_ net-_sc13-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc11-pad1_ net-_sc12-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+x9 net-_sc17-pad1_ net-_sc12-pad3_ net-_sc1-pad3_ net-_x10-pad1_ CMOS_INVTR
+x10 net-_x10-pad1_ net-_sc12-pad3_ net-_sc1-pad3_ net-_u1-pad11_ CMOS_INVTR
+x1 net-_u1-pad1_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc1-pad2_ CMOS_INVTR
+x2 net-_u1-pad2_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc2-pad2_ CMOS_INVTR
+x3 net-_u1-pad3_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc4-pad2_ CMOS_INVTR
+x4 net-_u1-pad4_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc10-pad2_ CMOS_INVTR
+x5 net-_u1-pad5_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc12-pad2_ CMOS_INVTR
+x6 net-_u1-pad6_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc13-pad2_ CMOS_INVTR
+x7 net-_u1-pad7_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc11-pad2_ CMOS_INVTR
+x8 net-_u1-pad8_ net-_sc12-pad3_ net-_sc1-pad3_ net-_sc15-pad2_ CMOS_INVTR
+xsc17 net-_sc17-pad1_ net-_sc1-pad1_ net-_sc12-pad3_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc20 net-_sc17-pad1_ net-_sc11-pad1_ net-_sc12-pad3_ net-_sc12-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc18 net-_sc17-pad1_ net-_sc1-pad1_ net-_sc18-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc19 net-_sc18-pad3_ net-_sc11-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+x11 net-_sc17-pad1_ net-_sc12-pad3_ net-_sc1-pad3_ net-_u1-pad12_ CMOS_INVTR
+* Control Statements
+
+.ends CD4068B
diff --git a/library/SubcircuitLibrary/CD4068B/CD4068B_Previous_Values.xml b/library/SubcircuitLibrary/CD4068B/CD4068B_Previous_Values.xml
new file mode 100644
index 000000000..9c603a591
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CD4068B_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4068B/CMOS_INVTR-cache.lib b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.cir b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.cir
new file mode 100644
index 000000000..d2199ddbb
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/CMOS_INVTR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 13 08:49:20 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.cir.out b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.cir.out
new file mode 100644
index 000000000..dec1c5fa5
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.pro b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.sch b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.sch
new file mode 100644
index 000000000..aa7a7ee81
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.sch
@@ -0,0 +1,161 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 684B982F
+P 5350 2950
+F 0 "SC1" H 5400 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 3037 50 0000 R CNN
+F 2 "" H 5350 1450 50 0001 C CNN
+F 3 "" H 5350 2950 50 0001 C CNN
+ 1 5350 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684B9856
+P 5350 3800
+F 0 "SC2" H 5400 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5650 3887 50 0000 R CNN
+F 2 "" H 5350 2300 50 0001 C CNN
+F 3 "" H 5350 3800 50 0001 C CNN
+ 1 5350 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B98AD
+P 4550 3300
+F 0 "U1" H 4600 3400 30 0000 C CNN
+F 1 "PORT" H 4550 3300 30 0000 C CNN
+F 2 "" H 4550 3300 60 0000 C CNN
+F 3 "" H 4550 3300 60 0000 C CNN
+ 1 4550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B98D8
+P 6300 3350
+F 0 "U1" H 6350 3450 30 0000 C CNN
+F 1 "PORT" H 6300 3350 30 0000 C CNN
+F 2 "" H 6300 3350 60 0000 C CNN
+F 3 "" H 6300 3350 60 0000 C CNN
+ 4 6300 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B9935
+P 5300 4350
+F 0 "U1" H 5350 4450 30 0000 C CNN
+F 1 "PORT" H 5300 4350 30 0000 C CNN
+F 2 "" H 5300 4350 60 0000 C CNN
+F 3 "" H 5300 4350 60 0000 C CNN
+ 3 5300 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B999A
+P 5300 2350
+F 0 "U1" H 5350 2450 30 0000 C CNN
+F 1 "PORT" H 5300 2350 30 0000 C CNN
+F 2 "" H 5300 2350 60 0000 C CNN
+F 3 "" H 5300 2350 60 0000 C CNN
+ 2 5300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B99CD
+P 7950 3000
+F 0 "scmode1" H 7950 3150 98 0000 C CNB
+F 1 "SKY130mode" H 7950 2900 118 0000 C CNB
+F 2 "" H 7950 3150 60 0001 C CNN
+F 3 "" H 7950 3150 60 0001 C CNN
+ 1 7950 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 2650 5550 2350
+Wire Wire Line
+ 5450 2950 5600 2950
+Wire Wire Line
+ 5600 2950 5600 2550
+Wire Wire Line
+ 5600 2550 5550 2550
+Connection ~ 5550 2550
+Wire Wire Line
+ 5550 3250 5550 3500
+Wire Wire Line
+ 6050 3350 5550 3350
+Connection ~ 5550 3350
+Wire Wire Line
+ 5050 2950 5050 3800
+Wire Wire Line
+ 4800 3300 5050 3300
+Connection ~ 5050 3300
+Wire Wire Line
+ 5450 3800 5600 3800
+Wire Wire Line
+ 5600 3800 5600 4150
+Wire Wire Line
+ 5600 4150 5550 4150
+Wire Wire Line
+ 5550 4100 5550 4350
+Connection ~ 5550 4150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.sub b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.sub
new file mode 100644
index 000000000..8283bca86
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR.sub
@@ -0,0 +1,11 @@
+* Subcircuit CMOS_INVTR
+.subckt CMOS_INVTR net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends CMOS_INVTR
diff --git a/library/SubcircuitLibrary/CD4068B/CMOS_INVTR_Previous_Values.xml b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR_Previous_Values.xml
new file mode 100644
index 000000000..d17c4f93e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/CMOS_INVTR_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3, l=0.15w=1, l=0.15
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4068B/analysis b/library/SubcircuitLibrary/CD4068B/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4068B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B-cache.lib b/library/SubcircuitLibrary/CD4085B/CD4085B-cache.lib
new file mode 100644
index 000000000..348446c2e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/CD4085B-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.bak b/library/SubcircuitLibrary/CD4085B/CD4085B.bak
new file mode 100644
index 000000000..5dcca9bb8
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/CD4085B.bak
@@ -0,0 +1,1384 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:AOI-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M3
+U 1 1 685581CA
+P 8450 3050
+F 0 "M3" H 8400 3100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 8500 3200 50 0000 R CNN
+F 2 "" H 8700 3150 29 0000 C CNN
+F 3 "" H 8500 3050 60 0000 C CNN
+ 1 8450 3050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M11
+U 1 1 685581CB
+P 10050 3050
+F 0 "M11" H 10000 3100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10100 3200 50 0000 R CNN
+F 2 "" H 10300 3150 29 0000 C CNN
+F 3 "" H 10100 3050 60 0000 C CNN
+ 1 10050 3050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M12
+U 1 1 685581CC
+P 10050 4300
+F 0 "M12" H 10050 4150 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10150 4250 50 0000 R CNN
+F 2 "" H 10350 4000 29 0000 C CNN
+F 3 "" H 10150 4100 60 0000 C CNN
+ 1 10050 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M13
+U 1 1 685581CD
+P 10050 5350
+F 0 "M13" H 10050 5200 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10150 5300 50 0000 R CNN
+F 2 "" H 10350 5050 29 0000 C CNN
+F 3 "" H 10150 5150 60 0000 C CNN
+ 1 10050 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 685581CE
+P 8600 7600
+F 0 "M4" H 8550 7650 50 0000 R CNN
+F 1 "eSim_MOS_P" H 8650 7750 50 0000 R CNN
+F 2 "" H 8850 7700 29 0000 C CNN
+F 3 "" H 8650 7600 60 0000 C CNN
+ 1 8600 7600
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M14
+U 1 1 685581CF
+P 10200 7600
+F 0 "M14" H 10150 7650 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10250 7750 50 0000 R CNN
+F 2 "" H 10450 7700 29 0000 C CNN
+F 3 "" H 10250 7600 60 0000 C CNN
+ 1 10200 7600
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M15
+U 1 1 685581D0
+P 10200 8850
+F 0 "M15" H 10200 8700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10300 8800 50 0000 R CNN
+F 2 "" H 10500 8550 29 0000 C CNN
+F 3 "" H 10300 8650 60 0000 C CNN
+ 1 10200 8850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M16
+U 1 1 685581D1
+P 10200 9900
+F 0 "M16" H 10200 9750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10300 9850 50 0000 R CNN
+F 2 "" H 10500 9600 29 0000 C CNN
+F 3 "" H 10300 9700 60 0000 C CNN
+ 1 10200 9900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M18
+U 1 1 685581D2
+P 13100 4300
+F 0 "M18" H 13050 4350 50 0000 R CNN
+F 1 "eSim_MOS_P" H 13150 4450 50 0000 R CNN
+F 2 "" H 13350 4400 29 0000 C CNN
+F 3 "" H 13150 4300 60 0000 C CNN
+ 1 13100 4300
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M22
+U 1 1 685581D3
+P 14700 4300
+F 0 "M22" H 14650 4350 50 0000 R CNN
+F 1 "eSim_MOS_P" H 14750 4450 50 0000 R CNN
+F 2 "" H 14950 4400 29 0000 C CNN
+F 3 "" H 14750 4300 60 0000 C CNN
+ 1 14700 4300
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M23
+U 1 1 685581D4
+P 14700 5550
+F 0 "M23" H 14700 5400 50 0000 R CNN
+F 1 "eSim_MOS_N" H 14800 5500 50 0000 R CNN
+F 2 "" H 15000 5250 29 0000 C CNN
+F 3 "" H 14800 5350 60 0000 C CNN
+ 1 14700 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M24
+U 1 1 685581D5
+P 14700 6600
+F 0 "M24" H 14700 6450 50 0000 R CNN
+F 1 "eSim_MOS_N" H 14800 6550 50 0000 R CNN
+F 2 "" H 15000 6300 29 0000 C CNN
+F 3 "" H 14800 6400 60 0000 C CNN
+ 1 14700 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M31
+U 1 1 685581D6
+P 18650 2900
+F 0 "M31" H 18600 2950 50 0000 R CNN
+F 1 "eSim_MOS_P" H 18700 3050 50 0000 R CNN
+F 2 "" H 18900 3000 29 0000 C CNN
+F 3 "" H 18700 2900 60 0000 C CNN
+ 1 18650 2900
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M32
+U 1 1 685581D7
+P 18650 4050
+F 0 "M32" H 18600 4100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 18700 4200 50 0000 R CNN
+F 2 "" H 18900 4150 29 0000 C CNN
+F 3 "" H 18700 4050 60 0000 C CNN
+ 1 18650 4050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M30
+U 1 1 685581D8
+P 18600 4850
+F 0 "M30" H 18600 4700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 18700 4800 50 0000 R CNN
+F 2 "" H 18900 4550 29 0000 C CNN
+F 3 "" H 18700 4650 60 0000 C CNN
+ 1 18600 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M26
+U 1 1 685581D9
+P 17000 4900
+F 0 "M26" H 17000 4750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 17100 4850 50 0000 R CNN
+F 2 "" H 17300 4600 29 0000 C CNN
+F 3 "" H 17100 4700 60 0000 C CNN
+ 1 17000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M35
+U 1 1 685581DA
+P 21400 5100
+F 0 "M35" H 21400 4950 50 0000 R CNN
+F 1 "eSim_MOS_N" H 21500 5050 50 0000 R CNN
+F 2 "" H 21700 4800 29 0000 C CNN
+F 3 "" H 21500 4900 60 0000 C CNN
+ 1 21400 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M36
+U 1 1 685581DB
+P 21450 4000
+F 0 "M36" H 21400 4050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 21500 4150 50 0000 R CNN
+F 2 "" H 21700 4100 29 0000 C CNN
+F 3 "" H 21500 4000 60 0000 C CNN
+ 1 21450 4000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M39
+U 1 1 685581DC
+P 24350 5150
+F 0 "M39" H 24350 5000 50 0000 R CNN
+F 1 "eSim_MOS_N" H 24450 5100 50 0000 R CNN
+F 2 "" H 24650 4850 29 0000 C CNN
+F 3 "" H 24450 4950 60 0000 C CNN
+ 1 24350 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M40
+U 1 1 685581DD
+P 24400 4050
+F 0 "M40" H 24350 4100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 24450 4200 50 0000 R CNN
+F 2 "" H 24650 4150 29 0000 C CNN
+F 3 "" H 24450 4050 60 0000 C CNN
+ 1 24400 4050
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685581DE
+P 5650 4000
+F 0 "U1" H 5700 4100 30 0000 C CNN
+F 1 "PORT" H 5650 4000 30 0000 C CNN
+F 2 "" H 5650 4000 60 0000 C CNN
+F 3 "" H 5650 4000 60 0000 C CNN
+ 1 5650 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685581DF
+P 5700 5500
+F 0 "U1" H 5750 5600 30 0000 C CNN
+F 1 "PORT" H 5700 5500 30 0000 C CNN
+F 2 "" H 5700 5500 60 0000 C CNN
+F 3 "" H 5700 5500 60 0000 C CNN
+ 2 5700 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685581E0
+P 7200 8550
+F 0 "U1" H 7250 8650 30 0000 C CNN
+F 1 "PORT" H 7200 8550 30 0000 C CNN
+F 2 "" H 7200 8550 60 0000 C CNN
+F 3 "" H 7200 8550 60 0000 C CNN
+ 12 7200 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685581E1
+P 7350 10000
+F 0 "U1" H 7400 10100 30 0000 C CNN
+F 1 "PORT" H 7350 10000 30 0000 C CNN
+F 2 "" H 7350 10000 60 0000 C CNN
+F 3 "" H 7350 10000 60 0000 C CNN
+ 13 7350 10000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685581E2
+P 26350 4600
+F 0 "U1" H 26400 4700 30 0000 C CNN
+F 1 "PORT" H 26350 4600 30 0000 C CNN
+F 2 "" H 26350 4600 60 0000 C CNN
+F 3 "" H 26350 4600 60 0000 C CNN
+ 3 26350 4600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685581E4
+P 14950 950
+F 0 "U1" H 15000 1050 30 0000 C CNN
+F 1 "PORT" H 14950 950 30 0000 C CNN
+F 2 "" H 14950 950 60 0000 C CNN
+F 3 "" H 14950 950 60 0000 C CNN
+ 14 14950 950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685581E5
+P 16000 1300
+F 0 "U1" H 16050 1400 30 0000 C CNN
+F 1 "PORT" H 16000 1300 30 0000 C CNN
+F 2 "" H 16000 1300 60 0000 C CNN
+F 3 "" H 16000 1300 60 0000 C CNN
+ 10 16000 1300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8600 2850 8600 2200
+Wire Wire Line
+ 8600 2200 10300 2200
+Wire Wire Line
+ 10200 2200 10200 2850
+Wire Wire Line
+ 10300 2200 10300 2900
+Connection ~ 10200 2200
+Wire Wire Line
+ 8700 2900 8700 2200
+Connection ~ 8700 2200
+Wire Wire Line
+ 8600 3250 8600 3700
+Wire Wire Line
+ 8600 3700 10250 3700
+Wire Wire Line
+ 10250 3300 10250 4300
+Wire Wire Line
+ 10200 3250 10200 3300
+Wire Wire Line
+ 10200 3300 10250 3300
+Connection ~ 10250 3700
+Wire Wire Line
+ 10250 4700 10250 5350
+Wire Wire Line
+ 10250 5750 10250 6100
+Wire Wire Line
+ 10350 5700 10350 5850
+Wire Wire Line
+ 10350 5850 10250 5850
+Connection ~ 10250 5850
+Wire Wire Line
+ 10350 4650 10350 4700
+Wire Wire Line
+ 10350 4700 10400 4700
+Wire Wire Line
+ 10400 4700 10400 6000
+Wire Wire Line
+ 10400 6000 10250 6000
+Connection ~ 10250 6000
+Wire Wire Line
+ 8300 3050 8000 3050
+Wire Wire Line
+ 8000 3050 8000 4500
+Wire Wire Line
+ 8000 4500 9950 4500
+Wire Wire Line
+ 9900 3050 9300 3050
+Wire Wire Line
+ 9300 3050 9300 5550
+Wire Wire Line
+ 7450 5550 9950 5550
+Wire Wire Line
+ 7450 5500 7450 5550
+Connection ~ 9300 5550
+Wire Wire Line
+ 8000 3900 7300 3900
+Wire Wire Line
+ 7300 3900 7300 3950
+Connection ~ 8000 3900
+Wire Wire Line
+ 8750 7400 8750 6750
+Wire Wire Line
+ 8750 6750 10450 6750
+Wire Wire Line
+ 10350 6750 10350 7400
+Wire Wire Line
+ 10450 6750 10450 7450
+Connection ~ 10350 6750
+Wire Wire Line
+ 8850 7450 8850 6750
+Connection ~ 8850 6750
+Wire Wire Line
+ 8750 7800 8750 8250
+Wire Wire Line
+ 8750 8250 10400 8250
+Wire Wire Line
+ 10400 7850 10400 8850
+Wire Wire Line
+ 10350 7800 10350 7850
+Wire Wire Line
+ 10350 7850 10400 7850
+Connection ~ 10400 8250
+Wire Wire Line
+ 10400 9250 10400 9900
+Wire Wire Line
+ 10400 10300 10400 10650
+Wire Wire Line
+ 10500 10250 10500 10400
+Wire Wire Line
+ 10500 10400 10400 10400
+Connection ~ 10400 10400
+Wire Wire Line
+ 10500 9200 10500 9250
+Wire Wire Line
+ 10500 9250 10550 9250
+Wire Wire Line
+ 10550 9250 10550 10550
+Wire Wire Line
+ 10550 10550 10400 10550
+Connection ~ 10400 10550
+Wire Wire Line
+ 8450 7600 8150 7600
+Wire Wire Line
+ 8150 7600 8150 9050
+Wire Wire Line
+ 8150 9050 10100 9050
+Wire Wire Line
+ 10050 7600 9450 7600
+Wire Wire Line
+ 9450 7600 9450 10100
+Wire Wire Line
+ 7600 10100 10100 10100
+Wire Wire Line
+ 7600 10000 7600 10100
+Connection ~ 9450 10100
+Wire Wire Line
+ 8150 8450 7450 8450
+Wire Wire Line
+ 7450 8450 7450 8550
+Connection ~ 8150 8450
+Wire Wire Line
+ 13250 4100 13250 3450
+Wire Wire Line
+ 13250 3450 14950 3450
+Wire Wire Line
+ 14850 3450 14850 4100
+Wire Wire Line
+ 14950 3450 14950 4150
+Connection ~ 14850 3450
+Wire Wire Line
+ 13350 4150 13350 3450
+Connection ~ 13350 3450
+Wire Wire Line
+ 13250 4500 13250 4950
+Wire Wire Line
+ 13250 4950 14900 4950
+Wire Wire Line
+ 14900 4550 14900 5550
+Wire Wire Line
+ 14850 4500 14850 4550
+Wire Wire Line
+ 14850 4550 14900 4550
+Connection ~ 14900 4950
+Wire Wire Line
+ 14900 5950 14900 6600
+Wire Wire Line
+ 14900 10650 14900 7000
+Wire Wire Line
+ 15000 6950 15000 7100
+Wire Wire Line
+ 15000 7100 14900 7100
+Connection ~ 14900 7100
+Wire Wire Line
+ 15000 5900 15000 5950
+Wire Wire Line
+ 15000 5950 15050 5950
+Wire Wire Line
+ 15050 5950 15050 7250
+Wire Wire Line
+ 15050 7250 14900 7250
+Connection ~ 14900 7250
+Wire Wire Line
+ 12950 4300 12650 4300
+Wire Wire Line
+ 12650 4300 12650 5750
+Wire Wire Line
+ 12650 5750 14600 5750
+Wire Wire Line
+ 14550 4300 13950 4300
+Wire Wire Line
+ 13950 4300 13950 6800
+Wire Wire Line
+ 12100 6800 14600 6800
+Wire Wire Line
+ 12100 6800 12100 6750
+Connection ~ 13950 6800
+Wire Wire Line
+ 12650 5150 11950 5150
+Wire Wire Line
+ 11950 5150 11950 5200
+Connection ~ 12650 5150
+Wire Wire Line
+ 10250 3500 11400 3500
+Wire Wire Line
+ 11400 3500 11400 5200
+Wire Wire Line
+ 11400 5200 11950 5200
+Connection ~ 10250 3500
+Wire Wire Line
+ 10400 8000 11550 8000
+Wire Wire Line
+ 11550 8000 11550 6750
+Wire Wire Line
+ 11550 6750 12100 6750
+Connection ~ 10400 8000
+Wire Wire Line
+ 18800 2700 18800 2050
+Wire Wire Line
+ 18900 2750 18900 2050
+Wire Wire Line
+ 18900 3900 18900 3500
+Wire Wire Line
+ 18900 3500 19200 3500
+Wire Wire Line
+ 19200 3500 19200 2050
+Wire Wire Line
+ 18800 3100 18800 3850
+Wire Wire Line
+ 18800 4250 18800 4850
+Wire Wire Line
+ 17200 4900 17200 4450
+Wire Wire Line
+ 17200 4450 18800 4450
+Connection ~ 18800 4450
+Wire Wire Line
+ 14900 4650 16200 4650
+Wire Wire Line
+ 16200 4650 16200 3700
+Wire Wire Line
+ 16200 3700 18100 3700
+Wire Wire Line
+ 18100 3700 18100 5050
+Wire Wire Line
+ 18100 4050 18500 4050
+Connection ~ 14900 4650
+Wire Wire Line
+ 18100 5050 18500 5050
+Connection ~ 18100 4050
+Wire Wire Line
+ 16250 2900 18500 2900
+Wire Wire Line
+ 16250 1300 16250 2900
+Wire Wire Line
+ 16400 2900 16400 5100
+Wire Wire Line
+ 16400 5100 16900 5100
+Connection ~ 16400 2900
+Wire Wire Line
+ 17200 5300 17200 7350
+Wire Wire Line
+ 14900 7350 21700 7350
+Wire Wire Line
+ 18800 7350 18800 5250
+Connection ~ 17200 7350
+Wire Wire Line
+ 18900 7350 18900 5200
+Connection ~ 18800 7350
+Wire Wire Line
+ 17300 5250 17300 7350
+Connection ~ 17300 7350
+Wire Wire Line
+ 18800 2050 24650 2050
+Connection ~ 18900 2050
+Wire Wire Line
+ 18800 4600 20850 4600
+Connection ~ 18800 4600
+Wire Wire Line
+ 21300 4000 20850 4000
+Wire Wire Line
+ 20850 4000 20850 5300
+Wire Wire Line
+ 20850 5300 21300 5300
+Connection ~ 20850 4600
+Wire Wire Line
+ 21600 4200 21600 5100
+Wire Wire Line
+ 21600 2050 21600 3800
+Connection ~ 19200 2050
+Wire Wire Line
+ 21700 2050 21700 3850
+Connection ~ 21600 2050
+Wire Wire Line
+ 21600 7350 21600 5500
+Connection ~ 18900 7350
+Wire Wire Line
+ 21700 5450 21700 7400
+Connection ~ 21600 7350
+Wire Wire Line
+ 21600 4650 23800 4650
+Wire Wire Line
+ 24250 4050 23800 4050
+Wire Wire Line
+ 23800 4050 23800 5350
+Wire Wire Line
+ 23800 5350 24250 5350
+Connection ~ 23800 4650
+Wire Wire Line
+ 24550 4250 24550 5150
+Wire Wire Line
+ 24550 2050 24550 3850
+Wire Wire Line
+ 24650 2050 24650 3900
+Wire Wire Line
+ 24550 7400 24550 5550
+Wire Wire Line
+ 24650 7400 24650 5500
+Connection ~ 21600 4650
+Wire Wire Line
+ 21700 7400 24650 7400
+Connection ~ 21700 7350
+Connection ~ 24550 7400
+Connection ~ 21700 2050
+Connection ~ 24550 2050
+Wire Wire Line
+ 24550 4650 25750 4650
+Wire Wire Line
+ 25750 4650 25750 4600
+Connection ~ 24550 4650
+Wire Wire Line
+ 14050 1600 14050 3450
+Wire Wire Line
+ 4150 1600 21850 1600
+Wire Wire Line
+ 21850 1600 21850 2050
+Connection ~ 21850 2050
+Connection ~ 14050 3450
+Connection ~ 9200 2200
+Wire Wire Line
+ 6750 1600 6750 6300
+Wire Wire Line
+ 6750 6300 9550 6300
+Wire Wire Line
+ 9550 6300 9550 6750
+Connection ~ 9550 6750
+Wire Wire Line
+ 10250 6100 11000 6100
+Wire Wire Line
+ 11000 6100 11000 10650
+Wire Wire Line
+ 10400 10650 26800 10650
+Connection ~ 14900 7350
+Connection ~ 11000 10650
+Wire Wire Line
+ 14600 950 14600 1600
+Wire Wire Line
+ 14600 950 14700 950
+Wire Wire Line
+ 5950 5500 7450 5500
+Wire Wire Line
+ 7300 3950 5900 3950
+Wire Wire Line
+ 5900 3950 5900 4000
+Wire Wire Line
+ 25750 4600 26100 4600
+Wire Wire Line
+ 9200 1600 9200 2200
+Connection ~ 14050 1600
+Connection ~ 9200 1600
+Connection ~ 14600 1600
+$Comp
+L eSim_MOS_P M1
+U 1 1 6855AD22
+P 7550 13800
+F 0 "M1" H 7500 13850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 7600 13950 50 0000 R CNN
+F 2 "" H 7800 13900 29 0000 C CNN
+F 3 "" H 7600 13800 60 0000 C CNN
+ 1 7550 13800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M5
+U 1 1 6855AD28
+P 9150 13800
+F 0 "M5" H 9100 13850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 9200 13950 50 0000 R CNN
+F 2 "" H 9400 13900 29 0000 C CNN
+F 3 "" H 9200 13800 60 0000 C CNN
+ 1 9150 13800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M6
+U 1 1 6855AD2E
+P 9150 15050
+F 0 "M6" H 9150 14900 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9250 15000 50 0000 R CNN
+F 2 "" H 9450 14750 29 0000 C CNN
+F 3 "" H 9250 14850 60 0000 C CNN
+ 1 9150 15050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M7
+U 1 1 6855AD34
+P 9150 16100
+F 0 "M7" H 9150 15950 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9250 16050 50 0000 R CNN
+F 2 "" H 9450 15800 29 0000 C CNN
+F 3 "" H 9250 15900 60 0000 C CNN
+ 1 9150 16100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M2
+U 1 1 6855AD3A
+P 7700 18350
+F 0 "M2" H 7650 18400 50 0000 R CNN
+F 1 "eSim_MOS_P" H 7750 18500 50 0000 R CNN
+F 2 "" H 7950 18450 29 0000 C CNN
+F 3 "" H 7750 18350 60 0000 C CNN
+ 1 7700 18350
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M8
+U 1 1 6855AD40
+P 9300 18350
+F 0 "M8" H 9250 18400 50 0000 R CNN
+F 1 "eSim_MOS_P" H 9350 18500 50 0000 R CNN
+F 2 "" H 9550 18450 29 0000 C CNN
+F 3 "" H 9350 18350 60 0000 C CNN
+ 1 9300 18350
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M9
+U 1 1 6855AD46
+P 9300 19600
+F 0 "M9" H 9300 19450 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9400 19550 50 0000 R CNN
+F 2 "" H 9600 19300 29 0000 C CNN
+F 3 "" H 9400 19400 60 0000 C CNN
+ 1 9300 19600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 6855AD4C
+P 9300 20650
+F 0 "M10" H 9300 20500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9400 20600 50 0000 R CNN
+F 2 "" H 9600 20350 29 0000 C CNN
+F 3 "" H 9400 20450 60 0000 C CNN
+ 1 9300 20650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M17
+U 1 1 6855AD52
+P 12200 15050
+F 0 "M17" H 12150 15100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 12250 15200 50 0000 R CNN
+F 2 "" H 12450 15150 29 0000 C CNN
+F 3 "" H 12250 15050 60 0000 C CNN
+ 1 12200 15050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M19
+U 1 1 6855AD58
+P 13800 15050
+F 0 "M19" H 13750 15100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 13850 15200 50 0000 R CNN
+F 2 "" H 14050 15150 29 0000 C CNN
+F 3 "" H 13850 15050 60 0000 C CNN
+ 1 13800 15050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M20
+U 1 1 6855AD5E
+P 13800 16300
+F 0 "M20" H 13800 16150 50 0000 R CNN
+F 1 "eSim_MOS_N" H 13900 16250 50 0000 R CNN
+F 2 "" H 14100 16000 29 0000 C CNN
+F 3 "" H 13900 16100 60 0000 C CNN
+ 1 13800 16300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M21
+U 1 1 6855AD64
+P 13800 17350
+F 0 "M21" H 13800 17200 50 0000 R CNN
+F 1 "eSim_MOS_N" H 13900 17300 50 0000 R CNN
+F 2 "" H 14100 17050 29 0000 C CNN
+F 3 "" H 13900 17150 60 0000 C CNN
+ 1 13800 17350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M28
+U 1 1 6855AD6A
+P 17750 13650
+F 0 "M28" H 17700 13700 50 0000 R CNN
+F 1 "eSim_MOS_P" H 17800 13800 50 0000 R CNN
+F 2 "" H 18000 13750 29 0000 C CNN
+F 3 "" H 17800 13650 60 0000 C CNN
+ 1 17750 13650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M29
+U 1 1 6855AD70
+P 17750 14800
+F 0 "M29" H 17700 14850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 17800 14950 50 0000 R CNN
+F 2 "" H 18000 14900 29 0000 C CNN
+F 3 "" H 17800 14800 60 0000 C CNN
+ 1 17750 14800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M27
+U 1 1 6855AD76
+P 17700 15600
+F 0 "M27" H 17700 15450 50 0000 R CNN
+F 1 "eSim_MOS_N" H 17800 15550 50 0000 R CNN
+F 2 "" H 18000 15300 29 0000 C CNN
+F 3 "" H 17800 15400 60 0000 C CNN
+ 1 17700 15600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M25
+U 1 1 6855AD7C
+P 16100 15650
+F 0 "M25" H 16100 15500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 16200 15600 50 0000 R CNN
+F 2 "" H 16400 15350 29 0000 C CNN
+F 3 "" H 16200 15450 60 0000 C CNN
+ 1 16100 15650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M33
+U 1 1 6855AD82
+P 20500 15850
+F 0 "M33" H 20500 15700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 20600 15800 50 0000 R CNN
+F 2 "" H 20800 15550 29 0000 C CNN
+F 3 "" H 20600 15650 60 0000 C CNN
+ 1 20500 15850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M34
+U 1 1 6855AD88
+P 20550 14750
+F 0 "M34" H 20500 14800 50 0000 R CNN
+F 1 "eSim_MOS_P" H 20600 14900 50 0000 R CNN
+F 2 "" H 20800 14850 29 0000 C CNN
+F 3 "" H 20600 14750 60 0000 C CNN
+ 1 20550 14750
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M37
+U 1 1 6855AD8E
+P 23450 15900
+F 0 "M37" H 23450 15750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 23550 15850 50 0000 R CNN
+F 2 "" H 23750 15600 29 0000 C CNN
+F 3 "" H 23550 15700 60 0000 C CNN
+ 1 23450 15900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M38
+U 1 1 6855AD94
+P 23500 14800
+F 0 "M38" H 23450 14850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 23550 14950 50 0000 R CNN
+F 2 "" H 23750 14900 29 0000 C CNN
+F 3 "" H 23550 14800 60 0000 C CNN
+ 1 23500 14800
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6855AD9A
+P 4750 14750
+F 0 "U1" H 4800 14850 30 0000 C CNN
+F 1 "PORT" H 4750 14750 30 0000 C CNN
+F 2 "" H 4750 14750 60 0000 C CNN
+F 3 "" H 4750 14750 60 0000 C CNN
+ 5 4750 14750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6855ADA0
+P 4800 16250
+F 0 "U1" H 4850 16350 30 0000 C CNN
+F 1 "PORT" H 4800 16250 30 0000 C CNN
+F 2 "" H 4800 16250 60 0000 C CNN
+F 3 "" H 4800 16250 60 0000 C CNN
+ 6 4800 16250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6855ADA6
+P 6300 19300
+F 0 "U1" H 6350 19400 30 0000 C CNN
+F 1 "PORT" H 6300 19300 30 0000 C CNN
+F 2 "" H 6300 19300 60 0000 C CNN
+F 3 "" H 6300 19300 60 0000 C CNN
+ 8 6300 19300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6855ADAC
+P 6450 20750
+F 0 "U1" H 6500 20850 30 0000 C CNN
+F 1 "PORT" H 6450 20750 30 0000 C CNN
+F 2 "" H 6450 20750 60 0000 C CNN
+F 3 "" H 6450 20750 60 0000 C CNN
+ 9 6450 20750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6855ADB2
+P 25450 15350
+F 0 "U1" H 25500 15450 30 0000 C CNN
+F 1 "PORT" H 25450 15350 30 0000 C CNN
+F 2 "" H 25450 15350 60 0000 C CNN
+F 3 "" H 25450 15350 60 0000 C CNN
+ 4 25450 15350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6855ADB8
+P 13750 22400
+F 0 "U1" H 13800 22500 30 0000 C CNN
+F 1 "PORT" H 13750 22400 30 0000 C CNN
+F 2 "" H 13750 22400 60 0000 C CNN
+F 3 "" H 13750 22400 60 0000 C CNN
+ 7 13750 22400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6855ADC4
+P 15100 12050
+F 0 "U1" H 15150 12150 30 0000 C CNN
+F 1 "PORT" H 15100 12050 30 0000 C CNN
+F 2 "" H 15100 12050 60 0000 C CNN
+F 3 "" H 15100 12050 60 0000 C CNN
+ 11 15100 12050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7700 13600 7700 12950
+Wire Wire Line
+ 7700 12950 9400 12950
+Wire Wire Line
+ 9300 12950 9300 13600
+Wire Wire Line
+ 9400 12950 9400 13650
+Connection ~ 9300 12950
+Wire Wire Line
+ 7800 13650 7800 12950
+Connection ~ 7800 12950
+Wire Wire Line
+ 7700 14000 7700 14450
+Wire Wire Line
+ 7700 14450 9350 14450
+Wire Wire Line
+ 9350 14050 9350 15050
+Wire Wire Line
+ 9300 14000 9300 14050
+Wire Wire Line
+ 9300 14050 9350 14050
+Connection ~ 9350 14450
+Wire Wire Line
+ 9350 15450 9350 16100
+Wire Wire Line
+ 9350 16500 9350 16850
+Wire Wire Line
+ 9450 16450 9450 16600
+Wire Wire Line
+ 9450 16600 9350 16600
+Connection ~ 9350 16600
+Wire Wire Line
+ 9450 15400 9450 15450
+Wire Wire Line
+ 9450 15450 9500 15450
+Wire Wire Line
+ 9500 15450 9500 16750
+Wire Wire Line
+ 9500 16750 9350 16750
+Connection ~ 9350 16750
+Wire Wire Line
+ 7400 13800 7100 13800
+Wire Wire Line
+ 7100 13800 7100 15250
+Wire Wire Line
+ 7100 15250 9050 15250
+Wire Wire Line
+ 9000 13800 8400 13800
+Wire Wire Line
+ 8400 13800 8400 16300
+Wire Wire Line
+ 6550 16300 9050 16300
+Wire Wire Line
+ 6550 16250 6550 16300
+Connection ~ 8400 16300
+Wire Wire Line
+ 7100 14650 6400 14650
+Wire Wire Line
+ 6400 14650 6400 14700
+Connection ~ 7100 14650
+Wire Wire Line
+ 7850 18150 7850 17500
+Wire Wire Line
+ 7850 17500 9550 17500
+Wire Wire Line
+ 9450 17500 9450 18150
+Wire Wire Line
+ 9550 17500 9550 18200
+Connection ~ 9450 17500
+Wire Wire Line
+ 7950 18200 7950 17500
+Connection ~ 7950 17500
+Wire Wire Line
+ 7850 18550 7850 19000
+Wire Wire Line
+ 7850 19000 9500 19000
+Wire Wire Line
+ 9500 18600 9500 19600
+Wire Wire Line
+ 9450 18550 9450 18600
+Wire Wire Line
+ 9450 18600 9500 18600
+Connection ~ 9500 19000
+Wire Wire Line
+ 9500 20000 9500 20650
+Wire Wire Line
+ 9500 21050 9500 21400
+Wire Wire Line
+ 9600 21000 9600 21150
+Wire Wire Line
+ 9600 21150 9500 21150
+Connection ~ 9500 21150
+Wire Wire Line
+ 9600 19950 9600 20000
+Wire Wire Line
+ 9600 20000 9650 20000
+Wire Wire Line
+ 9650 20000 9650 21300
+Wire Wire Line
+ 9650 21300 9500 21300
+Connection ~ 9500 21300
+Wire Wire Line
+ 7550 18350 7250 18350
+Wire Wire Line
+ 7250 18350 7250 19800
+Wire Wire Line
+ 7250 19800 9200 19800
+Wire Wire Line
+ 9150 18350 8550 18350
+Wire Wire Line
+ 8550 18350 8550 20850
+Wire Wire Line
+ 6700 20850 9200 20850
+Wire Wire Line
+ 6700 20750 6700 20850
+Connection ~ 8550 20850
+Wire Wire Line
+ 7250 19200 6550 19200
+Wire Wire Line
+ 6550 19200 6550 19300
+Connection ~ 7250 19200
+Wire Wire Line
+ 12350 14850 12350 14200
+Wire Wire Line
+ 12350 14200 14050 14200
+Wire Wire Line
+ 13950 14200 13950 14850
+Wire Wire Line
+ 14050 14200 14050 14900
+Connection ~ 13950 14200
+Wire Wire Line
+ 12450 14900 12450 14200
+Connection ~ 12450 14200
+Wire Wire Line
+ 12350 15250 12350 15700
+Wire Wire Line
+ 12350 15700 14000 15700
+Wire Wire Line
+ 14000 15300 14000 16300
+Wire Wire Line
+ 13950 15250 13950 15300
+Wire Wire Line
+ 13950 15300 14000 15300
+Connection ~ 14000 15700
+Wire Wire Line
+ 14000 16700 14000 17350
+Wire Wire Line
+ 14000 17750 14000 22400
+Wire Wire Line
+ 14100 17700 14100 17850
+Wire Wire Line
+ 14100 17850 14000 17850
+Connection ~ 14000 17850
+Wire Wire Line
+ 14100 16650 14100 16700
+Wire Wire Line
+ 14100 16700 14150 16700
+Wire Wire Line
+ 14150 16700 14150 18000
+Wire Wire Line
+ 14150 18000 14000 18000
+Connection ~ 14000 18000
+Wire Wire Line
+ 12050 15050 11750 15050
+Wire Wire Line
+ 11750 15050 11750 16500
+Wire Wire Line
+ 11750 16500 13700 16500
+Wire Wire Line
+ 13650 15050 13050 15050
+Wire Wire Line
+ 13050 15050 13050 17550
+Wire Wire Line
+ 11200 17550 13700 17550
+Wire Wire Line
+ 11200 17550 11200 17500
+Connection ~ 13050 17550
+Wire Wire Line
+ 11750 15900 11050 15900
+Wire Wire Line
+ 11050 15900 11050 15950
+Connection ~ 11750 15900
+Wire Wire Line
+ 9350 14250 10500 14250
+Wire Wire Line
+ 10500 14250 10500 15950
+Wire Wire Line
+ 10500 15950 11050 15950
+Connection ~ 9350 14250
+Wire Wire Line
+ 9500 18750 10650 18750
+Wire Wire Line
+ 10650 18750 10650 17500
+Wire Wire Line
+ 10650 17500 11200 17500
+Connection ~ 9500 18750
+Wire Wire Line
+ 17900 13450 17900 12800
+Wire Wire Line
+ 18000 13500 18000 12800
+Wire Wire Line
+ 18000 14650 18000 14250
+Wire Wire Line
+ 18000 14250 18300 14250
+Wire Wire Line
+ 18300 14250 18300 12800
+Wire Wire Line
+ 17900 13850 17900 14600
+Wire Wire Line
+ 17900 15000 17900 15600
+Wire Wire Line
+ 16300 15650 16300 15200
+Wire Wire Line
+ 16300 15200 17900 15200
+Connection ~ 17900 15200
+Wire Wire Line
+ 14000 15400 15300 15400
+Wire Wire Line
+ 15300 15400 15300 14450
+Wire Wire Line
+ 15300 14450 17200 14450
+Wire Wire Line
+ 17200 14450 17200 15800
+Wire Wire Line
+ 17200 14800 17600 14800
+Connection ~ 14000 15400
+Wire Wire Line
+ 17200 15800 17600 15800
+Connection ~ 17200 14800
+Wire Wire Line
+ 15350 13650 17600 13650
+Wire Wire Line
+ 15350 12050 15350 13650
+Wire Wire Line
+ 15500 13650 15500 15850
+Wire Wire Line
+ 15500 15850 16000 15850
+Connection ~ 15500 13650
+Wire Wire Line
+ 16300 16050 16300 18100
+Wire Wire Line
+ 14000 18100 20800 18100
+Wire Wire Line
+ 17900 18100 17900 16000
+Connection ~ 16300 18100
+Wire Wire Line
+ 18000 18100 18000 15950
+Connection ~ 17900 18100
+Wire Wire Line
+ 16400 16000 16400 18100
+Connection ~ 16400 18100
+Wire Wire Line
+ 17900 12800 23750 12800
+Connection ~ 18000 12800
+Wire Wire Line
+ 17900 15350 19950 15350
+Connection ~ 17900 15350
+Wire Wire Line
+ 20400 14750 19950 14750
+Wire Wire Line
+ 19950 14750 19950 16050
+Wire Wire Line
+ 19950 16050 20400 16050
+Connection ~ 19950 15350
+Wire Wire Line
+ 20700 14950 20700 15850
+Wire Wire Line
+ 20700 12800 20700 14550
+Connection ~ 18300 12800
+Wire Wire Line
+ 20800 12800 20800 14600
+Connection ~ 20700 12800
+Wire Wire Line
+ 20700 18100 20700 16250
+Connection ~ 18000 18100
+Wire Wire Line
+ 20800 16200 20800 18150
+Connection ~ 20700 18100
+Wire Wire Line
+ 20700 15400 22900 15400
+Wire Wire Line
+ 23350 14800 22900 14800
+Wire Wire Line
+ 22900 14800 22900 16100
+Wire Wire Line
+ 22900 16100 23350 16100
+Connection ~ 22900 15400
+Wire Wire Line
+ 23650 15000 23650 15900
+Wire Wire Line
+ 23650 12800 23650 14600
+Wire Wire Line
+ 23750 12800 23750 14650
+Wire Wire Line
+ 23650 18150 23650 16300
+Wire Wire Line
+ 23750 18150 23750 16250
+Connection ~ 20700 15400
+Wire Wire Line
+ 20800 18150 23750 18150
+Connection ~ 20800 18100
+Connection ~ 23650 18150
+Connection ~ 20800 12800
+Connection ~ 23650 12800
+Wire Wire Line
+ 23650 15400 24850 15400
+Wire Wire Line
+ 24850 15400 24850 15350
+Connection ~ 23650 15400
+Wire Wire Line
+ 13150 12350 13150 14200
+Wire Wire Line
+ 4150 12350 20950 12350
+Wire Wire Line
+ 20950 12350 20950 12800
+Connection ~ 20950 12800
+Connection ~ 13150 14200
+Connection ~ 8300 12950
+Wire Wire Line
+ 5850 12350 5850 17050
+Wire Wire Line
+ 5850 17050 8650 17050
+Wire Wire Line
+ 8650 17050 8650 17500
+Connection ~ 8650 17500
+Wire Wire Line
+ 9350 16850 10100 16850
+Wire Wire Line
+ 10100 16850 10100 21400
+Wire Wire Line
+ 9500 21400 26800 21400
+Connection ~ 14000 18100
+Connection ~ 10100 21400
+Connection ~ 14000 21400
+Wire Wire Line
+ 5050 16250 6550 16250
+Wire Wire Line
+ 6400 14700 5000 14700
+Wire Wire Line
+ 5000 14700 5000 14750
+Wire Wire Line
+ 24850 15350 25200 15350
+Wire Wire Line
+ 8300 12350 8300 12950
+Connection ~ 13150 12350
+Connection ~ 8300 12350
+Wire Wire Line
+ 26800 21400 26800 10650
+Connection ~ 14900 10650
+Wire Wire Line
+ 4150 1600 4150 12350
+Connection ~ 5850 12350
+Connection ~ 6750 1600
+Text Label 14600 1300 0 60 ~ 0
+VDD
+Text Label 14000 21950 0 60 ~ 0
+VSS
+Text Label 6050 3950 0 60 ~ 0
+A1
+Text Label 5300 14700 0 60 ~ 0
+A2
+Text Label 6150 5500 0 60 ~ 0
+B1
+Text Label 5200 16250 0 60 ~ 0
+B2
+Text Label 7650 8450 0 60 ~ 0
+C1
+Text Label 6700 19200 0 60 ~ 0
+C2
+Text Label 7850 10100 0 60 ~ 0
+D1
+Text Label 6850 20850 0 60 ~ 0
+D2
+Text Label 16250 1450 0 60 ~ 0
+INHIBIT1
+Text Label 15350 12200 0 60 ~ 0
+INHIBIT2
+Text Label 25750 4600 0 60 ~ 0
+E1
+Text Label 24850 15350 0 60 ~ 0
+E2
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.cir b/library/SubcircuitLibrary/CD4085B/CD4085B.cir
new file mode 100644
index 000000000..6b68ca025
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/CD4085B.cir
@@ -0,0 +1,51 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4085B\CD4085B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/20/25 21:32:25
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M3 Net-_M11-Pad1_ /A1 /VDD /VDD eSim_MOS_P
+M11 Net-_M11-Pad1_ /B1 /VDD /VDD eSim_MOS_P
+M12 Net-_M11-Pad1_ /A1 Net-_M12-Pad3_ /VSS eSim_MOS_N
+M13 Net-_M12-Pad3_ /B1 /VSS /VSS eSim_MOS_N
+M4 Net-_M14-Pad1_ /C1 /VDD /VDD eSim_MOS_P
+M14 Net-_M14-Pad1_ /D1 /VDD /VDD eSim_MOS_P
+M15 Net-_M14-Pad1_ /C1 Net-_M15-Pad3_ /VSS eSim_MOS_N
+M16 Net-_M15-Pad3_ /D1 /VSS /VSS eSim_MOS_N
+M18 Net-_M18-Pad1_ Net-_M11-Pad1_ /VDD /VDD eSim_MOS_P
+M22 Net-_M18-Pad1_ Net-_M14-Pad1_ /VDD /VDD eSim_MOS_P
+M23 Net-_M18-Pad1_ Net-_M11-Pad1_ Net-_M23-Pad3_ /VSS eSim_MOS_N
+M24 Net-_M23-Pad3_ Net-_M14-Pad1_ /VSS /VSS eSim_MOS_N
+M31 Net-_M31-Pad1_ /INHIBIT1 /VDD /VDD eSim_MOS_P
+M32 Net-_M26-Pad1_ Net-_M18-Pad1_ Net-_M31-Pad1_ /VDD eSim_MOS_P
+M30 Net-_M26-Pad1_ Net-_M18-Pad1_ /VSS /VSS eSim_MOS_N
+M26 Net-_M26-Pad1_ /INHIBIT1 /VSS /VSS eSim_MOS_N
+M35 Net-_M35-Pad1_ Net-_M26-Pad1_ /VSS /VSS eSim_MOS_N
+M36 Net-_M35-Pad1_ Net-_M26-Pad1_ /VDD /VDD eSim_MOS_P
+M39 /E1 Net-_M35-Pad1_ /VSS /VSS eSim_MOS_N
+M40 /E1 Net-_M35-Pad1_ /VDD /VDD eSim_MOS_P
+U1 /A1 /B1 /E1 /E2 /A2 /B2 /VSS /C2 /D2 /INHIBIT1 /INHIBIT2 /C1 /D1 /VDD PORT
+M1 Net-_M1-Pad1_ /A2 /VDD /VDD eSim_MOS_P
+M5 Net-_M1-Pad1_ /B2 /VDD /VDD eSim_MOS_P
+M6 Net-_M1-Pad1_ /A2 Net-_M6-Pad3_ /VSS eSim_MOS_N
+M7 Net-_M6-Pad3_ /B2 /VSS /VSS eSim_MOS_N
+M2 Net-_M19-Pad2_ /C2 /VDD /VDD eSim_MOS_P
+M8 Net-_M19-Pad2_ /D2 /VDD /VDD eSim_MOS_P
+M9 Net-_M19-Pad2_ /C2 Net-_M10-Pad1_ /VSS eSim_MOS_N
+M10 Net-_M10-Pad1_ /D2 /VSS /VSS eSim_MOS_N
+M17 Net-_M17-Pad1_ Net-_M1-Pad1_ /VDD /VDD eSim_MOS_P
+M19 Net-_M17-Pad1_ Net-_M19-Pad2_ /VDD /VDD eSim_MOS_P
+M20 Net-_M17-Pad1_ Net-_M1-Pad1_ Net-_M20-Pad3_ /VSS eSim_MOS_N
+M21 Net-_M20-Pad3_ Net-_M19-Pad2_ /VSS /VSS eSim_MOS_N
+M28 Net-_M28-Pad1_ /INHIBIT2 /VDD /VDD eSim_MOS_P
+M29 Net-_M25-Pad1_ Net-_M17-Pad1_ Net-_M28-Pad1_ /VDD eSim_MOS_P
+M27 Net-_M25-Pad1_ Net-_M17-Pad1_ /VSS /VSS eSim_MOS_N
+M25 Net-_M25-Pad1_ /INHIBIT2 /VSS /VSS eSim_MOS_N
+M33 Net-_M33-Pad1_ Net-_M25-Pad1_ /VSS /VSS eSim_MOS_N
+M34 Net-_M33-Pad1_ Net-_M25-Pad1_ /VDD /VDD eSim_MOS_P
+M37 /E2 Net-_M33-Pad1_ /VSS /VSS eSim_MOS_N
+M38 /E2 Net-_M33-Pad1_ /VDD /VDD eSim_MOS_P
+
+.end
diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.cir.out b/library/SubcircuitLibrary/CD4085B/CD4085B.cir.out
new file mode 100644
index 000000000..50e2e9e0a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/CD4085B.cir.out
@@ -0,0 +1,54 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4085b\cd4085b.cir
+
+.include NMOS-5um.lib
+.include PMOS-5um.lib
+m3 net-_m11-pad1_ /a1 /vdd /vdd mos_p W=100u L=100u M=1
+m11 net-_m11-pad1_ /b1 /vdd /vdd mos_p W=100u L=100u M=1
+m12 net-_m11-pad1_ /a1 net-_m12-pad3_ /vss mos_n W=100u L=100u M=1
+m13 net-_m12-pad3_ /b1 /vss /vss mos_n W=100u L=100u M=1
+m4 net-_m14-pad1_ /c1 /vdd /vdd mos_p W=100u L=100u M=1
+m14 net-_m14-pad1_ /d1 /vdd /vdd mos_p W=100u L=100u M=1
+m15 net-_m14-pad1_ /c1 net-_m15-pad3_ /vss mos_n W=100u L=100u M=1
+m16 net-_m15-pad3_ /d1 /vss /vss mos_n W=100u L=100u M=1
+m18 net-_m18-pad1_ net-_m11-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m22 net-_m18-pad1_ net-_m14-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m23 net-_m18-pad1_ net-_m11-pad1_ net-_m23-pad3_ /vss mos_n W=100u L=100u M=1
+m24 net-_m23-pad3_ net-_m14-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m31 net-_m31-pad1_ /inhibit1 /vdd /vdd mos_p W=100u L=100u M=1
+m32 net-_m26-pad1_ net-_m18-pad1_ net-_m31-pad1_ /vdd mos_p W=100u L=100u M=1
+m30 net-_m26-pad1_ net-_m18-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m26 net-_m26-pad1_ /inhibit1 /vss /vss mos_n W=100u L=100u M=1
+m35 net-_m35-pad1_ net-_m26-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m36 net-_m35-pad1_ net-_m26-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m39 /e1 net-_m35-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m40 /e1 net-_m35-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+* u1 /a1 /b1 /e1 /e2 /a2 /b2 /vss /c2 /d2 /inhibit1 /inhibit2 /c1 /d1 /vdd port
+m1 net-_m1-pad1_ /a2 /vdd /vdd mos_p W=100u L=100u M=1
+m5 net-_m1-pad1_ /b2 /vdd /vdd mos_p W=100u L=100u M=1
+m6 net-_m1-pad1_ /a2 net-_m6-pad3_ /vss mos_n W=100u L=100u M=1
+m7 net-_m6-pad3_ /b2 /vss /vss mos_n W=100u L=100u M=1
+m2 net-_m19-pad2_ /c2 /vdd /vdd mos_p W=100u L=100u M=1
+m8 net-_m19-pad2_ /d2 /vdd /vdd mos_p W=100u L=100u M=1
+m9 net-_m19-pad2_ /c2 net-_m10-pad1_ /vss mos_n W=100u L=100u M=1
+m10 net-_m10-pad1_ /d2 /vss /vss mos_n W=100u L=100u M=1
+m17 net-_m17-pad1_ net-_m1-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m19 net-_m17-pad1_ net-_m19-pad2_ /vdd /vdd mos_p W=100u L=100u M=1
+m20 net-_m17-pad1_ net-_m1-pad1_ net-_m20-pad3_ /vss mos_n W=100u L=100u M=1
+m21 net-_m20-pad3_ net-_m19-pad2_ /vss /vss mos_n W=100u L=100u M=1
+m28 net-_m28-pad1_ /inhibit2 /vdd /vdd mos_p W=100u L=100u M=1
+m29 net-_m25-pad1_ net-_m17-pad1_ net-_m28-pad1_ /vdd mos_p W=100u L=100u M=1
+m27 net-_m25-pad1_ net-_m17-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m25 net-_m25-pad1_ /inhibit2 /vss /vss mos_n W=100u L=100u M=1
+m33 net-_m33-pad1_ net-_m25-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m34 net-_m33-pad1_ net-_m25-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m37 /e2 net-_m33-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m38 /e2 net-_m33-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.pro b/library/SubcircuitLibrary/CD4085B/CD4085B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/CD4085B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.sch b/library/SubcircuitLibrary/CD4085B/CD4085B.sch
new file mode 100644
index 000000000..8bb704423
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/CD4085B.sch
@@ -0,0 +1,1384 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4085B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M3
+U 1 1 685581CA
+P 8450 3050
+F 0 "M3" H 8400 3100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 8500 3200 50 0000 R CNN
+F 2 "" H 8700 3150 29 0000 C CNN
+F 3 "" H 8500 3050 60 0000 C CNN
+ 1 8450 3050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M11
+U 1 1 685581CB
+P 10050 3050
+F 0 "M11" H 10000 3100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10100 3200 50 0000 R CNN
+F 2 "" H 10300 3150 29 0000 C CNN
+F 3 "" H 10100 3050 60 0000 C CNN
+ 1 10050 3050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M12
+U 1 1 685581CC
+P 10050 4300
+F 0 "M12" H 10050 4150 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10150 4250 50 0000 R CNN
+F 2 "" H 10350 4000 29 0000 C CNN
+F 3 "" H 10150 4100 60 0000 C CNN
+ 1 10050 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M13
+U 1 1 685581CD
+P 10050 5350
+F 0 "M13" H 10050 5200 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10150 5300 50 0000 R CNN
+F 2 "" H 10350 5050 29 0000 C CNN
+F 3 "" H 10150 5150 60 0000 C CNN
+ 1 10050 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 685581CE
+P 8600 7600
+F 0 "M4" H 8550 7650 50 0000 R CNN
+F 1 "eSim_MOS_P" H 8650 7750 50 0000 R CNN
+F 2 "" H 8850 7700 29 0000 C CNN
+F 3 "" H 8650 7600 60 0000 C CNN
+ 1 8600 7600
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M14
+U 1 1 685581CF
+P 10200 7600
+F 0 "M14" H 10150 7650 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10250 7750 50 0000 R CNN
+F 2 "" H 10450 7700 29 0000 C CNN
+F 3 "" H 10250 7600 60 0000 C CNN
+ 1 10200 7600
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M15
+U 1 1 685581D0
+P 10200 8850
+F 0 "M15" H 10200 8700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10300 8800 50 0000 R CNN
+F 2 "" H 10500 8550 29 0000 C CNN
+F 3 "" H 10300 8650 60 0000 C CNN
+ 1 10200 8850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M16
+U 1 1 685581D1
+P 10200 9900
+F 0 "M16" H 10200 9750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10300 9850 50 0000 R CNN
+F 2 "" H 10500 9600 29 0000 C CNN
+F 3 "" H 10300 9700 60 0000 C CNN
+ 1 10200 9900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M18
+U 1 1 685581D2
+P 13100 4300
+F 0 "M18" H 13050 4350 50 0000 R CNN
+F 1 "eSim_MOS_P" H 13150 4450 50 0000 R CNN
+F 2 "" H 13350 4400 29 0000 C CNN
+F 3 "" H 13150 4300 60 0000 C CNN
+ 1 13100 4300
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M22
+U 1 1 685581D3
+P 14700 4300
+F 0 "M22" H 14650 4350 50 0000 R CNN
+F 1 "eSim_MOS_P" H 14750 4450 50 0000 R CNN
+F 2 "" H 14950 4400 29 0000 C CNN
+F 3 "" H 14750 4300 60 0000 C CNN
+ 1 14700 4300
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M23
+U 1 1 685581D4
+P 14700 5550
+F 0 "M23" H 14700 5400 50 0000 R CNN
+F 1 "eSim_MOS_N" H 14800 5500 50 0000 R CNN
+F 2 "" H 15000 5250 29 0000 C CNN
+F 3 "" H 14800 5350 60 0000 C CNN
+ 1 14700 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M24
+U 1 1 685581D5
+P 14700 6600
+F 0 "M24" H 14700 6450 50 0000 R CNN
+F 1 "eSim_MOS_N" H 14800 6550 50 0000 R CNN
+F 2 "" H 15000 6300 29 0000 C CNN
+F 3 "" H 14800 6400 60 0000 C CNN
+ 1 14700 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M31
+U 1 1 685581D6
+P 18650 2900
+F 0 "M31" H 18600 2950 50 0000 R CNN
+F 1 "eSim_MOS_P" H 18700 3050 50 0000 R CNN
+F 2 "" H 18900 3000 29 0000 C CNN
+F 3 "" H 18700 2900 60 0000 C CNN
+ 1 18650 2900
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M32
+U 1 1 685581D7
+P 18650 4050
+F 0 "M32" H 18600 4100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 18700 4200 50 0000 R CNN
+F 2 "" H 18900 4150 29 0000 C CNN
+F 3 "" H 18700 4050 60 0000 C CNN
+ 1 18650 4050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M30
+U 1 1 685581D8
+P 18600 4850
+F 0 "M30" H 18600 4700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 18700 4800 50 0000 R CNN
+F 2 "" H 18900 4550 29 0000 C CNN
+F 3 "" H 18700 4650 60 0000 C CNN
+ 1 18600 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M26
+U 1 1 685581D9
+P 17000 4900
+F 0 "M26" H 17000 4750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 17100 4850 50 0000 R CNN
+F 2 "" H 17300 4600 29 0000 C CNN
+F 3 "" H 17100 4700 60 0000 C CNN
+ 1 17000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M35
+U 1 1 685581DA
+P 21400 5100
+F 0 "M35" H 21400 4950 50 0000 R CNN
+F 1 "eSim_MOS_N" H 21500 5050 50 0000 R CNN
+F 2 "" H 21700 4800 29 0000 C CNN
+F 3 "" H 21500 4900 60 0000 C CNN
+ 1 21400 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M36
+U 1 1 685581DB
+P 21450 4000
+F 0 "M36" H 21400 4050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 21500 4150 50 0000 R CNN
+F 2 "" H 21700 4100 29 0000 C CNN
+F 3 "" H 21500 4000 60 0000 C CNN
+ 1 21450 4000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M39
+U 1 1 685581DC
+P 24350 5150
+F 0 "M39" H 24350 5000 50 0000 R CNN
+F 1 "eSim_MOS_N" H 24450 5100 50 0000 R CNN
+F 2 "" H 24650 4850 29 0000 C CNN
+F 3 "" H 24450 4950 60 0000 C CNN
+ 1 24350 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M40
+U 1 1 685581DD
+P 24400 4050
+F 0 "M40" H 24350 4100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 24450 4200 50 0000 R CNN
+F 2 "" H 24650 4150 29 0000 C CNN
+F 3 "" H 24450 4050 60 0000 C CNN
+ 1 24400 4050
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685581DE
+P 5650 4000
+F 0 "U1" H 5700 4100 30 0000 C CNN
+F 1 "PORT" H 5650 4000 30 0000 C CNN
+F 2 "" H 5650 4000 60 0000 C CNN
+F 3 "" H 5650 4000 60 0000 C CNN
+ 1 5650 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685581DF
+P 5700 5500
+F 0 "U1" H 5750 5600 30 0000 C CNN
+F 1 "PORT" H 5700 5500 30 0000 C CNN
+F 2 "" H 5700 5500 60 0000 C CNN
+F 3 "" H 5700 5500 60 0000 C CNN
+ 2 5700 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685581E0
+P 7200 8550
+F 0 "U1" H 7250 8650 30 0000 C CNN
+F 1 "PORT" H 7200 8550 30 0000 C CNN
+F 2 "" H 7200 8550 60 0000 C CNN
+F 3 "" H 7200 8550 60 0000 C CNN
+ 12 7200 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685581E1
+P 7350 10000
+F 0 "U1" H 7400 10100 30 0000 C CNN
+F 1 "PORT" H 7350 10000 30 0000 C CNN
+F 2 "" H 7350 10000 60 0000 C CNN
+F 3 "" H 7350 10000 60 0000 C CNN
+ 13 7350 10000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685581E2
+P 26350 4600
+F 0 "U1" H 26400 4700 30 0000 C CNN
+F 1 "PORT" H 26350 4600 30 0000 C CNN
+F 2 "" H 26350 4600 60 0000 C CNN
+F 3 "" H 26350 4600 60 0000 C CNN
+ 3 26350 4600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685581E4
+P 14950 950
+F 0 "U1" H 15000 1050 30 0000 C CNN
+F 1 "PORT" H 14950 950 30 0000 C CNN
+F 2 "" H 14950 950 60 0000 C CNN
+F 3 "" H 14950 950 60 0000 C CNN
+ 14 14950 950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685581E5
+P 16000 1300
+F 0 "U1" H 16050 1400 30 0000 C CNN
+F 1 "PORT" H 16000 1300 30 0000 C CNN
+F 2 "" H 16000 1300 60 0000 C CNN
+F 3 "" H 16000 1300 60 0000 C CNN
+ 10 16000 1300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8600 2850 8600 2200
+Wire Wire Line
+ 8600 2200 10300 2200
+Wire Wire Line
+ 10200 2200 10200 2850
+Wire Wire Line
+ 10300 2200 10300 2900
+Connection ~ 10200 2200
+Wire Wire Line
+ 8700 2900 8700 2200
+Connection ~ 8700 2200
+Wire Wire Line
+ 8600 3250 8600 3700
+Wire Wire Line
+ 8600 3700 10250 3700
+Wire Wire Line
+ 10250 3300 10250 4300
+Wire Wire Line
+ 10200 3250 10200 3300
+Wire Wire Line
+ 10200 3300 10250 3300
+Connection ~ 10250 3700
+Wire Wire Line
+ 10250 4700 10250 5350
+Wire Wire Line
+ 10250 5750 10250 6100
+Wire Wire Line
+ 10350 5700 10350 5850
+Wire Wire Line
+ 10350 5850 10250 5850
+Connection ~ 10250 5850
+Wire Wire Line
+ 10350 4650 10350 4700
+Wire Wire Line
+ 10350 4700 10400 4700
+Wire Wire Line
+ 10400 4700 10400 6000
+Wire Wire Line
+ 10400 6000 10250 6000
+Connection ~ 10250 6000
+Wire Wire Line
+ 8300 3050 8000 3050
+Wire Wire Line
+ 8000 3050 8000 4500
+Wire Wire Line
+ 8000 4500 9950 4500
+Wire Wire Line
+ 9900 3050 9300 3050
+Wire Wire Line
+ 9300 3050 9300 5550
+Wire Wire Line
+ 7450 5550 9950 5550
+Wire Wire Line
+ 7450 5500 7450 5550
+Connection ~ 9300 5550
+Wire Wire Line
+ 8000 3900 7300 3900
+Wire Wire Line
+ 7300 3900 7300 3950
+Connection ~ 8000 3900
+Wire Wire Line
+ 8750 7400 8750 6750
+Wire Wire Line
+ 8750 6750 10450 6750
+Wire Wire Line
+ 10350 6750 10350 7400
+Wire Wire Line
+ 10450 6750 10450 7450
+Connection ~ 10350 6750
+Wire Wire Line
+ 8850 7450 8850 6750
+Connection ~ 8850 6750
+Wire Wire Line
+ 8750 7800 8750 8250
+Wire Wire Line
+ 8750 8250 10400 8250
+Wire Wire Line
+ 10400 7850 10400 8850
+Wire Wire Line
+ 10350 7800 10350 7850
+Wire Wire Line
+ 10350 7850 10400 7850
+Connection ~ 10400 8250
+Wire Wire Line
+ 10400 9250 10400 9900
+Wire Wire Line
+ 10400 10300 10400 10650
+Wire Wire Line
+ 10500 10250 10500 10400
+Wire Wire Line
+ 10500 10400 10400 10400
+Connection ~ 10400 10400
+Wire Wire Line
+ 10500 9200 10500 9250
+Wire Wire Line
+ 10500 9250 10550 9250
+Wire Wire Line
+ 10550 9250 10550 10550
+Wire Wire Line
+ 10550 10550 10400 10550
+Connection ~ 10400 10550
+Wire Wire Line
+ 8450 7600 8150 7600
+Wire Wire Line
+ 8150 7600 8150 9050
+Wire Wire Line
+ 8150 9050 10100 9050
+Wire Wire Line
+ 10050 7600 9450 7600
+Wire Wire Line
+ 9450 7600 9450 10100
+Wire Wire Line
+ 7600 10100 10100 10100
+Wire Wire Line
+ 7600 10000 7600 10100
+Connection ~ 9450 10100
+Wire Wire Line
+ 8150 8450 7450 8450
+Wire Wire Line
+ 7450 8450 7450 8550
+Connection ~ 8150 8450
+Wire Wire Line
+ 13250 4100 13250 3450
+Wire Wire Line
+ 13250 3450 14950 3450
+Wire Wire Line
+ 14850 3450 14850 4100
+Wire Wire Line
+ 14950 3450 14950 4150
+Connection ~ 14850 3450
+Wire Wire Line
+ 13350 4150 13350 3450
+Connection ~ 13350 3450
+Wire Wire Line
+ 13250 4500 13250 4950
+Wire Wire Line
+ 13250 4950 14900 4950
+Wire Wire Line
+ 14900 4550 14900 5550
+Wire Wire Line
+ 14850 4500 14850 4550
+Wire Wire Line
+ 14850 4550 14900 4550
+Connection ~ 14900 4950
+Wire Wire Line
+ 14900 5950 14900 6600
+Wire Wire Line
+ 14900 10650 14900 7000
+Wire Wire Line
+ 15000 6950 15000 7100
+Wire Wire Line
+ 15000 7100 14900 7100
+Connection ~ 14900 7100
+Wire Wire Line
+ 15000 5900 15000 5950
+Wire Wire Line
+ 15000 5950 15050 5950
+Wire Wire Line
+ 15050 5950 15050 7250
+Wire Wire Line
+ 15050 7250 14900 7250
+Connection ~ 14900 7250
+Wire Wire Line
+ 12950 4300 12650 4300
+Wire Wire Line
+ 12650 4300 12650 5750
+Wire Wire Line
+ 12650 5750 14600 5750
+Wire Wire Line
+ 14550 4300 13950 4300
+Wire Wire Line
+ 13950 4300 13950 6800
+Wire Wire Line
+ 12100 6800 14600 6800
+Wire Wire Line
+ 12100 6800 12100 6750
+Connection ~ 13950 6800
+Wire Wire Line
+ 12650 5150 11950 5150
+Wire Wire Line
+ 11950 5150 11950 5200
+Connection ~ 12650 5150
+Wire Wire Line
+ 10250 3500 11400 3500
+Wire Wire Line
+ 11400 3500 11400 5200
+Wire Wire Line
+ 11400 5200 11950 5200
+Connection ~ 10250 3500
+Wire Wire Line
+ 10400 8000 11550 8000
+Wire Wire Line
+ 11550 8000 11550 6750
+Wire Wire Line
+ 11550 6750 12100 6750
+Connection ~ 10400 8000
+Wire Wire Line
+ 18800 2700 18800 2050
+Wire Wire Line
+ 18900 2750 18900 2050
+Wire Wire Line
+ 18900 3900 18900 3500
+Wire Wire Line
+ 18900 3500 19200 3500
+Wire Wire Line
+ 19200 3500 19200 2050
+Wire Wire Line
+ 18800 3100 18800 3850
+Wire Wire Line
+ 18800 4250 18800 4850
+Wire Wire Line
+ 17200 4900 17200 4450
+Wire Wire Line
+ 17200 4450 18800 4450
+Connection ~ 18800 4450
+Wire Wire Line
+ 14900 4650 16200 4650
+Wire Wire Line
+ 16200 4650 16200 3700
+Wire Wire Line
+ 16200 3700 18100 3700
+Wire Wire Line
+ 18100 3700 18100 5050
+Wire Wire Line
+ 18100 4050 18500 4050
+Connection ~ 14900 4650
+Wire Wire Line
+ 18100 5050 18500 5050
+Connection ~ 18100 4050
+Wire Wire Line
+ 16250 2900 18500 2900
+Wire Wire Line
+ 16250 1300 16250 2900
+Wire Wire Line
+ 16400 2900 16400 5100
+Wire Wire Line
+ 16400 5100 16900 5100
+Connection ~ 16400 2900
+Wire Wire Line
+ 17200 5300 17200 7350
+Wire Wire Line
+ 14900 7350 21700 7350
+Wire Wire Line
+ 18800 7350 18800 5250
+Connection ~ 17200 7350
+Wire Wire Line
+ 18900 7350 18900 5200
+Connection ~ 18800 7350
+Wire Wire Line
+ 17300 5250 17300 7350
+Connection ~ 17300 7350
+Wire Wire Line
+ 18800 2050 24650 2050
+Connection ~ 18900 2050
+Wire Wire Line
+ 18800 4600 20850 4600
+Connection ~ 18800 4600
+Wire Wire Line
+ 21300 4000 20850 4000
+Wire Wire Line
+ 20850 4000 20850 5300
+Wire Wire Line
+ 20850 5300 21300 5300
+Connection ~ 20850 4600
+Wire Wire Line
+ 21600 4200 21600 5100
+Wire Wire Line
+ 21600 2050 21600 3800
+Connection ~ 19200 2050
+Wire Wire Line
+ 21700 2050 21700 3850
+Connection ~ 21600 2050
+Wire Wire Line
+ 21600 7350 21600 5500
+Connection ~ 18900 7350
+Wire Wire Line
+ 21700 5450 21700 7400
+Connection ~ 21600 7350
+Wire Wire Line
+ 21600 4650 23800 4650
+Wire Wire Line
+ 24250 4050 23800 4050
+Wire Wire Line
+ 23800 4050 23800 5350
+Wire Wire Line
+ 23800 5350 24250 5350
+Connection ~ 23800 4650
+Wire Wire Line
+ 24550 4250 24550 5150
+Wire Wire Line
+ 24550 2050 24550 3850
+Wire Wire Line
+ 24650 2050 24650 3900
+Wire Wire Line
+ 24550 7400 24550 5550
+Wire Wire Line
+ 24650 7400 24650 5500
+Connection ~ 21600 4650
+Wire Wire Line
+ 21700 7400 24650 7400
+Connection ~ 21700 7350
+Connection ~ 24550 7400
+Connection ~ 21700 2050
+Connection ~ 24550 2050
+Wire Wire Line
+ 24550 4650 25750 4650
+Wire Wire Line
+ 25750 4650 25750 4600
+Connection ~ 24550 4650
+Wire Wire Line
+ 14050 1600 14050 3450
+Wire Wire Line
+ 4150 1600 21850 1600
+Wire Wire Line
+ 21850 1600 21850 2050
+Connection ~ 21850 2050
+Connection ~ 14050 3450
+Connection ~ 9200 2200
+Wire Wire Line
+ 6750 1600 6750 6300
+Wire Wire Line
+ 6750 6300 9550 6300
+Wire Wire Line
+ 9550 6300 9550 6750
+Connection ~ 9550 6750
+Wire Wire Line
+ 10250 6100 11000 6100
+Wire Wire Line
+ 11000 6100 11000 10650
+Wire Wire Line
+ 10400 10650 26800 10650
+Connection ~ 14900 7350
+Connection ~ 11000 10650
+Wire Wire Line
+ 14600 950 14600 1600
+Wire Wire Line
+ 14600 950 14700 950
+Wire Wire Line
+ 5950 5500 7450 5500
+Wire Wire Line
+ 7300 3950 5900 3950
+Wire Wire Line
+ 5900 3950 5900 4000
+Wire Wire Line
+ 25750 4600 26100 4600
+Wire Wire Line
+ 9200 1600 9200 2200
+Connection ~ 14050 1600
+Connection ~ 9200 1600
+Connection ~ 14600 1600
+$Comp
+L eSim_MOS_P M1
+U 1 1 6855AD22
+P 7550 13800
+F 0 "M1" H 7500 13850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 7600 13950 50 0000 R CNN
+F 2 "" H 7800 13900 29 0000 C CNN
+F 3 "" H 7600 13800 60 0000 C CNN
+ 1 7550 13800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M5
+U 1 1 6855AD28
+P 9150 13800
+F 0 "M5" H 9100 13850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 9200 13950 50 0000 R CNN
+F 2 "" H 9400 13900 29 0000 C CNN
+F 3 "" H 9200 13800 60 0000 C CNN
+ 1 9150 13800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M6
+U 1 1 6855AD2E
+P 9150 15050
+F 0 "M6" H 9150 14900 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9250 15000 50 0000 R CNN
+F 2 "" H 9450 14750 29 0000 C CNN
+F 3 "" H 9250 14850 60 0000 C CNN
+ 1 9150 15050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M7
+U 1 1 6855AD34
+P 9150 16100
+F 0 "M7" H 9150 15950 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9250 16050 50 0000 R CNN
+F 2 "" H 9450 15800 29 0000 C CNN
+F 3 "" H 9250 15900 60 0000 C CNN
+ 1 9150 16100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M2
+U 1 1 6855AD3A
+P 7700 18350
+F 0 "M2" H 7650 18400 50 0000 R CNN
+F 1 "eSim_MOS_P" H 7750 18500 50 0000 R CNN
+F 2 "" H 7950 18450 29 0000 C CNN
+F 3 "" H 7750 18350 60 0000 C CNN
+ 1 7700 18350
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M8
+U 1 1 6855AD40
+P 9300 18350
+F 0 "M8" H 9250 18400 50 0000 R CNN
+F 1 "eSim_MOS_P" H 9350 18500 50 0000 R CNN
+F 2 "" H 9550 18450 29 0000 C CNN
+F 3 "" H 9350 18350 60 0000 C CNN
+ 1 9300 18350
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M9
+U 1 1 6855AD46
+P 9300 19600
+F 0 "M9" H 9300 19450 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9400 19550 50 0000 R CNN
+F 2 "" H 9600 19300 29 0000 C CNN
+F 3 "" H 9400 19400 60 0000 C CNN
+ 1 9300 19600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 6855AD4C
+P 9300 20650
+F 0 "M10" H 9300 20500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9400 20600 50 0000 R CNN
+F 2 "" H 9600 20350 29 0000 C CNN
+F 3 "" H 9400 20450 60 0000 C CNN
+ 1 9300 20650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M17
+U 1 1 6855AD52
+P 12200 15050
+F 0 "M17" H 12150 15100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 12250 15200 50 0000 R CNN
+F 2 "" H 12450 15150 29 0000 C CNN
+F 3 "" H 12250 15050 60 0000 C CNN
+ 1 12200 15050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M19
+U 1 1 6855AD58
+P 13800 15050
+F 0 "M19" H 13750 15100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 13850 15200 50 0000 R CNN
+F 2 "" H 14050 15150 29 0000 C CNN
+F 3 "" H 13850 15050 60 0000 C CNN
+ 1 13800 15050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M20
+U 1 1 6855AD5E
+P 13800 16300
+F 0 "M20" H 13800 16150 50 0000 R CNN
+F 1 "eSim_MOS_N" H 13900 16250 50 0000 R CNN
+F 2 "" H 14100 16000 29 0000 C CNN
+F 3 "" H 13900 16100 60 0000 C CNN
+ 1 13800 16300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M21
+U 1 1 6855AD64
+P 13800 17350
+F 0 "M21" H 13800 17200 50 0000 R CNN
+F 1 "eSim_MOS_N" H 13900 17300 50 0000 R CNN
+F 2 "" H 14100 17050 29 0000 C CNN
+F 3 "" H 13900 17150 60 0000 C CNN
+ 1 13800 17350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M28
+U 1 1 6855AD6A
+P 17750 13650
+F 0 "M28" H 17700 13700 50 0000 R CNN
+F 1 "eSim_MOS_P" H 17800 13800 50 0000 R CNN
+F 2 "" H 18000 13750 29 0000 C CNN
+F 3 "" H 17800 13650 60 0000 C CNN
+ 1 17750 13650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M29
+U 1 1 6855AD70
+P 17750 14800
+F 0 "M29" H 17700 14850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 17800 14950 50 0000 R CNN
+F 2 "" H 18000 14900 29 0000 C CNN
+F 3 "" H 17800 14800 60 0000 C CNN
+ 1 17750 14800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M27
+U 1 1 6855AD76
+P 17700 15600
+F 0 "M27" H 17700 15450 50 0000 R CNN
+F 1 "eSim_MOS_N" H 17800 15550 50 0000 R CNN
+F 2 "" H 18000 15300 29 0000 C CNN
+F 3 "" H 17800 15400 60 0000 C CNN
+ 1 17700 15600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M25
+U 1 1 6855AD7C
+P 16100 15650
+F 0 "M25" H 16100 15500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 16200 15600 50 0000 R CNN
+F 2 "" H 16400 15350 29 0000 C CNN
+F 3 "" H 16200 15450 60 0000 C CNN
+ 1 16100 15650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M33
+U 1 1 6855AD82
+P 20500 15850
+F 0 "M33" H 20500 15700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 20600 15800 50 0000 R CNN
+F 2 "" H 20800 15550 29 0000 C CNN
+F 3 "" H 20600 15650 60 0000 C CNN
+ 1 20500 15850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M34
+U 1 1 6855AD88
+P 20550 14750
+F 0 "M34" H 20500 14800 50 0000 R CNN
+F 1 "eSim_MOS_P" H 20600 14900 50 0000 R CNN
+F 2 "" H 20800 14850 29 0000 C CNN
+F 3 "" H 20600 14750 60 0000 C CNN
+ 1 20550 14750
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M37
+U 1 1 6855AD8E
+P 23450 15900
+F 0 "M37" H 23450 15750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 23550 15850 50 0000 R CNN
+F 2 "" H 23750 15600 29 0000 C CNN
+F 3 "" H 23550 15700 60 0000 C CNN
+ 1 23450 15900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M38
+U 1 1 6855AD94
+P 23500 14800
+F 0 "M38" H 23450 14850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 23550 14950 50 0000 R CNN
+F 2 "" H 23750 14900 29 0000 C CNN
+F 3 "" H 23550 14800 60 0000 C CNN
+ 1 23500 14800
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6855AD9A
+P 4750 14750
+F 0 "U1" H 4800 14850 30 0000 C CNN
+F 1 "PORT" H 4750 14750 30 0000 C CNN
+F 2 "" H 4750 14750 60 0000 C CNN
+F 3 "" H 4750 14750 60 0000 C CNN
+ 5 4750 14750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6855ADA0
+P 4800 16250
+F 0 "U1" H 4850 16350 30 0000 C CNN
+F 1 "PORT" H 4800 16250 30 0000 C CNN
+F 2 "" H 4800 16250 60 0000 C CNN
+F 3 "" H 4800 16250 60 0000 C CNN
+ 6 4800 16250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6855ADA6
+P 6300 19300
+F 0 "U1" H 6350 19400 30 0000 C CNN
+F 1 "PORT" H 6300 19300 30 0000 C CNN
+F 2 "" H 6300 19300 60 0000 C CNN
+F 3 "" H 6300 19300 60 0000 C CNN
+ 8 6300 19300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6855ADAC
+P 6450 20750
+F 0 "U1" H 6500 20850 30 0000 C CNN
+F 1 "PORT" H 6450 20750 30 0000 C CNN
+F 2 "" H 6450 20750 60 0000 C CNN
+F 3 "" H 6450 20750 60 0000 C CNN
+ 9 6450 20750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6855ADB2
+P 25450 15350
+F 0 "U1" H 25500 15450 30 0000 C CNN
+F 1 "PORT" H 25450 15350 30 0000 C CNN
+F 2 "" H 25450 15350 60 0000 C CNN
+F 3 "" H 25450 15350 60 0000 C CNN
+ 4 25450 15350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6855ADB8
+P 13750 22400
+F 0 "U1" H 13800 22500 30 0000 C CNN
+F 1 "PORT" H 13750 22400 30 0000 C CNN
+F 2 "" H 13750 22400 60 0000 C CNN
+F 3 "" H 13750 22400 60 0000 C CNN
+ 7 13750 22400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6855ADC4
+P 15100 12050
+F 0 "U1" H 15150 12150 30 0000 C CNN
+F 1 "PORT" H 15100 12050 30 0000 C CNN
+F 2 "" H 15100 12050 60 0000 C CNN
+F 3 "" H 15100 12050 60 0000 C CNN
+ 11 15100 12050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7700 13600 7700 12950
+Wire Wire Line
+ 7700 12950 9400 12950
+Wire Wire Line
+ 9300 12950 9300 13600
+Wire Wire Line
+ 9400 12950 9400 13650
+Connection ~ 9300 12950
+Wire Wire Line
+ 7800 13650 7800 12950
+Connection ~ 7800 12950
+Wire Wire Line
+ 7700 14000 7700 14450
+Wire Wire Line
+ 7700 14450 9350 14450
+Wire Wire Line
+ 9350 14050 9350 15050
+Wire Wire Line
+ 9300 14000 9300 14050
+Wire Wire Line
+ 9300 14050 9350 14050
+Connection ~ 9350 14450
+Wire Wire Line
+ 9350 15450 9350 16100
+Wire Wire Line
+ 9350 16500 9350 16850
+Wire Wire Line
+ 9450 16450 9450 16600
+Wire Wire Line
+ 9450 16600 9350 16600
+Connection ~ 9350 16600
+Wire Wire Line
+ 9450 15400 9450 15450
+Wire Wire Line
+ 9450 15450 9500 15450
+Wire Wire Line
+ 9500 15450 9500 16750
+Wire Wire Line
+ 9500 16750 9350 16750
+Connection ~ 9350 16750
+Wire Wire Line
+ 7400 13800 7100 13800
+Wire Wire Line
+ 7100 13800 7100 15250
+Wire Wire Line
+ 7100 15250 9050 15250
+Wire Wire Line
+ 9000 13800 8400 13800
+Wire Wire Line
+ 8400 13800 8400 16300
+Wire Wire Line
+ 6550 16300 9050 16300
+Wire Wire Line
+ 6550 16250 6550 16300
+Connection ~ 8400 16300
+Wire Wire Line
+ 7100 14650 6400 14650
+Wire Wire Line
+ 6400 14650 6400 14700
+Connection ~ 7100 14650
+Wire Wire Line
+ 7850 18150 7850 17500
+Wire Wire Line
+ 7850 17500 9550 17500
+Wire Wire Line
+ 9450 17500 9450 18150
+Wire Wire Line
+ 9550 17500 9550 18200
+Connection ~ 9450 17500
+Wire Wire Line
+ 7950 18200 7950 17500
+Connection ~ 7950 17500
+Wire Wire Line
+ 7850 18550 7850 19000
+Wire Wire Line
+ 7850 19000 9500 19000
+Wire Wire Line
+ 9500 18600 9500 19600
+Wire Wire Line
+ 9450 18550 9450 18600
+Wire Wire Line
+ 9450 18600 9500 18600
+Connection ~ 9500 19000
+Wire Wire Line
+ 9500 20000 9500 20650
+Wire Wire Line
+ 9500 21050 9500 21400
+Wire Wire Line
+ 9600 21000 9600 21150
+Wire Wire Line
+ 9600 21150 9500 21150
+Connection ~ 9500 21150
+Wire Wire Line
+ 9600 19950 9600 20000
+Wire Wire Line
+ 9600 20000 9650 20000
+Wire Wire Line
+ 9650 20000 9650 21300
+Wire Wire Line
+ 9650 21300 9500 21300
+Connection ~ 9500 21300
+Wire Wire Line
+ 7550 18350 7250 18350
+Wire Wire Line
+ 7250 18350 7250 19800
+Wire Wire Line
+ 7250 19800 9200 19800
+Wire Wire Line
+ 9150 18350 8550 18350
+Wire Wire Line
+ 8550 18350 8550 20850
+Wire Wire Line
+ 6700 20850 9200 20850
+Wire Wire Line
+ 6700 20750 6700 20850
+Connection ~ 8550 20850
+Wire Wire Line
+ 7250 19200 6550 19200
+Wire Wire Line
+ 6550 19200 6550 19300
+Connection ~ 7250 19200
+Wire Wire Line
+ 12350 14850 12350 14200
+Wire Wire Line
+ 12350 14200 14050 14200
+Wire Wire Line
+ 13950 14200 13950 14850
+Wire Wire Line
+ 14050 14200 14050 14900
+Connection ~ 13950 14200
+Wire Wire Line
+ 12450 14900 12450 14200
+Connection ~ 12450 14200
+Wire Wire Line
+ 12350 15250 12350 15700
+Wire Wire Line
+ 12350 15700 14000 15700
+Wire Wire Line
+ 14000 15300 14000 16300
+Wire Wire Line
+ 13950 15250 13950 15300
+Wire Wire Line
+ 13950 15300 14000 15300
+Connection ~ 14000 15700
+Wire Wire Line
+ 14000 16700 14000 17350
+Wire Wire Line
+ 14000 17750 14000 22400
+Wire Wire Line
+ 14100 17700 14100 17850
+Wire Wire Line
+ 14100 17850 14000 17850
+Connection ~ 14000 17850
+Wire Wire Line
+ 14100 16650 14100 16700
+Wire Wire Line
+ 14100 16700 14150 16700
+Wire Wire Line
+ 14150 16700 14150 18000
+Wire Wire Line
+ 14150 18000 14000 18000
+Connection ~ 14000 18000
+Wire Wire Line
+ 12050 15050 11750 15050
+Wire Wire Line
+ 11750 15050 11750 16500
+Wire Wire Line
+ 11750 16500 13700 16500
+Wire Wire Line
+ 13650 15050 13050 15050
+Wire Wire Line
+ 13050 15050 13050 17550
+Wire Wire Line
+ 11200 17550 13700 17550
+Wire Wire Line
+ 11200 17550 11200 17500
+Connection ~ 13050 17550
+Wire Wire Line
+ 11750 15900 11050 15900
+Wire Wire Line
+ 11050 15900 11050 15950
+Connection ~ 11750 15900
+Wire Wire Line
+ 9350 14250 10500 14250
+Wire Wire Line
+ 10500 14250 10500 15950
+Wire Wire Line
+ 10500 15950 11050 15950
+Connection ~ 9350 14250
+Wire Wire Line
+ 9500 18750 10650 18750
+Wire Wire Line
+ 10650 18750 10650 17500
+Wire Wire Line
+ 10650 17500 11200 17500
+Connection ~ 9500 18750
+Wire Wire Line
+ 17900 13450 17900 12800
+Wire Wire Line
+ 18000 13500 18000 12800
+Wire Wire Line
+ 18000 14650 18000 14250
+Wire Wire Line
+ 18000 14250 18300 14250
+Wire Wire Line
+ 18300 14250 18300 12800
+Wire Wire Line
+ 17900 13850 17900 14600
+Wire Wire Line
+ 17900 15000 17900 15600
+Wire Wire Line
+ 16300 15650 16300 15200
+Wire Wire Line
+ 16300 15200 17900 15200
+Connection ~ 17900 15200
+Wire Wire Line
+ 14000 15400 15300 15400
+Wire Wire Line
+ 15300 15400 15300 14450
+Wire Wire Line
+ 15300 14450 17200 14450
+Wire Wire Line
+ 17200 14450 17200 15800
+Wire Wire Line
+ 17200 14800 17600 14800
+Connection ~ 14000 15400
+Wire Wire Line
+ 17200 15800 17600 15800
+Connection ~ 17200 14800
+Wire Wire Line
+ 15350 13650 17600 13650
+Wire Wire Line
+ 15350 12050 15350 13650
+Wire Wire Line
+ 15500 13650 15500 15850
+Wire Wire Line
+ 15500 15850 16000 15850
+Connection ~ 15500 13650
+Wire Wire Line
+ 16300 16050 16300 18100
+Wire Wire Line
+ 14000 18100 20800 18100
+Wire Wire Line
+ 17900 18100 17900 16000
+Connection ~ 16300 18100
+Wire Wire Line
+ 18000 18100 18000 15950
+Connection ~ 17900 18100
+Wire Wire Line
+ 16400 16000 16400 18100
+Connection ~ 16400 18100
+Wire Wire Line
+ 17900 12800 23750 12800
+Connection ~ 18000 12800
+Wire Wire Line
+ 17900 15350 19950 15350
+Connection ~ 17900 15350
+Wire Wire Line
+ 20400 14750 19950 14750
+Wire Wire Line
+ 19950 14750 19950 16050
+Wire Wire Line
+ 19950 16050 20400 16050
+Connection ~ 19950 15350
+Wire Wire Line
+ 20700 14950 20700 15850
+Wire Wire Line
+ 20700 12800 20700 14550
+Connection ~ 18300 12800
+Wire Wire Line
+ 20800 12800 20800 14600
+Connection ~ 20700 12800
+Wire Wire Line
+ 20700 18100 20700 16250
+Connection ~ 18000 18100
+Wire Wire Line
+ 20800 16200 20800 18150
+Connection ~ 20700 18100
+Wire Wire Line
+ 20700 15400 22900 15400
+Wire Wire Line
+ 23350 14800 22900 14800
+Wire Wire Line
+ 22900 14800 22900 16100
+Wire Wire Line
+ 22900 16100 23350 16100
+Connection ~ 22900 15400
+Wire Wire Line
+ 23650 15000 23650 15900
+Wire Wire Line
+ 23650 12800 23650 14600
+Wire Wire Line
+ 23750 12800 23750 14650
+Wire Wire Line
+ 23650 18150 23650 16300
+Wire Wire Line
+ 23750 18150 23750 16250
+Connection ~ 20700 15400
+Wire Wire Line
+ 20800 18150 23750 18150
+Connection ~ 20800 18100
+Connection ~ 23650 18150
+Connection ~ 20800 12800
+Connection ~ 23650 12800
+Wire Wire Line
+ 23650 15400 24850 15400
+Wire Wire Line
+ 24850 15400 24850 15350
+Connection ~ 23650 15400
+Wire Wire Line
+ 13150 12350 13150 14200
+Wire Wire Line
+ 4150 12350 20950 12350
+Wire Wire Line
+ 20950 12350 20950 12800
+Connection ~ 20950 12800
+Connection ~ 13150 14200
+Connection ~ 8300 12950
+Wire Wire Line
+ 5850 12350 5850 17050
+Wire Wire Line
+ 5850 17050 8650 17050
+Wire Wire Line
+ 8650 17050 8650 17500
+Connection ~ 8650 17500
+Wire Wire Line
+ 9350 16850 10100 16850
+Wire Wire Line
+ 10100 16850 10100 21400
+Wire Wire Line
+ 9500 21400 26800 21400
+Connection ~ 14000 18100
+Connection ~ 10100 21400
+Connection ~ 14000 21400
+Wire Wire Line
+ 5050 16250 6550 16250
+Wire Wire Line
+ 6400 14700 5000 14700
+Wire Wire Line
+ 5000 14700 5000 14750
+Wire Wire Line
+ 24850 15350 25200 15350
+Wire Wire Line
+ 8300 12350 8300 12950
+Connection ~ 13150 12350
+Connection ~ 8300 12350
+Wire Wire Line
+ 26800 21400 26800 10650
+Connection ~ 14900 10650
+Wire Wire Line
+ 4150 1600 4150 12350
+Connection ~ 5850 12350
+Connection ~ 6750 1600
+Text Label 14600 1300 0 60 ~ 0
+VDD
+Text Label 14000 21950 0 60 ~ 0
+VSS
+Text Label 7700 3900 0 60 ~ 0
+A1
+Text Label 5300 14700 0 60 ~ 0
+A2
+Text Label 7750 5550 0 60 ~ 0
+B1
+Text Label 5200 16250 0 60 ~ 0
+B2
+Text Label 7650 8450 0 60 ~ 0
+C1
+Text Label 6700 19200 0 60 ~ 0
+C2
+Text Label 7850 10100 0 60 ~ 0
+D1
+Text Label 6850 20850 0 60 ~ 0
+D2
+Text Label 16250 1450 0 60 ~ 0
+INHIBIT1
+Text Label 15350 12200 0 60 ~ 0
+INHIBIT2
+Text Label 25750 4600 0 60 ~ 0
+E1
+Text Label 24850 15350 0 60 ~ 0
+E2
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B.sub b/library/SubcircuitLibrary/CD4085B/CD4085B.sub
new file mode 100644
index 000000000..474a06a9c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/CD4085B.sub
@@ -0,0 +1,48 @@
+* Subcircuit CD4085B
+.subckt CD4085B /a1 /b1 /e1 /e2 /a2 /b2 /vss /c2 /d2 /inhibit1 /inhibit2 /c1 /d1 /vdd
+* c:\fossee\esim\library\subcircuitlibrary\cd4085b\cd4085b.cir
+.include NMOS-5um.lib
+.include PMOS-5um.lib
+m3 net-_m11-pad1_ /a1 /vdd /vdd mos_p W=40u L=5u M=8
+m11 net-_m11-pad1_ /b1 /vdd /vdd mos_p W=40u L=5u M=8
+m12 net-_m11-pad1_ /a1 net-_m12-pad3_ /vss mos_n W=20u L=5u M=4
+m13 net-_m12-pad3_ /b1 /vss /vss mos_n W=20u L=5u M=4
+m4 net-_m14-pad1_ /c1 /vdd /vdd mos_p W=40u L=5u M=8
+m14 net-_m14-pad1_ /d1 /vdd /vdd mos_p W=40u L=5u M=8
+m15 net-_m14-pad1_ /c1 net-_m15-pad3_ /vss mos_n W=20u L=5u M=4
+m16 net-_m15-pad3_ /d1 /vss /vss mos_n W=20u L=5u M=4
+m18 net-_m18-pad1_ net-_m11-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m22 net-_m18-pad1_ net-_m14-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m23 net-_m18-pad1_ net-_m11-pad1_ net-_m23-pad3_ /vss mos_n W=20u L=5u M=4
+m24 net-_m23-pad3_ net-_m14-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m31 net-_m31-pad1_ /inhibit1 /vdd /vdd mos_p W=40u L=5u M=8
+m32 net-_m26-pad1_ net-_m18-pad1_ net-_m31-pad1_ /vdd mos_p W=40u L=5u M=8
+m30 net-_m26-pad1_ net-_m18-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m26 net-_m26-pad1_ /inhibit1 /vss /vss mos_n W=20u L=5u M=4
+m35 net-_m35-pad1_ net-_m26-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m36 net-_m35-pad1_ net-_m26-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m39 /e1 net-_m35-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m40 /e1 net-_m35-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m1 net-_m1-pad1_ /a2 /vdd /vdd mos_p W=40u L=5u M=8
+m5 net-_m1-pad1_ /b2 /vdd /vdd mos_p W=40u L=5u M=8
+m6 net-_m1-pad1_ /a2 net-_m6-pad3_ /vss mos_n W=20u L=5u M=4
+m7 net-_m6-pad3_ /b2 /vss /vss mos_n W=20u L=5u M=4
+m2 net-_m19-pad2_ /c2 /vdd /vdd mos_p W=40u L=5u M=8
+m8 net-_m19-pad2_ /d2 /vdd /vdd mos_p W=40u L=5u M=8
+m9 net-_m19-pad2_ /c2 net-_m10-pad1_ /vss mos_n W=20u L=5u M=4
+m10 net-_m10-pad1_ /d2 /vss /vss mos_n W=20u L=5u M=4
+m17 net-_m17-pad1_ net-_m1-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m19 net-_m17-pad1_ net-_m19-pad2_ /vdd /vdd mos_p W=40u L=5u M=8
+m20 net-_m17-pad1_ net-_m1-pad1_ net-_m20-pad3_ /vss mos_n W=20u L=5u M=4
+m21 net-_m20-pad3_ net-_m19-pad2_ /vss /vss mos_n W=20u L=5u M=4
+m28 net-_m28-pad1_ /inhibit2 /vdd /vdd mos_p W=40u L=5u M=8
+m29 net-_m25-pad1_ net-_m17-pad1_ net-_m28-pad1_ /vdd mos_p W=40u L=5u M=8
+m27 net-_m25-pad1_ net-_m17-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m25 net-_m25-pad1_ /inhibit2 /vss /vss mos_n W=20u L=5u M=4
+m33 net-_m33-pad1_ net-_m25-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m34 net-_m33-pad1_ net-_m25-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m37 /e2 net-_m33-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m38 /e2 net-_m33-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+* Control Statements
+
+.ends CD4085B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4085B/CD4085B_Previous_Values.xml b/library/SubcircuitLibrary/CD4085B/CD4085B_Previous_Values.xml
new file mode 100644
index 000000000..c072b50bf
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/CD4085B_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecsecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4085B/NMOS-5um.lib b/library/SubcircuitLibrary/CD4085B/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/CD4085B/PMOS-5um.lib b/library/SubcircuitLibrary/CD4085B/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/CD4085B/analysis b/library/SubcircuitLibrary/CD4085B/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4085B/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/CD4098-cache.lib b/library/SubcircuitLibrary/CD4098/CD4098-cache.lib
new file mode 100644
index 000000000..23a1ef279
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098-cache.lib
@@ -0,0 +1,195 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# cd4098_latch
+#
+DEF cd4098_latch U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "cd4098_latch" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1400 0 1 0 N
+X D0 1 2150 1900 200 R 50 50 1 1 I
+X C0 2 2150 1800 200 R 50 50 1 1 I
+X R10 3 2150 1700 200 R 50 50 1 1 I
+X R20 4 2150 1600 200 R 50 50 1 1 I
+X Q0 5 3550 1900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.cir b/library/SubcircuitLibrary/CD4098/CD4098.cir
new file mode 100644
index 000000000..919af079a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.cir
@@ -0,0 +1,32 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4098\CD4098.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/25 13:17:11
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U5 Net-_U1-Pad2_ Net-_U5-Pad2_ d_inverter
+U2 Net-_U19-Pad2_ Net-_U2-Pad2_ d_inverter
+U3 Net-_U19-Pad3_ Net-_U11-Pad1_ d_inverter
+U8 Net-_U5-Pad2_ Net-_U2-Pad2_ Net-_U4-Pad2_ d_nand
+U4 Net-_U19-Pad10_ Net-_U4-Pad2_ Net-_U11-Pad1_ Net-_U12-Pad2_ Net-_U10-Pad1_ cd4098_latch
+U6 Net-_U10-Pad3_ Net-_U6-Pad2_ d_inverter
+U9 Net-_U10-Pad3_ Net-_U19-Pad4_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U7 Net-_U6-Pad2_ Net-_U19-Pad5_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad2_ d_nor
+U12 Net-_U11-Pad2_ Net-_U12-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U10-Pad1_ Net-_U13-Pad3_ d_nor
+U14 Net-_U11-Pad2_ Net-_U13-Pad1_ d_inverter
+U15 Net-_U13-Pad3_ Net-_U11-Pad1_ Net-_U15-Pad3_ d_nor
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P
+U17 Net-_U15-Pad3_ Net-_M2-Pad2_ dac_bridge_1
+M3 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad1_ Net-_M2-Pad3_ eSim_MOS_P
+U18 Net-_M1-Pad1_ Net-_U11-Pad2_ adc_bridge_1
+U16 Net-_U10-Pad1_ Net-_M1-Pad2_ dac_bridge_1
+U19 Net-_U1-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ Net-_U19-Pad4_ Net-_U19-Pad5_ Net-_M2-Pad3_ Net-_M1-Pad3_ ? Net-_U11-Pad2_ Net-_U19-Pad10_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.cir.out b/library/SubcircuitLibrary/CD4098/CD4098.cir.out
new file mode 100644
index 000000000..57f317163
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.cir.out
@@ -0,0 +1,89 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4098\cd4098.cir
+
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u5 net-_u1-pad2_ net-_u5-pad2_ d_inverter
+* u2 net-_u19-pad2_ net-_u2-pad2_ d_inverter
+* u3 net-_u19-pad3_ net-_u11-pad1_ d_inverter
+* u8 net-_u5-pad2_ net-_u2-pad2_ net-_u4-pad2_ d_nand
+* u4 net-_u19-pad10_ net-_u4-pad2_ net-_u11-pad1_ net-_u12-pad2_ net-_u10-pad1_ cd4098_latch
+* u6 net-_u10-pad3_ net-_u6-pad2_ d_inverter
+* u9 net-_u10-pad3_ net-_u19-pad4_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u7 net-_u6-pad2_ net-_u19-pad5_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_nor
+* u12 net-_u11-pad2_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u10-pad1_ net-_u13-pad3_ d_nor
+* u14 net-_u11-pad2_ net-_u13-pad1_ d_inverter
+* u15 net-_u13-pad3_ net-_u11-pad1_ net-_u15-pad3_ d_nor
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1
+* u17 net-_u15-pad3_ net-_m2-pad2_ dac_bridge_1
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad1_ net-_m2-pad3_ CMOSP W=100u L=100u M=1
+* u18 net-_m1-pad1_ net-_u11-pad2_ adc_bridge_1
+* u16 net-_u10-pad1_ net-_m1-pad2_ dac_bridge_1
+* u19 net-_u1-pad1_ net-_u19-pad2_ net-_u19-pad3_ net-_u19-pad4_ net-_u19-pad5_ net-_m2-pad3_ net-_m1-pad3_ ? net-_u11-pad2_ net-_u19-pad10_ port
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u5-pad2_ u5
+a3 net-_u19-pad2_ net-_u2-pad2_ u2
+a4 net-_u19-pad3_ net-_u11-pad1_ u3
+a5 [net-_u5-pad2_ net-_u2-pad2_ ] net-_u4-pad2_ u8
+a6 [net-_u19-pad10_ ] [net-_u4-pad2_ ] [net-_u11-pad1_ ] [net-_u12-pad2_ ] [net-_u10-pad1_ ] u4
+a7 net-_u10-pad3_ net-_u6-pad2_ u6
+a8 net-_u10-pad3_ net-_u19-pad4_ u9
+a9 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a10 net-_u6-pad2_ net-_u19-pad5_ u7
+a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11
+a12 net-_u11-pad2_ net-_u12-pad2_ u12
+a13 [net-_u13-pad1_ net-_u10-pad1_ ] net-_u13-pad3_ u13
+a14 net-_u11-pad2_ net-_u13-pad1_ u14
+a15 [net-_u13-pad3_ net-_u11-pad1_ ] net-_u15-pad3_ u15
+a16 [net-_u15-pad3_ ] [net-_m2-pad2_ ] u17
+a17 [net-_m1-pad1_ ] [net-_u11-pad2_ ] u18
+a18 [net-_u10-pad1_ ] [net-_m1-pad2_ ] u16
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: cd4098_latch, NgSpice Name: cd4098_latch
+.model u4 cd4098_latch(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u18 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.pro b/library/SubcircuitLibrary/CD4098/CD4098.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.proj b/library/SubcircuitLibrary/CD4098/CD4098.proj
new file mode 100644
index 000000000..da1524788
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.proj
@@ -0,0 +1 @@
+schematicFile CD4098.sch
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.sch b/library/SubcircuitLibrary/CD4098/CD4098.sch
new file mode 100644
index 000000000..ca0e5bf4a
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.sch
@@ -0,0 +1,537 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4098-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U1
+U 1 1 685A774C
+P 5700 6850
+F 0 "U1" H 5700 6750 60 0000 C CNN
+F 1 "d_inverter" H 5700 7000 60 0000 C CNN
+F 2 "" H 5750 6800 60 0000 C CNN
+F 3 "" H 5750 6800 60 0000 C CNN
+ 1 5700 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 685A783C
+P 6450 6850
+F 0 "U5" H 6450 6750 60 0000 C CNN
+F 1 "d_inverter" H 6450 7000 60 0000 C CNN
+F 2 "" H 6500 6800 60 0000 C CNN
+F 3 "" H 6500 6800 60 0000 C CNN
+ 1 6450 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 685A785A
+P 5700 7250
+F 0 "U2" H 5700 7150 60 0000 C CNN
+F 1 "d_inverter" H 5700 7400 60 0000 C CNN
+F 2 "" H 5750 7200 60 0000 C CNN
+F 3 "" H 5750 7200 60 0000 C CNN
+ 1 5700 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 685A787D
+P 5700 7650
+F 0 "U3" H 5700 7550 60 0000 C CNN
+F 1 "d_inverter" H 5700 7800 60 0000 C CNN
+F 2 "" H 5750 7600 60 0000 C CNN
+F 3 "" H 5750 7600 60 0000 C CNN
+ 1 5700 7650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U8
+U 1 1 685A78A1
+P 7500 6950
+F 0 "U8" H 7500 6950 60 0000 C CNN
+F 1 "d_nand" H 7550 7050 60 0000 C CNN
+F 2 "" H 7500 6950 60 0000 C CNN
+F 3 "" H 7500 6950 60 0000 C CNN
+ 1 7500 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L cd4098_latch U4
+U 1 1 685A78FA
+P 6050 8700
+F 0 "U4" H 8900 10500 60 0000 C CNN
+F 1 "cd4098_latch" H 8900 10700 60 0000 C CNN
+F 2 "" H 8900 10650 60 0000 C CNN
+F 3 "" H 8900 10650 60 0000 C CNN
+ 1 6050 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 685A7A49
+P 7400 8850
+F 0 "U6" H 7400 8750 60 0000 C CNN
+F 1 "d_inverter" H 7400 9000 60 0000 C CNN
+F 2 "" H 7450 8800 60 0000 C CNN
+F 3 "" H 7450 8800 60 0000 C CNN
+ 1 7400 8850
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 685A7B83
+P 7800 8850
+F 0 "U9" H 7800 8750 60 0000 C CNN
+F 1 "d_inverter" H 7800 9000 60 0000 C CNN
+F 2 "" H 7850 8800 60 0000 C CNN
+F 3 "" H 7850 8800 60 0000 C CNN
+ 1 7800 8850
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U10
+U 1 1 685A7BCD
+P 8550 8600
+F 0 "U10" H 8550 8600 60 0000 C CNN
+F 1 "d_nor" H 8600 8700 60 0000 C CNN
+F 2 "" H 8550 8600 60 0000 C CNN
+F 3 "" H 8550 8600 60 0000 C CNN
+ 1 8550 8600
+ -1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 685A7C5A
+P 7400 9650
+F 0 "U7" H 7400 9550 60 0000 C CNN
+F 1 "d_inverter" H 7400 9800 60 0000 C CNN
+F 2 "" H 7450 9600 60 0000 C CNN
+F 3 "" H 7450 9600 60 0000 C CNN
+ 1 7400 9650
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U11
+U 1 1 685A7CB1
+P 9600 8900
+F 0 "U11" H 9600 8900 60 0000 C CNN
+F 1 "d_nor" H 9650 9000 60 0000 C CNN
+F 2 "" H 9600 8900 60 0000 C CNN
+F 3 "" H 9600 8900 60 0000 C CNN
+ 1 9600 8900
+ -1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 685A7FB4
+P 9900 9550
+F 0 "U12" H 9900 9450 60 0000 C CNN
+F 1 "d_inverter" H 9900 9700 60 0000 C CNN
+F 2 "" H 9950 9500 60 0000 C CNN
+F 3 "" H 9950 9500 60 0000 C CNN
+ 1 9900 9550
+ -1 0 0 -1
+$EndComp
+$Comp
+L d_nor U13
+U 1 1 685A85BD
+P 10300 7050
+F 0 "U13" H 10300 7050 60 0000 C CNN
+F 1 "d_nor" H 10350 7150 60 0000 C CNN
+F 2 "" H 10300 7050 60 0000 C CNN
+F 3 "" H 10300 7050 60 0000 C CNN
+ 1 10300 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U14
+U 1 1 685A864D
+P 10750 6600
+F 0 "U14" H 10750 6500 60 0000 C CNN
+F 1 "d_inverter" H 10750 6750 60 0000 C CNN
+F 2 "" H 10800 6550 60 0000 C CNN
+F 3 "" H 10800 6550 60 0000 C CNN
+ 1 10750 6600
+ -1 0 0 -1
+$EndComp
+$Comp
+L d_nor U15
+U 1 1 685A89C6
+P 11250 7300
+F 0 "U15" H 11250 7300 60 0000 C CNN
+F 1 "d_nor" H 11300 7400 60 0000 C CNN
+F 2 "" H 11250 7300 60 0000 C CNN
+F 3 "" H 11250 7300 60 0000 C CNN
+ 1 11250 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M1
+U 1 1 685A8AE5
+P 13200 8450
+F 0 "M1" H 13200 8300 50 0000 R CNN
+F 1 "eSim_MOS_N" H 13300 8400 50 0000 R CNN
+F 2 "" H 13500 8150 29 0000 C CNN
+F 3 "" H 13300 8250 60 0000 C CNN
+ 1 13200 8450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M2
+U 1 1 685A8B2C
+P 13250 7550
+F 0 "M2" H 13200 7600 50 0000 R CNN
+F 1 "eSim_MOS_P" H 13300 7700 50 0000 R CNN
+F 2 "" H 13500 7650 29 0000 C CNN
+F 3 "" H 13300 7550 60 0000 C CNN
+ 1 13250 7550
+ 1 0 0 1
+$EndComp
+$Comp
+L dac_bridge_1 U17
+U 1 1 685A8BED
+P 12450 7300
+F 0 "U17" H 12450 7300 60 0000 C CNN
+F 1 "dac_bridge_1" H 12450 7450 60 0000 C CNN
+F 2 "" H 12450 7300 60 0000 C CNN
+F 3 "" H 12450 7300 60 0000 C CNN
+ 1 12450 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M3
+U 1 1 685A8D82
+P 13250 8100
+F 0 "M3" H 13200 8150 50 0000 R CNN
+F 1 "eSim_MOS_P" H 13300 8250 50 0000 R CNN
+F 2 "" H 13500 8200 29 0000 C CNN
+F 3 "" H 13300 8100 60 0000 C CNN
+ 1 13250 8100
+ 1 0 0 1
+$EndComp
+$Comp
+L adc_bridge_1 U18
+U 1 1 685A8FBC
+P 15150 7900
+F 0 "U18" H 15150 7900 60 0000 C CNN
+F 1 "adc_bridge_1" H 15150 8050 60 0000 C CNN
+F 2 "" H 15150 7900 60 0000 C CNN
+F 3 "" H 15150 7900 60 0000 C CNN
+ 1 15150 7900
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_1 U16
+U 1 1 685A927F
+P 11900 8450
+F 0 "U16" H 11900 8450 60 0000 C CNN
+F 1 "dac_bridge_1" H 11900 8600 60 0000 C CNN
+F 2 "" H 11900 8450 60 0000 C CNN
+F 3 "" H 11900 8450 60 0000 C CNN
+ 1 11900 8450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 1 1 685B7973
+P 4950 6850
+F 0 "U19" H 5000 6950 30 0000 C CNN
+F 1 "PORT" H 4950 6850 30 0000 C CNN
+F 2 "" H 4950 6850 60 0000 C CNN
+F 3 "" H 4950 6850 60 0000 C CNN
+ 1 4950 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 2 1 685B7A0E
+P 4950 7250
+F 0 "U19" H 5000 7350 30 0000 C CNN
+F 1 "PORT" H 4950 7250 30 0000 C CNN
+F 2 "" H 4950 7250 60 0000 C CNN
+F 3 "" H 4950 7250 60 0000 C CNN
+ 2 4950 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 4 1 685B7A55
+P 7800 9550
+F 0 "U19" H 7850 9650 30 0000 C CNN
+F 1 "PORT" H 7800 9550 30 0000 C CNN
+F 2 "" H 7800 9550 60 0000 C CNN
+F 3 "" H 7800 9550 60 0000 C CNN
+ 4 7800 9550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U19
+U 3 1 685B7A9A
+P 4900 7650
+F 0 "U19" H 4950 7750 30 0000 C CNN
+F 1 "PORT" H 4900 7650 30 0000 C CNN
+F 2 "" H 4900 7650 60 0000 C CNN
+F 3 "" H 4900 7650 60 0000 C CNN
+ 3 4900 7650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 5 1 685B7AE1
+P 7150 10100
+F 0 "U19" H 7200 10200 30 0000 C CNN
+F 1 "PORT" H 7150 10100 30 0000 C CNN
+F 2 "" H 7150 10100 60 0000 C CNN
+F 3 "" H 7150 10100 60 0000 C CNN
+ 5 7150 10100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 6 1 685B7B2E
+P 14350 5200
+F 0 "U19" H 14400 5300 30 0000 C CNN
+F 1 "PORT" H 14350 5200 30 0000 C CNN
+F 2 "" H 14350 5200 60 0000 C CNN
+F 3 "" H 14350 5200 60 0000 C CNN
+ 6 14350 5200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 7 1 685B7B7D
+P 13200 9050
+F 0 "U19" H 13250 9150 30 0000 C CNN
+F 1 "PORT" H 13200 9050 30 0000 C CNN
+F 2 "" H 13200 9050 60 0000 C CNN
+F 3 "" H 13200 9050 60 0000 C CNN
+ 7 13200 9050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 8 1 685B7BCA
+P 7050 5100
+F 0 "U19" H 7100 5200 30 0000 C CNN
+F 1 "PORT" H 7050 5100 30 0000 C CNN
+F 2 "" H 7050 5100 60 0000 C CNN
+F 3 "" H 7050 5100 60 0000 C CNN
+ 8 7050 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 9 1 685B7C1D
+P 14650 8600
+F 0 "U19" H 14700 8700 30 0000 C CNN
+F 1 "PORT" H 14650 8600 30 0000 C CNN
+F 2 "" H 14650 8600 60 0000 C CNN
+F 3 "" H 14650 8600 60 0000 C CNN
+ 9 14650 8600
+ 1 0 0 -1
+$EndComp
+NoConn ~ 7300 5100
+$Comp
+L PORT U19
+U 10 1 685BE05C
+P 7950 6550
+F 0 "U19" H 8000 6650 30 0000 C CNN
+F 1 "PORT" H 7950 6550 30 0000 C CNN
+F 2 "" H 7950 6550 60 0000 C CNN
+F 3 "" H 7950 6550 60 0000 C CNN
+ 10 7950 6550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6000 6850 6150 6850
+Wire Wire Line
+ 6750 6850 7050 6850
+Wire Wire Line
+ 6000 7250 6900 7250
+Wire Wire Line
+ 6900 7250 6900 6950
+Wire Wire Line
+ 6900 6950 7050 6950
+Wire Wire Line
+ 7950 6900 8200 6900
+Wire Wire Line
+ 6000 7650 10800 7650
+Wire Wire Line
+ 8000 7650 8000 7000
+Wire Wire Line
+ 8000 7000 8200 7000
+Wire Wire Line
+ 7400 8550 8100 8550
+Connection ~ 7800 8550
+Wire Wire Line
+ 7400 9150 7400 9350
+Wire Wire Line
+ 9000 8600 9000 8850
+Wire Wire Line
+ 9000 8850 9150 8850
+Wire Wire Line
+ 9600 9550 9100 9550
+Wire Wire Line
+ 9100 9550 9100 7350
+Wire Wire Line
+ 9100 7350 8200 7350
+Wire Wire Line
+ 8200 7350 8200 7100
+Wire Wire Line
+ 9600 6800 9750 6800
+Wire Wire Line
+ 9750 6800 9750 7050
+Wire Wire Line
+ 9750 7050 9850 7050
+Wire Wire Line
+ 9850 6950 9850 6600
+Wire Wire Line
+ 9850 6600 10450 6600
+Wire Wire Line
+ 11050 6600 14250 6600
+Wire Wire Line
+ 14250 6600 14250 9550
+Wire Wire Line
+ 14250 9550 10200 9550
+Wire Wire Line
+ 10750 7000 10750 7200
+Wire Wire Line
+ 10750 7200 10800 7200
+Wire Wire Line
+ 10800 7300 10800 8800
+Connection ~ 8000 7650
+Wire Wire Line
+ 10800 8800 10050 8800
+Connection ~ 10800 7650
+Wire Wire Line
+ 10050 8900 14250 8900
+Connection ~ 14250 8900
+Wire Wire Line
+ 11850 7250 11700 7250
+Wire Wire Line
+ 13000 7250 13000 7550
+Wire Wire Line
+ 13000 7550 13100 7550
+Wire Wire Line
+ 13400 7350 13650 7350
+Wire Wire Line
+ 13500 5200 13500 7400
+Wire Wire Line
+ 13400 8850 13500 8850
+Wire Wire Line
+ 13500 8850 13500 8800
+Wire Wire Line
+ 13400 8300 13400 8450
+Wire Wire Line
+ 13400 7750 13400 7900
+Wire Wire Line
+ 13650 7350 13650 7950
+Wire Wire Line
+ 13650 7950 13500 7950
+Connection ~ 13500 7350
+Wire Wire Line
+ 13400 8350 14100 8350
+Wire Wire Line
+ 14100 8350 14100 7850
+Wire Wire Line
+ 14100 7850 14550 7850
+Connection ~ 13400 8350
+Wire Wire Line
+ 15700 8400 15700 7850
+Wire Wire Line
+ 14250 8400 15700 8400
+Connection ~ 14250 8400
+Wire Wire Line
+ 13100 8100 12750 8100
+Wire Wire Line
+ 12750 8100 12750 8650
+Wire Wire Line
+ 12750 8650 13100 8650
+Wire Wire Line
+ 12450 8400 12750 8400
+Connection ~ 12750 8400
+Wire Wire Line
+ 9650 6800 9650 8500
+Wire Wire Line
+ 9650 8500 9000 8500
+Connection ~ 9650 6800
+Wire Wire Line
+ 9700 6800 9700 8400
+Wire Wire Line
+ 9700 8400 11300 8400
+Connection ~ 9700 6800
+Wire Wire Line
+ 5200 6850 5400 6850
+Wire Wire Line
+ 5200 7250 5400 7250
+Wire Wire Line
+ 5150 7650 5400 7650
+Wire Wire Line
+ 7800 9150 7800 9300
+Wire Wire Line
+ 7400 9950 7400 10100
+Wire Wire Line
+ 13450 9050 13450 8850
+Connection ~ 13450 8850
+Wire Wire Line
+ 14900 8600 14900 8400
+Connection ~ 14900 8400
+Wire Wire Line
+ 13500 5200 14100 5200
+Wire Wire Line
+ 8200 6550 8200 6800
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4098/CD4098.sub b/library/SubcircuitLibrary/CD4098/CD4098.sub
new file mode 100644
index 000000000..2774be7b8
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098.sub
@@ -0,0 +1,83 @@
+* Subcircuit CD4098
+.subckt CD4098 net-_u1-pad1_ net-_u19-pad2_ net-_u19-pad3_ net-_u19-pad4_ net-_u19-pad5_ net-_m2-pad3_ net-_m1-pad3_ ? net-_u11-pad2_ net-_u19-pad10_
+* c:\fossee\esim\library\subcircuitlibrary\cd4098\cd4098.cir
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u5 net-_u1-pad2_ net-_u5-pad2_ d_inverter
+* u2 net-_u19-pad2_ net-_u2-pad2_ d_inverter
+* u3 net-_u19-pad3_ net-_u11-pad1_ d_inverter
+* u8 net-_u5-pad2_ net-_u2-pad2_ net-_u4-pad2_ d_nand
+* u4 net-_u19-pad10_ net-_u4-pad2_ net-_u11-pad1_ net-_u12-pad2_ net-_u10-pad1_ cd4098_latch
+* u6 net-_u10-pad3_ net-_u6-pad2_ d_inverter
+* u9 net-_u10-pad3_ net-_u19-pad4_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u7 net-_u6-pad2_ net-_u19-pad5_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u10-pad2_ d_nor
+* u12 net-_u11-pad2_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u10-pad1_ net-_u13-pad3_ d_nor
+* u14 net-_u11-pad2_ net-_u13-pad1_ d_inverter
+* u15 net-_u13-pad3_ net-_u11-pad1_ net-_u15-pad3_ d_nor
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1
+* u17 net-_u15-pad3_ net-_m2-pad2_ dac_bridge_1
+m3 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad1_ net-_m2-pad3_ CMOSP W=100u L=100u M=1
+* u18 net-_m1-pad1_ net-_u11-pad2_ adc_bridge_1
+* u16 net-_u10-pad1_ net-_m1-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u5-pad2_ u5
+a3 net-_u19-pad2_ net-_u2-pad2_ u2
+a4 net-_u19-pad3_ net-_u11-pad1_ u3
+a5 [net-_u5-pad2_ net-_u2-pad2_ ] net-_u4-pad2_ u8
+a6 [net-_u19-pad10_ ] [net-_u4-pad2_ ] [net-_u11-pad1_ ] [net-_u12-pad2_ ] [net-_u10-pad1_ ] u4
+a7 net-_u10-pad3_ net-_u6-pad2_ u6
+a8 net-_u10-pad3_ net-_u19-pad4_ u9
+a9 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a10 net-_u6-pad2_ net-_u19-pad5_ u7
+a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u10-pad2_ u11
+a12 net-_u11-pad2_ net-_u12-pad2_ u12
+a13 [net-_u13-pad1_ net-_u10-pad1_ ] net-_u13-pad3_ u13
+a14 net-_u11-pad2_ net-_u13-pad1_ u14
+a15 [net-_u13-pad3_ net-_u11-pad1_ ] net-_u15-pad3_ u15
+a16 [net-_u15-pad3_ ] [net-_m2-pad2_ ] u17
+a17 [net-_m1-pad1_ ] [net-_u11-pad2_ ] u18
+a18 [net-_u10-pad1_ ] [net-_m1-pad2_ ] u16
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: cd4098_latch, NgSpice Name: cd4098_latch
+.model u4 cd4098_latch(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u17 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u18 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u16 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends CD4098
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_Previous_Values.xml b/library/SubcircuitLibrary/CD4098/CD4098_Previous_Values.xml
new file mode 100644
index 000000000..d5270ce15
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_Previous_Values.xml
@@ -0,0 +1 @@
+d_inverterd_inverterd_inverterd_inverterd_nandcd4098_latchd_inverterd_inverterd_nord_inverterd_nord_inverterd_nord_inverterd_nordac_bridgeadc_bridgedac_bridgedac_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_latch.v b/library/SubcircuitLibrary/CD4098/CD4098_latch.v
new file mode 100644
index 000000000..85e13b4ec
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_latch.v
@@ -0,0 +1,18 @@
+ module CD4098_latch(
+input D,
+input C,
+input R1,
+input R2,
+output reg Q);
+
+
+
+always@(posedge R1 or posedge R2 or posedge C)
+begin
+if(R1 || R2)
+Q<=0;
+else
+Q<=D;
+end
+endmodule
+
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test-cache.lib b/library/SubcircuitLibrary/CD4098/CD4098_test-cache.lib
new file mode 100644
index 000000000..e9e616527
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test-cache.lib
@@ -0,0 +1,178 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# mono
+#
+DEF mono x 0 40 Y Y 1 F N
+F0 "x" 0 -650 60 H V C CNN
+F1 "mono" 0 650 60 H V C CNN
+F2 "" 0 650 60 H I C CNN
+F3 "" 0 650 60 H I C CNN
+DRAW
+S -500 400 550 -550 0 1 0 N
+X TR_plus 1 -700 300 200 R 50 50 1 1 I
+X TR_minus 2 -700 100 200 R 50 50 1 1 I
+X RST 3 -700 -100 200 R 50 50 1 1 I
+X Q 4 750 300 200 L 50 50 1 1 O
+X Q_bar 5 750 100 200 L 50 50 1 1 O
+X VDD 6 -700 -300 200 R 50 50 1 1 I
+X VSS 7 750 -150 200 L 50 50 1 1 I
+X Cx 8 750 -350 200 L 50 50 1 1 I
+X RxCx 9 -700 -450 200 R 50 50 1 1 I
+X DVCC 10 750 -500 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.cir b/library/SubcircuitLibrary/CD4098/CD4098_test.cir
new file mode 100644
index 000000000..5e71b4e94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.cir
@@ -0,0 +1,26 @@
+* C:\Users\pavithra\eSim-Workspace\CD4098_test\CD4098_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/25 15:32:18
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 trig rst Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2
+v1 trig GND pulse
+v2 rst GND pulse
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 1u
+R1 Net-_R1-Pad1_ Net-_C1-Pad2_ 5k
+U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Q Q_bar dac_bridge_2
+U5 Q plot_v1
+U6 Q_bar plot_v1
+U2 rst plot_v1
+U3 trig plot_v1
+x1 Net-_U1-Pad3_ Net-_U7-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_R1-Pad1_ GND Net-_C1-Pad1_ Net-_U8-Pad2_ Net-_U7-Pad2_ mono
+U7 Net-_U7-Pad1_ Net-_U7-Pad2_ adc_bridge_1
+v3 Net-_U7-Pad1_ GND DC
+U8 Net-_C1-Pad2_ Net-_U8-Pad2_ adc_bridge_1
+R2 Net-_C1-Pad2_ Net-_C1-Pad1_ 1k
+v4 Net-_R1-Pad1_ GND DC
+
+.end
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.cir.out b/library/SubcircuitLibrary/CD4098/CD4098_test.cir.out
new file mode 100644
index 000000000..707d438a0
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.cir.out
@@ -0,0 +1,43 @@
+ * c:\users\pavithra\esim-workspace\cd4098_test\cd4098_test.cir
+
+.include CD4098.sub
+* u1 trig rst net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
+v1 trig gnd pulse(0 5 2 0.1n 0.1n 0.125 3)
+v2 rst gnd pulse(5 0 1 0.1n 0.1n 0.3 3)
+c1 net-_c1-pad1_ net-_c1-pad2_ 1u
+r1 net-_r1-pad1_ net-_c1-pad2_ 5k
+* u4 net-_u4-pad1_ net-_u4-pad2_ q q_bar dac_bridge_2
+* u5 q plot_v1
+* u6 q_bar plot_v1
+* u2 rst plot_v1
+* u3 trig plot_v1
+x1 net-_u1-pad3_ net-_u7-pad2_ net-_u1-pad4_ net-_u4-pad1_ net-_u4-pad2_ net-_r1-pad1_ gnd net-_c1-pad1_ net-_u8-pad2_ net-_u7-pad2_ CD4098
+* u7 net-_u7-pad1_ net-_u7-pad2_ adc_bridge_1
+v3 net-_u7-pad1_ gnd dc 5
+* u8 net-_c1-pad2_ net-_u8-pad2_ adc_bridge_1
+r2 net-_c1-pad2_ net-_c1-pad1_ 1k
+v4 net-_r1-pad1_ gnd dc 0
+a1 [trig rst ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
+a2 [net-_u4-pad1_ net-_u4-pad2_ ] [q q_bar ] u4
+a3 [net-_u7-pad1_ ] [net-_u7-pad2_ ] u7
+a4 [net-_c1-pad2_ ] [net-_u8-pad2_ ] u8
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u8 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 1e-00 3e-00 0e-00
+.ic V(q)=0
+.ic V(q_bar)=5
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(q)+6 v(q_bar)+12v(rst)+18 v(trig)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.pro b/library/SubcircuitLibrary/CD4098/CD4098_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.proj b/library/SubcircuitLibrary/CD4098/CD4098_test.proj
new file mode 100644
index 000000000..7a80cae0d
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.proj
@@ -0,0 +1 @@
+schematicFile CD4098_test.sch
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test.sch b/library/SubcircuitLibrary/CD4098/CD4098_test.sch
new file mode 100644
index 000000000..d76034731
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test.sch
@@ -0,0 +1,405 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD4098_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_GND #PWR01
+U 1 1 685A92A1
+P 15750 4950
+F 0 "#PWR01" H 15750 4700 50 0001 C CNN
+F 1 "eSim_GND" H 15750 4800 50 0000 C CNN
+F 2 "" H 15750 4950 50 0001 C CNN
+F 3 "" H 15750 4950 50 0001 C CNN
+ 1 15750 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_2 U1
+U 1 1 685A92F3
+P 13450 4850
+F 0 "U1" H 13450 4850 60 0000 C CNN
+F 1 "adc_bridge_2" H 13450 5000 60 0000 C CNN
+F 2 "" H 13450 4850 60 0000 C CNN
+F 3 "" H 13450 4850 60 0000 C CNN
+ 1 13450 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v1
+U 1 1 685A932B
+P 12650 5250
+F 0 "v1" H 12450 5350 60 0000 C CNN
+F 1 "pulse" H 12450 5200 60 0000 C CNN
+F 2 "R1" H 12350 5250 60 0000 C CNN
+F 3 "" H 12650 5250 60 0000 C CNN
+ 1 12650 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v2
+U 1 1 685A936D
+P 12850 5500
+F 0 "v2" H 12650 5600 60 0000 C CNN
+F 1 "pulse" H 12650 5450 60 0000 C CNN
+F 2 "R1" H 12550 5500 60 0000 C CNN
+F 3 "" H 12850 5500 60 0000 C CNN
+ 1 12850 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 685A93B8
+P 12850 6050
+F 0 "#PWR02" H 12850 5800 50 0001 C CNN
+F 1 "eSim_GND" H 12850 5900 50 0000 C CNN
+F 2 "" H 12850 6050 50 0001 C CNN
+F 3 "" H 12850 6050 50 0001 C CNN
+ 1 12850 6050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 685A93D2
+P 12650 5800
+F 0 "#PWR03" H 12650 5550 50 0001 C CNN
+F 1 "eSim_GND" H 12650 5650 50 0000 C CNN
+F 2 "" H 12650 5800 50 0001 C CNN
+F 3 "" H 12650 5800 50 0001 C CNN
+ 1 12650 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor_polarised C1
+U 1 1 685A958F
+P 15300 5800
+F 0 "C1" H 15325 5900 50 0000 L CNN
+F 1 "1u" H 15325 5700 50 0000 L CNN
+F 2 "" H 15300 5800 50 0001 C CNN
+F 3 "" H 15300 5800 50 0001 C CNN
+ 1 15300 5800
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R1
+U 1 1 685A9605
+P 13650 5850
+F 0 "R1" H 13700 5980 50 0000 C CNN
+F 1 "5k" H 13700 5800 50 0000 C CNN
+F 2 "" H 13700 5830 30 0000 C CNN
+F 3 "" V 13700 5900 30 0000 C CNN
+ 1 13650 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_2 U4
+U 1 1 685A97A9
+P 16250 4550
+F 0 "U4" H 16250 4550 60 0000 C CNN
+F 1 "dac_bridge_2" H 16300 4700 60 0000 C CNN
+F 2 "" H 16250 4550 60 0000 C CNN
+F 3 "" H 16250 4550 60 0000 C CNN
+ 1 16250 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 685A9823
+P 16950 4600
+F 0 "U5" H 16950 5100 60 0000 C CNN
+F 1 "plot_v1" H 17150 4950 60 0000 C CNN
+F 2 "" H 16950 4600 60 0000 C CNN
+F 3 "" H 16950 4600 60 0000 C CNN
+ 1 16950 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 685A9863
+P 17250 4700
+F 0 "U6" H 17250 5200 60 0000 C CNN
+F 1 "plot_v1" H 17450 5050 60 0000 C CNN
+F 2 "" H 17250 4700 60 0000 C CNN
+F 3 "" H 17250 4700 60 0000 C CNN
+ 1 17250 4700
+ 1 0 0 -1
+$EndComp
+Text GLabel 16850 4350 0 60 Input ~ 0
+Q
+Text GLabel 17150 4750 0 60 Input ~ 0
+Q_bar
+$Comp
+L plot_v1 U2
+U 1 1 685A9C0F
+P 12100 5150
+F 0 "U2" H 12100 5650 60 0000 C CNN
+F 1 "plot_v1" H 12300 5500 60 0000 C CNN
+F 2 "" H 12100 5150 60 0000 C CNN
+F 3 "" H 12100 5150 60 0000 C CNN
+ 1 12100 5150
+ 1 0 0 -1
+$EndComp
+Text GLabel 12750 4750 0 60 Input ~ 0
+trig
+$Comp
+L plot_v1 U3
+U 1 1 685A9E86
+P 12800 4900
+F 0 "U3" H 12800 5400 60 0000 C CNN
+F 1 "plot_v1" H 13000 5250 60 0000 C CNN
+F 2 "" H 12800 4900 60 0000 C CNN
+F 3 "" H 12800 4900 60 0000 C CNN
+ 1 12800 4900
+ 1 0 0 -1
+$EndComp
+Text GLabel 12250 5100 0 60 Input ~ 0
+rst
+$Comp
+L mono x1
+U 1 1 685BC6FC
+P 14900 4800
+F 0 "x1" H 14900 4150 60 0000 C CNN
+F 1 "mono" H 14900 5450 60 0000 C CNN
+F 2 "" H 14900 5450 60 0001 C CNN
+F 3 "" H 14900 5450 60 0001 C CNN
+ 1 14900 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_1 U7
+U 1 1 685BC7A2
+P 17000 5350
+F 0 "U7" H 17000 5350 60 0000 C CNN
+F 1 "adc_bridge_1" H 17000 5500 60 0000 C CNN
+F 2 "" H 17000 5350 60 0000 C CNN
+F 3 "" H 17000 5350 60 0000 C CNN
+ 1 17000 5350
+ -1 0 0 -1
+$EndComp
+$Comp
+L DC v3
+U 1 1 685BC92B
+P 17800 5750
+F 0 "v3" H 17600 5850 60 0000 C CNN
+F 1 "DC" H 17600 5700 60 0000 C CNN
+F 2 "R1" H 17500 5750 60 0000 C CNN
+F 3 "" H 17800 5750 60 0000 C CNN
+ 1 17800 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR04
+U 1 1 685BC9BA
+P 17800 6300
+F 0 "#PWR04" H 17800 6050 50 0001 C CNN
+F 1 "eSim_GND" H 17800 6150 50 0000 C CNN
+F 2 "" H 17800 6300 50 0001 C CNN
+F 3 "" H 17800 6300 50 0001 C CNN
+ 1 17800 6300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 15650 4950 15750 4950
+Wire Wire Line
+ 14000 4900 14200 4900
+Wire Wire Line
+ 14000 4800 14000 4500
+Wire Wire Line
+ 14000 4500 14200 4500
+Wire Wire Line
+ 12650 4800 12850 4800
+Wire Wire Line
+ 12850 4900 12850 5050
+Wire Wire Line
+ 12650 5700 12650 5800
+Wire Wire Line
+ 12850 5950 12850 6050
+Wire Wire Line
+ 13850 5800 15150 5800
+Wire Wire Line
+ 15650 4500 15800 4500
+Wire Wire Line
+ 15650 4700 15650 4600
+Wire Wire Line
+ 15650 4600 15800 4600
+Wire Wire Line
+ 16800 4500 16950 4500
+Wire Wire Line
+ 16950 4500 16950 4400
+Wire Wire Line
+ 16800 4600 17250 4600
+Wire Wire Line
+ 17250 4600 17250 4500
+Wire Wire Line
+ 16850 4350 16850 4500
+Connection ~ 16850 4500
+Wire Wire Line
+ 17150 4750 17150 4600
+Connection ~ 17150 4600
+Wire Wire Line
+ 14150 5050 14150 5100
+Wire Wire Line
+ 13550 5100 14200 5100
+Wire Wire Line
+ 13550 5800 13550 5100
+Connection ~ 14150 5100
+Wire Wire Line
+ 15650 5150 16400 5150
+Wire Wire Line
+ 16400 5150 16400 5800
+Wire Wire Line
+ 16400 5800 15450 5800
+Wire Wire Line
+ 15650 5300 16450 5300
+Wire Wire Line
+ 17600 5300 17800 5300
+Wire Wire Line
+ 17800 6200 17800 6300
+Wire Wire Line
+ 14200 4700 14200 4800
+Wire Wire Line
+ 14200 4800 16100 4800
+Wire Wire Line
+ 16100 4800 16100 5300
+Connection ~ 16100 5300
+$Comp
+L adc_bridge_1 U8
+U 1 1 685BD0C1
+P 14250 6450
+F 0 "U8" H 14250 6450 60 0000 C CNN
+F 1 "adc_bridge_1" H 14250 6600 60 0000 C CNN
+F 2 "" H 14250 6450 60 0000 C CNN
+F 3 "" H 14250 6450 60 0000 C CNN
+ 1 14250 6450
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 14850 6400 14850 6050
+Wire Wire Line
+ 14850 6050 14350 6050
+Wire Wire Line
+ 14350 6050 14350 5800
+Connection ~ 14350 5800
+Wire Wire Line
+ 13700 6400 13700 6100
+Wire Wire Line
+ 13700 6100 14200 6100
+Wire Wire Line
+ 14200 6100 14200 5250
+$Comp
+L resistor R2
+U 1 1 685BDEEA
+P 15250 6100
+F 0 "R2" H 15300 6230 50 0000 C CNN
+F 1 "1k" H 15300 6050 50 0000 C CNN
+F 2 "" H 15300 6080 30 0000 C CNN
+F 3 "" V 15300 6150 30 0000 C CNN
+ 1 15250 6100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 15150 6050 15050 6050
+Wire Wire Line
+ 15050 6050 15050 5800
+Connection ~ 15050 5800
+Wire Wire Line
+ 15450 6050 15700 6050
+Wire Wire Line
+ 15700 6050 15700 5800
+Connection ~ 15700 5800
+$Comp
+L DC v4
+U 1 1 685D03C8
+P 13550 4050
+F 0 "v4" H 13350 4150 60 0000 C CNN
+F 1 "DC" H 13350 4000 60 0000 C CNN
+F 2 "R1" H 13250 4050 60 0000 C CNN
+F 3 "" H 13550 4050 60 0000 C CNN
+ 1 13550 4050
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 13550 4500 13900 4500
+Wire Wire Line
+ 13900 4500 13900 5050
+Wire Wire Line
+ 13900 5050 14150 5050
+$Comp
+L eSim_GND #PWR05
+U 1 1 685D0868
+P 13700 3600
+F 0 "#PWR05" H 13700 3350 50 0001 C CNN
+F 1 "eSim_GND" H 13700 3450 50 0000 C CNN
+F 2 "" H 13700 3600 50 0001 C CNN
+F 3 "" H 13700 3600 50 0001 C CNN
+ 1 13700 3600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 13550 3600 13700 3600
+Wire Wire Line
+ 12800 4700 12800 4800
+Connection ~ 12800 4800
+Wire Wire Line
+ 12750 4750 12800 4750
+Connection ~ 12800 4750
+Wire Wire Line
+ 12100 4950 12850 4950
+Connection ~ 12850 4950
+Wire Wire Line
+ 12250 5100 12250 4950
+Wire Wire Line
+ 12250 4950 12300 4950
+Connection ~ 12300 4950
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD4098/CD4098_test_Previous_Values.xml b/library/SubcircuitLibrary/CD4098/CD4098_test_Previous_Values.xml
new file mode 100644
index 000000000..ce4cec994
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/CD4098_test_Previous_Values.xml
@@ -0,0 +1 @@
+dc5pulse0520.1n0.1n0.1253pulse0510.1n0.1n0.33dc0adc_bridgedac_bridgeadc_bridgeadc_bridgeC:\FOSSEE\eSim\library\SubcircuitLibrary\CD4098truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes013secsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/NMOS-0.5um.lib b/library/SubcircuitLibrary/CD4098/NMOS-0.5um.lib
new file mode 100644
index 000000000..2e6f4635c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/NMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05
++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1
++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3
++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7
++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88
++ NSUB=1.40E17 )
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4098/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697
++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0
++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3
++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286
++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078
++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/CD4098/NMOS-5um.lib b/library/SubcircuitLibrary/CD4098/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/CD4098/PMOS-0.5um.lib b/library/SubcircuitLibrary/CD4098/PMOS-0.5um.lib
new file mode 100644
index 000000000..848e8b051
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/PMOS-0.5um.lib
@@ -0,0 +1,6 @@
+.model mos_p PMOS( TPG=-1 TOX=9.5n CJ=950u ETA=0.025 VMAX=0.3u
++ GAMMA=0.52 CGSO=0.35n LD=70n MJSW=0.25 PB=1
++ CGBO=0.45n XJ=0.2U CGDO=0.35n KAPPA=8.0 LEVEL=3
++ VTO=-0.6 NFS=6.50E11 THETA=0.2 CJSW=0.2n PHI=0.7
++ RSH=2.5 MJ=0.5 UO=130 KP=48u DELTA=0.25
++ NSUB=1.0E17 )
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD4098/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4098/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9
++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3
++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/CD4098/PMOS-5um.lib b/library/SubcircuitLibrary/CD4098/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/CD4098/analysis b/library/SubcircuitLibrary/CD4098/analysis
new file mode 100644
index 000000000..a2a273682
--- /dev/null
+++ b/library/SubcircuitLibrary/CD4098/analysis
@@ -0,0 +1 @@
+.tran 1e-00 3e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050-cache.lib b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050-cache.lib
new file mode 100644
index 000000000..5c77f56cc
--- /dev/null
+++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050-cache.lib
@@ -0,0 +1,72 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.bak b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.bak
new file mode 100644
index 000000000..4a38fca85
--- /dev/null
+++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.bak
@@ -0,0 +1,537 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD74HC4050-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_buffer U3
+U 1 1 685D658A
+P 4250 2750
+F 0 "U3" H 4250 2700 60 0000 C CNN
+F 1 "d_buffer" H 4250 2800 60 0000 C CNN
+F 2 "" H 4250 2750 60 0000 C CNN
+F 3 "" H 4250 2750 60 0000 C CNN
+ 1 4250 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U9
+U 1 1 685D658B
+P 7950 2750
+F 0 "U9" H 7950 2700 60 0000 C CNN
+F 1 "d_buffer" H 7950 2800 60 0000 C CNN
+F 2 "" H 7950 2750 60 0000 C CNN
+F 3 "" H 7950 2750 60 0000 C CNN
+ 1 7950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 685D658C
+P 5550 2750
+F 0 "U5" H 5550 2650 60 0000 C CNN
+F 1 "d_inverter" H 5550 2900 60 0000 C CNN
+F 2 "" H 5600 2700 60 0000 C CNN
+F 3 "" H 5600 2700 60 0000 C CNN
+ 1 5550 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 685D658D
+P 6600 2750
+F 0 "U6" H 6600 2650 60 0000 C CNN
+F 1 "d_inverter" H 6600 2900 60 0000 C CNN
+F 2 "" H 6650 2700 60 0000 C CNN
+F 3 "" H 6650 2700 60 0000 C CNN
+ 1 6600 2750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5850 2750 6300 2750
+Wire Wire Line
+ 6900 2750 7450 2750
+Wire Wire Line
+ 8600 2750 9200 2750
+Wire Wire Line
+ 4900 2750 5250 2750
+Wire Wire Line
+ 1500 2750 3750 2750
+$Comp
+L PORT U1
+U 3 1 685D658E
+P 1250 2750
+F 0 "U1" H 1300 2850 30 0000 C CNN
+F 1 "PORT" H 1250 2750 30 0000 C CNN
+F 2 "" H 1250 2750 60 0000 C CNN
+F 3 "" H 1250 2750 60 0000 C CNN
+ 3 1250 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685D658F
+P 9450 2750
+F 0 "U1" H 9500 2850 30 0000 C CNN
+F 1 "PORT" H 9450 2750 30 0000 C CNN
+F 2 "" H 9450 2750 60 0000 C CNN
+F 3 "" H 9450 2750 60 0000 C CNN
+ 2 9450 2750
+ -1 0 0 1
+$EndComp
+Text Label 2000 2750 0 60 ~ 0
+A1
+Text Label 9050 2750 0 60 ~ 0
+Y1
+$Comp
+L d_buffer U8
+U 1 1 685D720A
+P 6700 4500
+F 0 "U8" H 6700 4450 60 0000 C CNN
+F 1 "d_buffer" H 6700 4550 60 0000 C CNN
+F 2 "" H 6700 4500 60 0000 C CNN
+F 3 "" H 6700 4500 60 0000 C CNN
+ 1 6700 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U17
+U 1 1 685D7210
+P 10400 4500
+F 0 "U17" H 10400 4450 60 0000 C CNN
+F 1 "d_buffer" H 10400 4550 60 0000 C CNN
+F 2 "" H 10400 4500 60 0000 C CNN
+F 3 "" H 10400 4500 60 0000 C CNN
+ 1 10400 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 685D7216
+P 8000 4500
+F 0 "U10" H 8000 4400 60 0000 C CNN
+F 1 "d_inverter" H 8000 4650 60 0000 C CNN
+F 2 "" H 8050 4450 60 0000 C CNN
+F 3 "" H 8050 4450 60 0000 C CNN
+ 1 8000 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 685D721C
+P 9050 4500
+F 0 "U12" H 9050 4400 60 0000 C CNN
+F 1 "d_inverter" H 9050 4650 60 0000 C CNN
+F 2 "" H 9100 4450 60 0000 C CNN
+F 3 "" H 9100 4450 60 0000 C CNN
+ 1 9050 4500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8300 4500 8750 4500
+Wire Wire Line
+ 9350 4500 9900 4500
+Wire Wire Line
+ 11050 4500 11650 4500
+Wire Wire Line
+ 7350 4500 7700 4500
+Wire Wire Line
+ 5100 4500 6200 4500
+$Comp
+L PORT U1
+U 5 1 685D7227
+P 4850 4500
+F 0 "U1" H 4900 4600 30 0000 C CNN
+F 1 "PORT" H 4850 4500 30 0000 C CNN
+F 2 "" H 4850 4500 60 0000 C CNN
+F 3 "" H 4850 4500 60 0000 C CNN
+ 5 4850 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685D722D
+P 11900 4500
+F 0 "U1" H 11950 4600 30 0000 C CNN
+F 1 "PORT" H 11900 4500 30 0000 C CNN
+F 2 "" H 11900 4500 60 0000 C CNN
+F 3 "" H 11900 4500 60 0000 C CNN
+ 4 11900 4500
+ -1 0 0 1
+$EndComp
+Text Label 11500 4500 0 60 ~ 0
+2Y
+$Comp
+L d_buffer U11
+U 1 1 685D7573
+P 8000 6850
+F 0 "U11" H 8000 6800 60 0000 C CNN
+F 1 "d_buffer" H 8000 6900 60 0000 C CNN
+F 2 "" H 8000 6850 60 0000 C CNN
+F 3 "" H 8000 6850 60 0000 C CNN
+ 1 8000 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U19
+U 1 1 685D7579
+P 11700 6850
+F 0 "U19" H 11700 6800 60 0000 C CNN
+F 1 "d_buffer" H 11700 6900 60 0000 C CNN
+F 2 "" H 11700 6850 60 0000 C CNN
+F 3 "" H 11700 6850 60 0000 C CNN
+ 1 11700 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U15
+U 1 1 685D757F
+P 9300 6850
+F 0 "U15" H 9300 6750 60 0000 C CNN
+F 1 "d_inverter" H 9300 7000 60 0000 C CNN
+F 2 "" H 9350 6800 60 0000 C CNN
+F 3 "" H 9350 6800 60 0000 C CNN
+ 1 9300 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 685D7585
+P 10350 6850
+F 0 "U16" H 10350 6750 60 0000 C CNN
+F 1 "d_inverter" H 10350 7000 60 0000 C CNN
+F 2 "" H 10400 6800 60 0000 C CNN
+F 3 "" H 10400 6800 60 0000 C CNN
+ 1 10350 6850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9600 6850 10050 6850
+Wire Wire Line
+ 10650 6850 11200 6850
+Wire Wire Line
+ 12350 6850 12950 6850
+Wire Wire Line
+ 8650 6850 9000 6850
+Wire Wire Line
+ 6400 6850 7500 6850
+$Comp
+L PORT U1
+U 7 1 685D7590
+P 6150 6850
+F 0 "U1" H 6200 6950 30 0000 C CNN
+F 1 "PORT" H 6150 6850 30 0000 C CNN
+F 2 "" H 6150 6850 60 0000 C CNN
+F 3 "" H 6150 6850 60 0000 C CNN
+ 7 6150 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685D7596
+P 13200 6850
+F 0 "U1" H 13250 6950 30 0000 C CNN
+F 1 "PORT" H 13200 6850 30 0000 C CNN
+F 2 "" H 13200 6850 60 0000 C CNN
+F 3 "" H 13200 6850 60 0000 C CNN
+ 6 13200 6850
+ -1 0 0 1
+$EndComp
+Text Label 6950 6850 0 60 ~ 0
+3A
+Text Label 12800 6850 0 60 ~ 0
+3Y
+$Comp
+L d_buffer U18
+U 1 1 685D75AC
+P 10450 8600
+F 0 "U18" H 10450 8550 60 0000 C CNN
+F 1 "d_buffer" H 10450 8650 60 0000 C CNN
+F 2 "" H 10450 8600 60 0000 C CNN
+F 3 "" H 10450 8600 60 0000 C CNN
+ 1 10450 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U25
+U 1 1 685D75B2
+P 14150 8600
+F 0 "U25" H 14150 8550 60 0000 C CNN
+F 1 "d_buffer" H 14150 8650 60 0000 C CNN
+F 2 "" H 14150 8600 60 0000 C CNN
+F 3 "" H 14150 8600 60 0000 C CNN
+ 1 14150 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 685D75B8
+P 11750 8600
+F 0 "U21" H 11750 8500 60 0000 C CNN
+F 1 "d_inverter" H 11750 8750 60 0000 C CNN
+F 2 "" H 11800 8550 60 0000 C CNN
+F 3 "" H 11800 8550 60 0000 C CNN
+ 1 11750 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U22
+U 1 1 685D75BE
+P 12800 8600
+F 0 "U22" H 12800 8500 60 0000 C CNN
+F 1 "d_inverter" H 12800 8750 60 0000 C CNN
+F 2 "" H 12850 8550 60 0000 C CNN
+F 3 "" H 12850 8550 60 0000 C CNN
+ 1 12800 8600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 12050 8600 12500 8600
+Wire Wire Line
+ 13100 8600 13650 8600
+Wire Wire Line
+ 14800 8600 15400 8600
+Wire Wire Line
+ 11100 8600 11450 8600
+Wire Wire Line
+ 8850 8600 9950 8600
+$Comp
+L PORT U1
+U 9 1 685D75C9
+P 8600 8600
+F 0 "U1" H 8650 8700 30 0000 C CNN
+F 1 "PORT" H 8600 8600 30 0000 C CNN
+F 2 "" H 8600 8600 60 0000 C CNN
+F 3 "" H 8600 8600 60 0000 C CNN
+ 9 8600 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685D75CF
+P 15650 8600
+F 0 "U1" H 15700 8700 30 0000 C CNN
+F 1 "PORT" H 15650 8600 30 0000 C CNN
+F 2 "" H 15650 8600 60 0000 C CNN
+F 3 "" H 15650 8600 60 0000 C CNN
+ 10 15650 8600
+ -1 0 0 1
+$EndComp
+Text Label 9350 8600 0 60 ~ 0
+4A
+Text Label 15250 8600 0 60 ~ 0
+4Y
+$Comp
+L d_buffer U26
+U 1 1 685D7925
+P 14450 10600
+F 0 "U26" H 14450 10550 60 0000 C CNN
+F 1 "d_buffer" H 14450 10650 60 0000 C CNN
+F 2 "" H 14450 10600 60 0000 C CNN
+F 3 "" H 14450 10600 60 0000 C CNN
+ 1 14450 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U32
+U 1 1 685D792B
+P 18150 10600
+F 0 "U32" H 18150 10550 60 0000 C CNN
+F 1 "d_buffer" H 18150 10650 60 0000 C CNN
+F 2 "" H 18150 10600 60 0000 C CNN
+F 3 "" H 18150 10600 60 0000 C CNN
+ 1 18150 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U29
+U 1 1 685D7931
+P 15750 10600
+F 0 "U29" H 15750 10500 60 0000 C CNN
+F 1 "d_inverter" H 15750 10750 60 0000 C CNN
+F 2 "" H 15800 10550 60 0000 C CNN
+F 3 "" H 15800 10550 60 0000 C CNN
+ 1 15750 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U30
+U 1 1 685D7937
+P 16800 10600
+F 0 "U30" H 16800 10500 60 0000 C CNN
+F 1 "d_inverter" H 16800 10750 60 0000 C CNN
+F 2 "" H 16850 10550 60 0000 C CNN
+F 3 "" H 16850 10550 60 0000 C CNN
+ 1 16800 10600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 16050 10600 16500 10600
+Wire Wire Line
+ 17100 10600 17650 10600
+Wire Wire Line
+ 18800 10600 19400 10600
+Wire Wire Line
+ 15100 10600 15450 10600
+Wire Wire Line
+ 12850 10600 13950 10600
+$Comp
+L PORT U1
+U 11 1 685D7942
+P 12600 10600
+F 0 "U1" H 12650 10700 30 0000 C CNN
+F 1 "PORT" H 12600 10600 30 0000 C CNN
+F 2 "" H 12600 10600 60 0000 C CNN
+F 3 "" H 12600 10600 60 0000 C CNN
+ 11 12600 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685D7948
+P 19650 10600
+F 0 "U1" H 19700 10700 30 0000 C CNN
+F 1 "PORT" H 19650 10600 30 0000 C CNN
+F 2 "" H 19650 10600 60 0000 C CNN
+F 3 "" H 19650 10600 60 0000 C CNN
+ 12 19650 10600
+ -1 0 0 1
+$EndComp
+Text Label 13350 10600 0 60 ~ 0
+5A
+Text Label 19250 10600 0 60 ~ 0
+5Y
+$Comp
+L d_buffer U31
+U 1 1 685D795E
+P 16900 12350
+F 0 "U31" H 16900 12300 60 0000 C CNN
+F 1 "d_buffer" H 16900 12400 60 0000 C CNN
+F 2 "" H 16900 12350 60 0000 C CNN
+F 3 "" H 16900 12350 60 0000 C CNN
+ 1 16900 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U36
+U 1 1 685D7964
+P 20600 12350
+F 0 "U36" H 20600 12300 60 0000 C CNN
+F 1 "d_buffer" H 20600 12400 60 0000 C CNN
+F 2 "" H 20600 12350 60 0000 C CNN
+F 3 "" H 20600 12350 60 0000 C CNN
+ 1 20600 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U33
+U 1 1 685D796A
+P 18200 12350
+F 0 "U33" H 18200 12250 60 0000 C CNN
+F 1 "d_inverter" H 18200 12500 60 0000 C CNN
+F 2 "" H 18250 12300 60 0000 C CNN
+F 3 "" H 18250 12300 60 0000 C CNN
+ 1 18200 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U34
+U 1 1 685D7970
+P 19250 12350
+F 0 "U34" H 19250 12250 60 0000 C CNN
+F 1 "d_inverter" H 19250 12500 60 0000 C CNN
+F 2 "" H 19300 12300 60 0000 C CNN
+F 3 "" H 19300 12300 60 0000 C CNN
+ 1 19250 12350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 18500 12350 18950 12350
+Wire Wire Line
+ 19550 12350 20100 12350
+Wire Wire Line
+ 21250 12350 21850 12350
+Wire Wire Line
+ 17550 12350 17900 12350
+Wire Wire Line
+ 15300 12350 16400 12350
+$Comp
+L PORT U1
+U 14 1 685D797B
+P 15050 12350
+F 0 "U1" H 15100 12450 30 0000 C CNN
+F 1 "PORT" H 15050 12350 30 0000 C CNN
+F 2 "" H 15050 12350 60 0000 C CNN
+F 3 "" H 15050 12350 60 0000 C CNN
+ 14 15050 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 685D7981
+P 22100 12350
+F 0 "U1" H 22150 12450 30 0000 C CNN
+F 1 "PORT" H 22100 12350 30 0000 C CNN
+F 2 "" H 22100 12350 60 0000 C CNN
+F 3 "" H 22100 12350 60 0000 C CNN
+ 15 22100 12350
+ -1 0 0 1
+$EndComp
+Text Label 15800 12350 0 60 ~ 0
+6A
+Text Label 21700 12350 0 60 ~ 0
+6Y
+Text Label 5600 4500 0 60 ~ 0
+2A
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir
new file mode 100644
index 000000000..e8541409d
--- /dev/null
+++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir
@@ -0,0 +1,35 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD74HC4050\CD74HC4050.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/27/25 16:18:46
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 /A1 Net-_U3-Pad2_ d_buffer
+U9 Net-_U6-Pad2_ /Y1 d_buffer
+U5 Net-_U3-Pad2_ Net-_U5-Pad2_ d_inverter
+U6 Net-_U5-Pad2_ Net-_U6-Pad2_ d_inverter
+U1 /Y1 /A1 /2Y /2A /3Y /3A /4A /4Y /5A /5Y /6A /6Y PORT
+U8 /2A Net-_U10-Pad1_ d_buffer
+U17 Net-_U12-Pad2_ /2Y d_buffer
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U12 Net-_U10-Pad2_ Net-_U12-Pad2_ d_inverter
+U11 /3A Net-_U11-Pad2_ d_buffer
+U19 Net-_U16-Pad2_ /3Y d_buffer
+U15 Net-_U11-Pad2_ Net-_U15-Pad2_ d_inverter
+U16 Net-_U15-Pad2_ Net-_U16-Pad2_ d_inverter
+U18 /4A Net-_U18-Pad2_ d_buffer
+U25 Net-_U22-Pad2_ /4Y d_buffer
+U21 Net-_U18-Pad2_ Net-_U21-Pad2_ d_inverter
+U22 Net-_U21-Pad2_ Net-_U22-Pad2_ d_inverter
+U26 /5A Net-_U26-Pad2_ d_buffer
+U32 Net-_U30-Pad2_ /5Y d_buffer
+U29 Net-_U26-Pad2_ Net-_U29-Pad2_ d_inverter
+U30 Net-_U29-Pad2_ Net-_U30-Pad2_ d_inverter
+U31 /6A Net-_U31-Pad2_ d_buffer
+U36 Net-_U34-Pad2_ /6Y d_buffer
+U33 Net-_U31-Pad2_ Net-_U33-Pad2_ d_inverter
+U34 Net-_U33-Pad2_ Net-_U34-Pad2_ d_inverter
+
+.end
diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir.out b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir.out
new file mode 100644
index 000000000..dcab5954f
--- /dev/null
+++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.cir.out
@@ -0,0 +1,108 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd74hc4050\cd74hc4050.cir
+
+* u3 /a1 net-_u3-pad2_ d_buffer
+* u9 net-_u6-pad2_ /y1 d_buffer
+* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter
+* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter
+* u1 /y1 /a1 /2y /2a /3y /3a /4a /4y /5a /5y /6a /6y port
+* u8 /2a net-_u10-pad1_ d_buffer
+* u17 net-_u12-pad2_ /2y d_buffer
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u12 net-_u10-pad2_ net-_u12-pad2_ d_inverter
+* u11 /3a net-_u11-pad2_ d_buffer
+* u19 net-_u16-pad2_ /3y d_buffer
+* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter
+* u16 net-_u15-pad2_ net-_u16-pad2_ d_inverter
+* u18 /4a net-_u18-pad2_ d_buffer
+* u25 net-_u22-pad2_ /4y d_buffer
+* u21 net-_u18-pad2_ net-_u21-pad2_ d_inverter
+* u22 net-_u21-pad2_ net-_u22-pad2_ d_inverter
+* u26 /5a net-_u26-pad2_ d_buffer
+* u32 net-_u30-pad2_ /5y d_buffer
+* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter
+* u30 net-_u29-pad2_ net-_u30-pad2_ d_inverter
+* u31 /6a net-_u31-pad2_ d_buffer
+* u36 net-_u34-pad2_ /6y d_buffer
+* u33 net-_u31-pad2_ net-_u33-pad2_ d_inverter
+* u34 net-_u33-pad2_ net-_u34-pad2_ d_inverter
+a1 /a1 net-_u3-pad2_ u3
+a2 net-_u6-pad2_ /y1 u9
+a3 net-_u3-pad2_ net-_u5-pad2_ u5
+a4 net-_u5-pad2_ net-_u6-pad2_ u6
+a5 /2a net-_u10-pad1_ u8
+a6 net-_u12-pad2_ /2y u17
+a7 net-_u10-pad1_ net-_u10-pad2_ u10
+a8 net-_u10-pad2_ net-_u12-pad2_ u12
+a9 /3a net-_u11-pad2_ u11
+a10 net-_u16-pad2_ /3y u19
+a11 net-_u11-pad2_ net-_u15-pad2_ u15
+a12 net-_u15-pad2_ net-_u16-pad2_ u16
+a13 /4a net-_u18-pad2_ u18
+a14 net-_u22-pad2_ /4y u25
+a15 net-_u18-pad2_ net-_u21-pad2_ u21
+a16 net-_u21-pad2_ net-_u22-pad2_ u22
+a17 /5a net-_u26-pad2_ u26
+a18 net-_u30-pad2_ /5y u32
+a19 net-_u26-pad2_ net-_u29-pad2_ u29
+a20 net-_u29-pad2_ net-_u30-pad2_ u30
+a21 /6a net-_u31-pad2_ u31
+a22 net-_u34-pad2_ /6y u36
+a23 net-_u31-pad2_ net-_u33-pad2_ u33
+a24 net-_u33-pad2_ net-_u34-pad2_ u34
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u8 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u25 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.pro b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sch b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sch
new file mode 100644
index 000000000..6c8d82654
--- /dev/null
+++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sch
@@ -0,0 +1,537 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CD74HC4050-cache
+EELAYER 25 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_buffer U3
+U 1 1 685D658A
+P 4250 2750
+F 0 "U3" H 4250 2700 60 0000 C CNN
+F 1 "d_buffer" H 4250 2800 60 0000 C CNN
+F 2 "" H 4250 2750 60 0000 C CNN
+F 3 "" H 4250 2750 60 0000 C CNN
+ 1 4250 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U9
+U 1 1 685D658B
+P 7950 2750
+F 0 "U9" H 7950 2700 60 0000 C CNN
+F 1 "d_buffer" H 7950 2800 60 0000 C CNN
+F 2 "" H 7950 2750 60 0000 C CNN
+F 3 "" H 7950 2750 60 0000 C CNN
+ 1 7950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 685D658C
+P 5550 2750
+F 0 "U5" H 5550 2650 60 0000 C CNN
+F 1 "d_inverter" H 5550 2900 60 0000 C CNN
+F 2 "" H 5600 2700 60 0000 C CNN
+F 3 "" H 5600 2700 60 0000 C CNN
+ 1 5550 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 685D658D
+P 6600 2750
+F 0 "U6" H 6600 2650 60 0000 C CNN
+F 1 "d_inverter" H 6600 2900 60 0000 C CNN
+F 2 "" H 6650 2700 60 0000 C CNN
+F 3 "" H 6650 2700 60 0000 C CNN
+ 1 6600 2750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5850 2750 6300 2750
+Wire Wire Line
+ 6900 2750 7450 2750
+Wire Wire Line
+ 8600 2750 9200 2750
+Wire Wire Line
+ 4900 2750 5250 2750
+Wire Wire Line
+ 1500 2750 3750 2750
+$Comp
+L PORT U1
+U 3 1 685D658E
+P 1250 2750
+F 0 "U1" H 1300 2850 30 0000 C CNN
+F 1 "PORT" H 1250 2750 30 0000 C CNN
+F 2 "" H 1250 2750 60 0000 C CNN
+F 3 "" H 1250 2750 60 0000 C CNN
+ 3 1250 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685D658F
+P 9450 2750
+F 0 "U1" H 9500 2850 30 0000 C CNN
+F 1 "PORT" H 9450 2750 30 0000 C CNN
+F 2 "" H 9450 2750 60 0000 C CNN
+F 3 "" H 9450 2750 60 0000 C CNN
+ 2 9450 2750
+ -1 0 0 1
+$EndComp
+Text Label 2000 2750 0 60 ~ 0
+A1
+Text Label 9050 2750 0 60 ~ 0
+Y1
+$Comp
+L d_buffer U8
+U 1 1 685D720A
+P 6700 4500
+F 0 "U8" H 6700 4450 60 0000 C CNN
+F 1 "d_buffer" H 6700 4550 60 0000 C CNN
+F 2 "" H 6700 4500 60 0000 C CNN
+F 3 "" H 6700 4500 60 0000 C CNN
+ 1 6700 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U17
+U 1 1 685D7210
+P 10400 4500
+F 0 "U17" H 10400 4450 60 0000 C CNN
+F 1 "d_buffer" H 10400 4550 60 0000 C CNN
+F 2 "" H 10400 4500 60 0000 C CNN
+F 3 "" H 10400 4500 60 0000 C CNN
+ 1 10400 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 685D7216
+P 8000 4500
+F 0 "U10" H 8000 4400 60 0000 C CNN
+F 1 "d_inverter" H 8000 4650 60 0000 C CNN
+F 2 "" H 8050 4450 60 0000 C CNN
+F 3 "" H 8050 4450 60 0000 C CNN
+ 1 8000 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 685D721C
+P 9050 4500
+F 0 "U12" H 9050 4400 60 0000 C CNN
+F 1 "d_inverter" H 9050 4650 60 0000 C CNN
+F 2 "" H 9100 4450 60 0000 C CNN
+F 3 "" H 9100 4450 60 0000 C CNN
+ 1 9050 4500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8300 4500 8750 4500
+Wire Wire Line
+ 9350 4500 9900 4500
+Wire Wire Line
+ 11050 4500 11650 4500
+Wire Wire Line
+ 7350 4500 7700 4500
+Wire Wire Line
+ 5100 4500 6200 4500
+$Comp
+L PORT U1
+U 5 1 685D7227
+P 4850 4500
+F 0 "U1" H 4900 4600 30 0000 C CNN
+F 1 "PORT" H 4850 4500 30 0000 C CNN
+F 2 "" H 4850 4500 60 0000 C CNN
+F 3 "" H 4850 4500 60 0000 C CNN
+ 5 4850 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685D722D
+P 11900 4500
+F 0 "U1" H 11950 4600 30 0000 C CNN
+F 1 "PORT" H 11900 4500 30 0000 C CNN
+F 2 "" H 11900 4500 60 0000 C CNN
+F 3 "" H 11900 4500 60 0000 C CNN
+ 4 11900 4500
+ -1 0 0 1
+$EndComp
+Text Label 11500 4500 0 60 ~ 0
+2Y
+$Comp
+L d_buffer U11
+U 1 1 685D7573
+P 8000 6850
+F 0 "U11" H 8000 6800 60 0000 C CNN
+F 1 "d_buffer" H 8000 6900 60 0000 C CNN
+F 2 "" H 8000 6850 60 0000 C CNN
+F 3 "" H 8000 6850 60 0000 C CNN
+ 1 8000 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U19
+U 1 1 685D7579
+P 11700 6850
+F 0 "U19" H 11700 6800 60 0000 C CNN
+F 1 "d_buffer" H 11700 6900 60 0000 C CNN
+F 2 "" H 11700 6850 60 0000 C CNN
+F 3 "" H 11700 6850 60 0000 C CNN
+ 1 11700 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U15
+U 1 1 685D757F
+P 9300 6850
+F 0 "U15" H 9300 6750 60 0000 C CNN
+F 1 "d_inverter" H 9300 7000 60 0000 C CNN
+F 2 "" H 9350 6800 60 0000 C CNN
+F 3 "" H 9350 6800 60 0000 C CNN
+ 1 9300 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 685D7585
+P 10350 6850
+F 0 "U16" H 10350 6750 60 0000 C CNN
+F 1 "d_inverter" H 10350 7000 60 0000 C CNN
+F 2 "" H 10400 6800 60 0000 C CNN
+F 3 "" H 10400 6800 60 0000 C CNN
+ 1 10350 6850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9600 6850 10050 6850
+Wire Wire Line
+ 10650 6850 11200 6850
+Wire Wire Line
+ 12350 6850 12950 6850
+Wire Wire Line
+ 8650 6850 9000 6850
+Wire Wire Line
+ 6400 6850 7500 6850
+$Comp
+L PORT U1
+U 7 1 685D7590
+P 6150 6850
+F 0 "U1" H 6200 6950 30 0000 C CNN
+F 1 "PORT" H 6150 6850 30 0000 C CNN
+F 2 "" H 6150 6850 60 0000 C CNN
+F 3 "" H 6150 6850 60 0000 C CNN
+ 7 6150 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685D7596
+P 13200 6850
+F 0 "U1" H 13250 6950 30 0000 C CNN
+F 1 "PORT" H 13200 6850 30 0000 C CNN
+F 2 "" H 13200 6850 60 0000 C CNN
+F 3 "" H 13200 6850 60 0000 C CNN
+ 6 13200 6850
+ -1 0 0 1
+$EndComp
+Text Label 6950 6850 0 60 ~ 0
+3A
+Text Label 12800 6850 0 60 ~ 0
+3Y
+$Comp
+L d_buffer U18
+U 1 1 685D75AC
+P 10450 8600
+F 0 "U18" H 10450 8550 60 0000 C CNN
+F 1 "d_buffer" H 10450 8650 60 0000 C CNN
+F 2 "" H 10450 8600 60 0000 C CNN
+F 3 "" H 10450 8600 60 0000 C CNN
+ 1 10450 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U25
+U 1 1 685D75B2
+P 14150 8600
+F 0 "U25" H 14150 8550 60 0000 C CNN
+F 1 "d_buffer" H 14150 8650 60 0000 C CNN
+F 2 "" H 14150 8600 60 0000 C CNN
+F 3 "" H 14150 8600 60 0000 C CNN
+ 1 14150 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 685D75B8
+P 11750 8600
+F 0 "U21" H 11750 8500 60 0000 C CNN
+F 1 "d_inverter" H 11750 8750 60 0000 C CNN
+F 2 "" H 11800 8550 60 0000 C CNN
+F 3 "" H 11800 8550 60 0000 C CNN
+ 1 11750 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U22
+U 1 1 685D75BE
+P 12800 8600
+F 0 "U22" H 12800 8500 60 0000 C CNN
+F 1 "d_inverter" H 12800 8750 60 0000 C CNN
+F 2 "" H 12850 8550 60 0000 C CNN
+F 3 "" H 12850 8550 60 0000 C CNN
+ 1 12800 8600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 12050 8600 12500 8600
+Wire Wire Line
+ 13100 8600 13650 8600
+Wire Wire Line
+ 14800 8600 15400 8600
+Wire Wire Line
+ 11100 8600 11450 8600
+Wire Wire Line
+ 8850 8600 9950 8600
+$Comp
+L PORT U1
+U 9 1 685D75C9
+P 8600 8600
+F 0 "U1" H 8650 8700 30 0000 C CNN
+F 1 "PORT" H 8600 8600 30 0000 C CNN
+F 2 "" H 8600 8600 60 0000 C CNN
+F 3 "" H 8600 8600 60 0000 C CNN
+ 9 8600 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685D75CF
+P 15650 8600
+F 0 "U1" H 15700 8700 30 0000 C CNN
+F 1 "PORT" H 15650 8600 30 0000 C CNN
+F 2 "" H 15650 8600 60 0000 C CNN
+F 3 "" H 15650 8600 60 0000 C CNN
+ 10 15650 8600
+ -1 0 0 1
+$EndComp
+Text Label 9350 8600 0 60 ~ 0
+4A
+Text Label 15250 8600 0 60 ~ 0
+4Y
+$Comp
+L d_buffer U26
+U 1 1 685D7925
+P 14450 10600
+F 0 "U26" H 14450 10550 60 0000 C CNN
+F 1 "d_buffer" H 14450 10650 60 0000 C CNN
+F 2 "" H 14450 10600 60 0000 C CNN
+F 3 "" H 14450 10600 60 0000 C CNN
+ 1 14450 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U32
+U 1 1 685D792B
+P 18150 10600
+F 0 "U32" H 18150 10550 60 0000 C CNN
+F 1 "d_buffer" H 18150 10650 60 0000 C CNN
+F 2 "" H 18150 10600 60 0000 C CNN
+F 3 "" H 18150 10600 60 0000 C CNN
+ 1 18150 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U29
+U 1 1 685D7931
+P 15750 10600
+F 0 "U29" H 15750 10500 60 0000 C CNN
+F 1 "d_inverter" H 15750 10750 60 0000 C CNN
+F 2 "" H 15800 10550 60 0000 C CNN
+F 3 "" H 15800 10550 60 0000 C CNN
+ 1 15750 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U30
+U 1 1 685D7937
+P 16800 10600
+F 0 "U30" H 16800 10500 60 0000 C CNN
+F 1 "d_inverter" H 16800 10750 60 0000 C CNN
+F 2 "" H 16850 10550 60 0000 C CNN
+F 3 "" H 16850 10550 60 0000 C CNN
+ 1 16800 10600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 16050 10600 16500 10600
+Wire Wire Line
+ 17100 10600 17650 10600
+Wire Wire Line
+ 18800 10600 19400 10600
+Wire Wire Line
+ 15100 10600 15450 10600
+Wire Wire Line
+ 12850 10600 13950 10600
+$Comp
+L PORT U1
+U 11 1 685D7942
+P 12600 10600
+F 0 "U1" H 12650 10700 30 0000 C CNN
+F 1 "PORT" H 12600 10600 30 0000 C CNN
+F 2 "" H 12600 10600 60 0000 C CNN
+F 3 "" H 12600 10600 60 0000 C CNN
+ 11 12600 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685D7948
+P 19650 10600
+F 0 "U1" H 19700 10700 30 0000 C CNN
+F 1 "PORT" H 19650 10600 30 0000 C CNN
+F 2 "" H 19650 10600 60 0000 C CNN
+F 3 "" H 19650 10600 60 0000 C CNN
+ 12 19650 10600
+ -1 0 0 1
+$EndComp
+Text Label 13350 10600 0 60 ~ 0
+5A
+Text Label 19250 10600 0 60 ~ 0
+5Y
+$Comp
+L d_buffer U31
+U 1 1 685D795E
+P 16900 12350
+F 0 "U31" H 16900 12300 60 0000 C CNN
+F 1 "d_buffer" H 16900 12400 60 0000 C CNN
+F 2 "" H 16900 12350 60 0000 C CNN
+F 3 "" H 16900 12350 60 0000 C CNN
+ 1 16900 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U36
+U 1 1 685D7964
+P 20600 12350
+F 0 "U36" H 20600 12300 60 0000 C CNN
+F 1 "d_buffer" H 20600 12400 60 0000 C CNN
+F 2 "" H 20600 12350 60 0000 C CNN
+F 3 "" H 20600 12350 60 0000 C CNN
+ 1 20600 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U33
+U 1 1 685D796A
+P 18200 12350
+F 0 "U33" H 18200 12250 60 0000 C CNN
+F 1 "d_inverter" H 18200 12500 60 0000 C CNN
+F 2 "" H 18250 12300 60 0000 C CNN
+F 3 "" H 18250 12300 60 0000 C CNN
+ 1 18200 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U34
+U 1 1 685D7970
+P 19250 12350
+F 0 "U34" H 19250 12250 60 0000 C CNN
+F 1 "d_inverter" H 19250 12500 60 0000 C CNN
+F 2 "" H 19300 12300 60 0000 C CNN
+F 3 "" H 19300 12300 60 0000 C CNN
+ 1 19250 12350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 18500 12350 18950 12350
+Wire Wire Line
+ 19550 12350 20100 12350
+Wire Wire Line
+ 21250 12350 21850 12350
+Wire Wire Line
+ 17550 12350 17900 12350
+Wire Wire Line
+ 15300 12350 16400 12350
+$Comp
+L PORT U1
+U 14 1 685D797B
+P 15050 12350
+F 0 "U1" H 15100 12450 30 0000 C CNN
+F 1 "PORT" H 15050 12350 30 0000 C CNN
+F 2 "" H 15050 12350 60 0000 C CNN
+F 3 "" H 15050 12350 60 0000 C CNN
+ 14 15050 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 685D7981
+P 22100 12350
+F 0 "U1" H 22150 12450 30 0000 C CNN
+F 1 "PORT" H 22100 12350 30 0000 C CNN
+F 2 "" H 22100 12350 60 0000 C CNN
+F 3 "" H 22100 12350 60 0000 C CNN
+ 15 22100 12350
+ -1 0 0 1
+$EndComp
+Text Label 15800 12350 0 60 ~ 0
+6A
+Text Label 21700 12350 0 60 ~ 0
+6Y
+Text Label 5600 4500 0 60 ~ 0
+2A
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sub b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sub
new file mode 100644
index 000000000..421154d93
--- /dev/null
+++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050.sub
@@ -0,0 +1,102 @@
+* Subcircuit CD74HC4050
+.subckt CD74HC4050 /y1 /a1 /2y /2a /3y /3a /4a /4y /5a /5y /6a /6y
+* c:\fossee\esim\library\subcircuitlibrary\cd74hc4050\cd74hc4050.cir
+* u3 /a1 net-_u3-pad2_ d_buffer
+* u9 net-_u6-pad2_ /y1 d_buffer
+* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter
+* u6 net-_u5-pad2_ net-_u6-pad2_ d_inverter
+* u8 /2a net-_u10-pad1_ d_buffer
+* u17 net-_u12-pad2_ /2y d_buffer
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u12 net-_u10-pad2_ net-_u12-pad2_ d_inverter
+* u11 /3a net-_u11-pad2_ d_buffer
+* u19 net-_u16-pad2_ /3y d_buffer
+* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter
+* u16 net-_u15-pad2_ net-_u16-pad2_ d_inverter
+* u18 /4a net-_u18-pad2_ d_buffer
+* u25 net-_u22-pad2_ /4y d_buffer
+* u21 net-_u18-pad2_ net-_u21-pad2_ d_inverter
+* u22 net-_u21-pad2_ net-_u22-pad2_ d_inverter
+* u26 /5a net-_u26-pad2_ d_buffer
+* u32 net-_u30-pad2_ /5y d_buffer
+* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter
+* u30 net-_u29-pad2_ net-_u30-pad2_ d_inverter
+* u31 /6a net-_u31-pad2_ d_buffer
+* u36 net-_u34-pad2_ /6y d_buffer
+* u33 net-_u31-pad2_ net-_u33-pad2_ d_inverter
+* u34 net-_u33-pad2_ net-_u34-pad2_ d_inverter
+a1 /a1 net-_u3-pad2_ u3
+a2 net-_u6-pad2_ /y1 u9
+a3 net-_u3-pad2_ net-_u5-pad2_ u5
+a4 net-_u5-pad2_ net-_u6-pad2_ u6
+a5 /2a net-_u10-pad1_ u8
+a6 net-_u12-pad2_ /2y u17
+a7 net-_u10-pad1_ net-_u10-pad2_ u10
+a8 net-_u10-pad2_ net-_u12-pad2_ u12
+a9 /3a net-_u11-pad2_ u11
+a10 net-_u16-pad2_ /3y u19
+a11 net-_u11-pad2_ net-_u15-pad2_ u15
+a12 net-_u15-pad2_ net-_u16-pad2_ u16
+a13 /4a net-_u18-pad2_ u18
+a14 net-_u22-pad2_ /4y u25
+a15 net-_u18-pad2_ net-_u21-pad2_ u21
+a16 net-_u21-pad2_ net-_u22-pad2_ u22
+a17 /5a net-_u26-pad2_ u26
+a18 net-_u30-pad2_ /5y u32
+a19 net-_u26-pad2_ net-_u29-pad2_ u29
+a20 net-_u29-pad2_ net-_u30-pad2_ u30
+a21 /6a net-_u31-pad2_ u31
+a22 net-_u34-pad2_ /6y u36
+a23 net-_u31-pad2_ net-_u33-pad2_ u33
+a24 net-_u33-pad2_ net-_u34-pad2_ u34
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u9 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u8 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u19 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u18 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u25 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u31 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u36 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends CD74HC4050
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD74HC4050/CD74HC4050_Previous_Values.xml b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050_Previous_Values.xml
new file mode 100644
index 000000000..5a2aa2f5c
--- /dev/null
+++ b/library/SubcircuitLibrary/CD74HC4050/CD74HC4050_Previous_Values.xml
@@ -0,0 +1 @@
+dc5d_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridged_bufferd_bufferd_inverterd_inverteradc_bridgedac_bridgetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/CD74HC4050/analysis b/library/SubcircuitLibrary/CD74HC4050/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/CD74HC4050/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and-cache.lib b/library/SubcircuitLibrary/DSR_LATCH/3_and-cache.lib
new file mode 100644
index 000000000..0a3ccf7f9
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.cir b/library/SubcircuitLibrary/DSR_LATCH/3_and.cir
new file mode 100644
index 000000000..15f8954df
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.cir.out b/library/SubcircuitLibrary/DSR_LATCH/3_and.cir.out
new file mode 100644
index 000000000..e3c966454
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.pro b/library/SubcircuitLibrary/DSR_LATCH/3_and.pro
new file mode 100644
index 000000000..a4cdec482
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.sch b/library/SubcircuitLibrary/DSR_LATCH/3_and.sch
new file mode 100644
index 000000000..c853bf49d
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and.sub b/library/SubcircuitLibrary/DSR_LATCH/3_and.sub
new file mode 100644
index 000000000..b949ae4fb
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/DSR_LATCH/3_and_Previous_Values.xml b/library/SubcircuitLibrary/DSR_LATCH/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH-cache.lib b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH-cache.lib
new file mode 100644
index 000000000..c7697d09b
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH-cache.lib
@@ -0,0 +1,143 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.bak b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.bak
new file mode 100644
index 000000000..a586761a6
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.bak
@@ -0,0 +1,1143 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DSR_LATCH-cache
+EELAYER 25 0
+EELAYER END
+$Descr A0 46811 33110
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_buffer U3
+U 1 1 68501ACE
+P 7800 12400
+F 0 "U3" H 7800 12350 60 0000 C CNN
+F 1 "d_buffer" H 7800 12450 60 0000 C CNN
+F 2 "" H 7800 12400 60 0000 C CNN
+F 3 "" H 7800 12400 60 0000 C CNN
+ 1 7800 12400
+ 0 1 1 0
+$EndComp
+$Comp
+L d_buffer U5
+U 1 1 68501B69
+P 9350 12350
+F 0 "U5" H 9350 12300 60 0000 C CNN
+F 1 "d_buffer" H 9350 12400 60 0000 C CNN
+F 2 "" H 9350 12350 60 0000 C CNN
+F 3 "" H 9350 12350 60 0000 C CNN
+ 1 9350 12350
+ 0 1 1 0
+$EndComp
+$Comp
+L d_buffer U7
+U 1 1 68501BAA
+P 10800 12350
+F 0 "U7" H 10800 12300 60 0000 C CNN
+F 1 "d_buffer" H 10800 12400 60 0000 C CNN
+F 2 "" H 10800 12350 60 0000 C CNN
+F 3 "" H 10800 12350 60 0000 C CNN
+ 1 10800 12350
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 68501C0D
+P 7800 11300
+F 0 "U2" H 7800 11200 60 0000 C CNN
+F 1 "d_inverter" H 7800 11450 60 0000 C CNN
+F 2 "" H 7850 11250 60 0000 C CNN
+F 3 "" H 7850 11250 60 0000 C CNN
+ 1 7800 11300
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 68501C84
+P 9350 11300
+F 0 "U4" H 9350 11200 60 0000 C CNN
+F 1 "d_inverter" H 9350 11450 60 0000 C CNN
+F 2 "" H 9400 11250 60 0000 C CNN
+F 3 "" H 9400 11250 60 0000 C CNN
+ 1 9350 11300
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68501CD1
+P 10800 11250
+F 0 "U6" H 10800 11150 60 0000 C CNN
+F 1 "d_inverter" H 10800 11400 60 0000 C CNN
+F 2 "" H 10850 11200 60 0000 C CNN
+F 3 "" H 10850 11200 60 0000 C CNN
+ 1 10800 11250
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 10800 11850 10800 11550
+Wire Wire Line
+ 9350 11850 9350 11600
+Wire Wire Line
+ 7800 11900 7800 11600
+$Comp
+L 3_and X1
+U 1 1 68501E1D
+P 10750 13950
+F 0 "X1" H 10850 13900 60 0000 C CNN
+F 1 "3_and" H 10900 14100 60 0000 C CNN
+F 2 "" H 10750 13950 60 0000 C CNN
+F 3 "" H 10750 13950 60 0000 C CNN
+ 1 10750 13950
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 10800 13000 10800 13600
+Wire Wire Line
+ 10900 13600 10900 13350
+Wire Wire Line
+ 9350 13350 11300 13350
+Wire Wire Line
+ 9350 13350 9350 13000
+$Comp
+L d_and U12
+U 1 1 68501EA4
+P 12000 14050
+F 0 "U12" H 12000 14050 60 0000 C CNN
+F 1 "d_and" H 12050 14150 60 0000 C CNN
+F 2 "" H 12000 14050 60 0000 C CNN
+F 3 "" H 12000 14050 60 0000 C CNN
+ 1 12000 14050
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U14
+U 1 1 68501EFD
+P 13450 13050
+F 0 "U14" H 13450 12950 60 0000 C CNN
+F 1 "d_inverter" H 13450 13200 60 0000 C CNN
+F 2 "" H 13500 13000 60 0000 C CNN
+F 3 "" H 13500 13000 60 0000 C CNN
+ 1 13450 13050
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 13450 13700 13450 13350
+Wire Wire Line
+ 13550 13700 13550 13450
+Wire Wire Line
+ 12100 13450 13950 13450
+Wire Wire Line
+ 12100 13450 12100 13600
+Wire Wire Line
+ 12000 11650 12000 13600
+Wire Wire Line
+ 10700 13600 10700 13450
+Wire Wire Line
+ 10700 13450 12000 13450
+Connection ~ 12000 13450
+Wire Wire Line
+ 13450 12750 13450 12600
+Wire Wire Line
+ 11300 12600 16200 12600
+Wire Wire Line
+ 11300 13350 11300 12600
+Connection ~ 10900 13350
+$Comp
+L d_nor U9
+U 1 1 685022FF
+P 11400 15500
+F 0 "U9" H 11400 15500 60 0000 C CNN
+F 1 "d_nor" H 11450 15600 60 0000 C CNN
+F 2 "" H 11400 15500 60 0000 C CNN
+F 3 "" H 11400 15500 60 0000 C CNN
+ 1 11400 15500
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 11500 15050 12050 15050
+Wire Wire Line
+ 12050 15050 12050 14500
+Wire Wire Line
+ 11400 15050 10800 15050
+Wire Wire Line
+ 10800 15050 10800 14450
+$Comp
+L d_and U11
+U 1 1 685023D7
+P 11950 16850
+F 0 "U11" H 11950 16850 60 0000 C CNN
+F 1 "d_and" H 12000 16950 60 0000 C CNN
+F 2 "" H 11950 16850 60 0000 C CNN
+F 3 "" H 11950 16850 60 0000 C CNN
+ 1 11950 16850
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 11450 15950 11450 16300
+Wire Wire Line
+ 11450 16300 11950 16300
+Wire Wire Line
+ 11950 16300 11950 16400
+Wire Wire Line
+ 12050 16400 12050 16300
+Wire Wire Line
+ 12050 16300 13500 16300
+Wire Wire Line
+ 13500 16300 13500 14600
+$Comp
+L d_nand U15
+U 1 1 685025AA
+P 13450 14150
+F 0 "U15" H 13450 14150 60 0000 C CNN
+F 1 "d_nand" H 13500 14250 60 0000 C CNN
+F 2 "" H 13450 14150 60 0000 C CNN
+F 3 "" H 13450 14150 60 0000 C CNN
+ 1 13450 14150
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 68502657
+P 11200 17900
+F 0 "U8" H 11200 17800 60 0000 C CNN
+F 1 "d_inverter" H 11200 18050 60 0000 C CNN
+F 2 "" H 11250 17850 60 0000 C CNN
+F 3 "" H 11250 17850 60 0000 C CNN
+ 1 11200 17900
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U13
+U 1 1 685026C0
+P 12400 17900
+F 0 "U13" H 12400 17800 60 0000 C CNN
+F 1 "d_inverter" H 12400 18050 60 0000 C CNN
+F 2 "" H 12450 17850 60 0000 C CNN
+F 3 "" H 12450 17850 60 0000 C CNN
+ 1 12400 17900
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 11200 17600 12000 17600
+Wire Wire Line
+ 12000 17600 12000 17300
+Wire Wire Line
+ 12400 17600 12250 17600
+Wire Wire Line
+ 12250 17600 12250 17400
+Wire Wire Line
+ 12250 17400 7800 17400
+Wire Wire Line
+ 7800 17400 7800 13050
+$Comp
+L d_and U10
+U 1 1 685029B5
+P 11800 19500
+F 0 "U10" H 11800 19500 60 0000 C CNN
+F 1 "d_and" H 11850 19600 60 0000 C CNN
+F 2 "" H 11800 19500 60 0000 C CNN
+F 3 "" H 11800 19500 60 0000 C CNN
+ 1 11800 19500
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 11200 18200 11200 18700
+Wire Wire Line
+ 11200 18700 11800 18700
+Wire Wire Line
+ 11800 18700 11800 19050
+Wire Wire Line
+ 12400 18200 12400 18700
+Wire Wire Line
+ 12400 18700 11900 18700
+Wire Wire Line
+ 11900 18700 11900 19050
+Wire Wire Line
+ 11850 19950 11850 20600
+Wire Wire Line
+ 11850 20250 13950 20250
+Wire Wire Line
+ 13950 20250 13950 13450
+Connection ~ 13550 13450
+Connection ~ 11850 20250
+Wire Wire Line
+ 7800 11000 7800 10500
+Wire Wire Line
+ 9350 11000 9350 10450
+Wire Wire Line
+ 10800 10950 10800 10350
+Wire Wire Line
+ 10800 10350 10750 10350
+$Comp
+L PORT U1
+U 9 1 68502FCF
+P 7550 10500
+F 0 "U1" H 7600 10600 30 0000 C CNN
+F 1 "PORT" H 7550 10500 30 0000 C CNN
+F 2 "" H 7550 10500 60 0000 C CNN
+F 3 "" H 7550 10500 60 0000 C CNN
+ 9 7550 10500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685030E6
+P 9100 10450
+F 0 "U1" H 9150 10550 30 0000 C CNN
+F 1 "PORT" H 9100 10450 30 0000 C CNN
+F 2 "" H 9100 10450 60 0000 C CNN
+F 3 "" H 9100 10450 60 0000 C CNN
+ 1 9100 10450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685031E4
+P 10500 10350
+F 0 "U1" H 10550 10450 30 0000 C CNN
+F 1 "PORT" H 10500 10350 30 0000 C CNN
+F 2 "" H 10500 10350 60 0000 C CNN
+F 3 "" H 10500 10350 60 0000 C CNN
+ 2 10500 10350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6850330B
+P 11750 11650
+F 0 "U1" H 11800 11750 30 0000 C CNN
+F 1 "PORT" H 11750 11650 30 0000 C CNN
+F 2 "" H 11750 11650 60 0000 C CNN
+F 3 "" H 11750 11650 60 0000 C CNN
+ 3 11750 11650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 68503457
+P 11600 20600
+F 0 "U1" H 11650 20700 30 0000 C CNN
+F 1 "PORT" H 11600 20600 30 0000 C CNN
+F 2 "" H 11600 20600 60 0000 C CNN
+F 3 "" H 11600 20600 60 0000 C CNN
+ 15 11600 20600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U21
+U 1 1 6865558B
+P 20050 12000
+F 0 "U21" H 20050 11950 60 0000 C CNN
+F 1 "d_buffer" H 20050 12050 60 0000 C CNN
+F 2 "" H 20050 12000 60 0000 C CNN
+F 3 "" H 20050 12000 60 0000 C CNN
+ 1 20050 12000
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U20
+U 1 1 6865559D
+P 20050 10900
+F 0 "U20" H 20050 10800 60 0000 C CNN
+F 1 "d_inverter" H 20050 11050 60 0000 C CNN
+F 2 "" H 20100 10850 60 0000 C CNN
+F 3 "" H 20100 10850 60 0000 C CNN
+ 1 20050 10900
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 20050 11500 20050 11200
+$Comp
+L 3_and X2
+U 1 1 686555A6
+P 20000 13600
+F 0 "X2" H 20100 13550 60 0000 C CNN
+F 1 "3_and" H 20150 13750 60 0000 C CNN
+F 2 "" H 20000 13600 60 0000 C CNN
+F 3 "" H 20000 13600 60 0000 C CNN
+ 1 20000 13600
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 20050 12650 20050 13250
+Wire Wire Line
+ 20150 13250 20150 13000
+Wire Wire Line
+ 18600 13000 20550 13000
+Wire Wire Line
+ 18600 8200 18600 13000
+$Comp
+L d_and U26
+U 1 1 686555B0
+P 21250 13700
+F 0 "U26" H 21250 13700 60 0000 C CNN
+F 1 "d_and" H 21300 13800 60 0000 C CNN
+F 2 "" H 21250 13700 60 0000 C CNN
+F 3 "" H 21250 13700 60 0000 C CNN
+ 1 21250 13700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U28
+U 1 1 686555B6
+P 22700 12700
+F 0 "U28" H 22700 12600 60 0000 C CNN
+F 1 "d_inverter" H 22700 12850 60 0000 C CNN
+F 2 "" H 22750 12650 60 0000 C CNN
+F 3 "" H 22750 12650 60 0000 C CNN
+ 1 22700 12700
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 22700 13350 22700 13000
+Wire Wire Line
+ 22800 13350 22800 13100
+Wire Wire Line
+ 21350 13100 23200 13100
+Wire Wire Line
+ 21350 13100 21350 13250
+Wire Wire Line
+ 21250 11300 21250 13250
+Wire Wire Line
+ 19950 13250 19950 13100
+Wire Wire Line
+ 19950 13100 21250 13100
+Connection ~ 21250 13100
+Wire Wire Line
+ 22700 12400 22700 12250
+Wire Wire Line
+ 22700 12250 20550 12250
+Wire Wire Line
+ 20550 12250 20550 13000
+Connection ~ 20150 13000
+$Comp
+L d_nor U23
+U 1 1 686555C8
+P 20650 15150
+F 0 "U23" H 20650 15150 60 0000 C CNN
+F 1 "d_nor" H 20700 15250 60 0000 C CNN
+F 2 "" H 20650 15150 60 0000 C CNN
+F 3 "" H 20650 15150 60 0000 C CNN
+ 1 20650 15150
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 20750 14700 21300 14700
+Wire Wire Line
+ 21300 14700 21300 14150
+Wire Wire Line
+ 20650 14700 20050 14700
+Wire Wire Line
+ 20050 14700 20050 14100
+$Comp
+L d_and U25
+U 1 1 686555D2
+P 21200 16500
+F 0 "U25" H 21200 16500 60 0000 C CNN
+F 1 "d_and" H 21250 16600 60 0000 C CNN
+F 2 "" H 21200 16500 60 0000 C CNN
+F 3 "" H 21200 16500 60 0000 C CNN
+ 1 21200 16500
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 20700 15600 20700 15950
+Wire Wire Line
+ 20700 15950 21200 15950
+Wire Wire Line
+ 21200 15950 21200 16050
+Wire Wire Line
+ 21300 16050 21300 15950
+Wire Wire Line
+ 21300 15950 22750 15950
+Wire Wire Line
+ 22750 15950 22750 14250
+$Comp
+L d_nand U29
+U 1 1 686555DE
+P 22700 13800
+F 0 "U29" H 22700 13800 60 0000 C CNN
+F 1 "d_nand" H 22750 13900 60 0000 C CNN
+F 2 "" H 22700 13800 60 0000 C CNN
+F 3 "" H 22700 13800 60 0000 C CNN
+ 1 22700 13800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U22
+U 1 1 686555E4
+P 20450 17550
+F 0 "U22" H 20450 17450 60 0000 C CNN
+F 1 "d_inverter" H 20450 17700 60 0000 C CNN
+F 2 "" H 20500 17500 60 0000 C CNN
+F 3 "" H 20500 17500 60 0000 C CNN
+ 1 20450 17550
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U27
+U 1 1 686555EA
+P 21650 17550
+F 0 "U27" H 21650 17450 60 0000 C CNN
+F 1 "d_inverter" H 21650 17700 60 0000 C CNN
+F 2 "" H 21700 17500 60 0000 C CNN
+F 3 "" H 21700 17500 60 0000 C CNN
+ 1 21650 17550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 20450 17250 21250 17250
+Wire Wire Line
+ 21250 17250 21250 16950
+Wire Wire Line
+ 21650 17250 21500 17250
+Wire Wire Line
+ 21500 17250 21500 17050
+Wire Wire Line
+ 21500 17050 17050 17050
+Wire Wire Line
+ 17050 17050 17050 9200
+$Comp
+L d_and U24
+U 1 1 686555F6
+P 21050 19150
+F 0 "U24" H 21050 19150 60 0000 C CNN
+F 1 "d_and" H 21100 19250 60 0000 C CNN
+F 2 "" H 21050 19150 60 0000 C CNN
+F 3 "" H 21050 19150 60 0000 C CNN
+ 1 21050 19150
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 20450 17850 20450 18350
+Wire Wire Line
+ 20450 18350 21050 18350
+Wire Wire Line
+ 21050 18350 21050 18700
+Wire Wire Line
+ 21650 17850 21650 18350
+Wire Wire Line
+ 21650 18350 21150 18350
+Wire Wire Line
+ 21150 18350 21150 18700
+Wire Wire Line
+ 21100 19600 21100 20250
+Wire Wire Line
+ 21100 19900 23200 19900
+Wire Wire Line
+ 23200 19900 23200 13100
+Connection ~ 22800 13100
+Connection ~ 21100 19900
+Wire Wire Line
+ 20050 10600 20050 10000
+Wire Wire Line
+ 20050 10000 20000 10000
+$Comp
+L PORT U1
+U 14 1 68655617
+P 19750 10000
+F 0 "U1" H 19800 10100 30 0000 C CNN
+F 1 "PORT" H 19750 10000 30 0000 C CNN
+F 2 "" H 19750 10000 60 0000 C CNN
+F 3 "" H 19750 10000 60 0000 C CNN
+ 14 19750 10000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6865561D
+P 21000 11300
+F 0 "U1" H 21050 11400 30 0000 C CNN
+F 1 "PORT" H 21000 11300 30 0000 C CNN
+F 2 "" H 21000 11300 60 0000 C CNN
+F 3 "" H 21000 11300 60 0000 C CNN
+ 4 21000 11300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68655623
+P 20850 20250
+F 0 "U1" H 20900 20350 30 0000 C CNN
+F 1 "PORT" H 20850 20250 30 0000 C CNN
+F 2 "" H 20850 20250 60 0000 C CNN
+F 3 "" H 20850 20250 60 0000 C CNN
+ 13 20850 20250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U35
+U 1 1 686567BD
+P 28150 12400
+F 0 "U35" H 28150 12350 60 0000 C CNN
+F 1 "d_buffer" H 28150 12450 60 0000 C CNN
+F 2 "" H 28150 12400 60 0000 C CNN
+F 3 "" H 28150 12400 60 0000 C CNN
+ 1 28150 12400
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U34
+U 1 1 686567CF
+P 28150 11300
+F 0 "U34" H 28150 11200 60 0000 C CNN
+F 1 "d_inverter" H 28150 11450 60 0000 C CNN
+F 2 "" H 28200 11250 60 0000 C CNN
+F 3 "" H 28200 11250 60 0000 C CNN
+ 1 28150 11300
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 28150 11900 28150 11600
+$Comp
+L 3_and X3
+U 1 1 686567D8
+P 28100 14000
+F 0 "X3" H 28200 13950 60 0000 C CNN
+F 1 "3_and" H 28250 14150 60 0000 C CNN
+F 2 "" H 28100 14000 60 0000 C CNN
+F 3 "" H 28100 14000 60 0000 C CNN
+ 1 28100 14000
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 28150 13050 28150 13650
+Wire Wire Line
+ 28250 13650 28250 13400
+Wire Wire Line
+ 26700 13400 28650 13400
+Wire Wire Line
+ 26700 8200 26700 13400
+$Comp
+L d_and U40
+U 1 1 686567E3
+P 29350 14100
+F 0 "U40" H 29350 14100 60 0000 C CNN
+F 1 "d_and" H 29400 14200 60 0000 C CNN
+F 2 "" H 29350 14100 60 0000 C CNN
+F 3 "" H 29350 14100 60 0000 C CNN
+ 1 29350 14100
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U42
+U 1 1 686567E9
+P 30800 13100
+F 0 "U42" H 30800 13000 60 0000 C CNN
+F 1 "d_inverter" H 30800 13250 60 0000 C CNN
+F 2 "" H 30850 13050 60 0000 C CNN
+F 3 "" H 30850 13050 60 0000 C CNN
+ 1 30800 13100
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 30800 13750 30800 13400
+Wire Wire Line
+ 30900 13750 30900 13500
+Wire Wire Line
+ 29450 13500 31300 13500
+Wire Wire Line
+ 29450 13500 29450 13650
+Wire Wire Line
+ 29350 11700 29350 13650
+Wire Wire Line
+ 28050 13650 28050 13500
+Wire Wire Line
+ 28050 13500 29350 13500
+Connection ~ 29350 13500
+Wire Wire Line
+ 30800 12800 30800 12650
+Wire Wire Line
+ 30800 12650 28650 12650
+Wire Wire Line
+ 28650 12650 28650 13400
+Connection ~ 28250 13400
+$Comp
+L d_nor U37
+U 1 1 686567FD
+P 28750 15550
+F 0 "U37" H 28750 15550 60 0000 C CNN
+F 1 "d_nor" H 28800 15650 60 0000 C CNN
+F 2 "" H 28750 15550 60 0000 C CNN
+F 3 "" H 28750 15550 60 0000 C CNN
+ 1 28750 15550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 28850 15100 29400 15100
+Wire Wire Line
+ 29400 15100 29400 14550
+Wire Wire Line
+ 28750 15100 28150 15100
+Wire Wire Line
+ 28150 15100 28150 14500
+$Comp
+L d_and U39
+U 1 1 68656807
+P 29300 16900
+F 0 "U39" H 29300 16900 60 0000 C CNN
+F 1 "d_and" H 29350 17000 60 0000 C CNN
+F 2 "" H 29300 16900 60 0000 C CNN
+F 3 "" H 29300 16900 60 0000 C CNN
+ 1 29300 16900
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 28800 16000 28800 16350
+Wire Wire Line
+ 28800 16350 29300 16350
+Wire Wire Line
+ 29300 16350 29300 16450
+Wire Wire Line
+ 29400 16450 29400 16350
+Wire Wire Line
+ 29400 16350 30850 16350
+Wire Wire Line
+ 30850 16350 30850 14650
+$Comp
+L d_nand U43
+U 1 1 68656813
+P 30800 14200
+F 0 "U43" H 30800 14200 60 0000 C CNN
+F 1 "d_nand" H 30850 14300 60 0000 C CNN
+F 2 "" H 30800 14200 60 0000 C CNN
+F 3 "" H 30800 14200 60 0000 C CNN
+ 1 30800 14200
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U36
+U 1 1 68656819
+P 28550 17950
+F 0 "U36" H 28550 17850 60 0000 C CNN
+F 1 "d_inverter" H 28550 18100 60 0000 C CNN
+F 2 "" H 28600 17900 60 0000 C CNN
+F 3 "" H 28600 17900 60 0000 C CNN
+ 1 28550 17950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U41
+U 1 1 6865681F
+P 29750 17950
+F 0 "U41" H 29750 17850 60 0000 C CNN
+F 1 "d_inverter" H 29750 18100 60 0000 C CNN
+F 2 "" H 29800 17900 60 0000 C CNN
+F 3 "" H 29800 17900 60 0000 C CNN
+ 1 29750 17950
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 28550 17650 29350 17650
+Wire Wire Line
+ 29350 17650 29350 17350
+Wire Wire Line
+ 29750 17650 29600 17650
+Wire Wire Line
+ 29600 17650 29600 17450
+Wire Wire Line
+ 29600 17450 25150 17450
+Wire Wire Line
+ 25150 17450 25150 9200
+$Comp
+L d_and U38
+U 1 1 6865682B
+P 29150 19550
+F 0 "U38" H 29150 19550 60 0000 C CNN
+F 1 "d_and" H 29200 19650 60 0000 C CNN
+F 2 "" H 29150 19550 60 0000 C CNN
+F 3 "" H 29150 19550 60 0000 C CNN
+ 1 29150 19550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 28550 18250 28550 18750
+Wire Wire Line
+ 28550 18750 29150 18750
+Wire Wire Line
+ 29150 18750 29150 19100
+Wire Wire Line
+ 29750 18250 29750 18750
+Wire Wire Line
+ 29750 18750 29250 18750
+Wire Wire Line
+ 29250 18750 29250 19100
+Wire Wire Line
+ 29200 20000 29200 20650
+Wire Wire Line
+ 29200 20300 31300 20300
+Wire Wire Line
+ 31300 20300 31300 13500
+Connection ~ 30900 13500
+Connection ~ 29200 20300
+Wire Wire Line
+ 28150 11000 28150 10400
+Wire Wire Line
+ 28150 10400 28100 10400
+$Comp
+L PORT U1
+U 5 1 6865684D
+P 27850 10400
+F 0 "U1" H 27900 10500 30 0000 C CNN
+F 1 "PORT" H 27850 10400 30 0000 C CNN
+F 2 "" H 27850 10400 60 0000 C CNN
+F 3 "" H 27850 10400 60 0000 C CNN
+ 5 27850 10400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68656853
+P 29100 11700
+F 0 "U1" H 29150 11800 30 0000 C CNN
+F 1 "PORT" H 29100 11700 30 0000 C CNN
+F 2 "" H 29100 11700 60 0000 C CNN
+F 3 "" H 29100 11700 60 0000 C CNN
+ 6 29100 11700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 68656859
+P 28950 20650
+F 0 "U1" H 29000 20750 30 0000 C CNN
+F 1 "PORT" H 28950 20650 30 0000 C CNN
+F 2 "" H 28950 20650 60 0000 C CNN
+F 3 "" H 28950 20650 60 0000 C CNN
+ 12 28950 20650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U49
+U 1 1 6865686B
+P 37400 12050
+F 0 "U49" H 37400 12000 60 0000 C CNN
+F 1 "d_buffer" H 37400 12100 60 0000 C CNN
+F 2 "" H 37400 12050 60 0000 C CNN
+F 3 "" H 37400 12050 60 0000 C CNN
+ 1 37400 12050
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U48
+U 1 1 6865687D
+P 37400 10950
+F 0 "U48" H 37400 10850 60 0000 C CNN
+F 1 "d_inverter" H 37400 11100 60 0000 C CNN
+F 2 "" H 37450 10900 60 0000 C CNN
+F 3 "" H 37450 10900 60 0000 C CNN
+ 1 37400 10950
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 37400 11550 37400 11250
+$Comp
+L 3_and X4
+U 1 1 68656886
+P 37350 13650
+F 0 "X4" H 37450 13600 60 0000 C CNN
+F 1 "3_and" H 37500 13800 60 0000 C CNN
+F 2 "" H 37350 13650 60 0000 C CNN
+F 3 "" H 37350 13650 60 0000 C CNN
+ 1 37350 13650
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 37400 12700 37400 13300
+Wire Wire Line
+ 37500 13300 37500 13050
+Wire Wire Line
+ 35950 13050 37900 13050
+Wire Wire Line
+ 35950 8200 35950 13050
+$Comp
+L d_and U54
+U 1 1 68656891
+P 38600 13750
+F 0 "U54" H 38600 13750 60 0000 C CNN
+F 1 "d_and" H 38650 13850 60 0000 C CNN
+F 2 "" H 38600 13750 60 0000 C CNN
+F 3 "" H 38600 13750 60 0000 C CNN
+ 1 38600 13750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U56
+U 1 1 68656897
+P 40050 12750
+F 0 "U56" H 40050 12650 60 0000 C CNN
+F 1 "d_inverter" H 40050 12900 60 0000 C CNN
+F 2 "" H 40100 12700 60 0000 C CNN
+F 3 "" H 40100 12700 60 0000 C CNN
+ 1 40050 12750
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 40050 13400 40050 13050
+Wire Wire Line
+ 40150 13400 40150 13150
+Wire Wire Line
+ 38700 13150 40550 13150
+Wire Wire Line
+ 38700 13150 38700 13300
+Wire Wire Line
+ 38600 11350 38600 13300
+Wire Wire Line
+ 37300 13300 37300 13150
+Wire Wire Line
+ 37300 13150 38600 13150
+Connection ~ 38600 13150
+Wire Wire Line
+ 40050 12450 40050 12300
+Wire Wire Line
+ 40050 12300 37900 12300
+Wire Wire Line
+ 37900 12300 37900 13050
+Connection ~ 37500 13050
+$Comp
+L d_nor U51
+U 1 1 686568AB
+P 38000 15200
+F 0 "U51" H 38000 15200 60 0000 C CNN
+F 1 "d_nor" H 38050 15300 60 0000 C CNN
+F 2 "" H 38000 15200 60 0000 C CNN
+F 3 "" H 38000 15200 60 0000 C CNN
+ 1 38000 15200
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 38100 14750 38650 14750
+Wire Wire Line
+ 38650 14750 38650 14200
+Wire Wire Line
+ 38000 14750 37400 14750
+Wire Wire Line
+ 37400 14750 37400 14150
+$Comp
+L d_and U53
+U 1 1 686568B5
+P 38550 16550
+F 0 "U53" H 38550 16550 60 0000 C CNN
+F 1 "d_and" H 38600 16650 60 0000 C CNN
+F 2 "" H 38550 16550 60 0000 C CNN
+F 3 "" H 38550 16550 60 0000 C CNN
+ 1 38550 16550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 38050 15650 38050 16000
+Wire Wire Line
+ 38050 16000 38550 16000
+Wire Wire Line
+ 38550 16000 38550 16100
+Wire Wire Line
+ 38650 16100 38650 16000
+Wire Wire Line
+ 38650 16000 40100 16000
+Wire Wire Line
+ 40100 16000 40100 14300
+$Comp
+L d_nand U57
+U 1 1 686568C1
+P 40050 13850
+F 0 "U57" H 40050 13850 60 0000 C CNN
+F 1 "d_nand" H 40100 13950 60 0000 C CNN
+F 2 "" H 40050 13850 60 0000 C CNN
+F 3 "" H 40050 13850 60 0000 C CNN
+ 1 40050 13850
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U50
+U 1 1 686568C7
+P 37800 17600
+F 0 "U50" H 37800 17500 60 0000 C CNN
+F 1 "d_inverter" H 37800 17750 60 0000 C CNN
+F 2 "" H 37850 17550 60 0000 C CNN
+F 3 "" H 37850 17550 60 0000 C CNN
+ 1 37800 17600
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U55
+U 1 1 686568CD
+P 39000 17600
+F 0 "U55" H 39000 17500 60 0000 C CNN
+F 1 "d_inverter" H 39000 17750 60 0000 C CNN
+F 2 "" H 39050 17550 60 0000 C CNN
+F 3 "" H 39050 17550 60 0000 C CNN
+ 1 39000 17600
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 37800 17300 38600 17300
+Wire Wire Line
+ 38600 17300 38600 17000
+Wire Wire Line
+ 39000 17300 38850 17300
+Wire Wire Line
+ 38850 17300 38850 17100
+Wire Wire Line
+ 38850 17100 34400 17100
+Wire Wire Line
+ 34400 17100 34400 9200
+$Comp
+L d_and U52
+U 1 1 686568D9
+P 38400 19200
+F 0 "U52" H 38400 19200 60 0000 C CNN
+F 1 "d_and" H 38450 19300 60 0000 C CNN
+F 2 "" H 38400 19200 60 0000 C CNN
+F 3 "" H 38400 19200 60 0000 C CNN
+ 1 38400 19200
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 37800 17900 37800 18400
+Wire Wire Line
+ 37800 18400 38400 18400
+Wire Wire Line
+ 38400 18400 38400 18750
+Wire Wire Line
+ 39000 17900 39000 18400
+Wire Wire Line
+ 39000 18400 38500 18400
+Wire Wire Line
+ 38500 18400 38500 18750
+Wire Wire Line
+ 38450 19650 38450 20300
+Wire Wire Line
+ 38450 19950 40550 19950
+Wire Wire Line
+ 40550 19950 40550 13150
+Connection ~ 40150 13150
+Connection ~ 38450 19950
+Wire Wire Line
+ 37400 10650 37400 10050
+Wire Wire Line
+ 37400 10050 37350 10050
+$Comp
+L PORT U1
+U 11 1 686568FB
+P 37100 10050
+F 0 "U1" H 37150 10150 30 0000 C CNN
+F 1 "PORT" H 37100 10050 30 0000 C CNN
+F 2 "" H 37100 10050 60 0000 C CNN
+F 3 "" H 37100 10050 60 0000 C CNN
+ 11 37100 10050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68656901
+P 38350 11350
+F 0 "U1" H 38400 11450 30 0000 C CNN
+F 1 "PORT" H 38350 11350 30 0000 C CNN
+F 2 "" H 38350 11350 60 0000 C CNN
+F 3 "" H 38350 11350 60 0000 C CNN
+ 7 38350 11350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 68656907
+P 38200 20300
+F 0 "U1" H 38250 20400 30 0000 C CNN
+F 1 "PORT" H 38200 20300 30 0000 C CNN
+F 2 "" H 38200 20300 60 0000 C CNN
+F 3 "" H 38200 20300 60 0000 C CNN
+ 10 38200 20300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 34400 9200 8650 9200
+Connection ~ 25150 9200
+Wire Wire Line
+ 8650 9200 8650 14200
+Connection ~ 17050 9200
+Wire Wire Line
+ 16200 8200 35950 8200
+Connection ~ 26700 8200
+Wire Wire Line
+ 16200 12600 16200 8200
+Connection ~ 18600 8200
+Connection ~ 13450 12600
+Text Label 7800 10700 0 60 ~ 0
+MR_Bar
+Text Label 9350 10650 0 60 ~ 0
+E_Bar
+Text Label 10800 10600 0 60 ~ 0
+S0_Bar
+Text Label 12000 11800 0 60 ~ 0
+D0
+Text Label 20050 10150 0 60 ~ 0
+S1_Bar
+Text Label 21250 11500 0 60 ~ 0
+D1
+Text Label 28150 10600 0 60 ~ 0
+S2_Bar
+Text Label 29350 12000 0 60 ~ 0
+D2
+Text Label 38600 11650 0 60 ~ 0
+D3
+Text Label 37400 10250 0 60 ~ 0
+S3_Bar
+Text Label 11850 20450 0 60 ~ 0
+Q0
+Text Label 21100 20100 0 60 ~ 0
+Q1
+Text Label 29200 20500 0 60 ~ 0
+Q2
+Text Label 38450 20100 0 60 ~ 0
+Q3
+Wire Wire Line
+ 8650 14200 7800 14200
+Connection ~ 7800 14200
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir
new file mode 100644
index 000000000..300b515e4
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir
@@ -0,0 +1,59 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\DSR_LATCH\DSR_LATCH.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/04/25 20:03:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U2-Pad2_ Net-_U13-Pad1_ d_buffer
+U5 Net-_U4-Pad2_ Net-_U14-Pad1_ d_buffer
+U7 Net-_U6-Pad2_ Net-_U7-Pad2_ d_buffer
+U2 /MR_Bar Net-_U2-Pad2_ d_inverter
+U4 /E_Bar Net-_U4-Pad2_ d_inverter
+U6 /S0_Bar Net-_U6-Pad2_ d_inverter
+X1 Net-_U14-Pad1_ Net-_U7-Pad2_ /D0 Net-_U9-Pad2_ 3_and
+U12 /Q0 /D0 Net-_U12-Pad3_ d_and
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U9 Net-_U12-Pad3_ Net-_U9-Pad2_ Net-_U11-Pad2_ d_nor
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
+U15 /Q0 Net-_U14-Pad2_ Net-_U11-Pad1_ d_nand
+U8 Net-_U11-Pad3_ Net-_U10-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U10-Pad1_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ /Q0 d_and
+U1 /E_Bar /S0_Bar /D0 /D1 /S2_Bar /D2 /D3 /MR_Bar /Q3 /S3_Bar /Q2 /Q1 /S1_Bar /Q0 PORT
+U21 Net-_U20-Pad2_ Net-_U21-Pad2_ d_buffer
+U20 /S1_Bar Net-_U20-Pad2_ d_inverter
+X2 Net-_U14-Pad1_ Net-_U21-Pad2_ /D1 Net-_U23-Pad2_ 3_and
+U26 /Q1 /D1 Net-_U23-Pad1_ d_and
+U28 Net-_U14-Pad1_ Net-_U28-Pad2_ d_inverter
+U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_nor
+U25 Net-_U25-Pad1_ Net-_U23-Pad3_ Net-_U22-Pad1_ d_and
+U29 /Q1 Net-_U28-Pad2_ Net-_U25-Pad1_ d_nand
+U22 Net-_U22-Pad1_ Net-_U22-Pad2_ d_inverter
+U27 Net-_U13-Pad1_ Net-_U24-Pad1_ d_inverter
+U24 Net-_U24-Pad1_ Net-_U22-Pad2_ /Q1 d_and
+U35 Net-_U34-Pad2_ Net-_U35-Pad2_ d_buffer
+U34 /S2_Bar Net-_U34-Pad2_ d_inverter
+X3 Net-_U14-Pad1_ Net-_U35-Pad2_ /D2 Net-_U37-Pad2_ 3_and
+U40 /Q2 /D2 Net-_U37-Pad1_ d_and
+U42 Net-_U14-Pad1_ Net-_U42-Pad2_ d_inverter
+U37 Net-_U37-Pad1_ Net-_U37-Pad2_ Net-_U37-Pad3_ d_nor
+U39 Net-_U39-Pad1_ Net-_U37-Pad3_ Net-_U36-Pad1_ d_and
+U43 /Q2 Net-_U42-Pad2_ Net-_U39-Pad1_ d_nand
+U36 Net-_U36-Pad1_ Net-_U36-Pad2_ d_inverter
+U41 Net-_U13-Pad1_ Net-_U38-Pad1_ d_inverter
+U38 Net-_U38-Pad1_ Net-_U36-Pad2_ /Q2 d_and
+U49 Net-_U48-Pad2_ Net-_U49-Pad2_ d_buffer
+U48 /S3_Bar Net-_U48-Pad2_ d_inverter
+X4 Net-_U14-Pad1_ Net-_U49-Pad2_ /D3 Net-_U51-Pad2_ 3_and
+U54 /Q3 /D3 Net-_U51-Pad1_ d_and
+U56 Net-_U14-Pad1_ Net-_U56-Pad2_ d_inverter
+U51 Net-_U51-Pad1_ Net-_U51-Pad2_ Net-_U51-Pad3_ d_nor
+U53 Net-_U53-Pad1_ Net-_U51-Pad3_ Net-_U50-Pad1_ d_and
+U57 /Q3 Net-_U56-Pad2_ Net-_U53-Pad1_ d_nand
+U50 Net-_U50-Pad1_ Net-_U50-Pad2_ d_inverter
+U55 Net-_U13-Pad1_ Net-_U52-Pad1_ d_inverter
+U52 Net-_U52-Pad1_ Net-_U50-Pad2_ /Q3 d_and
+
+.end
diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir.out b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir.out
new file mode 100644
index 000000000..ead328265
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.cir.out
@@ -0,0 +1,193 @@
+* c:\fossee\esim\library\subcircuitlibrary\dsr_latch\dsr_latch.cir
+
+.include 3_and.sub
+* u3 net-_u2-pad2_ net-_u13-pad1_ d_buffer
+* u5 net-_u4-pad2_ net-_u14-pad1_ d_buffer
+* u7 net-_u6-pad2_ net-_u7-pad2_ d_buffer
+* u2 /mr_bar net-_u2-pad2_ d_inverter
+* u4 /e_bar net-_u4-pad2_ d_inverter
+* u6 /s0_bar net-_u6-pad2_ d_inverter
+x1 net-_u14-pad1_ net-_u7-pad2_ /d0 net-_u9-pad2_ 3_and
+* u12 /q0 /d0 net-_u12-pad3_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u9 net-_u12-pad3_ net-_u9-pad2_ net-_u11-pad2_ d_nor
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u15 /q0 net-_u14-pad2_ net-_u11-pad1_ d_nand
+* u8 net-_u11-pad3_ net-_u10-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u10-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ /q0 d_and
+* u1 /e_bar /s0_bar /d0 /d1 /s2_bar /d2 /d3 /mr_bar /q3 /s3_bar /q2 /q1 /s1_bar /q0 port
+* u21 net-_u20-pad2_ net-_u21-pad2_ d_buffer
+* u20 /s1_bar net-_u20-pad2_ d_inverter
+x2 net-_u14-pad1_ net-_u21-pad2_ /d1 net-_u23-pad2_ 3_and
+* u26 /q1 /d1 net-_u23-pad1_ d_and
+* u28 net-_u14-pad1_ net-_u28-pad2_ d_inverter
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_nor
+* u25 net-_u25-pad1_ net-_u23-pad3_ net-_u22-pad1_ d_and
+* u29 /q1 net-_u28-pad2_ net-_u25-pad1_ d_nand
+* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter
+* u27 net-_u13-pad1_ net-_u24-pad1_ d_inverter
+* u24 net-_u24-pad1_ net-_u22-pad2_ /q1 d_and
+* u35 net-_u34-pad2_ net-_u35-pad2_ d_buffer
+* u34 /s2_bar net-_u34-pad2_ d_inverter
+x3 net-_u14-pad1_ net-_u35-pad2_ /d2 net-_u37-pad2_ 3_and
+* u40 /q2 /d2 net-_u37-pad1_ d_and
+* u42 net-_u14-pad1_ net-_u42-pad2_ d_inverter
+* u37 net-_u37-pad1_ net-_u37-pad2_ net-_u37-pad3_ d_nor
+* u39 net-_u39-pad1_ net-_u37-pad3_ net-_u36-pad1_ d_and
+* u43 /q2 net-_u42-pad2_ net-_u39-pad1_ d_nand
+* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter
+* u41 net-_u13-pad1_ net-_u38-pad1_ d_inverter
+* u38 net-_u38-pad1_ net-_u36-pad2_ /q2 d_and
+* u49 net-_u48-pad2_ net-_u49-pad2_ d_buffer
+* u48 /s3_bar net-_u48-pad2_ d_inverter
+x4 net-_u14-pad1_ net-_u49-pad2_ /d3 net-_u51-pad2_ 3_and
+* u54 /q3 /d3 net-_u51-pad1_ d_and
+* u56 net-_u14-pad1_ net-_u56-pad2_ d_inverter
+* u51 net-_u51-pad1_ net-_u51-pad2_ net-_u51-pad3_ d_nor
+* u53 net-_u53-pad1_ net-_u51-pad3_ net-_u50-pad1_ d_and
+* u57 /q3 net-_u56-pad2_ net-_u53-pad1_ d_nand
+* u50 net-_u50-pad1_ net-_u50-pad2_ d_inverter
+* u55 net-_u13-pad1_ net-_u52-pad1_ d_inverter
+* u52 net-_u52-pad1_ net-_u50-pad2_ /q3 d_and
+a1 net-_u2-pad2_ net-_u13-pad1_ u3
+a2 net-_u4-pad2_ net-_u14-pad1_ u5
+a3 net-_u6-pad2_ net-_u7-pad2_ u7
+a4 /mr_bar net-_u2-pad2_ u2
+a5 /e_bar net-_u4-pad2_ u4
+a6 /s0_bar net-_u6-pad2_ u6
+a7 [/q0 /d0 ] net-_u12-pad3_ u12
+a8 net-_u14-pad1_ net-_u14-pad2_ u14
+a9 [net-_u12-pad3_ net-_u9-pad2_ ] net-_u11-pad2_ u9
+a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a11 [/q0 net-_u14-pad2_ ] net-_u11-pad1_ u15
+a12 net-_u11-pad3_ net-_u10-pad2_ u8
+a13 net-_u13-pad1_ net-_u10-pad1_ u13
+a14 [net-_u10-pad1_ net-_u10-pad2_ ] /q0 u10
+a15 net-_u20-pad2_ net-_u21-pad2_ u21
+a16 /s1_bar net-_u20-pad2_ u20
+a17 [/q1 /d1 ] net-_u23-pad1_ u26
+a18 net-_u14-pad1_ net-_u28-pad2_ u28
+a19 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a20 [net-_u25-pad1_ net-_u23-pad3_ ] net-_u22-pad1_ u25
+a21 [/q1 net-_u28-pad2_ ] net-_u25-pad1_ u29
+a22 net-_u22-pad1_ net-_u22-pad2_ u22
+a23 net-_u13-pad1_ net-_u24-pad1_ u27
+a24 [net-_u24-pad1_ net-_u22-pad2_ ] /q1 u24
+a25 net-_u34-pad2_ net-_u35-pad2_ u35
+a26 /s2_bar net-_u34-pad2_ u34
+a27 [/q2 /d2 ] net-_u37-pad1_ u40
+a28 net-_u14-pad1_ net-_u42-pad2_ u42
+a29 [net-_u37-pad1_ net-_u37-pad2_ ] net-_u37-pad3_ u37
+a30 [net-_u39-pad1_ net-_u37-pad3_ ] net-_u36-pad1_ u39
+a31 [/q2 net-_u42-pad2_ ] net-_u39-pad1_ u43
+a32 net-_u36-pad1_ net-_u36-pad2_ u36
+a33 net-_u13-pad1_ net-_u38-pad1_ u41
+a34 [net-_u38-pad1_ net-_u36-pad2_ ] /q2 u38
+a35 net-_u48-pad2_ net-_u49-pad2_ u49
+a36 /s3_bar net-_u48-pad2_ u48
+a37 [/q3 /d3 ] net-_u51-pad1_ u54
+a38 net-_u14-pad1_ net-_u56-pad2_ u56
+a39 [net-_u51-pad1_ net-_u51-pad2_ ] net-_u51-pad3_ u51
+a40 [net-_u53-pad1_ net-_u51-pad3_ ] net-_u50-pad1_ u53
+a41 [/q3 net-_u56-pad2_ ] net-_u53-pad1_ u57
+a42 net-_u50-pad1_ net-_u50-pad2_ u50
+a43 net-_u13-pad1_ net-_u52-pad1_ u55
+a44 [net-_u52-pad1_ net-_u50-pad2_ ] /q3 u52
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u35 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u49 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.pro b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sch b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sch
new file mode 100644
index 000000000..5ec94bedc
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sch
@@ -0,0 +1,1141 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DSR_LATCH-cache
+EELAYER 25 0
+EELAYER END
+$Descr A0 46811 33110
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_buffer U3
+U 1 1 68501ACE
+P 7800 12400
+F 0 "U3" H 7800 12350 60 0000 C CNN
+F 1 "d_buffer" H 7800 12450 60 0000 C CNN
+F 2 "" H 7800 12400 60 0000 C CNN
+F 3 "" H 7800 12400 60 0000 C CNN
+ 1 7800 12400
+ 0 1 1 0
+$EndComp
+$Comp
+L d_buffer U5
+U 1 1 68501B69
+P 9350 12350
+F 0 "U5" H 9350 12300 60 0000 C CNN
+F 1 "d_buffer" H 9350 12400 60 0000 C CNN
+F 2 "" H 9350 12350 60 0000 C CNN
+F 3 "" H 9350 12350 60 0000 C CNN
+ 1 9350 12350
+ 0 1 1 0
+$EndComp
+$Comp
+L d_buffer U7
+U 1 1 68501BAA
+P 10800 12350
+F 0 "U7" H 10800 12300 60 0000 C CNN
+F 1 "d_buffer" H 10800 12400 60 0000 C CNN
+F 2 "" H 10800 12350 60 0000 C CNN
+F 3 "" H 10800 12350 60 0000 C CNN
+ 1 10800 12350
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 68501C0D
+P 7800 11300
+F 0 "U2" H 7800 11200 60 0000 C CNN
+F 1 "d_inverter" H 7800 11450 60 0000 C CNN
+F 2 "" H 7850 11250 60 0000 C CNN
+F 3 "" H 7850 11250 60 0000 C CNN
+ 1 7800 11300
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 68501C84
+P 9350 11300
+F 0 "U4" H 9350 11200 60 0000 C CNN
+F 1 "d_inverter" H 9350 11450 60 0000 C CNN
+F 2 "" H 9400 11250 60 0000 C CNN
+F 3 "" H 9400 11250 60 0000 C CNN
+ 1 9350 11300
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68501CD1
+P 10800 11250
+F 0 "U6" H 10800 11150 60 0000 C CNN
+F 1 "d_inverter" H 10800 11400 60 0000 C CNN
+F 2 "" H 10850 11200 60 0000 C CNN
+F 3 "" H 10850 11200 60 0000 C CNN
+ 1 10800 11250
+ 0 1 1 0
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 68501E1D
+P 10750 13950
+F 0 "X1" H 10850 13900 60 0000 C CNN
+F 1 "3_and" H 10900 14100 60 0000 C CNN
+F 2 "" H 10750 13950 60 0000 C CNN
+F 3 "" H 10750 13950 60 0000 C CNN
+ 1 10750 13950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U12
+U 1 1 68501EA4
+P 12000 14050
+F 0 "U12" H 12000 14050 60 0000 C CNN
+F 1 "d_and" H 12050 14150 60 0000 C CNN
+F 2 "" H 12000 14050 60 0000 C CNN
+F 3 "" H 12000 14050 60 0000 C CNN
+ 1 12000 14050
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U14
+U 1 1 68501EFD
+P 13450 13050
+F 0 "U14" H 13450 12950 60 0000 C CNN
+F 1 "d_inverter" H 13450 13200 60 0000 C CNN
+F 2 "" H 13500 13000 60 0000 C CNN
+F 3 "" H 13500 13000 60 0000 C CNN
+ 1 13450 13050
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U9
+U 1 1 685022FF
+P 11400 15500
+F 0 "U9" H 11400 15500 60 0000 C CNN
+F 1 "d_nor" H 11450 15600 60 0000 C CNN
+F 2 "" H 11400 15500 60 0000 C CNN
+F 3 "" H 11400 15500 60 0000 C CNN
+ 1 11400 15500
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U11
+U 1 1 685023D7
+P 11950 16850
+F 0 "U11" H 11950 16850 60 0000 C CNN
+F 1 "d_and" H 12000 16950 60 0000 C CNN
+F 2 "" H 11950 16850 60 0000 C CNN
+F 3 "" H 11950 16850 60 0000 C CNN
+ 1 11950 16850
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nand U15
+U 1 1 685025AA
+P 13450 14150
+F 0 "U15" H 13450 14150 60 0000 C CNN
+F 1 "d_nand" H 13500 14250 60 0000 C CNN
+F 2 "" H 13450 14150 60 0000 C CNN
+F 3 "" H 13450 14150 60 0000 C CNN
+ 1 13450 14150
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 68502657
+P 11200 17900
+F 0 "U8" H 11200 17800 60 0000 C CNN
+F 1 "d_inverter" H 11200 18050 60 0000 C CNN
+F 2 "" H 11250 17850 60 0000 C CNN
+F 3 "" H 11250 17850 60 0000 C CNN
+ 1 11200 17900
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U13
+U 1 1 685026C0
+P 12400 17900
+F 0 "U13" H 12400 17800 60 0000 C CNN
+F 1 "d_inverter" H 12400 18050 60 0000 C CNN
+F 2 "" H 12450 17850 60 0000 C CNN
+F 3 "" H 12450 17850 60 0000 C CNN
+ 1 12400 17900
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U10
+U 1 1 685029B5
+P 11800 19500
+F 0 "U10" H 11800 19500 60 0000 C CNN
+F 1 "d_and" H 11850 19600 60 0000 C CNN
+F 2 "" H 11800 19500 60 0000 C CNN
+F 3 "" H 11800 19500 60 0000 C CNN
+ 1 11800 19500
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68502FCF
+P 7550 10500
+F 0 "U1" H 7600 10600 30 0000 C CNN
+F 1 "PORT" H 7550 10500 30 0000 C CNN
+F 2 "" H 7550 10500 60 0000 C CNN
+F 3 "" H 7550 10500 60 0000 C CNN
+ 9 7550 10500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685030E6
+P 9100 10450
+F 0 "U1" H 9150 10550 30 0000 C CNN
+F 1 "PORT" H 9100 10450 30 0000 C CNN
+F 2 "" H 9100 10450 60 0000 C CNN
+F 3 "" H 9100 10450 60 0000 C CNN
+ 1 9100 10450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685031E4
+P 10500 10350
+F 0 "U1" H 10550 10450 30 0000 C CNN
+F 1 "PORT" H 10500 10350 30 0000 C CNN
+F 2 "" H 10500 10350 60 0000 C CNN
+F 3 "" H 10500 10350 60 0000 C CNN
+ 2 10500 10350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6850330B
+P 11750 11650
+F 0 "U1" H 11800 11750 30 0000 C CNN
+F 1 "PORT" H 11750 11650 30 0000 C CNN
+F 2 "" H 11750 11650 60 0000 C CNN
+F 3 "" H 11750 11650 60 0000 C CNN
+ 3 11750 11650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 68503457
+P 11600 20600
+F 0 "U1" H 11650 20700 30 0000 C CNN
+F 1 "PORT" H 11600 20600 30 0000 C CNN
+F 2 "" H 11600 20600 60 0000 C CNN
+F 3 "" H 11600 20600 60 0000 C CNN
+ 15 11600 20600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U21
+U 1 1 6865558B
+P 20050 12000
+F 0 "U21" H 20050 11950 60 0000 C CNN
+F 1 "d_buffer" H 20050 12050 60 0000 C CNN
+F 2 "" H 20050 12000 60 0000 C CNN
+F 3 "" H 20050 12000 60 0000 C CNN
+ 1 20050 12000
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U20
+U 1 1 6865559D
+P 20050 10900
+F 0 "U20" H 20050 10800 60 0000 C CNN
+F 1 "d_inverter" H 20050 11050 60 0000 C CNN
+F 2 "" H 20100 10850 60 0000 C CNN
+F 3 "" H 20100 10850 60 0000 C CNN
+ 1 20050 10900
+ 0 1 1 0
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 686555A6
+P 20000 13600
+F 0 "X2" H 20100 13550 60 0000 C CNN
+F 1 "3_and" H 20150 13750 60 0000 C CNN
+F 2 "" H 20000 13600 60 0000 C CNN
+F 3 "" H 20000 13600 60 0000 C CNN
+ 1 20000 13600
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U26
+U 1 1 686555B0
+P 21250 13700
+F 0 "U26" H 21250 13700 60 0000 C CNN
+F 1 "d_and" H 21300 13800 60 0000 C CNN
+F 2 "" H 21250 13700 60 0000 C CNN
+F 3 "" H 21250 13700 60 0000 C CNN
+ 1 21250 13700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U28
+U 1 1 686555B6
+P 22700 12700
+F 0 "U28" H 22700 12600 60 0000 C CNN
+F 1 "d_inverter" H 22700 12850 60 0000 C CNN
+F 2 "" H 22750 12650 60 0000 C CNN
+F 3 "" H 22750 12650 60 0000 C CNN
+ 1 22700 12700
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U23
+U 1 1 686555C8
+P 20650 15150
+F 0 "U23" H 20650 15150 60 0000 C CNN
+F 1 "d_nor" H 20700 15250 60 0000 C CNN
+F 2 "" H 20650 15150 60 0000 C CNN
+F 3 "" H 20650 15150 60 0000 C CNN
+ 1 20650 15150
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U25
+U 1 1 686555D2
+P 21200 16500
+F 0 "U25" H 21200 16500 60 0000 C CNN
+F 1 "d_and" H 21250 16600 60 0000 C CNN
+F 2 "" H 21200 16500 60 0000 C CNN
+F 3 "" H 21200 16500 60 0000 C CNN
+ 1 21200 16500
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nand U29
+U 1 1 686555DE
+P 22700 13800
+F 0 "U29" H 22700 13800 60 0000 C CNN
+F 1 "d_nand" H 22750 13900 60 0000 C CNN
+F 2 "" H 22700 13800 60 0000 C CNN
+F 3 "" H 22700 13800 60 0000 C CNN
+ 1 22700 13800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U22
+U 1 1 686555E4
+P 20450 17550
+F 0 "U22" H 20450 17450 60 0000 C CNN
+F 1 "d_inverter" H 20450 17700 60 0000 C CNN
+F 2 "" H 20500 17500 60 0000 C CNN
+F 3 "" H 20500 17500 60 0000 C CNN
+ 1 20450 17550
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U27
+U 1 1 686555EA
+P 21650 17550
+F 0 "U27" H 21650 17450 60 0000 C CNN
+F 1 "d_inverter" H 21650 17700 60 0000 C CNN
+F 2 "" H 21700 17500 60 0000 C CNN
+F 3 "" H 21700 17500 60 0000 C CNN
+ 1 21650 17550
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U24
+U 1 1 686555F6
+P 21050 19150
+F 0 "U24" H 21050 19150 60 0000 C CNN
+F 1 "d_and" H 21100 19250 60 0000 C CNN
+F 2 "" H 21050 19150 60 0000 C CNN
+F 3 "" H 21050 19150 60 0000 C CNN
+ 1 21050 19150
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 14 1 68655617
+P 19750 10000
+F 0 "U1" H 19800 10100 30 0000 C CNN
+F 1 "PORT" H 19750 10000 30 0000 C CNN
+F 2 "" H 19750 10000 60 0000 C CNN
+F 3 "" H 19750 10000 60 0000 C CNN
+ 14 19750 10000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6865561D
+P 21000 11300
+F 0 "U1" H 21050 11400 30 0000 C CNN
+F 1 "PORT" H 21000 11300 30 0000 C CNN
+F 2 "" H 21000 11300 60 0000 C CNN
+F 3 "" H 21000 11300 60 0000 C CNN
+ 4 21000 11300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68655623
+P 20850 20250
+F 0 "U1" H 20900 20350 30 0000 C CNN
+F 1 "PORT" H 20850 20250 30 0000 C CNN
+F 2 "" H 20850 20250 60 0000 C CNN
+F 3 "" H 20850 20250 60 0000 C CNN
+ 13 20850 20250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U35
+U 1 1 686567BD
+P 28150 12400
+F 0 "U35" H 28150 12350 60 0000 C CNN
+F 1 "d_buffer" H 28150 12450 60 0000 C CNN
+F 2 "" H 28150 12400 60 0000 C CNN
+F 3 "" H 28150 12400 60 0000 C CNN
+ 1 28150 12400
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U34
+U 1 1 686567CF
+P 28150 11300
+F 0 "U34" H 28150 11200 60 0000 C CNN
+F 1 "d_inverter" H 28150 11450 60 0000 C CNN
+F 2 "" H 28200 11250 60 0000 C CNN
+F 3 "" H 28200 11250 60 0000 C CNN
+ 1 28150 11300
+ 0 1 1 0
+$EndComp
+$Comp
+L 3_and X3
+U 1 1 686567D8
+P 28100 14000
+F 0 "X3" H 28200 13950 60 0000 C CNN
+F 1 "3_and" H 28250 14150 60 0000 C CNN
+F 2 "" H 28100 14000 60 0000 C CNN
+F 3 "" H 28100 14000 60 0000 C CNN
+ 1 28100 14000
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U40
+U 1 1 686567E3
+P 29350 14100
+F 0 "U40" H 29350 14100 60 0000 C CNN
+F 1 "d_and" H 29400 14200 60 0000 C CNN
+F 2 "" H 29350 14100 60 0000 C CNN
+F 3 "" H 29350 14100 60 0000 C CNN
+ 1 29350 14100
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U42
+U 1 1 686567E9
+P 30800 13100
+F 0 "U42" H 30800 13000 60 0000 C CNN
+F 1 "d_inverter" H 30800 13250 60 0000 C CNN
+F 2 "" H 30850 13050 60 0000 C CNN
+F 3 "" H 30850 13050 60 0000 C CNN
+ 1 30800 13100
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U37
+U 1 1 686567FD
+P 28750 15550
+F 0 "U37" H 28750 15550 60 0000 C CNN
+F 1 "d_nor" H 28800 15650 60 0000 C CNN
+F 2 "" H 28750 15550 60 0000 C CNN
+F 3 "" H 28750 15550 60 0000 C CNN
+ 1 28750 15550
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U39
+U 1 1 68656807
+P 29300 16900
+F 0 "U39" H 29300 16900 60 0000 C CNN
+F 1 "d_and" H 29350 17000 60 0000 C CNN
+F 2 "" H 29300 16900 60 0000 C CNN
+F 3 "" H 29300 16900 60 0000 C CNN
+ 1 29300 16900
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nand U43
+U 1 1 68656813
+P 30800 14200
+F 0 "U43" H 30800 14200 60 0000 C CNN
+F 1 "d_nand" H 30850 14300 60 0000 C CNN
+F 2 "" H 30800 14200 60 0000 C CNN
+F 3 "" H 30800 14200 60 0000 C CNN
+ 1 30800 14200
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U36
+U 1 1 68656819
+P 28550 17950
+F 0 "U36" H 28550 17850 60 0000 C CNN
+F 1 "d_inverter" H 28550 18100 60 0000 C CNN
+F 2 "" H 28600 17900 60 0000 C CNN
+F 3 "" H 28600 17900 60 0000 C CNN
+ 1 28550 17950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U41
+U 1 1 6865681F
+P 29750 17950
+F 0 "U41" H 29750 17850 60 0000 C CNN
+F 1 "d_inverter" H 29750 18100 60 0000 C CNN
+F 2 "" H 29800 17900 60 0000 C CNN
+F 3 "" H 29800 17900 60 0000 C CNN
+ 1 29750 17950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U38
+U 1 1 6865682B
+P 29150 19550
+F 0 "U38" H 29150 19550 60 0000 C CNN
+F 1 "d_and" H 29200 19650 60 0000 C CNN
+F 2 "" H 29150 19550 60 0000 C CNN
+F 3 "" H 29150 19550 60 0000 C CNN
+ 1 29150 19550
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6865684D
+P 27850 10400
+F 0 "U1" H 27900 10500 30 0000 C CNN
+F 1 "PORT" H 27850 10400 30 0000 C CNN
+F 2 "" H 27850 10400 60 0000 C CNN
+F 3 "" H 27850 10400 60 0000 C CNN
+ 5 27850 10400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68656853
+P 29100 11700
+F 0 "U1" H 29150 11800 30 0000 C CNN
+F 1 "PORT" H 29100 11700 30 0000 C CNN
+F 2 "" H 29100 11700 60 0000 C CNN
+F 3 "" H 29100 11700 60 0000 C CNN
+ 6 29100 11700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 68656859
+P 28950 20650
+F 0 "U1" H 29000 20750 30 0000 C CNN
+F 1 "PORT" H 28950 20650 30 0000 C CNN
+F 2 "" H 28950 20650 60 0000 C CNN
+F 3 "" H 28950 20650 60 0000 C CNN
+ 12 28950 20650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U49
+U 1 1 6865686B
+P 37400 12050
+F 0 "U49" H 37400 12000 60 0000 C CNN
+F 1 "d_buffer" H 37400 12100 60 0000 C CNN
+F 2 "" H 37400 12050 60 0000 C CNN
+F 3 "" H 37400 12050 60 0000 C CNN
+ 1 37400 12050
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U48
+U 1 1 6865687D
+P 37400 10950
+F 0 "U48" H 37400 10850 60 0000 C CNN
+F 1 "d_inverter" H 37400 11100 60 0000 C CNN
+F 2 "" H 37450 10900 60 0000 C CNN
+F 3 "" H 37450 10900 60 0000 C CNN
+ 1 37400 10950
+ 0 1 1 0
+$EndComp
+$Comp
+L 3_and X4
+U 1 1 68656886
+P 37350 13650
+F 0 "X4" H 37450 13600 60 0000 C CNN
+F 1 "3_and" H 37500 13800 60 0000 C CNN
+F 2 "" H 37350 13650 60 0000 C CNN
+F 3 "" H 37350 13650 60 0000 C CNN
+ 1 37350 13650
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U54
+U 1 1 68656891
+P 38600 13750
+F 0 "U54" H 38600 13750 60 0000 C CNN
+F 1 "d_and" H 38650 13850 60 0000 C CNN
+F 2 "" H 38600 13750 60 0000 C CNN
+F 3 "" H 38600 13750 60 0000 C CNN
+ 1 38600 13750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U56
+U 1 1 68656897
+P 40050 12750
+F 0 "U56" H 40050 12650 60 0000 C CNN
+F 1 "d_inverter" H 40050 12900 60 0000 C CNN
+F 2 "" H 40100 12700 60 0000 C CNN
+F 3 "" H 40100 12700 60 0000 C CNN
+ 1 40050 12750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U51
+U 1 1 686568AB
+P 38000 15200
+F 0 "U51" H 38000 15200 60 0000 C CNN
+F 1 "d_nor" H 38050 15300 60 0000 C CNN
+F 2 "" H 38000 15200 60 0000 C CNN
+F 3 "" H 38000 15200 60 0000 C CNN
+ 1 38000 15200
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U53
+U 1 1 686568B5
+P 38550 16550
+F 0 "U53" H 38550 16550 60 0000 C CNN
+F 1 "d_and" H 38600 16650 60 0000 C CNN
+F 2 "" H 38550 16550 60 0000 C CNN
+F 3 "" H 38550 16550 60 0000 C CNN
+ 1 38550 16550
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nand U57
+U 1 1 686568C1
+P 40050 13850
+F 0 "U57" H 40050 13850 60 0000 C CNN
+F 1 "d_nand" H 40100 13950 60 0000 C CNN
+F 2 "" H 40050 13850 60 0000 C CNN
+F 3 "" H 40050 13850 60 0000 C CNN
+ 1 40050 13850
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U50
+U 1 1 686568C7
+P 37800 17600
+F 0 "U50" H 37800 17500 60 0000 C CNN
+F 1 "d_inverter" H 37800 17750 60 0000 C CNN
+F 2 "" H 37850 17550 60 0000 C CNN
+F 3 "" H 37850 17550 60 0000 C CNN
+ 1 37800 17600
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U55
+U 1 1 686568CD
+P 39000 17600
+F 0 "U55" H 39000 17500 60 0000 C CNN
+F 1 "d_inverter" H 39000 17750 60 0000 C CNN
+F 2 "" H 39050 17550 60 0000 C CNN
+F 3 "" H 39050 17550 60 0000 C CNN
+ 1 39000 17600
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U52
+U 1 1 686568D9
+P 38400 19200
+F 0 "U52" H 38400 19200 60 0000 C CNN
+F 1 "d_and" H 38450 19300 60 0000 C CNN
+F 2 "" H 38400 19200 60 0000 C CNN
+F 3 "" H 38400 19200 60 0000 C CNN
+ 1 38400 19200
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686568FB
+P 37100 10050
+F 0 "U1" H 37150 10150 30 0000 C CNN
+F 1 "PORT" H 37100 10050 30 0000 C CNN
+F 2 "" H 37100 10050 60 0000 C CNN
+F 3 "" H 37100 10050 60 0000 C CNN
+ 11 37100 10050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68656901
+P 38350 11350
+F 0 "U1" H 38400 11450 30 0000 C CNN
+F 1 "PORT" H 38350 11350 30 0000 C CNN
+F 2 "" H 38350 11350 60 0000 C CNN
+F 3 "" H 38350 11350 60 0000 C CNN
+ 7 38350 11350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 68656907
+P 38200 20300
+F 0 "U1" H 38250 20400 30 0000 C CNN
+F 1 "PORT" H 38200 20300 30 0000 C CNN
+F 2 "" H 38200 20300 60 0000 C CNN
+F 3 "" H 38200 20300 60 0000 C CNN
+ 10 38200 20300
+ 1 0 0 -1
+$EndComp
+Text Label 7800 10700 0 60 ~ 0
+MR_Bar
+Text Label 9350 10650 0 60 ~ 0
+E_Bar
+Text Label 10800 10600 0 60 ~ 0
+S0_Bar
+Text Label 12000 11800 0 60 ~ 0
+D0
+Text Label 20050 10150 0 60 ~ 0
+S1_Bar
+Text Label 21250 11500 0 60 ~ 0
+D1
+Text Label 28150 10600 0 60 ~ 0
+S2_Bar
+Text Label 29350 12000 0 60 ~ 0
+D2
+Text Label 38600 11650 0 60 ~ 0
+D3
+Text Label 37400 10250 0 60 ~ 0
+S3_Bar
+Text Label 11850 20450 0 60 ~ 0
+Q0
+Text Label 21100 20100 0 60 ~ 0
+Q1
+Text Label 29200 20500 0 60 ~ 0
+Q2
+Text Label 38450 20100 0 60 ~ 0
+Q3
+Wire Wire Line
+ 10800 11850 10800 11550
+Wire Wire Line
+ 9350 11850 9350 11600
+Wire Wire Line
+ 7800 11900 7800 11600
+Wire Wire Line
+ 10800 13000 10800 13600
+Wire Wire Line
+ 10900 13600 10900 13350
+Wire Wire Line
+ 9350 13350 11300 13350
+Wire Wire Line
+ 9350 13350 9350 13000
+Wire Wire Line
+ 13450 13700 13450 13350
+Wire Wire Line
+ 13550 13700 13550 13450
+Wire Wire Line
+ 12100 13450 13950 13450
+Wire Wire Line
+ 12100 13450 12100 13600
+Wire Wire Line
+ 12000 11650 12000 13600
+Wire Wire Line
+ 10700 13600 10700 13450
+Wire Wire Line
+ 10700 13450 12000 13450
+Connection ~ 12000 13450
+Wire Wire Line
+ 13450 12750 13450 12600
+Wire Wire Line
+ 11300 12600 16200 12600
+Wire Wire Line
+ 11300 13350 11300 12600
+Connection ~ 10900 13350
+Wire Wire Line
+ 11500 15050 12050 15050
+Wire Wire Line
+ 12050 15050 12050 14500
+Wire Wire Line
+ 11400 15050 10800 15050
+Wire Wire Line
+ 10800 15050 10800 14450
+Wire Wire Line
+ 11450 15950 11450 16300
+Wire Wire Line
+ 11450 16300 11950 16300
+Wire Wire Line
+ 11950 16300 11950 16400
+Wire Wire Line
+ 12050 16400 12050 16300
+Wire Wire Line
+ 12050 16300 13500 16300
+Wire Wire Line
+ 13500 16300 13500 14600
+Wire Wire Line
+ 11200 17600 12000 17600
+Wire Wire Line
+ 12000 17600 12000 17300
+Wire Wire Line
+ 12400 17600 12250 17600
+Wire Wire Line
+ 12250 17600 12250 17400
+Wire Wire Line
+ 7800 17400 16500 17400
+Wire Wire Line
+ 7800 17400 7800 13050
+Wire Wire Line
+ 11200 18200 11200 18700
+Wire Wire Line
+ 11200 18700 11800 18700
+Wire Wire Line
+ 11800 18700 11800 19050
+Wire Wire Line
+ 12400 18200 12400 18700
+Wire Wire Line
+ 12400 18700 11900 18700
+Wire Wire Line
+ 11900 18700 11900 19050
+Wire Wire Line
+ 11850 19950 11850 20600
+Wire Wire Line
+ 11850 20250 13950 20250
+Wire Wire Line
+ 13950 20250 13950 13450
+Connection ~ 13550 13450
+Connection ~ 11850 20250
+Wire Wire Line
+ 7800 11000 7800 10500
+Wire Wire Line
+ 9350 11000 9350 10450
+Wire Wire Line
+ 10800 10950 10800 10350
+Wire Wire Line
+ 10800 10350 10750 10350
+Wire Wire Line
+ 20050 11500 20050 11200
+Wire Wire Line
+ 20050 12650 20050 13250
+Wire Wire Line
+ 20150 13250 20150 13000
+Wire Wire Line
+ 18600 13000 20550 13000
+Wire Wire Line
+ 18600 8200 18600 13000
+Wire Wire Line
+ 22700 13350 22700 13000
+Wire Wire Line
+ 22800 13350 22800 13100
+Wire Wire Line
+ 21350 13100 23200 13100
+Wire Wire Line
+ 21350 13100 21350 13250
+Wire Wire Line
+ 21250 11300 21250 13250
+Wire Wire Line
+ 19950 13250 19950 13100
+Wire Wire Line
+ 19950 13100 21250 13100
+Connection ~ 21250 13100
+Wire Wire Line
+ 22700 12400 22700 12250
+Wire Wire Line
+ 22700 12250 20550 12250
+Wire Wire Line
+ 20550 12250 20550 13000
+Connection ~ 20150 13000
+Wire Wire Line
+ 20750 14700 21300 14700
+Wire Wire Line
+ 21300 14700 21300 14150
+Wire Wire Line
+ 20650 14700 20050 14700
+Wire Wire Line
+ 20050 14700 20050 14100
+Wire Wire Line
+ 20700 15600 20700 15950
+Wire Wire Line
+ 20700 15950 21200 15950
+Wire Wire Line
+ 21200 15950 21200 16050
+Wire Wire Line
+ 21300 16050 21300 15950
+Wire Wire Line
+ 21300 15950 22750 15950
+Wire Wire Line
+ 22750 15950 22750 14250
+Wire Wire Line
+ 20450 17250 21250 17250
+Wire Wire Line
+ 21250 17250 21250 16950
+Wire Wire Line
+ 21650 17250 21500 17250
+Wire Wire Line
+ 21500 17250 21500 17050
+Wire Wire Line
+ 21500 17050 17050 17050
+Wire Wire Line
+ 17050 17050 17050 9200
+Wire Wire Line
+ 20450 17850 20450 18350
+Wire Wire Line
+ 20450 18350 21050 18350
+Wire Wire Line
+ 21050 18350 21050 18700
+Wire Wire Line
+ 21650 17850 21650 18350
+Wire Wire Line
+ 21650 18350 21150 18350
+Wire Wire Line
+ 21150 18350 21150 18700
+Wire Wire Line
+ 21100 19600 21100 20250
+Wire Wire Line
+ 21100 19900 23200 19900
+Wire Wire Line
+ 23200 19900 23200 13100
+Connection ~ 22800 13100
+Connection ~ 21100 19900
+Wire Wire Line
+ 20050 10600 20050 10000
+Wire Wire Line
+ 20050 10000 20000 10000
+Wire Wire Line
+ 28150 11900 28150 11600
+Wire Wire Line
+ 28150 13050 28150 13650
+Wire Wire Line
+ 28250 13650 28250 13400
+Wire Wire Line
+ 26700 13400 28650 13400
+Wire Wire Line
+ 26700 8200 26700 13400
+Wire Wire Line
+ 30800 13750 30800 13400
+Wire Wire Line
+ 30900 13750 30900 13500
+Wire Wire Line
+ 29450 13500 31300 13500
+Wire Wire Line
+ 29450 13500 29450 13650
+Wire Wire Line
+ 29350 11700 29350 13650
+Wire Wire Line
+ 28050 13650 28050 13500
+Wire Wire Line
+ 28050 13500 29350 13500
+Connection ~ 29350 13500
+Wire Wire Line
+ 30800 12800 30800 12650
+Wire Wire Line
+ 30800 12650 28650 12650
+Wire Wire Line
+ 28650 12650 28650 13400
+Connection ~ 28250 13400
+Wire Wire Line
+ 28850 15100 29400 15100
+Wire Wire Line
+ 29400 15100 29400 14550
+Wire Wire Line
+ 28750 15100 28150 15100
+Wire Wire Line
+ 28150 15100 28150 14500
+Wire Wire Line
+ 28800 16000 28800 16350
+Wire Wire Line
+ 28800 16350 29300 16350
+Wire Wire Line
+ 29300 16350 29300 16450
+Wire Wire Line
+ 29400 16450 29400 16350
+Wire Wire Line
+ 29400 16350 30850 16350
+Wire Wire Line
+ 30850 16350 30850 14650
+Wire Wire Line
+ 28550 17650 29350 17650
+Wire Wire Line
+ 29350 17650 29350 17350
+Wire Wire Line
+ 29750 17650 29600 17650
+Wire Wire Line
+ 29600 17650 29600 17450
+Wire Wire Line
+ 29600 17450 25150 17450
+Wire Wire Line
+ 25150 17450 25150 9200
+Wire Wire Line
+ 28550 18250 28550 18750
+Wire Wire Line
+ 28550 18750 29150 18750
+Wire Wire Line
+ 29150 18750 29150 19100
+Wire Wire Line
+ 29750 18250 29750 18750
+Wire Wire Line
+ 29750 18750 29250 18750
+Wire Wire Line
+ 29250 18750 29250 19100
+Wire Wire Line
+ 29200 20000 29200 20650
+Wire Wire Line
+ 29200 20300 31300 20300
+Wire Wire Line
+ 31300 20300 31300 13500
+Connection ~ 30900 13500
+Connection ~ 29200 20300
+Wire Wire Line
+ 28150 11000 28150 10400
+Wire Wire Line
+ 28150 10400 28100 10400
+Wire Wire Line
+ 37400 11550 37400 11250
+Wire Wire Line
+ 37400 12700 37400 13300
+Wire Wire Line
+ 37500 13300 37500 13050
+Wire Wire Line
+ 35950 13050 37900 13050
+Wire Wire Line
+ 35950 8200 35950 13050
+Wire Wire Line
+ 40050 13400 40050 13050
+Wire Wire Line
+ 40150 13400 40150 13150
+Wire Wire Line
+ 38700 13150 40550 13150
+Wire Wire Line
+ 38700 13150 38700 13300
+Wire Wire Line
+ 38600 11350 38600 13300
+Wire Wire Line
+ 37300 13300 37300 13150
+Wire Wire Line
+ 37300 13150 38600 13150
+Connection ~ 38600 13150
+Wire Wire Line
+ 40050 12450 40050 12300
+Wire Wire Line
+ 40050 12300 37900 12300
+Wire Wire Line
+ 37900 12300 37900 13050
+Connection ~ 37500 13050
+Wire Wire Line
+ 38100 14750 38650 14750
+Wire Wire Line
+ 38650 14750 38650 14200
+Wire Wire Line
+ 38000 14750 37400 14750
+Wire Wire Line
+ 37400 14750 37400 14150
+Wire Wire Line
+ 38050 15650 38050 16000
+Wire Wire Line
+ 38050 16000 38550 16000
+Wire Wire Line
+ 38550 16000 38550 16100
+Wire Wire Line
+ 38650 16100 38650 16000
+Wire Wire Line
+ 38650 16000 40100 16000
+Wire Wire Line
+ 40100 16000 40100 14300
+Wire Wire Line
+ 37800 17300 38600 17300
+Wire Wire Line
+ 38600 17300 38600 17000
+Wire Wire Line
+ 39000 17300 38850 17300
+Wire Wire Line
+ 38850 17300 38850 17100
+Wire Wire Line
+ 38850 17100 34400 17100
+Wire Wire Line
+ 34400 17100 34400 9200
+Wire Wire Line
+ 37800 17900 37800 18400
+Wire Wire Line
+ 37800 18400 38400 18400
+Wire Wire Line
+ 38400 18400 38400 18750
+Wire Wire Line
+ 39000 17900 39000 18400
+Wire Wire Line
+ 39000 18400 38500 18400
+Wire Wire Line
+ 38500 18400 38500 18750
+Wire Wire Line
+ 38450 19650 38450 20300
+Wire Wire Line
+ 38450 19950 40550 19950
+Wire Wire Line
+ 40550 19950 40550 13150
+Connection ~ 40150 13150
+Connection ~ 38450 19950
+Wire Wire Line
+ 37400 10650 37400 10050
+Wire Wire Line
+ 37400 10050 37350 10050
+Wire Wire Line
+ 34400 9200 16500 9200
+Connection ~ 25150 9200
+Connection ~ 17050 9200
+Wire Wire Line
+ 16200 8200 35950 8200
+Connection ~ 26700 8200
+Wire Wire Line
+ 16200 12600 16200 8200
+Connection ~ 18600 8200
+Connection ~ 13450 12600
+Wire Wire Line
+ 16500 9200 16500 17400
+Connection ~ 12250 17400
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sub b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sub
new file mode 100644
index 000000000..843dc5120
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH.sub
@@ -0,0 +1,187 @@
+* Subcircuit DSR_LATCH
+.subckt DSR_LATCH /e_bar /s0_bar /d0 /d1 /s2_bar /d2 /d3 /mr_bar /q3 /s3_bar /q2 /q1 /s1_bar /q0
+* c:\fossee\esim\library\subcircuitlibrary\dsr_latch\dsr_latch.cir
+.include 3_and.sub
+* u3 net-_u2-pad2_ net-_u13-pad1_ d_buffer
+* u5 net-_u4-pad2_ net-_u14-pad1_ d_buffer
+* u7 net-_u6-pad2_ net-_u7-pad2_ d_buffer
+* u2 /mr_bar net-_u2-pad2_ d_inverter
+* u4 /e_bar net-_u4-pad2_ d_inverter
+* u6 /s0_bar net-_u6-pad2_ d_inverter
+x1 net-_u14-pad1_ net-_u7-pad2_ /d0 net-_u9-pad2_ 3_and
+* u12 /q0 /d0 net-_u12-pad3_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u9 net-_u12-pad3_ net-_u9-pad2_ net-_u11-pad2_ d_nor
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u15 /q0 net-_u14-pad2_ net-_u11-pad1_ d_nand
+* u8 net-_u11-pad3_ net-_u10-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u10-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ /q0 d_and
+* u21 net-_u20-pad2_ net-_u21-pad2_ d_buffer
+* u20 /s1_bar net-_u20-pad2_ d_inverter
+x2 net-_u14-pad1_ net-_u21-pad2_ /d1 net-_u23-pad2_ 3_and
+* u26 /q1 /d1 net-_u23-pad1_ d_and
+* u28 net-_u14-pad1_ net-_u28-pad2_ d_inverter
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_nor
+* u25 net-_u25-pad1_ net-_u23-pad3_ net-_u22-pad1_ d_and
+* u29 /q1 net-_u28-pad2_ net-_u25-pad1_ d_nand
+* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter
+* u27 net-_u13-pad1_ net-_u24-pad1_ d_inverter
+* u24 net-_u24-pad1_ net-_u22-pad2_ /q1 d_and
+* u35 net-_u34-pad2_ net-_u35-pad2_ d_buffer
+* u34 /s2_bar net-_u34-pad2_ d_inverter
+x3 net-_u14-pad1_ net-_u35-pad2_ /d2 net-_u37-pad2_ 3_and
+* u40 /q2 /d2 net-_u37-pad1_ d_and
+* u42 net-_u14-pad1_ net-_u42-pad2_ d_inverter
+* u37 net-_u37-pad1_ net-_u37-pad2_ net-_u37-pad3_ d_nor
+* u39 net-_u39-pad1_ net-_u37-pad3_ net-_u36-pad1_ d_and
+* u43 /q2 net-_u42-pad2_ net-_u39-pad1_ d_nand
+* u36 net-_u36-pad1_ net-_u36-pad2_ d_inverter
+* u41 net-_u13-pad1_ net-_u38-pad1_ d_inverter
+* u38 net-_u38-pad1_ net-_u36-pad2_ /q2 d_and
+* u49 net-_u48-pad2_ net-_u49-pad2_ d_buffer
+* u48 /s3_bar net-_u48-pad2_ d_inverter
+x4 net-_u14-pad1_ net-_u49-pad2_ /d3 net-_u51-pad2_ 3_and
+* u54 /q3 /d3 net-_u51-pad1_ d_and
+* u56 net-_u14-pad1_ net-_u56-pad2_ d_inverter
+* u51 net-_u51-pad1_ net-_u51-pad2_ net-_u51-pad3_ d_nor
+* u53 net-_u53-pad1_ net-_u51-pad3_ net-_u50-pad1_ d_and
+* u57 /q3 net-_u56-pad2_ net-_u53-pad1_ d_nand
+* u50 net-_u50-pad1_ net-_u50-pad2_ d_inverter
+* u55 net-_u13-pad1_ net-_u52-pad1_ d_inverter
+* u52 net-_u52-pad1_ net-_u50-pad2_ /q3 d_and
+a1 net-_u2-pad2_ net-_u13-pad1_ u3
+a2 net-_u4-pad2_ net-_u14-pad1_ u5
+a3 net-_u6-pad2_ net-_u7-pad2_ u7
+a4 /mr_bar net-_u2-pad2_ u2
+a5 /e_bar net-_u4-pad2_ u4
+a6 /s0_bar net-_u6-pad2_ u6
+a7 [/q0 /d0 ] net-_u12-pad3_ u12
+a8 net-_u14-pad1_ net-_u14-pad2_ u14
+a9 [net-_u12-pad3_ net-_u9-pad2_ ] net-_u11-pad2_ u9
+a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a11 [/q0 net-_u14-pad2_ ] net-_u11-pad1_ u15
+a12 net-_u11-pad3_ net-_u10-pad2_ u8
+a13 net-_u13-pad1_ net-_u10-pad1_ u13
+a14 [net-_u10-pad1_ net-_u10-pad2_ ] /q0 u10
+a15 net-_u20-pad2_ net-_u21-pad2_ u21
+a16 /s1_bar net-_u20-pad2_ u20
+a17 [/q1 /d1 ] net-_u23-pad1_ u26
+a18 net-_u14-pad1_ net-_u28-pad2_ u28
+a19 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a20 [net-_u25-pad1_ net-_u23-pad3_ ] net-_u22-pad1_ u25
+a21 [/q1 net-_u28-pad2_ ] net-_u25-pad1_ u29
+a22 net-_u22-pad1_ net-_u22-pad2_ u22
+a23 net-_u13-pad1_ net-_u24-pad1_ u27
+a24 [net-_u24-pad1_ net-_u22-pad2_ ] /q1 u24
+a25 net-_u34-pad2_ net-_u35-pad2_ u35
+a26 /s2_bar net-_u34-pad2_ u34
+a27 [/q2 /d2 ] net-_u37-pad1_ u40
+a28 net-_u14-pad1_ net-_u42-pad2_ u42
+a29 [net-_u37-pad1_ net-_u37-pad2_ ] net-_u37-pad3_ u37
+a30 [net-_u39-pad1_ net-_u37-pad3_ ] net-_u36-pad1_ u39
+a31 [/q2 net-_u42-pad2_ ] net-_u39-pad1_ u43
+a32 net-_u36-pad1_ net-_u36-pad2_ u36
+a33 net-_u13-pad1_ net-_u38-pad1_ u41
+a34 [net-_u38-pad1_ net-_u36-pad2_ ] /q2 u38
+a35 net-_u48-pad2_ net-_u49-pad2_ u49
+a36 /s3_bar net-_u48-pad2_ u48
+a37 [/q3 /d3 ] net-_u51-pad1_ u54
+a38 net-_u14-pad1_ net-_u56-pad2_ u56
+a39 [net-_u51-pad1_ net-_u51-pad2_ ] net-_u51-pad3_ u51
+a40 [net-_u53-pad1_ net-_u51-pad3_ ] net-_u50-pad1_ u53
+a41 [/q3 net-_u56-pad2_ ] net-_u53-pad1_ u57
+a42 net-_u50-pad1_ net-_u50-pad2_ u50
+a43 net-_u13-pad1_ net-_u52-pad1_ u55
+a44 [net-_u52-pad1_ net-_u50-pad2_ ] /q3 u52
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u5 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u7 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u21 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u35 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u49 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u56 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends DSR_LATCH
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH_Previous_Values.xml b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH_Previous_Values.xml
new file mode 100644
index 000000000..fab8123be
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/DSR_LATCH_Previous_Values.xml
@@ -0,0 +1 @@
+d_bufferd_bufferd_bufferd_inverterd_inverterd_inverterd_andd_inverterd_nord_andd_nandd_inverterd_inverterd_andd_bufferd_inverterd_andd_inverterd_nord_andd_nandd_inverterd_inverterd_andd_bufferd_inverterd_andd_inverterd_nord_andd_nandd_inverterd_inverterd_andd_bufferd_inverterd_andd_inverterd_nord_andd_nandd_inverterd_inverterd_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/DSR_LATCH/analysis b/library/SubcircuitLibrary/DSR_LATCH/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/DSR_LATCH/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICL7611/D.lib b/library/SubcircuitLibrary/ICL7611/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611-cache.lib b/library/SubcircuitLibrary/ICL7611/ICL7611-cache.lib
new file mode 100644
index 000000000..fef1592e2
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/ICL7611-cache.lib
@@ -0,0 +1,162 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.bak b/library/SubcircuitLibrary/ICL7611/ICL7611.bak
new file mode 100644
index 000000000..efdb5b3a4
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/ICL7611.bak
@@ -0,0 +1,926 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M2
+U 1 1 68596BF9
+P 5150 6000
+F 0 "M2" H 5100 6050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5200 6150 50 0000 R CNN
+F 2 "" H 5400 6100 29 0000 C CNN
+F 3 "" H 5200 6000 60 0000 C CNN
+ 1 5150 6000
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 68596C54
+P 6400 6000
+F 0 "M4" H 6350 6050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 6450 6150 50 0000 R CNN
+F 2 "" H 6650 6100 29 0000 C CNN
+F 3 "" H 6450 6000 60 0000 C CNN
+ 1 6400 6000
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 68596C8C
+P 4950 4800
+F 0 "R3" H 5000 4930 50 0000 C CNN
+F 1 "resistor" H 5000 4750 50 0000 C CNN
+F 2 "" H 5000 4780 30 0000 C CNN
+F 3 "" V 5000 4850 30 0000 C CNN
+ 1 4950 4800
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 68596CD5
+P 6500 4800
+F 0 "R4" H 6550 4930 50 0000 C CNN
+F 1 "resistor" H 6550 4750 50 0000 C CNN
+F 2 "" H 6550 4780 30 0000 C CNN
+F 3 "" V 6550 4850 30 0000 C CNN
+ 1 6500 4800
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_MOS_N M1
+U 1 1 68596DA8
+P 4800 6850
+F 0 "M1" H 4800 6700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 4900 6800 50 0000 R CNN
+F 2 "" H 5100 6550 29 0000 C CNN
+F 3 "" H 4900 6650 60 0000 C CNN
+ 1 4800 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 68596DF1
+P 6750 6800
+F 0 "M5" H 6750 6650 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6850 6750 50 0000 R CNN
+F 2 "" H 7050 6500 29 0000 C CNN
+F 3 "" H 6850 6600 60 0000 C CNN
+ 1 6750 6800
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M3
+U 1 1 68596FB8
+P 6000 12200
+F 0 "M3" H 6000 12050 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6100 12150 50 0000 R CNN
+F 2 "" H 6300 11900 29 0000 C CNN
+F 3 "" H 6100 12000 60 0000 C CNN
+ 1 6000 12200
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M6
+U 1 1 685976F9
+P 8650 11500
+F 0 "M6" H 8650 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 8750 11450 50 0000 R CNN
+F 2 "" H 8950 11200 29 0000 C CNN
+F 3 "" H 8750 11300 60 0000 C CNN
+ 1 8650 11500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M7
+U 1 1 68597A10
+P 10300 11500
+F 0 "M7" H 10300 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10400 11450 50 0000 R CNN
+F 2 "" H 10600 11200 29 0000 C CNN
+F 3 "" H 10400 11300 60 0000 C CNN
+ 1 10300 11500
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 68597AEE
+P 11650 12750
+F 0 "M10" H 11650 12600 50 0000 R CNN
+F 1 "eSim_MOS_N" H 11750 12700 50 0000 R CNN
+F 2 "" H 11950 12450 29 0000 C CNN
+F 3 "" H 11750 12550 60 0000 C CNN
+ 1 11650 12750
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M12
+U 1 1 68597B63
+P 12500 11500
+F 0 "M12" H 12500 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 12600 11450 50 0000 R CNN
+F 2 "" H 12800 11200 29 0000 C CNN
+F 3 "" H 12600 11300 60 0000 C CNN
+ 1 12500 11500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6550 5800 6550 5000
+Wire Wire Line
+ 6650 5850 6650 5600
+Wire Wire Line
+ 6650 5600 6550 5600
+Connection ~ 6550 5600
+Wire Wire Line
+ 5000 5800 5000 5000
+Wire Wire Line
+ 4900 5850 4900 5600
+Wire Wire Line
+ 4900 5600 5000 5600
+Connection ~ 5000 5600
+Wire Wire Line
+ 5300 6000 6250 6000
+Wire Wire Line
+ 5000 6850 5000 6200
+Wire Wire Line
+ 6550 6800 6550 6200
+Wire Wire Line
+ 6050 6000 6050 6500
+Wire Wire Line
+ 6050 6500 6550 6500
+Connection ~ 6550 6500
+Connection ~ 6050 6000
+Wire Wire Line
+ 5000 7250 5000 7800
+Wire Wire Line
+ 5000 7800 6550 7800
+Wire Wire Line
+ 6550 7800 6550 7200
+Wire Wire Line
+ 5800 12200 5800 7800
+Connection ~ 5800 7800
+Wire Wire Line
+ 5800 12600 5800 14400
+Wire Wire Line
+ 2800 14400 28900 14400
+Wire Wire Line
+ 5700 12550 5700 14400
+Connection ~ 5800 14400
+Wire Wire Line
+ 5000 4700 5000 2650
+Wire Wire Line
+ 2500 2650 29050 2650
+Wire Wire Line
+ 6550 4700 6550 2650
+Connection ~ 6550 2650
+Wire Wire Line
+ 5000 5200 3300 5200
+Wire Wire Line
+ 3300 5200 3300 5150
+Connection ~ 5000 5200
+Wire Wire Line
+ 7350 12400 6100 12400
+Wire Wire Line
+ 7350 11150 7350 12400
+Wire Wire Line
+ 7350 11700 8550 11700
+Wire Wire Line
+ 7350 11150 11450 11150
+Wire Wire Line
+ 8850 11150 8850 11500
+Connection ~ 7350 11700
+Wire Wire Line
+ 8850 11900 8850 14400
+Connection ~ 8850 14400
+Wire Wire Line
+ 8950 11850 8950 14400
+Connection ~ 8950 14400
+Wire Wire Line
+ 10400 11700 12400 11700
+Wire Wire Line
+ 10100 11900 10100 12400
+Wire Wire Line
+ 10000 12400 12800 12400
+Wire Wire Line
+ 12700 12400 12700 11900
+Wire Wire Line
+ 11450 12750 11450 12400
+Connection ~ 11450 12400
+Wire Wire Line
+ 10100 11150 10100 11500
+Connection ~ 8850 11150
+Wire Wire Line
+ 11450 11150 11450 12000
+Connection ~ 11450 11700
+Connection ~ 10100 11150
+Wire Wire Line
+ 11450 13150 11450 14400
+Connection ~ 11450 14400
+Wire Wire Line
+ 11350 13100 11350 14400
+Connection ~ 11350 14400
+Wire Wire Line
+ 10000 11850 10000 12400
+Connection ~ 10100 12400
+Wire Wire Line
+ 12800 12400 12800 11850
+Connection ~ 12700 12400
+$Comp
+L eSim_MOS_N M13
+U 1 1 68598199
+P 15050 11500
+F 0 "M13" H 15050 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 15150 11450 50 0000 R CNN
+F 2 "" H 15350 11200 29 0000 C CNN
+F 3 "" H 15150 11300 60 0000 C CNN
+ 1 15050 11500
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 12700 11500 12700 11250
+Wire Wire Line
+ 12400 11250 14850 11250
+Wire Wire Line
+ 14850 11250 14850 11500
+Wire Wire Line
+ 14850 11900 14850 14400
+Connection ~ 14850 14400
+Wire Wire Line
+ 14750 11850 14750 14400
+Connection ~ 14750 14400
+Wire Wire Line
+ 11450 12000 15650 12000
+Wire Wire Line
+ 15650 12000 15650 11700
+Wire Wire Line
+ 15150 11700 18600 11700
+$Comp
+L eSim_MOS_N M15
+U 1 1 68598842
+P 18700 11500
+F 0 "M15" H 18700 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 18800 11450 50 0000 R CNN
+F 2 "" H 19000 11200 29 0000 C CNN
+F 3 "" H 18800 11300 60 0000 C CNN
+ 1 18700 11500
+ 1 0 0 -1
+$EndComp
+Connection ~ 15650 11700
+Wire Wire Line
+ 18900 11900 18900 14400
+Connection ~ 18900 14400
+Wire Wire Line
+ 19000 11850 19000 14400
+Connection ~ 19000 14400
+$Comp
+L eSim_MOS_N M18
+U 1 1 68598CA3
+P 22300 11500
+F 0 "M18" H 22300 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 22400 11450 50 0000 R CNN
+F 2 "" H 22600 11200 29 0000 C CNN
+F 3 "" H 22400 11300 60 0000 C CNN
+ 1 22300 11500
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 22100 11900 22100 14400
+Connection ~ 22100 14400
+Wire Wire Line
+ 22000 11850 22000 14400
+Connection ~ 22000 14400
+$Comp
+L eSim_MOS_N M19
+U 1 1 68599072
+P 24850 11500
+F 0 "M19" H 24850 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 24950 11450 50 0000 R CNN
+F 2 "" H 25150 11200 29 0000 C CNN
+F 3 "" H 24950 11300 60 0000 C CNN
+ 1 24850 11500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 25050 11900 25050 14400
+Connection ~ 25050 14400
+Wire Wire Line
+ 25150 11850 25150 14400
+Connection ~ 25150 14400
+Wire Wire Line
+ 22400 11700 24750 11700
+$Comp
+L resistor R7
+U 1 1 685995FF
+P 16100 14950
+F 0 "R7" H 16150 15080 50 0000 C CNN
+F 1 "470k" H 16150 14900 50 0000 C CNN
+F 2 "" H 16150 14930 30 0000 C CNN
+F 3 "" V 16150 15000 30 0000 C CNN
+ 1 16100 14950
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R5
+U 1 1 68599992
+P 10500 3200
+F 0 "R5" H 10550 3330 50 0000 C CNN
+F 1 "900k" H 10550 3150 50 0000 C CNN
+F 2 "" H 10550 3180 30 0000 C CNN
+F 3 "" V 10550 3250 30 0000 C CNN
+ 1 10500 3200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R6
+U 1 1 68599B69
+P 10500 4350
+F 0 "R6" H 10550 4480 50 0000 C CNN
+F 1 "100k" H 10550 4300 50 0000 C CNN
+F 2 "" H 10550 4330 30 0000 C CNN
+F 3 "" V 10550 4400 30 0000 C CNN
+ 1 10500 4350
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_MOS_P M8
+U 1 1 68599C9A
+P 10700 5450
+F 0 "M8" H 10650 5500 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10750 5600 50 0000 R CNN
+F 2 "" H 10950 5550 29 0000 C CNN
+F 3 "" H 10750 5450 60 0000 C CNN
+ 1 10700 5450
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 10550 5650 10550 11150
+Connection ~ 10550 11150
+Wire Wire Line
+ 10550 5250 10550 4550
+Wire Wire Line
+ 10550 4250 10550 3400
+Wire Wire Line
+ 10550 3100 10550 2650
+Connection ~ 10550 2650
+$Comp
+L eSim_MOS_P M11
+U 1 1 6859A1ED
+P 12250 5400
+F 0 "M11" H 12200 5450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 12300 5550 50 0000 R CNN
+F 2 "" H 12500 5500 29 0000 C CNN
+F 3 "" H 12300 5400 60 0000 C CNN
+ 1 12250 5400
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 10850 5450 12100 5450
+Wire Wire Line
+ 12100 5450 12100 5400
+Wire Wire Line
+ 12400 5600 12400 11250
+Connection ~ 12700 11250
+Wire Wire Line
+ 11450 5450 11450 6550
+Wire Wire Line
+ 11450 6550 12400 6550
+Connection ~ 12400 6550
+Connection ~ 11450 5450
+Wire Wire Line
+ 10450 5300 10450 5150
+Wire Wire Line
+ 10450 5150 10550 5150
+Connection ~ 10550 5150
+Wire Wire Line
+ 12400 5200 12400 2650
+Connection ~ 12400 2650
+Wire Wire Line
+ 12500 5250 12500 5050
+Wire Wire Line
+ 12500 5050 12400 5050
+Connection ~ 12400 5050
+$Comp
+L eSim_MOS_P M9
+U 1 1 6859AB95
+P 11600 3450
+F 0 "M9" H 11550 3500 50 0000 R CNN
+F 1 "eSim_MOS_P" H 11650 3600 50 0000 R CNN
+F 2 "" H 11850 3550 29 0000 C CNN
+F 3 "" H 11650 3450 60 0000 C CNN
+ 1 11600 3450
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 11450 3650 11450 3800
+Wire Wire Line
+ 11450 3800 10550 3800
+Connection ~ 10550 3800
+Wire Wire Line
+ 11450 3250 11450 2650
+Connection ~ 11450 2650
+Wire Wire Line
+ 11350 3300 11350 3050
+Wire Wire Line
+ 11350 3050 11450 3050
+Connection ~ 11450 3050
+Wire Wire Line
+ 16150 14850 16150 3450
+Wire Wire Line
+ 16150 3450 11750 3450
+Wire Wire Line
+ 16150 15150 16150 15600
+Wire Wire Line
+ 11750 12950 16150 12950
+Connection ~ 16150 12950
+$Comp
+L eSim_MOS_P M14
+U 1 1 6859B9E9
+P 18500 4400
+F 0 "M14" H 18450 4450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 18550 4550 50 0000 R CNN
+F 2 "" H 18750 4500 29 0000 C CNN
+F 3 "" H 18550 4400 60 0000 C CNN
+ 1 18500 4400
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 18900 11500 18900 5000
+Wire Wire Line
+ 18650 5000 19250 5000
+Wire Wire Line
+ 18650 5000 18650 4600
+$Comp
+L eSim_MOS_P M16
+U 1 1 6859C510
+P 19400 4400
+F 0 "M16" H 19350 4450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 19450 4550 50 0000 R CNN
+F 2 "" H 19650 4500 29 0000 C CNN
+F 3 "" H 19450 4400 60 0000 C CNN
+ 1 19400 4400
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 19250 5000 19250 4600
+Connection ~ 18900 5000
+Wire Wire Line
+ 19250 4200 19250 3750
+Wire Wire Line
+ 19250 3750 18650 3750
+Wire Wire Line
+ 18650 3750 18650 4200
+Wire Wire Line
+ 18750 4250 18750 3900
+Wire Wire Line
+ 18750 3900 18650 3900
+Connection ~ 18650 3900
+Wire Wire Line
+ 19150 4250 19150 3900
+Wire Wire Line
+ 19150 3900 19250 3900
+Connection ~ 19250 3900
+Wire Wire Line
+ 18950 3750 18950 2650
+Connection ~ 18950 2650
+Connection ~ 18950 3750
+$Comp
+L eSim_MOS_P M20
+U 1 1 6859CA78
+P 24900 5450
+F 0 "M20" H 24850 5500 50 0000 R CNN
+F 1 "eSim_MOS_P" H 24950 5600 50 0000 R CNN
+F 2 "" H 25150 5550 29 0000 C CNN
+F 3 "" H 24950 5450 60 0000 C CNN
+ 1 24900 5450
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 25050 11500 25050 5650
+Wire Wire Line
+ 25050 5250 25050 2650
+Connection ~ 25050 2650
+Wire Wire Line
+ 25150 5300 25150 5100
+Wire Wire Line
+ 25150 5100 25050 5100
+Connection ~ 25050 5100
+Wire Wire Line
+ 5000 6700 24550 6700
+Wire Wire Line
+ 24550 6700 24550 5450
+Wire Wire Line
+ 24550 5450 24750 5450
+Connection ~ 5000 6700
+Wire Wire Line
+ 18350 4400 17350 4400
+Wire Wire Line
+ 17350 4400 17350 6700
+Connection ~ 17350 6700
+$Comp
+L eSim_MOS_P M17
+U 1 1 6859DCC7
+P 21950 4400
+F 0 "M17" H 21900 4450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 22000 4550 50 0000 R CNN
+F 2 "" H 22200 4500 29 0000 C CNN
+F 3 "" H 22000 4400 60 0000 C CNN
+ 1 21950 4400
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 22100 11500 22100 4600
+Wire Wire Line
+ 22100 4200 22100 2650
+Connection ~ 22100 2650
+Wire Wire Line
+ 22200 4250 22200 4000
+Wire Wire Line
+ 22200 4000 22100 4000
+Connection ~ 22100 4000
+Wire Wire Line
+ 19550 4400 21800 4400
+Wire Wire Line
+ 20600 4400 20600 5900
+Wire Wire Line
+ 20600 5900 18900 5900
+Connection ~ 18900 5900
+Connection ~ 20600 4400
+$Comp
+L capacitor C1
+U 1 1 6859EBA0
+P 23200 7550
+F 0 "C1" H 23225 7650 50 0000 L CNN
+F 1 "9p" H 23225 7450 50 0000 L CNN
+F 2 "" H 23238 7400 30 0000 C CNN
+F 3 "" H 23200 7550 60 0000 C CNN
+ 1 23200 7550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 23600 7550 23350 7550
+Wire Wire Line
+ 23600 4450 23600 7550
+Connection ~ 23600 6700
+Wire Wire Line
+ 23050 7550 22100 7550
+Connection ~ 22100 7550
+$Comp
+L eSim_Diode D7
+U 1 1 6859F3FA
+P 23600 4300
+F 0 "D7" H 23600 4400 50 0000 C CNN
+F 1 "eSim_Diode" H 23600 4200 50 0000 C CNN
+F 2 "" H 23600 4300 60 0000 C CNN
+F 3 "" H 23600 4300 60 0000 C CNN
+ 1 23600 4300
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 23600 4150 23600 2650
+Connection ~ 23600 2650
+Wire Wire Line
+ 20500 6700 20500 9050
+Wire Wire Line
+ 20500 9050 23100 9050
+Connection ~ 20500 6700
+$Comp
+L capacitor C2
+U 1 1 6859F985
+P 23250 9050
+F 0 "C2" H 23275 9150 50 0000 L CNN
+F 1 "33p" H 23275 8950 50 0000 L CNN
+F 2 "" H 23288 8900 30 0000 C CNN
+F 3 "" H 23250 9050 60 0000 C CNN
+ 1 23250 9050
+ 0 1 1 0
+$EndComp
+Connection ~ 25050 9050
+Wire Wire Line
+ 22100 10100 23550 10100
+Wire Wire Line
+ 23550 10100 23550 12800
+Connection ~ 23550 11700
+Connection ~ 22100 10100
+$Comp
+L eSim_Diode D6
+U 1 1 685A0135
+P 23550 12950
+F 0 "D6" H 23550 13050 50 0000 C CNN
+F 1 "eSim_Diode" H 23550 12850 50 0000 C CNN
+F 2 "" H 23550 12950 60 0000 C CNN
+F 3 "" H 23550 12950 60 0000 C CNN
+ 1 23550 12950
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 23550 13100 23550 14400
+Connection ~ 23550 14400
+Wire Wire Line
+ 6900 7000 6900 10000
+Wire Wire Line
+ 4700 7050 3600 7050
+Wire Wire Line
+ 6900 7000 6850 7000
+Wire Wire Line
+ 6450 7150 6450 7450
+Wire Wire Line
+ 6450 7450 6550 7450
+Connection ~ 6550 7450
+Wire Wire Line
+ 5100 7200 5100 7550
+Wire Wire Line
+ 5100 7550 5000 7550
+Connection ~ 5000 7550
+Wire Wire Line
+ 15450 15600 16800 15600
+Connection ~ 16150 15600
+$Comp
+L eSim_Diode D5
+U 1 1 685A1C84
+P 15300 15600
+F 0 "D5" H 15300 15700 50 0000 C CNN
+F 1 "eSim_Diode" H 15300 15500 50 0000 C CNN
+F 2 "" H 15300 15600 60 0000 C CNN
+F 3 "" H 15300 15600 60 0000 C CNN
+ 1 15300 15600
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 15150 15600 14550 15600
+$Comp
+L eSim_Diode D3
+U 1 1 685A2164
+P 3000 9450
+F 0 "D3" H 3000 9550 50 0000 C CNN
+F 1 "eSim_Diode" H 3000 9350 50 0000 C CNN
+F 2 "" H 3000 9450 60 0000 C CNN
+F 3 "" H 3000 9450 60 0000 C CNN
+ 1 3000 9450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_Diode D4
+U 1 1 685A221F
+P 3000 10650
+F 0 "D4" H 3000 10750 50 0000 C CNN
+F 1 "eSim_Diode" H 3000 10550 50 0000 C CNN
+F 2 "" H 3000 10650 60 0000 C CNN
+F 3 "" H 3000 10650 60 0000 C CNN
+ 1 3000 10650
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 3000 9600 3000 10500
+Connection ~ 3000 10000
+Wire Wire Line
+ 3000 9300 3000 9100
+Wire Wire Line
+ 3000 9100 2800 9100
+Wire Wire Line
+ 3000 10800 3000 11000
+Wire Wire Line
+ 3000 11000 2800 11000
+Wire Wire Line
+ 2800 11000 2800 14400
+Connection ~ 5700 14400
+$Comp
+L resistor R1
+U 1 1 685A2EB7
+P 3400 7100
+F 0 "R1" H 3450 7230 50 0000 C CNN
+F 1 "10k" H 3450 7050 50 0000 C CNN
+F 2 "" H 3450 7080 30 0000 C CNN
+F 3 "" V 3450 7150 30 0000 C CNN
+ 1 3400 7100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3300 7050 1400 7050
+Wire Wire Line
+ 1400 7050 1400 6950
+$Comp
+L eSim_Diode D1
+U 1 1 685A3192
+P 2500 6550
+F 0 "D1" H 2500 6650 50 0000 C CNN
+F 1 "eSim_Diode" H 2500 6450 50 0000 C CNN
+F 2 "" H 2500 6550 60 0000 C CNN
+F 3 "" H 2500 6550 60 0000 C CNN
+ 1 2500 6550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 685A329F
+P 2500 7450
+F 0 "D2" H 2500 7550 50 0000 C CNN
+F 1 "eSim_Diode" H 2500 7350 50 0000 C CNN
+F 2 "" H 2500 7450 60 0000 C CNN
+F 3 "" H 2500 7450 60 0000 C CNN
+ 1 2500 7450
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 2500 6700 2500 7300
+Connection ~ 2500 7050
+Wire Wire Line
+ 2500 7600 2500 8450
+Wire Wire Line
+ 2500 8450 4050 8450
+Wire Wire Line
+ 4050 8450 4050 14400
+Connection ~ 4050 14400
+Wire Wire Line
+ 2500 6400 2500 2650
+Connection ~ 5000 2650
+Wire Wire Line
+ 2800 9100 2800 2650
+Connection ~ 2800 2650
+Wire Wire Line
+ 14550 15600 14550 17000
+Wire Wire Line
+ 14550 17000 27000 17000
+Wire Wire Line
+ 27000 17000 27000 2650
+Connection ~ 27000 2650
+$Comp
+L resistor R2
+U 1 1 685A5751
+P 4900 10100
+F 0 "R2" H 4950 10230 50 0000 C CNN
+F 1 "10k" H 4950 10050 50 0000 C CNN
+F 2 "" H 4950 10080 30 0000 C CNN
+F 3 "" V 4950 10150 30 0000 C CNN
+ 1 4900 10100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6900 10000 5100 10000
+Wire Wire Line
+ 5100 10000 5100 10050
+Wire Wire Line
+ 3150 10050 4800 10050
+Wire Wire Line
+ 3150 10000 3150 10050
+Wire Wire Line
+ 1300 10000 3150 10000
+Wire Wire Line
+ 1300 10000 1300 9900
+$Comp
+L PORT U1
+U 3 1 685A6C2B
+P 1150 6950
+F 0 "U1" H 1200 7050 30 0000 C CNN
+F 1 "PORT" H 1150 6950 30 0000 C CNN
+F 2 "" H 1150 6950 60 0000 C CNN
+F 3 "" H 1150 6950 60 0000 C CNN
+ 3 1150 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685A6E1C
+P 1050 9900
+F 0 "U1" H 1100 10000 30 0000 C CNN
+F 1 "PORT" H 1050 9900 30 0000 C CNN
+F 2 "" H 1050 9900 60 0000 C CNN
+F 3 "" H 1050 9900 60 0000 C CNN
+ 2 1050 9900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A70A1
+P 3050 5150
+F 0 "U1" H 3100 5250 30 0000 C CNN
+F 1 "PORT" H 3050 5150 30 0000 C CNN
+F 2 "" H 3050 5150 60 0000 C CNN
+F 3 "" H 3050 5150 60 0000 C CNN
+ 1 3050 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685A7658
+P 17050 15600
+F 0 "U1" H 17100 15700 30 0000 C CNN
+F 1 "PORT" H 17050 15600 30 0000 C CNN
+F 2 "" H 17050 15600 60 0000 C CNN
+F 3 "" H 17050 15600 60 0000 C CNN
+ 8 17050 15600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685A7793
+P 29300 2650
+F 0 "U1" H 29350 2750 30 0000 C CNN
+F 1 "PORT" H 29300 2650 30 0000 C CNN
+F 2 "" H 29300 2650 60 0000 C CNN
+F 3 "" H 29300 2650 60 0000 C CNN
+ 7 29300 2650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A7DD7
+P 29150 14400
+F 0 "U1" H 29200 14500 30 0000 C CNN
+F 1 "PORT" H 29150 14400 30 0000 C CNN
+F 2 "" H 29150 14400 60 0000 C CNN
+F 3 "" H 29150 14400 60 0000 C CNN
+ 4 29150 14400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685A856C
+P 27800 9050
+F 0 "U1" H 27850 9150 30 0000 C CNN
+F 1 "PORT" H 27800 9050 30 0000 C CNN
+F 2 "" H 27800 9050 60 0000 C CNN
+F 3 "" H 27800 9050 60 0000 C CNN
+ 6 27800 9050
+ -1 0 0 1
+$EndComp
+Text Label 3600 5200 0 60 ~ 0
+Bal
+Text Label 1700 7050 0 60 ~ 0
+Input+
+Text Label 1550 10000 0 60 ~ 0
+Input-
+Wire Wire Line
+ 23400 9050 27550 9050
+Text Label 27150 9050 0 60 ~ 0
+Out
+Text Label 28600 2650 0 60 ~ 0
+V+
+Text Label 28750 14400 0 60 ~ 0
+V-
+Text Label 16600 15600 0 60 ~ 0
+Iqset
+Wire Wire Line
+ 6550 5150 7200 5150
+Connection ~ 6550 5150
+$Comp
+L PORT U?
+U 5 1 685ACDAE
+P 7450 5150
+F 0 "U?" H 7500 5250 30 0000 C CNN
+F 1 "PORT" H 7450 5150 30 0000 C CNN
+F 2 "" H 7450 5150 60 0000 C CNN
+F 3 "" H 7450 5150 60 0000 C CNN
+ 5 7450 5150
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.cir b/library/SubcircuitLibrary/ICL7611/ICL7611.cir
new file mode 100644
index 000000000..5b15871dd
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/ICL7611.cir
@@ -0,0 +1,47 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\ICL7611\ICL7611.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 08:09:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M2 Net-_C1-Pad1_ Net-_M2-Pad2_ /Bal /Bal eSim_MOS_P
+M4 Net-_M2-Pad2_ Net-_M2-Pad2_ Net-_M4-Pad3_ Net-_M4-Pad3_ eSim_MOS_P
+R3 /V+ /Bal 3k
+R4 /V+ Net-_M4-Pad3_ 3k
+M1 Net-_C1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M5 Net-_M2-Pad2_ Net-_M5-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M3 Net-_M1-Pad3_ Net-_M12-Pad2_ /V- /V- eSim_MOS_N
+M6 Net-_M12-Pad2_ Net-_M12-Pad2_ /V- /V- eSim_MOS_N
+M7 Net-_M12-Pad2_ Net-_M12-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_N
+M10 Net-_M10-Pad1_ Net-_M10-Pad2_ /V- /V- eSim_MOS_N
+M12 Net-_M11-Pad1_ Net-_M12-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ eSim_MOS_N
+M13 Net-_M11-Pad1_ Net-_M12-Pad2_ /V- /V- eSim_MOS_N
+M15 Net-_M14-Pad1_ Net-_M12-Pad2_ /V- /V- eSim_MOS_N
+M18 Net-_C1-Pad2_ Net-_C1-Pad2_ /V- /V- eSim_MOS_N
+M19 /Out Net-_C1-Pad2_ /V- /V- eSim_MOS_N
+R7 Net-_M10-Pad2_ /Iqset 470k
+R5 /V+ Net-_M9-Pad1_ 900k
+R6 Net-_M9-Pad1_ Net-_M8-Pad3_ 100k
+M8 Net-_M12-Pad2_ Net-_M11-Pad1_ Net-_M8-Pad3_ Net-_M8-Pad3_ eSim_MOS_P
+M11 Net-_M11-Pad1_ Net-_M11-Pad1_ /V+ /V+ eSim_MOS_P
+M9 Net-_M9-Pad1_ Net-_M10-Pad2_ /V+ /V+ eSim_MOS_P
+M14 Net-_M14-Pad1_ Net-_C1-Pad1_ /V+ /V+ eSim_MOS_P
+M16 Net-_M14-Pad1_ Net-_M14-Pad1_ /V+ /V+ eSim_MOS_P
+M20 /Out Net-_C1-Pad1_ /V+ /V+ eSim_MOS_P
+M17 Net-_C1-Pad2_ Net-_M14-Pad1_ /V+ /V+ eSim_MOS_P
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 9p
+D7 Net-_C1-Pad1_ /V+ eSim_Diode
+C2 /Out Net-_C1-Pad1_ 33p
+D6 /V- Net-_C1-Pad2_ eSim_Diode
+D5 /Iqset /V+ eSim_Diode
+D3 /Input- /V+ eSim_Diode
+D4 /V- /Input- eSim_Diode
+R1 /Input+ Net-_M1-Pad2_ 10k
+D1 /Input+ /V+ eSim_Diode
+D2 /V- /Input+ eSim_Diode
+R2 /Input- Net-_M5-Pad2_ 10k
+U1 /Bal /Input- /Input+ /V- Net-_M4-Pad3_ /Out /V+ /Iqset PORT
+
+.end
diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.cir.out b/library/SubcircuitLibrary/ICL7611/ICL7611.cir.out
new file mode 100644
index 000000000..ca28bd2fa
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/ICL7611.cir.out
@@ -0,0 +1,52 @@
+* c:\fossee\esim\library\subcircuitlibrary\icl7611\icl7611.cir
+
+.include NMOS-5um.lib
+.include ZenerD1N750.lib
+.include D.lib
+.include PMOS-5um.lib
+m2 net-_c1-pad1_ net-_m2-pad2_ /bal /bal mos_p W=100u L=100u M=1
+m4 net-_m2-pad2_ net-_m2-pad2_ net-_m4-pad3_ net-_m4-pad3_ mos_p W=100u L=100u M=1
+r3 /v+ /bal resistor
+r4 /v+ net-_m4-pad3_ resistor
+m1 net-_c1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m5 net-_m2-pad2_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m3 net-_m1-pad3_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m6 net-_m12-pad2_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m7 net-_m12-pad2_ net-_m12-pad2_ net-_m10-pad1_ net-_m10-pad1_ mos_n W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m12 net-_m11-pad1_ net-_m12-pad2_ net-_m10-pad1_ net-_m10-pad1_ mos_n W=100u L=100u M=1
+m13 net-_m11-pad1_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m15 net-_m14-pad1_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m18 net-_c1-pad2_ net-_c1-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m19 /out net-_c1-pad2_ /v- /v- mos_n W=100u L=100u M=1
+r7 net-_m10-pad2_ /iqset 470k
+r5 /v+ net-_m9-pad1_ 900k
+r6 net-_m9-pad1_ net-_m8-pad3_ 100k
+m8 net-_m12-pad2_ net-_m11-pad1_ net-_m8-pad3_ net-_m8-pad3_ mos_p W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m11-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+m9 net-_m9-pad1_ net-_m10-pad2_ /v+ /v+ mos_p W=100u L=100u M=1
+m14 net-_m14-pad1_ net-_c1-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+m16 net-_m14-pad1_ net-_m14-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+m20 /out net-_c1-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+m17 net-_c1-pad2_ net-_m14-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+c1 net-_c1-pad1_ net-_c1-pad2_ 9p
+d7 net-_c1-pad1_ /v+ D1N750
+c2 /out net-_c1-pad1_ 33p
+d6 /v- net-_c1-pad2_ D1N750
+d5 /iqset /v+ 1N4148
+d3 /input- /v+ 1N4148
+d4 /v- /input- 1N4148
+r1 /input+ net-_m1-pad2_ 10k
+d1 /input+ /v+ 1N4148
+d2 /v- /input+ 1N4148
+r2 /input- net-_m5-pad2_ 10k
+* u1 /bal /input- /input+ /v- net-_m4-pad3_ /out /v+ /iqset port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.pro b/library/SubcircuitLibrary/ICL7611/ICL7611.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/ICL7611.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.sch b/library/SubcircuitLibrary/ICL7611/ICL7611.sch
new file mode 100644
index 000000000..316eb0a19
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/ICL7611.sch
@@ -0,0 +1,926 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M2
+U 1 1 68596BF9
+P 5150 6000
+F 0 "M2" H 5100 6050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5200 6150 50 0000 R CNN
+F 2 "" H 5400 6100 29 0000 C CNN
+F 3 "" H 5200 6000 60 0000 C CNN
+ 1 5150 6000
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 68596C54
+P 6400 6000
+F 0 "M4" H 6350 6050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 6450 6150 50 0000 R CNN
+F 2 "" H 6650 6100 29 0000 C CNN
+F 3 "" H 6450 6000 60 0000 C CNN
+ 1 6400 6000
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 68596C8C
+P 4950 4800
+F 0 "R3" H 5000 4930 50 0000 C CNN
+F 1 "3k" H 5000 4750 50 0000 C CNN
+F 2 "" H 5000 4780 30 0000 C CNN
+F 3 "" V 5000 4850 30 0000 C CNN
+ 1 4950 4800
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 68596CD5
+P 6500 4800
+F 0 "R4" H 6550 4930 50 0000 C CNN
+F 1 "3k" H 6550 4750 50 0000 C CNN
+F 2 "" H 6550 4780 30 0000 C CNN
+F 3 "" V 6550 4850 30 0000 C CNN
+ 1 6500 4800
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_MOS_N M1
+U 1 1 68596DA8
+P 4800 6850
+F 0 "M1" H 4800 6700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 4900 6800 50 0000 R CNN
+F 2 "" H 5100 6550 29 0000 C CNN
+F 3 "" H 4900 6650 60 0000 C CNN
+ 1 4800 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 68596DF1
+P 6750 6800
+F 0 "M5" H 6750 6650 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6850 6750 50 0000 R CNN
+F 2 "" H 7050 6500 29 0000 C CNN
+F 3 "" H 6850 6600 60 0000 C CNN
+ 1 6750 6800
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M3
+U 1 1 68596FB8
+P 6000 12200
+F 0 "M3" H 6000 12050 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6100 12150 50 0000 R CNN
+F 2 "" H 6300 11900 29 0000 C CNN
+F 3 "" H 6100 12000 60 0000 C CNN
+ 1 6000 12200
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M6
+U 1 1 685976F9
+P 8650 11500
+F 0 "M6" H 8650 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 8750 11450 50 0000 R CNN
+F 2 "" H 8950 11200 29 0000 C CNN
+F 3 "" H 8750 11300 60 0000 C CNN
+ 1 8650 11500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M7
+U 1 1 68597A10
+P 10300 11500
+F 0 "M7" H 10300 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10400 11450 50 0000 R CNN
+F 2 "" H 10600 11200 29 0000 C CNN
+F 3 "" H 10400 11300 60 0000 C CNN
+ 1 10300 11500
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 68597AEE
+P 11650 12750
+F 0 "M10" H 11650 12600 50 0000 R CNN
+F 1 "eSim_MOS_N" H 11750 12700 50 0000 R CNN
+F 2 "" H 11950 12450 29 0000 C CNN
+F 3 "" H 11750 12550 60 0000 C CNN
+ 1 11650 12750
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M12
+U 1 1 68597B63
+P 12500 11500
+F 0 "M12" H 12500 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 12600 11450 50 0000 R CNN
+F 2 "" H 12800 11200 29 0000 C CNN
+F 3 "" H 12600 11300 60 0000 C CNN
+ 1 12500 11500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6550 5800 6550 5000
+Wire Wire Line
+ 6650 5850 6650 5600
+Wire Wire Line
+ 6650 5600 6550 5600
+Connection ~ 6550 5600
+Wire Wire Line
+ 5000 5800 5000 5000
+Wire Wire Line
+ 4900 5850 4900 5600
+Wire Wire Line
+ 4900 5600 5000 5600
+Connection ~ 5000 5600
+Wire Wire Line
+ 5300 6000 6250 6000
+Wire Wire Line
+ 5000 6850 5000 6200
+Wire Wire Line
+ 6550 6800 6550 6200
+Wire Wire Line
+ 6050 6000 6050 6500
+Wire Wire Line
+ 6050 6500 6550 6500
+Connection ~ 6550 6500
+Connection ~ 6050 6000
+Wire Wire Line
+ 5000 7250 5000 7800
+Wire Wire Line
+ 5000 7800 6550 7800
+Wire Wire Line
+ 6550 7800 6550 7200
+Wire Wire Line
+ 5800 12200 5800 7800
+Connection ~ 5800 7800
+Wire Wire Line
+ 5800 12600 5800 14400
+Wire Wire Line
+ 2800 14400 28900 14400
+Wire Wire Line
+ 5700 12550 5700 14400
+Connection ~ 5800 14400
+Wire Wire Line
+ 5000 4700 5000 2650
+Wire Wire Line
+ 2500 2650 29050 2650
+Wire Wire Line
+ 6550 4700 6550 2650
+Connection ~ 6550 2650
+Wire Wire Line
+ 5000 5200 3300 5200
+Wire Wire Line
+ 3300 5200 3300 5150
+Connection ~ 5000 5200
+Wire Wire Line
+ 7350 12400 6100 12400
+Wire Wire Line
+ 7350 11150 7350 12400
+Wire Wire Line
+ 7350 11700 8550 11700
+Wire Wire Line
+ 7350 11150 11450 11150
+Wire Wire Line
+ 8850 11150 8850 11500
+Connection ~ 7350 11700
+Wire Wire Line
+ 8850 11900 8850 14400
+Connection ~ 8850 14400
+Wire Wire Line
+ 8950 11850 8950 14400
+Connection ~ 8950 14400
+Wire Wire Line
+ 10400 11700 12400 11700
+Wire Wire Line
+ 10100 11900 10100 12400
+Wire Wire Line
+ 10000 12400 12800 12400
+Wire Wire Line
+ 12700 12400 12700 11900
+Wire Wire Line
+ 11450 12750 11450 12400
+Connection ~ 11450 12400
+Wire Wire Line
+ 10100 11150 10100 11500
+Connection ~ 8850 11150
+Wire Wire Line
+ 11450 11150 11450 12000
+Connection ~ 11450 11700
+Connection ~ 10100 11150
+Wire Wire Line
+ 11450 13150 11450 14400
+Connection ~ 11450 14400
+Wire Wire Line
+ 11350 13100 11350 14400
+Connection ~ 11350 14400
+Wire Wire Line
+ 10000 11850 10000 12400
+Connection ~ 10100 12400
+Wire Wire Line
+ 12800 12400 12800 11850
+Connection ~ 12700 12400
+$Comp
+L eSim_MOS_N M13
+U 1 1 68598199
+P 15050 11500
+F 0 "M13" H 15050 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 15150 11450 50 0000 R CNN
+F 2 "" H 15350 11200 29 0000 C CNN
+F 3 "" H 15150 11300 60 0000 C CNN
+ 1 15050 11500
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 12700 11500 12700 11250
+Wire Wire Line
+ 12400 11250 14850 11250
+Wire Wire Line
+ 14850 11250 14850 11500
+Wire Wire Line
+ 14850 11900 14850 14400
+Connection ~ 14850 14400
+Wire Wire Line
+ 14750 11850 14750 14400
+Connection ~ 14750 14400
+Wire Wire Line
+ 11450 12000 15650 12000
+Wire Wire Line
+ 15650 12000 15650 11700
+Wire Wire Line
+ 15150 11700 18600 11700
+$Comp
+L eSim_MOS_N M15
+U 1 1 68598842
+P 18700 11500
+F 0 "M15" H 18700 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 18800 11450 50 0000 R CNN
+F 2 "" H 19000 11200 29 0000 C CNN
+F 3 "" H 18800 11300 60 0000 C CNN
+ 1 18700 11500
+ 1 0 0 -1
+$EndComp
+Connection ~ 15650 11700
+Wire Wire Line
+ 18900 11900 18900 14400
+Connection ~ 18900 14400
+Wire Wire Line
+ 19000 11850 19000 14400
+Connection ~ 19000 14400
+$Comp
+L eSim_MOS_N M18
+U 1 1 68598CA3
+P 22300 11500
+F 0 "M18" H 22300 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 22400 11450 50 0000 R CNN
+F 2 "" H 22600 11200 29 0000 C CNN
+F 3 "" H 22400 11300 60 0000 C CNN
+ 1 22300 11500
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 22100 11900 22100 14400
+Connection ~ 22100 14400
+Wire Wire Line
+ 22000 11850 22000 14400
+Connection ~ 22000 14400
+$Comp
+L eSim_MOS_N M19
+U 1 1 68599072
+P 24850 11500
+F 0 "M19" H 24850 11350 50 0000 R CNN
+F 1 "eSim_MOS_N" H 24950 11450 50 0000 R CNN
+F 2 "" H 25150 11200 29 0000 C CNN
+F 3 "" H 24950 11300 60 0000 C CNN
+ 1 24850 11500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 25050 11900 25050 14400
+Connection ~ 25050 14400
+Wire Wire Line
+ 25150 11850 25150 14400
+Connection ~ 25150 14400
+Wire Wire Line
+ 22400 11700 24750 11700
+$Comp
+L resistor R7
+U 1 1 685995FF
+P 16100 14950
+F 0 "R7" H 16150 15080 50 0000 C CNN
+F 1 "470k" H 16150 14900 50 0000 C CNN
+F 2 "" H 16150 14930 30 0000 C CNN
+F 3 "" V 16150 15000 30 0000 C CNN
+ 1 16100 14950
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R5
+U 1 1 68599992
+P 10500 3200
+F 0 "R5" H 10550 3330 50 0000 C CNN
+F 1 "900k" H 10550 3150 50 0000 C CNN
+F 2 "" H 10550 3180 30 0000 C CNN
+F 3 "" V 10550 3250 30 0000 C CNN
+ 1 10500 3200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R6
+U 1 1 68599B69
+P 10500 4350
+F 0 "R6" H 10550 4480 50 0000 C CNN
+F 1 "100k" H 10550 4300 50 0000 C CNN
+F 2 "" H 10550 4330 30 0000 C CNN
+F 3 "" V 10550 4400 30 0000 C CNN
+ 1 10500 4350
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_MOS_P M8
+U 1 1 68599C9A
+P 10700 5450
+F 0 "M8" H 10650 5500 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10750 5600 50 0000 R CNN
+F 2 "" H 10950 5550 29 0000 C CNN
+F 3 "" H 10750 5450 60 0000 C CNN
+ 1 10700 5450
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 10550 5650 10550 11150
+Connection ~ 10550 11150
+Wire Wire Line
+ 10550 5250 10550 4550
+Wire Wire Line
+ 10550 4250 10550 3400
+Wire Wire Line
+ 10550 3100 10550 2650
+Connection ~ 10550 2650
+$Comp
+L eSim_MOS_P M11
+U 1 1 6859A1ED
+P 12250 5400
+F 0 "M11" H 12200 5450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 12300 5550 50 0000 R CNN
+F 2 "" H 12500 5500 29 0000 C CNN
+F 3 "" H 12300 5400 60 0000 C CNN
+ 1 12250 5400
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 10850 5450 12100 5450
+Wire Wire Line
+ 12100 5450 12100 5400
+Wire Wire Line
+ 12400 5600 12400 11250
+Connection ~ 12700 11250
+Wire Wire Line
+ 11450 5450 11450 6550
+Wire Wire Line
+ 11450 6550 12400 6550
+Connection ~ 12400 6550
+Connection ~ 11450 5450
+Wire Wire Line
+ 10450 5300 10450 5150
+Wire Wire Line
+ 10450 5150 10550 5150
+Connection ~ 10550 5150
+Wire Wire Line
+ 12400 5200 12400 2650
+Connection ~ 12400 2650
+Wire Wire Line
+ 12500 5250 12500 5050
+Wire Wire Line
+ 12500 5050 12400 5050
+Connection ~ 12400 5050
+$Comp
+L eSim_MOS_P M9
+U 1 1 6859AB95
+P 11600 3450
+F 0 "M9" H 11550 3500 50 0000 R CNN
+F 1 "eSim_MOS_P" H 11650 3600 50 0000 R CNN
+F 2 "" H 11850 3550 29 0000 C CNN
+F 3 "" H 11650 3450 60 0000 C CNN
+ 1 11600 3450
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 11450 3650 11450 3800
+Wire Wire Line
+ 11450 3800 10550 3800
+Connection ~ 10550 3800
+Wire Wire Line
+ 11450 3250 11450 2650
+Connection ~ 11450 2650
+Wire Wire Line
+ 11350 3300 11350 3050
+Wire Wire Line
+ 11350 3050 11450 3050
+Connection ~ 11450 3050
+Wire Wire Line
+ 16150 14850 16150 3450
+Wire Wire Line
+ 16150 3450 11750 3450
+Wire Wire Line
+ 16150 15150 16150 15600
+Wire Wire Line
+ 11750 12950 16150 12950
+Connection ~ 16150 12950
+$Comp
+L eSim_MOS_P M14
+U 1 1 6859B9E9
+P 18500 4400
+F 0 "M14" H 18450 4450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 18550 4550 50 0000 R CNN
+F 2 "" H 18750 4500 29 0000 C CNN
+F 3 "" H 18550 4400 60 0000 C CNN
+ 1 18500 4400
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 18900 11500 18900 5000
+Wire Wire Line
+ 18650 5000 19250 5000
+Wire Wire Line
+ 18650 5000 18650 4600
+$Comp
+L eSim_MOS_P M16
+U 1 1 6859C510
+P 19400 4400
+F 0 "M16" H 19350 4450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 19450 4550 50 0000 R CNN
+F 2 "" H 19650 4500 29 0000 C CNN
+F 3 "" H 19450 4400 60 0000 C CNN
+ 1 19400 4400
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 19250 5000 19250 4600
+Connection ~ 18900 5000
+Wire Wire Line
+ 19250 4200 19250 3750
+Wire Wire Line
+ 19250 3750 18650 3750
+Wire Wire Line
+ 18650 3750 18650 4200
+Wire Wire Line
+ 18750 4250 18750 3900
+Wire Wire Line
+ 18750 3900 18650 3900
+Connection ~ 18650 3900
+Wire Wire Line
+ 19150 4250 19150 3900
+Wire Wire Line
+ 19150 3900 19250 3900
+Connection ~ 19250 3900
+Wire Wire Line
+ 18950 3750 18950 2650
+Connection ~ 18950 2650
+Connection ~ 18950 3750
+$Comp
+L eSim_MOS_P M20
+U 1 1 6859CA78
+P 24900 5450
+F 0 "M20" H 24850 5500 50 0000 R CNN
+F 1 "eSim_MOS_P" H 24950 5600 50 0000 R CNN
+F 2 "" H 25150 5550 29 0000 C CNN
+F 3 "" H 24950 5450 60 0000 C CNN
+ 1 24900 5450
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 25050 11500 25050 5650
+Wire Wire Line
+ 25050 5250 25050 2650
+Connection ~ 25050 2650
+Wire Wire Line
+ 25150 5300 25150 5100
+Wire Wire Line
+ 25150 5100 25050 5100
+Connection ~ 25050 5100
+Wire Wire Line
+ 5000 6700 24550 6700
+Wire Wire Line
+ 24550 6700 24550 5450
+Wire Wire Line
+ 24550 5450 24750 5450
+Connection ~ 5000 6700
+Wire Wire Line
+ 18350 4400 17350 4400
+Wire Wire Line
+ 17350 4400 17350 6700
+Connection ~ 17350 6700
+$Comp
+L eSim_MOS_P M17
+U 1 1 6859DCC7
+P 21950 4400
+F 0 "M17" H 21900 4450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 22000 4550 50 0000 R CNN
+F 2 "" H 22200 4500 29 0000 C CNN
+F 3 "" H 22000 4400 60 0000 C CNN
+ 1 21950 4400
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 22100 11500 22100 4600
+Wire Wire Line
+ 22100 4200 22100 2650
+Connection ~ 22100 2650
+Wire Wire Line
+ 22200 4250 22200 4000
+Wire Wire Line
+ 22200 4000 22100 4000
+Connection ~ 22100 4000
+Wire Wire Line
+ 19550 4400 21800 4400
+Wire Wire Line
+ 20600 4400 20600 5900
+Wire Wire Line
+ 20600 5900 18900 5900
+Connection ~ 18900 5900
+Connection ~ 20600 4400
+$Comp
+L capacitor C1
+U 1 1 6859EBA0
+P 23200 7550
+F 0 "C1" H 23225 7650 50 0000 L CNN
+F 1 "9p" H 23225 7450 50 0000 L CNN
+F 2 "" H 23238 7400 30 0000 C CNN
+F 3 "" H 23200 7550 60 0000 C CNN
+ 1 23200 7550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 23600 7550 23350 7550
+Wire Wire Line
+ 23600 4450 23600 7550
+Connection ~ 23600 6700
+Wire Wire Line
+ 23050 7550 22100 7550
+Connection ~ 22100 7550
+$Comp
+L eSim_Diode D7
+U 1 1 6859F3FA
+P 23600 4300
+F 0 "D7" H 23600 4400 50 0000 C CNN
+F 1 "eSim_Diode" H 23600 4200 50 0000 C CNN
+F 2 "" H 23600 4300 60 0000 C CNN
+F 3 "" H 23600 4300 60 0000 C CNN
+ 1 23600 4300
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 23600 4150 23600 2650
+Connection ~ 23600 2650
+Wire Wire Line
+ 20500 6700 20500 9050
+Wire Wire Line
+ 20500 9050 23100 9050
+Connection ~ 20500 6700
+$Comp
+L capacitor C2
+U 1 1 6859F985
+P 23250 9050
+F 0 "C2" H 23275 9150 50 0000 L CNN
+F 1 "33p" H 23275 8950 50 0000 L CNN
+F 2 "" H 23288 8900 30 0000 C CNN
+F 3 "" H 23250 9050 60 0000 C CNN
+ 1 23250 9050
+ 0 1 1 0
+$EndComp
+Connection ~ 25050 9050
+Wire Wire Line
+ 22100 10100 23550 10100
+Wire Wire Line
+ 23550 10100 23550 12800
+Connection ~ 23550 11700
+Connection ~ 22100 10100
+$Comp
+L eSim_Diode D6
+U 1 1 685A0135
+P 23550 12950
+F 0 "D6" H 23550 13050 50 0000 C CNN
+F 1 "eSim_Diode" H 23550 12850 50 0000 C CNN
+F 2 "" H 23550 12950 60 0000 C CNN
+F 3 "" H 23550 12950 60 0000 C CNN
+ 1 23550 12950
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 23550 13100 23550 14400
+Connection ~ 23550 14400
+Wire Wire Line
+ 6900 7000 6900 10000
+Wire Wire Line
+ 4700 7050 3600 7050
+Wire Wire Line
+ 6900 7000 6850 7000
+Wire Wire Line
+ 6450 7150 6450 7450
+Wire Wire Line
+ 6450 7450 6550 7450
+Connection ~ 6550 7450
+Wire Wire Line
+ 5100 7200 5100 7550
+Wire Wire Line
+ 5100 7550 5000 7550
+Connection ~ 5000 7550
+Wire Wire Line
+ 15450 15600 16800 15600
+Connection ~ 16150 15600
+$Comp
+L eSim_Diode D5
+U 1 1 685A1C84
+P 15300 15600
+F 0 "D5" H 15300 15700 50 0000 C CNN
+F 1 "eSim_Diode" H 15300 15500 50 0000 C CNN
+F 2 "" H 15300 15600 60 0000 C CNN
+F 3 "" H 15300 15600 60 0000 C CNN
+ 1 15300 15600
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 15150 15600 14550 15600
+$Comp
+L eSim_Diode D3
+U 1 1 685A2164
+P 3000 9450
+F 0 "D3" H 3000 9550 50 0000 C CNN
+F 1 "eSim_Diode" H 3000 9350 50 0000 C CNN
+F 2 "" H 3000 9450 60 0000 C CNN
+F 3 "" H 3000 9450 60 0000 C CNN
+ 1 3000 9450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_Diode D4
+U 1 1 685A221F
+P 3000 10650
+F 0 "D4" H 3000 10750 50 0000 C CNN
+F 1 "eSim_Diode" H 3000 10550 50 0000 C CNN
+F 2 "" H 3000 10650 60 0000 C CNN
+F 3 "" H 3000 10650 60 0000 C CNN
+ 1 3000 10650
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 3000 9600 3000 10500
+Connection ~ 3000 10000
+Wire Wire Line
+ 3000 9300 3000 9100
+Wire Wire Line
+ 3000 9100 2800 9100
+Wire Wire Line
+ 3000 10800 3000 11000
+Wire Wire Line
+ 3000 11000 2800 11000
+Wire Wire Line
+ 2800 11000 2800 14400
+Connection ~ 5700 14400
+$Comp
+L resistor R1
+U 1 1 685A2EB7
+P 3400 7100
+F 0 "R1" H 3450 7230 50 0000 C CNN
+F 1 "10k" H 3450 7050 50 0000 C CNN
+F 2 "" H 3450 7080 30 0000 C CNN
+F 3 "" V 3450 7150 30 0000 C CNN
+ 1 3400 7100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3300 7050 1400 7050
+Wire Wire Line
+ 1400 7050 1400 6950
+$Comp
+L eSim_Diode D1
+U 1 1 685A3192
+P 2500 6550
+F 0 "D1" H 2500 6650 50 0000 C CNN
+F 1 "eSim_Diode" H 2500 6450 50 0000 C CNN
+F 2 "" H 2500 6550 60 0000 C CNN
+F 3 "" H 2500 6550 60 0000 C CNN
+ 1 2500 6550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 685A329F
+P 2500 7450
+F 0 "D2" H 2500 7550 50 0000 C CNN
+F 1 "eSim_Diode" H 2500 7350 50 0000 C CNN
+F 2 "" H 2500 7450 60 0000 C CNN
+F 3 "" H 2500 7450 60 0000 C CNN
+ 1 2500 7450
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 2500 6700 2500 7300
+Connection ~ 2500 7050
+Wire Wire Line
+ 2500 7600 2500 8450
+Wire Wire Line
+ 2500 8450 4050 8450
+Wire Wire Line
+ 4050 8450 4050 14400
+Connection ~ 4050 14400
+Wire Wire Line
+ 2500 6400 2500 2650
+Connection ~ 5000 2650
+Wire Wire Line
+ 2800 9100 2800 2650
+Connection ~ 2800 2650
+Wire Wire Line
+ 14550 15600 14550 17000
+Wire Wire Line
+ 14550 17000 27000 17000
+Wire Wire Line
+ 27000 17000 27000 2650
+Connection ~ 27000 2650
+$Comp
+L resistor R2
+U 1 1 685A5751
+P 4900 10100
+F 0 "R2" H 4950 10230 50 0000 C CNN
+F 1 "10k" H 4950 10050 50 0000 C CNN
+F 2 "" H 4950 10080 30 0000 C CNN
+F 3 "" V 4950 10150 30 0000 C CNN
+ 1 4900 10100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6900 10000 5100 10000
+Wire Wire Line
+ 5100 10000 5100 10050
+Wire Wire Line
+ 3150 10050 4800 10050
+Wire Wire Line
+ 3150 10000 3150 10050
+Wire Wire Line
+ 1300 10000 3150 10000
+Wire Wire Line
+ 1300 10000 1300 9900
+$Comp
+L PORT U1
+U 3 1 685A6C2B
+P 1150 6950
+F 0 "U1" H 1200 7050 30 0000 C CNN
+F 1 "PORT" H 1150 6950 30 0000 C CNN
+F 2 "" H 1150 6950 60 0000 C CNN
+F 3 "" H 1150 6950 60 0000 C CNN
+ 3 1150 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685A6E1C
+P 1050 9900
+F 0 "U1" H 1100 10000 30 0000 C CNN
+F 1 "PORT" H 1050 9900 30 0000 C CNN
+F 2 "" H 1050 9900 60 0000 C CNN
+F 3 "" H 1050 9900 60 0000 C CNN
+ 2 1050 9900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A70A1
+P 3050 5150
+F 0 "U1" H 3100 5250 30 0000 C CNN
+F 1 "PORT" H 3050 5150 30 0000 C CNN
+F 2 "" H 3050 5150 60 0000 C CNN
+F 3 "" H 3050 5150 60 0000 C CNN
+ 1 3050 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685A7658
+P 17050 15600
+F 0 "U1" H 17100 15700 30 0000 C CNN
+F 1 "PORT" H 17050 15600 30 0000 C CNN
+F 2 "" H 17050 15600 60 0000 C CNN
+F 3 "" H 17050 15600 60 0000 C CNN
+ 8 17050 15600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685A7793
+P 29300 2650
+F 0 "U1" H 29350 2750 30 0000 C CNN
+F 1 "PORT" H 29300 2650 30 0000 C CNN
+F 2 "" H 29300 2650 60 0000 C CNN
+F 3 "" H 29300 2650 60 0000 C CNN
+ 7 29300 2650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A7DD7
+P 29150 14400
+F 0 "U1" H 29200 14500 30 0000 C CNN
+F 1 "PORT" H 29150 14400 30 0000 C CNN
+F 2 "" H 29150 14400 60 0000 C CNN
+F 3 "" H 29150 14400 60 0000 C CNN
+ 4 29150 14400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685A856C
+P 27800 9050
+F 0 "U1" H 27850 9150 30 0000 C CNN
+F 1 "PORT" H 27800 9050 30 0000 C CNN
+F 2 "" H 27800 9050 60 0000 C CNN
+F 3 "" H 27800 9050 60 0000 C CNN
+ 6 27800 9050
+ -1 0 0 1
+$EndComp
+Text Label 3600 5200 0 60 ~ 0
+Bal
+Text Label 1700 7050 0 60 ~ 0
+Input+
+Text Label 1550 10000 0 60 ~ 0
+Input-
+Wire Wire Line
+ 23400 9050 27550 9050
+Text Label 27150 9050 0 60 ~ 0
+Out
+Text Label 28600 2650 0 60 ~ 0
+V+
+Text Label 28750 14400 0 60 ~ 0
+V-
+Text Label 16600 15600 0 60 ~ 0
+Iqset
+Wire Wire Line
+ 6550 5150 7200 5150
+Connection ~ 6550 5150
+$Comp
+L PORT U1
+U 5 1 685ACDAE
+P 7450 5150
+F 0 "U1" H 7500 5250 30 0000 C CNN
+F 1 "PORT" H 7450 5150 30 0000 C CNN
+F 2 "" H 7450 5150 60 0000 C CNN
+F 3 "" H 7450 5150 60 0000 C CNN
+ 5 7450 5150
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611.sub b/library/SubcircuitLibrary/ICL7611/ICL7611.sub
new file mode 100644
index 000000000..37d210aa0
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/ICL7611.sub
@@ -0,0 +1,46 @@
+* Subcircuit ICL7611
+.subckt ICL7611 /bal /input- /input+ /v- net-_m4-pad3_ /out /v+ /iqset
+* c:\fossee\esim\library\subcircuitlibrary\icl7611\icl7611.cir
+.include NMOS-5um.lib
+.include ZenerD1N750.lib
+.include D.lib
+.include PMOS-5um.lib
+m2 net-_c1-pad1_ net-_m2-pad2_ /bal /bal mos_p W=100u L=100u M=1
+m4 net-_m2-pad2_ net-_m2-pad2_ net-_m4-pad3_ net-_m4-pad3_ mos_p W=100u L=100u M=1
+r3 /v+ /bal 3k
+r4 /v+ net-_m4-pad3_ 3k
+m1 net-_c1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m5 net-_m2-pad2_ net-_m5-pad2_ net-_m1-pad3_ net-_m1-pad3_ mos_n W=100u L=100u M=1
+m3 net-_m1-pad3_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m6 net-_m12-pad2_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m7 net-_m12-pad2_ net-_m12-pad2_ net-_m10-pad1_ net-_m10-pad1_ mos_n W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m12 net-_m11-pad1_ net-_m12-pad2_ net-_m10-pad1_ net-_m10-pad1_ mos_n W=100u L=100u M=1
+m13 net-_m11-pad1_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m15 net-_m14-pad1_ net-_m12-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m18 net-_c1-pad2_ net-_c1-pad2_ /v- /v- mos_n W=100u L=100u M=1
+m19 /out net-_c1-pad2_ /v- /v- mos_n W=100u L=100u M=1
+r7 net-_m10-pad2_ /iqset 470k
+r5 /v+ net-_m9-pad1_ 900k
+r6 net-_m9-pad1_ net-_m8-pad3_ 100k
+m8 net-_m12-pad2_ net-_m11-pad1_ net-_m8-pad3_ net-_m8-pad3_ mos_p W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m11-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+m9 net-_m9-pad1_ net-_m10-pad2_ /v+ /v+ mos_p W=100u L=100u M=1
+m14 net-_m14-pad1_ net-_c1-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+m16 net-_m14-pad1_ net-_m14-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+m20 /out net-_c1-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+m17 net-_c1-pad2_ net-_m14-pad1_ /v+ /v+ mos_p W=100u L=100u M=1
+c1 net-_c1-pad1_ net-_c1-pad2_ 9p
+d7 net-_c1-pad1_ /v+ D1N750
+c2 /out net-_c1-pad1_ 33p
+d6 /v- net-_c1-pad2_ D1N750
+d5 /iqset /v+ 1N4148
+d3 /input- /v+ 1N4148
+d4 /v- /input- 1N4148
+r1 /input+ net-_m1-pad2_ 10k
+d1 /input+ /v+ 1N4148
+d2 /v- /input+ 1N4148
+r2 /input- net-_m5-pad2_ 10k
+* Control Statements
+
+.ends ICL7611
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICL7611/ICL7611_Previous_Values.xml b/library/SubcircuitLibrary/ICL7611/ICL7611_Previous_Values.xml
new file mode 100644
index 000000000..6023b1471
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/ICL7611_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ICL7611/NMOS-5um.lib b/library/SubcircuitLibrary/ICL7611/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/ICL7611/PMOS-5um.lib b/library/SubcircuitLibrary/ICL7611/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/ICL7611/ZenerD1N750.lib b/library/SubcircuitLibrary/ICL7611/ZenerD1N750.lib
new file mode 100644
index 000000000..890c37fe2
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/ZenerD1N750.lib
@@ -0,0 +1,3 @@
+.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516
++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m
++ Nbvl=14.976 Tbv1=-21.277u)
diff --git a/library/SubcircuitLibrary/ICL7611/analysis b/library/SubcircuitLibrary/ICL7611/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/ICL7611/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/L702/L702-cache.lib b/library/SubcircuitLibrary/L702/L702-cache.lib
new file mode 100644
index 000000000..1568691ef
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/L702-cache.lib
@@ -0,0 +1,83 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/L702/L702.bak b/library/SubcircuitLibrary/L702/L702.bak
new file mode 100644
index 000000000..9325922b3
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/L702.bak
@@ -0,0 +1,624 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R2
+U 1 1 685BADF2
+P 1800 1650
+F 0 "R2" H 1850 1780 50 0000 C CNN
+F 1 "340" H 1850 1600 50 0000 C CNN
+F 2 "" H 1850 1630 30 0000 C CNN
+F 3 "" V 1850 1700 30 0000 C CNN
+ 1 1800 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R4
+U 1 1 685BAE4F
+P 2700 2150
+F 0 "R4" H 2750 2280 50 0000 C CNN
+F 1 "7k" H 2750 2100 50 0000 C CNN
+F 2 "" H 2750 2130 30 0000 C CNN
+F 3 "" V 2750 2200 30 0000 C CNN
+ 1 2700 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R6
+U 1 1 685BAE96
+P 3250 2800
+F 0 "R6" H 3300 2930 50 0000 C CNN
+F 1 "500" H 3300 2750 50 0000 C CNN
+F 2 "" H 3300 2780 30 0000 C CNN
+F 3 "" V 3300 2850 30 0000 C CNN
+ 1 3250 2800
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 685BAEF9
+P 3250 1600
+F 0 "Q2" H 3150 1650 50 0000 R CNN
+F 1 "eSim_NPN" H 3200 1750 50 0000 R CNN
+F 2 "" H 3450 1700 29 0000 C CNN
+F 3 "" H 3250 1600 60 0000 C CNN
+ 1 3250 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 685BAF52
+P 3950 2100
+F 0 "Q4" H 3850 2150 50 0000 R CNN
+F 1 "eSim_NPN" H 3900 2250 50 0000 R CNN
+F 2 "" H 4150 2200 29 0000 C CNN
+F 3 "" H 3950 2100 60 0000 C CNN
+ 1 3950 2100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2000 1600 3050 1600
+Wire Wire Line
+ 2600 2100 2350 2100
+Wire Wire Line
+ 2350 2100 2350 1600
+Connection ~ 2350 1600
+Wire Wire Line
+ 2900 2100 3750 2100
+Wire Wire Line
+ 3350 1800 3350 2150
+Wire Wire Line
+ 3300 2700 3300 2150
+Wire Wire Line
+ 3300 2150 3350 2150
+Connection ~ 3350 2100
+Wire Wire Line
+ 3300 3000 3300 3500
+Wire Wire Line
+ 4050 3500 4050 2300
+Wire Wire Line
+ 1700 1600 1350 1600
+Wire Wire Line
+ 4050 800 4050 1900
+Wire Wire Line
+ 4050 1250 3350 1250
+Wire Wire Line
+ 3350 1250 3350 1400
+Connection ~ 4050 1250
+$Comp
+L resistor R8
+U 1 1 685BEA05
+P 5400 1600
+F 0 "R8" H 5450 1730 50 0000 C CNN
+F 1 "340" H 5450 1550 50 0000 C CNN
+F 2 "" H 5450 1580 30 0000 C CNN
+F 3 "" V 5450 1650 30 0000 C CNN
+ 1 5400 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R10
+U 1 1 685BEA0B
+P 6300 2100
+F 0 "R10" H 6350 2230 50 0000 C CNN
+F 1 "7k" H 6350 2050 50 0000 C CNN
+F 2 "" H 6350 2080 30 0000 C CNN
+F 3 "" V 6350 2150 30 0000 C CNN
+ 1 6300 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R12
+U 1 1 685BEA11
+P 6850 2750
+F 0 "R12" H 6900 2880 50 0000 C CNN
+F 1 "500" H 6900 2700 50 0000 C CNN
+F 2 "" H 6900 2730 30 0000 C CNN
+F 3 "" V 6900 2800 30 0000 C CNN
+ 1 6850 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 685BEA17
+P 6850 1550
+F 0 "Q6" H 6750 1600 50 0000 R CNN
+F 1 "eSim_NPN" H 6800 1700 50 0000 R CNN
+F 2 "" H 7050 1650 29 0000 C CNN
+F 3 "" H 6850 1550 60 0000 C CNN
+ 1 6850 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 685BEA1D
+P 7550 2050
+F 0 "Q8" H 7450 2100 50 0000 R CNN
+F 1 "eSim_NPN" H 7500 2200 50 0000 R CNN
+F 2 "" H 7750 2150 29 0000 C CNN
+F 3 "" H 7550 2050 60 0000 C CNN
+ 1 7550 2050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5600 1550 6650 1550
+Wire Wire Line
+ 6200 2050 5950 2050
+Wire Wire Line
+ 5950 2050 5950 1550
+Connection ~ 5950 1550
+Wire Wire Line
+ 6500 2050 7350 2050
+Wire Wire Line
+ 6950 1750 6950 2100
+Wire Wire Line
+ 6900 2650 6900 2100
+Wire Wire Line
+ 6900 2100 6950 2100
+Connection ~ 6950 2050
+Wire Wire Line
+ 6900 2950 6900 3450
+Wire Wire Line
+ 7650 3450 7650 2250
+Wire Wire Line
+ 5300 1550 4950 1550
+Wire Wire Line
+ 7650 750 7650 1850
+Wire Wire Line
+ 7650 1200 6950 1200
+Wire Wire Line
+ 6950 1200 6950 1350
+Connection ~ 7650 1200
+$Comp
+L resistor R1
+U 1 1 685BEBBB
+P 1750 5400
+F 0 "R1" H 1800 5530 50 0000 C CNN
+F 1 "340" H 1800 5350 50 0000 C CNN
+F 2 "" H 1800 5380 30 0000 C CNN
+F 3 "" V 1800 5450 30 0000 C CNN
+ 1 1750 5400
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 685BEBC1
+P 2650 5900
+F 0 "R3" H 2700 6030 50 0000 C CNN
+F 1 "7k" H 2700 5850 50 0000 C CNN
+F 2 "" H 2700 5880 30 0000 C CNN
+F 3 "" V 2700 5950 30 0000 C CNN
+ 1 2650 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R5
+U 1 1 685BEBC7
+P 3200 6550
+F 0 "R5" H 3250 6680 50 0000 C CNN
+F 1 "500" H 3250 6500 50 0000 C CNN
+F 2 "" H 3250 6530 30 0000 C CNN
+F 3 "" V 3250 6600 30 0000 C CNN
+ 1 3200 6550
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 685BEBCD
+P 3200 5350
+F 0 "Q1" H 3100 5400 50 0000 R CNN
+F 1 "eSim_NPN" H 3150 5500 50 0000 R CNN
+F 2 "" H 3400 5450 29 0000 C CNN
+F 3 "" H 3200 5350 60 0000 C CNN
+ 1 3200 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 685BEBD3
+P 3900 5850
+F 0 "Q3" H 3800 5900 50 0000 R CNN
+F 1 "eSim_NPN" H 3850 6000 50 0000 R CNN
+F 2 "" H 4100 5950 29 0000 C CNN
+F 3 "" H 3900 5850 60 0000 C CNN
+ 1 3900 5850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1950 5350 3000 5350
+Wire Wire Line
+ 2550 5850 2300 5850
+Wire Wire Line
+ 2300 5850 2300 5350
+Connection ~ 2300 5350
+Wire Wire Line
+ 2850 5850 3700 5850
+Wire Wire Line
+ 3300 5550 3300 5900
+Wire Wire Line
+ 3250 6450 3250 5900
+Wire Wire Line
+ 3250 5900 3300 5900
+Connection ~ 3300 5850
+Wire Wire Line
+ 3250 6750 3250 7250
+Wire Wire Line
+ 4000 7250 4000 6050
+Wire Wire Line
+ 1650 5350 1300 5350
+Wire Wire Line
+ 4000 4550 4000 5650
+Wire Wire Line
+ 4000 5000 3300 5000
+Wire Wire Line
+ 3300 5000 3300 5150
+Connection ~ 4000 5000
+$Comp
+L resistor R7
+U 1 1 685BEBEB
+P 5350 5350
+F 0 "R7" H 5400 5480 50 0000 C CNN
+F 1 "340" H 5400 5300 50 0000 C CNN
+F 2 "" H 5400 5330 30 0000 C CNN
+F 3 "" V 5400 5400 30 0000 C CNN
+ 1 5350 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R9
+U 1 1 685BEBF1
+P 6250 5850
+F 0 "R9" H 6300 5980 50 0000 C CNN
+F 1 "7k" H 6300 5800 50 0000 C CNN
+F 2 "" H 6300 5830 30 0000 C CNN
+F 3 "" V 6300 5900 30 0000 C CNN
+ 1 6250 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R11
+U 1 1 685BEBF7
+P 6800 6500
+F 0 "R11" H 6850 6630 50 0000 C CNN
+F 1 "500" H 6850 6450 50 0000 C CNN
+F 2 "" H 6850 6480 30 0000 C CNN
+F 3 "" V 6850 6550 30 0000 C CNN
+ 1 6800 6500
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 685BEBFD
+P 6800 5300
+F 0 "Q5" H 6700 5350 50 0000 R CNN
+F 1 "eSim_NPN" H 6750 5450 50 0000 R CNN
+F 2 "" H 7000 5400 29 0000 C CNN
+F 3 "" H 6800 5300 60 0000 C CNN
+ 1 6800 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 685BEC03
+P 7500 5800
+F 0 "Q7" H 7400 5850 50 0000 R CNN
+F 1 "eSim_NPN" H 7450 5950 50 0000 R CNN
+F 2 "" H 7700 5900 29 0000 C CNN
+F 3 "" H 7500 5800 60 0000 C CNN
+ 1 7500 5800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 5300 6600 5300
+Wire Wire Line
+ 6150 5800 5900 5800
+Wire Wire Line
+ 5900 5800 5900 5300
+Connection ~ 5900 5300
+Wire Wire Line
+ 6450 5800 7300 5800
+Wire Wire Line
+ 6900 5500 6900 5850
+Wire Wire Line
+ 6850 6400 6850 5850
+Wire Wire Line
+ 6850 5850 6900 5850
+Connection ~ 6900 5800
+Wire Wire Line
+ 6850 7250 6850 6700
+Wire Wire Line
+ 7600 7250 7600 6000
+Wire Wire Line
+ 5250 5300 4900 5300
+Wire Wire Line
+ 7600 4500 7600 5600
+Wire Wire Line
+ 7600 4950 6900 4950
+Wire Wire Line
+ 6900 4950 6900 5100
+Connection ~ 7600 4950
+Wire Wire Line
+ 3250 7250 9400 7250
+Connection ~ 4000 7250
+Connection ~ 6850 7250
+Wire Wire Line
+ 9400 7250 9400 3450
+Wire Wire Line
+ 4200 3450 9650 3450
+Connection ~ 7600 7250
+Connection ~ 7650 3450
+Wire Wire Line
+ 4200 3450 4200 3500
+Wire Wire Line
+ 4200 3500 3300 3500
+Connection ~ 6900 3450
+Connection ~ 4050 3500
+Connection ~ 9400 3450
+Wire Wire Line
+ 9400 3650 9650 3650
+Connection ~ 9400 3650
+Wire Wire Line
+ 9400 3850 9650 3850
+Connection ~ 9400 3850
+Wire Wire Line
+ 9400 4050 9650 4050
+Connection ~ 9400 4050
+Wire Wire Line
+ 9400 4300 9650 4300
+Connection ~ 9400 4300
+Wire Wire Line
+ 9400 4550 9650 4550
+Connection ~ 9400 4550
+Text Label 1500 1600 0 60 ~ 0
+B1
+Text Label 1450 5350 0 60 ~ 0
+B2
+Text Label 5100 5300 0 60 ~ 0
+B3
+Text Label 5200 1550 0 60 ~ 0
+B4
+Text Label 4050 1050 0 60 ~ 0
+C1
+Text Label 4000 4800 0 60 ~ 0
+C2
+Text Label 7600 4750 0 60 ~ 0
+C3
+Text Label 7650 950 0 60 ~ 0
+C4
+$Comp
+L PORT U1
+U 1 1 685C0791
+P 1100 1600
+F 0 "U1" H 1150 1700 30 0000 C CNN
+F 1 "PORT" H 1100 1600 30 0000 C CNN
+F 2 "" H 1100 1600 60 0000 C CNN
+F 3 "" H 1100 1600 60 0000 C CNN
+ 1 1100 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685C092E
+P 1050 5350
+F 0 "U1" H 1100 5450 30 0000 C CNN
+F 1 "PORT" H 1050 5350 30 0000 C CNN
+F 2 "" H 1050 5350 60 0000 C CNN
+F 3 "" H 1050 5350 60 0000 C CNN
+ 2 1050 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685C0ADD
+P 3800 800
+F 0 "U1" H 3850 900 30 0000 C CNN
+F 1 "PORT" H 3800 800 30 0000 C CNN
+F 2 "" H 3800 800 60 0000 C CNN
+F 3 "" H 3800 800 60 0000 C CNN
+ 3 3800 800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685C0D14
+P 3750 4550
+F 0 "U1" H 3800 4650 30 0000 C CNN
+F 1 "PORT" H 3750 4550 30 0000 C CNN
+F 2 "" H 3750 4550 60 0000 C CNN
+F 3 "" H 3750 4550 60 0000 C CNN
+ 4 3750 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685C101B
+P 4700 1550
+F 0 "U1" H 4750 1650 30 0000 C CNN
+F 1 "PORT" H 4700 1550 30 0000 C CNN
+F 2 "" H 4700 1550 60 0000 C CNN
+F 3 "" H 4700 1550 60 0000 C CNN
+ 8 4700 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685C10B9
+P 7400 750
+F 0 "U1" H 7450 850 30 0000 C CNN
+F 1 "PORT" H 7400 750 30 0000 C CNN
+F 2 "" H 7400 750 60 0000 C CNN
+F 3 "" H 7400 750 60 0000 C CNN
+ 6 7400 750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685C12C6
+P 4650 5300
+F 0 "U1" H 4700 5400 30 0000 C CNN
+F 1 "PORT" H 4650 5300 30 0000 C CNN
+F 2 "" H 4650 5300 60 0000 C CNN
+F 3 "" H 4650 5300 60 0000 C CNN
+ 7 4650 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685C1552
+P 7350 4500
+F 0 "U1" H 7400 4600 30 0000 C CNN
+F 1 "PORT" H 7350 4500 30 0000 C CNN
+F 2 "" H 7350 4500 60 0000 C CNN
+F 3 "" H 7350 4500 60 0000 C CNN
+ 5 7350 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685C1705
+P 9900 3450
+F 0 "U1" H 9950 3550 30 0000 C CNN
+F 1 "PORT" H 9900 3450 30 0000 C CNN
+F 2 "" H 9900 3450 60 0000 C CNN
+F 3 "" H 9900 3450 60 0000 C CNN
+ 9 9900 3450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685C1962
+P 9900 3650
+F 0 "U1" H 9950 3750 30 0000 C CNN
+F 1 "PORT" H 9900 3650 30 0000 C CNN
+F 2 "" H 9900 3650 60 0000 C CNN
+F 3 "" H 9900 3650 60 0000 C CNN
+ 10 9900 3650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685C19D3
+P 9900 3850
+F 0 "U1" H 9950 3950 30 0000 C CNN
+F 1 "PORT" H 9900 3850 30 0000 C CNN
+F 2 "" H 9900 3850 60 0000 C CNN
+F 3 "" H 9900 3850 60 0000 C CNN
+ 11 9900 3850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685C1A5C
+P 9900 4050
+F 0 "U1" H 9950 4150 30 0000 C CNN
+F 1 "PORT" H 9900 4050 30 0000 C CNN
+F 2 "" H 9900 4050 60 0000 C CNN
+F 3 "" H 9900 4050 60 0000 C CNN
+ 12 9900 4050
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685C1AC1
+P 9900 4300
+F 0 "U1" H 9950 4400 30 0000 C CNN
+F 1 "PORT" H 9900 4300 30 0000 C CNN
+F 2 "" H 9900 4300 60 0000 C CNN
+F 3 "" H 9900 4300 60 0000 C CNN
+ 13 9900 4300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685C1B2C
+P 9900 4550
+F 0 "U1" H 9950 4650 30 0000 C CNN
+F 1 "PORT" H 9900 4550 30 0000 C CNN
+F 2 "" H 9900 4550 60 0000 C CNN
+F 3 "" H 9900 4550 60 0000 C CNN
+ 14 9900 4550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 685C2250
+P 9900 4850
+F 0 "U1" H 9950 4950 30 0000 C CNN
+F 1 "PORT" H 9900 4850 30 0000 C CNN
+F 2 "" H 9900 4850 60 0000 C CNN
+F 3 "" H 9900 4850 60 0000 C CNN
+ 15 9900 4850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 685C22BD
+P 9900 5150
+F 0 "U1" H 9950 5250 30 0000 C CNN
+F 1 "PORT" H 9900 5150 30 0000 C CNN
+F 2 "" H 9900 5150 60 0000 C CNN
+F 3 "" H 9900 5150 60 0000 C CNN
+ 16 9900 5150
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9650 4850 9400 4850
+Connection ~ 9400 4850
+Wire Wire Line
+ 9650 5150 9400 5150
+Connection ~ 9400 5150
+Text Label 8800 3450 0 60 ~ 0
+GND
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/L702/L702.cir b/library/SubcircuitLibrary/L702/L702.cir
new file mode 100644
index 000000000..051251d86
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/L702.cir
@@ -0,0 +1,31 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\L702\L702.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/03/25 23:21:56
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R2 /B1 Net-_Q2-Pad2_ 340
+R4 Net-_Q2-Pad2_ Net-_Q2-Pad3_ 7k
+R6 Net-_Q2-Pad3_ /GND 500
+Q2 /C1 Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+Q4 /C1 Net-_Q2-Pad3_ /GND eSim_NPN
+R8 /B4 Net-_Q6-Pad2_ 340
+R10 Net-_Q6-Pad2_ Net-_Q6-Pad3_ 7k
+R12 Net-_Q6-Pad3_ /GND 500
+Q6 /C4 Net-_Q6-Pad2_ Net-_Q6-Pad3_ eSim_NPN
+Q8 /C4 Net-_Q6-Pad3_ /GND eSim_NPN
+R1 /B2 Net-_Q1-Pad2_ 340
+R3 Net-_Q1-Pad2_ Net-_Q1-Pad3_ 7k
+R5 Net-_Q1-Pad3_ /GND 500
+Q1 /C2 Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+Q3 /C2 Net-_Q1-Pad3_ /GND eSim_NPN
+R7 /B3 Net-_Q5-Pad2_ 340
+R9 Net-_Q5-Pad2_ Net-_Q5-Pad3_ 7k
+R11 Net-_Q5-Pad3_ /GND 500
+Q5 /C3 Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN
+Q7 /C3 Net-_Q5-Pad3_ /GND eSim_NPN
+U1 /B4 /B3 ? /C4 /C3 /GND /C2 /C1 ? /B2 /B1 PORT
+
+.end
diff --git a/library/SubcircuitLibrary/L702/L702.cir.out b/library/SubcircuitLibrary/L702/L702.cir.out
new file mode 100644
index 000000000..ddb606c64
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/L702.cir.out
@@ -0,0 +1,33 @@
+* c:\fossee\esim\library\subcircuitlibrary\l702\l702.cir
+
+.include NPN.lib
+r2 /b1 net-_q2-pad2_ 340
+r4 net-_q2-pad2_ net-_q2-pad3_ 7k
+r6 net-_q2-pad3_ /gnd 500
+q2 /c1 net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q4 /c1 net-_q2-pad3_ /gnd Q2N2222
+r8 /b4 net-_q6-pad2_ 340
+r10 net-_q6-pad2_ net-_q6-pad3_ 7k
+r12 net-_q6-pad3_ /gnd 500
+q6 /c4 net-_q6-pad2_ net-_q6-pad3_ Q2N2222
+q8 /c4 net-_q6-pad3_ /gnd Q2N2222
+r1 /b2 net-_q1-pad2_ 340
+r3 net-_q1-pad2_ net-_q1-pad3_ 7k
+r5 net-_q1-pad3_ /gnd 500
+q1 /c2 net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+q3 /c2 net-_q1-pad3_ /gnd Q2N2222
+r7 /b3 net-_q5-pad2_ 340
+r9 net-_q5-pad2_ net-_q5-pad3_ 7k
+r11 net-_q5-pad3_ /gnd 500
+q5 /c3 net-_q5-pad2_ net-_q5-pad3_ Q2N2222
+q7 /c3 net-_q5-pad3_ /gnd Q2N2222
+* u1 /b4 /b3 ? /c4 /c3 /gnd /c2 /c1 ? /b2 /b1 port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/L702/L702.pro b/library/SubcircuitLibrary/L702/L702.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/L702.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/L702/L702.sch b/library/SubcircuitLibrary/L702/L702.sch
new file mode 100644
index 000000000..10d2c0710
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/L702.sch
@@ -0,0 +1,555 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:L702-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R2
+U 1 1 685BADF2
+P 1800 1650
+F 0 "R2" H 1850 1780 50 0000 C CNN
+F 1 "340" H 1850 1600 50 0000 C CNN
+F 2 "" H 1850 1630 30 0000 C CNN
+F 3 "" V 1850 1700 30 0000 C CNN
+ 1 1800 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R4
+U 1 1 685BAE4F
+P 2700 2150
+F 0 "R4" H 2750 2280 50 0000 C CNN
+F 1 "7k" H 2750 2100 50 0000 C CNN
+F 2 "" H 2750 2130 30 0000 C CNN
+F 3 "" V 2750 2200 30 0000 C CNN
+ 1 2700 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R6
+U 1 1 685BAE96
+P 3250 2800
+F 0 "R6" H 3300 2930 50 0000 C CNN
+F 1 "500" H 3300 2750 50 0000 C CNN
+F 2 "" H 3300 2780 30 0000 C CNN
+F 3 "" V 3300 2850 30 0000 C CNN
+ 1 3250 2800
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 685BAEF9
+P 3250 1600
+F 0 "Q2" H 3150 1650 50 0000 R CNN
+F 1 "eSim_NPN" H 3200 1750 50 0000 R CNN
+F 2 "" H 3450 1700 29 0000 C CNN
+F 3 "" H 3250 1600 60 0000 C CNN
+ 1 3250 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 685BAF52
+P 3950 2100
+F 0 "Q4" H 3850 2150 50 0000 R CNN
+F 1 "eSim_NPN" H 3900 2250 50 0000 R CNN
+F 2 "" H 4150 2200 29 0000 C CNN
+F 3 "" H 3950 2100 60 0000 C CNN
+ 1 3950 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R8
+U 1 1 685BEA05
+P 5400 1600
+F 0 "R8" H 5450 1730 50 0000 C CNN
+F 1 "340" H 5450 1550 50 0000 C CNN
+F 2 "" H 5450 1580 30 0000 C CNN
+F 3 "" V 5450 1650 30 0000 C CNN
+ 1 5400 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R10
+U 1 1 685BEA0B
+P 6300 2100
+F 0 "R10" H 6350 2230 50 0000 C CNN
+F 1 "7k" H 6350 2050 50 0000 C CNN
+F 2 "" H 6350 2080 30 0000 C CNN
+F 3 "" V 6350 2150 30 0000 C CNN
+ 1 6300 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R12
+U 1 1 685BEA11
+P 6850 2750
+F 0 "R12" H 6900 2880 50 0000 C CNN
+F 1 "500" H 6900 2700 50 0000 C CNN
+F 2 "" H 6900 2730 30 0000 C CNN
+F 3 "" V 6900 2800 30 0000 C CNN
+ 1 6850 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 685BEA17
+P 6850 1550
+F 0 "Q6" H 6750 1600 50 0000 R CNN
+F 1 "eSim_NPN" H 6800 1700 50 0000 R CNN
+F 2 "" H 7050 1650 29 0000 C CNN
+F 3 "" H 6850 1550 60 0000 C CNN
+ 1 6850 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 685BEA1D
+P 7550 2050
+F 0 "Q8" H 7450 2100 50 0000 R CNN
+F 1 "eSim_NPN" H 7500 2200 50 0000 R CNN
+F 2 "" H 7750 2150 29 0000 C CNN
+F 3 "" H 7550 2050 60 0000 C CNN
+ 1 7550 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R1
+U 1 1 685BEBBB
+P 1750 5400
+F 0 "R1" H 1800 5530 50 0000 C CNN
+F 1 "340" H 1800 5350 50 0000 C CNN
+F 2 "" H 1800 5380 30 0000 C CNN
+F 3 "" V 1800 5450 30 0000 C CNN
+ 1 1750 5400
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 685BEBC1
+P 2650 5900
+F 0 "R3" H 2700 6030 50 0000 C CNN
+F 1 "7k" H 2700 5850 50 0000 C CNN
+F 2 "" H 2700 5880 30 0000 C CNN
+F 3 "" V 2700 5950 30 0000 C CNN
+ 1 2650 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R5
+U 1 1 685BEBC7
+P 3200 6550
+F 0 "R5" H 3250 6680 50 0000 C CNN
+F 1 "500" H 3250 6500 50 0000 C CNN
+F 2 "" H 3250 6530 30 0000 C CNN
+F 3 "" V 3250 6600 30 0000 C CNN
+ 1 3200 6550
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 685BEBCD
+P 3200 5350
+F 0 "Q1" H 3100 5400 50 0000 R CNN
+F 1 "eSim_NPN" H 3150 5500 50 0000 R CNN
+F 2 "" H 3400 5450 29 0000 C CNN
+F 3 "" H 3200 5350 60 0000 C CNN
+ 1 3200 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 685BEBD3
+P 3900 5850
+F 0 "Q3" H 3800 5900 50 0000 R CNN
+F 1 "eSim_NPN" H 3850 6000 50 0000 R CNN
+F 2 "" H 4100 5950 29 0000 C CNN
+F 3 "" H 3900 5850 60 0000 C CNN
+ 1 3900 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R7
+U 1 1 685BEBEB
+P 5350 5350
+F 0 "R7" H 5400 5480 50 0000 C CNN
+F 1 "340" H 5400 5300 50 0000 C CNN
+F 2 "" H 5400 5330 30 0000 C CNN
+F 3 "" V 5400 5400 30 0000 C CNN
+ 1 5350 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R9
+U 1 1 685BEBF1
+P 6250 5850
+F 0 "R9" H 6300 5980 50 0000 C CNN
+F 1 "7k" H 6300 5800 50 0000 C CNN
+F 2 "" H 6300 5830 30 0000 C CNN
+F 3 "" V 6300 5900 30 0000 C CNN
+ 1 6250 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R11
+U 1 1 685BEBF7
+P 6800 6500
+F 0 "R11" H 6850 6630 50 0000 C CNN
+F 1 "500" H 6850 6450 50 0000 C CNN
+F 2 "" H 6850 6480 30 0000 C CNN
+F 3 "" V 6850 6550 30 0000 C CNN
+ 1 6800 6500
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 685BEBFD
+P 6800 5300
+F 0 "Q5" H 6700 5350 50 0000 R CNN
+F 1 "eSim_NPN" H 6750 5450 50 0000 R CNN
+F 2 "" H 7000 5400 29 0000 C CNN
+F 3 "" H 6800 5300 60 0000 C CNN
+ 1 6800 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 685BEC03
+P 7500 5800
+F 0 "Q7" H 7400 5850 50 0000 R CNN
+F 1 "eSim_NPN" H 7450 5950 50 0000 R CNN
+F 2 "" H 7700 5900 29 0000 C CNN
+F 3 "" H 7500 5800 60 0000 C CNN
+ 1 7500 5800
+ 1 0 0 -1
+$EndComp
+Text Label 1500 1600 0 60 ~ 0
+B1
+Text Label 1450 5350 0 60 ~ 0
+B2
+Text Label 5100 5300 0 60 ~ 0
+B3
+Text Label 5200 1550 0 60 ~ 0
+B4
+Text Label 4050 1050 0 60 ~ 0
+C1
+Text Label 4000 4800 0 60 ~ 0
+C2
+Text Label 7600 4750 0 60 ~ 0
+C3
+Text Label 7650 950 0 60 ~ 0
+C4
+$Comp
+L PORT U1
+U 11 1 685C0791
+P 1100 1600
+F 0 "U1" H 1150 1700 30 0000 C CNN
+F 1 "PORT" H 1100 1600 30 0000 C CNN
+F 2 "" H 1100 1600 60 0000 C CNN
+F 3 "" H 1100 1600 60 0000 C CNN
+ 11 1100 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685C092E
+P 1050 5350
+F 0 "U1" H 1100 5450 30 0000 C CNN
+F 1 "PORT" H 1050 5350 30 0000 C CNN
+F 2 "" H 1050 5350 60 0000 C CNN
+F 3 "" H 1050 5350 60 0000 C CNN
+ 10 1050 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685C0ADD
+P 3800 800
+F 0 "U1" H 3850 900 30 0000 C CNN
+F 1 "PORT" H 3800 800 30 0000 C CNN
+F 2 "" H 3800 800 60 0000 C CNN
+F 3 "" H 3800 800 60 0000 C CNN
+ 8 3800 800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685C0D14
+P 3750 4550
+F 0 "U1" H 3800 4650 30 0000 C CNN
+F 1 "PORT" H 3750 4550 30 0000 C CNN
+F 2 "" H 3750 4550 60 0000 C CNN
+F 3 "" H 3750 4550 60 0000 C CNN
+ 7 3750 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685C101B
+P 4700 1550
+F 0 "U1" H 4750 1650 30 0000 C CNN
+F 1 "PORT" H 4700 1550 30 0000 C CNN
+F 2 "" H 4700 1550 60 0000 C CNN
+F 3 "" H 4700 1550 60 0000 C CNN
+ 1 4700 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685C10B9
+P 7400 750
+F 0 "U1" H 7450 850 30 0000 C CNN
+F 1 "PORT" H 7400 750 30 0000 C CNN
+F 2 "" H 7400 750 60 0000 C CNN
+F 3 "" H 7400 750 60 0000 C CNN
+ 4 7400 750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685C12C6
+P 4650 5300
+F 0 "U1" H 4700 5400 30 0000 C CNN
+F 1 "PORT" H 4650 5300 30 0000 C CNN
+F 2 "" H 4650 5300 60 0000 C CNN
+F 3 "" H 4650 5300 60 0000 C CNN
+ 2 4650 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685C1552
+P 7350 4500
+F 0 "U1" H 7400 4600 30 0000 C CNN
+F 1 "PORT" H 7350 4500 30 0000 C CNN
+F 2 "" H 7350 4500 60 0000 C CNN
+F 3 "" H 7350 4500 60 0000 C CNN
+ 5 7350 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685C1705
+P 10400 3400
+F 0 "U1" H 10450 3500 30 0000 C CNN
+F 1 "PORT" H 10400 3400 30 0000 C CNN
+F 2 "" H 10400 3400 60 0000 C CNN
+F 3 "" H 10400 3400 60 0000 C CNN
+ 9 10400 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685C1962
+P 10400 3600
+F 0 "U1" H 10450 3700 30 0000 C CNN
+F 1 "PORT" H 10400 3600 30 0000 C CNN
+F 2 "" H 10400 3600 60 0000 C CNN
+F 3 "" H 10400 3600 60 0000 C CNN
+ 6 10400 3600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685C19D3
+P 10400 3800
+F 0 "U1" H 10450 3900 30 0000 C CNN
+F 1 "PORT" H 10400 3800 30 0000 C CNN
+F 2 "" H 10400 3800 60 0000 C CNN
+F 3 "" H 10400 3800 60 0000 C CNN
+ 3 10400 3800
+ -1 0 0 1
+$EndComp
+Text Label 8800 3450 0 60 ~ 0
+GND
+Wire Wire Line
+ 2000 1600 3050 1600
+Wire Wire Line
+ 2600 2100 2350 2100
+Wire Wire Line
+ 2350 2100 2350 1600
+Connection ~ 2350 1600
+Wire Wire Line
+ 2900 2100 3750 2100
+Wire Wire Line
+ 3350 1800 3350 2150
+Wire Wire Line
+ 3300 2700 3300 2150
+Wire Wire Line
+ 3300 2150 3350 2150
+Connection ~ 3350 2100
+Wire Wire Line
+ 3300 3000 3300 3500
+Wire Wire Line
+ 4050 3500 4050 2300
+Wire Wire Line
+ 1700 1600 1350 1600
+Wire Wire Line
+ 4050 800 4050 1900
+Wire Wire Line
+ 4050 1250 3350 1250
+Wire Wire Line
+ 3350 1250 3350 1400
+Connection ~ 4050 1250
+Wire Wire Line
+ 5600 1550 6650 1550
+Wire Wire Line
+ 6200 2050 5950 2050
+Wire Wire Line
+ 5950 2050 5950 1550
+Connection ~ 5950 1550
+Wire Wire Line
+ 6500 2050 7350 2050
+Wire Wire Line
+ 6950 1750 6950 2100
+Wire Wire Line
+ 6900 2650 6900 2100
+Wire Wire Line
+ 6900 2100 6950 2100
+Connection ~ 6950 2050
+Wire Wire Line
+ 6900 2950 6900 3450
+Wire Wire Line
+ 7650 3450 7650 2250
+Wire Wire Line
+ 5300 1550 4950 1550
+Wire Wire Line
+ 7650 750 7650 1850
+Wire Wire Line
+ 7650 1200 6950 1200
+Wire Wire Line
+ 6950 1200 6950 1350
+Connection ~ 7650 1200
+Wire Wire Line
+ 1950 5350 3000 5350
+Wire Wire Line
+ 2550 5850 2300 5850
+Wire Wire Line
+ 2300 5850 2300 5350
+Connection ~ 2300 5350
+Wire Wire Line
+ 2850 5850 3700 5850
+Wire Wire Line
+ 3300 5550 3300 5900
+Wire Wire Line
+ 3250 6450 3250 5900
+Wire Wire Line
+ 3250 5900 3300 5900
+Connection ~ 3300 5850
+Wire Wire Line
+ 3250 6750 3250 7250
+Wire Wire Line
+ 4000 7250 4000 6050
+Wire Wire Line
+ 1650 5350 1300 5350
+Wire Wire Line
+ 4000 4550 4000 5650
+Wire Wire Line
+ 4000 5000 3300 5000
+Wire Wire Line
+ 3300 5000 3300 5150
+Connection ~ 4000 5000
+Wire Wire Line
+ 5550 5300 6600 5300
+Wire Wire Line
+ 6150 5800 5900 5800
+Wire Wire Line
+ 5900 5800 5900 5300
+Connection ~ 5900 5300
+Wire Wire Line
+ 6450 5800 7300 5800
+Wire Wire Line
+ 6900 5500 6900 5850
+Wire Wire Line
+ 6850 6400 6850 5850
+Wire Wire Line
+ 6850 5850 6900 5850
+Connection ~ 6900 5800
+Wire Wire Line
+ 6850 7250 6850 6700
+Wire Wire Line
+ 7600 7250 7600 6000
+Wire Wire Line
+ 5250 5300 4900 5300
+Wire Wire Line
+ 7600 4500 7600 5600
+Wire Wire Line
+ 7600 4950 6900 4950
+Wire Wire Line
+ 6900 4950 6900 5100
+Connection ~ 7600 4950
+Wire Wire Line
+ 3250 7250 9400 7250
+Connection ~ 4000 7250
+Connection ~ 6850 7250
+Wire Wire Line
+ 9400 7250 9400 3450
+Wire Wire Line
+ 4200 3450 9550 3450
+Connection ~ 7600 7250
+Connection ~ 7650 3450
+Wire Wire Line
+ 4200 3450 4200 3500
+Wire Wire Line
+ 4200 3500 3300 3500
+Connection ~ 6900 3450
+Connection ~ 4050 3500
+NoConn ~ 10150 3400
+NoConn ~ 10150 3800
+Wire Wire Line
+ 10150 3600 9550 3600
+Wire Wire Line
+ 9550 3600 9550 3450
+Connection ~ 9400 3450
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/L702/L702.sub b/library/SubcircuitLibrary/L702/L702.sub
new file mode 100644
index 000000000..f0f13c42c
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/L702.sub
@@ -0,0 +1,27 @@
+* Subcircuit L702
+.subckt L702 /b4 /b3 ? /c4 /c3 /gnd /c2 /c1 ? /b2 /b1
+* c:\fossee\esim\library\subcircuitlibrary\l702\l702.cir
+.include NPN.lib
+r2 /b1 net-_q2-pad2_ 340
+r4 net-_q2-pad2_ net-_q2-pad3_ 7k
+r6 net-_q2-pad3_ /gnd 500
+q2 /c1 net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q4 /c1 net-_q2-pad3_ /gnd Q2N2222
+r8 /b4 net-_q6-pad2_ 340
+r10 net-_q6-pad2_ net-_q6-pad3_ 7k
+r12 net-_q6-pad3_ /gnd 500
+q6 /c4 net-_q6-pad2_ net-_q6-pad3_ Q2N2222
+q8 /c4 net-_q6-pad3_ /gnd Q2N2222
+r1 /b2 net-_q1-pad2_ 340
+r3 net-_q1-pad2_ net-_q1-pad3_ 7k
+r5 net-_q1-pad3_ /gnd 500
+q1 /c2 net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+q3 /c2 net-_q1-pad3_ /gnd Q2N2222
+r7 /b3 net-_q5-pad2_ 340
+r9 net-_q5-pad2_ net-_q5-pad3_ 7k
+r11 net-_q5-pad3_ /gnd 500
+q5 /c3 net-_q5-pad2_ net-_q5-pad3_ Q2N2222
+q7 /c3 net-_q5-pad3_ /gnd Q2N2222
+* Control Statements
+
+.ends L702
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/L702/L702_Previous_Values.xml b/library/SubcircuitLibrary/L702/L702_Previous_Values.xml
new file mode 100644
index 000000000..17402ef44
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/L702_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/L702/NPN.lib b/library/SubcircuitLibrary/L702/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/L702/analysis b/library/SubcircuitLibrary/L702/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/L702/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LH0004/D.lib b/library/SubcircuitLibrary/LH0004/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/LH0004/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/LH0004/LH0004-cache.lib b/library/SubcircuitLibrary/LH0004/LH0004-cache.lib
index 49c594fc8..f970ce61c 100644
--- a/library/SubcircuitLibrary/LH0004/LH0004-cache.lib
+++ b/library/SubcircuitLibrary/LH0004/LH0004-cache.lib
@@ -1,102 +1,102 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# eSim_NPN
-#
-DEF eSim_NPN Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_NPN" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-ALIAS BC547 Q2N2222
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
-X C 1 100 200 100 D 50 50 1 1 P
-X B 2 -200 0 225 R 50 50 1 1 P
-X E 3 100 -200 100 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_PNP
-#
-DEF eSim_PNP Q 0 0 Y N 1 F N
-F0 "Q" -100 50 50 H V R CNN
-F1 "eSim_PNP" -50 150 50 H V R CNN
-F2 "" 200 100 29 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-C 50 0 111 0 1 10 N
-P 2 0 1 0 25 25 100 100 N
-P 3 0 1 0 25 -25 100 -100 100 -100 N
-P 3 0 1 20 25 75 25 -75 25 -75 N
-P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
-X C 1 100 200 100 D 50 50 1 1 P
-X B 2 -200 0 225 R 50 50 1 1 P
-X E 3 100 -200 100 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# eSim_R
-#
-DEF eSim_R R 0 0 N Y 1 F N
-F0 "R" 50 130 50 H V C CNN
-F1 "eSim_R" 50 -50 50 H V C CNN
-F2 "" 50 -20 30 H V C CNN
-F3 "" 50 50 30 V V C CNN
-ALIAS resistor
-$FPLIST
- R_*
- Resistor_*
-$ENDFPLIST
-DRAW
-S 150 10 -50 90 0 1 10 N
-X ~ 1 -100 50 50 R 60 60 1 1 P
-X ~ 2 200 50 50 L 60 60 1 1 P
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LH0004/LH0004.cir b/library/SubcircuitLibrary/LH0004/LH0004.cir
index bf9775e4e..eb210e8b2 100644
--- a/library/SubcircuitLibrary/LH0004/LH0004.cir
+++ b/library/SubcircuitLibrary/LH0004/LH0004.cir
@@ -1,28 +1,28 @@
-* C:\FOSSEE\eSim\library\SubcircuitLibrary\LH0004\LH0004.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 07/12/25 14:24:38
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-Q5 Net-_Q5-Pad1_ Net-_Q4-Pad1_ Net-_Q5-Pad3_ eSim_NPN
-Q8 Net-_Q10-Pad2_ Net-_Q1-Pad1_ Net-_Q5-Pad3_ eSim_NPN
-Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP
-Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q1-Pad3_ eSim_PNP
-R2 Net-_Q1-Pad1_ Net-_Q10-Pad1_ 300k
-R4 Net-_Q4-Pad1_ Net-_Q10-Pad1_ 300k
-R6 Net-_Q5-Pad3_ Net-_Q10-Pad1_ 50k
-Q3 Net-_Q1-Pad3_ Net-_Q2-Pad1_ Net-_Q2-Pad2_ eSim_PNP
-Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_PNP
-R3 Net-_Q2-Pad3_ Net-_Q2-Pad2_ 40k
-R1 Net-_Q2-Pad1_ Net-_R1-Pad2_ 600k
-Q6 Net-_Q5-Pad1_ Net-_Q5-Pad1_ Net-_Q6-Pad3_ eSim_PNP
-Q7 Net-_Q10-Pad2_ Net-_Q5-Pad1_ Net-_Q7-Pad3_ eSim_PNP
-R5 Net-_Q2-Pad3_ Net-_Q6-Pad3_ 50k
-R7 Net-_Q2-Pad3_ Net-_Q7-Pad3_ 50k
-Q9 Net-_Q2-Pad3_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
-Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_PNP
-U1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q10-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_R1-Pad2_ Net-_Q10-Pad3_ Net-_Q2-Pad3_ Net-_Q10-Pad2_ PORT
-
-.end
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\LH0004\LH0004.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/05/25 11:43:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP
+Q3 Net-_Q2-Pad3_ Net-_Q1-Pad1_ Net-_Q1-Pad2_ eSim_PNP
+R3 Net-_Q1-Pad3_ Net-_Q1-Pad2_ 40K
+R1 Net-_Q1-Pad1_ Net-_R1-Pad2_ 600K
+Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_PNP
+Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_Q2-Pad3_ eSim_PNP
+R2 Net-_Q2-Pad1_ Net-_Q10-Pad1_ 300K
+R4 Net-_Q4-Pad1_ Net-_Q10-Pad1_ 300K
+R5 Net-_Q1-Pad3_ Net-_Q6-Pad3_ 50K
+Q6 Net-_Q5-Pad1_ Net-_Q5-Pad1_ Net-_Q6-Pad3_ eSim_PNP
+Q7 Net-_Q10-Pad2_ Net-_Q5-Pad1_ Net-_Q7-Pad3_ eSim_PNP
+R7 Net-_Q1-Pad3_ Net-_Q7-Pad3_ 50K
+Q5 Net-_Q5-Pad1_ Net-_Q4-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+Q8 Net-_Q10-Pad2_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+R6 Net-_Q5-Pad3_ Net-_Q10-Pad1_ 50K
+Q9 Net-_Q1-Pad3_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+U1 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q10-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad1_ Net-_Q1-Pad1_ Net-_R1-Pad2_ Net-_Q10-Pad3_ Net-_Q1-Pad3_ Net-_Q10-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/LH0004/LH0004.cir.out b/library/SubcircuitLibrary/LH0004/LH0004.cir.out
index 4622a95ca..d4a9a1404 100644
--- a/library/SubcircuitLibrary/LH0004/LH0004.cir.out
+++ b/library/SubcircuitLibrary/LH0004/LH0004.cir.out
@@ -1,31 +1,31 @@
-* c:\fossee\esim\library\subcircuitlibrary\lh0004\lh0004.cir
-
-.include NPN.lib
-.include PNP.lib
-q5 net-_q5-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222
-q8 net-_q10-pad2_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
-q4 net-_q4-pad1_ net-_q4-pad2_ net-_q1-pad3_ Q2N2907A
-r2 net-_q1-pad1_ net-_q10-pad1_ 300k
-r4 net-_q4-pad1_ net-_q10-pad1_ 300k
-r6 net-_q5-pad3_ net-_q10-pad1_ 50k
-q3 net-_q1-pad3_ net-_q2-pad1_ net-_q2-pad2_ Q2N2907A
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A
-r3 net-_q2-pad3_ net-_q2-pad2_ 40k
-r1 net-_q2-pad1_ net-_r1-pad2_ 600k
-q6 net-_q5-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2907A
-q7 net-_q10-pad2_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A
-r5 net-_q2-pad3_ net-_q6-pad3_ 50k
-r7 net-_q2-pad3_ net-_q7-pad3_ 50k
-q9 net-_q2-pad3_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A
-* u1 net-_q1-pad1_ net-_q1-pad2_ net-_q10-pad1_ net-_q4-pad2_ net-_q4-pad1_ net-_q2-pad1_ net-_r1-pad2_ net-_q10-pad3_ net-_q2-pad3_ net-_q10-pad2_ port
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\fossee\esim\library\subcircuitlibrary\lh0004\lh0004.cir
+
+.include PNP.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
+q3 net-_q2-pad3_ net-_q1-pad1_ net-_q1-pad2_ Q2N2907A
+r3 net-_q1-pad3_ net-_q1-pad2_ 40k
+r1 net-_q1-pad1_ net-_r1-pad2_ 600k
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A
+q4 net-_q4-pad1_ net-_q4-pad2_ net-_q2-pad3_ Q2N2907A
+r2 net-_q2-pad1_ net-_q10-pad1_ 300k
+r4 net-_q4-pad1_ net-_q10-pad1_ 300k
+r5 net-_q1-pad3_ net-_q6-pad3_ 50k
+q6 net-_q5-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2907A
+q7 net-_q10-pad2_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A
+r7 net-_q1-pad3_ net-_q7-pad3_ 50k
+q5 net-_q5-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222
+q8 net-_q10-pad2_ net-_q2-pad1_ net-_q5-pad3_ Q2N2222
+r6 net-_q5-pad3_ net-_q10-pad1_ 50k
+q9 net-_q1-pad3_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A
+* u1 net-_q2-pad1_ net-_q2-pad2_ net-_q10-pad1_ net-_q4-pad2_ net-_q4-pad1_ net-_q1-pad1_ net-_r1-pad2_ net-_q10-pad3_ net-_q1-pad3_ net-_q10-pad2_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LH0004/LH0004.sch b/library/SubcircuitLibrary/LH0004/LH0004.sch
index 7edb94671..c565942ee 100644
--- a/library/SubcircuitLibrary/LH0004/LH0004.sch
+++ b/library/SubcircuitLibrary/LH0004/LH0004.sch
@@ -1,476 +1,462 @@
-EESchema Schematic File Version 2
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:power
-LIBS:eSim_Plot
-LIBS:transistors
-LIBS:conn
-LIBS:eSim_User
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Power
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_Nghdl
-LIBS:eSim_Ngveri
-LIBS:eSim_SKY130
-LIBS:eSim_SKY130_Subckts
-LIBS:LH0004_My-cache
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
-Comment2 ""
-Comment3 ""
-Comment4 ""
-$EndDescr
-$Comp
-L eSim_NPN Q5
-U 1 1 68385F3D
-P 4500 3550
-F 0 "Q5" H 4400 3600 50 0000 R CNN
-F 1 "eSim_NPN" H 4450 3700 50 0000 R CNN
-F 2 "" H 4700 3650 29 0000 C CNN
-F 3 "" H 4500 3550 60 0000 C CNN
- 1 4500 3550
- 1 0 0 -1
-$EndComp
-$Comp
-L eSim_NPN Q8
-U 1 1 68385F53
-P 6000 3500
-F 0 "Q8" H 5900 3550 50 0000 R CNN
-F 1 "eSim_NPN" H 5950 3650 50 0000 R CNN
-F 2 "" H 6200 3600 29 0000 C CNN
-F 3 "" H 6000 3500 60 0000 C CNN
- 1 6000 3500
- -1 0 0 -1
-$EndComp
-$Comp
-L eSim_PNP Q1
-U 1 1 68385FB2
-P 2750 2050
-F 0 "Q1" H 2650 2100 50 0000 R CNN
-F 1 "eSim_PNP" H 2700 2200 50 0000 R CNN
-F 2 "" H 2950 2150 29 0000 C CNN
-F 3 "" H 2750 2050 60 0000 C CNN
- 1 2750 2050
- 1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q4
-U 1 1 68385FD4
-P 3750 2050
-F 0 "Q4" H 3650 2100 50 0000 R CNN
-F 1 "eSim_PNP" H 3700 2200 50 0000 R CNN
-F 2 "" H 3950 2150 29 0000 C CNN
-F 3 "" H 3750 2050 60 0000 C CNN
- 1 3750 2050
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 2850 1850 3650 1850
-Wire Wire Line
- 4600 3750 5900 3750
-Wire Wire Line
- 5900 3750 5900 3700
-$Comp
-L resistor R2
-U 1 1 683860A3
-P 2800 3850
-F 0 "R2" H 2850 3980 50 0000 C CNN
-F 1 "300k" H 2850 3800 50 0000 C CNN
-F 2 "" H 2850 3830 30 0000 C CNN
-F 3 "" V 2850 3900 30 0000 C CNN
- 1 2800 3850
- 0 1 1 0
-$EndComp
-$Comp
-L resistor R4
-U 1 1 68386106
-P 3600 3850
-F 0 "R4" H 3650 3980 50 0000 C CNN
-F 1 "300k" H 3650 3800 50 0000 C CNN
-F 2 "" H 3650 3830 30 0000 C CNN
-F 3 "" V 3650 3900 30 0000 C CNN
- 1 3600 3850
- 0 1 1 0
-$EndComp
-$Comp
-L resistor R6
-U 1 1 68386132
-P 5200 4000
-F 0 "R6" H 5250 4130 50 0000 C CNN
-F 1 "50k" H 5250 3950 50 0000 C CNN
-F 2 "" H 5250 3980 30 0000 C CNN
-F 3 "" V 5250 4050 30 0000 C CNN
- 1 5200 4000
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 5250 3900 5250 3750
-Connection ~ 5250 3750
-Wire Wire Line
- 3650 2250 3650 3750
-Wire Wire Line
- 2850 2250 2850 3750
-Connection ~ 3650 4200
-$Comp
-L eSim_PNP Q3
-U 1 1 68386221
-P 3200 1200
-F 0 "Q3" H 3100 1250 50 0000 R CNN
-F 1 "eSim_PNP" H 3150 1350 50 0000 R CNN
-F 2 "" H 3400 1300 29 0000 C CNN
-F 3 "" H 3200 1200 60 0000 C CNN
- 1 3200 1200
- 1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q2
-U 1 1 68386261
-P 2950 750
-F 0 "Q2" H 2850 800 50 0000 R CNN
-F 1 "eSim_PNP" H 2900 900 50 0000 R CNN
-F 2 "" H 3150 850 29 0000 C CNN
-F 3 "" H 2950 750 60 0000 C CNN
- 1 2950 750
- -1 0 0 1
-$EndComp
-Wire Wire Line
- 3300 1400 3300 1850
-Connection ~ 3300 1850
-Wire Wire Line
- 2850 950 2850 1350
-Wire Wire Line
- 2300 1200 3000 1200
-Wire Wire Line
- 3150 750 3300 750
-Wire Wire Line
- 3300 650 3300 1000
-$Comp
-L resistor R3
-U 1 1 68386368
-P 3250 450
-F 0 "R3" H 3300 580 50 0000 C CNN
-F 1 "40k" H 3300 400 50 0000 C CNN
-F 2 "" H 3300 430 30 0000 C CNN
-F 3 "" V 3300 500 30 0000 C CNN
- 1 3250 450
- 0 1 1 0
-$EndComp
-Connection ~ 3300 750
-Wire Wire Line
- 2850 550 2850 350
-Wire Wire Line
- 2850 350 6550 350
-$Comp
-L resistor R1
-U 1 1 68386412
-P 2800 1450
-F 0 "R1" H 2850 1580 50 0000 C CNN
-F 1 "600k" H 2850 1400 50 0000 C CNN
-F 2 "" H 2850 1430 30 0000 C CNN
-F 3 "" V 2850 1500 30 0000 C CNN
- 1 2800 1450
- 0 1 1 0
-$EndComp
-Connection ~ 2850 1200
-Wire Wire Line
- 2200 1650 2850 1650
-$Comp
-L eSim_PNP Q6
-U 1 1 6838659D
-P 4800 1150
-F 0 "Q6" H 4700 1200 50 0000 R CNN
-F 1 "eSim_PNP" H 4750 1300 50 0000 R CNN
-F 2 "" H 5000 1250 29 0000 C CNN
-F 3 "" H 4800 1150 60 0000 C CNN
- 1 4800 1150
- -1 0 0 1
-$EndComp
-$Comp
-L eSim_PNP Q7
-U 1 1 683865E5
-P 5650 1150
-F 0 "Q7" H 5550 1200 50 0000 R CNN
-F 1 "eSim_PNP" H 5600 1300 50 0000 R CNN
-F 2 "" H 5850 1250 29 0000 C CNN
-F 3 "" H 5650 1150 60 0000 C CNN
- 1 5650 1150
- 1 0 0 1
-$EndComp
-Wire Wire Line
- 5000 1150 5450 1150
-Wire Wire Line
- 4700 1350 4700 3350
-Wire Wire Line
- 4700 3350 4600 3350
-Wire Wire Line
- 5750 1350 5750 3300
-Wire Wire Line
- 5750 3300 5900 3300
-Wire Wire Line
- 5150 1150 5150 1550
-Wire Wire Line
- 5150 1550 4700 1550
-Connection ~ 4700 1550
-Connection ~ 5150 1150
-$Comp
-L resistor R5
-U 1 1 68386991
-P 4650 650
-F 0 "R5" H 4700 780 50 0000 C CNN
-F 1 "50k" H 4700 600 50 0000 C CNN
-F 2 "" H 4700 630 30 0000 C CNN
-F 3 "" V 4700 700 30 0000 C CNN
- 1 4650 650
- 0 1 1 0
-$EndComp
-$Comp
-L resistor R7
-U 1 1 68386A13
-P 5700 650
-F 0 "R7" H 5750 780 50 0000 C CNN
-F 1 "50k" H 5750 600 50 0000 C CNN
-F 2 "" H 5750 630 30 0000 C CNN
-F 3 "" V 5750 700 30 0000 C CNN
- 1 5700 650
- 0 1 1 0
-$EndComp
-Wire Wire Line
- 4700 850 4700 950
-Wire Wire Line
- 5750 850 5750 950
-Wire Wire Line
- 4700 350 4700 550
-Connection ~ 3300 350
-Wire Wire Line
- 5750 350 5750 550
-Connection ~ 4700 350
-$Comp
-L eSim_NPN Q9
-U 1 1 68386B81
-P 6450 2100
-F 0 "Q9" H 6350 2150 50 0000 R CNN
-F 1 "eSim_NPN" H 6400 2250 50 0000 R CNN
-F 2 "" H 6650 2200 29 0000 C CNN
-F 3 "" H 6450 2100 60 0000 C CNN
- 1 6450 2100
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 2100 3550 4300 3550
-Connection ~ 3650 3550
-Wire Wire Line
- 6200 3150 6200 3500
-Wire Wire Line
- 1750 3150 6200 3150
-Connection ~ 2850 3150
-$Comp
-L eSim_PNP Q10
-U 1 1 68386E1B
-P 6450 2650
-F 0 "Q10" H 6350 2700 50 0000 R CNN
-F 1 "eSim_PNP" H 6400 2800 50 0000 R CNN
-F 2 "" H 6650 2750 29 0000 C CNN
-F 3 "" H 6450 2650 60 0000 C CNN
- 1 6450 2650
- 1 0 0 1
-$EndComp
-Wire Wire Line
- 6550 2300 6550 2450
-Wire Wire Line
- 6550 4200 6550 2850
-Connection ~ 5250 4200
-Wire Wire Line
- 6250 2100 6250 2650
-Wire Wire Line
- 6550 350 6550 1900
-Connection ~ 5750 350
-Wire Wire Line
- 5750 2250 6250 2250
-Connection ~ 6250 2250
-Connection ~ 5750 2250
-Wire Wire Line
- 3650 4050 3650 4200
-Wire Wire Line
- 2850 4050 2850 4200
-Wire Wire Line
- 1650 2050 2550 2050
-Wire Wire Line
- 3950 2550 3950 2050
-Wire Wire Line
- 4700 4200 4700 4350
-Connection ~ 4700 4200
-Wire Wire Line
- 5600 -350 5600 350
-Connection ~ 5600 350
-Wire Wire Line
- 6550 2400 7600 2400
-Connection ~ 6550 2400
-Connection ~ 2850 4200
-Wire Wire Line
- 2850 4200 6550 4200
-Wire Wire Line
- 5750 2900 7550 2900
-Connection ~ 5750 2900
-Wire Wire Line
- 1750 2550 3950 2550
-Wire Wire Line
- 1750 2450 1750 2550
-$Comp
-L PORT U1
-U 6 1 6839B4BA
-P 1900 1150
-F 0 "U1" H 1950 1250 30 0000 C CNN
-F 1 "PORT" H 1900 1150 30 0000 C CNN
-F 2 "" H 1900 1150 60 0000 C CNN
-F 3 "" H 1900 1150 60 0000 C CNN
- 6 1900 1150
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 7 1 6839B53D
-P 1950 1650
-F 0 "U1" H 2000 1750 30 0000 C CNN
-F 1 "PORT" H 1950 1650 30 0000 C CNN
-F 2 "" H 1950 1650 60 0000 C CNN
-F 3 "" H 1950 1650 60 0000 C CNN
- 7 1950 1650
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 2 1 6839B58C
-P 1400 2050
-F 0 "U1" H 1450 2150 30 0000 C CNN
-F 1 "PORT" H 1400 2050 30 0000 C CNN
-F 2 "" H 1400 2050 60 0000 C CNN
-F 3 "" H 1400 2050 60 0000 C CNN
- 2 1400 2050
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 6839B662
-P 1450 2450
-F 0 "U1" H 1500 2550 30 0000 C CNN
-F 1 "PORT" H 1450 2450 30 0000 C CNN
-F 2 "" H 1450 2450 60 0000 C CNN
-F 3 "" H 1450 2450 60 0000 C CNN
- 4 1450 2450
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 1 1 6839B6BB
-P 1500 3150
-F 0 "U1" H 1550 3250 30 0000 C CNN
-F 1 "PORT" H 1500 3150 30 0000 C CNN
-F 2 "" H 1500 3150 60 0000 C CNN
-F 3 "" H 1500 3150 60 0000 C CNN
- 1 1500 3150
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 6839B7A7
-P 1850 3550
-F 0 "U1" H 1900 3650 30 0000 C CNN
-F 1 "PORT" H 1850 3550 30 0000 C CNN
-F 2 "" H 1850 3550 60 0000 C CNN
-F 3 "" H 1850 3550 60 0000 C CNN
- 5 1850 3550
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 6839B806
-P 4350 4350
-F 0 "U1" H 4400 4450 30 0000 C CNN
-F 1 "PORT" H 4350 4350 30 0000 C CNN
-F 2 "" H 4350 4350 60 0000 C CNN
-F 3 "" H 4350 4350 60 0000 C CNN
- 3 4350 4350
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 9 1 6839BA26
-P 5200 -350
-F 0 "U1" H 5250 -250 30 0000 C CNN
-F 1 "PORT" H 5200 -350 30 0000 C CNN
-F 2 "" H 5200 -350 60 0000 C CNN
-F 3 "" H 5200 -350 60 0000 C CNN
- 9 5200 -350
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 8 1 6839BBC4
-P 7350 2200
-F 0 "U1" H 7400 2300 30 0000 C CNN
-F 1 "PORT" H 7350 2200 30 0000 C CNN
-F 2 "" H 7350 2200 60 0000 C CNN
-F 3 "" H 7350 2200 60 0000 C CNN
- 8 7350 2200
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 10 1 6839BD62
-P 7300 3050
-F 0 "U1" H 7350 3150 30 0000 C CNN
-F 1 "PORT" H 7300 3050 30 0000 C CNN
-F 2 "" H 7300 3050 60 0000 C CNN
-F 3 "" H 7300 3050 60 0000 C CNN
- 10 7300 3050
- 1 0 0 -1
-$EndComp
-Wire Wire Line
- 5450 -350 5600 -350
-Wire Wire Line
- 2150 1150 2300 1150
-Wire Wire Line
- 2300 1150 2300 1200
-Wire Wire Line
- 1700 2450 1750 2450
-Wire Wire Line
- 4700 4350 4600 4350
-Wire Wire Line
- 7550 2900 7550 3050
-Wire Wire Line
- 7600 2400 7600 2200
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_PNP Q1
+U 1 1 68412DDE
+P 4300 2350
+F 0 "Q1" H 4200 2400 50 0000 R CNN
+F 1 "eSim_PNP" H 4250 2500 50 0000 R CNN
+F 2 "" H 4500 2450 29 0000 C CNN
+F 3 "" H 4300 2350 60 0000 C CNN
+ 1 4300 2350
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q3
+U 1 1 68412E2C
+P 4650 3000
+F 0 "Q3" H 4550 3050 50 0000 R CNN
+F 1 "eSim_PNP" H 4600 3150 50 0000 R CNN
+F 2 "" H 4850 3100 29 0000 C CNN
+F 3 "" H 4650 3000 60 0000 C CNN
+ 1 4650 3000
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 68412E7F
+P 4700 1950
+F 0 "R3" H 4750 2080 50 0000 C CNN
+F 1 "40K" H 4750 1900 50 0000 C CNN
+F 2 "" H 4750 1930 30 0000 C CNN
+F 3 "" V 4750 2000 30 0000 C CNN
+ 1 4700 1950
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R1
+U 1 1 68412FBE
+P 4150 3300
+F 0 "R1" H 4200 3430 50 0000 C CNN
+F 1 "600K" H 4200 3250 50 0000 C CNN
+F 2 "" H 4200 3280 30 0000 C CNN
+F 3 "" V 4200 3350 30 0000 C CNN
+ 1 4150 3300
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_PNP Q2
+U 1 1 68412FF4
+P 4300 4050
+F 0 "Q2" H 4200 4100 50 0000 R CNN
+F 1 "eSim_PNP" H 4250 4200 50 0000 R CNN
+F 2 "" H 4500 4150 29 0000 C CNN
+F 3 "" H 4300 4050 60 0000 C CNN
+ 1 4300 4050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q4
+U 1 1 6841304F
+P 5100 4050
+F 0 "Q4" H 5000 4100 50 0000 R CNN
+F 1 "eSim_PNP" H 5050 4200 50 0000 R CNN
+F 2 "" H 5300 4150 29 0000 C CNN
+F 3 "" H 5100 4050 60 0000 C CNN
+ 1 5100 4050
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 6841308D
+P 4350 4850
+F 0 "R2" H 4400 4980 50 0000 C CNN
+F 1 "300K" H 4400 4800 50 0000 C CNN
+F 2 "" H 4400 4830 30 0000 C CNN
+F 3 "" V 4400 4900 30 0000 C CNN
+ 1 4350 4850
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 68413107
+P 4950 4850
+F 0 "R4" H 5000 4980 50 0000 C CNN
+F 1 "300K" H 5000 4800 50 0000 C CNN
+F 2 "" H 5000 4830 30 0000 C CNN
+F 3 "" V 5000 4900 30 0000 C CNN
+ 1 4950 4850
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R5
+U 1 1 68413149
+P 5650 2100
+F 0 "R5" H 5700 2230 50 0000 C CNN
+F 1 "50K" H 5700 2050 50 0000 C CNN
+F 2 "" H 5700 2080 30 0000 C CNN
+F 3 "" V 5700 2150 30 0000 C CNN
+ 1 5650 2100
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_PNP Q6
+U 1 1 684131C2
+P 5800 3000
+F 0 "Q6" H 5700 3050 50 0000 R CNN
+F 1 "eSim_PNP" H 5750 3150 50 0000 R CNN
+F 2 "" H 6000 3100 29 0000 C CNN
+F 3 "" H 5800 3000 60 0000 C CNN
+ 1 5800 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q7
+U 1 1 68413204
+P 6400 3000
+F 0 "Q7" H 6300 3050 50 0000 R CNN
+F 1 "eSim_PNP" H 6350 3150 50 0000 R CNN
+F 2 "" H 6600 3100 29 0000 C CNN
+F 3 "" H 6400 3000 60 0000 C CNN
+ 1 6400 3000
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R7
+U 1 1 68413253
+P 6450 2100
+F 0 "R7" H 6500 2230 50 0000 C CNN
+F 1 "50K" H 6500 2050 50 0000 C CNN
+F 2 "" H 6500 2080 30 0000 C CNN
+F 3 "" V 6500 2150 30 0000 C CNN
+ 1 6450 2100
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 68413293
+P 5600 4500
+F 0 "Q5" H 5500 4550 50 0000 R CNN
+F 1 "eSim_NPN" H 5550 4650 50 0000 R CNN
+F 2 "" H 5800 4600 29 0000 C CNN
+F 3 "" H 5600 4500 60 0000 C CNN
+ 1 5600 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 684133A8
+P 6600 4500
+F 0 "Q8" H 6500 4550 50 0000 R CNN
+F 1 "eSim_NPN" H 6550 4650 50 0000 R CNN
+F 2 "" H 6800 4600 29 0000 C CNN
+F 3 "" H 6600 4500 60 0000 C CNN
+ 1 6600 4500
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R6
+U 1 1 684136BF
+P 6050 4850
+F 0 "R6" H 6100 4980 50 0000 C CNN
+F 1 "50K" H 6100 4800 50 0000 C CNN
+F 2 "" H 6100 4830 30 0000 C CNN
+F 3 "" V 6100 4900 30 0000 C CNN
+ 1 6050 4850
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 6841371F
+P 7200 2800
+F 0 "Q9" H 7100 2850 50 0000 R CNN
+F 1 "eSim_NPN" H 7150 2950 50 0000 R CNN
+F 2 "" H 7400 2900 29 0000 C CNN
+F 3 "" H 7200 2800 60 0000 C CNN
+ 1 7200 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q10
+U 1 1 68413DCF
+P 7200 3800
+F 0 "Q10" H 7100 3850 50 0000 R CNN
+F 1 "eSim_PNP" H 7150 3950 50 0000 R CNN
+F 2 "" H 7400 3900 29 0000 C CNN
+F 3 "" H 7200 3800 60 0000 C CNN
+ 1 7200 3800
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 4500 2350 4750 2350
+Wire Wire Line
+ 4750 2150 4750 2800
+Connection ~ 4750 2350
+Wire Wire Line
+ 4200 2550 4200 3200
+Wire Wire Line
+ 3850 3000 4450 3000
+Connection ~ 4200 3000
+Wire Wire Line
+ 4400 3850 5000 3850
+Wire Wire Line
+ 4750 3850 4750 3200
+Connection ~ 4750 3850
+Wire Wire Line
+ 4400 4250 4400 4750
+Wire Wire Line
+ 5000 4250 5000 4750
+Wire Wire Line
+ 4400 5050 4400 5400
+Wire Wire Line
+ 4400 5400 7550 5400
+Wire Wire Line
+ 6100 5400 6100 5050
+Wire Wire Line
+ 5000 5050 5000 5400
+Connection ~ 5000 5400
+Wire Wire Line
+ 3850 4500 5400 4500
+Connection ~ 5000 4500
+Wire Wire Line
+ 6500 3200 6500 4300
+Wire Wire Line
+ 5700 3200 5700 4300
+Wire Wire Line
+ 5700 3500 6100 3500
+Wire Wire Line
+ 6100 3500 6100 3000
+Wire Wire Line
+ 6000 3000 6200 3000
+Connection ~ 5700 3500
+Connection ~ 6100 3000
+Wire Wire Line
+ 5700 2300 5700 2800
+Wire Wire Line
+ 6500 2800 6500 2300
+Wire Wire Line
+ 4200 2150 4200 1550
+Wire Wire Line
+ 4200 1550 7500 1550
+Wire Wire Line
+ 7300 1550 7300 2600
+Wire Wire Line
+ 6500 2000 6500 1550
+Connection ~ 6500 1550
+Wire Wire Line
+ 5700 2000 5700 1550
+Connection ~ 5700 1550
+Wire Wire Line
+ 4750 1850 4750 1550
+Connection ~ 4750 1550
+Wire Wire Line
+ 3850 4300 6900 4300
+Wire Wire Line
+ 6900 4300 6900 4500
+Wire Wire Line
+ 6900 4500 6800 4500
+Connection ~ 4400 4300
+Wire Wire Line
+ 5700 4700 6500 4700
+Wire Wire Line
+ 6100 4700 6100 4750
+Connection ~ 6100 4700
+Wire Wire Line
+ 7300 5400 7300 4000
+Connection ~ 6100 5400
+Wire Wire Line
+ 7300 3000 7300 3600
+Wire Wire Line
+ 6500 3300 6900 3300
+Wire Wire Line
+ 6900 2800 7000 2800
+Connection ~ 6500 3300
+$Comp
+L PORT U1
+U 6 1 6841456E
+P 3600 3000
+F 0 "U1" H 3650 3100 30 0000 C CNN
+F 1 "PORT" H 3600 3000 30 0000 C CNN
+F 2 "" H 3600 3000 60 0000 C CNN
+F 3 "" H 3600 3000 60 0000 C CNN
+ 6 3600 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684145EF
+P 7800 4100
+F 0 "U1" H 7850 4200 30 0000 C CNN
+F 1 "PORT" H 7800 4100 30 0000 C CNN
+F 2 "" H 7800 4100 60 0000 C CNN
+F 3 "" H 7800 4100 60 0000 C CNN
+ 10 7800 4100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6841462C
+P 7750 1550
+F 0 "U1" H 7800 1650 30 0000 C CNN
+F 1 "PORT" H 7750 1550 30 0000 C CNN
+F 2 "" H 7750 1550 60 0000 C CNN
+F 3 "" H 7750 1550 60 0000 C CNN
+ 9 7750 1550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6841466B
+P 3600 3750
+F 0 "U1" H 3650 3850 30 0000 C CNN
+F 1 "PORT" H 3600 3750 30 0000 C CNN
+F 2 "" H 3600 3750 60 0000 C CNN
+F 3 "" H 3600 3750 60 0000 C CNN
+ 4 3600 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684146B0
+P 3600 3600
+F 0 "U1" H 3650 3700 30 0000 C CNN
+F 1 "PORT" H 3600 3600 30 0000 C CNN
+F 2 "" H 3600 3600 60 0000 C CNN
+F 3 "" H 3600 3600 60 0000 C CNN
+ 7 3600 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 684146F3
+P 7800 3250
+F 0 "U1" H 7850 3350 30 0000 C CNN
+F 1 "PORT" H 7800 3250 30 0000 C CNN
+F 2 "" H 7800 3250 60 0000 C CNN
+F 3 "" H 7800 3250 60 0000 C CNN
+ 8 7800 3250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68414738
+P 3600 4300
+F 0 "U1" H 3650 4400 30 0000 C CNN
+F 1 "PORT" H 3600 4300 30 0000 C CNN
+F 2 "" H 3600 4300 60 0000 C CNN
+F 3 "" H 3600 4300 60 0000 C CNN
+ 1 3600 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684147D4
+P 3600 4050
+F 0 "U1" H 3650 4150 30 0000 C CNN
+F 1 "PORT" H 3600 4050 30 0000 C CNN
+F 2 "" H 3600 4050 60 0000 C CNN
+F 3 "" H 3600 4050 60 0000 C CNN
+ 2 3600 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68414829
+P 3600 4500
+F 0 "U1" H 3650 4600 30 0000 C CNN
+F 1 "PORT" H 3600 4500 30 0000 C CNN
+F 2 "" H 3600 4500 60 0000 C CNN
+F 3 "" H 3600 4500 60 0000 C CNN
+ 5 3600 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68414874
+P 7800 5400
+F 0 "U1" H 7850 5500 30 0000 C CNN
+F 1 "PORT" H 7800 5400 30 0000 C CNN
+F 2 "" H 7800 5400 60 0000 C CNN
+F 3 "" H 7800 5400 60 0000 C CNN
+ 3 7800 5400
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 3850 3600 4200 3600
+Wire Wire Line
+ 4200 3600 4200 3500
+Wire Wire Line
+ 3850 3750 5400 3750
+Wire Wire Line
+ 5400 3750 5400 4050
+Wire Wire Line
+ 5400 4050 5300 4050
+Wire Wire Line
+ 3850 4050 4100 4050
+Connection ~ 7300 5400
+Connection ~ 6900 3300
+Wire Wire Line
+ 7300 3250 7550 3250
+Connection ~ 7300 3250
+Connection ~ 7300 1550
+Wire Wire Line
+ 6900 2800 6900 3800
+Wire Wire Line
+ 6900 3800 7000 3800
+Wire Wire Line
+ 7550 4100 6500 4100
+Connection ~ 6500 4100
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/LH0004/LH0004.sub b/library/SubcircuitLibrary/LH0004/LH0004.sub
index 8be7e7554..910480465 100644
--- a/library/SubcircuitLibrary/LH0004/LH0004.sub
+++ b/library/SubcircuitLibrary/LH0004/LH0004.sub
@@ -1,25 +1,25 @@
-* Subcircuit LH0004
-.subckt LH0004 net-_q1-pad1_ net-_q1-pad2_ net-_q10-pad1_ net-_q4-pad2_ net-_q4-pad1_ net-_q2-pad1_ net-_r1-pad2_ net-_q10-pad3_ net-_q2-pad3_ net-_q10-pad2_
-* c:\fossee\esim\library\subcircuitlibrary\lh0004\lh0004.cir
-.include NPN.lib
-.include PNP.lib
-q5 net-_q5-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222
-q8 net-_q10-pad2_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
-q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
-q4 net-_q4-pad1_ net-_q4-pad2_ net-_q1-pad3_ Q2N2907A
-r2 net-_q1-pad1_ net-_q10-pad1_ 300k
-r4 net-_q4-pad1_ net-_q10-pad1_ 300k
-r6 net-_q5-pad3_ net-_q10-pad1_ 50k
-q3 net-_q1-pad3_ net-_q2-pad1_ net-_q2-pad2_ Q2N2907A
-q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A
-r3 net-_q2-pad3_ net-_q2-pad2_ 40k
-r1 net-_q2-pad1_ net-_r1-pad2_ 600k
-q6 net-_q5-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2907A
-q7 net-_q10-pad2_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A
-r5 net-_q2-pad3_ net-_q6-pad3_ 50k
-r7 net-_q2-pad3_ net-_q7-pad3_ 50k
-q9 net-_q2-pad3_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
-q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A
-* Control Statements
-
+* Subcircuit LH0004
+.subckt LH0004 net-_q2-pad1_ net-_q2-pad2_ net-_q10-pad1_ net-_q4-pad2_ net-_q4-pad1_ net-_q1-pad1_ net-_r1-pad2_ net-_q10-pad3_ net-_q1-pad3_ net-_q10-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\lh0004\lh0004.cir
+.include PNP.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A
+q3 net-_q2-pad3_ net-_q1-pad1_ net-_q1-pad2_ Q2N2907A
+r3 net-_q1-pad3_ net-_q1-pad2_ 40k
+r1 net-_q1-pad1_ net-_r1-pad2_ 600k
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2907A
+q4 net-_q4-pad1_ net-_q4-pad2_ net-_q2-pad3_ Q2N2907A
+r2 net-_q2-pad1_ net-_q10-pad1_ 300k
+r4 net-_q4-pad1_ net-_q10-pad1_ 300k
+r5 net-_q1-pad3_ net-_q6-pad3_ 50k
+q6 net-_q5-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2907A
+q7 net-_q10-pad2_ net-_q5-pad1_ net-_q7-pad3_ Q2N2907A
+r7 net-_q1-pad3_ net-_q7-pad3_ 50k
+q5 net-_q5-pad1_ net-_q4-pad1_ net-_q5-pad3_ Q2N2222
+q8 net-_q10-pad2_ net-_q2-pad1_ net-_q5-pad3_ Q2N2222
+r6 net-_q5-pad3_ net-_q10-pad1_ 50k
+q9 net-_q1-pad3_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A
+* Control Statements
+
.ends LH0004
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LH0004/LH0004_Previous_Values.xml b/library/SubcircuitLibrary/LH0004/LH0004_Previous_Values.xml
index 7b722a485..47ac12a27 100644
--- a/library/SubcircuitLibrary/LH0004/LH0004_Previous_Values.xml
+++ b/library/SubcircuitLibrary/LH0004/LH0004_Previous_Values.xml
@@ -1 +1 @@
-C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
+C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
diff --git a/library/SubcircuitLibrary/LM3900/D.lib b/library/SubcircuitLibrary/LM3900/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/LM3900/LM3900-cache.lib b/library/SubcircuitLibrary/LM3900/LM3900-cache.lib
new file mode 100644
index 000000000..fea7ae574
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900-cache.lib
@@ -0,0 +1,147 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# dc
+#
+DEF dc I 0 40 Y Y 1 F N
+F0 "I" -200 100 60 H V C CNN
+F1 "dc" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+P 2 0 1 0 0 -100 0 -100 N
+P 2 0 1 0 0 100 -50 50 N
+P 2 0 1 0 0 100 0 -100 N
+P 2 0 1 0 0 100 50 50 N
+X ~ 1 0 450 300 D 50 50 1 1 P
+X ~ 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.cir b/library/SubcircuitLibrary/LM3900/LM3900.cir
new file mode 100644
index 000000000..2de03b570
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.cir
@@ -0,0 +1,20 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM3900\LM3900.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 15:20:35
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_D1-Pad1_ Net-_C1-Pad2_ eSim_NPN
+Q5 Net-_I1-Pad2_ Net-_I1-Pad1_ Net-_I2-Pad2_ eSim_NPN
+Q2 Net-_C1-Pad1_ Net-_Q1-Pad1_ Net-_C1-Pad2_ eSim_NPN
+Q4 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_I2-Pad2_ eSim_PNP
+Q3 Net-_I2-Pad2_ Net-_C1-Pad1_ Net-_I1-Pad1_ eSim_PNP
+D1 Net-_D1-Pad1_ Net-_C1-Pad2_ eSim_Diode
+I2 Net-_C1-Pad2_ Net-_I2-Pad2_ 1.3m
+I1 Net-_I1-Pad1_ Net-_I1-Pad2_ 200u
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10p
+U1 Net-_Q1-Pad1_ Net-_D1-Pad1_ Net-_I2-Pad2_ Net-_I1-Pad2_ Net-_C1-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.cir.out b/library/SubcircuitLibrary/LM3900/LM3900.cir.out
new file mode 100644
index 000000000..394ca23a3
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.cir.out
@@ -0,0 +1,24 @@
+* c:\fossee\esim\library\subcircuitlibrary\lm3900\lm3900.cir
+
+.include PNP.lib
+.include NPN.lib
+.include D.lib
+q1 net-_q1-pad1_ net-_d1-pad1_ net-_c1-pad2_ Q2N2222
+q5 net-_i1-pad2_ net-_i1-pad1_ net-_i2-pad2_ Q2N2222
+q2 net-_c1-pad1_ net-_q1-pad1_ net-_c1-pad2_ Q2N2222
+q4 net-_c1-pad2_ net-_c1-pad1_ net-_i2-pad2_ Q2N2907A
+q3 net-_i2-pad2_ net-_c1-pad1_ net-_i1-pad1_ Q2N2907A
+d1 net-_d1-pad1_ net-_c1-pad2_ 1N4148
+i2 net-_c1-pad2_ net-_i2-pad2_ 1.3m
+i1 net-_i1-pad1_ net-_i1-pad2_ 200u
+c1 net-_c1-pad1_ net-_c1-pad2_ 10p
+* u1 net-_q1-pad1_ net-_d1-pad1_ net-_i2-pad2_ net-_i1-pad2_ net-_c1-pad2_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.pro b/library/SubcircuitLibrary/LM3900/LM3900.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.proj b/library/SubcircuitLibrary/LM3900/LM3900.proj
new file mode 100644
index 000000000..21c9011d4
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.proj
@@ -0,0 +1 @@
+schematicFile LM3900.sch
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.sch b/library/SubcircuitLibrary/LM3900/LM3900.sch
new file mode 100644
index 000000000..a7a7d4cb6
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.sch
@@ -0,0 +1,276 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:LM3900-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q1
+U 1 1 6835ED47
+P 3300 4550
+F 0 "Q1" H 3200 4600 50 0000 R CNN
+F 1 "eSim_NPN" H 3250 4700 50 0000 R CNN
+F 2 "" H 3500 4650 29 0000 C CNN
+F 3 "" H 3300 4550 60 0000 C CNN
+ 1 3300 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 6835ED7F
+P 5100 2650
+F 0 "Q5" H 5000 2700 50 0000 R CNN
+F 1 "eSim_NPN" H 5050 2800 50 0000 R CNN
+F 2 "" H 5300 2750 29 0000 C CNN
+F 3 "" H 5100 2650 60 0000 C CNN
+ 1 5100 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 6835EDA3
+P 3750 4050
+F 0 "Q2" H 3650 4100 50 0000 R CNN
+F 1 "eSim_NPN" H 3700 4200 50 0000 R CNN
+F 2 "" H 3950 4150 29 0000 C CNN
+F 3 "" H 3750 4050 60 0000 C CNN
+ 1 3750 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q4
+U 1 1 6835EDDD
+P 4200 3650
+F 0 "Q4" H 4100 3700 50 0000 R CNN
+F 1 "eSim_PNP" H 4150 3800 50 0000 R CNN
+F 2 "" H 4400 3750 29 0000 C CNN
+F 3 "" H 4200 3650 60 0000 C CNN
+ 1 4200 3650
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q3
+U 1 1 6835EE0A
+P 4200 3000
+F 0 "Q3" H 4100 3050 50 0000 R CNN
+F 1 "eSim_PNP" H 4150 3150 50 0000 R CNN
+F 2 "" H 4400 3100 29 0000 C CNN
+F 3 "" H 4200 3000 60 0000 C CNN
+ 1 4200 3000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_Diode D1
+U 1 1 6835EE44
+P 2900 4700
+F 0 "D1" H 2900 4800 50 0000 C CNN
+F 1 "eSim_Diode" H 2900 4600 50 0000 C CNN
+F 2 "" H 2900 4700 60 0000 C CNN
+F 3 "" H 2900 4700 60 0000 C CNN
+ 1 2900 4700
+ 0 1 1 0
+$EndComp
+$Comp
+L dc I2
+U 1 1 6835EE74
+P 5200 3900
+F 0 "I2" H 5000 4000 60 0000 C CNN
+F 1 "1.3m" H 5000 3850 60 0000 C CNN
+F 2 "R1" H 4900 3900 60 0000 C CNN
+F 3 "" H 5200 3900 60 0000 C CNN
+ 1 5200 3900
+ 1 0 0 1
+$EndComp
+$Comp
+L dc I1
+U 1 1 6835EEBA
+P 4300 2200
+F 0 "I1" H 4100 2300 60 0000 C CNN
+F 1 "200u" H 4100 2150 60 0000 C CNN
+F 2 "R1" H 4000 2200 60 0000 C CNN
+F 3 "" H 4300 2200 60 0000 C CNN
+ 1 4300 2200
+ 1 0 0 1
+$EndComp
+$Comp
+L capacitor C1
+U 1 1 6835F4C8
+P 4050 4300
+F 0 "C1" H 4075 4400 50 0000 L CNN
+F 1 "10p" H 4075 4200 50 0000 L CNN
+F 2 "" H 4088 4150 30 0000 C CNN
+F 3 "" H 4050 4300 60 0000 C CNN
+ 1 4050 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3400 4350 3400 4050
+Wire Wire Line
+ 2700 4050 3550 4050
+Wire Wire Line
+ 3850 3850 3850 3650
+Wire Wire Line
+ 3850 3650 4000 3650
+Wire Wire Line
+ 4300 3200 4300 3450
+Wire Wire Line
+ 4000 3650 4000 3000
+Wire Wire Line
+ 4300 2650 4300 2800
+Wire Wire Line
+ 4900 2650 4300 2650
+Wire Wire Line
+ 4300 1750 5350 1750
+Wire Wire Line
+ 5200 1750 5200 2450
+Connection ~ 5200 1750
+Wire Wire Line
+ 5200 2850 5200 3450
+Wire Wire Line
+ 2550 4550 3100 4550
+Wire Wire Line
+ 2900 4850 5200 4850
+Wire Wire Line
+ 3400 4850 3400 4750
+Wire Wire Line
+ 3850 4850 3850 4250
+Connection ~ 3400 4850
+Wire Wire Line
+ 4300 4850 4300 3850
+Connection ~ 3850 4850
+Wire Wire Line
+ 5200 4850 5200 4350
+Connection ~ 4300 4850
+Wire Wire Line
+ 4300 3300 5200 3300
+Connection ~ 5200 3300
+Connection ~ 4300 3300
+Wire Wire Line
+ 4050 4150 4050 3650
+Wire Wire Line
+ 4050 3650 3950 3650
+Connection ~ 3950 3650
+Wire Wire Line
+ 4050 4450 4050 4850
+Connection ~ 4050 4850
+Wire Wire Line
+ 2900 4950 2900 4850
+$Comp
+L PORT U1
+U 1 1 6835FDE8
+P 2450 4050
+F 0 "U1" H 2500 4150 30 0000 C CNN
+F 1 "PORT" H 2450 4050 30 0000 C CNN
+F 2 "" H 2450 4050 60 0000 C CNN
+F 3 "" H 2450 4050 60 0000 C CNN
+ 1 2450 4050
+ 1 0 0 -1
+$EndComp
+Connection ~ 2900 4550
+$Comp
+L PORT U1
+U 3 1 6835FE7F
+P 5750 3400
+F 0 "U1" H 5800 3500 30 0000 C CNN
+F 1 "PORT" H 5750 3400 30 0000 C CNN
+F 2 "" H 5750 3400 60 0000 C CNN
+F 3 "" H 5750 3400 60 0000 C CNN
+ 3 5750 3400
+ -1 0 0 -1
+$EndComp
+Connection ~ 3400 4050
+$Comp
+L PORT U1
+U 5 1 6835FEF1
+P 2400 4950
+F 0 "U1" H 2450 5050 30 0000 C CNN
+F 1 "PORT" H 2400 4950 30 0000 C CNN
+F 2 "" H 2400 4950 60 0000 C CNN
+F 3 "" H 2400 4950 60 0000 C CNN
+ 5 2400 4950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5200 3400 5500 3400
+Connection ~ 5200 3400
+$Comp
+L PORT U1
+U 4 1 6835FFC6
+P 5650 1950
+F 0 "U1" H 5700 2050 30 0000 C CNN
+F 1 "PORT" H 5650 1950 30 0000 C CNN
+F 2 "" H 5650 1950 60 0000 C CNN
+F 3 "" H 5650 1950 60 0000 C CNN
+ 4 5650 1950
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5350 1750 5350 1950
+Wire Wire Line
+ 5350 1950 5400 1950
+$Comp
+L PORT U1
+U 2 1 68360C1F
+P 2300 4550
+F 0 "U1" H 2350 4650 30 0000 C CNN
+F 1 "PORT" H 2300 4550 30 0000 C CNN
+F 2 "" H 2300 4550 60 0000 C CNN
+F 3 "" H 2300 4550 60 0000 C CNN
+ 2 2300 4550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2650 4950 2900 4950
+Text Label 5300 3350 0 60 ~ 0
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/LM3900/LM3900.sub b/library/SubcircuitLibrary/LM3900/LM3900.sub
new file mode 100644
index 000000000..d5849dff4
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900.sub
@@ -0,0 +1,18 @@
+* Subcircuit LM3900
+.subckt LM3900 net-_q1-pad1_ net-_d1-pad1_ net-_i2-pad2_ net-_i1-pad2_ net-_c1-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\lm3900\lm3900.cir
+.include PNP.lib
+.include NPN.lib
+.include D.lib
+q1 net-_q1-pad1_ net-_d1-pad1_ net-_c1-pad2_ Q2N2222
+q5 net-_i1-pad2_ net-_i1-pad1_ net-_i2-pad2_ Q2N2222
+q2 net-_c1-pad1_ net-_q1-pad1_ net-_c1-pad2_ Q2N2222
+q4 net-_c1-pad2_ net-_c1-pad1_ net-_i2-pad2_ Q2N2907A
+q3 net-_i2-pad2_ net-_c1-pad1_ net-_i1-pad1_ Q2N2907A
+d1 net-_d1-pad1_ net-_c1-pad2_ 1N4148
+i2 net-_c1-pad2_ net-_i2-pad2_ 1.3m
+i1 net-_i1-pad1_ net-_i1-pad2_ 200u
+c1 net-_c1-pad1_ net-_c1-pad2_ 10p
+* Control Statements
+
+.ends LM3900
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_Previous_Values.xml b/library/SubcircuitLibrary/LM3900/LM3900_Previous_Values.xml
new file mode 100644
index 000000000..d9c6cbb51
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_Previous_Values.xml
@@ -0,0 +1 @@
+1.3m200uC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test-cache.lib b/library/SubcircuitLibrary/LM3900/LM3900_test-cache.lib
new file mode 100644
index 000000000..6c5a94aea
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test-cache.lib
@@ -0,0 +1,121 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# LM3900
+#
+DEF LM3900 X 0 40 Y Y 1 F N
+F0 "X" 0 -400 60 H V C CNN
+F1 "LM3900" 0 500 60 H V C CNN
+F2 "" 0 500 60 H I C CNN
+F3 "" 0 500 60 H I C CNN
+DRAW
+P 4 0 1 0 200 0 -150 300 -150 -300 200 0 N
+X inv 1 -350 150 200 R 50 50 1 1 I
+X non_inv 2 -350 -100 200 R 50 50 1 1 I
+X Out 3 400 0 200 L 50 50 1 1 O
+X Vcc 4 50 300 200 D 50 50 1 1 I
+X Gnd 5 50 -300 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.cir b/library/SubcircuitLibrary/LM3900/LM3900_test.cir
new file mode 100644
index 000000000..90ef51162
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.cir
@@ -0,0 +1,21 @@
+* C:\Users\pavithra\eSim-Workspace\LM3900_test\LM3900_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/29/25 15:21:32
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_C1-Pad1_ Net-_R1-Pad2_ 10k
+R2 Net-_R2-Pad1_ Net-_R2-Pad2_ 39k
+R3 Net-_R1-Pad2_ Net-_C2-Pad2_ 100k
+R4 out GND 10k
+C1 Net-_C1-Pad1_ in 1u
+C2 out Net-_C2-Pad2_ 1u
+v1 in GND sine
+v2 Net-_R2-Pad1_ GND DC
+U2 out plot_v1
+U1 in plot_v1
+X1 Net-_R1-Pad2_ Net-_R2-Pad2_ Net-_C2-Pad2_ Net-_R2-Pad1_ GND LM3900
+
+.end
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.cir.out b/library/SubcircuitLibrary/LM3900/LM3900_test.cir.out
new file mode 100644
index 000000000..efd5ef2c0
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.cir.out
@@ -0,0 +1,24 @@
+* c:\users\pavithra\esim-workspace\lm3900_test\lm3900_test.cir
+
+.include LM3900.sub
+r1 net-_c1-pad1_ net-_r1-pad2_ 10k
+r2 net-_r2-pad1_ net-_r2-pad2_ 39k
+r3 net-_r1-pad2_ net-_c2-pad2_ 100k
+r4 out gnd 10k
+c1 net-_c1-pad1_ in 1u
+c2 out net-_c2-pad2_ 1u
+v1 in gnd sine(0 10m 1k 0 0)
+v2 net-_r2-pad1_ gnd dc 5
+* u2 out plot_v1
+* u1 in plot_v1
+x1 net-_r1-pad2_ net-_r2-pad2_ net-_c2-pad2_ net-_r2-pad1_ gnd LM3900
+.tran 10e-06 10e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out) v(in)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.pro b/library/SubcircuitLibrary/LM3900/LM3900_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.proj b/library/SubcircuitLibrary/LM3900/LM3900_test.proj
new file mode 100644
index 000000000..a2215586a
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.proj
@@ -0,0 +1 @@
+schematicFile LM3900_test.sch
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test.sch b/library/SubcircuitLibrary/LM3900/LM3900_test.sch
new file mode 100644
index 000000000..9cec7f25d
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test.sch
@@ -0,0 +1,277 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 68382208
+P 4700 3450
+F 0 "R1" H 4750 3580 50 0000 C CNN
+F 1 "10k" H 4750 3400 50 0000 C CNN
+F 2 "" H 4750 3430 30 0000 C CNN
+F 3 "" V 4750 3500 30 0000 C CNN
+ 1 4700 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 6838222B
+P 4750 3700
+F 0 "R2" H 4800 3830 50 0000 C CNN
+F 1 "39k" H 4800 3650 50 0000 C CNN
+F 2 "" H 4800 3680 30 0000 C CNN
+F 3 "" V 4800 3750 30 0000 C CNN
+ 1 4750 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 6838224D
+P 5550 2850
+F 0 "R3" H 5600 2980 50 0000 C CNN
+F 1 "100k" H 5600 2800 50 0000 C CNN
+F 2 "" H 5600 2830 30 0000 C CNN
+F 3 "" V 5600 2900 30 0000 C CNN
+ 1 5550 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R4
+U 1 1 68382273
+P 6500 3900
+F 0 "R4" H 6550 4030 50 0000 C CNN
+F 1 "10k" H 6550 3850 50 0000 C CNN
+F 2 "" H 6550 3880 30 0000 C CNN
+F 3 "" V 6550 3950 30 0000 C CNN
+ 1 6500 3900
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor C1
+U 1 1 6838229D
+P 4150 3400
+F 0 "C1" H 4175 3500 50 0000 L CNN
+F 1 "1u" H 4175 3300 50 0000 L CNN
+F 2 "" H 4188 3250 30 0000 C CNN
+F 3 "" H 4150 3400 60 0000 C CNN
+ 1 4150 3400
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor C2
+U 1 1 683822C6
+P 6150 3550
+F 0 "C2" H 6175 3650 50 0000 L CNN
+F 1 "1u" H 6175 3450 50 0000 L CNN
+F 2 "" H 6188 3400 30 0000 C CNN
+F 3 "" H 6150 3550 60 0000 C CNN
+ 1 6150 3550
+ 0 1 1 0
+$EndComp
+$Comp
+L sine v1
+U 1 1 683822F8
+P 3700 3850
+F 0 "v1" H 3500 3950 60 0000 C CNN
+F 1 "sine" H 3500 3800 60 0000 C CNN
+F 2 "R1" H 3400 3850 60 0000 C CNN
+F 3 "" H 3700 3850 60 0000 C CNN
+ 1 3700 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v2
+U 1 1 6838232F
+P 4400 4250
+F 0 "v2" H 4200 4350 60 0000 C CNN
+F 1 "DC" H 4200 4200 60 0000 C CNN
+F 2 "R1" H 4100 4250 60 0000 C CNN
+F 3 "" H 4400 4250 60 0000 C CNN
+ 1 4400 4250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4650 3650 4400 3650
+Wire Wire Line
+ 4400 3100 4400 3800
+Wire Wire Line
+ 4950 3650 5100 3650
+Wire Wire Line
+ 4900 3400 5100 3400
+Wire Wire Line
+ 4300 3400 4600 3400
+Wire Wire Line
+ 3700 3400 4000 3400
+Wire Wire Line
+ 4400 3100 5500 3100
+Wire Wire Line
+ 5500 3100 5500 3250
+Connection ~ 4400 3650
+Wire Wire Line
+ 5850 3550 6000 3550
+Wire Wire Line
+ 6300 3550 6550 3550
+Wire Wire Line
+ 6550 3550 6550 3800
+$Comp
+L eSim_GND #PWR01
+U 1 1 6838259D
+P 6550 4300
+F 0 "#PWR01" H 6550 4050 50 0001 C CNN
+F 1 "eSim_GND" H 6550 4150 50 0000 C CNN
+F 2 "" H 6550 4300 50 0001 C CNN
+F 3 "" H 6550 4300 50 0001 C CNN
+ 1 6550 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 683825CA
+P 3700 4500
+F 0 "#PWR02" H 3700 4250 50 0001 C CNN
+F 1 "eSim_GND" H 3700 4350 50 0000 C CNN
+F 2 "" H 3700 4500 50 0001 C CNN
+F 3 "" H 3700 4500 50 0001 C CNN
+ 1 3700 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 68382602
+P 5500 4000
+F 0 "#PWR03" H 5500 3750 50 0001 C CNN
+F 1 "eSim_GND" H 5500 3850 50 0000 C CNN
+F 2 "" H 5500 4000 50 0001 C CNN
+F 3 "" H 5500 4000 50 0001 C CNN
+ 1 5500 4000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5500 4000 5500 3850
+Wire Wire Line
+ 3700 4300 3700 4500
+Wire Wire Line
+ 6550 4100 6550 4300
+$Comp
+L eSim_GND #PWR04
+U 1 1 683827B5
+P 4400 4900
+F 0 "#PWR04" H 4400 4650 50 0001 C CNN
+F 1 "eSim_GND" H 4400 4750 50 0000 C CNN
+F 2 "" H 4400 4900 50 0001 C CNN
+F 3 "" H 4400 4900 50 0001 C CNN
+ 1 4400 4900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 4700 4400 4900
+Wire Wire Line
+ 5050 3400 5050 2800
+Wire Wire Line
+ 5050 2800 5450 2800
+Connection ~ 5050 3400
+Wire Wire Line
+ 5750 2800 5950 2800
+Wire Wire Line
+ 5950 2800 5950 3550
+Connection ~ 5950 3550
+$Comp
+L plot_v1 U2
+U 1 1 68382854
+P 6550 3500
+F 0 "U2" H 6550 4000 60 0000 C CNN
+F 1 "plot_v1" H 6750 3850 60 0000 C CNN
+F 2 "" H 6550 3500 60 0000 C CNN
+F 3 "" H 6550 3500 60 0000 C CNN
+ 1 6550 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 683828BD
+P 3700 3500
+F 0 "U1" H 3700 4000 60 0000 C CNN
+F 1 "plot_v1" H 3900 3850 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3700 3300 3700 3400
+Wire Wire Line
+ 6550 3300 6550 3600
+Connection ~ 6550 3600
+Text GLabel 6450 3400 0 60 Input ~ 0
+out
+Wire Wire Line
+ 6450 3400 6550 3400
+Connection ~ 6550 3400
+Text GLabel 3550 3350 0 60 Input ~ 0
+in
+Wire Wire Line
+ 3550 3350 3700 3350
+Connection ~ 3700 3350
+$Comp
+L LM3900 X1
+U 1 1 68382FF8
+P 5450 3550
+F 0 "X1" H 5450 3150 60 0000 C CNN
+F 1 "LM3900" H 5450 4050 60 0000 C CNN
+F 2 "" H 5450 4050 60 0001 C CNN
+F 3 "" H 5450 4050 60 0001 C CNN
+ 1 5450 3550
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/LM3900/LM3900_test_Previous_Values.xml b/library/SubcircuitLibrary/LM3900/LM3900_test_Previous_Values.xml
new file mode 100644
index 000000000..d6bd25985
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/LM3900_test_Previous_Values.xml
@@ -0,0 +1 @@
+sine010m1kdc5C:\FOSSEE\eSim\library\SubcircuitLibrary\LM3900falsetruefalse1010010KHzKHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01010msusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/LM3900/NPN.lib b/library/SubcircuitLibrary/LM3900/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/LM3900/PNP.lib b/library/SubcircuitLibrary/LM3900/PNP.lib
new file mode 100644
index 000000000..7edda0eab
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/LM3900/analysis b/library/SubcircuitLibrary/LM3900/analysis
new file mode 100644
index 000000000..6783e70d4
--- /dev/null
+++ b/library/SubcircuitLibrary/LM3900/analysis
@@ -0,0 +1 @@
+.tran 10e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160-cache.lib b/library/SubcircuitLibrary/MC10H160/MC10H160-cache.lib
new file mode 100644
index 000000000..15b9880ea
--- /dev/null
+++ b/library/SubcircuitLibrary/MC10H160/MC10H160-cache.lib
@@ -0,0 +1,64 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.cir b/library/SubcircuitLibrary/MC10H160/MC10H160.cir
new file mode 100644
index 000000000..d9a2b7543
--- /dev/null
+++ b/library/SubcircuitLibrary/MC10H160/MC10H160.cir
@@ -0,0 +1,22 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC10H160\MC10H160.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/09/25 12:10:19
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_xor
+U2 Net-_U10-Pad5_ Net-_U10-Pad6_ Net-_U11-Pad2_ d_xor
+U3 Net-_U10-Pad7_ Net-_U10-Pad9_ Net-_U3-Pad3_ d_xor
+U4 Net-_U10-Pad10_ Net-_U10-Pad11_ Net-_U4-Pad3_ d_xor
+U5 Net-_U10-Pad12_ Net-_U10-Pad13_ Net-_U5-Pad3_ d_xor
+U6 Net-_U10-Pad14_ Net-_U10-Pad15_ Net-_U12-Pad2_ d_xor
+U7 Net-_U11-Pad3_ Net-_U3-Pad3_ Net-_U7-Pad3_ d_xor
+U8 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U12-Pad1_ d_xor
+U9 Net-_U7-Pad3_ Net-_U12-Pad3_ Net-_U10-Pad2_ d_xor
+U10 ? Net-_U10-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad5_ Net-_U10-Pad6_ Net-_U10-Pad7_ ? Net-_U10-Pad9_ Net-_U10-Pad10_ Net-_U10-Pad11_ Net-_U10-Pad12_ Net-_U10-Pad13_ Net-_U10-Pad14_ Net-_U10-Pad15_ ? PORT
+U11 Net-_U1-Pad3_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_xor
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_xor
+
+.end
diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.cir.out b/library/SubcircuitLibrary/MC10H160/MC10H160.cir.out
new file mode 100644
index 000000000..942c19916
--- /dev/null
+++ b/library/SubcircuitLibrary/MC10H160/MC10H160.cir.out
@@ -0,0 +1,56 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc10h160\mc10h160.cir
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
+* u2 net-_u10-pad5_ net-_u10-pad6_ net-_u11-pad2_ d_xor
+* u3 net-_u10-pad7_ net-_u10-pad9_ net-_u3-pad3_ d_xor
+* u4 net-_u10-pad10_ net-_u10-pad11_ net-_u4-pad3_ d_xor
+* u5 net-_u10-pad12_ net-_u10-pad13_ net-_u5-pad3_ d_xor
+* u6 net-_u10-pad14_ net-_u10-pad15_ net-_u12-pad2_ d_xor
+* u7 net-_u11-pad3_ net-_u3-pad3_ net-_u7-pad3_ d_xor
+* u8 net-_u4-pad3_ net-_u5-pad3_ net-_u12-pad1_ d_xor
+* u9 net-_u7-pad3_ net-_u12-pad3_ net-_u10-pad2_ d_xor
+* u10 ? net-_u10-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ ? net-_u10-pad9_ net-_u10-pad10_ net-_u10-pad11_ net-_u10-pad12_ net-_u10-pad13_ net-_u10-pad14_ net-_u10-pad15_ ? port
+* u11 net-_u1-pad3_ net-_u11-pad2_ net-_u11-pad3_ d_xor
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_xor
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u10-pad5_ net-_u10-pad6_ ] net-_u11-pad2_ u2
+a3 [net-_u10-pad7_ net-_u10-pad9_ ] net-_u3-pad3_ u3
+a4 [net-_u10-pad10_ net-_u10-pad11_ ] net-_u4-pad3_ u4
+a5 [net-_u10-pad12_ net-_u10-pad13_ ] net-_u5-pad3_ u5
+a6 [net-_u10-pad14_ net-_u10-pad15_ ] net-_u12-pad2_ u6
+a7 [net-_u11-pad3_ net-_u3-pad3_ ] net-_u7-pad3_ u7
+a8 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u12-pad1_ u8
+a9 [net-_u7-pad3_ net-_u12-pad3_ ] net-_u10-pad2_ u9
+a10 [net-_u1-pad3_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a11 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u1 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.pro b/library/SubcircuitLibrary/MC10H160/MC10H160.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC10H160/MC10H160.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.sch b/library/SubcircuitLibrary/MC10H160/MC10H160.sch
new file mode 100644
index 000000000..c84b91d23
--- /dev/null
+++ b/library/SubcircuitLibrary/MC10H160/MC10H160.sch
@@ -0,0 +1,435 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC10H160-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U1
+U 1 1 68467D6D
+P 3550 1500
+F 0 "U1" H 3550 1500 60 0000 C CNN
+F 1 "d_xor" H 3600 1600 47 0000 C CNN
+F 2 "" H 3550 1500 60 0000 C CNN
+F 3 "" H 3550 1500 60 0000 C CNN
+ 1 3550 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U2
+U 1 1 68467DC9
+P 3550 1950
+F 0 "U2" H 3550 1950 60 0000 C CNN
+F 1 "d_xor" H 3600 2050 47 0000 C CNN
+F 2 "" H 3550 1950 60 0000 C CNN
+F 3 "" H 3550 1950 60 0000 C CNN
+ 1 3550 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U3
+U 1 1 68467DED
+P 3550 2400
+F 0 "U3" H 3550 2400 60 0000 C CNN
+F 1 "d_xor" H 3600 2500 47 0000 C CNN
+F 2 "" H 3550 2400 60 0000 C CNN
+F 3 "" H 3550 2400 60 0000 C CNN
+ 1 3550 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U4
+U 1 1 68467E22
+P 3550 3000
+F 0 "U4" H 3550 3000 60 0000 C CNN
+F 1 "d_xor" H 3600 3100 47 0000 C CNN
+F 2 "" H 3550 3000 60 0000 C CNN
+F 3 "" H 3550 3000 60 0000 C CNN
+ 1 3550 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U5
+U 1 1 68467E62
+P 3550 3400
+F 0 "U5" H 3550 3400 60 0000 C CNN
+F 1 "d_xor" H 3600 3500 47 0000 C CNN
+F 2 "" H 3550 3400 60 0000 C CNN
+F 3 "" H 3550 3400 60 0000 C CNN
+ 1 3550 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U6
+U 1 1 68467E95
+P 3550 3800
+F 0 "U6" H 3550 3800 60 0000 C CNN
+F 1 "d_xor" H 3600 3900 47 0000 C CNN
+F 2 "" H 3550 3800 60 0000 C CNN
+F 3 "" H 3550 3800 60 0000 C CNN
+ 1 3550 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U7
+U 1 1 68467ED1
+P 5650 1900
+F 0 "U7" H 5650 1900 60 0000 C CNN
+F 1 "d_xor" H 5700 2000 47 0000 C CNN
+F 2 "" H 5650 1900 60 0000 C CNN
+F 3 "" H 5650 1900 60 0000 C CNN
+ 1 5650 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U8
+U 1 1 68467F48
+P 4650 3150
+F 0 "U8" H 4650 3150 60 0000 C CNN
+F 1 "d_xor" H 4700 3250 47 0000 C CNN
+F 2 "" H 4650 3150 60 0000 C CNN
+F 3 "" H 4650 3150 60 0000 C CNN
+ 1 4650 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U9
+U 1 1 68467FA4
+P 6750 2450
+F 0 "U9" H 6750 2450 60 0000 C CNN
+F 1 "d_xor" H 6800 2550 47 0000 C CNN
+F 2 "" H 6750 2450 60 0000 C CNN
+F 3 "" H 6750 2450 60 0000 C CNN
+ 1 6750 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 3 1 68468010
+P 2650 1400
+F 0 "U10" H 2700 1500 30 0000 C CNN
+F 1 "PORT" H 2650 1400 30 0000 C CNN
+F 2 "" H 2650 1400 60 0000 C CNN
+F 3 "" H 2650 1400 60 0000 C CNN
+ 3 2650 1400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 4 1 68468099
+P 2650 1550
+F 0 "U10" H 2700 1650 30 0000 C CNN
+F 1 "PORT" H 2650 1550 30 0000 C CNN
+F 2 "" H 2650 1550 60 0000 C CNN
+F 3 "" H 2650 1550 60 0000 C CNN
+ 4 2650 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 5 1 684680C4
+P 2650 1800
+F 0 "U10" H 2700 1900 30 0000 C CNN
+F 1 "PORT" H 2650 1800 30 0000 C CNN
+F 2 "" H 2650 1800 60 0000 C CNN
+F 3 "" H 2650 1800 60 0000 C CNN
+ 5 2650 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 6 1 684680F1
+P 2650 1950
+F 0 "U10" H 2700 2050 30 0000 C CNN
+F 1 "PORT" H 2650 1950 30 0000 C CNN
+F 2 "" H 2650 1950 60 0000 C CNN
+F 3 "" H 2650 1950 60 0000 C CNN
+ 6 2650 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 14 1 68468120
+P 2650 3650
+F 0 "U10" H 2700 3750 30 0000 C CNN
+F 1 "PORT" H 2650 3650 30 0000 C CNN
+F 2 "" H 2650 3650 60 0000 C CNN
+F 3 "" H 2650 3650 60 0000 C CNN
+ 14 2650 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 15 1 68468151
+P 2650 3800
+F 0 "U10" H 2700 3900 30 0000 C CNN
+F 1 "PORT" H 2650 3800 30 0000 C CNN
+F 2 "" H 2650 3800 60 0000 C CNN
+F 3 "" H 2650 3800 60 0000 C CNN
+ 15 2650 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 16 1 68468184
+P 6750 1250
+F 0 "U10" H 6800 1350 30 0000 C CNN
+F 1 "PORT" H 6750 1250 30 0000 C CNN
+F 2 "" H 6750 1250 60 0000 C CNN
+F 3 "" H 6750 1250 60 0000 C CNN
+ 16 6750 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 7 1 684681B9
+P 2650 2250
+F 0 "U10" H 2700 2350 30 0000 C CNN
+F 1 "PORT" H 2650 2250 30 0000 C CNN
+F 2 "" H 2650 2250 60 0000 C CNN
+F 3 "" H 2650 2250 60 0000 C CNN
+ 7 2650 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 8 1 684681F6
+P 6750 1450
+F 0 "U10" H 6800 1550 30 0000 C CNN
+F 1 "PORT" H 6750 1450 30 0000 C CNN
+F 2 "" H 6750 1450 60 0000 C CNN
+F 3 "" H 6750 1450 60 0000 C CNN
+ 8 6750 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 1 1 6846822F
+P 6750 1650
+F 0 "U10" H 6800 1750 30 0000 C CNN
+F 1 "PORT" H 6750 1650 30 0000 C CNN
+F 2 "" H 6750 1650 60 0000 C CNN
+F 3 "" H 6750 1650 60 0000 C CNN
+ 1 6750 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 9 1 68468272
+P 2650 2400
+F 0 "U10" H 2700 2500 30 0000 C CNN
+F 1 "PORT" H 2650 2400 30 0000 C CNN
+F 2 "" H 2650 2400 60 0000 C CNN
+F 3 "" H 2650 2400 60 0000 C CNN
+ 9 2650 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 2 1 684682AF
+P 7550 2400
+F 0 "U10" H 7600 2500 30 0000 C CNN
+F 1 "PORT" H 7550 2400 30 0000 C CNN
+F 2 "" H 7550 2400 60 0000 C CNN
+F 3 "" H 7550 2400 60 0000 C CNN
+ 2 7550 2400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U10
+U 10 1 684682F6
+P 2650 2900
+F 0 "U10" H 2700 3000 30 0000 C CNN
+F 1 "PORT" H 2650 2900 30 0000 C CNN
+F 2 "" H 2650 2900 60 0000 C CNN
+F 3 "" H 2650 2900 60 0000 C CNN
+ 10 2650 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 11 1 68468339
+P 2650 3050
+F 0 "U10" H 2700 3150 30 0000 C CNN
+F 1 "PORT" H 2650 3050 30 0000 C CNN
+F 2 "" H 2650 3050 60 0000 C CNN
+F 3 "" H 2650 3050 60 0000 C CNN
+ 11 2650 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 12 1 6846837C
+P 2650 3250
+F 0 "U10" H 2700 3350 30 0000 C CNN
+F 1 "PORT" H 2650 3250 30 0000 C CNN
+F 2 "" H 2650 3250 60 0000 C CNN
+F 3 "" H 2650 3250 60 0000 C CNN
+ 12 2650 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U10
+U 13 1 684683C1
+P 2650 3400
+F 0 "U10" H 2700 3500 30 0000 C CNN
+F 1 "PORT" H 2650 3400 30 0000 C CNN
+F 2 "" H 2650 3400 60 0000 C CNN
+F 3 "" H 2650 3400 60 0000 C CNN
+ 13 2650 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U11
+U 1 1 68468695
+P 4650 1700
+F 0 "U11" H 4650 1700 60 0000 C CNN
+F 1 "d_xor" H 4700 1800 47 0000 C CNN
+F 2 "" H 4650 1700 60 0000 C CNN
+F 3 "" H 4650 1700 60 0000 C CNN
+ 1 4650 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U12
+U 1 1 6846874F
+P 5650 3400
+F 0 "U12" H 5650 3400 60 0000 C CNN
+F 1 "d_xor" H 5700 3500 47 0000 C CNN
+F 2 "" H 5650 3400 60 0000 C CNN
+F 3 "" H 5650 3400 60 0000 C CNN
+ 1 5650 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2900 1400 3100 1400
+Wire Wire Line
+ 2900 1550 3100 1550
+Wire Wire Line
+ 3100 1550 3100 1500
+Wire Wire Line
+ 2900 1800 3100 1800
+Wire Wire Line
+ 3100 1800 3100 1850
+Wire Wire Line
+ 2900 1950 3100 1950
+Wire Wire Line
+ 2900 2250 3100 2250
+Wire Wire Line
+ 3100 2250 3100 2300
+Wire Wire Line
+ 2900 2400 3100 2400
+Wire Wire Line
+ 2900 2900 3100 2900
+Wire Wire Line
+ 2900 3050 3100 3050
+Wire Wire Line
+ 3100 3050 3100 3000
+Wire Wire Line
+ 2900 3250 3100 3250
+Wire Wire Line
+ 3100 3250 3100 3300
+Wire Wire Line
+ 2900 3400 3100 3400
+Wire Wire Line
+ 2900 3650 3100 3650
+Wire Wire Line
+ 3100 3650 3100 3700
+Wire Wire Line
+ 2900 3800 3100 3800
+Wire Wire Line
+ 4000 1450 4200 1450
+Wire Wire Line
+ 4200 1450 4200 1600
+Wire Wire Line
+ 4000 1900 4200 1900
+Wire Wire Line
+ 4200 1900 4200 1700
+Wire Wire Line
+ 4000 2350 5200 2350
+Wire Wire Line
+ 5200 2350 5200 1900
+Wire Wire Line
+ 5100 1650 5200 1650
+Wire Wire Line
+ 5200 1650 5200 1800
+Wire Wire Line
+ 6100 1850 6300 1850
+Wire Wire Line
+ 6300 1850 6300 2350
+Wire Wire Line
+ 4000 2950 4200 2950
+Wire Wire Line
+ 4200 2950 4200 3050
+Wire Wire Line
+ 4000 3350 4200 3350
+Wire Wire Line
+ 4200 3350 4200 3150
+Wire Wire Line
+ 4000 3750 5200 3750
+Wire Wire Line
+ 5200 3750 5200 3400
+Wire Wire Line
+ 5100 3100 5200 3100
+Wire Wire Line
+ 5200 3100 5200 3300
+Wire Wire Line
+ 6100 3350 6300 3350
+Wire Wire Line
+ 6300 3350 6300 2450
+Wire Wire Line
+ 7200 2400 7300 2400
+NoConn ~ 7000 1250
+NoConn ~ 7000 1450
+NoConn ~ 7000 1650
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160.sub b/library/SubcircuitLibrary/MC10H160/MC10H160.sub
new file mode 100644
index 000000000..03e8d26f3
--- /dev/null
+++ b/library/SubcircuitLibrary/MC10H160/MC10H160.sub
@@ -0,0 +1,50 @@
+* Subcircuit MC10H160
+.subckt MC10H160 ? net-_u10-pad2_ net-_u1-pad1_ net-_u1-pad2_ net-_u10-pad5_ net-_u10-pad6_ net-_u10-pad7_ ? net-_u10-pad9_ net-_u10-pad10_ net-_u10-pad11_ net-_u10-pad12_ net-_u10-pad13_ net-_u10-pad14_ net-_u10-pad15_ ?
+* c:\fossee\esim\library\subcircuitlibrary\mc10h160\mc10h160.cir
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_xor
+* u2 net-_u10-pad5_ net-_u10-pad6_ net-_u11-pad2_ d_xor
+* u3 net-_u10-pad7_ net-_u10-pad9_ net-_u3-pad3_ d_xor
+* u4 net-_u10-pad10_ net-_u10-pad11_ net-_u4-pad3_ d_xor
+* u5 net-_u10-pad12_ net-_u10-pad13_ net-_u5-pad3_ d_xor
+* u6 net-_u10-pad14_ net-_u10-pad15_ net-_u12-pad2_ d_xor
+* u7 net-_u11-pad3_ net-_u3-pad3_ net-_u7-pad3_ d_xor
+* u8 net-_u4-pad3_ net-_u5-pad3_ net-_u12-pad1_ d_xor
+* u9 net-_u7-pad3_ net-_u12-pad3_ net-_u10-pad2_ d_xor
+* u11 net-_u1-pad3_ net-_u11-pad2_ net-_u11-pad3_ d_xor
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_xor
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u10-pad5_ net-_u10-pad6_ ] net-_u11-pad2_ u2
+a3 [net-_u10-pad7_ net-_u10-pad9_ ] net-_u3-pad3_ u3
+a4 [net-_u10-pad10_ net-_u10-pad11_ ] net-_u4-pad3_ u4
+a5 [net-_u10-pad12_ net-_u10-pad13_ ] net-_u5-pad3_ u5
+a6 [net-_u10-pad14_ net-_u10-pad15_ ] net-_u12-pad2_ u6
+a7 [net-_u11-pad3_ net-_u3-pad3_ ] net-_u7-pad3_ u7
+a8 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u12-pad1_ u8
+a9 [net-_u7-pad3_ net-_u12-pad3_ ] net-_u10-pad2_ u9
+a10 [net-_u1-pad3_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a11 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u1 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u3 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u4 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u5 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u6 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u7 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u9 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends MC10H160
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC10H160/MC10H160_Previous_Values.xml b/library/SubcircuitLibrary/MC10H160/MC10H160_Previous_Values.xml
new file mode 100644
index 000000000..cb15384cb
--- /dev/null
+++ b/library/SubcircuitLibrary/MC10H160/MC10H160_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_xord_xord_xord_xord_xord_xord_xord_xord_xord_xord_xor
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC10H160/analysis b/library/SubcircuitLibrary/MC10H160/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/MC10H160/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B-cache.lib b/library/SubcircuitLibrary/MC14016B/MC14016B-cache.lib
new file mode 100644
index 000000000..3b7d214a1
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.cir b/library/SubcircuitLibrary/MC14016B/MC14016B.cir
new file mode 100644
index 000000000..8c317047f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.cir
@@ -0,0 +1,17 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B\MC14016B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 15:06:49
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad4_ eSim_MOS_P
+M2 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad4_ eSim_MOS_N
+U3 Net-_U2-Pad2_ Net-_M1-Pad2_ dac_bridge_1
+U5 Net-_M1-Pad3_ Net-_U1-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad4_ Net-_M2-Pad4_ PORT
+U4 Net-_U1-Pad2_ Net-_M2-Pad2_ dac_bridge_1
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.cir.out b/library/SubcircuitLibrary/MC14016B/MC14016B.cir.out
new file mode 100644
index 000000000..42ed3c57a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.cir.out
@@ -0,0 +1,32 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b\mc14016b.cir
+
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad4_ mos_n W=100u L=100u M=1
+* u3 net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1
+* u5 net-_m1-pad3_ net-_u1-pad1_ net-_m1-pad1_ net-_m1-pad4_ net-_m2-pad4_ port
+* u4 net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u3
+a4 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u4
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.pro b/library/SubcircuitLibrary/MC14016B/MC14016B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.proj b/library/SubcircuitLibrary/MC14016B/MC14016B.proj
new file mode 100644
index 000000000..fe3e0087c
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.proj
@@ -0,0 +1 @@
+schematicFile MC14016B.sch
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.sch b/library/SubcircuitLibrary/MC14016B/MC14016B.sch
new file mode 100644
index 000000000..b02290ac5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.sch
@@ -0,0 +1,213 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14016B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U1
+U 1 1 68590916
+P 2650 3150
+F 0 "U1" H 2650 3050 60 0000 C CNN
+F 1 "d_inverter" H 2650 3300 60 0000 C CNN
+F 2 "" H 2700 3100 60 0000 C CNN
+F 3 "" H 2700 3100 60 0000 C CNN
+ 1 2650 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 68590952
+P 3650 3150
+F 0 "U2" H 3650 3050 60 0000 C CNN
+F 1 "d_inverter" H 3650 3300 60 0000 C CNN
+F 2 "" H 3700 3100 60 0000 C CNN
+F 3 "" H 3700 3100 60 0000 C CNN
+ 1 3650 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2950 3150 3350 3150
+$Comp
+L eSim_MOS_P M1
+U 1 1 685909B0
+P 5800 3150
+F 0 "M1" H 5750 3200 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5850 3300 50 0000 R CNN
+F 2 "" H 6050 3250 29 0000 C CNN
+F 3 "" H 5850 3150 60 0000 C CNN
+ 1 5800 3150
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 68590A0A
+P 6000 3950
+F 0 "M2" H 6000 3800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6100 3900 50 0000 R CNN
+F 2 "" H 6300 3650 29 0000 C CNN
+F 3 "" H 6100 3750 60 0000 C CNN
+ 1 6000 3950
+ 0 1 -1 0
+$EndComp
+Wire Wire Line
+ 5600 3300 5600 3750
+Wire Wire Line
+ 6000 3300 6000 3750
+$Comp
+L dac_bridge_1 U3
+U 1 1 68590B03
+P 4750 3200
+F 0 "U3" H 4750 3200 60 0000 C CNN
+F 1 "dac_bridge_1" H 4750 3350 60 0000 C CNN
+F 2 "" H 4750 3200 60 0000 C CNN
+F 3 "" H 4750 3200 60 0000 C CNN
+ 1 4750 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3950 3150 4150 3150
+$Comp
+L PORT U5
+U 2 1 68590BE8
+P 1900 3150
+F 0 "U5" H 1950 3250 30 0000 C CNN
+F 1 "PORT" H 1900 3150 30 0000 C CNN
+F 2 "" H 1900 3150 60 0000 C CNN
+F 3 "" H 1900 3150 60 0000 C CNN
+ 2 1900 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U5
+U 1 1 68590C23
+P 4750 3550
+F 0 "U5" H 4800 3650 30 0000 C CNN
+F 1 "PORT" H 4750 3550 30 0000 C CNN
+F 2 "" H 4750 3550 60 0000 C CNN
+F 3 "" H 4750 3550 60 0000 C CNN
+ 1 4750 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U5
+U 4 1 68590C48
+P 5300 3400
+F 0 "U5" H 5350 3500 30 0000 C CNN
+F 1 "PORT" H 5300 3400 30 0000 C CNN
+F 2 "" H 5300 3400 60 0000 C CNN
+F 3 "" H 5300 3400 60 0000 C CNN
+ 4 5300 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U5
+U 3 1 68590C87
+P 6450 3500
+F 0 "U5" H 6500 3600 30 0000 C CNN
+F 1 "PORT" H 6450 3500 30 0000 C CNN
+F 2 "" H 6450 3500 60 0000 C CNN
+F 3 "" H 6450 3500 60 0000 C CNN
+ 3 6450 3500
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U5
+U 5 1 68590CB0
+P 5300 3650
+F 0 "U5" H 5350 3750 30 0000 C CNN
+F 1 "PORT" H 5300 3650 30 0000 C CNN
+F 2 "" H 5300 3650 60 0000 C CNN
+F 3 "" H 5300 3650 60 0000 C CNN
+ 5 5300 3650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2150 3150 2350 3150
+$Comp
+L dac_bridge_1 U4
+U 1 1 68592608
+P 4800 4300
+F 0 "U4" H 4800 4300 60 0000 C CNN
+F 1 "dac_bridge_1" H 4800 4450 60 0000 C CNN
+F 2 "" H 4800 4300 60 0000 C CNN
+F 3 "" H 4800 4300 60 0000 C CNN
+ 1 4800 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5300 3150 5650 3150
+Wire Wire Line
+ 5650 3150 5650 3000
+Wire Wire Line
+ 5650 3000 5800 3000
+Wire Wire Line
+ 3200 3150 3200 4250
+Wire Wire Line
+ 3200 4250 4200 4250
+Connection ~ 3200 3150
+Wire Wire Line
+ 5350 4250 5800 4250
+Wire Wire Line
+ 5800 4250 5800 4050
+Wire Wire Line
+ 5550 3650 5650 3650
+Wire Wire Line
+ 5550 3400 5650 3400
+Wire Wire Line
+ 5000 3550 5600 3550
+Connection ~ 5600 3550
+Wire Wire Line
+ 6200 3500 6000 3500
+Connection ~ 6000 3500
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B.sub b/library/SubcircuitLibrary/MC14016B/MC14016B.sub
new file mode 100644
index 000000000..abb10c93f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B.sub
@@ -0,0 +1,26 @@
+* Subcircuit MC14016B
+.subckt MC14016B net-_m1-pad3_ net-_u1-pad1_ net-_m1-pad1_ net-_m1-pad4_ net-_m2-pad4_
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b\mc14016b.cir
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad4_ mos_n W=100u L=100u M=1
+* u3 net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1
+* u4 net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u3
+a4 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u4
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends MC14016B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B/MC14016B_Previous_Values.xml
new file mode 100644
index 000000000..e8c909fcb
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_Previous_Values.xml
@@ -0,0 +1 @@
+d_inverterd_inverterdac_bridgeadc_bridgedac_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad-cache.lib b/library/SubcircuitLibrary/MC14016B/MC14016B_quad-cache.lib
new file mode 100644
index 000000000..6a4c4d1a0
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# MC14016B_1
+#
+DEF MC14016B_1 X 0 40 Y Y 1 F N
+F0 "X" 0 -650 60 H V C CNN
+F1 "MC14016B_1" 50 650 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 400 400 -400 0 1 0 N
+X IN 1 -550 300 200 R 50 50 1 1 I
+X CONTROL 2 -550 100 200 R 50 50 1 1 I
+X OUT 3 -550 -250 200 R 50 50 1 1 O
+X VDD 4 600 250 200 L 50 50 1 1 I
+X GND 5 600 -200 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir
new file mode 100644
index 000000000..4ce43c410
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir
@@ -0,0 +1,15 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B_quad\MC14016B_quad.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 11:44:09
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad13_ Net-_U1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad7_ MC14016B_1
+X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad3_ Net-_U1-Pad14_ Net-_U1-Pad7_ MC14016B_1
+X3 Net-_U1-Pad8_ Net-_U1-Pad6_ Net-_U1-Pad9_ Net-_U1-Pad14_ Net-_U1-Pad7_ MC14016B_1
+X4 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad10_ Net-_U1-Pad14_ Net-_U1-Pad7_ MC14016B_1
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir.out b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir.out
new file mode 100644
index 000000000..d762fa9c2
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.cir.out
@@ -0,0 +1,17 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b_quad\mc14016b_quad.cir
+
+.include MC14016B.sub
+x1 net-_u1-pad1_ net-_u1-pad13_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x3 net-_u1-pad8_ net-_u1-pad6_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x4 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad10_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.pro b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sch b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sch
new file mode 100644
index 000000000..c5897efff
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sch
@@ -0,0 +1,305 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14016B_quad-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L MC14016B_1 X1
+U 1 1 685BC07B
+P 21400 8300
+F 0 "X1" H 21400 7650 60 0000 C CNN
+F 1 "MC14016B_1" H 21450 8950 60 0000 C CNN
+F 2 "" H 21400 8300 60 0001 C CNN
+F 3 "" H 21400 8300 60 0001 C CNN
+ 1 21400 8300
+ 1 0 0 -1
+$EndComp
+$Comp
+L MC14016B_1 X2
+U 1 1 685BC0C0
+P 21400 9550
+F 0 "X2" H 21400 8900 60 0000 C CNN
+F 1 "MC14016B_1" H 21450 10200 60 0000 C CNN
+F 2 "" H 21400 9550 60 0001 C CNN
+F 3 "" H 21400 9550 60 0001 C CNN
+ 1 21400 9550
+ 1 0 0 -1
+$EndComp
+$Comp
+L MC14016B_1 X3
+U 1 1 685BC0F0
+P 21400 10700
+F 0 "X3" H 21400 10050 60 0000 C CNN
+F 1 "MC14016B_1" H 21450 11350 60 0000 C CNN
+F 2 "" H 21400 10700 60 0001 C CNN
+F 3 "" H 21400 10700 60 0001 C CNN
+ 1 21400 10700
+ 1 0 0 -1
+$EndComp
+$Comp
+L MC14016B_1 X4
+U 1 1 685BC1AF
+P 21450 11900
+F 0 "X4" H 21450 11250 60 0000 C CNN
+F 1 "MC14016B_1" H 21500 12550 60 0000 C CNN
+F 2 "" H 21450 11900 60 0001 C CNN
+F 3 "" H 21450 11900 60 0001 C CNN
+ 1 21450 11900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 22000 8050 22600 8050
+Wire Wire Line
+ 22500 8050 22500 11650
+Wire Wire Line
+ 22500 9300 22000 9300
+Wire Wire Line
+ 22500 10450 22000 10450
+Connection ~ 22500 9300
+Wire Wire Line
+ 22500 11650 22050 11650
+Connection ~ 22500 10450
+Wire Wire Line
+ 22750 12100 22050 12100
+Wire Wire Line
+ 22750 8500 22750 12100
+Wire Wire Line
+ 22750 10900 22000 10900
+Wire Wire Line
+ 22000 9750 22750 9750
+Connection ~ 22750 10900
+Wire Wire Line
+ 22000 8500 22850 8500
+Connection ~ 22750 9750
+$Comp
+L PORT U1
+U 7 1 685BC5D2
+P 23100 8500
+F 0 "U1" H 23150 8600 30 0000 C CNN
+F 1 "PORT" H 23100 8500 30 0000 C CNN
+F 2 "" H 23100 8500 60 0000 C CNN
+F 3 "" H 23100 8500 60 0000 C CNN
+ 7 23100 8500
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685BC5F1
+P 20450 10400
+F 0 "U1" H 20500 10500 30 0000 C CNN
+F 1 "PORT" H 20450 10400 30 0000 C CNN
+F 2 "" H 20450 10400 60 0000 C CNN
+F 3 "" H 20450 10400 60 0000 C CNN
+ 8 20450 10400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685BC612
+P 20500 11600
+F 0 "U1" H 20550 11700 30 0000 C CNN
+F 1 "PORT" H 20500 11600 30 0000 C CNN
+F 2 "" H 20500 11600 60 0000 C CNN
+F 3 "" H 20500 11600 60 0000 C CNN
+ 11 20500 11600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685BC635
+P 20500 11800
+F 0 "U1" H 20550 11900 30 0000 C CNN
+F 1 "PORT" H 20500 11800 30 0000 C CNN
+F 2 "" H 20500 11800 60 0000 C CNN
+F 3 "" H 20500 11800 60 0000 C CNN
+ 12 20500 11800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685BC65A
+P 20450 8550
+F 0 "U1" H 20500 8650 30 0000 C CNN
+F 1 "PORT" H 20450 8550 30 0000 C CNN
+F 2 "" H 20450 8550 60 0000 C CNN
+F 3 "" H 20450 8550 60 0000 C CNN
+ 2 20450 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685BC681
+P 20450 10950
+F 0 "U1" H 20500 11050 30 0000 C CNN
+F 1 "PORT" H 20450 10950 30 0000 C CNN
+F 2 "" H 20450 10950 60 0000 C CNN
+F 3 "" H 20450 10950 60 0000 C CNN
+ 9 20450 10950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685BC6AA
+P 20450 8200
+F 0 "U1" H 20500 8300 30 0000 C CNN
+F 1 "PORT" H 20450 8200 30 0000 C CNN
+F 2 "" H 20450 8200 60 0000 C CNN
+F 3 "" H 20450 8200 60 0000 C CNN
+ 13 20450 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685BC6D5
+P 20400 9250
+F 0 "U1" H 20450 9350 30 0000 C CNN
+F 1 "PORT" H 20400 9250 30 0000 C CNN
+F 2 "" H 20400 9250 60 0000 C CNN
+F 3 "" H 20400 9250 60 0000 C CNN
+ 4 20400 9250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685BC702
+P 20450 9800
+F 0 "U1" H 20500 9900 30 0000 C CNN
+F 1 "PORT" H 20450 9800 30 0000 C CNN
+F 2 "" H 20450 9800 60 0000 C CNN
+F 3 "" H 20450 9800 60 0000 C CNN
+ 3 20450 9800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685BC735
+P 20450 8000
+F 0 "U1" H 20500 8100 30 0000 C CNN
+F 1 "PORT" H 20450 8000 30 0000 C CNN
+F 2 "" H 20450 8000 60 0000 C CNN
+F 3 "" H 20450 8000 60 0000 C CNN
+ 1 20450 8000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685BC766
+P 20450 9450
+F 0 "U1" H 20500 9550 30 0000 C CNN
+F 1 "PORT" H 20450 9450 30 0000 C CNN
+F 2 "" H 20450 9450 60 0000 C CNN
+F 3 "" H 20450 9450 60 0000 C CNN
+ 5 20450 9450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685BC79D
+P 20500 10600
+F 0 "U1" H 20550 10700 30 0000 C CNN
+F 1 "PORT" H 20500 10600 30 0000 C CNN
+F 2 "" H 20500 10600 60 0000 C CNN
+F 3 "" H 20500 10600 60 0000 C CNN
+ 6 20500 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685BC7D2
+P 20500 12150
+F 0 "U1" H 20550 12250 30 0000 C CNN
+F 1 "PORT" H 20500 12150 30 0000 C CNN
+F 2 "" H 20500 12150 60 0000 C CNN
+F 3 "" H 20500 12150 60 0000 C CNN
+ 10 20500 12150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685BC809
+P 22850 8050
+F 0 "U1" H 22900 8150 30 0000 C CNN
+F 1 "PORT" H 22850 8050 30 0000 C CNN
+F 2 "" H 22850 8050 60 0000 C CNN
+F 3 "" H 22850 8050 60 0000 C CNN
+ 14 22850 8050
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 20700 8200 20850 8200
+Wire Wire Line
+ 20700 8000 20850 8000
+Wire Wire Line
+ 20700 8550 20850 8550
+Wire Wire Line
+ 20700 9450 20850 9450
+Wire Wire Line
+ 20650 9250 20850 9250
+Wire Wire Line
+ 20700 9800 20850 9800
+Wire Wire Line
+ 20750 10600 20850 10600
+Wire Wire Line
+ 20700 10400 20850 10400
+Wire Wire Line
+ 20700 10950 20850 10950
+Wire Wire Line
+ 20750 11800 20900 11800
+Wire Wire Line
+ 20750 11600 20900 11600
+Wire Wire Line
+ 20750 12150 20900 12150
+Connection ~ 22750 8500
+Connection ~ 22500 8050
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sub b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sub
new file mode 100644
index 000000000..23cf58569
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad.sub
@@ -0,0 +1,11 @@
+* Subcircuit MC14016B_quad
+.subckt MC14016B_quad net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b_quad\mc14016b_quad.cir
+.include MC14016B.sub
+x1 net-_u1-pad1_ net-_u1-pad13_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad3_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x3 net-_u1-pad8_ net-_u1-pad6_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+x4 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad10_ net-_u1-pad14_ net-_u1-pad7_ MC14016B
+* Control Statements
+
+.ends MC14016B_quad
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_quad_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B/MC14016B_quad_Previous_Values.xml
new file mode 100644
index 000000000..b1c23cb67
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_quad_Previous_Values.xml
@@ -0,0 +1 @@
+d_inverterd_inverterdac_bridgedac_bridged_inverterd_inverterdac_bridgedac_bridged_inverterd_inverterdac_bridgedac_bridged_inverterd_inverterdac_bridgedac_bridgeC:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016BC:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016BC:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016BC:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016BtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test-cache.lib b/library/SubcircuitLibrary/MC14016B/MC14016B_test-cache.lib
new file mode 100644
index 000000000..2cafb8e4a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test-cache.lib
@@ -0,0 +1,131 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# MC14016B
+#
+DEF MC14016B X 0 40 Y Y 1 F N
+F0 "X" 0 -1100 60 H V C CNN
+F1 "MC14016B" 50 1250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -400 950 500 -550 0 1 0 N
+X IN_1 1 -600 800 200 R 50 50 1 1 I
+X OUT_1 2 -600 600 200 R 50 50 1 1 O
+X OUT_2 3 -600 400 200 R 50 50 1 1 O
+X IN_2 4 -600 200 200 R 50 50 1 1 I
+X CONT2 5 -600 0 200 R 50 50 1 1 I
+X CONT3 6 -600 -200 200 R 50 50 1 1 I
+X VSS 7 -600 -400 200 R 50 50 1 1 I
+X IN_3 8 700 -400 200 L 50 50 1 1 I
+X OUT_3 9 700 -200 200 L 50 50 1 1 O
+X OUT_4 10 700 0 200 L 50 50 1 1 O
+X IN_4 11 700 200 200 L 50 50 1 1 I
+X CONT4 12 700 400 200 L 50 50 1 1 I
+X CONT1 13 700 600 200 L 50 50 1 1 I
+X VDD 14 700 800 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir b/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir
new file mode 100644
index 000000000..74c2f828d
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir
@@ -0,0 +1,26 @@
+* C:\Users\pavithra\eSim-Workspace\MC14016B_test\MC14016B_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 11:45:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v3 in GND sine
+v4 Net-_X1-Pad4_ GND sine
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ adc_bridge_2
+v1 Net-_U1-Pad1_ GND pulse
+v2 Net-_U1-Pad2_ GND pulse
+U3 out plot_v1
+v5 Net-_X1-Pad14_ GND DC
+U6 cont Net-_U6-Pad2_ Net-_U6-Pad3_ Net-_U6-Pad4_ adc_bridge_2
+v9 cont GND pulse
+v8 Net-_U6-Pad2_ GND pulse
+U2 Net-_U2-Pad~_ plot_v1
+U4 Net-_U4-Pad~_ plot_v1
+U5 Net-_U5-Pad~_ plot_v1
+v6 Net-_X1-Pad8_ GND sine
+v7 Net-_X1-Pad11_ GND sine
+X1 in out Net-_U2-Pad~_ Net-_X1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad4_ GND Net-_X1-Pad8_ Net-_U5-Pad~_ Net-_U4-Pad~_ Net-_X1-Pad11_ Net-_U6-Pad4_ Net-_U6-Pad3_ Net-_X1-Pad14_ MC14016B
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir.out b/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir.out
new file mode 100644
index 000000000..5a9ba062c
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.cir.out
@@ -0,0 +1,35 @@
+* c:\users\pavithra\esim-workspace\mc14016b_test\mc14016b_test.cir
+
+.include MC14016B_quad.sub
+v3 in gnd sine(0 5 1k 0 0)
+v4 net-_x1-pad4_ gnd sine(0 5 1k 0 0)
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
+v1 net-_u1-pad1_ gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+v2 net-_u1-pad2_ gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+* u3 out plot_v1
+v5 net-_x1-pad14_ gnd dc 5
+* u6 cont net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ adc_bridge_2
+v9 cont gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+v8 net-_u6-pad2_ gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+* u2 net-_u2-pad_ plot_v1
+* u4 net-_u4-pad_ plot_v1
+* u5 net-_u5-pad_ plot_v1
+v6 net-_x1-pad8_ gnd sine(0 5 1k 0 0)
+v7 net-_x1-pad11_ gnd sine(0 5 1k 0 0)
+x1 in out net-_u2-pad_ net-_x1-pad4_ net-_u1-pad3_ net-_u1-pad4_ gnd net-_x1-pad8_ net-_u5-pad~_ net-_u4-pad_ net-_x1-pad11_ net-_u6-pad4_ net-_u6-pad3_ net-_x1-pad14_ MC14016B_quad
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
+a2 [cont net-_u6-pad2_ ] [net-_u6-pad3_ net-_u6-pad4_ ] u6
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 1e-06 10e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out)+6v(in)+12v(cont)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.pro b/library/SubcircuitLibrary/MC14016B/MC14016B_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.proj b/library/SubcircuitLibrary/MC14016B/MC14016B_test.proj
new file mode 100644
index 000000000..2ef836be4
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.proj
@@ -0,0 +1 @@
+schematicFile MC14016B_test.sch
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test.sch b/library/SubcircuitLibrary/MC14016B/MC14016B_test.sch
new file mode 100644
index 000000000..f812946e9
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test.sch
@@ -0,0 +1,431 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sine v3
+U 1 1 685A3BC7
+P 4350 3250
+F 0 "v3" H 4150 3350 60 0000 C CNN
+F 1 "sine" H 4150 3200 60 0000 C CNN
+F 2 "R1" H 4050 3250 60 0000 C CNN
+F 3 "" H 4350 3250 60 0000 C CNN
+ 1 4350 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4350 2800 4800 2800
+$Comp
+L sine v4
+U 1 1 685A3C08
+P 4550 3900
+F 0 "v4" H 4350 4000 60 0000 C CNN
+F 1 "sine" H 4350 3850 60 0000 C CNN
+F 2 "R1" H 4250 3900 60 0000 C CNN
+F 3 "" H 4550 3900 60 0000 C CNN
+ 1 4550 3900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4550 3450 4550 3400
+Wire Wire Line
+ 4550 3400 4800 3400
+$Comp
+L eSim_GND #PWR01
+U 1 1 685A3DD1
+P 4200 3750
+F 0 "#PWR01" H 4200 3500 50 0001 C CNN
+F 1 "eSim_GND" H 4200 3600 50 0000 C CNN
+F 2 "" H 4200 3750 50 0001 C CNN
+F 3 "" H 4200 3750 50 0001 C CNN
+ 1 4200 3750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4200 3750 4200 3700
+Wire Wire Line
+ 4200 3700 4350 3700
+$Comp
+L eSim_GND #PWR02
+U 1 1 685A3DF4
+P 4450 4350
+F 0 "#PWR02" H 4450 4100 50 0001 C CNN
+F 1 "eSim_GND" H 4450 4200 50 0000 C CNN
+F 2 "" H 4450 4350 50 0001 C CNN
+F 3 "" H 4450 4350 50 0001 C CNN
+ 1 4450 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4450 4350 4550 4350
+$Comp
+L eSim_GND #PWR03
+U 1 1 685A3F5C
+P 4800 4100
+F 0 "#PWR03" H 4800 3850 50 0001 C CNN
+F 1 "eSim_GND" H 4800 3950 50 0000 C CNN
+F 2 "" H 4800 4100 50 0001 C CNN
+F 3 "" H 4800 4100 50 0001 C CNN
+ 1 4800 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 4000 4800 4100
+$Comp
+L adc_bridge_2 U1
+U 1 1 685A3F7A
+P 3550 3600
+F 0 "U1" H 3550 3600 60 0000 C CNN
+F 1 "adc_bridge_2" H 3550 3750 60 0000 C CNN
+F 2 "" H 3550 3600 60 0000 C CNN
+F 3 "" H 3550 3600 60 0000 C CNN
+ 1 3550 3600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4100 3550 4800 3550
+Wire Wire Line
+ 4800 3550 4800 3600
+Wire Wire Line
+ 4100 3650 4800 3650
+Wire Wire Line
+ 4800 3650 4800 3800
+$Comp
+L pulse v1
+U 1 1 685A40D1
+P 2650 4000
+F 0 "v1" H 2450 4100 60 0000 C CNN
+F 1 "pulse" H 2450 3950 60 0000 C CNN
+F 2 "R1" H 2350 4000 60 0000 C CNN
+F 3 "" H 2650 4000 60 0000 C CNN
+ 1 2650 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v2
+U 1 1 685A4109
+P 2950 4250
+F 0 "v2" H 2750 4350 60 0000 C CNN
+F 1 "pulse" H 2750 4200 60 0000 C CNN
+F 2 "R1" H 2650 4250 60 0000 C CNN
+F 3 "" H 2950 4250 60 0000 C CNN
+ 1 2950 4250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2950 3650 2950 3800
+Wire Wire Line
+ 2650 3550 2950 3550
+$Comp
+L eSim_GND #PWR04
+U 1 1 685A4160
+P 2950 4800
+F 0 "#PWR04" H 2950 4550 50 0001 C CNN
+F 1 "eSim_GND" H 2950 4650 50 0000 C CNN
+F 2 "" H 2950 4800 50 0001 C CNN
+F 3 "" H 2950 4800 50 0001 C CNN
+ 1 2950 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR05
+U 1 1 685A417D
+P 2650 4550
+F 0 "#PWR05" H 2650 4300 50 0001 C CNN
+F 1 "eSim_GND" H 2650 4400 50 0000 C CNN
+F 2 "" H 2650 4550 50 0001 C CNN
+F 3 "" H 2650 4550 50 0001 C CNN
+ 1 2650 4550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2650 4450 2650 4550
+Wire Wire Line
+ 2950 4700 2950 4800
+$Comp
+L plot_v1 U3
+U 1 1 685A44FD
+P 4700 3150
+F 0 "U3" H 4700 3650 60 0000 C CNN
+F 1 "plot_v1" H 4900 3500 60 0000 C CNN
+F 2 "" H 4700 3150 60 0000 C CNN
+F 3 "" H 4700 3150 60 0000 C CNN
+ 1 4700 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4700 2950 4700 3000
+Wire Wire Line
+ 4700 3000 4800 3000
+Wire Wire Line
+ 4600 3100 4600 3200
+Wire Wire Line
+ 4600 3200 4800 3200
+$Comp
+L DC v5
+U 1 1 685A47BA
+P 6250 2350
+F 0 "v5" H 6050 2450 60 0000 C CNN
+F 1 "DC" H 6050 2300 60 0000 C CNN
+F 2 "R1" H 5950 2350 60 0000 C CNN
+F 3 "" H 6250 2350 60 0000 C CNN
+ 1 6250 2350
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 6250 2800 6100 2800
+$Comp
+L eSim_GND #PWR06
+U 1 1 685A4833
+P 6400 1900
+F 0 "#PWR06" H 6400 1650 50 0001 C CNN
+F 1 "eSim_GND" H 6400 1750 50 0000 C CNN
+F 2 "" H 6400 1900 50 0001 C CNN
+F 3 "" H 6400 1900 50 0001 C CNN
+ 1 6400 1900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6250 1900 6400 1900
+$Comp
+L adc_bridge_2 U6
+U 1 1 685A487F
+P 6850 3100
+F 0 "U6" H 6850 3100 60 0000 C CNN
+F 1 "adc_bridge_2" H 6850 3250 60 0000 C CNN
+F 2 "" H 6850 3100 60 0000 C CNN
+F 3 "" H 6850 3100 60 0000 C CNN
+ 1 6850 3100
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6300 3050 6100 3050
+Wire Wire Line
+ 6100 3050 6100 3000
+Wire Wire Line
+ 6300 3150 6100 3150
+Wire Wire Line
+ 6100 3150 6100 3200
+$Comp
+L pulse v9
+U 1 1 685A4A5C
+P 7850 3500
+F 0 "v9" H 7650 3600 60 0000 C CNN
+F 1 "pulse" H 7650 3450 60 0000 C CNN
+F 2 "R1" H 7550 3500 60 0000 C CNN
+F 3 "" H 7850 3500 60 0000 C CNN
+ 1 7850 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v8
+U 1 1 685A4CEA
+P 7600 3700
+F 0 "v8" H 7400 3800 60 0000 C CNN
+F 1 "pulse" H 7400 3650 60 0000 C CNN
+F 2 "R1" H 7300 3700 60 0000 C CNN
+F 3 "" H 7600 3700 60 0000 C CNN
+ 1 7600 3700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7450 3150 7600 3150
+Wire Wire Line
+ 7600 3150 7600 3250
+Wire Wire Line
+ 7450 3050 7850 3050
+$Comp
+L eSim_GND #PWR07
+U 1 1 685A508F
+P 7600 4300
+F 0 "#PWR07" H 7600 4050 50 0001 C CNN
+F 1 "eSim_GND" H 7600 4150 50 0000 C CNN
+F 2 "" H 7600 4300 50 0001 C CNN
+F 3 "" H 7600 4300 50 0001 C CNN
+ 1 7600 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR08
+U 1 1 685A50BE
+P 7850 4100
+F 0 "#PWR08" H 7850 3850 50 0001 C CNN
+F 1 "eSim_GND" H 7850 3950 50 0000 C CNN
+F 2 "" H 7850 4100 50 0001 C CNN
+F 3 "" H 7850 4100 50 0001 C CNN
+ 1 7850 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7600 4150 7600 4300
+Wire Wire Line
+ 7850 3950 7850 4100
+$Comp
+L plot_v1 U2
+U 1 1 685A455F
+P 4600 3300
+F 0 "U2" H 4600 3800 60 0000 C CNN
+F 1 "plot_v1" H 4800 3650 60 0000 C CNN
+F 2 "" H 4600 3300 60 0000 C CNN
+F 3 "" H 4600 3300 60 0000 C CNN
+ 1 4600 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 685A5166
+P 6250 3800
+F 0 "U4" H 6250 4300 60 0000 C CNN
+F 1 "plot_v1" H 6450 4150 60 0000 C CNN
+F 2 "" H 6250 3800 60 0000 C CNN
+F 3 "" H 6250 3800 60 0000 C CNN
+ 1 6250 3800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6100 3600 6250 3600
+$Comp
+L plot_v1 U5
+U 1 1 685A51E6
+P 6350 4000
+F 0 "U5" H 6350 4500 60 0000 C CNN
+F 1 "plot_v1" H 6550 4350 60 0000 C CNN
+F 2 "" H 6350 4000 60 0000 C CNN
+F 3 "" H 6350 4000 60 0000 C CNN
+ 1 6350 4000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6100 3800 6350 3800
+$Comp
+L sine v6
+U 1 1 685A525D
+P 6250 4450
+F 0 "v6" H 6050 4550 60 0000 C CNN
+F 1 "sine" H 6050 4400 60 0000 C CNN
+F 2 "R1" H 5950 4450 60 0000 C CNN
+F 3 "" H 6250 4450 60 0000 C CNN
+ 1 6250 4450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6100 4000 6250 4000
+$Comp
+L eSim_GND #PWR09
+U 1 1 685A52DF
+P 6250 5000
+F 0 "#PWR09" H 6250 4750 50 0001 C CNN
+F 1 "eSim_GND" H 6250 4850 50 0000 C CNN
+F 2 "" H 6250 5000 50 0001 C CNN
+F 3 "" H 6250 5000 50 0001 C CNN
+ 1 6250 5000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6250 4900 6250 5000
+$Comp
+L sine v7
+U 1 1 685A5349
+P 6850 3900
+F 0 "v7" H 6650 4000 60 0000 C CNN
+F 1 "sine" H 6650 3850 60 0000 C CNN
+F 2 "R1" H 6550 3900 60 0000 C CNN
+F 3 "" H 6850 3900 60 0000 C CNN
+ 1 6850 3900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6100 3400 6850 3400
+Wire Wire Line
+ 6850 3400 6850 3450
+$Comp
+L eSim_GND #PWR010
+U 1 1 685A53D0
+P 6850 4450
+F 0 "#PWR010" H 6850 4200 50 0001 C CNN
+F 1 "eSim_GND" H 6850 4300 50 0000 C CNN
+F 2 "" H 6850 4450 50 0001 C CNN
+F 3 "" H 6850 4450 50 0001 C CNN
+ 1 6850 4450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6850 4350 6850 4450
+Text GLabel 4450 2700 0 60 Input ~ 0
+in
+Wire Wire Line
+ 4450 2700 4450 2800
+Connection ~ 4450 2800
+Text GLabel 7700 2900 0 60 Input ~ 0
+cont
+Wire Wire Line
+ 7700 2900 7700 3050
+Connection ~ 7700 3050
+Text GLabel 4750 3050 0 60 Input ~ 0
+out
+Wire Wire Line
+ 4750 3050 4750 3000
+Connection ~ 4750 3000
+$Comp
+L MC14016B X1
+U 1 1 685A5D9F
+P 5400 3600
+F 0 "X1" H 5400 2500 60 0000 C CNN
+F 1 "MC14016B" H 5450 4850 60 0000 C CNN
+F 2 "" H 5400 3600 60 0001 C CNN
+F 3 "" H 5400 3600 60 0001 C CNN
+ 1 5400 3600
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14016B/MC14016B_test_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B/MC14016B_test_Previous_Values.xml
new file mode 100644
index 000000000..f0bd5a163
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/MC14016B_test_Previous_Values.xml
@@ -0,0 +1 @@
+sine051k0sine051k0pulse0500.1n0.1n1m2mpulse0500.1n0.1n1m2mdc5pulse0500.1n0.1n1m 2mpulse0500.1n0.1n1m2msine051k0sine05 1k0adc_bridgeadc_bridgeC:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B_quadtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes0110msusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B/NMOS-5um.lib b/library/SubcircuitLibrary/MC14016B/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/MC14016B/PMOS-5um.lib b/library/SubcircuitLibrary/MC14016B/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/MC14016B/analysis b/library/SubcircuitLibrary/MC14016B/analysis
new file mode 100644
index 000000000..b21a9e13b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B/analysis
@@ -0,0 +1 @@
+.tran 1e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B_One/D.lib b/library/SubcircuitLibrary/MC14016B_One/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B-cache.lib b/library/SubcircuitLibrary/MC14016B_One/MC14016B-cache.lib
new file mode 100644
index 000000000..3b7d214a1
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir b/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir
new file mode 100644
index 000000000..8c317047f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir
@@ -0,0 +1,17 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016B\MC14016B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 15:06:49
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad4_ eSim_MOS_P
+M2 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad4_ eSim_MOS_N
+U3 Net-_U2-Pad2_ Net-_M1-Pad2_ dac_bridge_1
+U5 Net-_M1-Pad3_ Net-_U1-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad4_ Net-_M2-Pad4_ PORT
+U4 Net-_U1-Pad2_ Net-_M2-Pad2_ dac_bridge_1
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir.out b/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir.out
new file mode 100644
index 000000000..42ed3c57a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.cir.out
@@ -0,0 +1,32 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b\mc14016b.cir
+
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad4_ mos_n W=100u L=100u M=1
+* u3 net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1
+* u5 net-_m1-pad3_ net-_u1-pad1_ net-_m1-pad1_ net-_m1-pad4_ net-_m2-pad4_ port
+* u4 net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u3
+a4 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u4
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.pro b/library/SubcircuitLibrary/MC14016B_One/MC14016B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.sch b/library/SubcircuitLibrary/MC14016B_One/MC14016B.sch
new file mode 100644
index 000000000..b02290ac5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.sch
@@ -0,0 +1,213 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14016B-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U1
+U 1 1 68590916
+P 2650 3150
+F 0 "U1" H 2650 3050 60 0000 C CNN
+F 1 "d_inverter" H 2650 3300 60 0000 C CNN
+F 2 "" H 2700 3100 60 0000 C CNN
+F 3 "" H 2700 3100 60 0000 C CNN
+ 1 2650 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 68590952
+P 3650 3150
+F 0 "U2" H 3650 3050 60 0000 C CNN
+F 1 "d_inverter" H 3650 3300 60 0000 C CNN
+F 2 "" H 3700 3100 60 0000 C CNN
+F 3 "" H 3700 3100 60 0000 C CNN
+ 1 3650 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2950 3150 3350 3150
+$Comp
+L eSim_MOS_P M1
+U 1 1 685909B0
+P 5800 3150
+F 0 "M1" H 5750 3200 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5850 3300 50 0000 R CNN
+F 2 "" H 6050 3250 29 0000 C CNN
+F 3 "" H 5850 3150 60 0000 C CNN
+ 1 5800 3150
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 68590A0A
+P 6000 3950
+F 0 "M2" H 6000 3800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6100 3900 50 0000 R CNN
+F 2 "" H 6300 3650 29 0000 C CNN
+F 3 "" H 6100 3750 60 0000 C CNN
+ 1 6000 3950
+ 0 1 -1 0
+$EndComp
+Wire Wire Line
+ 5600 3300 5600 3750
+Wire Wire Line
+ 6000 3300 6000 3750
+$Comp
+L dac_bridge_1 U3
+U 1 1 68590B03
+P 4750 3200
+F 0 "U3" H 4750 3200 60 0000 C CNN
+F 1 "dac_bridge_1" H 4750 3350 60 0000 C CNN
+F 2 "" H 4750 3200 60 0000 C CNN
+F 3 "" H 4750 3200 60 0000 C CNN
+ 1 4750 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3950 3150 4150 3150
+$Comp
+L PORT U5
+U 2 1 68590BE8
+P 1900 3150
+F 0 "U5" H 1950 3250 30 0000 C CNN
+F 1 "PORT" H 1900 3150 30 0000 C CNN
+F 2 "" H 1900 3150 60 0000 C CNN
+F 3 "" H 1900 3150 60 0000 C CNN
+ 2 1900 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U5
+U 1 1 68590C23
+P 4750 3550
+F 0 "U5" H 4800 3650 30 0000 C CNN
+F 1 "PORT" H 4750 3550 30 0000 C CNN
+F 2 "" H 4750 3550 60 0000 C CNN
+F 3 "" H 4750 3550 60 0000 C CNN
+ 1 4750 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U5
+U 4 1 68590C48
+P 5300 3400
+F 0 "U5" H 5350 3500 30 0000 C CNN
+F 1 "PORT" H 5300 3400 30 0000 C CNN
+F 2 "" H 5300 3400 60 0000 C CNN
+F 3 "" H 5300 3400 60 0000 C CNN
+ 4 5300 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U5
+U 3 1 68590C87
+P 6450 3500
+F 0 "U5" H 6500 3600 30 0000 C CNN
+F 1 "PORT" H 6450 3500 30 0000 C CNN
+F 2 "" H 6450 3500 60 0000 C CNN
+F 3 "" H 6450 3500 60 0000 C CNN
+ 3 6450 3500
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U5
+U 5 1 68590CB0
+P 5300 3650
+F 0 "U5" H 5350 3750 30 0000 C CNN
+F 1 "PORT" H 5300 3650 30 0000 C CNN
+F 2 "" H 5300 3650 60 0000 C CNN
+F 3 "" H 5300 3650 60 0000 C CNN
+ 5 5300 3650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2150 3150 2350 3150
+$Comp
+L dac_bridge_1 U4
+U 1 1 68592608
+P 4800 4300
+F 0 "U4" H 4800 4300 60 0000 C CNN
+F 1 "dac_bridge_1" H 4800 4450 60 0000 C CNN
+F 2 "" H 4800 4300 60 0000 C CNN
+F 3 "" H 4800 4300 60 0000 C CNN
+ 1 4800 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5300 3150 5650 3150
+Wire Wire Line
+ 5650 3150 5650 3000
+Wire Wire Line
+ 5650 3000 5800 3000
+Wire Wire Line
+ 3200 3150 3200 4250
+Wire Wire Line
+ 3200 4250 4200 4250
+Connection ~ 3200 3150
+Wire Wire Line
+ 5350 4250 5800 4250
+Wire Wire Line
+ 5800 4250 5800 4050
+Wire Wire Line
+ 5550 3650 5650 3650
+Wire Wire Line
+ 5550 3400 5650 3400
+Wire Wire Line
+ 5000 3550 5600 3550
+Connection ~ 5600 3550
+Wire Wire Line
+ 6200 3500 6000 3500
+Connection ~ 6000 3500
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B.sub b/library/SubcircuitLibrary/MC14016B_One/MC14016B.sub
new file mode 100644
index 000000000..abb10c93f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B.sub
@@ -0,0 +1,26 @@
+* Subcircuit MC14016B
+.subckt MC14016B net-_m1-pad3_ net-_u1-pad1_ net-_m1-pad1_ net-_m1-pad4_ net-_m2-pad4_
+* c:\fossee\esim\library\subcircuitlibrary\mc14016b\mc14016b.cir
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad4_ mos_n W=100u L=100u M=1
+* u3 net-_u2-pad2_ net-_m1-pad2_ dac_bridge_1
+* u4 net-_u1-pad2_ net-_m2-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m1-pad2_ ] u3
+a4 [net-_u1-pad2_ ] [net-_m2-pad2_ ] u4
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends MC14016B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B_One/MC14016B_Previous_Values.xml
new file mode 100644
index 000000000..e8c909fcb
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_Previous_Values.xml
@@ -0,0 +1 @@
+d_inverterd_inverterdac_bridgeadc_bridgedac_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_one.proj b/library/SubcircuitLibrary/MC14016B_One/MC14016B_one.proj
new file mode 100644
index 000000000..fe3e0087c
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_one.proj
@@ -0,0 +1 @@
+schematicFile MC14016B.sch
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest-cache.lib b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest-cache.lib
new file mode 100644
index 000000000..924b1b3b5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest-cache.lib
@@ -0,0 +1,144 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# MC14016B_1
+#
+DEF MC14016B_1 X 0 40 Y Y 1 F N
+F0 "X" 0 -650 60 H V C CNN
+F1 "MC14016B_1" 50 650 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 400 400 -400 0 1 0 N
+X IN 1 -550 300 200 R 50 50 1 1 I
+X CONTROL 2 -550 100 200 R 50 50 1 1 I
+X OUT 3 -550 -250 200 R 50 50 1 1 O
+X VDD 4 600 250 200 L 50 50 1 1 I
+X GND 5 600 -200 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir
new file mode 100644
index 000000000..33315cfaa
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir
@@ -0,0 +1,22 @@
+* C:\Users\pavithra\eSim-Workspace\MC14016B_onetest\MC14016B_onetest.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 15:37:22
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 cont Net-_U2-Pad2_ adc_bridge_1
+v1 cont GND pulse
+U3 cont plot_v1
+X1 in Net-_U2-Pad2_ out Net-_D1-Pad2_ GND MC14016B_1
+D3 in Net-_D1-Pad2_ eSim_Diode
+D4 GND in eSim_Diode
+v3 Net-_D1-Pad2_ GND DC
+v2 in GND sine
+U4 in plot_v1
+D1 out Net-_D1-Pad2_ eSim_Diode
+D2 GND out eSim_Diode
+U1 out plot_v1
+
+.end
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir.out b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir.out
new file mode 100644
index 000000000..a6da5e416
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.cir.out
@@ -0,0 +1,29 @@
+* c:\users\pavithra\esim-workspace\mc14016b_onetest\mc14016b_onetest.cir
+
+.include MC14016B.sub
+.include D.lib
+* u2 cont net-_u2-pad2_ adc_bridge_1
+v1 cont gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+* u3 cont plot_v1
+x1 in net-_u2-pad2_ out net-_d1-pad2_ gnd MC14016B
+d3 in net-_d1-pad2_ 1N4148
+d4 gnd in 1N4148
+v3 net-_d1-pad2_ gnd dc 5
+v2 in gnd sine(0 5 1k 0 0)
+* u4 in plot_v1
+d1 out net-_d1-pad2_ 1N4148
+d2 gnd out 1N4148
+* u1 out plot_v1
+a1 [cont ] [net-_u2-pad2_ ] u2
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 1e-06 10e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out) +6v(in)+12v(cont)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.pro b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.proj b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.proj
new file mode 100644
index 000000000..8bce94bb8
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.proj
@@ -0,0 +1 @@
+schematicFile MC14016B_onetest.sch
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.sch b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.sch
new file mode 100644
index 000000000..f1b61e569
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest.sch
@@ -0,0 +1,308 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14016B_onetest-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L adc_bridge_1 U2
+U 1 1 68590F01
+P 4800 4950
+F 0 "U2" H 4800 4950 60 0000 C CNN
+F 1 "adc_bridge_1" H 4800 5100 60 0000 C CNN
+F 2 "" H 4800 4950 60 0000 C CNN
+F 3 "" H 4800 4950 60 0000 C CNN
+ 1 4800 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v1
+U 1 1 68590F45
+P 3950 5350
+F 0 "v1" H 3750 5450 60 0000 C CNN
+F 1 "pulse" H 3750 5300 60 0000 C CNN
+F 2 "R1" H 3650 5350 60 0000 C CNN
+F 3 "" H 3950 5350 60 0000 C CNN
+ 1 3950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 68590F9C
+P 3950 5900
+F 0 "#PWR01" H 3950 5650 50 0001 C CNN
+F 1 "eSim_GND" H 3950 5750 50 0000 C CNN
+F 2 "" H 3950 5900 50 0001 C CNN
+F 3 "" H 3950 5900 50 0001 C CNN
+ 1 3950 5900
+ 1 0 0 -1
+$EndComp
+Text GLabel 3900 4850 0 60 Input ~ 0
+cont
+$Comp
+L plot_v1 U3
+U 1 1 685912DC
+P 4150 5000
+F 0 "U3" H 4150 5500 60 0000 C CNN
+F 1 "plot_v1" H 4350 5350 60 0000 C CNN
+F 2 "" H 4150 5000 60 0000 C CNN
+F 3 "" H 4150 5000 60 0000 C CNN
+ 1 4150 5000
+ 1 0 0 -1
+$EndComp
+Text GLabel 5350 3000 0 60 Input ~ 0
+in
+Text GLabel 3750 3200 0 60 Input ~ 0
+out
+$Comp
+L MC14016B_1 X1
+U 1 1 6859297B
+P 6000 3400
+F 0 "X1" H 6000 2750 60 0000 C CNN
+F 1 "MC14016B_1" H 6050 4050 60 0000 C CNN
+F 2 "" H 6000 3400 60 0001 C CNN
+F 3 "" H 6000 3400 60 0001 C CNN
+ 1 6000 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D3
+U 1 1 685929A9
+P 5150 2750
+F 0 "D3" H 5150 2850 50 0000 C CNN
+F 1 "eSim_Diode" H 5150 2650 50 0000 C CNN
+F 2 "" H 5150 2750 60 0000 C CNN
+F 3 "" H 5150 2750 60 0000 C CNN
+ 1 5150 2750
+ 0 1 -1 0
+$EndComp
+$Comp
+L eSim_Diode D4
+U 1 1 68592A10
+P 5150 3350
+F 0 "D4" H 5150 3450 50 0000 C CNN
+F 1 "eSim_Diode" H 5150 3250 50 0000 C CNN
+F 2 "" H 5150 3350 60 0000 C CNN
+F 3 "" H 5150 3350 60 0000 C CNN
+ 1 5150 3350
+ 0 1 -1 0
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 68592B24
+P 6950 3600
+F 0 "#PWR02" H 6950 3350 50 0001 C CNN
+F 1 "eSim_GND" H 6950 3450 50 0000 C CNN
+F 2 "" H 6950 3600 50 0001 C CNN
+F 3 "" H 6950 3600 50 0001 C CNN
+ 1 6950 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v3
+U 1 1 68592BA8
+P 7000 2700
+F 0 "v3" H 6800 2800 60 0000 C CNN
+F 1 "DC" H 6800 2650 60 0000 C CNN
+F 2 "R1" H 6700 2700 60 0000 C CNN
+F 3 "" H 7000 2700 60 0000 C CNN
+ 1 7000 2700
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 68592C20
+P 7150 2250
+F 0 "#PWR03" H 7150 2000 50 0001 C CNN
+F 1 "eSim_GND" H 7150 2100 50 0000 C CNN
+F 2 "" H 7150 2250 50 0001 C CNN
+F 3 "" H 7150 2250 50 0001 C CNN
+ 1 7150 2250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3900 4850 4150 4850
+Wire Wire Line
+ 5150 2900 5150 3200
+Wire Wire Line
+ 4650 3100 5450 3100
+Connection ~ 5150 3100
+Wire Wire Line
+ 5150 3500 5150 3950
+Wire Wire Line
+ 5150 3950 6750 3950
+Wire Wire Line
+ 6750 3600 6750 4200
+Wire Wire Line
+ 6600 3600 6950 3600
+Connection ~ 6750 3600
+Wire Wire Line
+ 6600 3150 7000 3150
+Wire Wire Line
+ 7000 2250 7150 2250
+Wire Wire Line
+ 5150 2600 6700 2600
+Wire Wire Line
+ 6700 1900 6700 3150
+Connection ~ 6700 3150
+$Comp
+L sine v2
+U 1 1 68592D40
+P 4650 3550
+F 0 "v2" H 4450 3650 60 0000 C CNN
+F 1 "sine" H 4450 3500 60 0000 C CNN
+F 2 "R1" H 4350 3550 60 0000 C CNN
+F 3 "" H 4650 3550 60 0000 C CNN
+ 1 4650 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 68592DC9
+P 5400 2700
+F 0 "U4" H 5400 3200 60 0000 C CNN
+F 1 "plot_v1" H 5600 3050 60 0000 C CNN
+F 2 "" H 5400 2700 60 0000 C CNN
+F 3 "" H 5400 2700 60 0000 C CNN
+ 1 5400 2700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5400 2500 5400 3100
+Connection ~ 5400 3100
+Wire Wire Line
+ 5350 3000 5400 3000
+Connection ~ 5400 3000
+$Comp
+L eSim_Diode D1
+U 1 1 68592F9A
+P 4150 2800
+F 0 "D1" H 4150 2900 50 0000 C CNN
+F 1 "eSim_Diode" H 4150 2700 50 0000 C CNN
+F 2 "" H 4150 2800 60 0000 C CNN
+F 3 "" H 4150 2800 60 0000 C CNN
+ 1 4150 2800
+ 0 1 -1 0
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 68592FA0
+P 4150 3400
+F 0 "D2" H 4150 3500 50 0000 C CNN
+F 1 "eSim_Diode" H 4150 3300 50 0000 C CNN
+F 2 "" H 4150 3400 60 0000 C CNN
+F 3 "" H 4150 3400 60 0000 C CNN
+ 1 4150 3400
+ 0 1 -1 0
+$EndComp
+Wire Wire Line
+ 4150 2950 4150 3250
+Wire Wire Line
+ 4150 3550 4150 4200
+Wire Wire Line
+ 4150 4200 6750 4200
+Connection ~ 6750 3950
+Wire Wire Line
+ 4150 2650 4150 1900
+Wire Wire Line
+ 4150 1900 6700 1900
+Connection ~ 6700 2600
+$Comp
+L eSim_GND #PWR04
+U 1 1 68593ACF
+P 4650 4100
+F 0 "#PWR04" H 4650 3850 50 0001 C CNN
+F 1 "eSim_GND" H 4650 3950 50 0000 C CNN
+F 2 "" H 4650 4100 50 0001 C CNN
+F 3 "" H 4650 4100 50 0001 C CNN
+ 1 4650 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4650 4000 4650 4100
+Wire Wire Line
+ 5450 3650 4900 3650
+Wire Wire Line
+ 4900 3650 4900 3050
+Wire Wire Line
+ 4900 3050 3700 3050
+Connection ~ 4150 3050
+$Comp
+L plot_v1 U1
+U 1 1 68594041
+P 3700 3250
+F 0 "U1" H 3700 3750 60 0000 C CNN
+F 1 "plot_v1" H 3900 3600 60 0000 C CNN
+F 2 "" H 3700 3250 60 0000 C CNN
+F 3 "" H 3700 3250 60 0000 C CNN
+ 1 3700 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3750 3200 3850 3200
+Wire Wire Line
+ 3850 3200 3850 3050
+Connection ~ 3850 3050
+Wire Wire Line
+ 5350 4900 5350 3300
+Wire Wire Line
+ 5350 3300 5450 3300
+Wire Wire Line
+ 3950 4900 4200 4900
+Wire Wire Line
+ 3950 5800 3950 5900
+Wire Wire Line
+ 4150 4800 4150 4900
+Connection ~ 4150 4900
+Connection ~ 4150 4850
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest_Previous_Values.xml b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest_Previous_Values.xml
new file mode 100644
index 000000000..6806df558
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/MC14016B_onetest_Previous_Values.xml
@@ -0,0 +1 @@
+dc5sine051k0pulse0500.1n0.1n1m2madc_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\SubcircuitLibrary\MC14016BtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes0110msusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14016B_One/NMOS-5um.lib b/library/SubcircuitLibrary/MC14016B_One/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/MC14016B_One/PMOS-5um.lib b/library/SubcircuitLibrary/MC14016B_One/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/MC14016B_One/analysis b/library/SubcircuitLibrary/MC14016B_One/analysis
new file mode 100644
index 000000000..b21a9e13b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14016B_One/analysis
@@ -0,0 +1 @@
+.tran 1e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B-cache.lib b/library/SubcircuitLibrary/MC14076B/MC14076B-cache.lib
new file mode 100644
index 000000000..8b4e4048e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B-cache.lib
@@ -0,0 +1,143 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_flip
+#
+DEF d_flip U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "d_flip" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1500 0 1 0 N
+X d0 1 2150 1900 200 R 50 50 1 1 I
+X clk0 2 2150 1800 200 R 50 50 1 1 I
+X rst_n0 3 2150 1700 200 R 50 50 1 1 I
+X q0 4 3550 1900 200 L 50 50 1 1 O
+X q_bar0 5 3550 1800 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# tristate_inverter
+#
+DEF tristate_inverter U 0 40 Y Y 1 F N
+F0 "U" 2850 1800 60 H V C CNN
+F1 "tristate_inverter" 2850 2000 60 H V C CNN
+F2 "" 2850 1950 60 H V C CNN
+F3 "" 2850 1950 60 H V C CNN
+DRAW
+S 2350 2100 3350 1600 0 1 0 N
+X a0 1 2150 1900 200 R 50 50 1 1 I
+X en0 2 2150 1800 200 R 50 50 1 1 I
+X y0 3 3550 1900 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.cir b/library/SubcircuitLibrary/MC14076B/MC14076B.cir
new file mode 100644
index 000000000..b50d521a1
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.cir
@@ -0,0 +1,37 @@
+* C:\Users\pavithra\eSim-Workspace\MC14076B\MC14076B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/20/25 15:45:00
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7 Net-_U19-Pad3_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U11-Pad1_ Net-_U24-Pad2_ d_flip
+U19 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U19-Pad3_ d_or
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and
+U5 Net-_U12-Pad2_ Net-_U11-Pad2_ d_inverter
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U12-Pad2_ d_nand
+U8 Net-_U20-Pad3_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U13-Pad1_ Net-_U23-Pad2_ d_flip
+U20 Net-_U13-Pad3_ Net-_U14-Pad3_ Net-_U20-Pad3_ d_or
+U13 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and
+U14 Net-_U14-Pad1_ Net-_U12-Pad2_ Net-_U14-Pad3_ d_and
+U9 Net-_U21-Pad3_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U15-Pad1_ Net-_U25-Pad2_ d_flip
+U21 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U21-Pad3_ d_or
+U15 Net-_U15-Pad1_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_and
+U16 Net-_U16-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad3_ d_and
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U10-Pad5_ d_flip
+U22 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U10-Pad1_ d_or
+U17 Net-_U10-Pad4_ Net-_U11-Pad2_ Net-_U17-Pad3_ d_and
+U18 Net-_U18-Pad1_ Net-_U12-Pad2_ Net-_U18-Pad3_ d_and
+U3 Net-_U27-Pad7_ Net-_U10-Pad2_ d_inverter
+U4 Net-_U27-Pad15_ Net-_U10-Pad3_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_nand
+U6 Net-_U1-Pad3_ Net-_U23-Pad1_ d_inverter
+U24 Net-_U23-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ tristate_inverter
+U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U23-Pad3_ tristate_inverter
+U25 Net-_U23-Pad1_ Net-_U25-Pad2_ Net-_U25-Pad3_ tristate_inverter
+U26 Net-_U23-Pad1_ Net-_U10-Pad5_ Net-_U26-Pad3_ tristate_inverter
+U27 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U24-Pad3_ Net-_U23-Pad3_ Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U27-Pad7_ ? Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U18-Pad1_ Net-_U16-Pad1_ Net-_U14-Pad1_ Net-_U12-Pad1_ Net-_U27-Pad15_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.cir.out b/library/SubcircuitLibrary/MC14076B/MC14076B.cir.out
new file mode 100644
index 000000000..6eff3fe40
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.cir.out
@@ -0,0 +1,116 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc14076b\mc14076b.cir
+
+* u19 net-_u11-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_or
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u5 net-_u12-pad2_ net-_u11-pad2_ d_inverter
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u12-pad2_ d_nand
+* u20 net-_u13-pad3_ net-_u14-pad3_ net-_u20-pad3_ d_or
+* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and
+* u14 net-_u14-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_and
+* u21 net-_u15-pad3_ net-_u16-pad3_ net-_u21-pad3_ d_or
+* u15 net-_u15-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and
+* u16 net-_u16-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and
+* u22 net-_u17-pad3_ net-_u18-pad3_ net-_u10-pad1_ d_or
+* u17 net-_u10-pad4_ net-_u11-pad2_ net-_u17-pad3_ d_and
+* u18 net-_u18-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_and
+* u3 net-_u27-pad7_ net-_u10-pad2_ d_inverter
+* u4 net-_u27-pad15_ net-_u10-pad3_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_nand
+* u6 net-_u1-pad3_ net-_u23-pad1_ d_inverter
+* u24 net-_u23-pad1_ net-_u24-pad2_ net-_u24-pad3_ tristate_inverter
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ tristate_inverter
+* u25 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ tristate_inverter
+* u26 net-_u23-pad1_ net-_u10-pad5_ net-_u26-pad3_ tristate_inverter
+* u27 net-_u1-pad1_ net-_u1-pad2_ net-_u24-pad3_ net-_u23-pad3_ net-_u25-pad3_ net-_u26-pad3_ net-_u27-pad7_ ? net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ net-_u16-pad1_ net-_u14-pad1_ net-_u12-pad1_ net-_u27-pad15_ ? port
+* u7 net-_u19-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u11-pad1_ net-_u24-pad2_ d_flip
+* u8 net-_u20-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u13-pad1_ net-_u23-pad2_ d_flip
+* u9 net-_u21-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u15-pad1_ net-_u25-pad2_ d_flip
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ d_flip
+a1 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19
+a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a4 net-_u12-pad2_ net-_u11-pad2_ u5
+a5 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u12-pad2_ u2
+a6 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u20-pad3_ u20
+a7 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13
+a8 [net-_u14-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14
+a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u21-pad3_ u21
+a10 [net-_u15-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15
+a11 [net-_u16-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16
+a12 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u10-pad1_ u22
+a13 [net-_u10-pad4_ net-_u11-pad2_ ] net-_u17-pad3_ u17
+a14 [net-_u18-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18
+a15 net-_u27-pad7_ net-_u10-pad2_ u3
+a16 net-_u27-pad15_ net-_u10-pad3_ u4
+a17 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a18 net-_u1-pad3_ net-_u23-pad1_ u6
+a19 [net-_u23-pad1_ ] [net-_u24-pad2_ ] [net-_u24-pad3_ ] u24
+a20 [net-_u23-pad1_ ] [net-_u23-pad2_ ] [net-_u23-pad3_ ] u23
+a21 [net-_u23-pad1_ ] [net-_u25-pad2_ ] [net-_u25-pad3_ ] u25
+a22 [net-_u23-pad1_ ] [net-_u10-pad5_ ] [net-_u26-pad3_ ] u26
+a23 [net-_u19-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u11-pad1_ ] [net-_u24-pad2_ ] u7
+a24 [net-_u20-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u13-pad1_ ] [net-_u23-pad2_ ] u8
+a25 [net-_u21-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u15-pad1_ ] [net-_u25-pad2_ ] u9
+a26 [net-_u10-pad1_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u10-pad4_ ] [net-_u10-pad5_ ] u10
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u1 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: tristate_inverter, NgSpice Name: tristate_inverter
+.model u24 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: tristate_inverter, NgSpice Name: tristate_inverter
+.model u23 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: tristate_inverter, NgSpice Name: tristate_inverter
+.model u25 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: tristate_inverter, NgSpice Name: tristate_inverter
+.model u26 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_flip, NgSpice Name: d_flip
+.model u7 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_flip, NgSpice Name: d_flip
+.model u8 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_flip, NgSpice Name: d_flip
+.model u9 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_flip, NgSpice Name: d_flip
+.model u10 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.pro b/library/SubcircuitLibrary/MC14076B/MC14076B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.proj b/library/SubcircuitLibrary/MC14076B/MC14076B.proj
new file mode 100644
index 000000000..19428788d
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.proj
@@ -0,0 +1 @@
+schematicFile MC14076B.sch
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.sch b/library/SubcircuitLibrary/MC14076B/MC14076B.sch
new file mode 100644
index 000000000..a40dff83f
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.sch
@@ -0,0 +1,701 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_flip U7
+U 1 1 6854FB03
+P 8800 8200
+F 0 "U7" H 11650 10000 60 0000 C CNN
+F 1 "d_flip" H 11650 10200 60 0000 C CNN
+F 2 "" H 11650 10150 60 0000 C CNN
+F 3 "" H 11650 10150 60 0000 C CNN
+ 1 8800 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U19
+U 1 1 6854FBB3
+P 10350 6350
+F 0 "U19" H 10350 6350 60 0000 C CNN
+F 1 "d_or" H 10350 6450 60 0000 C CNN
+F 2 "" H 10350 6350 60 0000 C CNN
+F 3 "" H 10350 6350 60 0000 C CNN
+ 1 10350 6350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U11
+U 1 1 6854FC08
+P 9300 6150
+F 0 "U11" H 9300 6150 60 0000 C CNN
+F 1 "d_and" H 9350 6250 60 0000 C CNN
+F 2 "" H 9300 6150 60 0000 C CNN
+F 3 "" H 9300 6150 60 0000 C CNN
+ 1 9300 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 6854FC36
+P 9300 6550
+F 0 "U12" H 9300 6550 60 0000 C CNN
+F 1 "d_and" H 9350 6650 60 0000 C CNN
+F 2 "" H 9300 6550 60 0000 C CNN
+F 3 "" H 9300 6550 60 0000 C CNN
+ 1 9300 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 6854FC8B
+P 8300 7250
+F 0 "U5" H 8300 7150 60 0000 C CNN
+F 1 "d_inverter" H 8300 7400 60 0000 C CNN
+F 2 "" H 8350 7200 60 0000 C CNN
+F 3 "" H 8350 7200 60 0000 C CNN
+ 1 8300 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U2
+U 1 1 6854FE40
+P 7350 7300
+F 0 "U2" H 7350 7300 60 0000 C CNN
+F 1 "d_nand" H 7400 7400 60 0000 C CNN
+F 2 "" H 7350 7300 60 0000 C CNN
+F 3 "" H 7350 7300 60 0000 C CNN
+ 1 7350 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_flip U8
+U 1 1 685501A9
+P 8850 10100
+F 0 "U8" H 11700 11900 60 0000 C CNN
+F 1 "d_flip" H 11700 12100 60 0000 C CNN
+F 2 "" H 11700 12050 60 0000 C CNN
+F 3 "" H 11700 12050 60 0000 C CNN
+ 1 8850 10100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U20
+U 1 1 685501AF
+P 10400 8250
+F 0 "U20" H 10400 8250 60 0000 C CNN
+F 1 "d_or" H 10400 8350 60 0000 C CNN
+F 2 "" H 10400 8250 60 0000 C CNN
+F 3 "" H 10400 8250 60 0000 C CNN
+ 1 10400 8250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 685501B5
+P 9350 8050
+F 0 "U13" H 9350 8050 60 0000 C CNN
+F 1 "d_and" H 9400 8150 60 0000 C CNN
+F 2 "" H 9350 8050 60 0000 C CNN
+F 3 "" H 9350 8050 60 0000 C CNN
+ 1 9350 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 685501BB
+P 9350 8450
+F 0 "U14" H 9350 8450 60 0000 C CNN
+F 1 "d_and" H 9400 8550 60 0000 C CNN
+F 2 "" H 9350 8450 60 0000 C CNN
+F 3 "" H 9350 8450 60 0000 C CNN
+ 1 9350 8450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_flip U9
+U 1 1 68550998
+P 8900 11350
+F 0 "U9" H 11750 13150 60 0000 C CNN
+F 1 "d_flip" H 11750 13350 60 0000 C CNN
+F 2 "" H 11750 13300 60 0000 C CNN
+F 3 "" H 11750 13300 60 0000 C CNN
+ 1 8900 11350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U21
+U 1 1 6855099E
+P 10450 9500
+F 0 "U21" H 10450 9500 60 0000 C CNN
+F 1 "d_or" H 10450 9600 60 0000 C CNN
+F 2 "" H 10450 9500 60 0000 C CNN
+F 3 "" H 10450 9500 60 0000 C CNN
+ 1 10450 9500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U15
+U 1 1 685509A4
+P 9400 9300
+F 0 "U15" H 9400 9300 60 0000 C CNN
+F 1 "d_and" H 9450 9400 60 0000 C CNN
+F 2 "" H 9400 9300 60 0000 C CNN
+F 3 "" H 9400 9300 60 0000 C CNN
+ 1 9400 9300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U16
+U 1 1 685509AA
+P 9400 9700
+F 0 "U16" H 9400 9700 60 0000 C CNN
+F 1 "d_and" H 9450 9800 60 0000 C CNN
+F 2 "" H 9400 9700 60 0000 C CNN
+F 3 "" H 9400 9700 60 0000 C CNN
+ 1 9400 9700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_flip U10
+U 1 1 68550E16
+P 8900 12450
+F 0 "U10" H 11750 14250 60 0000 C CNN
+F 1 "d_flip" H 11750 14450 60 0000 C CNN
+F 2 "" H 11750 14400 60 0000 C CNN
+F 3 "" H 11750 14400 60 0000 C CNN
+ 1 8900 12450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U22
+U 1 1 68550E1C
+P 10450 10600
+F 0 "U22" H 10450 10600 60 0000 C CNN
+F 1 "d_or" H 10450 10700 60 0000 C CNN
+F 2 "" H 10450 10600 60 0000 C CNN
+F 3 "" H 10450 10600 60 0000 C CNN
+ 1 10450 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U17
+U 1 1 68550E22
+P 9400 10400
+F 0 "U17" H 9400 10400 60 0000 C CNN
+F 1 "d_and" H 9450 10500 60 0000 C CNN
+F 2 "" H 9400 10400 60 0000 C CNN
+F 3 "" H 9400 10400 60 0000 C CNN
+ 1 9400 10400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U18
+U 1 1 68550E28
+P 9400 10800
+F 0 "U18" H 9400 10800 60 0000 C CNN
+F 1 "d_and" H 9450 10900 60 0000 C CNN
+F 2 "" H 9400 10800 60 0000 C CNN
+F 3 "" H 9400 10800 60 0000 C CNN
+ 1 9400 10800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 68552637
+P 7400 8700
+F 0 "U3" H 7400 8600 60 0000 C CNN
+F 1 "d_inverter" H 7400 8850 60 0000 C CNN
+F 2 "" H 7450 8650 60 0000 C CNN
+F 3 "" H 7450 8650 60 0000 C CNN
+ 1 7400 8700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10800 6300 10950 6300
+Wire Wire Line
+ 9750 6500 9900 6500
+Wire Wire Line
+ 9900 6500 9900 6350
+Wire Wire Line
+ 9750 6100 9900 6100
+Wire Wire Line
+ 9900 6100 9900 6250
+Wire Wire Line
+ 8850 6050 8850 5900
+Wire Wire Line
+ 8850 5900 12350 5900
+Wire Wire Line
+ 12350 5900 12350 6300
+Wire Wire Line
+ 7800 7250 8000 7250
+Wire Wire Line
+ 8850 6550 7900 6550
+Wire Wire Line
+ 7900 6550 7900 10800
+Connection ~ 7900 7250
+Wire Wire Line
+ 10850 8200 11000 8200
+Wire Wire Line
+ 9800 8400 9950 8400
+Wire Wire Line
+ 9950 8400 9950 8250
+Wire Wire Line
+ 9800 8000 9950 8000
+Wire Wire Line
+ 9950 8000 9950 8150
+Wire Wire Line
+ 8900 7950 8900 7800
+Wire Wire Line
+ 8900 7800 12400 7800
+Wire Wire Line
+ 12400 7800 12400 8200
+Wire Wire Line
+ 8650 8050 8900 8050
+Wire Wire Line
+ 8850 6150 8650 6150
+Wire Wire Line
+ 8650 6150 8650 10400
+Wire Wire Line
+ 8600 7250 8650 7250
+Connection ~ 8650 7250
+Wire Wire Line
+ 7900 8450 8900 8450
+Wire Wire Line
+ 10900 9450 11050 9450
+Wire Wire Line
+ 9850 9650 10000 9650
+Wire Wire Line
+ 10000 9650 10000 9500
+Wire Wire Line
+ 9850 9250 10000 9250
+Wire Wire Line
+ 10000 9250 10000 9400
+Wire Wire Line
+ 8950 9200 8950 9050
+Wire Wire Line
+ 8950 9050 12450 9050
+Wire Wire Line
+ 12450 9050 12450 9450
+Wire Wire Line
+ 8650 9300 8950 9300
+Connection ~ 8650 8050
+Wire Wire Line
+ 7900 9700 8950 9700
+Connection ~ 7900 8450
+Wire Wire Line
+ 10900 10550 11050 10550
+Wire Wire Line
+ 9850 10750 10000 10750
+Wire Wire Line
+ 10000 10750 10000 10600
+Wire Wire Line
+ 9850 10350 10000 10350
+Wire Wire Line
+ 10000 10350 10000 10500
+Wire Wire Line
+ 8950 10300 8950 10150
+Wire Wire Line
+ 8950 10150 12450 10150
+Wire Wire Line
+ 12450 10150 12450 10550
+Wire Wire Line
+ 8650 10400 8950 10400
+Connection ~ 8650 9300
+Wire Wire Line
+ 7900 10800 8950 10800
+Connection ~ 7900 9700
+Wire Wire Line
+ 11000 8300 10850 8300
+Wire Wire Line
+ 10850 6400 10850 10650
+Wire Wire Line
+ 10850 9550 11050 9550
+Wire Wire Line
+ 10950 6400 10850 6400
+Connection ~ 10850 8300
+Wire Wire Line
+ 10850 10650 11050 10650
+Connection ~ 10850 9550
+Wire Wire Line
+ 7700 8700 10850 8700
+Connection ~ 10850 8700
+Wire Wire Line
+ 10950 6500 10950 11250
+Wire Wire Line
+ 10950 8400 11000 8400
+Wire Wire Line
+ 10950 9650 11050 9650
+Connection ~ 10950 8400
+Wire Wire Line
+ 10950 10750 11050 10750
+Connection ~ 10950 9650
+$Comp
+L d_inverter U4
+U 1 1 68552F98
+P 7450 11250
+F 0 "U4" H 7450 11150 60 0000 C CNN
+F 1 "d_inverter" H 7450 11400 60 0000 C CNN
+F 2 "" H 7500 11200 60 0000 C CNN
+F 3 "" H 7500 11200 60 0000 C CNN
+ 1 7450 11250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10950 11250 7750 11250
+Connection ~ 10950 10750
+$Comp
+L d_nand U1
+U 1 1 68553906
+P 7350 5400
+F 0 "U1" H 7350 5400 60 0000 C CNN
+F 1 "d_nand" H 7400 5500 60 0000 C CNN
+F 2 "" H 7350 5400 60 0000 C CNN
+F 3 "" H 7350 5400 60 0000 C CNN
+ 1 7350 5400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68553977
+P 8450 5350
+F 0 "U6" H 8450 5250 60 0000 C CNN
+F 1 "d_inverter" H 8450 5500 60 0000 C CNN
+F 2 "" H 8500 5300 60 0000 C CNN
+F 3 "" H 8500 5300 60 0000 C CNN
+ 1 8450 5350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7800 5350 8150 5350
+$Comp
+L tristate_inverter U24
+U 1 1 68553A2E
+P 10550 8200
+F 0 "U24" H 13400 10000 60 0000 C CNN
+F 1 "tristate_inverter" H 13400 10200 60 0000 C CNN
+F 2 "" H 13400 10150 60 0000 C CNN
+F 3 "" H 13400 10150 60 0000 C CNN
+ 1 10550 8200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 12350 6400 12700 6400
+$Comp
+L tristate_inverter U23
+U 1 1 68553ECC
+P 10500 10100
+F 0 "U23" H 13350 11900 60 0000 C CNN
+F 1 "tristate_inverter" H 13350 12100 60 0000 C CNN
+F 2 "" H 13350 12050 60 0000 C CNN
+F 3 "" H 13350 12050 60 0000 C CNN
+ 1 10500 10100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 12400 8300 12650 8300
+$Comp
+L tristate_inverter U25
+U 1 1 685544FF
+P 10550 11350
+F 0 "U25" H 13400 13150 60 0000 C CNN
+F 1 "tristate_inverter" H 13400 13350 60 0000 C CNN
+F 2 "" H 13400 13300 60 0000 C CNN
+F 3 "" H 13400 13300 60 0000 C CNN
+ 1 10550 11350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 12450 9550 12700 9550
+$Comp
+L tristate_inverter U26
+U 1 1 6855461F
+P 10600 12450
+F 0 "U26" H 13450 14250 60 0000 C CNN
+F 1 "tristate_inverter" H 13450 14450 60 0000 C CNN
+F 2 "" H 13450 14400 60 0000 C CNN
+F 3 "" H 13450 14400 60 0000 C CNN
+ 1 10600 12450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 12450 10650 12750 10650
+Wire Wire Line
+ 8750 5350 12550 5350
+Wire Wire Line
+ 12550 5350 12550 10550
+Wire Wire Line
+ 12550 10550 12750 10550
+Wire Wire Line
+ 12700 9450 12550 9450
+Connection ~ 12550 9450
+Wire Wire Line
+ 12650 8200 12550 8200
+Connection ~ 12550 8200
+Wire Wire Line
+ 12700 6300 12550 6300
+Connection ~ 12550 6300
+$Comp
+L PORT U27
+U 2 1 68555B35
+P 6350 5450
+F 0 "U27" H 6400 5550 30 0000 C CNN
+F 1 "PORT" H 6350 5450 30 0000 C CNN
+F 2 "" H 6350 5450 60 0000 C CNN
+F 3 "" H 6350 5450 60 0000 C CNN
+ 2 6350 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 1 1 68555B80
+P 6350 5300
+F 0 "U27" H 6400 5400 30 0000 C CNN
+F 1 "PORT" H 6350 5300 30 0000 C CNN
+F 2 "" H 6350 5300 60 0000 C CNN
+F 3 "" H 6350 5300 60 0000 C CNN
+ 1 6350 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 3 1 68555BCD
+P 14550 6300
+F 0 "U27" H 14600 6400 30 0000 C CNN
+F 1 "PORT" H 14550 6300 30 0000 C CNN
+F 2 "" H 14550 6300 60 0000 C CNN
+F 3 "" H 14550 6300 60 0000 C CNN
+ 3 14550 6300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 4 1 68555C22
+P 14550 8200
+F 0 "U27" H 14600 8300 30 0000 C CNN
+F 1 "PORT" H 14550 8200 30 0000 C CNN
+F 2 "" H 14550 8200 60 0000 C CNN
+F 3 "" H 14550 8200 60 0000 C CNN
+ 4 14550 8200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 5 1 68555C7B
+P 14600 9450
+F 0 "U27" H 14650 9550 30 0000 C CNN
+F 1 "PORT" H 14600 9450 30 0000 C CNN
+F 2 "" H 14600 9450 60 0000 C CNN
+F 3 "" H 14600 9450 60 0000 C CNN
+ 5 14600 9450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 6 1 68555CCE
+P 14650 10550
+F 0 "U27" H 14700 10650 30 0000 C CNN
+F 1 "PORT" H 14650 10550 30 0000 C CNN
+F 2 "" H 14650 10550 60 0000 C CNN
+F 3 "" H 14650 10550 60 0000 C CNN
+ 6 14650 10550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 7 1 68555D2B
+P 6650 8700
+F 0 "U27" H 6700 8800 30 0000 C CNN
+F 1 "PORT" H 6650 8700 30 0000 C CNN
+F 2 "" H 6650 8700 60 0000 C CNN
+F 3 "" H 6650 8700 60 0000 C CNN
+ 7 6650 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 9 1 68555D86
+P 6500 7100
+F 0 "U27" H 6550 7200 30 0000 C CNN
+F 1 "PORT" H 6500 7100 30 0000 C CNN
+F 2 "" H 6500 7100 60 0000 C CNN
+F 3 "" H 6500 7100 60 0000 C CNN
+ 9 6500 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 8 1 68555DE3
+P 14050 4850
+F 0 "U27" H 14100 4950 30 0000 C CNN
+F 1 "PORT" H 14050 4850 30 0000 C CNN
+F 2 "" H 14050 4850 60 0000 C CNN
+F 3 "" H 14050 4850 60 0000 C CNN
+ 8 14050 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 11 1 68555E6C
+P 8500 10700
+F 0 "U27" H 8550 10800 30 0000 C CNN
+F 1 "PORT" H 8500 10700 30 0000 C CNN
+F 2 "" H 8500 10700 60 0000 C CNN
+F 3 "" H 8500 10700 60 0000 C CNN
+ 11 8500 10700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 10 1 68555EED
+P 6500 7400
+F 0 "U27" H 6550 7500 30 0000 C CNN
+F 1 "PORT" H 6500 7400 30 0000 C CNN
+F 2 "" H 6500 7400 60 0000 C CNN
+F 3 "" H 6500 7400 60 0000 C CNN
+ 10 6500 7400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 12 1 68555F60
+P 8250 9600
+F 0 "U27" H 8300 9700 30 0000 C CNN
+F 1 "PORT" H 8250 9600 30 0000 C CNN
+F 2 "" H 8250 9600 60 0000 C CNN
+F 3 "" H 8250 9600 60 0000 C CNN
+ 12 8250 9600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 13 1 68555FC1
+P 8350 8350
+F 0 "U27" H 8400 8450 30 0000 C CNN
+F 1 "PORT" H 8350 8350 30 0000 C CNN
+F 2 "" H 8350 8350 60 0000 C CNN
+F 3 "" H 8350 8350 60 0000 C CNN
+ 13 8350 8350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 14 1 68556028
+P 8300 6450
+F 0 "U27" H 8350 6550 30 0000 C CNN
+F 1 "PORT" H 8300 6450 30 0000 C CNN
+F 2 "" H 8300 6450 60 0000 C CNN
+F 3 "" H 8300 6450 60 0000 C CNN
+ 14 8300 6450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 15 1 6855608F
+P 6700 11250
+F 0 "U27" H 6750 11350 30 0000 C CNN
+F 1 "PORT" H 6700 11250 30 0000 C CNN
+F 2 "" H 6700 11250 60 0000 C CNN
+F 3 "" H 6700 11250 60 0000 C CNN
+ 15 6700 11250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U27
+U 16 1 685560FA
+P 14050 5150
+F 0 "U27" H 14100 5250 30 0000 C CNN
+F 1 "PORT" H 14050 5150 30 0000 C CNN
+F 2 "" H 14050 5150 60 0000 C CNN
+F 3 "" H 14050 5150 60 0000 C CNN
+ 16 14050 5150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6600 5300 6900 5300
+Wire Wire Line
+ 6600 5450 6900 5450
+Wire Wire Line
+ 6900 5450 6900 5400
+Wire Wire Line
+ 14300 6300 14100 6300
+Wire Wire Line
+ 14300 8200 14050 8200
+Wire Wire Line
+ 14100 9450 14350 9450
+Wire Wire Line
+ 14400 10550 14150 10550
+Wire Wire Line
+ 6900 8700 7100 8700
+NoConn ~ 14300 4850
+Wire Wire Line
+ 6750 7100 6900 7100
+Wire Wire Line
+ 6900 7100 6900 7200
+Wire Wire Line
+ 6750 7400 6900 7400
+Wire Wire Line
+ 6900 7400 6900 7300
+Wire Wire Line
+ 8750 10700 8950 10700
+Wire Wire Line
+ 8500 9600 8950 9600
+Wire Wire Line
+ 8600 8350 8900 8350
+Wire Wire Line
+ 8550 6450 8850 6450
+NoConn ~ 14300 5150
+Wire Wire Line
+ 6950 11250 7150 11250
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B.sub b/library/SubcircuitLibrary/MC14076B/MC14076B.sub
new file mode 100644
index 000000000..b4205b4d2
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B.sub
@@ -0,0 +1,110 @@
+* Subcircuit MC14076B
+.subckt MC14076B net-_u1-pad1_ net-_u1-pad2_ net-_u24-pad3_ net-_u23-pad3_ net-_u25-pad3_ net-_u26-pad3_ net-_u27-pad7_ ? net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ net-_u16-pad1_ net-_u14-pad1_ net-_u12-pad1_ net-_u27-pad15_ ?
+* c:\fossee\esim\library\subcircuitlibrary\mc14076b\mc14076b.cir
+* u19 net-_u11-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_or
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u5 net-_u12-pad2_ net-_u11-pad2_ d_inverter
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u12-pad2_ d_nand
+* u20 net-_u13-pad3_ net-_u14-pad3_ net-_u20-pad3_ d_or
+* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and
+* u14 net-_u14-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_and
+* u21 net-_u15-pad3_ net-_u16-pad3_ net-_u21-pad3_ d_or
+* u15 net-_u15-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and
+* u16 net-_u16-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and
+* u22 net-_u17-pad3_ net-_u18-pad3_ net-_u10-pad1_ d_or
+* u17 net-_u10-pad4_ net-_u11-pad2_ net-_u17-pad3_ d_and
+* u18 net-_u18-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_and
+* u3 net-_u27-pad7_ net-_u10-pad2_ d_inverter
+* u4 net-_u27-pad15_ net-_u10-pad3_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_nand
+* u6 net-_u1-pad3_ net-_u23-pad1_ d_inverter
+* u24 net-_u23-pad1_ net-_u24-pad2_ net-_u24-pad3_ tristate_inverter
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ tristate_inverter
+* u25 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ tristate_inverter
+* u26 net-_u23-pad1_ net-_u10-pad5_ net-_u26-pad3_ tristate_inverter
+* u7 net-_u19-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u11-pad1_ net-_u24-pad2_ d_flip
+* u8 net-_u20-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u13-pad1_ net-_u23-pad2_ d_flip
+* u9 net-_u21-pad3_ net-_u10-pad2_ net-_u10-pad3_ net-_u15-pad1_ net-_u25-pad2_ d_flip
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ d_flip
+a1 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19
+a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a3 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a4 net-_u12-pad2_ net-_u11-pad2_ u5
+a5 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u12-pad2_ u2
+a6 [net-_u13-pad3_ net-_u14-pad3_ ] net-_u20-pad3_ u20
+a7 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13
+a8 [net-_u14-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14
+a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u21-pad3_ u21
+a10 [net-_u15-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15
+a11 [net-_u16-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16
+a12 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u10-pad1_ u22
+a13 [net-_u10-pad4_ net-_u11-pad2_ ] net-_u17-pad3_ u17
+a14 [net-_u18-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18
+a15 net-_u27-pad7_ net-_u10-pad2_ u3
+a16 net-_u27-pad15_ net-_u10-pad3_ u4
+a17 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a18 net-_u1-pad3_ net-_u23-pad1_ u6
+a19 [net-_u23-pad1_ ] [net-_u24-pad2_ ] [net-_u24-pad3_ ] u24
+a20 [net-_u23-pad1_ ] [net-_u23-pad2_ ] [net-_u23-pad3_ ] u23
+a21 [net-_u23-pad1_ ] [net-_u25-pad2_ ] [net-_u25-pad3_ ] u25
+a22 [net-_u23-pad1_ ] [net-_u10-pad5_ ] [net-_u26-pad3_ ] u26
+a23 [net-_u19-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u11-pad1_ ] [net-_u24-pad2_ ] u7
+a24 [net-_u20-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u13-pad1_ ] [net-_u23-pad2_ ] u8
+a25 [net-_u21-pad3_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u15-pad1_ ] [net-_u25-pad2_ ] u9
+a26 [net-_u10-pad1_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] [net-_u10-pad4_ ] [net-_u10-pad5_ ] u10
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u1 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: tristate_inverter, NgSpice Name: tristate_inverter
+.model u24 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: tristate_inverter, NgSpice Name: tristate_inverter
+.model u23 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: tristate_inverter, NgSpice Name: tristate_inverter
+.model u25 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: tristate_inverter, NgSpice Name: tristate_inverter
+.model u26 tristate_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_flip, NgSpice Name: d_flip
+.model u7 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_flip, NgSpice Name: d_flip
+.model u8 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_flip, NgSpice Name: d_flip
+.model u9 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Schematic Name: d_flip, NgSpice Name: d_flip
+.model u10 d_flip(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 )
+* Control Statements
+
+.ends MC14076B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_Previous_Values.xml b/library/SubcircuitLibrary/MC14076B/MC14076B_Previous_Values.xml
new file mode 100644
index 000000000..dd87de853
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_Previous_Values.xml
@@ -0,0 +1 @@
+d_flipd_ord_andd_andd_inverterd_nandd_flipd_ord_andd_andd_flipd_ord_andd_andd_flipd_ord_andd_andd_inverterd_inverterd_nandd_invertertristate_invertertristate_invertertristate_invertertristate_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test-cache.lib b/library/SubcircuitLibrary/MC14076B/MC14076B_test-cache.lib
new file mode 100644
index 000000000..4098fce1e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test-cache.lib
@@ -0,0 +1,170 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# MC14076B
+#
+DEF MC14076B X 0 40 Y Y 1 F N
+F0 "X" 0 -950 60 H V C CNN
+F1 "MC14076B" 50 850 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -450 750 450 -750 0 1 0 N
+X A 1 -650 650 200 R 50 50 1 1 I
+X B 2 -650 500 200 R 50 50 1 1 I
+X Q0 3 -650 300 200 R 50 50 1 1 O
+X Q1 4 -650 100 200 R 50 50 1 1 O
+X Q2 5 -650 -100 200 R 50 50 1 1 O
+X Q3 6 -650 -300 200 R 50 50 1 1 O
+X C 7 -650 -500 200 R 50 50 1 1 I
+X VSS 8 -650 -700 200 R 50 50 1 1 I
+X A 9 650 -700 200 L 50 50 1 1 I
+X B 10 650 -500 200 L 50 50 1 1 I
+X D3 11 650 -300 200 L 50 50 1 1 I
+X D2 12 650 -100 200 L 50 50 1 1 I
+X D1 13 650 100 200 L 50 50 1 1 I
+X D0 14 650 300 200 L 50 50 1 1 I
+X R 15 650 500 200 L 50 50 1 1 I
+X VDD 16 650 650 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_2
+#
+DEF adc_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_2" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -100 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT2 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_5
+#
+DEF adc_bridge_5 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_5" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -400 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X OUT1 6 550 50 200 L 50 50 1 1 O
+X OUT2 7 550 -50 200 L 50 50 1 1 O
+X OUT3 8 550 -150 200 L 50 50 1 1 O
+X OUT4 9 550 -250 200 L 50 50 1 1 O
+X OUT5 10 550 -350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_4
+#
+DEF dac_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir b/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir
new file mode 100644
index 000000000..3c5fe27e7
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir
@@ -0,0 +1,38 @@
+* C:\Users\pavithra\eSim-Workspace\MC14076B_test\MC14076B_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/20/25 17:49:07
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ Net-_U6-Pad4_ adc_bridge_2
+v1 Net-_U6-Pad1_ GND DC
+v3 Net-_U6-Pad2_ GND DC
+U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U8-Pad3_ Net-_U8-Pad4_ W X Y Z dac_bridge_4
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ adc_bridge_2
+v6 Net-_U10-Pad1_ GND DC
+v5 Net-_U10-Pad2_ GND DC
+U11 RST A B C D Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ Net-_U11-Pad9_ Net-_U11-Pad10_ adc_bridge_5
+v7 D GND pulse
+v8 C GND pulse
+v9 B GND pulse
+v10 A GND pulse
+v11 RST GND pulse
+U9 Net-_U9-Pad1_ Net-_U9-Pad2_ adc_bridge_1
+v4 Net-_U9-Pad1_ GND DC
+U4 W plot_v1
+U2 X plot_v1
+U1 Y plot_v1
+U3 Z plot_v1
+U7 CLK Net-_U7-Pad2_ adc_bridge_1
+v2 CLK GND pulse
+U5 CLK plot_v1
+U12 RST plot_v1
+U13 A plot_v1
+U14 B plot_v1
+U15 C plot_v1
+U16 D plot_v1
+X1 Net-_U6-Pad3_ Net-_U6-Pad4_ Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U8-Pad3_ Net-_U8-Pad4_ Net-_U7-Pad2_ GND Net-_U10-Pad4_ Net-_U10-Pad3_ Net-_U11-Pad10_ Net-_U11-Pad9_ Net-_U11-Pad8_ Net-_U11-Pad7_ Net-_U11-Pad6_ Net-_U9-Pad2_ MC14076B
+
+.end
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir.out b/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir.out
new file mode 100644
index 000000000..14aa58df3
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.cir.out
@@ -0,0 +1,59 @@
+* c:\users\pavithra\esim-workspace\mc14076b_test\mc14076b_test.cir
+
+.include MC14076B.sub
+* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ adc_bridge_2
+v1 net-_u6-pad1_ gnd dc 0
+v3 net-_u6-pad2_ gnd dc 0
+* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ net-_u8-pad4_ w x y z dac_bridge_4
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ adc_bridge_2
+v6 net-_u10-pad1_ gnd dc 0
+v5 net-_u10-pad2_ gnd dc 0
+* u11 rst a b c d net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ adc_bridge_5
+v7 d gnd pulse(0 5 50n 0.1n 0.1n 1m 9m)
+v8 c gnd pulse(5 0 50n 0.1n 0.1n 2m 8m)
+v9 b gnd pulse(0 5 50n 0.1n 0.1n 1m 9m)
+v10 a gnd pulse(5 80n 2m 0.1n 0.1n 2m 8m)
+v11 rst gnd pulse(0 5 0 0.1n 0.1n 4m 9m)
+* u9 net-_u9-pad1_ net-_u9-pad2_ adc_bridge_1
+v4 net-_u9-pad1_ gnd dc 9
+* u4 w plot_v1
+* u2 x plot_v1
+* u1 y plot_v1
+* u3 z plot_v1
+* u7 clk net-_u7-pad2_ adc_bridge_1
+v2 clk gnd pulse(0 5 0 0.1n 0.1n 1m 2m)
+* u5 clk plot_v1
+* u12 rst plot_v1
+* u13 a plot_v1
+* u14 b plot_v1
+* u15 c plot_v1
+* u16 d plot_v1
+x1 net-_u6-pad3_ net-_u6-pad4_ net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ net-_u8-pad4_ net-_u7-pad2_ gnd net-_u10-pad4_ net-_u10-pad3_ net-_u11-pad10_ net-_u11-pad9_ net-_u11-pad8_ net-_u11-pad7_ net-_u11-pad6_ net-_u9-pad2_ MC14076B
+a1 [net-_u6-pad1_ net-_u6-pad2_ ] [net-_u6-pad3_ net-_u6-pad4_ ] u6
+a2 [net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ net-_u8-pad4_ ] [w x y z ] u8
+a3 [net-_u10-pad1_ net-_u10-pad2_ ] [net-_u10-pad3_ net-_u10-pad4_ ] u10
+a4 [rst a b c d ] [net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ net-_u11-pad9_ net-_u11-pad10_ ] u11
+a5 [net-_u9-pad1_ ] [net-_u9-pad2_ ] u9
+a6 [clk ] [net-_u7-pad2_ ] u7
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u6 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge
+.model u8 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge
+.model u10 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_5, NgSpice Name: adc_bridge
+.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u7 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 1e-06 10e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(w)+10v(x)+20 v(y)+30 v(z)+40v(clk)+50 v(rst)+60 v(a)+70 v(b)+80v(c)+90v(d)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.pro b/library/SubcircuitLibrary/MC14076B/MC14076B_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.proj b/library/SubcircuitLibrary/MC14076B/MC14076B_test.proj
new file mode 100644
index 000000000..78243dfc0
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.proj
@@ -0,0 +1 @@
+schematicFile MC14076B_test.sch
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test.sch b/library/SubcircuitLibrary/MC14076B/MC14076B_test.sch
new file mode 100644
index 000000000..f70383c66
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test.sch
@@ -0,0 +1,732 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC14076B_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L adc_bridge_2 U6
+U 1 1 685538BE
+P 5000 3800
+F 0 "U6" H 5000 3800 60 0000 C CNN
+F 1 "adc_bridge_2" H 5000 3950 60 0000 C CNN
+F 2 "" H 5000 3800 60 0000 C CNN
+F 3 "" H 5000 3800 60 0000 C CNN
+ 1 5000 3800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 3750 6350 3750
+Wire Wire Line
+ 6350 3750 6350 3700
+Wire Wire Line
+ 5550 3850 6350 3850
+$Comp
+L DC v1
+U 1 1 685538EF
+P 3850 4200
+F 0 "v1" H 3650 4300 60 0000 C CNN
+F 1 "DC" H 3650 4150 60 0000 C CNN
+F 2 "R1" H 3550 4200 60 0000 C CNN
+F 3 "" H 3850 4200 60 0000 C CNN
+ 1 3850 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L DC v3
+U 1 1 68553927
+P 4200 4300
+F 0 "v3" H 4000 4400 60 0000 C CNN
+F 1 "DC" H 4000 4250 60 0000 C CNN
+F 2 "R1" H 3900 4300 60 0000 C CNN
+F 3 "" H 4200 4300 60 0000 C CNN
+ 1 4200 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3850 3750 4400 3750
+Wire Wire Line
+ 4200 3850 4400 3850
+$Comp
+L eSim_GND #PWR01
+U 1 1 6855396C
+P 4200 4900
+F 0 "#PWR01" H 4200 4650 50 0001 C CNN
+F 1 "eSim_GND" H 4200 4750 50 0000 C CNN
+F 2 "" H 4200 4900 50 0001 C CNN
+F 3 "" H 4200 4900 50 0001 C CNN
+ 1 4200 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 6855398A
+P 3850 4750
+F 0 "#PWR02" H 3850 4500 50 0001 C CNN
+F 1 "eSim_GND" H 3850 4600 50 0000 C CNN
+F 2 "" H 3850 4750 50 0001 C CNN
+F 3 "" H 3850 4750 50 0001 C CNN
+ 1 3850 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 685539A1
+P 6200 5050
+F 0 "#PWR03" H 6200 4800 50 0001 C CNN
+F 1 "eSim_GND" H 6200 4900 50 0000 C CNN
+F 2 "" H 6200 5050 50 0001 C CNN
+F 3 "" H 6200 5050 50 0001 C CNN
+ 1 6200 5050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6200 5050 6350 5050
+Wire Wire Line
+ 4200 4750 4200 4900
+Wire Wire Line
+ 3850 4650 3850 4750
+$Comp
+L dac_bridge_4 U8
+U 1 1 685539E0
+P 5650 4450
+F 0 "U8" H 5650 4450 60 0000 C CNN
+F 1 "dac_bridge_4" H 5650 4750 60 0000 C CNN
+F 2 "" H 5650 4450 60 0000 C CNN
+F 3 "" H 5650 4450 60 0000 C CNN
+ 1 5650 4450
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6200 4250 6200 4050
+Wire Wire Line
+ 6200 4050 6350 4050
+Wire Wire Line
+ 6200 4350 6350 4350
+Wire Wire Line
+ 6350 4350 6350 4250
+Wire Wire Line
+ 6200 4450 6350 4450
+Wire Wire Line
+ 6200 4550 6350 4550
+Wire Wire Line
+ 6350 4550 6350 4650
+$Comp
+L adc_bridge_2 U10
+U 1 1 68553AD2
+P 8400 4950
+F 0 "U10" H 8400 4950 60 0000 C CNN
+F 1 "adc_bridge_2" H 8400 5100 60 0000 C CNN
+F 2 "" H 8400 4950 60 0000 C CNN
+F 3 "" H 8400 4950 60 0000 C CNN
+ 1 8400 4950
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7650 4850 7850 4850
+Wire Wire Line
+ 7850 4850 7850 4900
+Wire Wire Line
+ 7650 5050 7850 5050
+Wire Wire Line
+ 7850 5050 7850 5000
+$Comp
+L DC v6
+U 1 1 68553BA2
+P 9600 5350
+F 0 "v6" H 9400 5450 60 0000 C CNN
+F 1 "DC" H 9400 5300 60 0000 C CNN
+F 2 "R1" H 9300 5350 60 0000 C CNN
+F 3 "" H 9600 5350 60 0000 C CNN
+ 1 9600 5350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9000 4900 9600 4900
+$Comp
+L DC v5
+U 1 1 68553C76
+P 9150 5450
+F 0 "v5" H 8950 5550 60 0000 C CNN
+F 1 "DC" H 8950 5400 60 0000 C CNN
+F 2 "R1" H 8850 5450 60 0000 C CNN
+F 3 "" H 9150 5450 60 0000 C CNN
+ 1 9150 5450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9000 5000 9150 5000
+$Comp
+L eSim_GND #PWR04
+U 1 1 68553D86
+P 9150 6050
+F 0 "#PWR04" H 9150 5800 50 0001 C CNN
+F 1 "eSim_GND" H 9150 5900 50 0000 C CNN
+F 2 "" H 9150 6050 50 0001 C CNN
+F 3 "" H 9150 6050 50 0001 C CNN
+ 1 9150 6050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR05
+U 1 1 68554020
+P 9600 5950
+F 0 "#PWR05" H 9600 5700 50 0001 C CNN
+F 1 "eSim_GND" H 9600 5800 50 0000 C CNN
+F 2 "" H 9600 5950 50 0001 C CNN
+F 3 "" H 9600 5950 50 0001 C CNN
+ 1 9600 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_5 U11
+U 1 1 685543EE
+P 8550 4200
+F 0 "U11" H 8550 4200 60 0000 C CNN
+F 1 "adc_bridge_5" H 8550 4350 60 0000 C CNN
+F 2 "" H 8550 4200 60 0000 C CNN
+F 3 "" H 8550 4200 60 0000 C CNN
+ 1 8550 4200
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8000 4550 7850 4550
+Wire Wire Line
+ 7850 4550 7850 4650
+Wire Wire Line
+ 7850 4650 7650 4650
+Wire Wire Line
+ 7650 4450 8000 4450
+Wire Wire Line
+ 7650 4250 7750 4250
+Wire Wire Line
+ 7750 4250 7750 4350
+Wire Wire Line
+ 7750 4350 8000 4350
+Wire Wire Line
+ 8000 4250 7800 4250
+Wire Wire Line
+ 7800 4250 7800 4050
+Wire Wire Line
+ 7800 4050 7650 4050
+Wire Wire Line
+ 7650 3850 8000 3850
+Wire Wire Line
+ 8000 3850 8000 4150
+$Comp
+L pulse v7
+U 1 1 685548CF
+P 9400 6850
+F 0 "v7" H 9200 6950 60 0000 C CNN
+F 1 "pulse" H 9200 6800 60 0000 C CNN
+F 2 "R1" H 9100 6850 60 0000 C CNN
+F 3 "" H 9400 6850 60 0000 C CNN
+ 1 9400 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L pulse v8
+U 1 1 68554963
+P 9900 4950
+F 0 "v8" H 9700 5050 60 0000 C CNN
+F 1 "pulse" H 9700 4900 60 0000 C CNN
+F 2 "R1" H 9600 4950 60 0000 C CNN
+F 3 "" H 9900 4950 60 0000 C CNN
+ 1 9900 4950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9150 4450 9900 4450
+Wire Wire Line
+ 9900 4450 9900 4500
+$Comp
+L pulse v9
+U 1 1 685549DC
+P 10150 4800
+F 0 "v9" H 9950 4900 60 0000 C CNN
+F 1 "pulse" H 9950 4750 60 0000 C CNN
+F 2 "R1" H 9850 4800 60 0000 C CNN
+F 3 "" H 10150 4800 60 0000 C CNN
+ 1 10150 4800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9150 4350 10150 4350
+$Comp
+L pulse v10
+U 1 1 68554A51
+P 10400 4750
+F 0 "v10" H 10200 4850 60 0000 C CNN
+F 1 "pulse" H 10200 4700 60 0000 C CNN
+F 2 "R1" H 10100 4750 60 0000 C CNN
+F 3 "" H 10400 4750 60 0000 C CNN
+ 1 10400 4750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9150 4250 10400 4250
+Wire Wire Line
+ 10400 4250 10400 4300
+$Comp
+L pulse v11
+U 1 1 68554B71
+P 10700 4600
+F 0 "v11" H 10500 4700 60 0000 C CNN
+F 1 "pulse" H 10500 4550 60 0000 C CNN
+F 2 "R1" H 10400 4600 60 0000 C CNN
+F 3 "" H 10700 4600 60 0000 C CNN
+ 1 10700 4600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9150 4150 10700 4150
+$Comp
+L eSim_GND #PWR06
+U 1 1 68554E75
+P 9800 5600
+F 0 "#PWR06" H 9800 5350 50 0001 C CNN
+F 1 "eSim_GND" H 9800 5450 50 0000 C CNN
+F 2 "" H 9800 5600 50 0001 C CNN
+F 3 "" H 9800 5600 50 0001 C CNN
+ 1 9800 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR07
+U 1 1 68554EAA
+P 9900 5550
+F 0 "#PWR07" H 9900 5300 50 0001 C CNN
+F 1 "eSim_GND" H 9900 5400 50 0000 C CNN
+F 2 "" H 9900 5550 50 0001 C CNN
+F 3 "" H 9900 5550 50 0001 C CNN
+ 1 9900 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR08
+U 1 1 68554EDF
+P 10150 5400
+F 0 "#PWR08" H 10150 5150 50 0001 C CNN
+F 1 "eSim_GND" H 10150 5250 50 0000 C CNN
+F 2 "" H 10150 5400 50 0001 C CNN
+F 3 "" H 10150 5400 50 0001 C CNN
+ 1 10150 5400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR09
+U 1 1 68554F14
+P 10400 5350
+F 0 "#PWR09" H 10400 5100 50 0001 C CNN
+F 1 "eSim_GND" H 10400 5200 50 0000 C CNN
+F 2 "" H 10400 5350 50 0001 C CNN
+F 3 "" H 10400 5350 50 0001 C CNN
+ 1 10400 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR010
+U 1 1 68554F49
+P 10700 5200
+F 0 "#PWR010" H 10700 4950 50 0001 C CNN
+F 1 "eSim_GND" H 10700 5050 50 0000 C CNN
+F 2 "" H 10700 5200 50 0001 C CNN
+F 3 "" H 10700 5200 50 0001 C CNN
+ 1 10700 5200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9900 5400 9900 5550
+Wire Wire Line
+ 10150 5250 10150 5400
+Wire Wire Line
+ 10400 5200 10400 5350
+Wire Wire Line
+ 10700 5050 10700 5200
+$Comp
+L adc_bridge_1 U9
+U 1 1 68555813
+P 8300 3750
+F 0 "U9" H 8300 3750 60 0000 C CNN
+F 1 "adc_bridge_1" H 8300 3900 60 0000 C CNN
+F 2 "" H 8300 3750 60 0000 C CNN
+F 3 "" H 8300 3750 60 0000 C CNN
+ 1 8300 3750
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7650 3700 7750 3700
+$Comp
+L DC v4
+U 1 1 6855589C
+P 9050 3250
+F 0 "v4" H 8850 3350 60 0000 C CNN
+F 1 "DC" H 8850 3200 60 0000 C CNN
+F 2 "R1" H 8750 3250 60 0000 C CNN
+F 3 "" H 9050 3250 60 0000 C CNN
+ 1 9050 3250
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 8900 3700 9050 3700
+$Comp
+L eSim_GND #PWR011
+U 1 1 6855597A
+P 9200 2800
+F 0 "#PWR011" H 9200 2550 50 0001 C CNN
+F 1 "eSim_GND" H 9200 2650 50 0000 C CNN
+F 2 "" H 9200 2800 50 0001 C CNN
+F 3 "" H 9200 2800 50 0001 C CNN
+ 1 9200 2800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9050 2800 9200 2800
+$Comp
+L plot_v1 U4
+U 1 1 685559EB
+P 4900 4450
+F 0 "U4" H 4900 4950 60 0000 C CNN
+F 1 "plot_v1" H 5100 4800 60 0000 C CNN
+F 2 "" H 4900 4450 60 0000 C CNN
+F 3 "" H 4900 4450 60 0000 C CNN
+ 1 4900 4450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4900 4250 5100 4250
+$Comp
+L plot_v1 U2
+U 1 1 68555A8F
+P 4700 4500
+F 0 "U2" H 4700 5000 60 0000 C CNN
+F 1 "plot_v1" H 4900 4850 60 0000 C CNN
+F 2 "" H 4700 4500 60 0000 C CNN
+F 3 "" H 4700 4500 60 0000 C CNN
+ 1 4700 4500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4700 4300 4700 4350
+Wire Wire Line
+ 4700 4350 5100 4350
+$Comp
+L plot_v1 U1
+U 1 1 68555B2D
+P 4550 4700
+F 0 "U1" H 4550 5200 60 0000 C CNN
+F 1 "plot_v1" H 4750 5050 60 0000 C CNN
+F 2 "" H 4550 4700 60 0000 C CNN
+F 3 "" H 4550 4700 60 0000 C CNN
+ 1 4550 4700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4550 4500 5000 4500
+Wire Wire Line
+ 5000 4500 5000 4450
+Wire Wire Line
+ 5000 4450 5100 4450
+$Comp
+L plot_v1 U3
+U 1 1 68555BD0
+P 4700 5150
+F 0 "U3" H 4700 5650 60 0000 C CNN
+F 1 "plot_v1" H 4900 5500 60 0000 C CNN
+F 2 "" H 4700 5150 60 0000 C CNN
+F 3 "" H 4700 5150 60 0000 C CNN
+ 1 4700 5150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4700 4950 5100 4950
+Wire Wire Line
+ 5100 4950 5100 4550
+$Comp
+L adc_bridge_1 U7
+U 1 1 68555C75
+P 5100 5400
+F 0 "U7" H 5100 5400 60 0000 C CNN
+F 1 "adc_bridge_1" H 5100 5550 60 0000 C CNN
+F 2 "" H 5100 5400 60 0000 C CNN
+F 3 "" H 5100 5400 60 0000 C CNN
+ 1 5100 5400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5650 5350 5650 4850
+Wire Wire Line
+ 5650 4850 6350 4850
+$Comp
+L pulse v2
+U 1 1 68555D3A
+P 4150 5800
+F 0 "v2" H 3950 5900 60 0000 C CNN
+F 1 "pulse" H 3950 5750 60 0000 C CNN
+F 2 "R1" H 3850 5800 60 0000 C CNN
+F 3 "" H 4150 5800 60 0000 C CNN
+ 1 4150 5800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4150 5350 4500 5350
+$Comp
+L eSim_GND #PWR012
+U 1 1 68556377
+P 4150 6400
+F 0 "#PWR012" H 4150 6150 50 0001 C CNN
+F 1 "eSim_GND" H 4150 6250 50 0000 C CNN
+F 2 "" H 4150 6400 50 0001 C CNN
+F 3 "" H 4150 6400 50 0001 C CNN
+ 1 4150 6400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4150 6250 4150 6400
+$Comp
+L plot_v1 U5
+U 1 1 68556446
+P 4900 6200
+F 0 "U5" H 4900 6700 60 0000 C CNN
+F 1 "plot_v1" H 5100 6550 60 0000 C CNN
+F 2 "" H 4900 6200 60 0000 C CNN
+F 3 "" H 4900 6200 60 0000 C CNN
+ 1 4900 6200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 5350 4400 6000
+Wire Wire Line
+ 4400 6000 4900 6000
+Connection ~ 4400 5350
+$Comp
+L plot_v1 U12
+U 1 1 68558D65
+P 9500 4100
+F 0 "U12" H 9500 4600 60 0000 C CNN
+F 1 "plot_v1" H 9700 4450 60 0000 C CNN
+F 2 "" H 9500 4100 60 0000 C CNN
+F 3 "" H 9500 4100 60 0000 C CNN
+ 1 9500 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9500 3900 9500 4150
+Connection ~ 9500 4150
+$Comp
+L plot_v1 U13
+U 1 1 685592FA
+P 9850 4100
+F 0 "U13" H 9850 4600 60 0000 C CNN
+F 1 "plot_v1" H 10050 4450 60 0000 C CNN
+F 2 "" H 9850 4100 60 0000 C CNN
+F 3 "" H 9850 4100 60 0000 C CNN
+ 1 9850 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9850 3900 9850 4250
+Connection ~ 9850 4250
+$Comp
+L plot_v1 U14
+U 1 1 685593DD
+P 10250 4100
+F 0 "U14" H 10250 4600 60 0000 C CNN
+F 1 "plot_v1" H 10450 4450 60 0000 C CNN
+F 2 "" H 10250 4100 60 0000 C CNN
+F 3 "" H 10250 4100 60 0000 C CNN
+ 1 10250 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10250 3900 10250 4200
+Wire Wire Line
+ 10250 4200 10000 4200
+Wire Wire Line
+ 10000 4200 10000 4350
+Connection ~ 10000 4350
+$Comp
+L plot_v1 U15
+U 1 1 685594B5
+P 11150 4550
+F 0 "U15" H 11150 5050 60 0000 C CNN
+F 1 "plot_v1" H 11350 4900 60 0000 C CNN
+F 2 "" H 11150 4550 60 0000 C CNN
+F 3 "" H 11150 4550 60 0000 C CNN
+ 1 11150 4550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9650 4450 9650 4400
+Wire Wire Line
+ 9650 4400 11150 4400
+Wire Wire Line
+ 11150 4400 11150 4350
+Connection ~ 9650 4450
+$Comp
+L plot_v1 U16
+U 1 1 68559599
+P 10000 6600
+F 0 "U16" H 10000 7100 60 0000 C CNN
+F 1 "plot_v1" H 10200 6950 60 0000 C CNN
+F 2 "" H 10000 6600 60 0000 C CNN
+F 3 "" H 10000 6600 60 0000 C CNN
+ 1 10000 6600
+ 1 0 0 -1
+$EndComp
+Text GLabel 9400 3950 0 60 Input ~ 0
+RST
+Wire Wire Line
+ 9400 3950 9500 3950
+Connection ~ 9500 3950
+Text GLabel 9800 4050 0 60 Input ~ 0
+A
+Wire Wire Line
+ 9800 4050 9850 4050
+Connection ~ 9850 4050
+Text GLabel 10200 4000 0 60 Input ~ 0
+B
+Wire Wire Line
+ 10200 4000 10250 4000
+Connection ~ 10250 4000
+Text GLabel 10950 4250 0 60 Input ~ 0
+C
+Wire Wire Line
+ 10950 4250 10950 4400
+Connection ~ 10950 4400
+Text GLabel 9900 6500 0 60 Input ~ 0
+D
+Text GLabel 5150 4000 0 60 Input ~ 0
+W
+Wire Wire Line
+ 5150 4000 5150 4200
+Wire Wire Line
+ 5150 4200 5050 4200
+Wire Wire Line
+ 5050 4200 5050 4250
+Connection ~ 5050 4250
+Text GLabel 4850 4250 0 60 Input ~ 0
+X
+Wire Wire Line
+ 4850 4250 4850 4350
+Connection ~ 4850 4350
+Text GLabel 4450 4600 0 60 Input ~ 0
+Y
+Wire Wire Line
+ 4450 4600 4600 4600
+Wire Wire Line
+ 4600 4600 4600 4500
+Connection ~ 4600 4500
+Text GLabel 4700 5100 0 60 Input ~ 0
+Z
+Wire Wire Line
+ 4700 5100 4800 5100
+Wire Wire Line
+ 4800 5100 4800 4950
+Connection ~ 4800 4950
+Text GLabel 4600 6150 0 60 Input ~ 0
+CLK
+Wire Wire Line
+ 4600 6150 4650 6150
+Wire Wire Line
+ 4650 6150 4650 6000
+Connection ~ 4650 6000
+Wire Wire Line
+ 9600 5800 9600 5950
+Wire Wire Line
+ 9150 5900 9150 6050
+$Comp
+L eSim_GND #PWR013
+U 1 1 6855893A
+P 9800 7350
+F 0 "#PWR013" H 9800 7100 50 0001 C CNN
+F 1 "eSim_GND" H 9800 7200 50 0000 C CNN
+F 2 "" H 9800 7350 50 0001 C CNN
+F 3 "" H 9800 7350 50 0001 C CNN
+ 1 9800 7350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9800 7200 9800 7350
+Wire Wire Line
+ 9150 4550 9400 4550
+Wire Wire Line
+ 9400 4550 9400 6400
+Wire Wire Line
+ 9400 7300 9700 7300
+Wire Wire Line
+ 9700 7300 9700 7200
+Wire Wire Line
+ 9700 7200 9800 7200
+Wire Wire Line
+ 9400 6300 9700 6300
+Wire Wire Line
+ 9700 6300 9700 6400
+Wire Wire Line
+ 9700 6400 10000 6400
+Connection ~ 9400 6300
+Wire Wire Line
+ 9900 6500 9900 6400
+Connection ~ 9900 6400
+$Comp
+L MC14076B X?
+U 1 1 6855C3A2
+P 7000 4350
+F 0 "X?" H 7000 3400 60 0000 C CNN
+F 1 "MC14076B" H 7050 5200 60 0000 C CNN
+F 2 "" H 7000 4350 60 0001 C CNN
+F 3 "" H 7000 4350 60 0001 C CNN
+ 1 7000 4350
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14076B/MC14076B_test_Previous_Values.xml b/library/SubcircuitLibrary/MC14076B/MC14076B_test_Previous_Values.xml
new file mode 100644
index 000000000..ee95fe450
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/MC14076B_test_Previous_Values.xml
@@ -0,0 +1 @@
+dc0dc0dc0dc0pulse0550n0.1n0.1n1m9mpulse5050n0.1n0.1n2m8mpulse0550n0.1n0.1n1m9mpulse580n2m0.1n0.1n2m8mpulse0500.1n0.1n4m9mdc9pulse0500.1n0.1n1m2madc_bridgedac_bridgeadc_bridgeadc_bridgeadc_bridgeadc_bridgeC:\FOSSEE\eSim\library\SubcircuitLibrary\MC14076BtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes0110msusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14076B/analysis b/library/SubcircuitLibrary/MC14076B/analysis
new file mode 100644
index 000000000..b21a9e13b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14076B/analysis
@@ -0,0 +1 @@
+.tran 1e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14560B/3_and-cache.lib b/library/SubcircuitLibrary/MC14560B/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14560B/3_and.cir b/library/SubcircuitLibrary/MC14560B/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC14560B/3_and.cir.out b/library/SubcircuitLibrary/MC14560B/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14560B/3_and.pro b/library/SubcircuitLibrary/MC14560B/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/MC14560B/3_and.sch b/library/SubcircuitLibrary/MC14560B/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14560B/3_and.sub b/library/SubcircuitLibrary/MC14560B/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14560B/3_and_Previous_Values.xml b/library/SubcircuitLibrary/MC14560B/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14560B/4_and-cache.lib b/library/SubcircuitLibrary/MC14560B/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14560B/4_and-rescue.lib b/library/SubcircuitLibrary/MC14560B/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14560B/4_and.cir b/library/SubcircuitLibrary/MC14560B/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC14560B/4_and.cir.out b/library/SubcircuitLibrary/MC14560B/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14560B/4_and.pro b/library/SubcircuitLibrary/MC14560B/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/MC14560B/4_and.sch b/library/SubcircuitLibrary/MC14560B/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14560B/4_and.sub b/library/SubcircuitLibrary/MC14560B/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14560B/4_and_Previous_Values.xml b/library/SubcircuitLibrary/MC14560B/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B-cache.lib b/library/SubcircuitLibrary/MC14560B/MC14560B-cache.lib
new file mode 100644
index 000000000..680d7b47d
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/MC14560B-cache.lib
@@ -0,0 +1,168 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B.cir b/library/SubcircuitLibrary/MC14560B/MC14560B.cir
new file mode 100644
index 000000000..8eac4591d
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/MC14560B.cir
@@ -0,0 +1,81 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC14560B\MC14560B.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/04/25 23:36:10
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U10-Pad1_ d_nand
+U9 Net-_U1-Pad5_ Net-_U10-Pad1_ Net-_U17-Pad1_ d_and
+U10 Net-_U10-Pad1_ Net-_U1-Pad6_ Net-_U10-Pad3_ d_and
+U17 Net-_U17-Pad1_ Net-_U10-Pad3_ Net-_U17-Pad3_ d_nor
+U2 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_nand
+U7 Net-_U1-Pad3_ Net-_U2-Pad3_ Net-_U16-Pad1_ d_and
+U8 Net-_U2-Pad3_ Net-_U1-Pad4_ Net-_U16-Pad2_ d_and
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nor
+U70 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U14-Pad1_ d_nand
+U5 Net-_U1-Pad1_ Net-_U14-Pad1_ Net-_U15-Pad1_ d_and
+U6 Net-_U14-Pad1_ Net-_U1-Pad2_ Net-_U15-Pad2_ d_and
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor
+U4 Net-_U1-Pad15_ Net-_U1-Pad14_ Net-_U11-Pad2_ d_nand
+U11 Net-_U1-Pad15_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
+U12 Net-_U11-Pad2_ Net-_U1-Pad14_ Net-_U12-Pad3_ d_and
+U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U18-Pad3_ d_nor
+U13 Net-_U11-Pad2_ Net-_U13-Pad2_ d_inverter
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U26 Net-_U1-Pad7_ Net-_U18-Pad3_ Net-_U26-Pad3_ d_nand
+U29 Net-_U1-Pad7_ Net-_U26-Pad3_ Net-_U29-Pad3_ d_and
+U30 Net-_U26-Pad3_ Net-_U18-Pad3_ Net-_U30-Pad3_ d_and
+U36 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U1-Pad13_ d_nor
+U20 Net-_U18-Pad3_ Net-_U20-Pad2_ d_inverter
+U19 Net-_U15-Pad3_ Net-_U19-Pad2_ d_inverter
+U21 Net-_U16-Pad3_ Net-_U21-Pad2_ d_inverter
+U27 Net-_U1-Pad7_ Net-_U20-Pad2_ Net-_U27-Pad3_ d_and
+U25 Net-_U13-Pad2_ Net-_U25-Pad2_ d_inverter
+U31 Net-_U27-Pad3_ Net-_U25-Pad2_ Net-_U31-Pad3_ d_nor
+U34 Net-_U31-Pad3_ Net-_U19-Pad2_ Net-_U34-Pad3_ d_xor
+U40 Net-_U34-Pad3_ Net-_U40-Pad2_ d_inverter
+X3 Net-_U1-Pad7_ Net-_U20-Pad2_ Net-_U19-Pad2_ Net-_U32-Pad1_ 3_and
+U23 Net-_U13-Pad2_ Net-_U19-Pad2_ Net-_U23-Pad3_ d_and
+U24 Net-_U14-Pad2_ Net-_U24-Pad2_ d_inverter
+U32 Net-_U32-Pad1_ Net-_U23-Pad3_ Net-_U32-Pad3_ d_nor
+U37 Net-_U32-Pad3_ Net-_U24-Pad2_ Net-_U37-Pad3_ d_nor
+U41 Net-_U37-Pad3_ Net-_U21-Pad2_ Net-_U41-Pad3_ d_xor
+X1 Net-_U13-Pad2_ Net-_U19-Pad2_ Net-_U21-Pad2_ Net-_U28-Pad2_ 3_and
+U22 Net-_U14-Pad2_ Net-_U21-Pad2_ Net-_U22-Pad3_ d_and
+U28 Net-_U28-Pad1_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_nor
+U33 Net-_U28-Pad3_ Net-_U22-Pad3_ Net-_U33-Pad3_ d_nor
+X2 Net-_U1-Pad7_ Net-_U20-Pad2_ Net-_U19-Pad2_ Net-_U21-Pad2_ Net-_U28-Pad1_ 4_and
+X5 Net-_U2-Pad3_ Net-_U33-Pad3_ Net-_U38-Pad3_ Net-_U44-Pad1_ 3_and
+U35 Net-_U33-Pad3_ Net-_U2-Pad3_ Net-_U35-Pad3_ d_nand
+U38 Net-_U35-Pad3_ Net-_U38-Pad2_ Net-_U38-Pad3_ d_nand
+X4 Net-_U33-Pad3_ Net-_U2-Pad3_ Net-_U10-Pad1_ Net-_U43-Pad1_ 3_and
+U39 Net-_U38-Pad2_ Net-_U10-Pad1_ Net-_U39-Pad3_ d_and
+U43 Net-_U43-Pad1_ Net-_U39-Pad3_ Net-_U43-Pad3_ d_nor
+U42 Net-_U38-Pad3_ Net-_U17-Pad3_ Net-_U42-Pad3_ d_and
+U44 Net-_U44-Pad1_ Net-_U42-Pad3_ Net-_U44-Pad3_ d_nor
+U45 Net-_U44-Pad3_ Net-_U45-Pad2_ d_inverter
+U46 Net-_U43-Pad3_ Net-_U46-Pad2_ d_inverter
+X8 Net-_U34-Pad3_ Net-_U44-Pad3_ Net-_U46-Pad2_ Net-_U57-Pad1_ 3_and
+U49 Net-_U40-Pad2_ Net-_U45-Pad2_ Net-_U49-Pad3_ d_and
+U50 Net-_U41-Pad3_ Net-_U45-Pad2_ Net-_U50-Pad3_ d_and
+U51 Net-_U40-Pad2_ Net-_U43-Pad3_ Net-_U51-Pad3_ d_and
+U57 Net-_U57-Pad1_ Net-_U49-Pad3_ Net-_U57-Pad3_ d_nor
+U58 Net-_U50-Pad3_ Net-_U51-Pad3_ Net-_U58-Pad3_ d_nor
+U61 Net-_U57-Pad3_ Net-_U58-Pad3_ Net-_U1-Pad12_ d_nor
+U47 Net-_U46-Pad2_ Net-_U44-Pad3_ Net-_U47-Pad3_ d_and
+X7 Net-_U34-Pad3_ Net-_U41-Pad3_ Net-_U46-Pad2_ Net-_U55-Pad1_ 3_and
+U55 Net-_U55-Pad1_ Net-_U47-Pad3_ Net-_U1-Pad9_ d_nor
+U48 Net-_U40-Pad2_ Net-_U43-Pad3_ Net-_U48-Pad3_ d_and
+X6 Net-_U34-Pad3_ Net-_U41-Pad3_ Net-_U45-Pad2_ Net-_U56-Pad1_ 3_and
+U56 Net-_U56-Pad1_ Net-_U48-Pad3_ Net-_U56-Pad3_ d_nor
+U60 Net-_U56-Pad3_ Net-_U1-Pad10_ d_inverter
+U53 Net-_U34-Pad3_ Net-_U45-Pad2_ Net-_U53-Pad3_ d_and
+U54 Net-_U40-Pad2_ Net-_U43-Pad3_ Net-_U54-Pad3_ d_and
+U52 Net-_U41-Pad3_ Net-_U46-Pad2_ Net-_U52-Pad3_ d_and
+U59 Net-_U52-Pad3_ Net-_U53-Pad3_ Net-_U59-Pad3_ d_nor
+U62 Net-_U59-Pad3_ Net-_U54-Pad3_ Net-_U1-Pad11_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B.cir.out b/library/SubcircuitLibrary/MC14560B/MC14560B.cir.out
new file mode 100644
index 000000000..fc3b725de
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/MC14560B.cir.out
@@ -0,0 +1,270 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc14560b\mc14560b.cir
+
+.include 3_and.sub
+.include 4_and.sub
+* u3 net-_u1-pad5_ net-_u1-pad6_ net-_u10-pad1_ d_nand
+* u9 net-_u1-pad5_ net-_u10-pad1_ net-_u17-pad1_ d_and
+* u10 net-_u10-pad1_ net-_u1-pad6_ net-_u10-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u10-pad3_ net-_u17-pad3_ d_nor
+* u2 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad3_ d_nand
+* u7 net-_u1-pad3_ net-_u2-pad3_ net-_u16-pad1_ d_and
+* u8 net-_u2-pad3_ net-_u1-pad4_ net-_u16-pad2_ d_and
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nor
+* u70 net-_u1-pad1_ net-_u1-pad2_ net-_u14-pad1_ d_nand
+* u5 net-_u1-pad1_ net-_u14-pad1_ net-_u15-pad1_ d_and
+* u6 net-_u14-pad1_ net-_u1-pad2_ net-_u15-pad2_ d_and
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor
+* u4 net-_u1-pad15_ net-_u1-pad14_ net-_u11-pad2_ d_nand
+* u11 net-_u1-pad15_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12 net-_u11-pad2_ net-_u1-pad14_ net-_u12-pad3_ d_and
+* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u18-pad3_ d_nor
+* u13 net-_u11-pad2_ net-_u13-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u26 net-_u1-pad7_ net-_u18-pad3_ net-_u26-pad3_ d_nand
+* u29 net-_u1-pad7_ net-_u26-pad3_ net-_u29-pad3_ d_and
+* u30 net-_u26-pad3_ net-_u18-pad3_ net-_u30-pad3_ d_and
+* u36 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad13_ d_nor
+* u20 net-_u18-pad3_ net-_u20-pad2_ d_inverter
+* u19 net-_u15-pad3_ net-_u19-pad2_ d_inverter
+* u21 net-_u16-pad3_ net-_u21-pad2_ d_inverter
+* u27 net-_u1-pad7_ net-_u20-pad2_ net-_u27-pad3_ d_and
+* u25 net-_u13-pad2_ net-_u25-pad2_ d_inverter
+* u31 net-_u27-pad3_ net-_u25-pad2_ net-_u31-pad3_ d_nor
+* u34 net-_u31-pad3_ net-_u19-pad2_ net-_u34-pad3_ d_xor
+* u40 net-_u34-pad3_ net-_u40-pad2_ d_inverter
+x3 net-_u1-pad7_ net-_u20-pad2_ net-_u19-pad2_ net-_u32-pad1_ 3_and
+* u23 net-_u13-pad2_ net-_u19-pad2_ net-_u23-pad3_ d_and
+* u24 net-_u14-pad2_ net-_u24-pad2_ d_inverter
+* u32 net-_u32-pad1_ net-_u23-pad3_ net-_u32-pad3_ d_nor
+* u37 net-_u32-pad3_ net-_u24-pad2_ net-_u37-pad3_ d_nor
+* u41 net-_u37-pad3_ net-_u21-pad2_ net-_u41-pad3_ d_xor
+x1 net-_u13-pad2_ net-_u19-pad2_ net-_u21-pad2_ net-_u28-pad2_ 3_and
+* u22 net-_u14-pad2_ net-_u21-pad2_ net-_u22-pad3_ d_and
+* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nor
+* u33 net-_u28-pad3_ net-_u22-pad3_ net-_u33-pad3_ d_nor
+x2 net-_u1-pad7_ net-_u20-pad2_ net-_u19-pad2_ net-_u21-pad2_ net-_u28-pad1_ 4_and
+x5 net-_u2-pad3_ net-_u33-pad3_ net-_u38-pad3_ net-_u44-pad1_ 3_and
+* u35 net-_u33-pad3_ net-_u2-pad3_ net-_u35-pad3_ d_nand
+* u38 net-_u35-pad3_ net-_u38-pad2_ net-_u38-pad3_ d_nand
+x4 net-_u33-pad3_ net-_u2-pad3_ net-_u10-pad1_ net-_u43-pad1_ 3_and
+* u39 net-_u38-pad2_ net-_u10-pad1_ net-_u39-pad3_ d_and
+* u43 net-_u43-pad1_ net-_u39-pad3_ net-_u43-pad3_ d_nor
+* u42 net-_u38-pad3_ net-_u17-pad3_ net-_u42-pad3_ d_and
+* u44 net-_u44-pad1_ net-_u42-pad3_ net-_u44-pad3_ d_nor
+* u45 net-_u44-pad3_ net-_u45-pad2_ d_inverter
+* u46 net-_u43-pad3_ net-_u46-pad2_ d_inverter
+x8 net-_u34-pad3_ net-_u44-pad3_ net-_u46-pad2_ net-_u57-pad1_ 3_and
+* u49 net-_u40-pad2_ net-_u45-pad2_ net-_u49-pad3_ d_and
+* u50 net-_u41-pad3_ net-_u45-pad2_ net-_u50-pad3_ d_and
+* u51 net-_u40-pad2_ net-_u43-pad3_ net-_u51-pad3_ d_and
+* u57 net-_u57-pad1_ net-_u49-pad3_ net-_u57-pad3_ d_nor
+* u58 net-_u50-pad3_ net-_u51-pad3_ net-_u58-pad3_ d_nor
+* u61 net-_u57-pad3_ net-_u58-pad3_ net-_u1-pad12_ d_nor
+* u47 net-_u46-pad2_ net-_u44-pad3_ net-_u47-pad3_ d_and
+x7 net-_u34-pad3_ net-_u41-pad3_ net-_u46-pad2_ net-_u55-pad1_ 3_and
+* u55 net-_u55-pad1_ net-_u47-pad3_ net-_u1-pad9_ d_nor
+* u48 net-_u40-pad2_ net-_u43-pad3_ net-_u48-pad3_ d_and
+x6 net-_u34-pad3_ net-_u41-pad3_ net-_u45-pad2_ net-_u56-pad1_ 3_and
+* u56 net-_u56-pad1_ net-_u48-pad3_ net-_u56-pad3_ d_nor
+* u60 net-_u56-pad3_ net-_u1-pad10_ d_inverter
+* u53 net-_u34-pad3_ net-_u45-pad2_ net-_u53-pad3_ d_and
+* u54 net-_u40-pad2_ net-_u43-pad3_ net-_u54-pad3_ d_and
+* u52 net-_u41-pad3_ net-_u46-pad2_ net-_u52-pad3_ d_and
+* u59 net-_u52-pad3_ net-_u53-pad3_ net-_u59-pad3_ d_nor
+* u62 net-_u59-pad3_ net-_u54-pad3_ net-_u1-pad11_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port
+a1 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u10-pad1_ u3
+a2 [net-_u1-pad5_ net-_u10-pad1_ ] net-_u17-pad1_ u9
+a3 [net-_u10-pad1_ net-_u1-pad6_ ] net-_u10-pad3_ u10
+a4 [net-_u17-pad1_ net-_u10-pad3_ ] net-_u17-pad3_ u17
+a5 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u2-pad3_ u2
+a6 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u16-pad1_ u7
+a7 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u16-pad2_ u8
+a8 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a9 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u14-pad1_ u70
+a10 [net-_u1-pad1_ net-_u14-pad1_ ] net-_u15-pad1_ u5
+a11 [net-_u14-pad1_ net-_u1-pad2_ ] net-_u15-pad2_ u6
+a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a13 [net-_u1-pad15_ net-_u1-pad14_ ] net-_u11-pad2_ u4
+a14 [net-_u1-pad15_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a15 [net-_u11-pad2_ net-_u1-pad14_ ] net-_u12-pad3_ u12
+a16 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u18-pad3_ u18
+a17 net-_u11-pad2_ net-_u13-pad2_ u13
+a18 net-_u14-pad1_ net-_u14-pad2_ u14
+a19 [net-_u1-pad7_ net-_u18-pad3_ ] net-_u26-pad3_ u26
+a20 [net-_u1-pad7_ net-_u26-pad3_ ] net-_u29-pad3_ u29
+a21 [net-_u26-pad3_ net-_u18-pad3_ ] net-_u30-pad3_ u30
+a22 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad13_ u36
+a23 net-_u18-pad3_ net-_u20-pad2_ u20
+a24 net-_u15-pad3_ net-_u19-pad2_ u19
+a25 net-_u16-pad3_ net-_u21-pad2_ u21
+a26 [net-_u1-pad7_ net-_u20-pad2_ ] net-_u27-pad3_ u27
+a27 net-_u13-pad2_ net-_u25-pad2_ u25
+a28 [net-_u27-pad3_ net-_u25-pad2_ ] net-_u31-pad3_ u31
+a29 [net-_u31-pad3_ net-_u19-pad2_ ] net-_u34-pad3_ u34
+a30 net-_u34-pad3_ net-_u40-pad2_ u40
+a31 [net-_u13-pad2_ net-_u19-pad2_ ] net-_u23-pad3_ u23
+a32 net-_u14-pad2_ net-_u24-pad2_ u24
+a33 [net-_u32-pad1_ net-_u23-pad3_ ] net-_u32-pad3_ u32
+a34 [net-_u32-pad3_ net-_u24-pad2_ ] net-_u37-pad3_ u37
+a35 [net-_u37-pad3_ net-_u21-pad2_ ] net-_u41-pad3_ u41
+a36 [net-_u14-pad2_ net-_u21-pad2_ ] net-_u22-pad3_ u22
+a37 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
+a38 [net-_u28-pad3_ net-_u22-pad3_ ] net-_u33-pad3_ u33
+a39 [net-_u33-pad3_ net-_u2-pad3_ ] net-_u35-pad3_ u35
+a40 [net-_u35-pad3_ net-_u38-pad2_ ] net-_u38-pad3_ u38
+a41 [net-_u38-pad2_ net-_u10-pad1_ ] net-_u39-pad3_ u39
+a42 [net-_u43-pad1_ net-_u39-pad3_ ] net-_u43-pad3_ u43
+a43 [net-_u38-pad3_ net-_u17-pad3_ ] net-_u42-pad3_ u42
+a44 [net-_u44-pad1_ net-_u42-pad3_ ] net-_u44-pad3_ u44
+a45 net-_u44-pad3_ net-_u45-pad2_ u45
+a46 net-_u43-pad3_ net-_u46-pad2_ u46
+a47 [net-_u40-pad2_ net-_u45-pad2_ ] net-_u49-pad3_ u49
+a48 [net-_u41-pad3_ net-_u45-pad2_ ] net-_u50-pad3_ u50
+a49 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u51-pad3_ u51
+a50 [net-_u57-pad1_ net-_u49-pad3_ ] net-_u57-pad3_ u57
+a51 [net-_u50-pad3_ net-_u51-pad3_ ] net-_u58-pad3_ u58
+a52 [net-_u57-pad3_ net-_u58-pad3_ ] net-_u1-pad12_ u61
+a53 [net-_u46-pad2_ net-_u44-pad3_ ] net-_u47-pad3_ u47
+a54 [net-_u55-pad1_ net-_u47-pad3_ ] net-_u1-pad9_ u55
+a55 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u48-pad3_ u48
+a56 [net-_u56-pad1_ net-_u48-pad3_ ] net-_u56-pad3_ u56
+a57 net-_u56-pad3_ net-_u1-pad10_ u60
+a58 [net-_u34-pad3_ net-_u45-pad2_ ] net-_u53-pad3_ u53
+a59 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u54-pad3_ u54
+a60 [net-_u41-pad3_ net-_u46-pad2_ ] net-_u52-pad3_ u52
+a61 [net-_u52-pad3_ net-_u53-pad3_ ] net-_u59-pad3_ u59
+a62 [net-_u59-pad3_ net-_u54-pad3_ ] net-_u1-pad11_ u62
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u34 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u41 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u57 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u58 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u61 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u55 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u56 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u59 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u62 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 250e-03 10e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B.pro b/library/SubcircuitLibrary/MC14560B/MC14560B.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/MC14560B.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B.sch b/library/SubcircuitLibrary/MC14560B/MC14560B.sch
new file mode 100644
index 000000000..a94a23bab
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/MC14560B.sch
@@ -0,0 +1,1571 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:nbcd_adder-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nand U3
+U 1 1 6868181D
+P 12300 11000
+F 0 "U3" H 12300 11000 60 0000 C CNN
+F 1 "d_nand" H 12350 11100 60 0000 C CNN
+F 2 "" H 12300 11000 60 0000 C CNN
+F 3 "" H 12300 11000 60 0000 C CNN
+ 1 12300 11000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U9
+U 1 1 6868181E
+P 13400 10650
+F 0 "U9" H 13400 10650 60 0000 C CNN
+F 1 "d_and" H 13450 10750 60 0000 C CNN
+F 2 "" H 13400 10650 60 0000 C CNN
+F 3 "" H 13400 10650 60 0000 C CNN
+ 1 13400 10650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U10
+U 1 1 6868181F
+P 13400 11250
+F 0 "U10" H 13400 11250 60 0000 C CNN
+F 1 "d_and" H 13450 11350 60 0000 C CNN
+F 2 "" H 13400 11250 60 0000 C CNN
+F 3 "" H 13400 11250 60 0000 C CNN
+ 1 13400 11250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U17
+U 1 1 68681820
+P 14600 10900
+F 0 "U17" H 14600 10900 60 0000 C CNN
+F 1 "d_nor" H 14650 11000 60 0000 C CNN
+F 2 "" H 14600 10900 60 0000 C CNN
+F 3 "" H 14600 10900 60 0000 C CNN
+ 1 14600 10900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U2
+U 1 1 68681821
+P 12300 9900
+F 0 "U2" H 12300 9900 60 0000 C CNN
+F 1 "d_nand" H 12350 10000 60 0000 C CNN
+F 2 "" H 12300 9900 60 0000 C CNN
+F 3 "" H 12300 9900 60 0000 C CNN
+ 1 12300 9900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U7
+U 1 1 68681822
+P 13400 9550
+F 0 "U7" H 13400 9550 60 0000 C CNN
+F 1 "d_and" H 13450 9650 60 0000 C CNN
+F 2 "" H 13400 9550 60 0000 C CNN
+F 3 "" H 13400 9550 60 0000 C CNN
+ 1 13400 9550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U8
+U 1 1 68681823
+P 13400 10150
+F 0 "U8" H 13400 10150 60 0000 C CNN
+F 1 "d_and" H 13450 10250 60 0000 C CNN
+F 2 "" H 13400 10150 60 0000 C CNN
+F 3 "" H 13400 10150 60 0000 C CNN
+ 1 13400 10150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U16
+U 1 1 68681824
+P 14600 9800
+F 0 "U16" H 14600 9800 60 0000 C CNN
+F 1 "d_nor" H 14650 9900 60 0000 C CNN
+F 2 "" H 14600 9800 60 0000 C CNN
+F 3 "" H 14600 9800 60 0000 C CNN
+ 1 14600 9800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U70
+U 1 1 68681825
+P 12300 8100
+F 0 "U70" H 12300 8100 60 0000 C CNN
+F 1 "d_nand" H 12350 8200 60 0000 C CNN
+F 2 "" H 12300 8100 60 0000 C CNN
+F 3 "" H 12300 8100 60 0000 C CNN
+ 1 12300 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 68681826
+P 13400 7750
+F 0 "U5" H 13400 7750 60 0000 C CNN
+F 1 "d_and" H 13450 7850 60 0000 C CNN
+F 2 "" H 13400 7750 60 0000 C CNN
+F 3 "" H 13400 7750 60 0000 C CNN
+ 1 13400 7750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 68681827
+P 13400 8350
+F 0 "U6" H 13400 8350 60 0000 C CNN
+F 1 "d_and" H 13450 8450 60 0000 C CNN
+F 2 "" H 13400 8350 60 0000 C CNN
+F 3 "" H 13400 8350 60 0000 C CNN
+ 1 13400 8350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U15
+U 1 1 68681828
+P 14600 8000
+F 0 "U15" H 14600 8000 60 0000 C CNN
+F 1 "d_nor" H 14650 8100 60 0000 C CNN
+F 2 "" H 14600 8000 60 0000 C CNN
+F 3 "" H 14600 8000 60 0000 C CNN
+ 1 14600 8000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 68681829
+P 12400 6700
+F 0 "U4" H 12400 6700 60 0000 C CNN
+F 1 "d_nand" H 12450 6800 60 0000 C CNN
+F 2 "" H 12400 6700 60 0000 C CNN
+F 3 "" H 12400 6700 60 0000 C CNN
+ 1 12400 6700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U11
+U 1 1 6868182A
+P 13500 6350
+F 0 "U11" H 13500 6350 60 0000 C CNN
+F 1 "d_and" H 13550 6450 60 0000 C CNN
+F 2 "" H 13500 6350 60 0000 C CNN
+F 3 "" H 13500 6350 60 0000 C CNN
+ 1 13500 6350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 6868182B
+P 13500 6950
+F 0 "U12" H 13500 6950 60 0000 C CNN
+F 1 "d_and" H 13550 7050 60 0000 C CNN
+F 2 "" H 13500 6950 60 0000 C CNN
+F 3 "" H 13500 6950 60 0000 C CNN
+ 1 13500 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U18
+U 1 1 6868182C
+P 14700 6600
+F 0 "U18" H 14700 6600 60 0000 C CNN
+F 1 "d_nor" H 14750 6700 60 0000 C CNN
+F 2 "" H 14700 6600 60 0000 C CNN
+F 3 "" H 14700 6600 60 0000 C CNN
+ 1 14700 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U13
+U 1 1 6868182D
+P 13500 7250
+F 0 "U13" H 13500 7150 60 0000 C CNN
+F 1 "d_inverter" H 13500 7400 60 0000 C CNN
+F 2 "" H 13550 7200 60 0000 C CNN
+F 3 "" H 13550 7200 60 0000 C CNN
+ 1 13500 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U14
+U 1 1 6868182E
+P 13500 8750
+F 0 "U14" H 13500 8650 60 0000 C CNN
+F 1 "d_inverter" H 13500 8900 60 0000 C CNN
+F 2 "" H 13550 8700 60 0000 C CNN
+F 3 "" H 13550 8700 60 0000 C CNN
+ 1 13500 8750
+ 1 0 0 -1
+$EndComp
+Text Notes 11850 6200 0 60 ~ 0
+a1
+Text Notes 11900 7100 0 60 ~ 0
+b1
+Text Notes 11800 7550 0 60 ~ 0
+a2
+Text Notes 11800 8500 0 60 ~ 0
+b2
+Text Notes 11750 9350 0 60 ~ 0
+a3
+Text Notes 11800 10300 0 60 ~ 0
+b3
+Text Notes 11800 10500 0 60 ~ 0
+a4
+Text Notes 11750 11400 0 60 ~ 0
+b4
+$Comp
+L d_nand U26
+U 1 1 6868182F
+P 17150 6450
+F 0 "U26" H 17150 6450 60 0000 C CNN
+F 1 "d_nand" H 17200 6550 60 0000 C CNN
+F 2 "" H 17150 6450 60 0000 C CNN
+F 3 "" H 17150 6450 60 0000 C CNN
+ 1 17150 6450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U29
+U 1 1 68681830
+P 18250 6100
+F 0 "U29" H 18250 6100 60 0000 C CNN
+F 1 "d_and" H 18300 6200 60 0000 C CNN
+F 2 "" H 18250 6100 60 0000 C CNN
+F 3 "" H 18250 6100 60 0000 C CNN
+ 1 18250 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U30
+U 1 1 68681831
+P 18250 6700
+F 0 "U30" H 18250 6700 60 0000 C CNN
+F 1 "d_and" H 18300 6800 60 0000 C CNN
+F 2 "" H 18250 6700 60 0000 C CNN
+F 3 "" H 18250 6700 60 0000 C CNN
+ 1 18250 6700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U36
+U 1 1 68681832
+P 19450 6350
+F 0 "U36" H 19450 6350 60 0000 C CNN
+F 1 "d_nor" H 19500 6450 60 0000 C CNN
+F 2 "" H 19450 6350 60 0000 C CNN
+F 3 "" H 19450 6350 60 0000 C CNN
+ 1 19450 6350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U20
+U 1 1 68681833
+P 15550 6950
+F 0 "U20" H 15550 6850 60 0000 C CNN
+F 1 "d_inverter" H 15550 7100 60 0000 C CNN
+F 2 "" H 15600 6900 60 0000 C CNN
+F 3 "" H 15600 6900 60 0000 C CNN
+ 1 15550 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U19
+U 1 1 68681834
+P 15500 7950
+F 0 "U19" H 15500 7850 60 0000 C CNN
+F 1 "d_inverter" H 15500 8100 60 0000 C CNN
+F 2 "" H 15550 7900 60 0000 C CNN
+F 3 "" H 15550 7900 60 0000 C CNN
+ 1 15500 7950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 68681835
+P 15600 9750
+F 0 "U21" H 15600 9650 60 0000 C CNN
+F 1 "d_inverter" H 15600 9900 60 0000 C CNN
+F 2 "" H 15650 9700 60 0000 C CNN
+F 3 "" H 15650 9700 60 0000 C CNN
+ 1 15600 9750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U27
+U 1 1 68681836
+P 17150 7100
+F 0 "U27" H 17150 7100 60 0000 C CNN
+F 1 "d_and" H 17200 7200 60 0000 C CNN
+F 2 "" H 17150 7100 60 0000 C CNN
+F 3 "" H 17150 7100 60 0000 C CNN
+ 1 17150 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U25
+U 1 1 68681837
+P 17050 7500
+F 0 "U25" H 17050 7400 60 0000 C CNN
+F 1 "d_inverter" H 17050 7650 60 0000 C CNN
+F 2 "" H 17100 7450 60 0000 C CNN
+F 3 "" H 17100 7450 60 0000 C CNN
+ 1 17050 7500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U31
+U 1 1 68681838
+P 18400 7350
+F 0 "U31" H 18400 7350 60 0000 C CNN
+F 1 "d_nor" H 18450 7450 60 0000 C CNN
+F 2 "" H 18400 7350 60 0000 C CNN
+F 3 "" H 18400 7350 60 0000 C CNN
+ 1 18400 7350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U34
+U 1 1 68681839
+P 19200 7850
+F 0 "U34" H 19200 7850 60 0000 C CNN
+F 1 "d_xor" H 19250 7950 47 0000 C CNN
+F 2 "" H 19200 7850 60 0000 C CNN
+F 3 "" H 19200 7850 60 0000 C CNN
+ 1 19200 7850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U40
+U 1 1 6868183A
+P 20150 7550
+F 0 "U40" H 20150 7450 60 0000 C CNN
+F 1 "d_inverter" H 20150 7700 60 0000 C CNN
+F 2 "" H 20200 7500 60 0000 C CNN
+F 3 "" H 20200 7500 60 0000 C CNN
+ 1 20150 7550
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X3
+U 1 1 6868183B
+P 16950 8550
+F 0 "X3" H 17050 8500 60 0000 C CNN
+F 1 "3_and" H 17100 8700 60 0000 C CNN
+F 2 "" H 16950 8550 60 0000 C CNN
+F 3 "" H 16950 8550 60 0000 C CNN
+ 1 16950 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U23
+U 1 1 6868183C
+P 17000 8900
+F 0 "U23" H 17000 8900 60 0000 C CNN
+F 1 "d_and" H 17050 9000 60 0000 C CNN
+F 2 "" H 17000 8900 60 0000 C CNN
+F 3 "" H 17000 8900 60 0000 C CNN
+ 1 17000 8900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U24
+U 1 1 6868183D
+P 17000 9200
+F 0 "U24" H 17000 9100 60 0000 C CNN
+F 1 "d_inverter" H 17000 9350 60 0000 C CNN
+F 2 "" H 17050 9150 60 0000 C CNN
+F 3 "" H 17050 9150 60 0000 C CNN
+ 1 17000 9200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U32
+U 1 1 6868183E
+P 18400 8800
+F 0 "U32" H 18400 8800 60 0000 C CNN
+F 1 "d_nor" H 18450 8900 60 0000 C CNN
+F 2 "" H 18400 8800 60 0000 C CNN
+F 3 "" H 18400 8800 60 0000 C CNN
+ 1 18400 8800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U37
+U 1 1 6868183F
+P 19450 9200
+F 0 "U37" H 19450 9200 60 0000 C CNN
+F 1 "d_nor" H 19500 9300 60 0000 C CNN
+F 2 "" H 19450 9200 60 0000 C CNN
+F 3 "" H 19450 9200 60 0000 C CNN
+ 1 19450 9200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U41
+U 1 1 68681840
+P 20500 9500
+F 0 "U41" H 20500 9500 60 0000 C CNN
+F 1 "d_xor" H 20550 9600 47 0000 C CNN
+F 2 "" H 20500 9500 60 0000 C CNN
+F 3 "" H 20500 9500 60 0000 C CNN
+ 1 20500 9500
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 68681841
+P 16850 11050
+F 0 "X1" H 16950 11000 60 0000 C CNN
+F 1 "3_and" H 17000 11200 60 0000 C CNN
+F 2 "" H 16850 11050 60 0000 C CNN
+F 3 "" H 16850 11050 60 0000 C CNN
+ 1 16850 11050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U22
+U 1 1 68681842
+P 16900 11600
+F 0 "U22" H 16900 11600 60 0000 C CNN
+F 1 "d_and" H 16950 11700 60 0000 C CNN
+F 2 "" H 16900 11600 60 0000 C CNN
+F 3 "" H 16900 11600 60 0000 C CNN
+ 1 16900 11600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U28
+U 1 1 68681843
+P 18100 10700
+F 0 "U28" H 18100 10700 60 0000 C CNN
+F 1 "d_nor" H 18150 10800 60 0000 C CNN
+F 2 "" H 18100 10700 60 0000 C CNN
+F 3 "" H 18100 10700 60 0000 C CNN
+ 1 18100 10700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U33
+U 1 1 68681844
+P 19150 11250
+F 0 "U33" H 19150 11250 60 0000 C CNN
+F 1 "d_nor" H 19200 11350 60 0000 C CNN
+F 2 "" H 19150 11250 60 0000 C CNN
+F 3 "" H 19150 11250 60 0000 C CNN
+ 1 19150 11250
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X2
+U 1 1 68681845
+P 16900 10500
+F 0 "X2" H 16950 10450 60 0000 C CNN
+F 1 "4_and" H 17000 10600 60 0000 C CNN
+F 2 "" H 16900 10500 60 0000 C CNN
+F 3 "" H 16900 10500 60 0000 C CNN
+ 1 16900 10500
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X5
+U 1 1 68681846
+P 20550 11850
+F 0 "X5" H 20650 11800 60 0000 C CNN
+F 1 "3_and" H 20700 12000 60 0000 C CNN
+F 2 "" H 20550 11850 60 0000 C CNN
+F 3 "" H 20550 11850 60 0000 C CNN
+ 1 20550 11850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U35
+U 1 1 68681847
+P 19350 12400
+F 0 "U35" H 19350 12400 60 0000 C CNN
+F 1 "d_nand" H 19400 12500 60 0000 C CNN
+F 2 "" H 19350 12400 60 0000 C CNN
+F 3 "" H 19350 12400 60 0000 C CNN
+ 1 19350 12400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U38
+U 1 1 68681848
+P 19800 12850
+F 0 "U38" H 19800 12850 60 0000 C CNN
+F 1 "d_nand" H 19850 12950 60 0000 C CNN
+F 2 "" H 19800 12850 60 0000 C CNN
+F 3 "" H 19800 12850 60 0000 C CNN
+ 1 19800 12850
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X4
+U 1 1 68681849
+P 19950 13700
+F 0 "X4" H 20050 13650 60 0000 C CNN
+F 1 "3_and" H 20100 13850 60 0000 C CNN
+F 2 "" H 19950 13700 60 0000 C CNN
+F 3 "" H 19950 13700 60 0000 C CNN
+ 1 19950 13700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U39
+U 1 1 6868184A
+P 20050 14200
+F 0 "U39" H 20050 14200 60 0000 C CNN
+F 1 "d_and" H 20100 14300 60 0000 C CNN
+F 2 "" H 20050 14200 60 0000 C CNN
+F 3 "" H 20050 14200 60 0000 C CNN
+ 1 20050 14200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U43
+U 1 1 6868184B
+P 21150 13900
+F 0 "U43" H 21150 13900 60 0000 C CNN
+F 1 "d_nor" H 21200 14000 60 0000 C CNN
+F 2 "" H 21150 13900 60 0000 C CNN
+F 3 "" H 21150 13900 60 0000 C CNN
+ 1 21150 13900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U42
+U 1 1 6868184C
+P 20950 13300
+F 0 "U42" H 20950 13300 60 0000 C CNN
+F 1 "d_and" H 21000 13400 60 0000 C CNN
+F 2 "" H 20950 13300 60 0000 C CNN
+F 3 "" H 20950 13300 60 0000 C CNN
+ 1 20950 13300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U44
+U 1 1 6868184D
+P 21900 12400
+F 0 "U44" H 21900 12400 60 0000 C CNN
+F 1 "d_nor" H 21950 12500 60 0000 C CNN
+F 2 "" H 21900 12400 60 0000 C CNN
+F 3 "" H 21900 12400 60 0000 C CNN
+ 1 21900 12400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U45
+U 1 1 6868184E
+P 23300 12350
+F 0 "U45" H 23300 12250 60 0000 C CNN
+F 1 "d_inverter" H 23300 12500 60 0000 C CNN
+F 2 "" H 23350 12300 60 0000 C CNN
+F 3 "" H 23350 12300 60 0000 C CNN
+ 1 23300 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U46
+U 1 1 6868184F
+P 23550 13850
+F 0 "U46" H 23550 13750 60 0000 C CNN
+F 1 "d_inverter" H 23550 14000 60 0000 C CNN
+F 2 "" H 23600 13800 60 0000 C CNN
+F 3 "" H 23600 13800 60 0000 C CNN
+ 1 23550 13850
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X8
+U 1 1 68681850
+P 26200 6150
+F 0 "X8" H 26300 6100 60 0000 C CNN
+F 1 "3_and" H 26350 6300 60 0000 C CNN
+F 2 "" H 26200 6150 60 0000 C CNN
+F 3 "" H 26200 6150 60 0000 C CNN
+ 1 26200 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U49
+U 1 1 68681851
+P 26350 6500
+F 0 "U49" H 26350 6500 60 0000 C CNN
+F 1 "d_and" H 26400 6600 60 0000 C CNN
+F 2 "" H 26350 6500 60 0000 C CNN
+F 3 "" H 26350 6500 60 0000 C CNN
+ 1 26350 6500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U50
+U 1 1 68681852
+P 26350 6800
+F 0 "U50" H 26350 6800 60 0000 C CNN
+F 1 "d_and" H 26400 6900 60 0000 C CNN
+F 2 "" H 26350 6800 60 0000 C CNN
+F 3 "" H 26350 6800 60 0000 C CNN
+ 1 26350 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U51
+U 1 1 68681853
+P 26350 7100
+F 0 "U51" H 26350 7100 60 0000 C CNN
+F 1 "d_and" H 26400 7200 60 0000 C CNN
+F 2 "" H 26350 7100 60 0000 C CNN
+F 3 "" H 26350 7100 60 0000 C CNN
+ 1 26350 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U57
+U 1 1 68681854
+P 27450 6300
+F 0 "U57" H 27450 6300 60 0000 C CNN
+F 1 "d_nor" H 27500 6400 60 0000 C CNN
+F 2 "" H 27450 6300 60 0000 C CNN
+F 3 "" H 27450 6300 60 0000 C CNN
+ 1 27450 6300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U58
+U 1 1 68681855
+P 27450 7000
+F 0 "U58" H 27450 7000 60 0000 C CNN
+F 1 "d_nor" H 27500 7100 60 0000 C CNN
+F 2 "" H 27450 7000 60 0000 C CNN
+F 3 "" H 27450 7000 60 0000 C CNN
+ 1 27450 7000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U61
+U 1 1 68681856
+P 28550 6650
+F 0 "U61" H 28550 6650 60 0000 C CNN
+F 1 "d_nor" H 28600 6750 60 0000 C CNN
+F 2 "" H 28550 6650 60 0000 C CNN
+F 3 "" H 28550 6650 60 0000 C CNN
+ 1 28550 6650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U47
+U 1 1 68681857
+P 26100 12250
+F 0 "U47" H 26100 12250 60 0000 C CNN
+F 1 "d_and" H 26150 12350 60 0000 C CNN
+F 2 "" H 26100 12250 60 0000 C CNN
+F 3 "" H 26100 12250 60 0000 C CNN
+ 1 26100 12250
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X7
+U 1 1 68681858
+P 26100 11750
+F 0 "X7" H 26200 11700 60 0000 C CNN
+F 1 "3_and" H 26250 11900 60 0000 C CNN
+F 2 "" H 26100 11750 60 0000 C CNN
+F 3 "" H 26100 11750 60 0000 C CNN
+ 1 26100 11750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U55
+U 1 1 68681859
+P 27200 12000
+F 0 "U55" H 27200 12000 60 0000 C CNN
+F 1 "d_nor" H 27250 12100 60 0000 C CNN
+F 2 "" H 27200 12000 60 0000 C CNN
+F 3 "" H 27200 12000 60 0000 C CNN
+ 1 27200 12000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U48
+U 1 1 6868185A
+P 26200 10750
+F 0 "U48" H 26200 10750 60 0000 C CNN
+F 1 "d_and" H 26250 10850 60 0000 C CNN
+F 2 "" H 26200 10750 60 0000 C CNN
+F 3 "" H 26200 10750 60 0000 C CNN
+ 1 26200 10750
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X6
+U 1 1 6868185B
+P 26100 10350
+F 0 "X6" H 26200 10300 60 0000 C CNN
+F 1 "3_and" H 26250 10500 60 0000 C CNN
+F 2 "" H 26100 10350 60 0000 C CNN
+F 3 "" H 26100 10350 60 0000 C CNN
+ 1 26100 10350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U56
+U 1 1 6868185C
+P 27300 10550
+F 0 "U56" H 27300 10550 60 0000 C CNN
+F 1 "d_nor" H 27350 10650 60 0000 C CNN
+F 2 "" H 27300 10550 60 0000 C CNN
+F 3 "" H 27300 10550 60 0000 C CNN
+ 1 27300 10550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U60
+U 1 1 6868185D
+P 28450 10500
+F 0 "U60" H 28450 10400 60 0000 C CNN
+F 1 "d_inverter" H 28450 10650 60 0000 C CNN
+F 2 "" H 28500 10450 60 0000 C CNN
+F 3 "" H 28500 10450 60 0000 C CNN
+ 1 28450 10500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U53
+U 1 1 6868185E
+P 26350 8750
+F 0 "U53" H 26350 8750 60 0000 C CNN
+F 1 "d_and" H 26400 8850 60 0000 C CNN
+F 2 "" H 26350 8750 60 0000 C CNN
+F 3 "" H 26350 8750 60 0000 C CNN
+ 1 26350 8750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U54
+U 1 1 6868185F
+P 26350 9200
+F 0 "U54" H 26350 9200 60 0000 C CNN
+F 1 "d_and" H 26400 9300 60 0000 C CNN
+F 2 "" H 26350 9200 60 0000 C CNN
+F 3 "" H 26350 9200 60 0000 C CNN
+ 1 26350 9200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U52
+U 1 1 68681860
+P 26350 8350
+F 0 "U52" H 26350 8350 60 0000 C CNN
+F 1 "d_and" H 26400 8450 60 0000 C CNN
+F 2 "" H 26350 8350 60 0000 C CNN
+F 3 "" H 26350 8350 60 0000 C CNN
+ 1 26350 8350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U59
+U 1 1 68681861
+P 27550 8500
+F 0 "U59" H 27550 8500 60 0000 C CNN
+F 1 "d_nor" H 27600 8600 60 0000 C CNN
+F 2 "" H 27550 8500 60 0000 C CNN
+F 3 "" H 27550 8500 60 0000 C CNN
+ 1 27550 8500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U62
+U 1 1 68681862
+P 28600 8950
+F 0 "U62" H 28600 8950 60 0000 C CNN
+F 1 "d_nor" H 28650 9050 60 0000 C CNN
+F 2 "" H 28600 8950 60 0000 C CNN
+F 3 "" H 28600 8950 60 0000 C CNN
+ 1 28600 8950
+ 1 0 0 -1
+$EndComp
+Text Notes 27400 12250 0 60 ~ 0
+cout\n
+Text Notes 28550 10750 0 60 ~ 0
+s4\n
+Text Notes 28600 9200 0 60 ~ 0
+s3
+Text Notes 28600 6850 0 60 ~ 0
+s2
+Text Notes 28450 5850 0 60 ~ 0
+s1
+Text Notes 11800 5850 0 60 ~ 0
+cin\n
+$Comp
+L PORT U1
+U 1 1 68688E74
+P 8700 7650
+F 0 "U1" H 8750 7750 30 0000 C CNN
+F 1 "PORT" H 8700 7650 30 0000 C CNN
+F 2 "" H 8700 7650 60 0000 C CNN
+F 3 "" H 8700 7650 60 0000 C CNN
+ 1 8700 7650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6868905E
+P 8750 8350
+F 0 "U1" H 8800 8450 30 0000 C CNN
+F 1 "PORT" H 8750 8350 30 0000 C CNN
+F 2 "" H 8750 8350 60 0000 C CNN
+F 3 "" H 8750 8350 60 0000 C CNN
+ 2 8750 8350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68689117
+P 11050 9450
+F 0 "U1" H 11100 9550 30 0000 C CNN
+F 1 "PORT" H 11050 9450 30 0000 C CNN
+F 2 "" H 11050 9450 60 0000 C CNN
+F 3 "" H 11050 9450 60 0000 C CNN
+ 3 11050 9450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68689257
+P 8050 10150
+F 0 "U1" H 8100 10250 30 0000 C CNN
+F 1 "PORT" H 8050 10150 30 0000 C CNN
+F 2 "" H 8050 10150 60 0000 C CNN
+F 3 "" H 8050 10150 60 0000 C CNN
+ 4 8050 10150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68689432
+P 8150 10550
+F 0 "U1" H 8200 10650 30 0000 C CNN
+F 1 "PORT" H 8150 10550 30 0000 C CNN
+F 2 "" H 8150 10550 60 0000 C CNN
+F 3 "" H 8150 10550 60 0000 C CNN
+ 5 8150 10550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68689509
+P 8200 11250
+F 0 "U1" H 8250 11350 30 0000 C CNN
+F 1 "PORT" H 8200 11250 30 0000 C CNN
+F 2 "" H 8200 11250 60 0000 C CNN
+F 3 "" H 8200 11250 60 0000 C CNN
+ 6 8200 11250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68689A0E
+P 9100 5950
+F 0 "U1" H 9150 6050 30 0000 C CNN
+F 1 "PORT" H 9100 5950 30 0000 C CNN
+F 2 "" H 9100 5950 60 0000 C CNN
+F 3 "" H 9100 5950 60 0000 C CNN
+ 7 9100 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68689ADD
+P 29850 11950
+F 0 "U1" H 29900 12050 30 0000 C CNN
+F 1 "PORT" H 29850 11950 30 0000 C CNN
+F 2 "" H 29850 11950 60 0000 C CNN
+F 3 "" H 29850 11950 60 0000 C CNN
+ 9 29850 11950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6868A40A
+P 29400 10500
+F 0 "U1" H 29450 10600 30 0000 C CNN
+F 1 "PORT" H 29400 10500 30 0000 C CNN
+F 2 "" H 29400 10500 60 0000 C CNN
+F 3 "" H 29400 10500 60 0000 C CNN
+ 10 29400 10500
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6868A4DB
+P 29700 8900
+F 0 "U1" H 29750 9000 30 0000 C CNN
+F 1 "PORT" H 29700 8900 30 0000 C CNN
+F 2 "" H 29700 8900 60 0000 C CNN
+F 3 "" H 29700 8900 60 0000 C CNN
+ 11 29700 8900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6868A68C
+P 30200 6600
+F 0 "U1" H 30250 6700 30 0000 C CNN
+F 1 "PORT" H 30200 6600 30 0000 C CNN
+F 2 "" H 30200 6600 60 0000 C CNN
+F 3 "" H 30200 6600 60 0000 C CNN
+ 12 30200 6600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6868A890
+P 30350 5700
+F 0 "U1" H 30400 5800 30 0000 C CNN
+F 1 "PORT" H 30350 5700 30 0000 C CNN
+F 2 "" H 30350 5700 60 0000 C CNN
+F 3 "" H 30350 5700 60 0000 C CNN
+ 13 30350 5700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6868C268
+P 8700 6950
+F 0 "U1" H 8750 7050 30 0000 C CNN
+F 1 "PORT" H 8700 6950 30 0000 C CNN
+F 2 "" H 8700 6950 60 0000 C CNN
+F 3 "" H 8700 6950 60 0000 C CNN
+ 14 8700 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 6868C9D2
+P 8550 6250
+F 0 "U1" H 8600 6350 30 0000 C CNN
+F 1 "PORT" H 8550 6250 30 0000 C CNN
+F 2 "" H 8550 6250 60 0000 C CNN
+F 3 "" H 8550 6250 60 0000 C CNN
+ 15 8550 6250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 12950 10650 12750 10650
+Wire Wire Line
+ 12750 10650 12750 14200
+Wire Wire Line
+ 12750 11150 12950 11150
+Connection ~ 12750 10950
+Wire Wire Line
+ 13850 10600 14150 10600
+Wire Wire Line
+ 14150 10600 14150 10800
+Wire Wire Line
+ 14150 10900 14150 11200
+Wire Wire Line
+ 14150 11200 13850 11200
+Wire Wire Line
+ 11750 10900 11850 10900
+Wire Wire Line
+ 11750 10900 11750 10550
+Wire Wire Line
+ 8400 10550 12950 10550
+Wire Wire Line
+ 11850 11000 11750 11000
+Wire Wire Line
+ 11750 11000 11750 11250
+Wire Wire Line
+ 8450 11250 12950 11250
+Wire Wire Line
+ 12950 9550 12750 9550
+Wire Wire Line
+ 12750 9550 12750 10250
+Wire Wire Line
+ 12750 10050 12950 10050
+Connection ~ 12750 9850
+Wire Wire Line
+ 13850 9500 14150 9500
+Wire Wire Line
+ 14150 9500 14150 9700
+Wire Wire Line
+ 14150 9800 14150 10100
+Wire Wire Line
+ 14150 10100 13850 10100
+Wire Wire Line
+ 11750 9800 11850 9800
+Wire Wire Line
+ 11750 9800 11750 9450
+Wire Wire Line
+ 11850 9900 11750 9900
+Wire Wire Line
+ 11750 9900 11750 10150
+Wire Wire Line
+ 8300 10150 12950 10150
+Wire Wire Line
+ 12950 7750 12750 7750
+Wire Wire Line
+ 12750 7750 12750 8750
+Wire Wire Line
+ 12750 8250 12950 8250
+Connection ~ 12750 8050
+Wire Wire Line
+ 13850 7700 14150 7700
+Wire Wire Line
+ 14150 7700 14150 7900
+Wire Wire Line
+ 14150 8000 14150 8300
+Wire Wire Line
+ 14150 8300 13850 8300
+Wire Wire Line
+ 11750 8000 11850 8000
+Wire Wire Line
+ 11750 8000 11750 7650
+Wire Wire Line
+ 8950 7650 12950 7650
+Wire Wire Line
+ 11850 8100 11750 8100
+Wire Wire Line
+ 11750 8100 11750 8350
+Wire Wire Line
+ 9000 8350 12950 8350
+Wire Wire Line
+ 13050 6350 12850 6350
+Wire Wire Line
+ 12850 6350 12850 7250
+Wire Wire Line
+ 12850 6850 13050 6850
+Connection ~ 12850 6650
+Wire Wire Line
+ 13950 6300 14250 6300
+Wire Wire Line
+ 14250 6300 14250 6500
+Wire Wire Line
+ 14250 6600 14250 6900
+Wire Wire Line
+ 14250 6900 13950 6900
+Wire Wire Line
+ 11850 6600 11950 6600
+Wire Wire Line
+ 11850 6600 11850 6250
+Wire Wire Line
+ 8800 6250 13050 6250
+Wire Wire Line
+ 11950 6700 11850 6700
+Wire Wire Line
+ 11850 6700 11850 6950
+Wire Wire Line
+ 8950 6950 13050 6950
+Wire Wire Line
+ 12850 7250 13200 7250
+Connection ~ 12850 6850
+Wire Wire Line
+ 12750 8750 13200 8750
+Connection ~ 12750 8250
+Wire Wire Line
+ 17800 6100 17600 6100
+Wire Wire Line
+ 17600 6100 17600 6600
+Wire Wire Line
+ 17600 6600 17800 6600
+Connection ~ 17600 6400
+Wire Wire Line
+ 18700 6050 19000 6050
+Wire Wire Line
+ 19000 6050 19000 6250
+Wire Wire Line
+ 19000 6350 19000 6650
+Wire Wire Line
+ 19000 6650 18700 6650
+Wire Wire Line
+ 16600 6350 16700 6350
+Wire Wire Line
+ 16600 6350 16600 6000
+Wire Wire Line
+ 16300 6000 17800 6000
+Wire Wire Line
+ 16700 6450 16600 6450
+Wire Wire Line
+ 16600 6450 16600 6700
+Wire Wire Line
+ 15300 6700 17800 6700
+Wire Wire Line
+ 15050 7950 15200 7950
+Wire Wire Line
+ 15050 9750 15300 9750
+Wire Wire Line
+ 15150 6550 15300 6550
+Wire Wire Line
+ 15300 6550 15300 6700
+Connection ~ 16600 6700
+Wire Wire Line
+ 16300 5950 16300 10350
+Wire Wire Line
+ 16300 7000 16700 7000
+Connection ~ 16600 6000
+Wire Wire Line
+ 15850 6950 15850 7100
+Wire Wire Line
+ 15850 7100 16700 7100
+Wire Wire Line
+ 13800 7250 16750 7250
+Wire Wire Line
+ 16750 7250 16750 7500
+Wire Wire Line
+ 17600 7050 17950 7050
+Wire Wire Line
+ 17950 7050 17950 7250
+Wire Wire Line
+ 17950 7350 17950 7500
+Wire Wire Line
+ 17950 7500 17350 7500
+Wire Wire Line
+ 18850 7300 18850 7600
+Wire Wire Line
+ 18850 7600 18750 7600
+Wire Wire Line
+ 18750 7600 18750 7750
+Wire Wire Line
+ 15800 7950 18750 7950
+Wire Wire Line
+ 18750 7950 18750 7850
+Wire Wire Line
+ 19650 7800 19650 7550
+Wire Wire Line
+ 19650 7550 19850 7550
+Wire Wire Line
+ 15250 6950 15250 6550
+Connection ~ 15250 6550
+Wire Wire Line
+ 16300 8400 16600 8400
+Connection ~ 16300 7000
+Wire Wire Line
+ 16200 7100 16200 10450
+Wire Wire Line
+ 16200 8500 16600 8500
+Connection ~ 16200 7100
+Wire Wire Line
+ 16100 7950 16100 11000
+Wire Wire Line
+ 16100 8600 16600 8600
+Connection ~ 16100 7950
+Wire Wire Line
+ 15950 7250 15950 10900
+Wire Wire Line
+ 15950 8800 16550 8800
+Connection ~ 15950 7250
+Wire Wire Line
+ 16100 8900 16550 8900
+Connection ~ 16100 8600
+Wire Wire Line
+ 13800 8750 15800 8750
+Wire Wire Line
+ 15800 8750 15800 9200
+Wire Wire Line
+ 15800 9200 16700 9200
+Wire Wire Line
+ 17450 8500 17950 8500
+Wire Wire Line
+ 17950 8500 17950 8700
+Wire Wire Line
+ 17450 8850 17950 8850
+Wire Wire Line
+ 17950 8850 17950 8800
+Wire Wire Line
+ 17300 9200 19000 9200
+Wire Wire Line
+ 18850 8750 18850 9100
+Wire Wire Line
+ 18850 9100 19000 9100
+Wire Wire Line
+ 19900 9150 20050 9150
+Wire Wire Line
+ 20050 9150 20050 9400
+Wire Wire Line
+ 15900 9750 20050 9750
+Wire Wire Line
+ 20050 9750 20050 9500
+Wire Wire Line
+ 16300 10350 16500 10350
+Connection ~ 16300 8400
+Wire Wire Line
+ 16200 10450 16500 10450
+Connection ~ 16200 8500
+Wire Wire Line
+ 16100 10550 16500 10550
+Connection ~ 16100 8900
+Wire Wire Line
+ 16000 9750 16000 11600
+Wire Wire Line
+ 16000 10650 16500 10650
+Connection ~ 16000 9750
+Wire Wire Line
+ 15950 10900 16500 10900
+Connection ~ 15950 8800
+Wire Wire Line
+ 16100 11000 16500 11000
+Connection ~ 16100 10550
+Wire Wire Line
+ 16000 11100 16500 11100
+Connection ~ 16000 10650
+Wire Wire Line
+ 16050 9200 16050 11500
+Wire Wire Line
+ 16050 11500 16450 11500
+Connection ~ 16050 9200
+Wire Wire Line
+ 16000 11600 16450 11600
+Connection ~ 16000 11100
+Wire Wire Line
+ 17400 10500 17650 10500
+Wire Wire Line
+ 17650 10500 17650 10600
+Wire Wire Line
+ 17350 11000 17650 11000
+Wire Wire Line
+ 17650 11000 17650 10700
+Wire Wire Line
+ 18550 10650 18550 11150
+Wire Wire Line
+ 18550 11150 18700 11150
+Wire Wire Line
+ 17350 11550 18550 11550
+Wire Wire Line
+ 18550 11550 18550 11250
+Wire Wire Line
+ 18550 11250 18700 11250
+Wire Wire Line
+ 12750 10250 20200 10250
+Wire Wire Line
+ 20200 10250 20200 11700
+Connection ~ 12750 10050
+Wire Wire Line
+ 19600 11200 19950 11200
+Wire Wire Line
+ 19950 11200 19950 11800
+Wire Wire Line
+ 18600 11800 20200 11800
+Wire Wire Line
+ 18900 11800 18900 12300
+Connection ~ 19950 11800
+Wire Wire Line
+ 20200 11500 18800 11500
+Wire Wire Line
+ 18800 11500 18800 13650
+Wire Wire Line
+ 18800 12400 18900 12400
+Connection ~ 20200 11500
+Wire Wire Line
+ 19600 14100 18950 14100
+Wire Wire Line
+ 18950 14100 18950 12850
+Wire Wire Line
+ 20200 11900 20200 12050
+Wire Wire Line
+ 20200 12050 20350 12050
+Wire Wire Line
+ 20350 12050 20350 13200
+Wire Wire Line
+ 20350 12800 20250 12800
+Wire Wire Line
+ 20350 13200 20500 13200
+Connection ~ 20350 12800
+Wire Wire Line
+ 15050 10850 15050 13300
+Wire Wire Line
+ 15050 13300 20500 13300
+Wire Wire Line
+ 21050 11800 21450 11800
+Wire Wire Line
+ 21450 11800 21450 12300
+Wire Wire Line
+ 21450 12400 21450 13250
+Wire Wire Line
+ 21450 13250 21400 13250
+Wire Wire Line
+ 18600 11800 18600 13550
+Wire Wire Line
+ 18600 13550 19600 13550
+Connection ~ 18900 11800
+Wire Wire Line
+ 18800 13650 19600 13650
+Connection ~ 18800 12400
+Wire Wire Line
+ 19600 13750 19350 13750
+Wire Wire Line
+ 19350 13750 19350 14200
+Wire Wire Line
+ 12750 14200 19600 14200
+Connection ~ 12750 11150
+Connection ~ 19350 14200
+Wire Wire Line
+ 20450 13650 20700 13650
+Wire Wire Line
+ 20700 13650 20700 13800
+Wire Wire Line
+ 20700 13900 20700 14150
+Wire Wire Line
+ 20700 14150 20500 14150
+Wire Wire Line
+ 22350 12350 23000 12350
+Wire Wire Line
+ 21600 13850 23250 13850
+Wire Wire Line
+ 25500 12250 25650 12250
+Wire Wire Line
+ 25500 6100 25500 12600
+Wire Wire Line
+ 25500 12600 22550 12600
+Wire Wire Line
+ 22550 12600 22550 12350
+Connection ~ 22550 12350
+Wire Wire Line
+ 25650 12150 25400 12150
+Wire Wire Line
+ 25400 6200 25400 13850
+Wire Wire Line
+ 25400 13850 23850 13850
+Wire Wire Line
+ 25750 11800 25400 11800
+Connection ~ 25400 12150
+Wire Wire Line
+ 20950 9450 25150 9450
+Wire Wire Line
+ 25150 6700 25150 11700
+Wire Wire Line
+ 25150 11700 25750 11700
+Wire Wire Line
+ 19650 7700 19900 7700
+Wire Wire Line
+ 19900 7700 19900 9050
+Wire Wire Line
+ 19900 9050 25050 9050
+Wire Wire Line
+ 25050 6000 25050 11600
+Wire Wire Line
+ 25050 11600 25750 11600
+Connection ~ 19650 7700
+Wire Wire Line
+ 26600 11700 26750 11700
+Wire Wire Line
+ 26750 11700 26750 11900
+Wire Wire Line
+ 26750 12000 26750 12200
+Wire Wire Line
+ 26750 12200 26550 12200
+Wire Wire Line
+ 25750 10750 22750 10750
+Wire Wire Line
+ 22750 7100 22750 13850
+Connection ~ 22750 13850
+Wire Wire Line
+ 20450 7550 24900 7550
+Wire Wire Line
+ 24900 6400 24900 10650
+Wire Wire Line
+ 24900 10650 25750 10650
+Wire Wire Line
+ 25750 10400 23950 10400
+Wire Wire Line
+ 23950 6500 23950 12350
+Wire Wire Line
+ 23950 12350 23600 12350
+Wire Wire Line
+ 25750 10300 25150 10300
+Connection ~ 25150 10300
+Wire Wire Line
+ 25750 10200 25050 10200
+Connection ~ 25050 10200
+Wire Wire Line
+ 26600 10300 26850 10300
+Wire Wire Line
+ 26850 10300 26850 10450
+Wire Wire Line
+ 26850 10550 26850 10700
+Wire Wire Line
+ 26850 10700 26650 10700
+Wire Wire Line
+ 27750 10500 28150 10500
+Wire Wire Line
+ 25900 9200 22750 9200
+Connection ~ 22750 10750
+Wire Wire Line
+ 25900 9100 25200 9100
+Wire Wire Line
+ 25200 9100 25200 8950
+Wire Wire Line
+ 25200 8950 24900 8950
+Connection ~ 24900 8950
+Wire Wire Line
+ 25900 8750 23950 8750
+Connection ~ 23950 10400
+Wire Wire Line
+ 25050 8650 25900 8650
+Connection ~ 25050 9050
+Wire Wire Line
+ 25900 8350 25400 8350
+Connection ~ 25400 11800
+Wire Wire Line
+ 25150 8250 25900 8250
+Connection ~ 25150 9450
+Wire Wire Line
+ 26800 8300 27100 8300
+Wire Wire Line
+ 27100 8300 27100 8400
+Wire Wire Line
+ 26800 8700 27100 8700
+Wire Wire Line
+ 27100 8700 27100 8500
+Wire Wire Line
+ 26800 9150 28150 9150
+Wire Wire Line
+ 28150 9150 28150 8950
+Wire Wire Line
+ 28000 8450 28150 8450
+Wire Wire Line
+ 28150 8450 28150 8850
+Wire Wire Line
+ 25900 7100 22750 7100
+Connection ~ 22750 9200
+Wire Wire Line
+ 25900 7000 24900 7000
+Connection ~ 24900 7550
+Wire Wire Line
+ 23950 6800 25900 6800
+Connection ~ 23950 8750
+Wire Wire Line
+ 25900 6500 23950 6500
+Connection ~ 23950 6800
+Wire Wire Line
+ 25900 6700 25150 6700
+Connection ~ 25150 8250
+Wire Wire Line
+ 24900 6400 25900 6400
+Connection ~ 24900 7000
+Wire Wire Line
+ 25400 6200 25850 6200
+Connection ~ 25400 8350
+Wire Wire Line
+ 25500 6100 25850 6100
+Connection ~ 25500 12250
+Wire Wire Line
+ 25050 6000 25850 6000
+Connection ~ 25050 8650
+Wire Wire Line
+ 26700 6100 27000 6100
+Wire Wire Line
+ 27000 6100 27000 6200
+Wire Wire Line
+ 27000 6300 27000 6450
+Wire Wire Line
+ 27000 6450 26800 6450
+Wire Wire Line
+ 26800 6750 27000 6750
+Wire Wire Line
+ 27000 6750 27000 6900
+Wire Wire Line
+ 27000 7000 27000 7050
+Wire Wire Line
+ 27000 7050 26800 7050
+Wire Wire Line
+ 27900 6250 28100 6250
+Wire Wire Line
+ 28100 6250 28100 6550
+Wire Wire Line
+ 28100 6650 28100 6950
+Wire Wire Line
+ 28100 6950 27900 6950
+Wire Wire Line
+ 9350 5950 16300 5950
+Connection ~ 16300 6000
+Wire Wire Line
+ 19900 6300 19900 5700
+Wire Wire Line
+ 19900 5700 30100 5700
+Connection ~ 11850 6250
+Connection ~ 11850 6950
+Connection ~ 11750 7650
+Connection ~ 11750 8350
+Connection ~ 11750 10150
+Connection ~ 11750 10550
+Connection ~ 11750 11250
+Wire Wire Line
+ 29000 6600 29950 6600
+Wire Wire Line
+ 27650 11950 29600 11950
+Wire Wire Line
+ 19800 12350 19950 12350
+Wire Wire Line
+ 19950 12350 19950 12600
+Wire Wire Line
+ 19950 12600 19250 12600
+Wire Wire Line
+ 19250 12600 19250 12750
+Wire Wire Line
+ 19250 12750 19350 12750
+Wire Wire Line
+ 29450 8900 29050 8900
+Wire Wire Line
+ 29150 10500 28750 10500
+Wire Wire Line
+ 11300 9450 12950 9450
+Connection ~ 11750 9450
+Wire Wire Line
+ 18950 12850 19350 12850
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B.sub b/library/SubcircuitLibrary/MC14560B/MC14560B.sub
new file mode 100644
index 000000000..6a54b13a8
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/MC14560B.sub
@@ -0,0 +1,264 @@
+* Subcircuit MC14560B
+.subckt MC14560B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_
+* c:\fossee\esim\library\subcircuitlibrary\mc14560b\mc14560b.cir
+.include 3_and.sub
+.include 4_and.sub
+* u3 net-_u1-pad5_ net-_u1-pad6_ net-_u10-pad1_ d_nand
+* u9 net-_u1-pad5_ net-_u10-pad1_ net-_u17-pad1_ d_and
+* u10 net-_u10-pad1_ net-_u1-pad6_ net-_u10-pad3_ d_and
+* u17 net-_u17-pad1_ net-_u10-pad3_ net-_u17-pad3_ d_nor
+* u2 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad3_ d_nand
+* u7 net-_u1-pad3_ net-_u2-pad3_ net-_u16-pad1_ d_and
+* u8 net-_u2-pad3_ net-_u1-pad4_ net-_u16-pad2_ d_and
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nor
+* u70 net-_u1-pad1_ net-_u1-pad2_ net-_u14-pad1_ d_nand
+* u5 net-_u1-pad1_ net-_u14-pad1_ net-_u15-pad1_ d_and
+* u6 net-_u14-pad1_ net-_u1-pad2_ net-_u15-pad2_ d_and
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor
+* u4 net-_u1-pad15_ net-_u1-pad14_ net-_u11-pad2_ d_nand
+* u11 net-_u1-pad15_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u12 net-_u11-pad2_ net-_u1-pad14_ net-_u12-pad3_ d_and
+* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u18-pad3_ d_nor
+* u13 net-_u11-pad2_ net-_u13-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u26 net-_u1-pad7_ net-_u18-pad3_ net-_u26-pad3_ d_nand
+* u29 net-_u1-pad7_ net-_u26-pad3_ net-_u29-pad3_ d_and
+* u30 net-_u26-pad3_ net-_u18-pad3_ net-_u30-pad3_ d_and
+* u36 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad13_ d_nor
+* u20 net-_u18-pad3_ net-_u20-pad2_ d_inverter
+* u19 net-_u15-pad3_ net-_u19-pad2_ d_inverter
+* u21 net-_u16-pad3_ net-_u21-pad2_ d_inverter
+* u27 net-_u1-pad7_ net-_u20-pad2_ net-_u27-pad3_ d_and
+* u25 net-_u13-pad2_ net-_u25-pad2_ d_inverter
+* u31 net-_u27-pad3_ net-_u25-pad2_ net-_u31-pad3_ d_nor
+* u34 net-_u31-pad3_ net-_u19-pad2_ net-_u34-pad3_ d_xor
+* u40 net-_u34-pad3_ net-_u40-pad2_ d_inverter
+x3 net-_u1-pad7_ net-_u20-pad2_ net-_u19-pad2_ net-_u32-pad1_ 3_and
+* u23 net-_u13-pad2_ net-_u19-pad2_ net-_u23-pad3_ d_and
+* u24 net-_u14-pad2_ net-_u24-pad2_ d_inverter
+* u32 net-_u32-pad1_ net-_u23-pad3_ net-_u32-pad3_ d_nor
+* u37 net-_u32-pad3_ net-_u24-pad2_ net-_u37-pad3_ d_nor
+* u41 net-_u37-pad3_ net-_u21-pad2_ net-_u41-pad3_ d_xor
+x1 net-_u13-pad2_ net-_u19-pad2_ net-_u21-pad2_ net-_u28-pad2_ 3_and
+* u22 net-_u14-pad2_ net-_u21-pad2_ net-_u22-pad3_ d_and
+* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nor
+* u33 net-_u28-pad3_ net-_u22-pad3_ net-_u33-pad3_ d_nor
+x2 net-_u1-pad7_ net-_u20-pad2_ net-_u19-pad2_ net-_u21-pad2_ net-_u28-pad1_ 4_and
+x5 net-_u2-pad3_ net-_u33-pad3_ net-_u38-pad3_ net-_u44-pad1_ 3_and
+* u35 net-_u33-pad3_ net-_u2-pad3_ net-_u35-pad3_ d_nand
+* u38 net-_u35-pad3_ net-_u38-pad2_ net-_u38-pad3_ d_nand
+x4 net-_u33-pad3_ net-_u2-pad3_ net-_u10-pad1_ net-_u43-pad1_ 3_and
+* u39 net-_u38-pad2_ net-_u10-pad1_ net-_u39-pad3_ d_and
+* u43 net-_u43-pad1_ net-_u39-pad3_ net-_u43-pad3_ d_nor
+* u42 net-_u38-pad3_ net-_u17-pad3_ net-_u42-pad3_ d_and
+* u44 net-_u44-pad1_ net-_u42-pad3_ net-_u44-pad3_ d_nor
+* u45 net-_u44-pad3_ net-_u45-pad2_ d_inverter
+* u46 net-_u43-pad3_ net-_u46-pad2_ d_inverter
+x8 net-_u34-pad3_ net-_u44-pad3_ net-_u46-pad2_ net-_u57-pad1_ 3_and
+* u49 net-_u40-pad2_ net-_u45-pad2_ net-_u49-pad3_ d_and
+* u50 net-_u41-pad3_ net-_u45-pad2_ net-_u50-pad3_ d_and
+* u51 net-_u40-pad2_ net-_u43-pad3_ net-_u51-pad3_ d_and
+* u57 net-_u57-pad1_ net-_u49-pad3_ net-_u57-pad3_ d_nor
+* u58 net-_u50-pad3_ net-_u51-pad3_ net-_u58-pad3_ d_nor
+* u61 net-_u57-pad3_ net-_u58-pad3_ net-_u1-pad12_ d_nor
+* u47 net-_u46-pad2_ net-_u44-pad3_ net-_u47-pad3_ d_and
+x7 net-_u34-pad3_ net-_u41-pad3_ net-_u46-pad2_ net-_u55-pad1_ 3_and
+* u55 net-_u55-pad1_ net-_u47-pad3_ net-_u1-pad9_ d_nor
+* u48 net-_u40-pad2_ net-_u43-pad3_ net-_u48-pad3_ d_and
+x6 net-_u34-pad3_ net-_u41-pad3_ net-_u45-pad2_ net-_u56-pad1_ 3_and
+* u56 net-_u56-pad1_ net-_u48-pad3_ net-_u56-pad3_ d_nor
+* u60 net-_u56-pad3_ net-_u1-pad10_ d_inverter
+* u53 net-_u34-pad3_ net-_u45-pad2_ net-_u53-pad3_ d_and
+* u54 net-_u40-pad2_ net-_u43-pad3_ net-_u54-pad3_ d_and
+* u52 net-_u41-pad3_ net-_u46-pad2_ net-_u52-pad3_ d_and
+* u59 net-_u52-pad3_ net-_u53-pad3_ net-_u59-pad3_ d_nor
+* u62 net-_u59-pad3_ net-_u54-pad3_ net-_u1-pad11_ d_nor
+a1 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u10-pad1_ u3
+a2 [net-_u1-pad5_ net-_u10-pad1_ ] net-_u17-pad1_ u9
+a3 [net-_u10-pad1_ net-_u1-pad6_ ] net-_u10-pad3_ u10
+a4 [net-_u17-pad1_ net-_u10-pad3_ ] net-_u17-pad3_ u17
+a5 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u2-pad3_ u2
+a6 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u16-pad1_ u7
+a7 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u16-pad2_ u8
+a8 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a9 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u14-pad1_ u70
+a10 [net-_u1-pad1_ net-_u14-pad1_ ] net-_u15-pad1_ u5
+a11 [net-_u14-pad1_ net-_u1-pad2_ ] net-_u15-pad2_ u6
+a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a13 [net-_u1-pad15_ net-_u1-pad14_ ] net-_u11-pad2_ u4
+a14 [net-_u1-pad15_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a15 [net-_u11-pad2_ net-_u1-pad14_ ] net-_u12-pad3_ u12
+a16 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u18-pad3_ u18
+a17 net-_u11-pad2_ net-_u13-pad2_ u13
+a18 net-_u14-pad1_ net-_u14-pad2_ u14
+a19 [net-_u1-pad7_ net-_u18-pad3_ ] net-_u26-pad3_ u26
+a20 [net-_u1-pad7_ net-_u26-pad3_ ] net-_u29-pad3_ u29
+a21 [net-_u26-pad3_ net-_u18-pad3_ ] net-_u30-pad3_ u30
+a22 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad13_ u36
+a23 net-_u18-pad3_ net-_u20-pad2_ u20
+a24 net-_u15-pad3_ net-_u19-pad2_ u19
+a25 net-_u16-pad3_ net-_u21-pad2_ u21
+a26 [net-_u1-pad7_ net-_u20-pad2_ ] net-_u27-pad3_ u27
+a27 net-_u13-pad2_ net-_u25-pad2_ u25
+a28 [net-_u27-pad3_ net-_u25-pad2_ ] net-_u31-pad3_ u31
+a29 [net-_u31-pad3_ net-_u19-pad2_ ] net-_u34-pad3_ u34
+a30 net-_u34-pad3_ net-_u40-pad2_ u40
+a31 [net-_u13-pad2_ net-_u19-pad2_ ] net-_u23-pad3_ u23
+a32 net-_u14-pad2_ net-_u24-pad2_ u24
+a33 [net-_u32-pad1_ net-_u23-pad3_ ] net-_u32-pad3_ u32
+a34 [net-_u32-pad3_ net-_u24-pad2_ ] net-_u37-pad3_ u37
+a35 [net-_u37-pad3_ net-_u21-pad2_ ] net-_u41-pad3_ u41
+a36 [net-_u14-pad2_ net-_u21-pad2_ ] net-_u22-pad3_ u22
+a37 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
+a38 [net-_u28-pad3_ net-_u22-pad3_ ] net-_u33-pad3_ u33
+a39 [net-_u33-pad3_ net-_u2-pad3_ ] net-_u35-pad3_ u35
+a40 [net-_u35-pad3_ net-_u38-pad2_ ] net-_u38-pad3_ u38
+a41 [net-_u38-pad2_ net-_u10-pad1_ ] net-_u39-pad3_ u39
+a42 [net-_u43-pad1_ net-_u39-pad3_ ] net-_u43-pad3_ u43
+a43 [net-_u38-pad3_ net-_u17-pad3_ ] net-_u42-pad3_ u42
+a44 [net-_u44-pad1_ net-_u42-pad3_ ] net-_u44-pad3_ u44
+a45 net-_u44-pad3_ net-_u45-pad2_ u45
+a46 net-_u43-pad3_ net-_u46-pad2_ u46
+a47 [net-_u40-pad2_ net-_u45-pad2_ ] net-_u49-pad3_ u49
+a48 [net-_u41-pad3_ net-_u45-pad2_ ] net-_u50-pad3_ u50
+a49 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u51-pad3_ u51
+a50 [net-_u57-pad1_ net-_u49-pad3_ ] net-_u57-pad3_ u57
+a51 [net-_u50-pad3_ net-_u51-pad3_ ] net-_u58-pad3_ u58
+a52 [net-_u57-pad3_ net-_u58-pad3_ ] net-_u1-pad12_ u61
+a53 [net-_u46-pad2_ net-_u44-pad3_ ] net-_u47-pad3_ u47
+a54 [net-_u55-pad1_ net-_u47-pad3_ ] net-_u1-pad9_ u55
+a55 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u48-pad3_ u48
+a56 [net-_u56-pad1_ net-_u48-pad3_ ] net-_u56-pad3_ u56
+a57 net-_u56-pad3_ net-_u1-pad10_ u60
+a58 [net-_u34-pad3_ net-_u45-pad2_ ] net-_u53-pad3_ u53
+a59 [net-_u40-pad2_ net-_u43-pad3_ ] net-_u54-pad3_ u54
+a60 [net-_u41-pad3_ net-_u46-pad2_ ] net-_u52-pad3_ u52
+a61 [net-_u52-pad3_ net-_u53-pad3_ ] net-_u59-pad3_ u59
+a62 [net-_u59-pad3_ net-_u54-pad3_ ] net-_u1-pad11_ u62
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u34 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u41 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u42 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u49 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u50 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u51 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u57 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u58 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u61 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u47 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u55 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u48 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u56 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u52 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u59 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u62 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends MC14560B
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14560B/MC14560B_Previous_Values.xml b/library/SubcircuitLibrary/MC14560B/MC14560B_Previous_Values.xml
new file mode 100644
index 000000000..8e2e40529
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/MC14560B_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_nandd_andd_andd_nord_nandd_andd_andd_nord_nandd_andd_andd_nord_nandd_andd_andd_nord_inverterd_inverterd_nandd_andd_andd_nord_inverterd_inverterd_inverterd_andd_inverterd_nord_xord_inverterd_andd_inverterd_nord_nord_xord_andd_nord_nord_nandd_nandd_andd_nord_andd_nord_inverterd_inverterd_andd_andd_andd_nord_nord_nord_andd_nord_andd_nord_inverterd_andd_andd_andd_nord_norC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC14560B/analysis b/library/SubcircuitLibrary/MC14560B/analysis
new file mode 100644
index 000000000..0a6c83b5a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC14560B/analysis
@@ -0,0 +1 @@
+.tran 250e-03 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC1723/MC1723-cache.lib b/library/SubcircuitLibrary/MC1723/MC1723-cache.lib
new file mode 100644
index 000000000..0fdcdbaa5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/MC1723-cache.lib
@@ -0,0 +1,184 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NJF
+#
+DEF eSim_NJF J 0 0 Y N 1 F N
+F0 "J" -100 50 50 H V R CNN
+F1 "eSim_NJF" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS jfet_n
+DRAW
+C 50 0 111 0 1 10 N
+P 3 0 1 10 10 75 10 -75 10 -75 N
+P 3 0 1 0 100 -100 100 -50 10 -50 N
+P 3 0 1 0 100 100 100 55 10 55 N
+P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F
+X D 1 100 200 100 D 50 50 1 1 P
+X G 2 -200 0 210 R 50 50 1 1 P
+X S 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC1723/MC1723.bak b/library/SubcircuitLibrary/MC1723/MC1723.bak
new file mode 100644
index 000000000..a9f2b7e19
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/MC1723.bak
@@ -0,0 +1,771 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_Diode D1
+U 1 1 6866D034
+P 5450 7100
+F 0 "D1" H 5450 7200 50 0000 C CNN
+F 1 "eSim_Diode" H 5450 7000 50 0000 C CNN
+F 2 "" H 5450 7100 60 0000 C CNN
+F 3 "" H 5450 7100 60 0000 C CNN
+ 1 5450 7100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R1
+U 1 1 6866D12F
+P 7650 5900
+F 0 "R1" H 7700 6030 50 0000 C CNN
+F 1 "500" H 7700 5850 50 0000 C CNN
+F 2 "" H 7700 5880 30 0000 C CNN
+F 3 "" V 7700 5950 30 0000 C CNN
+ 1 7650 5900
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_PNP Q1
+U 1 1 6866D1B5
+P 7800 7150
+F 0 "Q1" H 7700 7200 50 0000 R CNN
+F 1 "eSim_PNP" H 7750 7300 50 0000 R CNN
+F 2 "" H 8000 7250 29 0000 C CNN
+F 3 "" H 7800 7150 60 0000 C CNN
+ 1 7800 7150
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 6866D242
+P 7650 8350
+F 0 "R2" H 7700 8480 50 0000 C CNN
+F 1 "15k" H 7700 8300 50 0000 C CNN
+F 2 "" H 7700 8330 30 0000 C CNN
+F 3 "" V 7700 8400 30 0000 C CNN
+ 1 7650 8350
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NJF J1
+U 1 1 6866D35B
+P 5700 12650
+F 0 "J1" H 5600 12700 50 0000 R CNN
+F 1 "eSim_NJF" H 5650 12800 50 0000 R CNN
+F 2 "" H 5900 12750 29 0000 C CNN
+F 3 "" H 5700 12650 60 0000 C CNN
+ 1 5700 12650
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q3
+U 1 1 6866D540
+P 10100 7150
+F 0 "Q3" H 10000 7200 50 0000 R CNN
+F 1 "eSim_PNP" H 10050 7300 50 0000 R CNN
+F 2 "" H 10300 7250 29 0000 C CNN
+F 3 "" H 10100 7150 60 0000 C CNN
+ 1 10100 7150
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 6866D698
+P 10150 6050
+F 0 "R3" H 10200 6180 50 0000 C CNN
+F 1 "25k" H 10200 6000 50 0000 C CNN
+F 2 "" H 10200 6030 30 0000 C CNN
+F 3 "" V 10200 6100 30 0000 C CNN
+ 1 10150 6050
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 6866D973
+P 8400 15050
+F 0 "Q2" H 8300 15100 50 0000 R CNN
+F 1 "eSim_NPN" H 8350 15200 50 0000 R CNN
+F 2 "" H 8600 15150 29 0000 C CNN
+F 3 "" H 8400 15050 60 0000 C CNN
+ 1 8400 15050
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 6866DA95
+P 11200 9550
+F 0 "Q4" H 11100 9600 50 0000 R CNN
+F 1 "eSim_NPN" H 11150 9700 50 0000 R CNN
+F 2 "" H 11400 9650 29 0000 C CNN
+F 3 "" H 11200 9550 60 0000 C CNN
+ 1 11200 9550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 6866DAFC
+P 12500 10800
+F 0 "Q5" H 12400 10850 50 0000 R CNN
+F 1 "eSim_NPN" H 12450 10950 50 0000 R CNN
+F 2 "" H 12700 10900 29 0000 C CNN
+F 3 "" H 12500 10800 60 0000 C CNN
+ 1 12500 10800
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R5
+U 1 1 6866DF63
+P 12550 12050
+F 0 "R5" H 12600 12180 50 0000 C CNN
+F 1 "100" H 12600 12000 50 0000 C CNN
+F 2 "" H 12600 12030 30 0000 C CNN
+F 3 "" V 12600 12100 30 0000 C CNN
+ 1 12550 12050
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 6866E068
+P 12600 12750
+F 0 "D2" H 12600 12850 50 0000 C CNN
+F 1 "eSim_Diode" H 12600 12650 50 0000 C CNN
+F 2 "" H 12600 12750 60 0000 C CNN
+F 3 "" H 12600 12750 60 0000 C CNN
+ 1 12600 12750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R6
+U 1 1 6866E0F8
+P 12550 14300
+F 0 "R6" H 12600 14430 50 0000 C CNN
+F 1 "5.0k" H 12600 14250 50 0000 C CNN
+F 2 "" H 12600 14280 30 0000 C CNN
+F 3 "" V 12600 14350 30 0000 C CNN
+ 1 12550 14300
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 6866E39B
+P 10500 14000
+F 0 "R4" H 10550 14130 50 0000 C CNN
+F 1 "30k" H 10550 13950 50 0000 C CNN
+F 2 "" H 10550 13980 30 0000 C CNN
+F 3 "" V 10550 14050 30 0000 C CNN
+ 1 10500 14000
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor_polarised C1
+U 1 1 6866E601
+P 9150 13550
+F 0 "C1" H 9175 13650 50 0000 L CNN
+F 1 "5.0p" H 9175 13450 50 0000 L CNN
+F 2 "" H 9150 13550 50 0001 C CNN
+F 3 "" H 9150 13550 50 0001 C CNN
+ 1 9150 13550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5450 6950 5450 5500
+Wire Wire Line
+ 5450 5500 24150 5500
+Wire Wire Line
+ 7700 5500 7700 5800
+Wire Wire Line
+ 7700 6950 7700 6100
+Wire Wire Line
+ 7700 7350 7700 8250
+Wire Wire Line
+ 7700 8550 7700 8900
+Wire Wire Line
+ 7700 8900 5450 8900
+Wire Wire Line
+ 5450 7250 5450 9250
+Wire Wire Line
+ 5600 12450 5600 9250
+Wire Wire Line
+ 5600 9250 5450 9250
+Connection ~ 5450 8900
+Wire Wire Line
+ 5600 12850 5600 16350
+Wire Wire Line
+ 5600 16350 18650 16350
+Wire Wire Line
+ 18650 14900 18650 17150
+Wire Wire Line
+ 8000 7150 9900 7150
+Wire Wire Line
+ 8800 7150 8800 7800
+Wire Wire Line
+ 8800 7800 7700 7800
+Connection ~ 7700 7800
+Connection ~ 8800 7150
+Wire Wire Line
+ 10200 6950 10200 6250
+Wire Wire Line
+ 10200 5500 10200 5950
+Connection ~ 7700 5500
+Wire Wire Line
+ 5900 12650 6850 12650
+Wire Wire Line
+ 6850 12650 6850 16350
+Connection ~ 6850 16350
+Wire Wire Line
+ 8300 15250 8300 16350
+Connection ~ 8300 16350
+Wire Wire Line
+ 8300 9550 8300 14850
+Wire Wire Line
+ 8300 9550 11000 9550
+Wire Wire Line
+ 10200 7350 10200 9550
+Connection ~ 10200 9550
+Wire Wire Line
+ 11300 5500 11300 9350
+Connection ~ 10200 5500
+Wire Wire Line
+ 12300 10800 11300 10800
+Wire Wire Line
+ 11300 10800 11300 9750
+Wire Wire Line
+ 12600 11950 12600 11000
+Wire Wire Line
+ 12600 12250 12600 12600
+Wire Wire Line
+ 12600 12900 12600 14200
+Wire Wire Line
+ 8600 15050 9700 15050
+Wire Wire Line
+ 9700 15050 9700 14000
+Wire Wire Line
+ 9700 14000 10400 14000
+Wire Wire Line
+ 10400 14000 10400 13950
+Wire Wire Line
+ 10700 13950 12600 13950
+Connection ~ 12600 13950
+Wire Wire Line
+ 9150 13700 9150 15050
+Connection ~ 9150 15050
+Wire Wire Line
+ 9150 13400 9150 13000
+Wire Wire Line
+ 9150 13000 8300 13000
+Connection ~ 8300 13000
+Wire Wire Line
+ 12600 14500 12600 16350
+Connection ~ 12600 16350
+Wire Wire Line
+ 12600 12400 13450 12400
+Wire Wire Line
+ 13450 12400 13450 17700
+Connection ~ 12600 12400
+Wire Wire Line
+ 12600 5500 12600 10600
+Connection ~ 11300 5500
+$Comp
+L resistor R8
+U 1 1 6866ED9A
+P 14700 15200
+F 0 "R8" H 14750 15330 50 0000 C CNN
+F 1 "300" H 14750 15150 50 0000 C CNN
+F 2 "" H 14750 15180 30 0000 C CNN
+F 3 "" V 14750 15250 30 0000 C CNN
+ 1 14700 15200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 6866EE4C
+P 14850 13700
+F 0 "Q7" H 14750 13750 50 0000 R CNN
+F 1 "eSim_NPN" H 14800 13850 50 0000 R CNN
+F 2 "" H 15050 13800 29 0000 C CNN
+F 3 "" H 14850 13700 60 0000 C CNN
+ 1 14850 13700
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 14750 15100 14750 13900
+Wire Wire Line
+ 14750 15400 14750 16350
+Connection ~ 14750 16350
+$Comp
+L eSim_PNP Q6
+U 1 1 6866F0B6
+P 14650 7100
+F 0 "Q6" H 14550 7150 50 0000 R CNN
+F 1 "eSim_PNP" H 14600 7250 50 0000 R CNN
+F 2 "" H 14850 7200 29 0000 C CNN
+F 3 "" H 14650 7100 60 0000 C CNN
+ 1 14650 7100
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 14750 7300 14750 13500
+$Comp
+L resistor R7
+U 1 1 6866F697
+P 14700 6100
+F 0 "R7" H 14750 6230 50 0000 C CNN
+F 1 "1.0k" H 14750 6050 50 0000 C CNN
+F 2 "" H 14750 6080 30 0000 C CNN
+F 3 "" V 14750 6150 30 0000 C CNN
+ 1 14700 6100
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 14750 6900 14750 6300
+Wire Wire Line
+ 14750 5500 14750 6000
+Connection ~ 12600 5500
+Wire Wire Line
+ 9500 7150 9500 7550
+Wire Wire Line
+ 9500 7550 18800 7550
+Wire Wire Line
+ 13200 7550 13200 7100
+Wire Wire Line
+ 13200 7100 14450 7100
+Connection ~ 9500 7150
+Wire Wire Line
+ 14750 11150 16100 11150
+Connection ~ 14750 11150
+$Comp
+L eSim_NPN Q8
+U 1 1 6866FC42
+P 16300 11150
+F 0 "Q8" H 16200 11200 50 0000 R CNN
+F 1 "eSim_NPN" H 16250 11300 50 0000 R CNN
+F 2 "" H 16500 11250 29 0000 C CNN
+F 3 "" H 16300 11150 60 0000 C CNN
+ 1 16300 11150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 16400 11350 16400 14700
+Wire Wire Line
+ 15050 13700 18350 13700
+Connection ~ 16400 13700
+$Comp
+L resistor R9
+U 1 1 6866FF68
+P 16350 14800
+F 0 "R9" H 16400 14930 50 0000 C CNN
+F 1 "20k" H 16400 14750 50 0000 C CNN
+F 2 "" H 16400 14780 30 0000 C CNN
+F 3 "" V 16400 14850 30 0000 C CNN
+ 1 16350 14800
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 16400 15000 16400 16350
+Connection ~ 16400 16350
+$Comp
+L eSim_NPN Q10
+U 1 1 68670127
+P 18550 13700
+F 0 "Q10" H 18450 13750 50 0000 R CNN
+F 1 "eSim_NPN" H 18500 13850 50 0000 R CNN
+F 2 "" H 18750 13800 29 0000 C CNN
+F 3 "" H 18550 13700 60 0000 C CNN
+ 1 18550 13700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 18650 13900 18650 14600
+$Comp
+L resistor R10
+U 1 1 68670483
+P 18600 14700
+F 0 "R10" H 18650 14830 50 0000 C CNN
+F 1 "150" H 18650 14650 50 0000 C CNN
+F 2 "" H 18650 14680 30 0000 C CNN
+F 3 "" V 18650 14750 30 0000 C CNN
+ 1 18600 14700
+ 0 1 1 0
+$EndComp
+Connection ~ 18650 16350
+Wire Wire Line
+ 16400 5500 16400 10950
+Connection ~ 14750 5500
+$Comp
+L eSim_NPN Q9
+U 1 1 68670B38
+P 18000 11100
+F 0 "Q9" H 17900 11150 50 0000 R CNN
+F 1 "eSim_NPN" H 17950 11250 50 0000 R CNN
+F 2 "" H 18200 11200 29 0000 C CNN
+F 3 "" H 18000 11100 60 0000 C CNN
+ 1 18000 11100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q12
+U 1 1 68670C29
+P 19550 11100
+F 0 "Q12" H 19450 11150 50 0000 R CNN
+F 1 "eSim_NPN" H 19500 11250 50 0000 R CNN
+F 2 "" H 19750 11200 29 0000 C CNN
+F 3 "" H 19550 11100 60 0000 C CNN
+ 1 19550 11100
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 18100 11300 18100 11700
+Wire Wire Line
+ 18100 11700 19450 11700
+Wire Wire Line
+ 19450 11700 19450 11300
+Wire Wire Line
+ 18650 13500 18650 11700
+Connection ~ 18650 11700
+Wire Wire Line
+ 17800 11100 17350 11100
+Wire Wire Line
+ 17350 11100 17350 17450
+Wire Wire Line
+ 18100 7550 18100 10900
+Wire Wire Line
+ 18100 10050 11600 10050
+Wire Wire Line
+ 11600 10050 11600 10800
+Connection ~ 11600 10800
+$Comp
+L eSim_PNP Q11
+U 1 1 686717D7
+P 19350 7350
+F 0 "Q11" H 19250 7400 50 0000 R CNN
+F 1 "eSim_PNP" H 19300 7500 50 0000 R CNN
+F 2 "" H 19550 7450 29 0000 C CNN
+F 3 "" H 19350 7350 60 0000 C CNN
+ 1 19350 7350
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R11
+U 1 1 6867192A
+P 19400 6400
+F 0 "R11" H 19450 6530 50 0000 C CNN
+F 1 "1.0k" H 19450 6350 50 0000 C CNN
+F 2 "" H 19450 6380 30 0000 C CNN
+F 3 "" V 19450 6450 30 0000 C CNN
+ 1 19400 6400
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 19450 7150 19450 6600
+Wire Wire Line
+ 19450 5500 19450 6300
+Connection ~ 16400 5500
+Wire Wire Line
+ 19450 10900 19450 7550
+Wire Wire Line
+ 18800 7550 18800 7350
+Wire Wire Line
+ 18800 7350 19150 7350
+Connection ~ 13200 7550
+Connection ~ 18100 7550
+Connection ~ 18100 10050
+Wire Wire Line
+ 19750 11100 20250 11100
+Wire Wire Line
+ 20250 11100 20250 17000
+Wire Wire Line
+ 19450 9600 21350 9600
+Wire Wire Line
+ 21350 9600 21350 12600
+Connection ~ 19450 9600
+$Comp
+L eSim_NPN Q13
+U 1 1 686728F4
+P 21450 12800
+F 0 "Q13" H 21350 12850 50 0000 R CNN
+F 1 "eSim_NPN" H 21400 12950 50 0000 R CNN
+F 2 "" H 21650 12900 29 0000 C CNN
+F 3 "" H 21450 12800 60 0000 C CNN
+ 1 21450 12800
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 21350 13000 21350 14250
+Wire Wire Line
+ 21350 14250 23200 14250
+Wire Wire Line
+ 21650 12800 22750 12800
+Wire Wire Line
+ 21350 12250 23100 12250
+Connection ~ 21350 12250
+Wire Wire Line
+ 19450 8550 23850 8550
+Connection ~ 19450 8550
+$Comp
+L eSim_NPN Q14
+U 1 1 6867315E
+P 24050 8550
+F 0 "Q14" H 23950 8600 50 0000 R CNN
+F 1 "eSim_NPN" H 24000 8700 50 0000 R CNN
+F 2 "" H 24250 8650 29 0000 C CNN
+F 3 "" H 24050 8550 60 0000 C CNN
+ 1 24050 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q15
+U 1 1 68673385
+P 25000 9250
+F 0 "Q15" H 24900 9300 50 0000 R CNN
+F 1 "eSim_NPN" H 24950 9400 50 0000 R CNN
+F 2 "" H 25200 9350 29 0000 C CNN
+F 3 "" H 25000 9250 60 0000 C CNN
+ 1 25000 9250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 24800 9250 24150 9250
+Wire Wire Line
+ 24150 9250 24150 8750
+Wire Wire Line
+ 24400 9250 24400 10000
+Connection ~ 24400 9250
+$Comp
+L resistor R12
+U 1 1 68673627
+P 24350 10100
+F 0 "R12" H 24400 10230 50 0000 C CNN
+F 1 "15k" H 24400 10050 50 0000 C CNN
+F 2 "" H 24400 10080 30 0000 C CNN
+F 3 "" V 24400 10150 30 0000 C CNN
+ 1 24350 10100
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 24400 10300 24400 10800
+Wire Wire Line
+ 24400 10800 26100 10800
+Wire Wire Line
+ 25100 9450 25100 10800
+Connection ~ 25100 10800
+Wire Wire Line
+ 25100 9900 25750 9900
+Wire Wire Line
+ 25750 9900 25750 9700
+Connection ~ 25100 9900
+$Comp
+L eSim_Diode D3
+U 1 1 6867389F
+P 25750 9550
+F 0 "D3" H 25750 9650 50 0000 C CNN
+F 1 "eSim_Diode" H 25750 9450 50 0000 C CNN
+F 2 "" H 25750 9550 60 0000 C CNN
+F 3 "" H 25750 9550 60 0000 C CNN
+ 1 25750 9550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 25750 9400 25750 9100
+Wire Wire Line
+ 24150 5100 24150 8350
+Connection ~ 19450 5500
+Connection ~ 24150 5500
+Wire Wire Line
+ 25100 9050 25100 8250
+Wire Wire Line
+ 25100 8250 25150 8250
+$Comp
+L PORT U1
+U 6 1 68674B11
+P 13200 17700
+F 0 "U1" H 13250 17800 30 0000 C CNN
+F 1 "PORT" H 13200 17700 30 0000 C CNN
+F 2 "" H 13200 17700 60 0000 C CNN
+F 3 "" H 13200 17700 60 0000 C CNN
+ 6 13200 17700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68674F10
+P 17100 17450
+F 0 "U1" H 17150 17550 30 0000 C CNN
+F 1 "PORT" H 17100 17450 30 0000 C CNN
+F 2 "" H 17100 17450 60 0000 C CNN
+F 3 "" H 17100 17450 60 0000 C CNN
+ 5 17100 17450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6867522F
+P 18400 17150
+F 0 "U1" H 18450 17250 30 0000 C CNN
+F 1 "PORT" H 18400 17150 30 0000 C CNN
+F 2 "" H 18400 17150 60 0000 C CNN
+F 3 "" H 18400 17150 60 0000 C CNN
+ 7 18400 17150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68675409
+P 20000 17000
+F 0 "U1" H 20050 17100 30 0000 C CNN
+F 1 "PORT" H 20000 17000 30 0000 C CNN
+F 2 "" H 20000 17000 60 0000 C CNN
+F 3 "" H 20000 17000 60 0000 C CNN
+ 4 20000 17000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6867580E
+P 23450 14250
+F 0 "U1" H 23500 14350 30 0000 C CNN
+F 1 "PORT" H 23450 14250 30 0000 C CNN
+F 2 "" H 23450 14250 60 0000 C CNN
+F 3 "" H 23450 14250 60 0000 C CNN
+ 3 23450 14250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68675AF8
+P 23000 12800
+F 0 "U1" H 23050 12900 30 0000 C CNN
+F 1 "PORT" H 23000 12800 30 0000 C CNN
+F 2 "" H 23000 12800 60 0000 C CNN
+F 3 "" H 23000 12800 60 0000 C CNN
+ 2 23000 12800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68675B85
+P 23350 12250
+F 0 "U1" H 23400 12350 30 0000 C CNN
+F 1 "PORT" H 23350 12250 30 0000 C CNN
+F 2 "" H 23350 12250 60 0000 C CNN
+F 3 "" H 23350 12250 60 0000 C CNN
+ 13 23350 12250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 68675CAE
+P 26350 10800
+F 0 "U1" H 26400 10900 30 0000 C CNN
+F 1 "PORT" H 26350 10800 30 0000 C CNN
+F 2 "" H 26350 10800 60 0000 C CNN
+F 3 "" H 26350 10800 60 0000 C CNN
+ 10 26350 10800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68675EF5
+P 26000 9100
+F 0 "U1" H 26050 9200 30 0000 C CNN
+F 1 "PORT" H 26000 9100 30 0000 C CNN
+F 2 "" H 26000 9100 60 0000 C CNN
+F 3 "" H 26000 9100 60 0000 C CNN
+ 9 26000 9100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68675F94
+P 25400 8250
+F 0 "U1" H 25450 8350 30 0000 C CNN
+F 1 "PORT" H 25400 8250 30 0000 C CNN
+F 2 "" H 25400 8250 60 0000 C CNN
+F 3 "" H 25400 8250 60 0000 C CNN
+ 11 25400 8250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 68676039
+P 24400 5100
+F 0 "U1" H 24450 5200 30 0000 C CNN
+F 1 "PORT" H 24400 5100 30 0000 C CNN
+F 2 "" H 24400 5100 60 0000 C CNN
+F 3 "" H 24400 5100 60 0000 C CNN
+ 12 24400 5100
+ -1 0 0 1
+$EndComp
+Text Label 24150 5350 0 60 ~ 0
+VCC
+Text Label 25100 8550 0 60 ~ 0
+VC
+Text Label 25750 9250 0 60 ~ 0
+VZ
+Text Label 25950 10800 0 60 ~ 0
+VO
+Text Label 22700 12250 0 60 ~ 0
+COMP
+Text Label 22250 12800 0 60 ~ 0
+Curr_lim
+Text Label 22500 14250 0 60 ~ 0
+Curr_sense
+Text Label 20250 16300 0 60 ~ 0
+INV_IN
+Text Label 17350 17050 0 60 ~ 0
+NON_INV_IN
+Text Label 18650 16800 0 60 ~ 0
+VEE
+Text Label 13450 17250 0 60 ~ 0
+VREF
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC1723/MC1723.cir b/library/SubcircuitLibrary/MC1723/MC1723.cir
new file mode 100644
index 000000000..0f19af8fd
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/MC1723.cir
@@ -0,0 +1,44 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1723\MC1723.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/04/25 01:37:30
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+D1 Net-_D1-Pad1_ /VCC eSim_Diode
+R1 /VCC Net-_Q1-Pad3_ 500
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad3_ eSim_PNP
+R2 Net-_Q1-Pad1_ Net-_D1-Pad1_ 15k
+J1 Net-_D1-Pad1_ /VEE /VEE eSim_NJF
+Q3 Net-_C1-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_PNP
+R3 /VCC Net-_Q3-Pad3_ 25k
+Q2 Net-_C1-Pad1_ Net-_C1-Pad2_ /VEE eSim_NPN
+Q4 /VCC Net-_C1-Pad1_ Net-_Q1-Pad1_ eSim_NPN
+Q5 /VCC Net-_Q1-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+R5 Net-_Q5-Pad3_ Net-_D2-Pad2_ 100
+D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode
+R6 Net-_D2-Pad1_ /VEE 5.0k
+R4 Net-_C1-Pad2_ Net-_D2-Pad1_ 30k
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 5.0p
+R8 Net-_Q7-Pad3_ /VEE 300
+Q7 Net-_Q6-Pad1_ Net-_Q10-Pad2_ Net-_Q7-Pad3_ eSim_NPN
+Q6 Net-_Q6-Pad1_ Net-_Q1-Pad1_ Net-_Q6-Pad3_ eSim_PNP
+R7 /VCC Net-_Q6-Pad3_ 1.0k
+Q8 /VCC Net-_Q6-Pad1_ Net-_Q10-Pad2_ eSim_NPN
+R9 Net-_Q10-Pad2_ /VEE 20k
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+R10 Net-_Q10-Pad3_ /VEE 150
+Q9 Net-_Q1-Pad1_ /NON_INV_IN Net-_Q10-Pad1_ eSim_NPN
+Q12 /COMP /INV_IN Net-_Q10-Pad1_ eSim_NPN
+Q11 /COMP Net-_Q1-Pad1_ Net-_Q11-Pad3_ eSim_PNP
+R11 /VCC Net-_Q11-Pad3_ 1.0k
+Q13 /COMP /Curr_lim /Curr_sense eSim_NPN
+Q14 /VCC /COMP Net-_Q14-Pad3_ eSim_NPN
+Q15 /VC Net-_Q14-Pad3_ /VO eSim_NPN
+R12 Net-_Q14-Pad3_ /VO 15k
+D3 /VZ /VO eSim_Diode
+U1 /Curr_lim /Curr_sense /INV_IN /NON_INV_IN /VREF /VEE /VZ /VO /VC /VCC /COMP PORT
+v1 Net-_D2-Pad2_ /VREF DC
+
+.end
diff --git a/library/SubcircuitLibrary/MC1723/MC1723.cir.out b/library/SubcircuitLibrary/MC1723/MC1723.cir.out
new file mode 100644
index 000000000..6d61d06e9
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/MC1723.cir.out
@@ -0,0 +1,49 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc1723\mc1723.cir
+
+.include ZenerD1N750.lib
+.include NPN.lib
+.include NJF.lib
+.include PNP.lib
+d1 net-_d1-pad1_ /vcc D1N750
+r1 /vcc net-_q1-pad3_ 500
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2907A
+r2 net-_q1-pad1_ net-_d1-pad1_ 15k
+j1 net-_d1-pad1_ /vee /vee J2N3819
+q3 net-_c1-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2907A
+r3 /vcc net-_q3-pad3_ 25k
+q2 net-_c1-pad1_ net-_c1-pad2_ /vee Q2N2222
+q4 /vcc net-_c1-pad1_ net-_q1-pad1_ Q2N2222
+q5 /vcc net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+r5 net-_q5-pad3_ net-_d2-pad2_ 100
+d2 net-_d2-pad1_ net-_d2-pad2_ D1N750
+r6 net-_d2-pad1_ /vee 5.0k
+r4 net-_c1-pad2_ net-_d2-pad1_ 30k
+c1 net-_c1-pad1_ net-_c1-pad2_ 5.0p
+r8 net-_q7-pad3_ /vee 300
+q7 net-_q6-pad1_ net-_q10-pad2_ net-_q7-pad3_ Q2N2222
+q6 net-_q6-pad1_ net-_q1-pad1_ net-_q6-pad3_ Q2N2907A
+r7 /vcc net-_q6-pad3_ 1.0k
+q8 /vcc net-_q6-pad1_ net-_q10-pad2_ Q2N2222
+r9 net-_q10-pad2_ /vee 20k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r10 net-_q10-pad3_ /vee 150
+q9 net-_q1-pad1_ /non_inv_in net-_q10-pad1_ Q2N2222
+q12 /comp /inv_in net-_q10-pad1_ Q2N2222
+q11 /comp net-_q1-pad1_ net-_q11-pad3_ Q2N2907A
+r11 /vcc net-_q11-pad3_ 1.0k
+q13 /comp /curr_lim /curr_sense Q2N2222
+q14 /vcc /comp net-_q14-pad3_ Q2N2222
+q15 /vc net-_q14-pad3_ /vo Q2N2222
+r12 net-_q14-pad3_ /vo 15k
+d3 /vz /vo D1N750
+* u1 /curr_lim /curr_sense /inv_in /non_inv_in /vref /vee /vz /vo /vc /vcc /comp port
+v1 net-_d2-pad2_ /vref dc 7
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC1723/MC1723.pro b/library/SubcircuitLibrary/MC1723/MC1723.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/MC1723.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC1723/MC1723.sch b/library/SubcircuitLibrary/MC1723/MC1723.sch
new file mode 100644
index 000000000..162167f0a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/MC1723.sch
@@ -0,0 +1,784 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_Diode D1
+U 1 1 6866D034
+P 5450 7100
+F 0 "D1" H 5450 7200 50 0000 C CNN
+F 1 "eSim_Diode" H 5450 7000 50 0000 C CNN
+F 2 "" H 5450 7100 60 0000 C CNN
+F 3 "" H 5450 7100 60 0000 C CNN
+ 1 5450 7100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R1
+U 1 1 6866D12F
+P 7650 5900
+F 0 "R1" H 7700 6030 50 0000 C CNN
+F 1 "500" H 7700 5850 50 0000 C CNN
+F 2 "" H 7700 5880 30 0000 C CNN
+F 3 "" V 7700 5950 30 0000 C CNN
+ 1 7650 5900
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_PNP Q1
+U 1 1 6866D1B5
+P 7800 7150
+F 0 "Q1" H 7700 7200 50 0000 R CNN
+F 1 "eSim_PNP" H 7750 7300 50 0000 R CNN
+F 2 "" H 8000 7250 29 0000 C CNN
+F 3 "" H 7800 7150 60 0000 C CNN
+ 1 7800 7150
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 6866D242
+P 7650 8350
+F 0 "R2" H 7700 8480 50 0000 C CNN
+F 1 "15k" H 7700 8300 50 0000 C CNN
+F 2 "" H 7700 8330 30 0000 C CNN
+F 3 "" V 7700 8400 30 0000 C CNN
+ 1 7650 8350
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NJF J1
+U 1 1 6866D35B
+P 5700 12650
+F 0 "J1" H 5600 12700 50 0000 R CNN
+F 1 "eSim_NJF" H 5650 12800 50 0000 R CNN
+F 2 "" H 5900 12750 29 0000 C CNN
+F 3 "" H 5700 12650 60 0000 C CNN
+ 1 5700 12650
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q3
+U 1 1 6866D540
+P 10100 7150
+F 0 "Q3" H 10000 7200 50 0000 R CNN
+F 1 "eSim_PNP" H 10050 7300 50 0000 R CNN
+F 2 "" H 10300 7250 29 0000 C CNN
+F 3 "" H 10100 7150 60 0000 C CNN
+ 1 10100 7150
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 6866D698
+P 10150 6050
+F 0 "R3" H 10200 6180 50 0000 C CNN
+F 1 "25k" H 10200 6000 50 0000 C CNN
+F 2 "" H 10200 6030 30 0000 C CNN
+F 3 "" V 10200 6100 30 0000 C CNN
+ 1 10150 6050
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 6866D973
+P 8400 15050
+F 0 "Q2" H 8300 15100 50 0000 R CNN
+F 1 "eSim_NPN" H 8350 15200 50 0000 R CNN
+F 2 "" H 8600 15150 29 0000 C CNN
+F 3 "" H 8400 15050 60 0000 C CNN
+ 1 8400 15050
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 6866DA95
+P 11200 9550
+F 0 "Q4" H 11100 9600 50 0000 R CNN
+F 1 "eSim_NPN" H 11150 9700 50 0000 R CNN
+F 2 "" H 11400 9650 29 0000 C CNN
+F 3 "" H 11200 9550 60 0000 C CNN
+ 1 11200 9550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 6866DAFC
+P 12500 10800
+F 0 "Q5" H 12400 10850 50 0000 R CNN
+F 1 "eSim_NPN" H 12450 10950 50 0000 R CNN
+F 2 "" H 12700 10900 29 0000 C CNN
+F 3 "" H 12500 10800 60 0000 C CNN
+ 1 12500 10800
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R5
+U 1 1 6866DF63
+P 12550 12050
+F 0 "R5" H 12600 12180 50 0000 C CNN
+F 1 "100" H 12600 12000 50 0000 C CNN
+F 2 "" H 12600 12030 30 0000 C CNN
+F 3 "" V 12600 12100 30 0000 C CNN
+ 1 12550 12050
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 6866E068
+P 12600 12750
+F 0 "D2" H 12600 12850 50 0000 C CNN
+F 1 "eSim_Diode" H 12600 12650 50 0000 C CNN
+F 2 "" H 12600 12750 60 0000 C CNN
+F 3 "" H 12600 12750 60 0000 C CNN
+ 1 12600 12750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R6
+U 1 1 6866E0F8
+P 12550 14300
+F 0 "R6" H 12600 14430 50 0000 C CNN
+F 1 "5.0k" H 12600 14250 50 0000 C CNN
+F 2 "" H 12600 14280 30 0000 C CNN
+F 3 "" V 12600 14350 30 0000 C CNN
+ 1 12550 14300
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 6866E39B
+P 10500 14000
+F 0 "R4" H 10550 14130 50 0000 C CNN
+F 1 "30k" H 10550 13950 50 0000 C CNN
+F 2 "" H 10550 13980 30 0000 C CNN
+F 3 "" V 10550 14050 30 0000 C CNN
+ 1 10500 14000
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor_polarised C1
+U 1 1 6866E601
+P 9150 13550
+F 0 "C1" H 9175 13650 50 0000 L CNN
+F 1 "5.0p" H 9175 13450 50 0000 L CNN
+F 2 "" H 9150 13550 50 0001 C CNN
+F 3 "" H 9150 13550 50 0001 C CNN
+ 1 9150 13550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5450 6950 5450 5500
+Wire Wire Line
+ 5450 5500 24150 5500
+Wire Wire Line
+ 7700 5500 7700 5800
+Wire Wire Line
+ 7700 6950 7700 6100
+Wire Wire Line
+ 7700 7350 7700 8250
+Wire Wire Line
+ 7700 8550 7700 8900
+Wire Wire Line
+ 7700 8900 5450 8900
+Wire Wire Line
+ 5450 7250 5450 9250
+Wire Wire Line
+ 5600 12450 5600 9250
+Wire Wire Line
+ 5600 9250 5450 9250
+Connection ~ 5450 8900
+Wire Wire Line
+ 5600 12850 5600 16350
+Wire Wire Line
+ 5600 16350 18650 16350
+Wire Wire Line
+ 18650 14900 18650 17150
+Wire Wire Line
+ 8000 7150 9900 7150
+Wire Wire Line
+ 8800 7150 8800 7800
+Wire Wire Line
+ 8800 7800 7700 7800
+Connection ~ 7700 7800
+Connection ~ 8800 7150
+Wire Wire Line
+ 10200 6950 10200 6250
+Wire Wire Line
+ 10200 5500 10200 5950
+Connection ~ 7700 5500
+Wire Wire Line
+ 5900 12650 6850 12650
+Wire Wire Line
+ 6850 12650 6850 16350
+Connection ~ 6850 16350
+Wire Wire Line
+ 8300 15250 8300 16350
+Connection ~ 8300 16350
+Wire Wire Line
+ 8300 9550 8300 14850
+Wire Wire Line
+ 8300 9550 11000 9550
+Wire Wire Line
+ 10200 7350 10200 9550
+Connection ~ 10200 9550
+Wire Wire Line
+ 11300 5500 11300 9350
+Connection ~ 10200 5500
+Wire Wire Line
+ 12300 10800 11300 10800
+Wire Wire Line
+ 11300 10800 11300 9750
+Wire Wire Line
+ 12600 11950 12600 11000
+Wire Wire Line
+ 12600 12250 12600 12600
+Wire Wire Line
+ 12600 12900 12600 14200
+Wire Wire Line
+ 8600 15050 9700 15050
+Wire Wire Line
+ 9700 15050 9700 14000
+Wire Wire Line
+ 9700 14000 10400 14000
+Wire Wire Line
+ 10400 14000 10400 13950
+Wire Wire Line
+ 10700 13950 12600 13950
+Connection ~ 12600 13950
+Wire Wire Line
+ 9150 13700 9150 15050
+Connection ~ 9150 15050
+Wire Wire Line
+ 9150 13400 9150 13000
+Wire Wire Line
+ 9150 13000 8300 13000
+Connection ~ 8300 13000
+Wire Wire Line
+ 12600 14500 12600 16350
+Connection ~ 12600 16350
+Wire Wire Line
+ 12600 12400 13450 12400
+Connection ~ 12600 12400
+Wire Wire Line
+ 12600 5500 12600 10600
+Connection ~ 11300 5500
+$Comp
+L resistor R8
+U 1 1 6866ED9A
+P 14700 15200
+F 0 "R8" H 14750 15330 50 0000 C CNN
+F 1 "300" H 14750 15150 50 0000 C CNN
+F 2 "" H 14750 15180 30 0000 C CNN
+F 3 "" V 14750 15250 30 0000 C CNN
+ 1 14700 15200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 6866EE4C
+P 14850 13700
+F 0 "Q7" H 14750 13750 50 0000 R CNN
+F 1 "eSim_NPN" H 14800 13850 50 0000 R CNN
+F 2 "" H 15050 13800 29 0000 C CNN
+F 3 "" H 14850 13700 60 0000 C CNN
+ 1 14850 13700
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 14750 15100 14750 13900
+Wire Wire Line
+ 14750 15400 14750 16350
+Connection ~ 14750 16350
+$Comp
+L eSim_PNP Q6
+U 1 1 6866F0B6
+P 14650 7100
+F 0 "Q6" H 14550 7150 50 0000 R CNN
+F 1 "eSim_PNP" H 14600 7250 50 0000 R CNN
+F 2 "" H 14850 7200 29 0000 C CNN
+F 3 "" H 14650 7100 60 0000 C CNN
+ 1 14650 7100
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 14750 7300 14750 13500
+$Comp
+L resistor R7
+U 1 1 6866F697
+P 14700 6100
+F 0 "R7" H 14750 6230 50 0000 C CNN
+F 1 "1.0k" H 14750 6050 50 0000 C CNN
+F 2 "" H 14750 6080 30 0000 C CNN
+F 3 "" V 14750 6150 30 0000 C CNN
+ 1 14700 6100
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 14750 6900 14750 6300
+Wire Wire Line
+ 14750 5500 14750 6000
+Connection ~ 12600 5500
+Wire Wire Line
+ 9500 7150 9500 7550
+Wire Wire Line
+ 9500 7550 18800 7550
+Wire Wire Line
+ 13200 7550 13200 7100
+Wire Wire Line
+ 13200 7100 14450 7100
+Connection ~ 9500 7150
+Wire Wire Line
+ 14750 11150 16100 11150
+Connection ~ 14750 11150
+$Comp
+L eSim_NPN Q8
+U 1 1 6866FC42
+P 16300 11150
+F 0 "Q8" H 16200 11200 50 0000 R CNN
+F 1 "eSim_NPN" H 16250 11300 50 0000 R CNN
+F 2 "" H 16500 11250 29 0000 C CNN
+F 3 "" H 16300 11150 60 0000 C CNN
+ 1 16300 11150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 16400 11350 16400 14700
+Wire Wire Line
+ 15050 13700 18350 13700
+Connection ~ 16400 13700
+$Comp
+L resistor R9
+U 1 1 6866FF68
+P 16350 14800
+F 0 "R9" H 16400 14930 50 0000 C CNN
+F 1 "20k" H 16400 14750 50 0000 C CNN
+F 2 "" H 16400 14780 30 0000 C CNN
+F 3 "" V 16400 14850 30 0000 C CNN
+ 1 16350 14800
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 16400 15000 16400 16350
+Connection ~ 16400 16350
+$Comp
+L eSim_NPN Q10
+U 1 1 68670127
+P 18550 13700
+F 0 "Q10" H 18450 13750 50 0000 R CNN
+F 1 "eSim_NPN" H 18500 13850 50 0000 R CNN
+F 2 "" H 18750 13800 29 0000 C CNN
+F 3 "" H 18550 13700 60 0000 C CNN
+ 1 18550 13700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 18650 13900 18650 14600
+$Comp
+L resistor R10
+U 1 1 68670483
+P 18600 14700
+F 0 "R10" H 18650 14830 50 0000 C CNN
+F 1 "150" H 18650 14650 50 0000 C CNN
+F 2 "" H 18650 14680 30 0000 C CNN
+F 3 "" V 18650 14750 30 0000 C CNN
+ 1 18600 14700
+ 0 1 1 0
+$EndComp
+Connection ~ 18650 16350
+Wire Wire Line
+ 16400 5500 16400 10950
+Connection ~ 14750 5500
+$Comp
+L eSim_NPN Q9
+U 1 1 68670B38
+P 18000 11100
+F 0 "Q9" H 17900 11150 50 0000 R CNN
+F 1 "eSim_NPN" H 17950 11250 50 0000 R CNN
+F 2 "" H 18200 11200 29 0000 C CNN
+F 3 "" H 18000 11100 60 0000 C CNN
+ 1 18000 11100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q12
+U 1 1 68670C29
+P 19550 11100
+F 0 "Q12" H 19450 11150 50 0000 R CNN
+F 1 "eSim_NPN" H 19500 11250 50 0000 R CNN
+F 2 "" H 19750 11200 29 0000 C CNN
+F 3 "" H 19550 11100 60 0000 C CNN
+ 1 19550 11100
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 18100 11300 18100 11700
+Wire Wire Line
+ 18100 11700 19450 11700
+Wire Wire Line
+ 19450 11700 19450 11300
+Wire Wire Line
+ 18650 13500 18650 11700
+Connection ~ 18650 11700
+Wire Wire Line
+ 17800 11100 17350 11100
+Wire Wire Line
+ 17350 11100 17350 17450
+Wire Wire Line
+ 18100 7550 18100 10900
+Wire Wire Line
+ 18100 10050 11600 10050
+Wire Wire Line
+ 11600 10050 11600 10800
+Connection ~ 11600 10800
+$Comp
+L eSim_PNP Q11
+U 1 1 686717D7
+P 19350 7350
+F 0 "Q11" H 19250 7400 50 0000 R CNN
+F 1 "eSim_PNP" H 19300 7500 50 0000 R CNN
+F 2 "" H 19550 7450 29 0000 C CNN
+F 3 "" H 19350 7350 60 0000 C CNN
+ 1 19350 7350
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R11
+U 1 1 6867192A
+P 19400 6400
+F 0 "R11" H 19450 6530 50 0000 C CNN
+F 1 "1.0k" H 19450 6350 50 0000 C CNN
+F 2 "" H 19450 6380 30 0000 C CNN
+F 3 "" V 19450 6450 30 0000 C CNN
+ 1 19400 6400
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 19450 7150 19450 6600
+Wire Wire Line
+ 19450 5500 19450 6300
+Connection ~ 16400 5500
+Wire Wire Line
+ 19450 10900 19450 7550
+Wire Wire Line
+ 18800 7550 18800 7350
+Wire Wire Line
+ 18800 7350 19150 7350
+Connection ~ 13200 7550
+Connection ~ 18100 7550
+Connection ~ 18100 10050
+Wire Wire Line
+ 19750 11100 20250 11100
+Wire Wire Line
+ 20250 11100 20250 17000
+Wire Wire Line
+ 19450 9600 21350 9600
+Wire Wire Line
+ 21350 9600 21350 12600
+Connection ~ 19450 9600
+$Comp
+L eSim_NPN Q13
+U 1 1 686728F4
+P 21450 12800
+F 0 "Q13" H 21350 12850 50 0000 R CNN
+F 1 "eSim_NPN" H 21400 12950 50 0000 R CNN
+F 2 "" H 21650 12900 29 0000 C CNN
+F 3 "" H 21450 12800 60 0000 C CNN
+ 1 21450 12800
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 21350 13000 21350 14250
+Wire Wire Line
+ 21350 14250 23200 14250
+Wire Wire Line
+ 21650 12800 22750 12800
+Wire Wire Line
+ 21350 12250 23100 12250
+Connection ~ 21350 12250
+Wire Wire Line
+ 19450 8550 23850 8550
+Connection ~ 19450 8550
+$Comp
+L eSim_NPN Q14
+U 1 1 6867315E
+P 24050 8550
+F 0 "Q14" H 23950 8600 50 0000 R CNN
+F 1 "eSim_NPN" H 24000 8700 50 0000 R CNN
+F 2 "" H 24250 8650 29 0000 C CNN
+F 3 "" H 24050 8550 60 0000 C CNN
+ 1 24050 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q15
+U 1 1 68673385
+P 25000 9250
+F 0 "Q15" H 24900 9300 50 0000 R CNN
+F 1 "eSim_NPN" H 24950 9400 50 0000 R CNN
+F 2 "" H 25200 9350 29 0000 C CNN
+F 3 "" H 25000 9250 60 0000 C CNN
+ 1 25000 9250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 24800 9250 24150 9250
+Wire Wire Line
+ 24150 9250 24150 8750
+Wire Wire Line
+ 24400 9250 24400 10000
+Connection ~ 24400 9250
+$Comp
+L resistor R12
+U 1 1 68673627
+P 24350 10100
+F 0 "R12" H 24400 10230 50 0000 C CNN
+F 1 "15k" H 24400 10050 50 0000 C CNN
+F 2 "" H 24400 10080 30 0000 C CNN
+F 3 "" V 24400 10150 30 0000 C CNN
+ 1 24350 10100
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 24400 10300 24400 10800
+Wire Wire Line
+ 24400 10800 26100 10800
+Wire Wire Line
+ 25100 9450 25100 10800
+Connection ~ 25100 10800
+Wire Wire Line
+ 25100 9900 25750 9900
+Wire Wire Line
+ 25750 9900 25750 9700
+Connection ~ 25100 9900
+$Comp
+L eSim_Diode D3
+U 1 1 6867389F
+P 25750 9550
+F 0 "D3" H 25750 9650 50 0000 C CNN
+F 1 "eSim_Diode" H 25750 9450 50 0000 C CNN
+F 2 "" H 25750 9550 60 0000 C CNN
+F 3 "" H 25750 9550 60 0000 C CNN
+ 1 25750 9550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 25750 9400 25750 9100
+Wire Wire Line
+ 24150 5100 24150 8350
+Connection ~ 19450 5500
+Connection ~ 24150 5500
+Wire Wire Line
+ 25100 9050 25100 8250
+Wire Wire Line
+ 25100 8250 25150 8250
+$Comp
+L PORT U1
+U 6 1 68674B11
+P 13200 17700
+F 0 "U1" H 13250 17800 30 0000 C CNN
+F 1 "PORT" H 13200 17700 30 0000 C CNN
+F 2 "" H 13200 17700 60 0000 C CNN
+F 3 "" H 13200 17700 60 0000 C CNN
+ 6 13200 17700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68674F10
+P 17100 17450
+F 0 "U1" H 17150 17550 30 0000 C CNN
+F 1 "PORT" H 17100 17450 30 0000 C CNN
+F 2 "" H 17100 17450 60 0000 C CNN
+F 3 "" H 17100 17450 60 0000 C CNN
+ 5 17100 17450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6867522F
+P 18400 17150
+F 0 "U1" H 18450 17250 30 0000 C CNN
+F 1 "PORT" H 18400 17150 30 0000 C CNN
+F 2 "" H 18400 17150 60 0000 C CNN
+F 3 "" H 18400 17150 60 0000 C CNN
+ 7 18400 17150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68675409
+P 20000 17000
+F 0 "U1" H 20050 17100 30 0000 C CNN
+F 1 "PORT" H 20000 17000 30 0000 C CNN
+F 2 "" H 20000 17000 60 0000 C CNN
+F 3 "" H 20000 17000 60 0000 C CNN
+ 4 20000 17000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6867580E
+P 23450 14250
+F 0 "U1" H 23500 14350 30 0000 C CNN
+F 1 "PORT" H 23450 14250 30 0000 C CNN
+F 2 "" H 23450 14250 60 0000 C CNN
+F 3 "" H 23450 14250 60 0000 C CNN
+ 3 23450 14250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68675AF8
+P 23000 12800
+F 0 "U1" H 23050 12900 30 0000 C CNN
+F 1 "PORT" H 23000 12800 30 0000 C CNN
+F 2 "" H 23000 12800 60 0000 C CNN
+F 3 "" H 23000 12800 60 0000 C CNN
+ 2 23000 12800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68675B85
+P 23350 12250
+F 0 "U1" H 23400 12350 30 0000 C CNN
+F 1 "PORT" H 23350 12250 30 0000 C CNN
+F 2 "" H 23350 12250 60 0000 C CNN
+F 3 "" H 23350 12250 60 0000 C CNN
+ 13 23350 12250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 68675CAE
+P 26350 10800
+F 0 "U1" H 26400 10900 30 0000 C CNN
+F 1 "PORT" H 26350 10800 30 0000 C CNN
+F 2 "" H 26350 10800 60 0000 C CNN
+F 3 "" H 26350 10800 60 0000 C CNN
+ 10 26350 10800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68675EF5
+P 26000 9100
+F 0 "U1" H 26050 9200 30 0000 C CNN
+F 1 "PORT" H 26000 9100 30 0000 C CNN
+F 2 "" H 26000 9100 60 0000 C CNN
+F 3 "" H 26000 9100 60 0000 C CNN
+ 9 26000 9100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68675F94
+P 25400 8250
+F 0 "U1" H 25450 8350 30 0000 C CNN
+F 1 "PORT" H 25400 8250 30 0000 C CNN
+F 2 "" H 25400 8250 60 0000 C CNN
+F 3 "" H 25400 8250 60 0000 C CNN
+ 11 25400 8250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 68676039
+P 24400 5100
+F 0 "U1" H 24450 5200 30 0000 C CNN
+F 1 "PORT" H 24400 5100 30 0000 C CNN
+F 2 "" H 24400 5100 60 0000 C CNN
+F 3 "" H 24400 5100 60 0000 C CNN
+ 12 24400 5100
+ -1 0 0 1
+$EndComp
+Text Label 24150 5350 0 60 ~ 0
+VCC
+Text Label 25100 8550 0 60 ~ 0
+VC
+Text Label 25750 9250 0 60 ~ 0
+VZ
+Text Label 25950 10800 0 60 ~ 0
+VO
+Text Label 22700 12250 0 60 ~ 0
+COMP
+Text Label 22250 12800 0 60 ~ 0
+Curr_lim
+Text Label 22500 14250 0 60 ~ 0
+Curr_sense
+Text Label 20250 16300 0 60 ~ 0
+INV_IN
+Text Label 17350 17050 0 60 ~ 0
+NON_INV_IN
+Text Label 18650 16800 0 60 ~ 0
+VEE
+Text Label 13450 17250 0 60 ~ 0
+VREF
+$Comp
+L DC v1
+U 1 1 6867CB7E
+P 13450 15750
+F 0 "v1" H 13250 15850 60 0000 C CNN
+F 1 "DC" H 13250 15700 60 0000 C CNN
+F 2 "R1" H 13150 15750 60 0000 C CNN
+F 3 "" H 13450 15750 60 0000 C CNN
+ 1 13450 15750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 13450 16200 13450 17700
+Wire Wire Line
+ 13450 12400 13450 15300
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC1723/MC1723.sub b/library/SubcircuitLibrary/MC1723/MC1723.sub
new file mode 100644
index 000000000..083f3dd2c
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/MC1723.sub
@@ -0,0 +1,43 @@
+* Subcircuit MC1723
+.subckt MC1723 /curr_lim /curr_sense /inv_in /non_inv_in /vref /vee /vz /vo /vc /vcc /comp
+* c:\fossee\esim\library\subcircuitlibrary\mc1723\mc1723.cir
+.include ZenerD1N750.lib
+.include NPN.lib
+.include NJF.lib
+.include PNP.lib
+d1 net-_d1-pad1_ /vcc D1N750
+r1 /vcc net-_q1-pad3_ 500
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2907A
+r2 net-_q1-pad1_ net-_d1-pad1_ 15k
+j1 net-_d1-pad1_ /vee /vee J2N3819
+q3 net-_c1-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2907A
+r3 /vcc net-_q3-pad3_ 25k
+q2 net-_c1-pad1_ net-_c1-pad2_ /vee Q2N2222
+q4 /vcc net-_c1-pad1_ net-_q1-pad1_ Q2N2222
+q5 /vcc net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+r5 net-_q5-pad3_ net-_d2-pad2_ 100
+d2 net-_d2-pad1_ net-_d2-pad2_ D1N750
+r6 net-_d2-pad1_ /vee 5.0k
+r4 net-_c1-pad2_ net-_d2-pad1_ 30k
+c1 net-_c1-pad1_ net-_c1-pad2_ 5.0p
+r8 net-_q7-pad3_ /vee 300
+q7 net-_q6-pad1_ net-_q10-pad2_ net-_q7-pad3_ Q2N2222
+q6 net-_q6-pad1_ net-_q1-pad1_ net-_q6-pad3_ Q2N2907A
+r7 /vcc net-_q6-pad3_ 1.0k
+q8 /vcc net-_q6-pad1_ net-_q10-pad2_ Q2N2222
+r9 net-_q10-pad2_ /vee 20k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r10 net-_q10-pad3_ /vee 150
+q9 net-_q1-pad1_ /non_inv_in net-_q10-pad1_ Q2N2222
+q12 /comp /inv_in net-_q10-pad1_ Q2N2222
+q11 /comp net-_q1-pad1_ net-_q11-pad3_ Q2N2907A
+r11 /vcc net-_q11-pad3_ 1.0k
+q13 /comp /curr_lim /curr_sense Q2N2222
+q14 /vcc /comp net-_q14-pad3_ Q2N2222
+q15 /vc net-_q14-pad3_ /vo Q2N2222
+r12 net-_q14-pad3_ /vo 15k
+d3 /vz /vo D1N750
+v1 net-_d2-pad2_ /vref dc 7
+* Control Statements
+
+.ends MC1723
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC1723/MC1723_Previous_Values.xml b/library/SubcircuitLibrary/MC1723/MC1723_Previous_Values.xml
new file mode 100644
index 000000000..26178a282
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/MC1723_Previous_Values.xml
@@ -0,0 +1 @@
+dc7C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC1723/NJF.lib b/library/SubcircuitLibrary/MC1723/NJF.lib
new file mode 100644
index 000000000..dbb2cbae5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/NJF.lib
@@ -0,0 +1,4 @@
+.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3
++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u
++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18
++ Af=1)
diff --git a/library/SubcircuitLibrary/MC1723/NPN.lib b/library/SubcircuitLibrary/MC1723/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/MC1723/PNP.lib b/library/SubcircuitLibrary/MC1723/PNP.lib
new file mode 100644
index 000000000..7edda0eab
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/MC1723/ZenerD1N750.lib b/library/SubcircuitLibrary/MC1723/ZenerD1N750.lib
new file mode 100644
index 000000000..890c37fe2
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/ZenerD1N750.lib
@@ -0,0 +1,3 @@
+.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516
++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m
++ Nbvl=14.976 Tbv1=-21.277u)
diff --git a/library/SubcircuitLibrary/MC1723/analysis b/library/SubcircuitLibrary/MC1723/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1723/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC3340/D.lib b/library/SubcircuitLibrary/MC3340/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/MC3340/MC3340-cache.lib b/library/SubcircuitLibrary/MC3340/MC3340-cache.lib
new file mode 100644
index 000000000..6615a3fcb
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340-cache.lib
@@ -0,0 +1,120 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.cir b/library/SubcircuitLibrary/MC3340/MC3340.cir
new file mode 100644
index 000000000..04864799d
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.cir
@@ -0,0 +1,40 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC3340\MC3340.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/05/25 17:24:07
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ 5.1K
+R2 Net-_Q1-Pad2_ GND 4.7K
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 750
+R4 Net-_Q2-Pad2_ GND 10K
+Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+R6 Net-_Q1-Pad3_ Net-_Q3-Pad2_ 750
+R7 Net-_Q3-Pad2_ Net-_R7-Pad2_ 3.9K
+Q3 Net-_Q1-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
+R8 Net-_Q1-Pad1_ Net-_R5-Pad2_ 5.1K
+Q4 Net-_Q1-Pad1_ Net-_Q3-Pad3_ Net-_Q4-Pad3_ eSim_NPN
+Q6 Net-_Q10-Pad2_ Net-_Q2-Pad3_ Net-_Q4-Pad3_ eSim_NPN
+Q7 Net-_Q1-Pad1_ Net-_Q2-Pad3_ Net-_Q7-Pad3_ eSim_NPN
+Q9 Net-_Q9-Pad1_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN
+R13 Net-_Q1-Pad1_ Net-_Q9-Pad1_ 6.2k
+Q10 Net-_Q1-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+R15 Net-_Q10-Pad3_ GND 5.1k
+R16 Net-_Q1-Pad1_ Net-_D1-Pad1_ 5.1k
+R11 Net-_Q2-Pad3_ GND 5.1k
+R14 Net-_Q3-Pad3_ GND 5.1k
+R18 Net-_R18-Pad1_ Net-_Q10-Pad3_ 200
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+R17 Net-_D1-Pad2_ GND 510
+Q8 Net-_Q7-Pad3_ Net-_D1-Pad1_ Net-_Q8-Pad3_ eSim_NPN
+R12 Net-_Q8-Pad3_ GND 1.5k
+Q5 Net-_Q4-Pad3_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN
+R10 Net-_Q5-Pad3_ GND 1.3k
+R5 Net-_Q5-Pad2_ Net-_R5-Pad2_ 20K
+R9 Net-_R5-Pad2_ GND 510
+U1 Net-_Q5-Pad2_ Net-_R7-Pad2_ ? ? ? Net-_Q10-Pad2_ Net-_R18-Pad1_ Net-_Q1-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.cir.out b/library/SubcircuitLibrary/MC3340/MC3340.cir.out
new file mode 100644
index 000000000..aaddad9d0
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.cir.out
@@ -0,0 +1,43 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc3340\mc3340.cir
+
+.include D.lib
+.include NPN.lib
+r1 net-_q1-pad1_ net-_q1-pad2_ 5.1k
+r2 net-_q1-pad2_ gnd 4.7k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r3 net-_q1-pad3_ net-_q2-pad2_ 750
+r4 net-_q2-pad2_ gnd 10k
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+r6 net-_q1-pad3_ net-_q3-pad2_ 750
+r7 net-_q3-pad2_ net-_r7-pad2_ 3.9k
+q3 net-_q1-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+r8 net-_q1-pad1_ net-_r5-pad2_ 5.1k
+q4 net-_q1-pad1_ net-_q3-pad3_ net-_q4-pad3_ Q2N2222
+q6 net-_q10-pad2_ net-_q2-pad3_ net-_q4-pad3_ Q2N2222
+q7 net-_q1-pad1_ net-_q2-pad3_ net-_q7-pad3_ Q2N2222
+q9 net-_q9-pad1_ net-_q3-pad3_ net-_q7-pad3_ Q2N2222
+r13 net-_q1-pad1_ net-_q9-pad1_ 6.2k
+q10 net-_q1-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r15 net-_q10-pad3_ gnd 5.1k
+r16 net-_q1-pad1_ net-_d1-pad1_ 5.1k
+r11 net-_q2-pad3_ gnd 5.1k
+r14 net-_q3-pad3_ gnd 5.1k
+r18 net-_r18-pad1_ net-_q10-pad3_ 200
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r17 net-_d1-pad2_ gnd 510
+q8 net-_q7-pad3_ net-_d1-pad1_ net-_q8-pad3_ Q2N2222
+r12 net-_q8-pad3_ gnd 1.5k
+q5 net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222
+r10 net-_q5-pad3_ gnd 1.3k
+r5 net-_q5-pad2_ net-_r5-pad2_ 20k
+r9 net-_r5-pad2_ gnd 510
+* u1 net-_q5-pad2_ net-_r7-pad2_ ? ? ? net-_q10-pad2_ net-_r18-pad1_ net-_q1-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.pro b/library/SubcircuitLibrary/MC3340/MC3340.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.proj b/library/SubcircuitLibrary/MC3340/MC3340.proj
new file mode 100644
index 000000000..8ac98f15e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.proj
@@ -0,0 +1 @@
+schematicFile MC3340.sch
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.sch b/library/SubcircuitLibrary/MC3340/MC3340.sch
new file mode 100644
index 000000000..9a72dc614
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.sch
@@ -0,0 +1,715 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 6840219C
+P 1900 1850
+F 0 "R1" H 1950 1980 50 0000 C CNN
+F 1 "5.1K" H 1950 1800 50 0000 C CNN
+F 2 "" H 1950 1830 30 0000 C CNN
+F 3 "" V 1950 1900 30 0000 C CNN
+ 1 1900 1850
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R2
+U 1 1 684022BB
+P 1900 2400
+F 0 "R2" H 1950 2530 50 0000 C CNN
+F 1 "4.7K" H 1950 2350 50 0000 C CNN
+F 2 "" H 1950 2380 30 0000 C CNN
+F 3 "" V 1950 2450 30 0000 C CNN
+ 1 1900 2400
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 684022DD
+P 2500 2200
+F 0 "Q1" H 2400 2250 50 0000 R CNN
+F 1 "eSim_NPN" H 2450 2350 50 0000 R CNN
+F 2 "" H 2700 2300 29 0000 C CNN
+F 3 "" H 2500 2200 60 0000 C CNN
+ 1 2500 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 68402320
+P 2800 2750
+F 0 "R3" H 2850 2880 50 0000 C CNN
+F 1 "750" H 2850 2700 50 0000 C CNN
+F 2 "" H 2850 2730 30 0000 C CNN
+F 3 "" V 2850 2800 30 0000 C CNN
+ 1 2800 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 68402512
+P 2800 3300
+F 0 "R4" H 2850 3430 50 0000 C CNN
+F 1 "10K" H 2850 3250 50 0000 C CNN
+F 2 "" H 2850 3280 30 0000 C CNN
+F 3 "" V 2850 3350 30 0000 C CNN
+ 1 2800 3300
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 6840255A
+P 1950 2800
+F 0 "#PWR01" H 1950 2550 50 0001 C CNN
+F 1 "eSim_GND" H 1950 2650 50 0000 C CNN
+F 2 "" H 1950 2800 50 0001 C CNN
+F 3 "" H 1950 2800 50 0001 C CNN
+ 1 1950 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 684025CC
+P 2850 3650
+F 0 "#PWR02" H 2850 3400 50 0001 C CNN
+F 1 "eSim_GND" H 2850 3500 50 0000 C CNN
+F 2 "" H 2850 3650 50 0001 C CNN
+F 3 "" H 2850 3650 50 0001 C CNN
+ 1 2850 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 684025F7
+P 3400 3100
+F 0 "Q2" H 3300 3150 50 0000 R CNN
+F 1 "eSim_NPN" H 3350 3250 50 0000 R CNN
+F 2 "" H 3600 3200 29 0000 C CNN
+F 3 "" H 3400 3100 60 0000 C CNN
+ 1 3400 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R6
+U 1 1 684027FF
+P 3850 2750
+F 0 "R6" H 3900 2880 50 0000 C CNN
+F 1 "750" H 3900 2700 50 0000 C CNN
+F 2 "" H 3900 2730 30 0000 C CNN
+F 3 "" V 3900 2800 30 0000 C CNN
+ 1 3850 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R7
+U 1 1 6840283A
+P 3850 3350
+F 0 "R7" H 3900 3480 50 0000 C CNN
+F 1 "3.9K" H 3900 3300 50 0000 C CNN
+F 2 "" H 3900 3330 30 0000 C CNN
+F 3 "" V 3900 3400 30 0000 C CNN
+ 1 3850 3350
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 684028AE
+P 4450 3050
+F 0 "Q3" H 4350 3100 50 0000 R CNN
+F 1 "eSim_NPN" H 4400 3200 50 0000 R CNN
+F 2 "" H 4650 3150 29 0000 C CNN
+F 3 "" H 4450 3050 60 0000 C CNN
+ 1 4450 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R8
+U 1 1 6840290F
+P 4100 1650
+F 0 "R8" H 4150 1780 50 0000 C CNN
+F 1 "5.1K" H 4150 1600 50 0000 C CNN
+F 2 "" H 4150 1630 30 0000 C CNN
+F 3 "" V 4150 1700 30 0000 C CNN
+ 1 4100 1650
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 68402ECE
+P 5000 3350
+F 0 "Q4" H 4900 3400 50 0000 R CNN
+F 1 "eSim_NPN" H 4950 3500 50 0000 R CNN
+F 2 "" H 5200 3450 29 0000 C CNN
+F 3 "" H 5000 3350 60 0000 C CNN
+ 1 5000 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 68402F17
+P 5650 3350
+F 0 "Q6" H 5550 3400 50 0000 R CNN
+F 1 "eSim_NPN" H 5600 3500 50 0000 R CNN
+F 2 "" H 5850 3450 29 0000 C CNN
+F 3 "" H 5650 3350 60 0000 C CNN
+ 1 5650 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 68403375
+P 6550 3350
+F 0 "Q7" H 6450 3400 50 0000 R CNN
+F 1 "eSim_NPN" H 6500 3500 50 0000 R CNN
+F 2 "" H 6750 3450 29 0000 C CNN
+F 3 "" H 6550 3350 60 0000 C CNN
+ 1 6550 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 6840337B
+P 7200 3350
+F 0 "Q9" H 7100 3400 50 0000 R CNN
+F 1 "eSim_NPN" H 7150 3500 50 0000 R CNN
+F 2 "" H 7400 3450 29 0000 C CNN
+F 3 "" H 7200 3350 60 0000 C CNN
+ 1 7200 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R13
+U 1 1 68403469
+P 7050 1550
+F 0 "R13" H 7100 1680 50 0000 C CNN
+F 1 "6.2k" H 7100 1500 50 0000 C CNN
+F 2 "" H 7100 1530 30 0000 C CNN
+F 3 "" V 7100 1600 30 0000 C CNN
+ 1 7050 1550
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q10
+U 1 1 6840352A
+P 7550 2050
+F 0 "Q10" H 7450 2100 50 0000 R CNN
+F 1 "eSim_NPN" H 7500 2200 50 0000 R CNN
+F 2 "" H 7750 2150 29 0000 C CNN
+F 3 "" H 7550 2050 60 0000 C CNN
+ 1 7550 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R15
+U 1 1 68403613
+P 7600 2500
+F 0 "R15" H 7650 2630 50 0000 C CNN
+F 1 "5.1k" H 7650 2450 50 0000 C CNN
+F 2 "" H 7650 2480 30 0000 C CNN
+F 3 "" V 7650 2550 30 0000 C CNN
+ 1 7600 2500
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 684036A1
+P 7650 2850
+F 0 "#PWR03" H 7650 2600 50 0001 C CNN
+F 1 "eSim_GND" H 7650 2700 50 0000 C CNN
+F 2 "" H 7650 2850 50 0001 C CNN
+F 3 "" H 7650 2850 50 0001 C CNN
+ 1 7650 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R16
+U 1 1 6840371B
+P 8000 1600
+F 0 "R16" H 8050 1730 50 0000 C CNN
+F 1 "5.1k" H 8050 1550 50 0000 C CNN
+F 2 "" H 8050 1580 30 0000 C CNN
+F 3 "" V 8050 1650 30 0000 C CNN
+ 1 8000 1600
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R11
+U 1 1 68403A34
+P 6050 3800
+F 0 "R11" H 6100 3930 50 0000 C CNN
+F 1 "5.1k" H 6100 3750 50 0000 C CNN
+F 2 "" H 6100 3780 30 0000 C CNN
+F 3 "" V 6100 3850 30 0000 C CNN
+ 1 6050 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_GND #PWR04
+U 1 1 68403B9A
+P 6100 4200
+F 0 "#PWR04" H 6100 3950 50 0001 C CNN
+F 1 "eSim_GND" H 6100 4050 50 0000 C CNN
+F 2 "" H 6100 4200 50 0001 C CNN
+F 3 "" H 6100 4200 50 0001 C CNN
+ 1 6100 4200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1950 2050 1950 2300
+Wire Wire Line
+ 2300 2200 1950 2200
+Connection ~ 1950 2200
+Wire Wire Line
+ 1950 1750 1950 1400
+Wire Wire Line
+ 1950 1400 8250 1400
+Wire Wire Line
+ 2600 1400 2600 2000
+Wire Wire Line
+ 2600 2400 3900 2400
+Wire Wire Line
+ 2850 2400 2850 2650
+Wire Wire Line
+ 2850 2950 2850 3200
+Wire Wire Line
+ 1950 2600 1950 2800
+Wire Wire Line
+ 2850 3500 2850 3650
+Wire Wire Line
+ 3200 3100 2850 3100
+Connection ~ 2850 3100
+Wire Wire Line
+ 3500 1400 3500 2900
+Connection ~ 2600 1400
+Wire Wire Line
+ 3900 2400 3900 2650
+Connection ~ 2850 2400
+Wire Wire Line
+ 3900 2950 3900 3250
+Wire Wire Line
+ 4250 3050 3900 3050
+Connection ~ 3900 3050
+Wire Wire Line
+ 4150 1400 4150 1550
+Connection ~ 3500 1400
+Wire Wire Line
+ 4550 1400 4550 2850
+Connection ~ 4150 1400
+Wire Wire Line
+ 4550 3250 4550 3600
+Wire Wire Line
+ 4550 3350 4800 3350
+Wire Wire Line
+ 5100 1400 5100 3150
+Connection ~ 4550 1400
+Wire Wire Line
+ 5100 3550 5550 3550
+Wire Wire Line
+ 6650 3550 7100 3550
+Wire Wire Line
+ 5850 3350 6350 3350
+Wire Wire Line
+ 6650 1400 6650 3150
+Connection ~ 5100 1400
+Wire Wire Line
+ 7100 1750 7100 3150
+Wire Wire Line
+ 7100 1400 7100 1450
+Connection ~ 6650 1400
+Wire Wire Line
+ 5550 3150 5550 2050
+Wire Wire Line
+ 5550 2050 7350 2050
+Wire Wire Line
+ 7650 1400 7650 1850
+Connection ~ 7100 1400
+Wire Wire Line
+ 7650 2250 7650 2400
+Wire Wire Line
+ 7650 2700 7650 2850
+Wire Wire Line
+ 8050 1400 8050 1500
+Connection ~ 7650 1400
+Wire Wire Line
+ 6100 3350 6100 3700
+Connection ~ 6100 3350
+Wire Wire Line
+ 6100 4000 6100 4200
+Wire Wire Line
+ 3500 3300 3500 3650
+Wire Wire Line
+ 3500 3650 6100 3650
+Connection ~ 6100 3650
+$Comp
+L resistor R14
+U 1 1 68403CD1
+P 7450 3800
+F 0 "R14" H 7500 3930 50 0000 C CNN
+F 1 "5.1k" H 7500 3750 50 0000 C CNN
+F 2 "" H 7500 3780 30 0000 C CNN
+F 3 "" V 7500 3850 30 0000 C CNN
+ 1 7450 3800
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 7400 3350 7500 3350
+Wire Wire Line
+ 7500 3350 7500 3700
+$Comp
+L eSim_GND #PWR05
+U 1 1 68403D83
+P 7500 4150
+F 0 "#PWR05" H 7500 3900 50 0001 C CNN
+F 1 "eSim_GND" H 7500 4000 50 0000 C CNN
+F 2 "" H 7500 4150 50 0001 C CNN
+F 3 "" H 7500 4150 50 0001 C CNN
+ 1 7500 4150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7500 4000 7500 4150
+Wire Wire Line
+ 4550 3600 7500 3600
+Connection ~ 7500 3600
+Connection ~ 4550 3350
+$Comp
+L resistor R18
+U 1 1 68403E61
+P 8050 2250
+F 0 "R18" H 8100 2380 50 0000 C CNN
+F 1 "200" H 8100 2200 50 0000 C CNN
+F 2 "" H 8100 2230 30 0000 C CNN
+F 3 "" V 8100 2300 30 0000 C CNN
+ 1 8050 2250
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7850 2300 7650 2300
+Connection ~ 7650 2300
+$Comp
+L eSim_Diode D1
+U 1 1 68403F41
+P 8050 4500
+F 0 "D1" H 8050 4600 50 0000 C CNN
+F 1 "eSim_Diode" H 8050 4400 50 0000 C CNN
+F 2 "" H 8050 4500 60 0000 C CNN
+F 3 "" H 8050 4500 60 0000 C CNN
+ 1 8050 4500
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R17
+U 1 1 6840556F
+P 8000 5100
+F 0 "R17" H 8050 5230 50 0000 C CNN
+F 1 "510" H 8050 5050 50 0000 C CNN
+F 2 "" H 8050 5080 30 0000 C CNN
+F 3 "" V 8050 5150 30 0000 C CNN
+ 1 8000 5100
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_GND #PWR06
+U 1 1 68405630
+P 8050 5550
+F 0 "#PWR06" H 8050 5300 50 0001 C CNN
+F 1 "eSim_GND" H 8050 5400 50 0000 C CNN
+F 2 "" H 8050 5550 50 0001 C CNN
+F 3 "" H 8050 5550 50 0001 C CNN
+ 1 8050 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 684056D5
+P 7000 4650
+F 0 "Q8" H 6900 4700 50 0000 R CNN
+F 1 "eSim_NPN" H 6950 4800 50 0000 R CNN
+F 2 "" H 7200 4750 29 0000 C CNN
+F 3 "" H 7000 4650 60 0000 C CNN
+ 1 7000 4650
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6900 4450 6900 3550
+Connection ~ 6900 3550
+$Comp
+L resistor R12
+U 1 1 68405826
+P 6850 5150
+F 0 "R12" H 6900 5280 50 0000 C CNN
+F 1 "1.5k" H 6900 5100 50 0000 C CNN
+F 2 "" H 6900 5130 30 0000 C CNN
+F 3 "" V 6900 5200 30 0000 C CNN
+ 1 6850 5150
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_GND #PWR07
+U 1 1 68405897
+P 6900 5550
+F 0 "#PWR07" H 6900 5300 50 0001 C CNN
+F 1 "eSim_GND" H 6900 5400 50 0000 C CNN
+F 2 "" H 6900 5550 50 0001 C CNN
+F 3 "" H 6900 5550 50 0001 C CNN
+ 1 6900 5550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6900 4850 6900 5050
+Wire Wire Line
+ 6900 5350 6900 5550
+Wire Wire Line
+ 8050 1800 8050 4350
+Wire Wire Line
+ 8050 4650 8050 5000
+Wire Wire Line
+ 8050 5300 8050 5550
+Wire Wire Line
+ 7200 4650 7800 4650
+Wire Wire Line
+ 7800 4650 7800 4050
+Wire Wire Line
+ 7800 4050 8050 4050
+Connection ~ 8050 4050
+$Comp
+L eSim_NPN Q5
+U 1 1 68407F71
+P 5200 4900
+F 0 "Q5" H 5100 4950 50 0000 R CNN
+F 1 "eSim_NPN" H 5150 5050 50 0000 R CNN
+F 2 "" H 5400 5000 29 0000 C CNN
+F 3 "" H 5200 4900 60 0000 C CNN
+ 1 5200 4900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5300 4700 5300 3550
+Connection ~ 5300 3550
+$Comp
+L resistor R10
+U 1 1 684085F9
+P 5250 5400
+F 0 "R10" H 5300 5530 50 0000 C CNN
+F 1 "1.3k" H 5300 5350 50 0000 C CNN
+F 2 "" H 5300 5380 30 0000 C CNN
+F 3 "" V 5300 5450 30 0000 C CNN
+ 1 5250 5400
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_GND #PWR08
+U 1 1 68408672
+P 5300 5800
+F 0 "#PWR08" H 5300 5550 50 0001 C CNN
+F 1 "eSim_GND" H 5300 5650 50 0000 C CNN
+F 2 "" H 5300 5800 50 0001 C CNN
+F 3 "" H 5300 5800 50 0001 C CNN
+ 1 5300 5800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5300 5600 5300 5800
+Wire Wire Line
+ 5300 5100 5300 5300
+$Comp
+L resistor R5
+U 1 1 684087D0
+P 3650 5200
+F 0 "R5" H 3700 5330 50 0000 C CNN
+F 1 "20K" H 3700 5150 50 0000 C CNN
+F 2 "" H 3700 5180 30 0000 C CNN
+F 3 "" V 3700 5250 30 0000 C CNN
+ 1 3650 5200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3550 5150 3550 4900
+Wire Wire Line
+ 3350 4900 5000 4900
+Wire Wire Line
+ 4150 1850 4150 5350
+Wire Wire Line
+ 4150 5150 3850 5150
+$Comp
+L resistor R9
+U 1 1 6840B887
+P 4100 5450
+F 0 "R9" H 4150 5580 50 0000 C CNN
+F 1 "510" H 4150 5400 50 0000 C CNN
+F 2 "" H 4150 5430 30 0000 C CNN
+F 3 "" V 4150 5500 30 0000 C CNN
+ 1 4100 5450
+ 0 1 1 0
+$EndComp
+Connection ~ 4150 5150
+$Comp
+L eSim_GND #PWR09
+U 1 1 6840B990
+P 4150 5800
+F 0 "#PWR09" H 4150 5550 50 0001 C CNN
+F 1 "eSim_GND" H 4150 5650 50 0000 C CNN
+F 2 "" H 4150 5800 50 0001 C CNN
+F 3 "" H 4150 5800 50 0001 C CNN
+ 1 4150 5800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4150 5650 4150 5800
+$Comp
+L PORT U1
+U 1 1 68417B8A
+P 3100 4900
+F 0 "U1" H 3150 5000 30 0000 C CNN
+F 1 "PORT" H 3100 4900 30 0000 C CNN
+F 2 "" H 3100 4900 60 0000 C CNN
+F 3 "" H 3100 4900 60 0000 C CNN
+ 1 3100 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68417C0B
+P 3550 3850
+F 0 "U1" H 3600 3950 30 0000 C CNN
+F 1 "PORT" H 3550 3850 30 0000 C CNN
+F 2 "" H 3550 3850 60 0000 C CNN
+F 3 "" H 3550 3850 60 0000 C CNN
+ 2 3550 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68417CA4
+P 2050 5250
+F 0 "U1" H 2100 5350 30 0000 C CNN
+F 1 "PORT" H 2050 5250 30 0000 C CNN
+F 2 "" H 2050 5250 60 0000 C CNN
+F 3 "" H 2050 5250 60 0000 C CNN
+ 3 2050 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68417D3F
+P 2050 5500
+F 0 "U1" H 2100 5600 30 0000 C CNN
+F 1 "PORT" H 2050 5500 30 0000 C CNN
+F 2 "" H 2050 5500 60 0000 C CNN
+F 3 "" H 2050 5500 60 0000 C CNN
+ 4 2050 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68417E3C
+P 2050 5750
+F 0 "U1" H 2100 5850 30 0000 C CNN
+F 1 "PORT" H 2050 5750 30 0000 C CNN
+F 2 "" H 2050 5750 60 0000 C CNN
+F 3 "" H 2050 5750 60 0000 C CNN
+ 5 2050 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68417E9B
+P 8550 1900
+F 0 "U1" H 8600 2000 30 0000 C CNN
+F 1 "PORT" H 8550 1900 30 0000 C CNN
+F 2 "" H 8550 1900 60 0000 C CNN
+F 3 "" H 8550 1900 60 0000 C CNN
+ 6 8550 1900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68417F12
+P 8550 2300
+F 0 "U1" H 8600 2400 30 0000 C CNN
+F 1 "PORT" H 8550 2300 30 0000 C CNN
+F 2 "" H 8550 2300 60 0000 C CNN
+F 3 "" H 8550 2300 60 0000 C CNN
+ 7 8550 2300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68417F7D
+P 8500 1400
+F 0 "U1" H 8550 1500 30 0000 C CNN
+F 1 "PORT" H 8500 1400 30 0000 C CNN
+F 2 "" H 8500 1400 60 0000 C CNN
+F 3 "" H 8500 1400 60 0000 C CNN
+ 8 8500 1400
+ -1 0 0 -1
+$EndComp
+Connection ~ 3550 4900
+Wire Wire Line
+ 3900 3550 3900 3850
+Wire Wire Line
+ 3900 3850 3800 3850
+NoConn ~ 2300 5250
+NoConn ~ 2300 5500
+NoConn ~ 2300 5750
+Wire Wire Line
+ 8300 1900 7200 1900
+Wire Wire Line
+ 7200 1900 7200 2050
+Connection ~ 7200 2050
+Connection ~ 8050 1400
+Wire Wire Line
+ 8300 2300 8150 2300
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC3340/MC3340.sub b/library/SubcircuitLibrary/MC3340/MC3340.sub
new file mode 100644
index 000000000..c36548bf1
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340.sub
@@ -0,0 +1,37 @@
+* Subcircuit MC3340
+.subckt MC3340 net-_q5-pad2_ net-_r7-pad2_ ? ? ? net-_q10-pad2_ net-_r18-pad1_ net-_q1-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\mc3340\mc3340.cir
+.include D.lib
+.include NPN.lib
+r1 net-_q1-pad1_ net-_q1-pad2_ 5.1k
+r2 net-_q1-pad2_ gnd 4.7k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222
+r3 net-_q1-pad3_ net-_q2-pad2_ 750
+r4 net-_q2-pad2_ gnd 10k
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+r6 net-_q1-pad3_ net-_q3-pad2_ 750
+r7 net-_q3-pad2_ net-_r7-pad2_ 3.9k
+q3 net-_q1-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+r8 net-_q1-pad1_ net-_r5-pad2_ 5.1k
+q4 net-_q1-pad1_ net-_q3-pad3_ net-_q4-pad3_ Q2N2222
+q6 net-_q10-pad2_ net-_q2-pad3_ net-_q4-pad3_ Q2N2222
+q7 net-_q1-pad1_ net-_q2-pad3_ net-_q7-pad3_ Q2N2222
+q9 net-_q9-pad1_ net-_q3-pad3_ net-_q7-pad3_ Q2N2222
+r13 net-_q1-pad1_ net-_q9-pad1_ 6.2k
+q10 net-_q1-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r15 net-_q10-pad3_ gnd 5.1k
+r16 net-_q1-pad1_ net-_d1-pad1_ 5.1k
+r11 net-_q2-pad3_ gnd 5.1k
+r14 net-_q3-pad3_ gnd 5.1k
+r18 net-_r18-pad1_ net-_q10-pad3_ 200
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r17 net-_d1-pad2_ gnd 510
+q8 net-_q7-pad3_ net-_d1-pad1_ net-_q8-pad3_ Q2N2222
+r12 net-_q8-pad3_ gnd 1.5k
+q5 net-_q4-pad3_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222
+r10 net-_q5-pad3_ gnd 1.3k
+r5 net-_q5-pad2_ net-_r5-pad2_ 20k
+r9 net-_r5-pad2_ gnd 510
+* Control Statements
+
+.ends MC3340
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_Previous_Values.xml b/library/SubcircuitLibrary/MC3340/MC3340_Previous_Values.xml
new file mode 100644
index 000000000..a4a0ecf99
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test-cache.lib b/library/SubcircuitLibrary/MC3340/MC3340_test-cache.lib
new file mode 100644
index 000000000..2eee24ecb
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# MC3340
+#
+DEF MC3340 X 0 40 Y Y 1 F N
+F0 "X" 0 -500 60 H V C CNN
+F1 "MC3340" 0 600 60 H V C CNN
+F2 "" 0 600 60 H I C CNN
+F3 "" 0 600 60 H I C CNN
+DRAW
+P 4 0 1 0 -250 300 -250 -350 500 0 -250 300 N
+X A 1 -450 0 200 R 50 50 1 1 I
+X B 2 -150 -500 200 U 50 50 1 1 I
+X C 3 0 -450 200 U 50 50 1 1 W
+X D 4 150 -350 200 U 50 50 1 1 N
+X E 5 300 -300 200 U 50 50 1 1 N
+X F 6 400 -250 200 U 50 50 1 1 P
+X G 7 700 0 200 L 50 50 1 1 O
+X H 8 50 350 200 D 50 50 1 1 W
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.cir b/library/SubcircuitLibrary/MC3340/MC3340_test.cir
new file mode 100644
index 000000000..483510fe7
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.cir
@@ -0,0 +1,20 @@
+* C:\Users\pavithra\eSim-Workspace\MC3340_test\MC3340_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/05/25 11:08:05
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_C1-Pad1_ Net-_C2-Pad1_ GND ? ? Net-_C3-Pad2_ out Net-_X1-Pad8_ MC3340
+C1 Net-_C1-Pad1_ in 1u
+v1 in GND sine
+C2 Net-_C2-Pad1_ GND 50u
+R1 Net-_C2-Pad1_ GND 50k
+C3 GND Net-_C3-Pad2_ 620p
+U1 out plot_v1
+U2 in plot_v1
+R2 Net-_C1-Pad1_ GND 100k
+v2 Net-_X1-Pad8_ GND DC
+
+.end
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.cir.out b/library/SubcircuitLibrary/MC3340/MC3340_test.cir.out
new file mode 100644
index 000000000..37e8ac1a5
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.cir.out
@@ -0,0 +1,24 @@
+* c:\users\pavithra\esim-workspace\mc3340_test\mc3340_test.cir
+
+.include MC3340.sub
+x1 net-_c1-pad1_ net-_c2-pad1_ gnd ? ? net-_c3-pad2_ out net-_x1-pad8_ MC3340
+c1 net-_c1-pad1_ in 1u
+v1 in gnd sine(0 0.4 1000 0 0)
+c2 net-_c2-pad1_ gnd 50u
+r1 net-_c2-pad1_ gnd 50k
+c3 gnd net-_c3-pad2_ 620p
+* u1 out plot_v1
+* u2 in plot_v1
+r2 net-_c1-pad1_ gnd 100k
+v2 net-_x1-pad8_ gnd dc 12
+.tran 1e-06 10e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out)
+plot v(in)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.pro b/library/SubcircuitLibrary/MC3340/MC3340_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.proj b/library/SubcircuitLibrary/MC3340/MC3340_test.proj
new file mode 100644
index 000000000..05f38fe8e
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.proj
@@ -0,0 +1 @@
+schematicFile MC3340_test.sch
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test.sch b/library/SubcircuitLibrary/MC3340/MC3340_test.sch
new file mode 100644
index 000000000..b3886f74b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test.sch
@@ -0,0 +1,257 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L MC3340 X1
+U 1 1 684032A2
+P 5400 3300
+F 0 "X1" H 5400 2800 60 0000 C CNN
+F 1 "MC3340" H 5750 3550 60 0000 C CNN
+F 2 "" H 5400 3900 60 0001 C CNN
+F 3 "" H 5400 3900 60 0001 C CNN
+ 1 5400 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor_polarised C1
+U 1 1 68403397
+P 4400 3300
+F 0 "C1" H 4425 3400 50 0000 L CNN
+F 1 "1u" H 4425 3200 50 0000 L CNN
+F 2 "" H 4400 3300 50 0001 C CNN
+F 3 "" H 4400 3300 50 0001 C CNN
+ 1 4400 3300
+ 0 1 1 0
+$EndComp
+$Comp
+L sine v1
+U 1 1 68403533
+P 4250 4100
+F 0 "v1" H 4050 4200 60 0000 C CNN
+F 1 "sine" H 4050 4050 60 0000 C CNN
+F 2 "R1" H 3950 4100 60 0000 C CNN
+F 3 "" H 4250 4100 60 0000 C CNN
+ 1 4250 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor_polarised C2
+U 1 1 68403666
+P 5050 4250
+F 0 "C2" H 5075 4350 50 0000 L CNN
+F 1 "50u" H 5075 4150 50 0000 L CNN
+F 2 "" H 5050 4250 50 0001 C CNN
+F 3 "" H 5050 4250 50 0001 C CNN
+ 1 5050 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 6840394D
+P 5400 4800
+F 0 "#PWR01" H 5400 4550 50 0001 C CNN
+F 1 "eSim_GND" H 5400 4650 50 0000 C CNN
+F 2 "" H 5400 4800 50 0001 C CNN
+F 3 "" H 5400 4800 50 0001 C CNN
+ 1 5400 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R1
+U 1 1 68403F36
+P 5200 5000
+F 0 "R1" H 5250 5130 50 0000 C CNN
+F 1 "50k" H 5250 4950 50 0000 C CNN
+F 2 "" H 5250 4980 30 0000 C CNN
+F 3 "" V 5250 5050 30 0000 C CNN
+ 1 5200 5000
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_GND #PWR02
+U 1 1 68403FF4
+P 5250 5300
+F 0 "#PWR02" H 5250 5050 50 0001 C CNN
+F 1 "eSim_GND" H 5250 5150 50 0000 C CNN
+F 2 "" H 5250 5300 50 0001 C CNN
+F 3 "" H 5250 5300 50 0001 C CNN
+ 1 5250 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor_polarised C3
+U 1 1 6840431E
+P 5800 4150
+F 0 "C3" H 5825 4250 50 0000 L CNN
+F 1 "620p" H 5825 4050 50 0000 L CNN
+F 2 "" H 5800 4150 50 0001 C CNN
+F 3 "" H 5800 4150 50 0001 C CNN
+ 1 5800 4150
+ 1 0 0 1
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 68404541
+P 6250 3350
+F 0 "U1" H 6250 3850 60 0000 C CNN
+F 1 "plot_v1" H 6450 3700 60 0000 C CNN
+F 2 "" H 6250 3350 60 0000 C CNN
+F 3 "" H 6250 3350 60 0000 C CNN
+ 1 6250 3350
+ 1 0 0 -1
+$EndComp
+Text GLabel 6450 3250 2 60 Input ~ 0
+out
+$Comp
+L plot_v1 U2
+U 1 1 68404A11
+P 3600 3800
+F 0 "U2" H 3600 4300 60 0000 C CNN
+F 1 "plot_v1" H 3800 4150 60 0000 C CNN
+F 2 "" H 3600 3800 60 0000 C CNN
+F 3 "" H 3600 3800 60 0000 C CNN
+ 1 3600 3800
+ 1 0 0 -1
+$EndComp
+Text GLabel 3700 3800 0 60 Input ~ 0
+in
+Wire Wire Line
+ 5450 2850 5450 2950
+Wire Wire Line
+ 4550 3300 4950 3300
+Wire Wire Line
+ 4250 3300 4250 3650
+Wire Wire Line
+ 5050 4100 5250 4100
+Wire Wire Line
+ 5250 3800 5250 4900
+Wire Wire Line
+ 5050 4400 5050 4650
+Wire Wire Line
+ 4250 4650 5800 4650
+Wire Wire Line
+ 5400 3750 5400 4800
+Connection ~ 5400 4650
+Connection ~ 5250 4100
+Wire Wire Line
+ 5250 5200 5250 5300
+Wire Wire Line
+ 5800 4000 5800 3550
+Wire Wire Line
+ 5800 4650 5800 4300
+Wire Wire Line
+ 6250 3300 6100 3300
+Wire Wire Line
+ 6250 3150 6250 3300
+Wire Wire Line
+ 6250 3250 6450 3250
+Connection ~ 6250 3250
+Wire Wire Line
+ 4250 4550 4250 4650
+Connection ~ 5050 4650
+Wire Wire Line
+ 3600 3600 4250 3600
+Wire Wire Line
+ 4250 3600 4250 3550
+Connection ~ 4250 3550
+Wire Wire Line
+ 3700 3800 3850 3800
+Wire Wire Line
+ 3850 3800 3850 3600
+Connection ~ 3850 3600
+$Comp
+L resistor R2
+U 1 1 68413101
+P 4650 4000
+F 0 "R2" H 4700 4130 50 0000 C CNN
+F 1 "100k" H 4700 3950 50 0000 C CNN
+F 2 "" H 4700 3980 30 0000 C CNN
+F 3 "" V 4700 4050 30 0000 C CNN
+ 1 4650 4000
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 4700 3900 4700 3300
+Wire Wire Line
+ 4700 3300 4750 3300
+Connection ~ 4750 3300
+Wire Wire Line
+ 4700 4200 4700 4650
+Connection ~ 4700 4650
+$Comp
+L DC v2
+U 1 1 6841325C
+P 5450 2400
+F 0 "v2" H 5250 2500 60 0000 C CNN
+F 1 "DC" H 5250 2350 60 0000 C CNN
+F 2 "R1" H 5150 2400 60 0000 C CNN
+F 3 "" H 5450 2400 60 0000 C CNN
+ 1 5450 2400
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_GND #PWR03
+U 1 1 6841330C
+P 5700 1950
+F 0 "#PWR03" H 5700 1700 50 0001 C CNN
+F 1 "eSim_GND" H 5700 1800 50 0000 C CNN
+F 2 "" H 5700 1950 50 0001 C CNN
+F 3 "" H 5700 1950 50 0001 C CNN
+ 1 5700 1950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5450 1950 5700 1950
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC3340/MC3340_test_Previous_Values.xml b/library/SubcircuitLibrary/MC3340/MC3340_test_Previous_Values.xml
new file mode 100644
index 000000000..825ffca38
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/MC3340_test_Previous_Values.xml
@@ -0,0 +1 @@
+sine00.4100000dc12C:\FOSSEE\eSim\library\SubcircuitLibrary\MC3340truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes0110secusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MC3340/NPN.lib b/library/SubcircuitLibrary/MC3340/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/MC3340/analysis b/library/SubcircuitLibrary/MC3340/analysis
new file mode 100644
index 000000000..4ccdff53b
--- /dev/null
+++ b/library/SubcircuitLibrary/MC3340/analysis
@@ -0,0 +1 @@
+.tran 1e-06 10e-03 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MCT7800/BC547B.lib b/library/SubcircuitLibrary/MCT7800/BC547B.lib
new file mode 100644
index 000000000..723537a7a
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/BC547B.lib
@@ -0,0 +1 @@
+.model BC547B NPN(IS=1.8E-14 BF=400 NF=0.9955 VAF=80 IKF=0.14 ISE=5E-14 NE=1.46 BR=35.5 NR=1.005 VAR=12.5 IKR=0.03 ISC=1.72E-13 NC=1.27 RB=0.56 RE=0.6 RC=0.25 CJE=1.3E-11 TF=6.4E-10 CJC=4E-12 VJC=0.54 TR=5.072E-8)
diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800-cache.lib b/library/SubcircuitLibrary/MCT7800/MCT7800-cache.lib
new file mode 100644
index 000000000..da3f9bc42
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/MCT7800-cache.lib
@@ -0,0 +1,147 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.bak b/library/SubcircuitLibrary/MCT7800/MCT7800.bak
new file mode 100644
index 000000000..4f9aa4962
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/MCT7800.bak
@@ -0,0 +1,793 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 683733D3
+P 1950 2400
+F 0 "R1" H 2000 2530 50 0000 C CNN
+F 1 "100" H 2000 2350 50 0000 C CNN
+F 2 "" H 2000 2380 30 0000 C CNN
+F 3 "" V 2000 2450 30 0000 C CNN
+ 1 1950 2400
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R2
+U 1 1 6837345D
+P 3000 2150
+F 0 "R2" H 3050 2280 50 0000 C CNN
+F 1 "500" H 3050 2100 50 0000 C CNN
+F 2 "" H 3050 2130 30 0000 C CNN
+F 3 "" V 3050 2200 30 0000 C CNN
+ 1 3000 2150
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 683734A6
+P 2950 3200
+F 0 "Q1" H 2850 3250 50 0000 R CNN
+F 1 "eSim_NPN" H 2900 3350 50 0000 R CNN
+F 2 "" H 3150 3300 29 0000 C CNN
+F 3 "" H 2950 3200 60 0000 C CNN
+ 1 2950 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 6837359D
+P 3000 3900
+F 0 "R3" H 3050 4030 50 0000 C CNN
+F 1 "3.3K" H 3050 3850 50 0000 C CNN
+F 2 "" H 3050 3880 30 0000 C CNN
+F 3 "" V 3050 3950 30 0000 C CNN
+ 1 3000 3900
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 683735FC
+P 3000 5200
+F 0 "R4" H 3050 5330 50 0000 C CNN
+F 1 "2.7K" H 3050 5150 50 0000 C CNN
+F 2 "" H 3050 5180 30 0000 C CNN
+F 3 "" V 3050 5250 30 0000 C CNN
+ 1 3000 5200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R5
+U 1 1 68373671
+P 3000 6350
+F 0 "R5" H 3050 6480 50 0000 C CNN
+F 1 "500" H 3050 6300 50 0000 C CNN
+F 2 "" H 3050 6330 30 0000 C CNN
+F 3 "" V 3050 6400 30 0000 C CNN
+ 1 3000 6350
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_Diode D1
+U 1 1 683737CF
+P 2000 4450
+F 0 "D1" H 2000 4550 50 0000 C CNN
+F 1 "eSim_Diode" H 2000 4350 50 0000 C CNN
+F 2 "" H 2000 4450 60 0000 C CNN
+F 3 "" H 2000 4450 60 0000 C CNN
+ 1 2000 4450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_PNP Q8
+U 1 1 68373CF4
+P 5600 1750
+F 0 "Q8" H 5500 1800 50 0000 R CNN
+F 1 "eSim_PNP" H 5550 1900 50 0000 R CNN
+F 2 "" H 5800 1850 29 0000 C CNN
+F 3 "" H 5600 1750 60 0000 C CNN
+ 1 5600 1750
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q12
+U 1 1 68373DC1
+P 6800 1750
+F 0 "Q12" H 6700 1800 50 0000 R CNN
+F 1 "eSim_PNP" H 6750 1900 50 0000 R CNN
+F 2 "" H 7000 1850 29 0000 C CNN
+F 3 "" H 6800 1750 60 0000 C CNN
+ 1 6800 1750
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R13
+U 1 1 68373E8C
+P 6850 1200
+F 0 "R13" H 6900 1330 50 0000 C CNN
+F 1 "100K" H 6900 1150 50 0000 C CNN
+F 2 "" H 6900 1180 30 0000 C CNN
+F 3 "" V 6900 1250 30 0000 C CNN
+ 1 6850 1200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R8
+U 1 1 68373EF9
+P 5450 1200
+F 0 "R8" H 5500 1330 50 0000 C CNN
+F 1 "100" H 5500 1150 50 0000 C CNN
+F 2 "" H 5500 1180 30 0000 C CNN
+F 3 "" V 5500 1250 30 0000 C CNN
+ 1 5450 1200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 683742CA
+P 4250 4400
+F 0 "Q2" H 4150 4450 50 0000 R CNN
+F 1 "eSim_NPN" H 4200 4550 50 0000 R CNN
+F 2 "" H 4450 4500 29 0000 C CNN
+F 3 "" H 4250 4400 60 0000 C CNN
+ 1 4250 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q10
+U 1 1 6837491E
+P 6350 2550
+F 0 "Q10" H 6250 2600 50 0000 R CNN
+F 1 "eSim_NPN" H 6300 2700 50 0000 R CNN
+F 2 "" H 6550 2650 29 0000 C CNN
+F 3 "" H 6350 2550 60 0000 C CNN
+ 1 6350 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 68374F77
+P 4450 6450
+F 0 "Q3" H 4350 6500 50 0000 R CNN
+F 1 "eSim_NPN" H 4400 6600 50 0000 R CNN
+F 2 "" H 4650 6550 29 0000 C CNN
+F 3 "" H 4450 6450 60 0000 C CNN
+ 1 4450 6450
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R6
+U 1 1 683753C8
+P 4300 5600
+F 0 "R6" H 4350 5730 50 0000 C CNN
+F 1 "1.4K" H 4350 5550 50 0000 C CNN
+F 2 "" H 4350 5580 30 0000 C CNN
+F 3 "" V 4350 5650 30 0000 C CNN
+ 1 4300 5600
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 683756E3
+P 5400 6450
+F 0 "Q7" H 5300 6500 50 0000 R CNN
+F 1 "eSim_NPN" H 5350 6600 50 0000 R CNN
+F 2 "" H 5600 6550 29 0000 C CNN
+F 3 "" H 5400 6450 60 0000 C CNN
+ 1 5400 6450
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R7
+U 1 1 68375756
+P 4850 6900
+F 0 "R7" H 4900 7030 50 0000 C CNN
+F 1 "6.0K" H 4900 6850 50 0000 C CNN
+F 2 "" H 4900 6880 30 0000 C CNN
+F 3 "" V 4900 6950 30 0000 C CNN
+ 1 4850 6900
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R11
+U 1 1 683757BF
+P 5450 6950
+F 0 "R11" H 5500 7080 50 0000 C CNN
+F 1 "1.0K" H 5500 6900 50 0000 C CNN
+F 2 "" H 5500 6930 30 0000 C CNN
+F 3 "" V 5500 7000 30 0000 C CNN
+ 1 5450 6950
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 68375D06
+P 4650 6000
+F 0 "Q4" H 4550 6050 50 0000 R CNN
+F 1 "eSim_NPN" H 4600 6150 50 0000 R CNN
+F 2 "" H 4850 6100 29 0000 C CNN
+F 3 "" H 4650 6000 60 0000 C CNN
+ 1 4650 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R10
+U 1 1 68376041
+P 5450 5600
+F 0 "R10" H 5500 5730 50 0000 C CNN
+F 1 "28K" H 5500 5550 50 0000 C CNN
+F 2 "" H 5500 5580 30 0000 C CNN
+F 3 "" V 5500 5650 30 0000 C CNN
+ 1 5450 5600
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R9
+U 1 1 68376321
+P 5450 5050
+F 0 "R9" H 5500 5180 50 0000 C CNN
+F 1 "6.0K" H 5500 5000 50 0000 C CNN
+F 2 "" H 5500 5030 30 0000 C CNN
+F 3 "" V 5500 5100 30 0000 C CNN
+ 1 5450 5050
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 683771FE
+P 5150 4550
+F 0 "Q6" H 5050 4600 50 0000 R CNN
+F 1 "eSim_NPN" H 5100 4700 50 0000 R CNN
+F 2 "" H 5350 4650 29 0000 C CNN
+F 3 "" H 5150 4550 60 0000 C CNN
+ 1 5150 4550
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 68377293
+P 5150 3500
+F 0 "Q5" H 5050 3550 50 0000 R CNN
+F 1 "eSim_NPN" H 5100 3650 50 0000 R CNN
+F 2 "" H 5350 3600 29 0000 C CNN
+F 3 "" H 5150 3500 60 0000 C CNN
+ 1 5150 3500
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 6837732F
+P 5600 4000
+F 0 "Q9" H 5500 4050 50 0000 R CNN
+F 1 "eSim_NPN" H 5550 4150 50 0000 R CNN
+F 2 "" H 5800 4100 29 0000 C CNN
+F 3 "" H 5600 4000 60 0000 C CNN
+ 1 5600 4000
+ -1 0 0 -1
+$EndComp
+$Comp
+L capacitor_polarised C1
+U 1 1 68378529
+P 6050 5900
+F 0 "C1" H 6075 6000 50 0000 L CNN
+F 1 "30p" H 6075 5800 50 0000 L CNN
+F 2 "" H 6050 5900 50 0001 C CNN
+F 3 "" H 6050 5900 50 0001 C CNN
+ 1 6050 5900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q11
+U 1 1 68378606
+P 6400 6200
+F 0 "Q11" H 6300 6250 50 0000 R CNN
+F 1 "eSim_NPN" H 6350 6350 50 0000 R CNN
+F 2 "" H 6600 6300 29 0000 C CNN
+F 3 "" H 6400 6200 60 0000 C CNN
+ 1 6400 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q14
+U 1 1 68378E51
+P 7100 5200
+F 0 "Q14" H 7000 5250 50 0000 R CNN
+F 1 "eSim_PNP" H 7050 5350 50 0000 R CNN
+F 2 "" H 7300 5300 29 0000 C CNN
+F 3 "" H 7100 5200 60 0000 C CNN
+ 1 7100 5200
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R14
+U 1 1 68378EF1
+P 6850 4650
+F 0 "R14" H 6900 4780 50 0000 C CNN
+F 1 "2.0K" H 6900 4600 50 0000 C CNN
+F 2 "" H 6900 4630 30 0000 C CNN
+F 3 "" V 6900 4700 30 0000 C CNN
+ 1 6850 4650
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R12
+U 1 1 68379769
+P 6250 6950
+F 0 "R12" H 6300 7080 50 0000 C CNN
+F 1 "5.0K" H 6300 6900 50 0000 C CNN
+F 2 "" H 6300 6930 30 0000 C CNN
+F 3 "" V 6300 7000 30 0000 C CNN
+ 1 6250 6950
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q13
+U 1 1 68379995
+P 6800 6550
+F 0 "Q13" H 6700 6600 50 0000 R CNN
+F 1 "eSim_NPN" H 6750 6700 50 0000 R CNN
+F 2 "" H 7000 6650 29 0000 C CNN
+F 3 "" H 6800 6550 60 0000 C CNN
+ 1 6800 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q16
+U 1 1 6837A706
+P 8550 2300
+F 0 "Q16" H 8450 2350 50 0000 R CNN
+F 1 "eSim_NPN" H 8500 2450 50 0000 R CNN
+F 2 "" H 8750 2400 29 0000 C CNN
+F 3 "" H 8550 2300 60 0000 C CNN
+ 1 8550 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 6837A79F
+P 10000 2650
+F 0 "Q17" H 9900 2700 50 0000 R CNN
+F 1 "eSim_NPN" H 9950 2800 50 0000 R CNN
+F 2 "" H 10200 2750 29 0000 C CNN
+F 3 "" H 10000 2650 60 0000 C CNN
+ 1 10000 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 6837A926
+P 8000 1850
+F 0 "D2" H 8000 1950 50 0000 C CNN
+F 1 "eSim_Diode" H 8000 1750 50 0000 C CNN
+F 2 "" H 8000 1850 60 0000 C CNN
+F 3 "" H 8000 1850 60 0000 C CNN
+ 1 8000 1850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R15
+U 1 1 6837AA35
+P 7950 1250
+F 0 "R15" H 8000 1380 50 0000 C CNN
+F 1 "10K" H 8000 1200 50 0000 C CNN
+F 2 "" H 8000 1230 30 0000 C CNN
+F 3 "" V 8000 1300 30 0000 C CNN
+ 1 7950 1250
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q15
+U 1 1 6837AE59
+P 7750 2950
+F 0 "Q15" H 7650 3000 50 0000 R CNN
+F 1 "eSim_NPN" H 7700 3100 50 0000 R CNN
+F 2 "" H 7950 3050 29 0000 C CNN
+F 3 "" H 7750 2950 60 0000 C CNN
+ 1 7750 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R16
+U 1 1 6837B14E
+P 8600 3150
+F 0 "R16" H 8650 3280 50 0000 C CNN
+F 1 "200" H 8650 3100 50 0000 C CNN
+F 2 "" H 8650 3130 30 0000 C CNN
+F 3 "" V 8650 3200 30 0000 C CNN
+ 1 8600 3150
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R20
+U 1 1 6837B3E1
+P 10150 3250
+F 0 "R20" H 10200 3380 50 0000 C CNN
+F 1 "0.3" H 10200 3200 50 0000 C CNN
+F 2 "" H 10200 3230 30 0000 C CNN
+F 3 "" V 10200 3300 30 0000 C CNN
+ 1 10150 3250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R19
+U 1 1 6837B589
+P 9300 3000
+F 0 "R19" H 9350 3130 50 0000 C CNN
+F 1 "240" H 9350 2950 50 0000 C CNN
+F 2 "" H 9350 2980 30 0000 C CNN
+F 3 "" V 9350 3050 30 0000 C CNN
+ 1 9300 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R17
+U 1 1 6837D366
+P 9200 4250
+F 0 "R17" H 9250 4380 50 0000 C CNN
+F 1 "0.25K" H 9250 4200 50 0000 C CNN
+F 2 "" H 9250 4230 30 0000 C CNN
+F 3 "" V 9250 4300 30 0000 C CNN
+ 1 9200 4250
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R18
+U 1 1 6837D3FF
+P 9200 5550
+F 0 "R18" H 9250 5680 50 0000 C CNN
+F 1 "5.0K" H 9250 5500 50 0000 C CNN
+F 2 "" H 9250 5530 30 0000 C CNN
+F 3 "" V 9250 5600 30 0000 C CNN
+ 1 9200 5550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 2000 2300 2000 1400
+Wire Wire Line
+ 2000 1400 4450 1400
+Wire Wire Line
+ 2750 3200 2000 3200
+Wire Wire Line
+ 2000 2600 2000 4300
+Wire Wire Line
+ 3050 3000 3050 2350
+Wire Wire Line
+ 3050 1400 3050 2050
+Wire Wire Line
+ 3050 3800 3050 3400
+Wire Wire Line
+ 3050 4100 3050 5100
+Wire Wire Line
+ 3050 5400 3050 6250
+Connection ~ 2000 3200
+Wire Wire Line
+ 3050 6550 3050 6750
+Wire Wire Line
+ 2000 6750 2000 4600
+Connection ~ 3050 6750
+Wire Wire Line
+ 5500 1100 5500 1000
+Wire Wire Line
+ 5500 1400 5500 1550
+Wire Wire Line
+ 6900 1550 6900 1400
+Wire Wire Line
+ 6900 1000 6900 1100
+Wire Wire Line
+ 5800 1750 6600 1750
+Wire Wire Line
+ 4350 2950 4350 4200
+Wire Wire Line
+ 5500 2950 5500 1950
+Wire Wire Line
+ 6200 1750 6200 2150
+Wire Wire Line
+ 6200 2150 5500 2150
+Connection ~ 5500 2150
+Connection ~ 6200 1750
+Wire Wire Line
+ 4050 4400 3050 4400
+Connection ~ 3050 4400
+Wire Wire Line
+ 6450 2350 6450 2250
+Wire Wire Line
+ 6450 2250 6900 2250
+Connection ~ 6900 2250
+Wire Wire Line
+ 3550 2550 3550 5850
+Wire Wire Line
+ 3550 5850 3050 5850
+Connection ~ 3050 5850
+Wire Wire Line
+ 3700 6750 3700 2750
+Connection ~ 3700 6750
+Wire Wire Line
+ 4350 6650 4350 7400
+Wire Wire Line
+ 4350 5800 4350 6250
+Wire Wire Line
+ 4350 4600 4350 5500
+Wire Wire Line
+ 4650 6450 5200 6450
+Wire Wire Line
+ 4900 6800 4900 6450
+Connection ~ 4900 6450
+Wire Wire Line
+ 5500 6650 5500 6850
+Wire Wire Line
+ 5500 7400 5500 7150
+Wire Wire Line
+ 4900 7100 4900 7400
+Wire Wire Line
+ 4750 6200 4750 6400
+Wire Wire Line
+ 4750 6400 4800 6400
+Wire Wire Line
+ 4800 6400 4800 6450
+Connection ~ 4800 6450
+Wire Wire Line
+ 4450 6000 4350 6000
+Connection ~ 4350 6000
+Wire Wire Line
+ 5500 6250 5500 5800
+Wire Wire Line
+ 5500 5250 5500 5500
+Wire Wire Line
+ 4350 5350 5500 5350
+Connection ~ 4350 5350
+Wire Wire Line
+ 4750 5800 4750 5350
+Connection ~ 4750 5350
+Connection ~ 5500 5350
+Wire Wire Line
+ 5500 4950 5500 4200
+Wire Wire Line
+ 5350 4550 5500 4550
+Connection ~ 5500 4550
+Wire Wire Line
+ 5050 4350 5050 3700
+Wire Wire Line
+ 4350 2950 5500 2950
+Wire Wire Line
+ 5050 2950 5050 3300
+Connection ~ 5050 2950
+Wire Wire Line
+ 3550 2550 6150 2550
+Wire Wire Line
+ 3700 2750 6450 2750
+Wire Wire Line
+ 5350 3500 10500 3500
+Wire Wire Line
+ 5500 3800 5500 3500
+Connection ~ 5500 3500
+Wire Wire Line
+ 5800 4000 8550 4000
+Wire Wire Line
+ 8550 4000 8550 5100
+Wire Wire Line
+ 8550 5100 9250 5100
+Wire Wire Line
+ 5900 5900 5500 5900
+Connection ~ 5500 5900
+Wire Wire Line
+ 6200 6200 5650 6200
+Wire Wire Line
+ 5650 6200 5650 6100
+Wire Wire Line
+ 5650 6100 5500 6100
+Connection ~ 5500 6100
+Wire Wire Line
+ 6200 5900 6400 5900
+Wire Wire Line
+ 6400 5900 6400 5800
+Wire Wire Line
+ 6400 5800 6900 5800
+Wire Wire Line
+ 6500 6000 6500 5800
+Connection ~ 6500 5800
+Wire Wire Line
+ 6900 4850 6900 6350
+Connection ~ 6900 5200
+Wire Wire Line
+ 6900 1950 6900 4550
+Wire Wire Line
+ 7200 5000 7200 4300
+Wire Wire Line
+ 7200 4300 6900 4300
+Connection ~ 6900 4300
+Wire Wire Line
+ 7200 5400 7550 5400
+Wire Wire Line
+ 7550 5400 7550 6400
+Wire Wire Line
+ 6500 6400 6500 6700
+Wire Wire Line
+ 6300 6700 6550 6700
+Wire Wire Line
+ 6300 6700 6300 6850
+Connection ~ 6900 5800
+Wire Wire Line
+ 6600 6550 6550 6550
+Wire Wire Line
+ 6550 6550 6550 6700
+Connection ~ 6500 6700
+Wire Wire Line
+ 6900 7400 6900 6750
+Wire Wire Line
+ 6300 7400 6300 7150
+Wire Wire Line
+ 4450 1400 4450 1000
+Wire Wire Line
+ 4450 1000 9750 1000
+Connection ~ 3050 1400
+Connection ~ 5500 1000
+Wire Wire Line
+ 9750 1000 9750 1050
+Connection ~ 6900 1000
+Wire Wire Line
+ 8350 2300 7200 2300
+Wire Wire Line
+ 7200 2300 7200 2100
+Wire Wire Line
+ 7200 2100 6900 2100
+Connection ~ 6900 2100
+Wire Wire Line
+ 7650 3150 7650 3500
+Connection ~ 7650 3500
+Wire Wire Line
+ 9200 2950 7950 2950
+Wire Wire Line
+ 8000 2000 8000 2850
+Wire Wire Line
+ 8000 2850 8100 2850
+Wire Wire Line
+ 8100 2850 8100 2950
+Connection ~ 8100 2950
+Wire Wire Line
+ 8000 1450 8000 1700
+Wire Wire Line
+ 8000 1150 8000 1000
+Connection ~ 8000 1000
+Wire Wire Line
+ 8650 2100 8650 1000
+Connection ~ 8650 1000
+Wire Wire Line
+ 8650 2500 8650 3050
+Wire Wire Line
+ 8650 3350 8650 3500
+Connection ~ 8650 3500
+Wire Wire Line
+ 10100 2850 10100 3050
+Wire Wire Line
+ 10100 3350 10100 3500
+Connection ~ 10100 3500
+Wire Wire Line
+ 9800 2650 8650 2650
+Connection ~ 8650 2650
+Wire Wire Line
+ 9500 2950 10100 2950
+Connection ~ 10100 2950
+Wire Wire Line
+ 10100 2450 10100 1050
+Wire Wire Line
+ 9750 1050 10400 1050
+Connection ~ 10100 1050
+Wire Wire Line
+ 9250 4450 9250 5450
+Connection ~ 9250 5100
+Wire Wire Line
+ 9250 6400 9250 5750
+Wire Wire Line
+ 9250 4150 9250 3500
+Connection ~ 9250 3500
+Wire Wire Line
+ 5050 4750 5050 5350
+Connection ~ 5050 5350
+Wire Wire Line
+ 2000 6750 4100 6750
+Wire Wire Line
+ 4100 6750 4100 6950
+Wire Wire Line
+ 4100 6950 4350 6950
+Wire Wire Line
+ 4350 7400 7250 7400
+Connection ~ 4350 6950
+Connection ~ 4900 7400
+Connection ~ 5500 7400
+Connection ~ 6300 7400
+Wire Wire Line
+ 7250 7400 7250 6400
+Wire Wire Line
+ 7250 6400 10250 6400
+Connection ~ 6900 7400
+Connection ~ 7550 6400
+Connection ~ 9250 6400
+$Comp
+L PORT U1
+U 2 1 683804D4
+P 10500 6400
+F 0 "U1" H 10550 6500 30 0000 C CNN
+F 1 "PORT" H 10500 6400 30 0000 C CNN
+F 2 "" H 10500 6400 60 0000 C CNN
+F 3 "" H 10500 6400 60 0000 C CNN
+ 2 10500 6400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6838073F
+P 10650 1050
+F 0 "U1" H 10700 1150 30 0000 C CNN
+F 1 "PORT" H 10650 1050 30 0000 C CNN
+F 2 "" H 10650 1050 60 0000 C CNN
+F 3 "" H 10650 1050 60 0000 C CNN
+ 1 10650 1050
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6838098E
+P 10750 3500
+F 0 "U1" H 10800 3600 30 0000 C CNN
+F 1 "PORT" H 10750 3500 30 0000 C CNN
+F 2 "" H 10750 3500 60 0000 C CNN
+F 3 "" H 10750 3500 60 0000 C CNN
+ 3 10750 3500
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7650 2750 7650 2300
+Connection ~ 7650 2300
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.cir b/library/SubcircuitLibrary/MCT7800/MCT7800.cir
new file mode 100644
index 000000000..ee2afa7dd
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/MCT7800.cir
@@ -0,0 +1,51 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MCT7800\MCT7800.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/28/25 23:41:19
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_Q16-Pad1_ Net-_D1-Pad2_ 100
+R2 Net-_Q16-Pad1_ Net-_Q1-Pad1_ 500
+Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+R3 Net-_Q1-Pad3_ Net-_Q2-Pad2_ 3.3K
+R4 Net-_Q2-Pad2_ Net-_Q10-Pad2_ 2.7K
+R5 Net-_Q10-Pad2_ Net-_D1-Pad1_ 500
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+Q8 Net-_Q12-Pad2_ Net-_Q12-Pad2_ Net-_Q8-Pad3_ eSim_PNP
+Q12 Net-_Q10-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_PNP
+R13 Net-_Q16-Pad1_ Net-_Q12-Pad3_ 100K
+R8 Net-_Q16-Pad1_ Net-_Q8-Pad3_ 100
+Q2 Net-_Q12-Pad2_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_D1-Pad1_ eSim_NPN
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D1-Pad1_ eSim_NPN
+R6 Net-_Q2-Pad3_ Net-_Q3-Pad1_ 1.4K
+Q7 Net-_C1-Pad1_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN
+R7 Net-_Q3-Pad2_ Net-_D1-Pad1_ 6.0K
+R11 Net-_Q7-Pad3_ Net-_D1-Pad1_ 1.0K
+Q4 Net-_Q2-Pad3_ Net-_Q3-Pad1_ Net-_Q3-Pad2_ eSim_NPN
+R10 Net-_Q2-Pad3_ Net-_C1-Pad1_ 28K
+R9 Net-_Q6-Pad2_ Net-_Q2-Pad3_ 6.0K
+Q6 Net-_Q5-Pad3_ Net-_Q6-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+Q5 Net-_Q12-Pad2_ Net-_Q15-Pad3_ Net-_Q5-Pad3_ eSim_NPN
+Q9 Net-_Q15-Pad3_ Net-_Q9-Pad2_ Net-_Q6-Pad2_ eSim_NPN
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p
+Q11 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q11-Pad3_ eSim_NPN
+Q14 Net-_D1-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad1_ eSim_PNP
+R14 Net-_Q10-Pad1_ Net-_C1-Pad2_ 2.0K
+R12 Net-_Q11-Pad3_ Net-_D1-Pad1_ 5.0K
+Q13 Net-_C1-Pad2_ Net-_Q11-Pad3_ Net-_D1-Pad1_ eSim_NPN
+Q16 Net-_Q16-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ eSim_NPN
+Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_Q17-Pad3_ eSim_NPN
+D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode
+R15 Net-_Q16-Pad1_ Net-_D2-Pad2_ 10K
+Q15 Net-_Q10-Pad1_ Net-_D2-Pad1_ Net-_Q15-Pad3_ eSim_NPN
+R16 Net-_Q16-Pad3_ Net-_Q15-Pad3_ 200
+R20 Net-_Q15-Pad3_ Net-_Q17-Pad3_ 0.3
+R19 Net-_D2-Pad1_ Net-_Q17-Pad3_ 240
+R17 Net-_Q15-Pad3_ Net-_Q9-Pad2_ 0.25K
+R18 Net-_Q9-Pad2_ Net-_D1-Pad1_ 5.0K
+U1 Net-_Q16-Pad1_ Net-_D1-Pad1_ Net-_Q15-Pad3_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.cir.out b/library/SubcircuitLibrary/MCT7800/MCT7800.cir.out
new file mode 100644
index 000000000..ad2f477ab
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/MCT7800.cir.out
@@ -0,0 +1,55 @@
+* c:\fossee\esim\library\subcircuitlibrary\mct7800\mct7800.cir
+
+.include BC547B.lib
+.include PNP.lib
+.include ZenerD1N750.lib
+r1 net-_q16-pad1_ net-_d1-pad2_ 100
+r2 net-_q16-pad1_ net-_q1-pad1_ 500
+q1 net-_q1-pad1_ net-_d1-pad2_ net-_q1-pad3_ BC547B
+r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k
+r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k
+r5 net-_q10-pad2_ net-_d1-pad1_ 500
+d1 net-_d1-pad1_ net-_d1-pad2_ D1N750
+q8 net-_q12-pad2_ net-_q12-pad2_ net-_q8-pad3_ Q2N2907A
+q12 net-_q10-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A
+r13 net-_q16-pad1_ net-_q12-pad3_ 100k
+r8 net-_q16-pad1_ net-_q8-pad3_ 100
+q2 net-_q12-pad2_ net-_q2-pad2_ net-_q2-pad3_ BC547B
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_d1-pad1_ BC547B
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d1-pad1_ BC547B
+r6 net-_q2-pad3_ net-_q3-pad1_ 1.4k
+q7 net-_c1-pad1_ net-_q3-pad2_ net-_q7-pad3_ BC547B
+r7 net-_q3-pad2_ net-_d1-pad1_ 6.0k
+r11 net-_q7-pad3_ net-_d1-pad1_ 1.0k
+q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ BC547B
+r10 net-_q2-pad3_ net-_c1-pad1_ 28k
+r9 net-_q6-pad2_ net-_q2-pad3_ 6.0k
+q6 net-_q5-pad3_ net-_q6-pad2_ net-_q2-pad3_ BC547B
+q5 net-_q12-pad2_ net-_q15-pad3_ net-_q5-pad3_ BC547B
+q9 net-_q15-pad3_ net-_q9-pad2_ net-_q6-pad2_ BC547B
+c1 net-_c1-pad1_ net-_c1-pad2_ 30p
+q11 net-_c1-pad2_ net-_c1-pad1_ net-_q11-pad3_ BC547B
+q14 net-_d1-pad1_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A
+r14 net-_q10-pad1_ net-_c1-pad2_ 2.0k
+r12 net-_q11-pad3_ net-_d1-pad1_ 5.0k
+q13 net-_c1-pad2_ net-_q11-pad3_ net-_d1-pad1_ BC547B
+q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ BC547B
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ BC547B
+d2 net-_d2-pad1_ net-_d2-pad2_ D1N750
+r15 net-_q16-pad1_ net-_d2-pad2_ 10k
+q15 net-_q10-pad1_ net-_d2-pad1_ net-_q15-pad3_ BC547B
+r16 net-_q16-pad3_ net-_q15-pad3_ 200
+r20 net-_q15-pad3_ net-_q17-pad3_ 0.3
+r19 net-_d2-pad1_ net-_q17-pad3_ 240
+r17 net-_q15-pad3_ net-_q9-pad2_ 0.25k
+r18 net-_q9-pad2_ net-_d1-pad1_ 5.0k
+* u1 net-_q16-pad1_ net-_d1-pad1_ net-_q15-pad3_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.pro b/library/SubcircuitLibrary/MCT7800/MCT7800.pro
new file mode 100644
index 000000000..9591dc820
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/MCT7800.pro
@@ -0,0 +1,83 @@
+update=07/01/25 20:35:23
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.sch b/library/SubcircuitLibrary/MCT7800/MCT7800.sch
new file mode 100644
index 000000000..4467b8444
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/MCT7800.sch
@@ -0,0 +1,794 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MCT7800-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 683733D3
+P 1400 2350
+F 0 "R1" H 1450 2480 50 0000 C CNN
+F 1 "100" H 1450 2300 50 0000 C CNN
+F 2 "" H 1450 2330 30 0000 C CNN
+F 3 "" V 1450 2400 30 0000 C CNN
+ 1 1400 2350
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R2
+U 1 1 6837345D
+P 2450 2100
+F 0 "R2" H 2500 2230 50 0000 C CNN
+F 1 "500" H 2500 2050 50 0000 C CNN
+F 2 "" H 2500 2080 30 0000 C CNN
+F 3 "" V 2500 2150 30 0000 C CNN
+ 1 2450 2100
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 683734A6
+P 2400 3150
+F 0 "Q1" H 2300 3200 50 0000 R CNN
+F 1 "eSim_NPN" H 2350 3300 50 0000 R CNN
+F 2 "" H 2600 3250 29 0000 C CNN
+F 3 "" H 2400 3150 60 0000 C CNN
+ 1 2400 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 6837359D
+P 2450 3850
+F 0 "R3" H 2500 3980 50 0000 C CNN
+F 1 "3.3K" H 2500 3800 50 0000 C CNN
+F 2 "" H 2500 3830 30 0000 C CNN
+F 3 "" V 2500 3900 30 0000 C CNN
+ 1 2450 3850
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 683735FC
+P 2450 5150
+F 0 "R4" H 2500 5280 50 0000 C CNN
+F 1 "2.7K" H 2500 5100 50 0000 C CNN
+F 2 "" H 2500 5130 30 0000 C CNN
+F 3 "" V 2500 5200 30 0000 C CNN
+ 1 2450 5150
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R5
+U 1 1 68373671
+P 2450 6300
+F 0 "R5" H 2500 6430 50 0000 C CNN
+F 1 "500" H 2500 6250 50 0000 C CNN
+F 2 "" H 2500 6280 30 0000 C CNN
+F 3 "" V 2500 6350 30 0000 C CNN
+ 1 2450 6300
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_Diode D1
+U 1 1 683737CF
+P 1450 4400
+F 0 "D1" H 1450 4500 50 0000 C CNN
+F 1 "eSim_Diode" H 1450 4300 50 0000 C CNN
+F 2 "" H 1450 4400 60 0000 C CNN
+F 3 "" H 1450 4400 60 0000 C CNN
+ 1 1450 4400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_PNP Q8
+U 1 1 68373CF4
+P 5050 1700
+F 0 "Q8" H 4950 1750 50 0000 R CNN
+F 1 "eSim_PNP" H 5000 1850 50 0000 R CNN
+F 2 "" H 5250 1800 29 0000 C CNN
+F 3 "" H 5050 1700 60 0000 C CNN
+ 1 5050 1700
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q12
+U 1 1 68373DC1
+P 6250 1700
+F 0 "Q12" H 6150 1750 50 0000 R CNN
+F 1 "eSim_PNP" H 6200 1850 50 0000 R CNN
+F 2 "" H 6450 1800 29 0000 C CNN
+F 3 "" H 6250 1700 60 0000 C CNN
+ 1 6250 1700
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R13
+U 1 1 68373E8C
+P 6300 1150
+F 0 "R13" H 6350 1280 50 0000 C CNN
+F 1 "100K" H 6350 1100 50 0000 C CNN
+F 2 "" H 6350 1130 30 0000 C CNN
+F 3 "" V 6350 1200 30 0000 C CNN
+ 1 6300 1150
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R8
+U 1 1 68373EF9
+P 4900 1150
+F 0 "R8" H 4950 1280 50 0000 C CNN
+F 1 "100" H 4950 1100 50 0000 C CNN
+F 2 "" H 4950 1130 30 0000 C CNN
+F 3 "" V 4950 1200 30 0000 C CNN
+ 1 4900 1150
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 683742CA
+P 3700 4350
+F 0 "Q2" H 3600 4400 50 0000 R CNN
+F 1 "eSim_NPN" H 3650 4500 50 0000 R CNN
+F 2 "" H 3900 4450 29 0000 C CNN
+F 3 "" H 3700 4350 60 0000 C CNN
+ 1 3700 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q10
+U 1 1 6837491E
+P 5800 2500
+F 0 "Q10" H 5700 2550 50 0000 R CNN
+F 1 "eSim_NPN" H 5750 2650 50 0000 R CNN
+F 2 "" H 6000 2600 29 0000 C CNN
+F 3 "" H 5800 2500 60 0000 C CNN
+ 1 5800 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 68374F77
+P 3900 6400
+F 0 "Q3" H 3800 6450 50 0000 R CNN
+F 1 "eSim_NPN" H 3850 6550 50 0000 R CNN
+F 2 "" H 4100 6500 29 0000 C CNN
+F 3 "" H 3900 6400 60 0000 C CNN
+ 1 3900 6400
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R6
+U 1 1 683753C8
+P 3750 5550
+F 0 "R6" H 3800 5680 50 0000 C CNN
+F 1 "1.4K" H 3800 5500 50 0000 C CNN
+F 2 "" H 3800 5530 30 0000 C CNN
+F 3 "" V 3800 5600 30 0000 C CNN
+ 1 3750 5550
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 683756E3
+P 4850 6400
+F 0 "Q7" H 4750 6450 50 0000 R CNN
+F 1 "eSim_NPN" H 4800 6550 50 0000 R CNN
+F 2 "" H 5050 6500 29 0000 C CNN
+F 3 "" H 4850 6400 60 0000 C CNN
+ 1 4850 6400
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R7
+U 1 1 68375756
+P 4300 6850
+F 0 "R7" H 4350 6980 50 0000 C CNN
+F 1 "6.0K" H 4350 6800 50 0000 C CNN
+F 2 "" H 4350 6830 30 0000 C CNN
+F 3 "" V 4350 6900 30 0000 C CNN
+ 1 4300 6850
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R11
+U 1 1 683757BF
+P 4900 6900
+F 0 "R11" H 4950 7030 50 0000 C CNN
+F 1 "1.0K" H 4950 6850 50 0000 C CNN
+F 2 "" H 4950 6880 30 0000 C CNN
+F 3 "" V 4950 6950 30 0000 C CNN
+ 1 4900 6900
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 68375D06
+P 4100 5950
+F 0 "Q4" H 4000 6000 50 0000 R CNN
+F 1 "eSim_NPN" H 4050 6100 50 0000 R CNN
+F 2 "" H 4300 6050 29 0000 C CNN
+F 3 "" H 4100 5950 60 0000 C CNN
+ 1 4100 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R10
+U 1 1 68376041
+P 4900 5550
+F 0 "R10" H 4950 5680 50 0000 C CNN
+F 1 "28K" H 4950 5500 50 0000 C CNN
+F 2 "" H 4950 5530 30 0000 C CNN
+F 3 "" V 4950 5600 30 0000 C CNN
+ 1 4900 5550
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R9
+U 1 1 68376321
+P 4900 5000
+F 0 "R9" H 4950 5130 50 0000 C CNN
+F 1 "6.0K" H 4950 4950 50 0000 C CNN
+F 2 "" H 4950 4980 30 0000 C CNN
+F 3 "" V 4950 5050 30 0000 C CNN
+ 1 4900 5000
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 683771FE
+P 4600 4500
+F 0 "Q6" H 4500 4550 50 0000 R CNN
+F 1 "eSim_NPN" H 4550 4650 50 0000 R CNN
+F 2 "" H 4800 4600 29 0000 C CNN
+F 3 "" H 4600 4500 60 0000 C CNN
+ 1 4600 4500
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 68377293
+P 4600 3450
+F 0 "Q5" H 4500 3500 50 0000 R CNN
+F 1 "eSim_NPN" H 4550 3600 50 0000 R CNN
+F 2 "" H 4800 3550 29 0000 C CNN
+F 3 "" H 4600 3450 60 0000 C CNN
+ 1 4600 3450
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 6837732F
+P 5050 3950
+F 0 "Q9" H 4950 4000 50 0000 R CNN
+F 1 "eSim_NPN" H 5000 4100 50 0000 R CNN
+F 2 "" H 5250 4050 29 0000 C CNN
+F 3 "" H 5050 3950 60 0000 C CNN
+ 1 5050 3950
+ -1 0 0 -1
+$EndComp
+$Comp
+L capacitor_polarised C1
+U 1 1 68378529
+P 5500 5850
+F 0 "C1" H 5525 5950 50 0000 L CNN
+F 1 "30p" H 5525 5750 50 0000 L CNN
+F 2 "" H 5500 5850 50 0001 C CNN
+F 3 "" H 5500 5850 50 0001 C CNN
+ 1 5500 5850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q11
+U 1 1 68378606
+P 5850 6150
+F 0 "Q11" H 5750 6200 50 0000 R CNN
+F 1 "eSim_NPN" H 5800 6300 50 0000 R CNN
+F 2 "" H 6050 6250 29 0000 C CNN
+F 3 "" H 5850 6150 60 0000 C CNN
+ 1 5850 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q14
+U 1 1 68378E51
+P 6550 5150
+F 0 "Q14" H 6450 5200 50 0000 R CNN
+F 1 "eSim_PNP" H 6500 5300 50 0000 R CNN
+F 2 "" H 6750 5250 29 0000 C CNN
+F 3 "" H 6550 5150 60 0000 C CNN
+ 1 6550 5150
+ 1 0 0 1
+$EndComp
+$Comp
+L resistor R14
+U 1 1 68378EF1
+P 6300 4600
+F 0 "R14" H 6350 4730 50 0000 C CNN
+F 1 "2.0K" H 6350 4550 50 0000 C CNN
+F 2 "" H 6350 4580 30 0000 C CNN
+F 3 "" V 6350 4650 30 0000 C CNN
+ 1 6300 4600
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R12
+U 1 1 68379769
+P 5700 6900
+F 0 "R12" H 5750 7030 50 0000 C CNN
+F 1 "5.0K" H 5750 6850 50 0000 C CNN
+F 2 "" H 5750 6880 30 0000 C CNN
+F 3 "" V 5750 6950 30 0000 C CNN
+ 1 5700 6900
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q13
+U 1 1 68379995
+P 6250 6500
+F 0 "Q13" H 6150 6550 50 0000 R CNN
+F 1 "eSim_NPN" H 6200 6650 50 0000 R CNN
+F 2 "" H 6450 6600 29 0000 C CNN
+F 3 "" H 6250 6500 60 0000 C CNN
+ 1 6250 6500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q16
+U 1 1 6837A706
+P 8000 2250
+F 0 "Q16" H 7900 2300 50 0000 R CNN
+F 1 "eSim_NPN" H 7950 2400 50 0000 R CNN
+F 2 "" H 8200 2350 29 0000 C CNN
+F 3 "" H 8000 2250 60 0000 C CNN
+ 1 8000 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 6837A79F
+P 9450 2600
+F 0 "Q17" H 9350 2650 50 0000 R CNN
+F 1 "eSim_NPN" H 9400 2750 50 0000 R CNN
+F 2 "" H 9650 2700 29 0000 C CNN
+F 3 "" H 9450 2600 60 0000 C CNN
+ 1 9450 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 6837A926
+P 7450 1800
+F 0 "D2" H 7450 1900 50 0000 C CNN
+F 1 "eSim_Diode" H 7450 1700 50 0000 C CNN
+F 2 "" H 7450 1800 60 0000 C CNN
+F 3 "" H 7450 1800 60 0000 C CNN
+ 1 7450 1800
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R15
+U 1 1 6837AA35
+P 7400 1200
+F 0 "R15" H 7450 1330 50 0000 C CNN
+F 1 "10K" H 7450 1150 50 0000 C CNN
+F 2 "" H 7450 1180 30 0000 C CNN
+F 3 "" V 7450 1250 30 0000 C CNN
+ 1 7400 1200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q15
+U 1 1 6837AE59
+P 7200 2900
+F 0 "Q15" H 7100 2950 50 0000 R CNN
+F 1 "eSim_NPN" H 7150 3050 50 0000 R CNN
+F 2 "" H 7400 3000 29 0000 C CNN
+F 3 "" H 7200 2900 60 0000 C CNN
+ 1 7200 2900
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R16
+U 1 1 6837B14E
+P 8050 3100
+F 0 "R16" H 8100 3230 50 0000 C CNN
+F 1 "200" H 8100 3050 50 0000 C CNN
+F 2 "" H 8100 3080 30 0000 C CNN
+F 3 "" V 8100 3150 30 0000 C CNN
+ 1 8050 3100
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R20
+U 1 1 6837B3E1
+P 9600 3200
+F 0 "R20" H 9650 3330 50 0000 C CNN
+F 1 "0.3" H 9650 3150 50 0000 C CNN
+F 2 "" H 9650 3180 30 0000 C CNN
+F 3 "" V 9650 3250 30 0000 C CNN
+ 1 9600 3200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R19
+U 1 1 6837B589
+P 8750 2950
+F 0 "R19" H 8800 3080 50 0000 C CNN
+F 1 "240" H 8800 2900 50 0000 C CNN
+F 2 "" H 8800 2930 30 0000 C CNN
+F 3 "" V 8800 3000 30 0000 C CNN
+ 1 8750 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R17
+U 1 1 6837D366
+P 8650 4200
+F 0 "R17" H 8700 4330 50 0000 C CNN
+F 1 "0.25K" H 8700 4150 50 0000 C CNN
+F 2 "" H 8700 4180 30 0000 C CNN
+F 3 "" V 8700 4250 30 0000 C CNN
+ 1 8650 4200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R18
+U 1 1 6837D3FF
+P 8650 5500
+F 0 "R18" H 8700 5630 50 0000 C CNN
+F 1 "5.0K" H 8700 5450 50 0000 C CNN
+F 2 "" H 8700 5480 30 0000 C CNN
+F 3 "" V 8700 5550 30 0000 C CNN
+ 1 8650 5500
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 1450 2250 1450 1350
+Wire Wire Line
+ 1450 1350 3900 1350
+Wire Wire Line
+ 2200 3150 1450 3150
+Wire Wire Line
+ 1450 2550 1450 4250
+Wire Wire Line
+ 2500 2950 2500 2300
+Wire Wire Line
+ 2500 1350 2500 2000
+Wire Wire Line
+ 2500 3750 2500 3350
+Wire Wire Line
+ 2500 4050 2500 5050
+Wire Wire Line
+ 2500 5350 2500 6200
+Connection ~ 1450 3150
+Wire Wire Line
+ 2500 6500 2500 6700
+Wire Wire Line
+ 1450 6700 1450 4550
+Connection ~ 2500 6700
+Wire Wire Line
+ 4950 1050 4950 950
+Wire Wire Line
+ 4950 1350 4950 1500
+Wire Wire Line
+ 6350 1500 6350 1350
+Wire Wire Line
+ 6350 950 6350 1050
+Wire Wire Line
+ 5250 1700 6050 1700
+Wire Wire Line
+ 3800 2900 3800 4150
+Wire Wire Line
+ 4950 2900 4950 1900
+Wire Wire Line
+ 5650 1700 5650 2100
+Wire Wire Line
+ 5650 2100 4950 2100
+Connection ~ 4950 2100
+Connection ~ 5650 1700
+Wire Wire Line
+ 3500 4350 2500 4350
+Connection ~ 2500 4350
+Wire Wire Line
+ 5900 2300 5900 2200
+Wire Wire Line
+ 5900 2200 6350 2200
+Connection ~ 6350 2200
+Wire Wire Line
+ 3000 2500 3000 5800
+Wire Wire Line
+ 3000 5800 2500 5800
+Connection ~ 2500 5800
+Wire Wire Line
+ 3150 6700 3150 2700
+Connection ~ 3150 6700
+Wire Wire Line
+ 3800 6600 3800 7350
+Wire Wire Line
+ 3800 5750 3800 6200
+Wire Wire Line
+ 3800 4550 3800 5450
+Wire Wire Line
+ 4100 6400 4650 6400
+Wire Wire Line
+ 4350 6750 4350 6400
+Connection ~ 4350 6400
+Wire Wire Line
+ 4950 6600 4950 6800
+Wire Wire Line
+ 4950 7350 4950 7100
+Wire Wire Line
+ 4350 7050 4350 7350
+Wire Wire Line
+ 4200 6150 4200 6350
+Wire Wire Line
+ 4200 6350 4250 6350
+Wire Wire Line
+ 4250 6350 4250 6400
+Connection ~ 4250 6400
+Wire Wire Line
+ 3900 5950 3800 5950
+Connection ~ 3800 5950
+Wire Wire Line
+ 4950 6200 4950 5750
+Wire Wire Line
+ 4950 5200 4950 5450
+Wire Wire Line
+ 3800 5300 4950 5300
+Connection ~ 3800 5300
+Wire Wire Line
+ 4200 5750 4200 5300
+Connection ~ 4200 5300
+Connection ~ 4950 5300
+Wire Wire Line
+ 4950 4900 4950 4150
+Wire Wire Line
+ 4800 4500 4950 4500
+Connection ~ 4950 4500
+Wire Wire Line
+ 4500 4300 4500 3650
+Wire Wire Line
+ 3800 2900 4950 2900
+Wire Wire Line
+ 4500 2900 4500 3250
+Connection ~ 4500 2900
+Wire Wire Line
+ 3000 2500 5600 2500
+Wire Wire Line
+ 3150 2700 5900 2700
+Wire Wire Line
+ 4800 3450 9950 3450
+Wire Wire Line
+ 4950 3750 4950 3450
+Connection ~ 4950 3450
+Wire Wire Line
+ 5250 3950 8000 3950
+Wire Wire Line
+ 8000 3950 8000 5050
+Wire Wire Line
+ 8000 5050 8700 5050
+Wire Wire Line
+ 5350 5850 4950 5850
+Connection ~ 4950 5850
+Wire Wire Line
+ 5650 6150 5100 6150
+Wire Wire Line
+ 5100 6150 5100 6050
+Wire Wire Line
+ 5100 6050 4950 6050
+Connection ~ 4950 6050
+Wire Wire Line
+ 5650 5850 5850 5850
+Wire Wire Line
+ 5850 5850 5850 5750
+Wire Wire Line
+ 5850 5750 6350 5750
+Wire Wire Line
+ 5950 5950 5950 5750
+Connection ~ 5950 5750
+Wire Wire Line
+ 6350 4800 6350 6300
+Connection ~ 6350 5150
+Wire Wire Line
+ 6350 1900 6350 4500
+Wire Wire Line
+ 6650 4950 6650 4250
+Wire Wire Line
+ 6650 4250 6350 4250
+Connection ~ 6350 4250
+Wire Wire Line
+ 6650 5350 7000 5350
+Wire Wire Line
+ 7000 5350 7000 6350
+Wire Wire Line
+ 5950 6350 5950 6650
+Wire Wire Line
+ 5750 6650 6000 6650
+Wire Wire Line
+ 5750 6650 5750 6800
+Connection ~ 6350 5750
+Wire Wire Line
+ 6050 6500 6000 6500
+Wire Wire Line
+ 6000 6500 6000 6650
+Connection ~ 5950 6650
+Wire Wire Line
+ 6350 7350 6350 6700
+Wire Wire Line
+ 5750 7350 5750 7100
+Wire Wire Line
+ 3900 1350 3900 950
+Wire Wire Line
+ 3900 950 9200 950
+Connection ~ 2500 1350
+Connection ~ 4950 950
+Wire Wire Line
+ 9200 950 9200 1000
+Connection ~ 6350 950
+Wire Wire Line
+ 7800 2250 6650 2250
+Wire Wire Line
+ 6650 2250 6650 2050
+Wire Wire Line
+ 6650 2050 6350 2050
+Connection ~ 6350 2050
+Wire Wire Line
+ 7100 3100 7100 3450
+Connection ~ 7100 3450
+Wire Wire Line
+ 8650 2900 7400 2900
+Wire Wire Line
+ 7450 1950 7450 2800
+Wire Wire Line
+ 7450 2800 7550 2800
+Wire Wire Line
+ 7550 2800 7550 2900
+Connection ~ 7550 2900
+Wire Wire Line
+ 7450 1400 7450 1650
+Wire Wire Line
+ 7450 1100 7450 950
+Connection ~ 7450 950
+Wire Wire Line
+ 8100 2050 8100 950
+Connection ~ 8100 950
+Wire Wire Line
+ 8100 2450 8100 3000
+Wire Wire Line
+ 8100 3300 8100 3450
+Connection ~ 8100 3450
+Wire Wire Line
+ 9550 2800 9550 3000
+Wire Wire Line
+ 9550 3300 9550 3450
+Connection ~ 9550 3450
+Wire Wire Line
+ 9250 2600 8100 2600
+Connection ~ 8100 2600
+Wire Wire Line
+ 8950 2900 9550 2900
+Connection ~ 9550 2900
+Wire Wire Line
+ 9550 2400 9550 1000
+Wire Wire Line
+ 9200 1000 9850 1000
+Connection ~ 9550 1000
+Wire Wire Line
+ 8700 4400 8700 5400
+Connection ~ 8700 5050
+Wire Wire Line
+ 8700 6350 8700 5700
+Wire Wire Line
+ 8700 4100 8700 3450
+Connection ~ 8700 3450
+Wire Wire Line
+ 4500 4700 4500 5300
+Connection ~ 4500 5300
+Wire Wire Line
+ 1450 6700 3550 6700
+Wire Wire Line
+ 3550 6700 3550 6900
+Wire Wire Line
+ 3550 6900 3800 6900
+Wire Wire Line
+ 3800 7350 6700 7350
+Connection ~ 3800 6900
+Connection ~ 4350 7350
+Connection ~ 4950 7350
+Connection ~ 5750 7350
+Wire Wire Line
+ 6700 7350 6700 6350
+Wire Wire Line
+ 6700 6350 9700 6350
+Connection ~ 6350 7350
+Connection ~ 7000 6350
+Connection ~ 8700 6350
+$Comp
+L PORT U1
+U 2 1 683804D4
+P 9950 6350
+F 0 "U1" H 10000 6450 30 0000 C CNN
+F 1 "PORT" H 9950 6350 30 0000 C CNN
+F 2 "" H 9950 6350 60 0000 C CNN
+F 3 "" H 9950 6350 60 0000 C CNN
+ 2 9950 6350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6838073F
+P 10100 1000
+F 0 "U1" H 10150 1100 30 0000 C CNN
+F 1 "PORT" H 10100 1000 30 0000 C CNN
+F 2 "" H 10100 1000 60 0000 C CNN
+F 3 "" H 10100 1000 60 0000 C CNN
+ 1 10100 1000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6838098E
+P 10200 3450
+F 0 "U1" H 10250 3550 30 0000 C CNN
+F 1 "PORT" H 10200 3450 30 0000 C CNN
+F 2 "" H 10200 3450 60 0000 C CNN
+F 3 "" H 10200 3450 60 0000 C CNN
+ 3 10200 3450
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7100 2700 7100 2250
+Connection ~ 7100 2250
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800.sub b/library/SubcircuitLibrary/MCT7800/MCT7800.sub
new file mode 100644
index 000000000..539a1707d
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/MCT7800.sub
@@ -0,0 +1,49 @@
+* Subcircuit MCT7800
+.subckt MCT7800 net-_q16-pad1_ net-_d1-pad1_ net-_q15-pad3_
+* c:\fossee\esim\library\subcircuitlibrary\mct7800\mct7800.cir
+.include BC547B.lib
+.include PNP.lib
+.include ZenerD1N750.lib
+r1 net-_q16-pad1_ net-_d1-pad2_ 100
+r2 net-_q16-pad1_ net-_q1-pad1_ 500
+q1 net-_q1-pad1_ net-_d1-pad2_ net-_q1-pad3_ BC547B
+r3 net-_q1-pad3_ net-_q2-pad2_ 3.3k
+r4 net-_q2-pad2_ net-_q10-pad2_ 2.7k
+r5 net-_q10-pad2_ net-_d1-pad1_ 500
+d1 net-_d1-pad1_ net-_d1-pad2_ D1N750
+q8 net-_q12-pad2_ net-_q12-pad2_ net-_q8-pad3_ Q2N2907A
+q12 net-_q10-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A
+r13 net-_q16-pad1_ net-_q12-pad3_ 100k
+r8 net-_q16-pad1_ net-_q8-pad3_ 100
+q2 net-_q12-pad2_ net-_q2-pad2_ net-_q2-pad3_ BC547B
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_d1-pad1_ BC547B
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d1-pad1_ BC547B
+r6 net-_q2-pad3_ net-_q3-pad1_ 1.4k
+q7 net-_c1-pad1_ net-_q3-pad2_ net-_q7-pad3_ BC547B
+r7 net-_q3-pad2_ net-_d1-pad1_ 6.0k
+r11 net-_q7-pad3_ net-_d1-pad1_ 1.0k
+q4 net-_q2-pad3_ net-_q3-pad1_ net-_q3-pad2_ BC547B
+r10 net-_q2-pad3_ net-_c1-pad1_ 28k
+r9 net-_q6-pad2_ net-_q2-pad3_ 6.0k
+q6 net-_q5-pad3_ net-_q6-pad2_ net-_q2-pad3_ BC547B
+q5 net-_q12-pad2_ net-_q15-pad3_ net-_q5-pad3_ BC547B
+q9 net-_q15-pad3_ net-_q9-pad2_ net-_q6-pad2_ BC547B
+c1 net-_c1-pad1_ net-_c1-pad2_ 30p
+q11 net-_c1-pad2_ net-_c1-pad1_ net-_q11-pad3_ BC547B
+q14 net-_d1-pad1_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A
+r14 net-_q10-pad1_ net-_c1-pad2_ 2.0k
+r12 net-_q11-pad3_ net-_d1-pad1_ 5.0k
+q13 net-_c1-pad2_ net-_q11-pad3_ net-_d1-pad1_ BC547B
+q16 net-_q16-pad1_ net-_q10-pad1_ net-_q16-pad3_ BC547B
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_q17-pad3_ BC547B
+d2 net-_d2-pad1_ net-_d2-pad2_ D1N750
+r15 net-_q16-pad1_ net-_d2-pad2_ 10k
+q15 net-_q10-pad1_ net-_d2-pad1_ net-_q15-pad3_ BC547B
+r16 net-_q16-pad3_ net-_q15-pad3_ 200
+r20 net-_q15-pad3_ net-_q17-pad3_ 0.3
+r19 net-_d2-pad1_ net-_q17-pad3_ 240
+r17 net-_q15-pad3_ net-_q9-pad2_ 0.25k
+r18 net-_q9-pad2_ net-_d1-pad1_ 5.0k
+* Control Statements
+
+.ends MCT7800
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MCT7800/MCT7800_Previous_Values.xml b/library/SubcircuitLibrary/MCT7800/MCT7800_Previous_Values.xml
new file mode 100644
index 000000000..e86a9aceb
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/MCT7800_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecsecC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\ZenerD1N750.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\BC547B.lib
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MCT7800/PNP.lib b/library/SubcircuitLibrary/MCT7800/PNP.lib
new file mode 100644
index 000000000..7edda0eab
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/MCT7800/ZenerD1N750.lib b/library/SubcircuitLibrary/MCT7800/ZenerD1N750.lib
new file mode 100644
index 000000000..890c37fe2
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/ZenerD1N750.lib
@@ -0,0 +1,3 @@
+.model D1N750 D( Is=880.5E-18 Rs=.25 Ikf=0 N=1 Xti=3 Eg=1.11 Cjo=175p M=.5516
++ Vj=.75 Fc=.5 Isr=1.859n Nr=2 Bv=8.1 Ibv=20.245m Nbv=1.6989 Ibvl=1.9556m
++ Nbvl=14.976 Tbv1=-21.277u)
diff --git a/library/SubcircuitLibrary/MCT7800/analysis b/library/SubcircuitLibrary/MCT7800/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/MCT7800/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011-cache.lib b/library/SubcircuitLibrary/MMC4011/MMC4011-cache.lib
new file mode 100644
index 000000000..348446c2e
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/MMC4011-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.bak b/library/SubcircuitLibrary/MMC4011/MMC4011.bak
new file mode 100644
index 000000000..427130294
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/MMC4011.bak
@@ -0,0 +1,57 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MMC4011-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.cir b/library/SubcircuitLibrary/MMC4011/MMC4011.cir
new file mode 100644
index 000000000..ad9556e1d
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/MMC4011.cir
@@ -0,0 +1,51 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\MMC4011\MMC4011.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/20/25 01:25:37
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M2 Net-_M1-Pad1_ /A /VDD /VDD eSim_MOS_P
+M1 Net-_M1-Pad1_ /A /VSS /VSS eSim_MOS_N
+M6 Net-_M11-Pad2_ /B /VDD /VDD eSim_MOS_P
+M5 Net-_M11-Pad2_ /B /VSS /VSS eSim_MOS_N
+M9 Net-_M11-Pad1_ Net-_M1-Pad1_ /VSS /VSS eSim_MOS_N
+M12 Net-_M12-Pad1_ Net-_M1-Pad1_ /VDD /VDD eSim_MOS_P
+M13 Net-_M11-Pad1_ Net-_M11-Pad2_ Net-_M12-Pad1_ /VDD eSim_MOS_P
+M11 Net-_M11-Pad1_ Net-_M11-Pad2_ /VSS /VSS eSim_MOS_N
+M18 /J Net-_M11-Pad1_ /VDD /VDD eSim_MOS_P
+U1 /A /B /J /K /C /D /VSS /E /F /L /M /G /H /VDD PORT
+M17 /J Net-_M11-Pad1_ /VSS /VSS eSim_MOS_N
+M22 Net-_M21-Pad1_ /C /VDD /VDD eSim_MOS_P
+M21 Net-_M21-Pad1_ /C /VSS /VSS eSim_MOS_N
+M26 Net-_M25-Pad1_ /D /VDD /VDD eSim_MOS_P
+M25 Net-_M25-Pad1_ /D /VSS /VSS eSim_MOS_N
+M29 Net-_M29-Pad1_ Net-_M21-Pad1_ /VSS /VSS eSim_MOS_N
+M32 Net-_M32-Pad1_ Net-_M21-Pad1_ /VDD /VDD eSim_MOS_P
+M33 Net-_M29-Pad1_ Net-_M25-Pad1_ Net-_M32-Pad1_ /VDD eSim_MOS_P
+M31 Net-_M29-Pad1_ Net-_M25-Pad1_ /VSS /VSS eSim_MOS_N
+M38 /K Net-_M29-Pad1_ /VDD /VDD eSim_MOS_P
+M37 /K Net-_M29-Pad1_ /VSS /VSS eSim_MOS_N
+M4 Net-_M10-Pad2_ /E /VDD /VDD eSim_MOS_P
+M3 Net-_M10-Pad2_ /E /VSS /VSS eSim_MOS_N
+M8 Net-_M14-Pad2_ /F /VDD /VDD eSim_MOS_P
+M7 Net-_M14-Pad2_ /F /VSS /VSS eSim_MOS_N
+M10 Net-_M10-Pad1_ Net-_M10-Pad2_ /VSS /VSS eSim_MOS_N
+M15 Net-_M15-Pad1_ Net-_M10-Pad2_ /VDD /VDD eSim_MOS_P
+M16 Net-_M10-Pad1_ Net-_M14-Pad2_ Net-_M15-Pad1_ /VDD eSim_MOS_P
+M14 Net-_M10-Pad1_ Net-_M14-Pad2_ /VSS /VSS eSim_MOS_N
+M20 /L Net-_M10-Pad1_ /VDD /VDD eSim_MOS_P
+M19 /L Net-_M10-Pad1_ /VSS /VSS eSim_MOS_N
+M24 Net-_M23-Pad1_ /G /VDD /VDD eSim_MOS_P
+M23 Net-_M23-Pad1_ /G /VSS /VSS eSim_MOS_N
+M28 Net-_M27-Pad1_ /H /VDD /VDD eSim_MOS_P
+M27 Net-_M27-Pad1_ /H /VSS /VSS eSim_MOS_N
+M30 Net-_M30-Pad1_ Net-_M23-Pad1_ /VSS /VSS eSim_MOS_N
+M35 Net-_M35-Pad1_ Net-_M23-Pad1_ /VDD /VDD eSim_MOS_P
+M36 Net-_M30-Pad1_ Net-_M27-Pad1_ Net-_M35-Pad1_ /VDD eSim_MOS_P
+M34 Net-_M30-Pad1_ Net-_M27-Pad1_ /VSS /VSS eSim_MOS_N
+M40 /M Net-_M30-Pad1_ /VDD /VDD eSim_MOS_P
+M39 /M Net-_M30-Pad1_ /VSS /VSS eSim_MOS_N
+
+.end
diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.cir.out b/library/SubcircuitLibrary/MMC4011/MMC4011.cir.out
new file mode 100644
index 000000000..f29417319
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/MMC4011.cir.out
@@ -0,0 +1,54 @@
+* c:\fossee\esim\library\subcircuitlibrary\mmc4011\mmc4011.cir
+
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+m2 net-_m1-pad1_ /a /vdd /vdd mos_p W=40u L=5u M=1
+m1 net-_m1-pad1_ /a /vss /vss mos_n W=100u L=100u M=1
+m6 net-_m11-pad2_ /b /vdd /vdd mos_p W=100u L=100u M=1
+m5 net-_m11-pad2_ /b /vss /vss mos_n W=100u L=100u M=1
+m9 net-_m11-pad1_ net-_m1-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m12 net-_m12-pad1_ net-_m1-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m13 net-_m11-pad1_ net-_m11-pad2_ net-_m12-pad1_ /vdd mos_p W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m11-pad2_ /vss /vss mos_n W=100u L=100u M=1
+m18 /j net-_m11-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+* u1 /a /b /j /k /c /d /vss /e /f /l /m /g /h /vdd port
+m17 /j net-_m11-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m22 net-_m21-pad1_ /c /vdd /vdd mos_p W=100u L=100u M=1
+m21 net-_m21-pad1_ /c /vss /vss mos_n W=100u L=100u M=1
+m26 net-_m25-pad1_ /d /vdd /vdd mos_p W=100u L=100u M=1
+m25 net-_m25-pad1_ /d /vss /vss mos_n W=100u L=100u M=1
+m29 net-_m29-pad1_ net-_m21-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m32 net-_m32-pad1_ net-_m21-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m33 net-_m29-pad1_ net-_m25-pad1_ net-_m32-pad1_ /vdd mos_p W=100u L=100u M=1
+m31 net-_m29-pad1_ net-_m25-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m38 /k net-_m29-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m37 /k net-_m29-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m4 net-_m10-pad2_ /e /vdd /vdd mos_p W=100u L=100u M=1
+m3 net-_m10-pad2_ /e /vss /vss mos_n W=100u L=100u M=1
+m8 net-_m14-pad2_ /f /vdd /vdd mos_p W=100u L=100u M=1
+m7 net-_m14-pad2_ /f /vss /vss mos_n W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ /vss /vss mos_n W=100u L=100u M=1
+m15 net-_m15-pad1_ net-_m10-pad2_ /vdd /vdd mos_p W=100u L=100u M=1
+m16 net-_m10-pad1_ net-_m14-pad2_ net-_m15-pad1_ /vdd mos_p W=100u L=100u M=1
+m14 net-_m10-pad1_ net-_m14-pad2_ /vss /vss mos_n W=100u L=100u M=1
+m20 /l net-_m10-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m19 /l net-_m10-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m24 net-_m23-pad1_ /g /vdd /vdd mos_p W=100u L=100u M=1
+m23 net-_m23-pad1_ /g /vss /vss mos_n W=100u L=100u M=1
+m28 net-_m27-pad1_ /h /vdd /vdd mos_p W=100u L=100u M=1
+m27 net-_m27-pad1_ /h /vss /vss mos_n W=100u L=100u M=1
+m30 net-_m30-pad1_ net-_m23-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m35 net-_m35-pad1_ net-_m23-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m36 net-_m30-pad1_ net-_m27-pad1_ net-_m35-pad1_ /vdd mos_p W=100u L=100u M=1
+m34 net-_m30-pad1_ net-_m27-pad1_ /vss /vss mos_n W=100u L=100u M=1
+m40 /m net-_m30-pad1_ /vdd /vdd mos_p W=100u L=100u M=1
+m39 /m net-_m30-pad1_ /vss /vss mos_n W=100u L=100u M=1
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.pro b/library/SubcircuitLibrary/MMC4011/MMC4011.pro
new file mode 100644
index 000000000..8fc830805
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/MMC4011.pro
@@ -0,0 +1,83 @@
+update=07/02/25 13:40:37
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.sch b/library/SubcircuitLibrary/MMC4011/MMC4011.sch
new file mode 100644
index 000000000..c4134d371
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/MMC4011.sch
@@ -0,0 +1,1314 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MMC4011-cache
+LIBS:SINGLE-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_P M2
+U 1 1 68545DED
+P 6100 5800
+F 0 "M2" H 6050 5850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 6150 5950 50 0000 R CNN
+F 2 "" H 6350 5900 29 0000 C CNN
+F 3 "" H 6150 5800 60 0000 C CNN
+ 1 6100 5800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M1
+U 1 1 68545DEE
+P 6050 6650
+F 0 "M1" H 6050 6500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6150 6600 50 0000 R CNN
+F 2 "" H 6350 6350 29 0000 C CNN
+F 3 "" H 6150 6450 60 0000 C CNN
+ 1 6050 6650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M6
+U 1 1 68545DEF
+P 7800 6550
+F 0 "M6" H 7750 6600 50 0000 R CNN
+F 1 "eSim_MOS_P" H 7850 6700 50 0000 R CNN
+F 2 "" H 8050 6650 29 0000 C CNN
+F 3 "" H 7850 6550 60 0000 C CNN
+ 1 7800 6550
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 68545DF0
+P 7750 7200
+F 0 "M5" H 7750 7050 50 0000 R CNN
+F 1 "eSim_MOS_N" H 7850 7150 50 0000 R CNN
+F 2 "" H 8050 6900 29 0000 C CNN
+F 3 "" H 7850 7000 60 0000 C CNN
+ 1 7750 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M9
+U 1 1 68545DF1
+P 9200 7900
+F 0 "M9" H 9200 7750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9300 7850 50 0000 R CNN
+F 2 "" H 9500 7600 29 0000 C CNN
+F 3 "" H 9300 7700 60 0000 C CNN
+ 1 9200 7900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M12
+U 1 1 68545DF2
+P 10800 6000
+F 0 "M12" H 10750 6050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10850 6150 50 0000 R CNN
+F 2 "" H 11050 6100 29 0000 C CNN
+F 3 "" H 10850 6000 60 0000 C CNN
+ 1 10800 6000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M13
+U 1 1 68545DF3
+P 10800 6750
+F 0 "M13" H 10750 6800 50 0000 R CNN
+F 1 "eSim_MOS_P" H 10850 6900 50 0000 R CNN
+F 2 "" H 11050 6850 29 0000 C CNN
+F 3 "" H 10850 6750 60 0000 C CNN
+ 1 10800 6750
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M11
+U 1 1 68545DF4
+P 10500 7900
+F 0 "M11" H 10500 7750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10600 7850 50 0000 R CNN
+F 2 "" H 10800 7600 29 0000 C CNN
+F 3 "" H 10600 7700 60 0000 C CNN
+ 1 10500 7900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M18
+U 1 1 68545DF5
+P 12200 6700
+F 0 "M18" H 12150 6750 50 0000 R CNN
+F 1 "eSim_MOS_P" H 12250 6850 50 0000 R CNN
+F 2 "" H 12450 6800 29 0000 C CNN
+F 3 "" H 12250 6700 60 0000 C CNN
+ 1 12200 6700
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68545DF6
+P 4200 6200
+F 0 "U1" H 4250 6300 30 0000 C CNN
+F 1 "PORT" H 4200 6200 30 0000 C CNN
+F 2 "" H 4200 6200 60 0000 C CNN
+F 3 "" H 4200 6200 60 0000 C CNN
+ 1 4200 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68545DF7
+P 4350 7800
+F 0 "U1" H 4400 7900 30 0000 C CNN
+F 1 "PORT" H 4350 7800 30 0000 C CNN
+F 2 "" H 4350 7800 60 0000 C CNN
+F 3 "" H 4350 7800 60 0000 C CNN
+ 2 4350 7800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68545DF8
+P 13950 7100
+F 0 "U1" H 14000 7200 30 0000 C CNN
+F 1 "PORT" H 13950 7100 30 0000 C CNN
+F 2 "" H 13950 7100 60 0000 C CNN
+F 3 "" H 13950 7100 60 0000 C CNN
+ 3 13950 7100
+ -1 0 0 1
+$EndComp
+Text Label 4600 6250 0 60 ~ 0
+A
+Text Label 4800 7800 0 60 ~ 0
+B
+Text Label 13350 7100 0 60 ~ 0
+J
+$Comp
+L eSim_MOS_N M17
+U 1 1 68545DFB
+P 12150 7300
+F 0 "M17" H 12150 7150 50 0000 R CNN
+F 1 "eSim_MOS_N" H 12250 7250 50 0000 R CNN
+F 2 "" H 12450 7000 29 0000 C CNN
+F 3 "" H 12250 7100 60 0000 C CNN
+ 1 12150 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M22
+U 1 1 6854613A
+P 19050 5600
+F 0 "M22" H 19000 5650 50 0000 R CNN
+F 1 "eSim_MOS_P" H 19100 5750 50 0000 R CNN
+F 2 "" H 19300 5700 29 0000 C CNN
+F 3 "" H 19100 5600 60 0000 C CNN
+ 1 19050 5600
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M21
+U 1 1 68546140
+P 19000 6450
+F 0 "M21" H 19000 6300 50 0000 R CNN
+F 1 "eSim_MOS_N" H 19100 6400 50 0000 R CNN
+F 2 "" H 19300 6150 29 0000 C CNN
+F 3 "" H 19100 6250 60 0000 C CNN
+ 1 19000 6450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M26
+U 1 1 6854614F
+P 20750 6350
+F 0 "M26" H 20700 6400 50 0000 R CNN
+F 1 "eSim_MOS_P" H 20800 6500 50 0000 R CNN
+F 2 "" H 21000 6450 29 0000 C CNN
+F 3 "" H 20800 6350 60 0000 C CNN
+ 1 20750 6350
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M25
+U 1 1 68546155
+P 20700 7000
+F 0 "M25" H 20700 6850 50 0000 R CNN
+F 1 "eSim_MOS_N" H 20800 6950 50 0000 R CNN
+F 2 "" H 21000 6700 29 0000 C CNN
+F 3 "" H 20800 6800 60 0000 C CNN
+ 1 20700 7000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M29
+U 1 1 6854616C
+P 22150 7700
+F 0 "M29" H 22150 7550 50 0000 R CNN
+F 1 "eSim_MOS_N" H 22250 7650 50 0000 R CNN
+F 2 "" H 22450 7400 29 0000 C CNN
+F 3 "" H 22250 7500 60 0000 C CNN
+ 1 22150 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M32
+U 1 1 6854617C
+P 23750 5800
+F 0 "M32" H 23700 5850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 23800 5950 50 0000 R CNN
+F 2 "" H 24000 5900 29 0000 C CNN
+F 3 "" H 23800 5800 60 0000 C CNN
+ 1 23750 5800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M33
+U 1 1 68546182
+P 23750 6550
+F 0 "M33" H 23700 6600 50 0000 R CNN
+F 1 "eSim_MOS_P" H 23800 6700 50 0000 R CNN
+F 2 "" H 24000 6650 29 0000 C CNN
+F 3 "" H 23800 6550 60 0000 C CNN
+ 1 23750 6550
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M31
+U 1 1 68546196
+P 23450 7700
+F 0 "M31" H 23450 7550 50 0000 R CNN
+F 1 "eSim_MOS_N" H 23550 7650 50 0000 R CNN
+F 2 "" H 23750 7400 29 0000 C CNN
+F 3 "" H 23550 7500 60 0000 C CNN
+ 1 23450 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M38
+U 1 1 685461A7
+P 25150 6500
+F 0 "M38" H 25100 6550 50 0000 R CNN
+F 1 "eSim_MOS_P" H 25200 6650 50 0000 R CNN
+F 2 "" H 25400 6600 29 0000 C CNN
+F 3 "" H 25200 6500 60 0000 C CNN
+ 1 25150 6500
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685461BE
+P 17150 6000
+F 0 "U1" H 17200 6100 30 0000 C CNN
+F 1 "PORT" H 17150 6000 30 0000 C CNN
+F 2 "" H 17150 6000 60 0000 C CNN
+F 3 "" H 17150 6000 60 0000 C CNN
+ 5 17150 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685461C4
+P 17300 7600
+F 0 "U1" H 17350 7700 30 0000 C CNN
+F 1 "PORT" H 17300 7600 30 0000 C CNN
+F 2 "" H 17300 7600 60 0000 C CNN
+F 3 "" H 17300 7600 60 0000 C CNN
+ 6 17300 7600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685461CA
+P 26900 6900
+F 0 "U1" H 26950 7000 30 0000 C CNN
+F 1 "PORT" H 26900 6900 30 0000 C CNN
+F 2 "" H 26900 6900 60 0000 C CNN
+F 3 "" H 26900 6900 60 0000 C CNN
+ 4 26900 6900
+ -1 0 0 1
+$EndComp
+Text Label 17550 6050 0 60 ~ 0
+C
+Text Label 17750 7600 0 60 ~ 0
+D
+Text Label 26300 6900 0 60 ~ 0
+K
+Text Label 30850 7550 0 60 ~ 0
+VDD
+$Comp
+L eSim_MOS_N M37
+U 1 1 685461EC
+P 25100 7100
+F 0 "M37" H 25100 6950 50 0000 R CNN
+F 1 "eSim_MOS_N" H 25200 7050 50 0000 R CNN
+F 2 "" H 25400 6800 29 0000 C CNN
+F 3 "" H 25200 6900 60 0000 C CNN
+ 1 25100 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 685463F0
+P 6400 13050
+F 0 "M4" H 6350 13100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 6450 13200 50 0000 R CNN
+F 2 "" H 6650 13150 29 0000 C CNN
+F 3 "" H 6450 13050 60 0000 C CNN
+ 1 6400 13050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M3
+U 1 1 685463F6
+P 6350 13900
+F 0 "M3" H 6350 13750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6450 13850 50 0000 R CNN
+F 2 "" H 6650 13600 29 0000 C CNN
+F 3 "" H 6450 13700 60 0000 C CNN
+ 1 6350 13900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M8
+U 1 1 68546405
+P 8100 13800
+F 0 "M8" H 8050 13850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 8150 13950 50 0000 R CNN
+F 2 "" H 8350 13900 29 0000 C CNN
+F 3 "" H 8150 13800 60 0000 C CNN
+ 1 8100 13800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M7
+U 1 1 6854640B
+P 8050 14450
+F 0 "M7" H 8050 14300 50 0000 R CNN
+F 1 "eSim_MOS_N" H 8150 14400 50 0000 R CNN
+F 2 "" H 8350 14150 29 0000 C CNN
+F 3 "" H 8150 14250 60 0000 C CNN
+ 1 8050 14450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 68546422
+P 9500 15150
+F 0 "M10" H 9500 15000 50 0000 R CNN
+F 1 "eSim_MOS_N" H 9600 15100 50 0000 R CNN
+F 2 "" H 9800 14850 29 0000 C CNN
+F 3 "" H 9600 14950 60 0000 C CNN
+ 1 9500 15150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M15
+U 1 1 68546432
+P 11100 13250
+F 0 "M15" H 11050 13300 50 0000 R CNN
+F 1 "eSim_MOS_P" H 11150 13400 50 0000 R CNN
+F 2 "" H 11350 13350 29 0000 C CNN
+F 3 "" H 11150 13250 60 0000 C CNN
+ 1 11100 13250
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M16
+U 1 1 68546438
+P 11100 14000
+F 0 "M16" H 11050 14050 50 0000 R CNN
+F 1 "eSim_MOS_P" H 11150 14150 50 0000 R CNN
+F 2 "" H 11350 14100 29 0000 C CNN
+F 3 "" H 11150 14000 60 0000 C CNN
+ 1 11100 14000
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M14
+U 1 1 6854644C
+P 10800 15150
+F 0 "M14" H 10800 15000 50 0000 R CNN
+F 1 "eSim_MOS_N" H 10900 15100 50 0000 R CNN
+F 2 "" H 11100 14850 29 0000 C CNN
+F 3 "" H 10900 14950 60 0000 C CNN
+ 1 10800 15150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M20
+U 1 1 6854645D
+P 12500 13950
+F 0 "M20" H 12450 14000 50 0000 R CNN
+F 1 "eSim_MOS_P" H 12550 14100 50 0000 R CNN
+F 2 "" H 12750 14050 29 0000 C CNN
+F 3 "" H 12550 13950 60 0000 C CNN
+ 1 12500 13950
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68546474
+P 4500 13450
+F 0 "U1" H 4550 13550 30 0000 C CNN
+F 1 "PORT" H 4500 13450 30 0000 C CNN
+F 2 "" H 4500 13450 60 0000 C CNN
+F 3 "" H 4500 13450 60 0000 C CNN
+ 8 4500 13450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6854647A
+P 4650 15050
+F 0 "U1" H 4700 15150 30 0000 C CNN
+F 1 "PORT" H 4650 15050 30 0000 C CNN
+F 2 "" H 4650 15050 60 0000 C CNN
+F 3 "" H 4650 15050 60 0000 C CNN
+ 9 4650 15050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 68546480
+P 14250 14350
+F 0 "U1" H 14300 14450 30 0000 C CNN
+F 1 "PORT" H 14250 14350 30 0000 C CNN
+F 2 "" H 14250 14350 60 0000 C CNN
+F 3 "" H 14250 14350 60 0000 C CNN
+ 10 14250 14350
+ -1 0 0 1
+$EndComp
+Text Label 4900 13500 0 60 ~ 0
+E
+Text Label 5100 15050 0 60 ~ 0
+F
+Text Label 13650 14350 0 60 ~ 0
+L
+$Comp
+L eSim_MOS_N M19
+U 1 1 685464A2
+P 12450 14550
+F 0 "M19" H 12450 14400 50 0000 R CNN
+F 1 "eSim_MOS_N" H 12550 14500 50 0000 R CNN
+F 2 "" H 12750 14250 29 0000 C CNN
+F 3 "" H 12550 14350 60 0000 C CNN
+ 1 12450 14550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M24
+U 1 1 685464A8
+P 19350 12850
+F 0 "M24" H 19300 12900 50 0000 R CNN
+F 1 "eSim_MOS_P" H 19400 13000 50 0000 R CNN
+F 2 "" H 19600 12950 29 0000 C CNN
+F 3 "" H 19400 12850 60 0000 C CNN
+ 1 19350 12850
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M23
+U 1 1 685464AE
+P 19300 13700
+F 0 "M23" H 19300 13550 50 0000 R CNN
+F 1 "eSim_MOS_N" H 19400 13650 50 0000 R CNN
+F 2 "" H 19600 13400 29 0000 C CNN
+F 3 "" H 19400 13500 60 0000 C CNN
+ 1 19300 13700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M28
+U 1 1 685464BD
+P 21050 13600
+F 0 "M28" H 21000 13650 50 0000 R CNN
+F 1 "eSim_MOS_P" H 21100 13750 50 0000 R CNN
+F 2 "" H 21300 13700 29 0000 C CNN
+F 3 "" H 21100 13600 60 0000 C CNN
+ 1 21050 13600
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M27
+U 1 1 685464C3
+P 21000 14250
+F 0 "M27" H 21000 14100 50 0000 R CNN
+F 1 "eSim_MOS_N" H 21100 14200 50 0000 R CNN
+F 2 "" H 21300 13950 29 0000 C CNN
+F 3 "" H 21100 14050 60 0000 C CNN
+ 1 21000 14250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M30
+U 1 1 685464DA
+P 22450 14950
+F 0 "M30" H 22450 14800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 22550 14900 50 0000 R CNN
+F 2 "" H 22750 14650 29 0000 C CNN
+F 3 "" H 22550 14750 60 0000 C CNN
+ 1 22450 14950
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M35
+U 1 1 685464EA
+P 24050 13050
+F 0 "M35" H 24000 13100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 24100 13200 50 0000 R CNN
+F 2 "" H 24300 13150 29 0000 C CNN
+F 3 "" H 24100 13050 60 0000 C CNN
+ 1 24050 13050
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_P M36
+U 1 1 685464F0
+P 24050 13800
+F 0 "M36" H 24000 13850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 24100 13950 50 0000 R CNN
+F 2 "" H 24300 13900 29 0000 C CNN
+F 3 "" H 24100 13800 60 0000 C CNN
+ 1 24050 13800
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_MOS_N M34
+U 1 1 68546504
+P 23750 14950
+F 0 "M34" H 23750 14800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 23850 14900 50 0000 R CNN
+F 2 "" H 24050 14650 29 0000 C CNN
+F 3 "" H 23850 14750 60 0000 C CNN
+ 1 23750 14950
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M40
+U 1 1 68546515
+P 25450 13750
+F 0 "M40" H 25400 13800 50 0000 R CNN
+F 1 "eSim_MOS_P" H 25500 13900 50 0000 R CNN
+F 2 "" H 25700 13850 29 0000 C CNN
+F 3 "" H 25500 13750 60 0000 C CNN
+ 1 25450 13750
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6854652C
+P 17450 13250
+F 0 "U1" H 17500 13350 30 0000 C CNN
+F 1 "PORT" H 17450 13250 30 0000 C CNN
+F 2 "" H 17450 13250 60 0000 C CNN
+F 3 "" H 17450 13250 60 0000 C CNN
+ 12 17450 13250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68546532
+P 17600 14850
+F 0 "U1" H 17650 14950 30 0000 C CNN
+F 1 "PORT" H 17600 14850 30 0000 C CNN
+F 2 "" H 17600 14850 60 0000 C CNN
+F 3 "" H 17600 14850 60 0000 C CNN
+ 13 17600 14850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68546538
+P 27200 14150
+F 0 "U1" H 27250 14250 30 0000 C CNN
+F 1 "PORT" H 27200 14150 30 0000 C CNN
+F 2 "" H 27200 14150 60 0000 C CNN
+F 3 "" H 27200 14150 60 0000 C CNN
+ 11 27200 14150
+ -1 0 0 1
+$EndComp
+Text Label 17850 13300 0 60 ~ 0
+G
+Text Label 18050 14850 0 60 ~ 0
+H
+Text Label 26600 14150 0 60 ~ 0
+M
+Text Label 1800 12300 0 60 ~ 0
+VSS
+$Comp
+L eSim_MOS_N M39
+U 1 1 6854655A
+P 25400 14350
+F 0 "M39" H 25400 14200 50 0000 R CNN
+F 1 "eSim_MOS_N" H 25500 14300 50 0000 R CNN
+F 2 "" H 25700 14050 29 0000 C CNN
+F 3 "" H 25500 14150 60 0000 C CNN
+ 1 25400 14350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6250 6000 6250 6650
+Wire Wire Line
+ 5950 5800 5500 5800
+Wire Wire Line
+ 5500 5800 5500 6850
+Wire Wire Line
+ 5500 6850 5950 6850
+Wire Wire Line
+ 6250 5600 6250 4350
+Wire Wire Line
+ 6250 4350 14150 4350
+Wire Wire Line
+ 6350 4350 6350 5650
+Wire Wire Line
+ 6250 7050 6250 8750
+Wire Wire Line
+ 2300 8750 12450 8750
+Wire Wire Line
+ 7950 6750 7950 7200
+Wire Wire Line
+ 7950 7600 7950 8750
+Connection ~ 7950 8750
+Wire Wire Line
+ 8050 7550 8050 8750
+Wire Wire Line
+ 7650 6550 7350 6550
+Wire Wire Line
+ 7350 6550 7350 7400
+Wire Wire Line
+ 7350 7400 7650 7400
+Wire Wire Line
+ 7350 6950 6850 6950
+Wire Wire Line
+ 6850 6950 6850 7800
+Wire Wire Line
+ 6850 7800 4600 7800
+Connection ~ 7350 6950
+Wire Wire Line
+ 5500 6250 4450 6250
+Wire Wire Line
+ 4450 6250 4450 6200
+Connection ~ 5500 6250
+Wire Wire Line
+ 7950 6350 7950 4350
+Connection ~ 7950 4350
+Wire Wire Line
+ 8050 4350 8050 6400
+Wire Wire Line
+ 9400 8300 9400 8750
+Connection ~ 9400 8750
+Wire Wire Line
+ 9500 8250 9500 8750
+Wire Wire Line
+ 6250 6300 6900 6300
+Wire Wire Line
+ 6900 6300 6900 5600
+Wire Wire Line
+ 6900 5600 10650 5600
+Connection ~ 6250 6300
+Wire Wire Line
+ 9100 8100 8550 8100
+Wire Wire Line
+ 8550 8100 8550 5600
+Connection ~ 8550 5600
+Wire Wire Line
+ 10950 6200 10950 6550
+Wire Wire Line
+ 10650 5600 10650 6000
+Wire Wire Line
+ 10950 5800 10950 4500
+Wire Wire Line
+ 10950 4500 10850 4500
+Wire Wire Line
+ 10850 4500 10850 4350
+Connection ~ 10850 4350
+Wire Wire Line
+ 11050 4350 11050 5850
+Wire Wire Line
+ 11050 6600 11050 6450
+Wire Wire Line
+ 11050 6450 11250 6450
+Wire Wire Line
+ 11250 6450 11250 4350
+Wire Wire Line
+ 7950 6950 10150 6950
+Wire Wire Line
+ 10150 6950 10150 6750
+Wire Wire Line
+ 10150 6750 10650 6750
+Connection ~ 7950 6950
+Wire Wire Line
+ 10700 8300 10700 8750
+Connection ~ 10700 8750
+Wire Wire Line
+ 10800 8250 10800 8750
+Wire Wire Line
+ 9400 7900 9400 7600
+Wire Wire Line
+ 9400 7600 10950 7600
+Wire Wire Line
+ 10950 7600 10950 6950
+Wire Wire Line
+ 10700 7900 10700 7600
+Connection ~ 10700 7600
+Wire Wire Line
+ 10400 8100 9850 8100
+Wire Wire Line
+ 9850 8100 9850 6950
+Connection ~ 9850 6950
+Wire Wire Line
+ 12350 6900 12350 7300
+Wire Wire Line
+ 12350 4350 12350 6500
+Wire Wire Line
+ 12450 4350 12450 6550
+Wire Wire Line
+ 12350 8750 12350 7700
+Wire Wire Line
+ 12450 8750 12450 7650
+Wire Wire Line
+ 12050 6700 11900 6700
+Wire Wire Line
+ 11900 6700 11900 7500
+Wire Wire Line
+ 11900 7500 12050 7500
+Wire Wire Line
+ 11900 7050 11300 7050
+Wire Wire Line
+ 11300 7050 11300 7200
+Wire Wire Line
+ 11300 7200 10950 7200
+Connection ~ 10950 7200
+Connection ~ 11900 7050
+Wire Wire Line
+ 12350 7100 13700 7100
+Connection ~ 12350 7100
+Connection ~ 12350 8750
+Connection ~ 12350 4350
+Connection ~ 11250 4350
+Connection ~ 6350 4350
+Wire Wire Line
+ 6350 7000 6350 8750
+Connection ~ 6350 8750
+Connection ~ 8050 8750
+Connection ~ 9500 8750
+Connection ~ 10800 8750
+Connection ~ 12450 4350
+Connection ~ 11050 4350
+Connection ~ 8050 4350
+Wire Wire Line
+ 19200 5800 19200 6450
+Wire Wire Line
+ 18900 5600 18450 5600
+Wire Wire Line
+ 18450 5600 18450 6650
+Wire Wire Line
+ 18450 6650 18900 6650
+Wire Wire Line
+ 19200 5400 19200 4150
+Wire Wire Line
+ 19200 4150 30550 4150
+Wire Wire Line
+ 19300 4150 19300 5450
+Wire Wire Line
+ 19200 6850 19200 8550
+Wire Wire Line
+ 15050 8550 25400 8550
+Wire Wire Line
+ 20900 6550 20900 7000
+Wire Wire Line
+ 20900 7400 20900 8550
+Connection ~ 20900 8550
+Wire Wire Line
+ 21000 7350 21000 8550
+Wire Wire Line
+ 20600 6350 20300 6350
+Wire Wire Line
+ 20300 6350 20300 7200
+Wire Wire Line
+ 20300 7200 20600 7200
+Wire Wire Line
+ 20300 6750 19800 6750
+Wire Wire Line
+ 19800 6750 19800 7600
+Wire Wire Line
+ 19800 7600 17550 7600
+Connection ~ 20300 6750
+Wire Wire Line
+ 18450 6050 17400 6050
+Wire Wire Line
+ 17400 6050 17400 6000
+Connection ~ 18450 6050
+Wire Wire Line
+ 20900 6150 20900 4150
+Connection ~ 20900 4150
+Wire Wire Line
+ 21000 4150 21000 6200
+Wire Wire Line
+ 22350 8100 22350 8550
+Connection ~ 22350 8550
+Wire Wire Line
+ 22450 8050 22450 8550
+Wire Wire Line
+ 19200 6100 19850 6100
+Wire Wire Line
+ 19850 6100 19850 5400
+Wire Wire Line
+ 19850 5400 23600 5400
+Connection ~ 19200 6100
+Wire Wire Line
+ 22050 7900 21500 7900
+Wire Wire Line
+ 21500 7900 21500 5400
+Connection ~ 21500 5400
+Wire Wire Line
+ 23900 6000 23900 6350
+Wire Wire Line
+ 23600 5400 23600 5800
+Wire Wire Line
+ 23900 5600 23900 4300
+Wire Wire Line
+ 23900 4300 23800 4300
+Wire Wire Line
+ 23800 4300 23800 4150
+Connection ~ 23800 4150
+Wire Wire Line
+ 24000 4150 24000 5650
+Wire Wire Line
+ 24000 6400 24000 6250
+Wire Wire Line
+ 24000 6250 24200 6250
+Wire Wire Line
+ 24200 6250 24200 4150
+Wire Wire Line
+ 20900 6750 23100 6750
+Wire Wire Line
+ 23100 6750 23100 6550
+Wire Wire Line
+ 23100 6550 23600 6550
+Connection ~ 20900 6750
+Wire Wire Line
+ 23650 8100 23650 8550
+Connection ~ 23650 8550
+Wire Wire Line
+ 23750 8050 23750 8550
+Wire Wire Line
+ 22350 7700 22350 7400
+Wire Wire Line
+ 22350 7400 23900 7400
+Wire Wire Line
+ 23900 7400 23900 6750
+Wire Wire Line
+ 23650 7700 23650 7400
+Connection ~ 23650 7400
+Wire Wire Line
+ 23350 7900 22800 7900
+Wire Wire Line
+ 22800 7900 22800 6750
+Connection ~ 22800 6750
+Wire Wire Line
+ 25300 6700 25300 7100
+Wire Wire Line
+ 25300 4150 25300 6300
+Wire Wire Line
+ 25400 4150 25400 6350
+Wire Wire Line
+ 25300 8550 25300 7500
+Wire Wire Line
+ 25400 8550 25400 7450
+Wire Wire Line
+ 25000 6500 24850 6500
+Wire Wire Line
+ 24850 6500 24850 7300
+Wire Wire Line
+ 24850 7300 25000 7300
+Wire Wire Line
+ 24850 6850 24250 6850
+Wire Wire Line
+ 24250 6850 24250 7000
+Wire Wire Line
+ 24250 7000 23900 7000
+Connection ~ 23900 7000
+Connection ~ 24850 6850
+Wire Wire Line
+ 25300 6900 26650 6900
+Connection ~ 25300 6900
+Connection ~ 25300 8550
+Connection ~ 25300 4150
+Connection ~ 24200 4150
+Connection ~ 19300 4150
+Wire Wire Line
+ 19300 6800 19300 8550
+Connection ~ 19300 8550
+Connection ~ 21000 8550
+Connection ~ 22450 8550
+Connection ~ 23750 8550
+Connection ~ 25400 4150
+Connection ~ 24000 4150
+Connection ~ 21000 4150
+Wire Wire Line
+ 6550 13250 6550 13900
+Wire Wire Line
+ 6250 13050 5800 13050
+Wire Wire Line
+ 5800 13050 5800 14100
+Wire Wire Line
+ 5800 14100 6250 14100
+Wire Wire Line
+ 6550 12850 6550 11600
+Wire Wire Line
+ 6550 11600 17150 11600
+Wire Wire Line
+ 6650 11600 6650 12900
+Wire Wire Line
+ 6550 14300 6550 16000
+Wire Wire Line
+ 2300 16000 12750 16000
+Wire Wire Line
+ 8250 14000 8250 14450
+Wire Wire Line
+ 8250 14850 8250 16000
+Connection ~ 8250 16000
+Wire Wire Line
+ 8350 14800 8350 16000
+Wire Wire Line
+ 7950 13800 7650 13800
+Wire Wire Line
+ 7650 13800 7650 14650
+Wire Wire Line
+ 7650 14650 7950 14650
+Wire Wire Line
+ 7650 14200 7150 14200
+Wire Wire Line
+ 7150 14200 7150 15050
+Wire Wire Line
+ 7150 15050 4900 15050
+Connection ~ 7650 14200
+Wire Wire Line
+ 5800 13500 4750 13500
+Wire Wire Line
+ 4750 13500 4750 13450
+Connection ~ 5800 13500
+Wire Wire Line
+ 8250 13600 8250 11600
+Connection ~ 8250 11600
+Wire Wire Line
+ 8350 11600 8350 13650
+Wire Wire Line
+ 9700 15550 9700 16000
+Connection ~ 9700 16000
+Wire Wire Line
+ 9800 15500 9800 16000
+Wire Wire Line
+ 6550 13550 7200 13550
+Wire Wire Line
+ 7200 13550 7200 12850
+Wire Wire Line
+ 7200 12850 10950 12850
+Connection ~ 6550 13550
+Wire Wire Line
+ 9400 15350 8850 15350
+Wire Wire Line
+ 8850 15350 8850 12850
+Connection ~ 8850 12850
+Wire Wire Line
+ 11250 13450 11250 13800
+Wire Wire Line
+ 10950 12850 10950 13250
+Wire Wire Line
+ 11250 13050 11250 11750
+Wire Wire Line
+ 11250 11750 11150 11750
+Wire Wire Line
+ 11150 11750 11150 11600
+Connection ~ 11150 11600
+Wire Wire Line
+ 11350 11600 11350 13100
+Wire Wire Line
+ 11350 13850 11350 13700
+Wire Wire Line
+ 11350 13700 11550 13700
+Wire Wire Line
+ 11550 13700 11550 11600
+Wire Wire Line
+ 8250 14200 10450 14200
+Wire Wire Line
+ 10450 14200 10450 14000
+Wire Wire Line
+ 10450 14000 10950 14000
+Connection ~ 8250 14200
+Wire Wire Line
+ 11000 15550 11000 16000
+Connection ~ 11000 16000
+Wire Wire Line
+ 11100 15500 11100 16000
+Wire Wire Line
+ 9700 15150 9700 14850
+Wire Wire Line
+ 9700 14850 11250 14850
+Wire Wire Line
+ 11250 14850 11250 14200
+Wire Wire Line
+ 11000 15150 11000 14850
+Connection ~ 11000 14850
+Wire Wire Line
+ 10700 15350 10150 15350
+Wire Wire Line
+ 10150 15350 10150 14200
+Connection ~ 10150 14200
+Wire Wire Line
+ 12650 14150 12650 14550
+Wire Wire Line
+ 12650 11600 12650 13750
+Wire Wire Line
+ 12750 11600 12750 13800
+Wire Wire Line
+ 12650 16000 12650 14950
+Wire Wire Line
+ 12750 16000 12750 14900
+Wire Wire Line
+ 12350 13950 12200 13950
+Wire Wire Line
+ 12200 13950 12200 14750
+Wire Wire Line
+ 12200 14750 12350 14750
+Wire Wire Line
+ 12200 14300 11600 14300
+Wire Wire Line
+ 11600 14300 11600 14450
+Wire Wire Line
+ 11600 14450 11250 14450
+Connection ~ 11250 14450
+Connection ~ 12200 14300
+Wire Wire Line
+ 12650 14350 14000 14350
+Connection ~ 12650 14350
+Connection ~ 12650 16000
+Connection ~ 12650 11600
+Connection ~ 11550 11600
+Connection ~ 6650 11600
+Wire Wire Line
+ 6650 14250 6650 16000
+Connection ~ 6650 16000
+Connection ~ 8350 16000
+Connection ~ 9800 16000
+Connection ~ 11100 16000
+Connection ~ 12750 11600
+Connection ~ 11350 11600
+Connection ~ 8350 11600
+Wire Wire Line
+ 19500 13050 19500 13700
+Wire Wire Line
+ 19200 12850 18750 12850
+Wire Wire Line
+ 18750 12850 18750 13900
+Wire Wire Line
+ 18750 13900 19200 13900
+Wire Wire Line
+ 19500 12650 19500 11400
+Wire Wire Line
+ 19500 11400 30550 11400
+Wire Wire Line
+ 19600 11400 19600 12700
+Wire Wire Line
+ 19500 14100 19500 15800
+Wire Wire Line
+ 18700 15800 25700 15800
+Wire Wire Line
+ 21200 13800 21200 14250
+Wire Wire Line
+ 21200 14650 21200 15800
+Connection ~ 21200 15800
+Wire Wire Line
+ 21300 14600 21300 15800
+Wire Wire Line
+ 20900 13600 20600 13600
+Wire Wire Line
+ 20600 13600 20600 14450
+Wire Wire Line
+ 20600 14450 20900 14450
+Wire Wire Line
+ 20600 14000 20100 14000
+Wire Wire Line
+ 20100 14000 20100 14850
+Wire Wire Line
+ 20100 14850 17850 14850
+Connection ~ 20600 14000
+Wire Wire Line
+ 18750 13300 17700 13300
+Wire Wire Line
+ 17700 13300 17700 13250
+Connection ~ 18750 13300
+Wire Wire Line
+ 21200 13400 21200 11400
+Connection ~ 21200 11400
+Wire Wire Line
+ 21300 11400 21300 13450
+Wire Wire Line
+ 22650 15350 22650 15800
+Connection ~ 22650 15800
+Wire Wire Line
+ 22750 15300 22750 15800
+Wire Wire Line
+ 19500 13350 20150 13350
+Wire Wire Line
+ 20150 13350 20150 12650
+Wire Wire Line
+ 20150 12650 23900 12650
+Connection ~ 19500 13350
+Wire Wire Line
+ 22350 15150 21800 15150
+Wire Wire Line
+ 21800 15150 21800 12650
+Connection ~ 21800 12650
+Wire Wire Line
+ 24200 13250 24200 13600
+Wire Wire Line
+ 23900 12650 23900 13050
+Wire Wire Line
+ 24200 12850 24200 11550
+Wire Wire Line
+ 24200 11550 24100 11550
+Wire Wire Line
+ 24100 11550 24100 11400
+Connection ~ 24100 11400
+Wire Wire Line
+ 24300 11400 24300 12900
+Wire Wire Line
+ 24300 13650 24300 13500
+Wire Wire Line
+ 24300 13500 24500 13500
+Wire Wire Line
+ 24500 13500 24500 11400
+Wire Wire Line
+ 21200 14000 23400 14000
+Wire Wire Line
+ 23400 14000 23400 13800
+Wire Wire Line
+ 23400 13800 23900 13800
+Connection ~ 21200 14000
+Wire Wire Line
+ 23950 15350 23950 15800
+Connection ~ 23950 15800
+Wire Wire Line
+ 24050 15300 24050 15800
+Wire Wire Line
+ 22650 14950 22650 14650
+Wire Wire Line
+ 22650 14650 24200 14650
+Wire Wire Line
+ 24200 14650 24200 14000
+Wire Wire Line
+ 23950 14950 23950 14650
+Connection ~ 23950 14650
+Wire Wire Line
+ 23650 15150 23100 15150
+Wire Wire Line
+ 23100 15150 23100 14000
+Connection ~ 23100 14000
+Wire Wire Line
+ 25600 13950 25600 14350
+Wire Wire Line
+ 25600 11400 25600 13550
+Wire Wire Line
+ 25700 11400 25700 13600
+Wire Wire Line
+ 25600 15800 25600 14750
+Wire Wire Line
+ 25700 15800 25700 14700
+Wire Wire Line
+ 25300 13750 25150 13750
+Wire Wire Line
+ 25150 13750 25150 14550
+Wire Wire Line
+ 25150 14550 25300 14550
+Wire Wire Line
+ 25150 14100 24550 14100
+Wire Wire Line
+ 24550 14100 24550 14250
+Wire Wire Line
+ 24550 14250 24200 14250
+Connection ~ 24200 14250
+Connection ~ 25150 14100
+Wire Wire Line
+ 25600 14150 26950 14150
+Connection ~ 25600 14150
+Connection ~ 25600 15800
+Connection ~ 25600 11400
+Connection ~ 24500 11400
+Connection ~ 19600 11400
+Wire Wire Line
+ 19600 14050 19600 15800
+Connection ~ 19600 15800
+Connection ~ 21300 15800
+Connection ~ 22750 15800
+Connection ~ 24050 15800
+Connection ~ 25700 11400
+Connection ~ 24300 11400
+Connection ~ 21300 11400
+Wire Wire Line
+ 30550 11400 30550 2950
+Wire Wire Line
+ 17150 11600 17150 10550
+Wire Wire Line
+ 17150 10550 30550 10550
+Connection ~ 30550 10550
+Wire Wire Line
+ 14150 4350 14150 2950
+Wire Wire Line
+ 14150 2950 30550 2950
+Connection ~ 30550 4150
+Wire Wire Line
+ 2300 8750 2300 16550
+Connection ~ 6250 8750
+Connection ~ 6550 16000
+Wire Wire Line
+ 15050 8550 15050 10150
+Wire Wire Line
+ 15050 10150 2300 10150
+Connection ~ 2300 10150
+Connection ~ 19200 8550
+Wire Wire Line
+ 18700 15800 18700 16550
+Wire Wire Line
+ 18700 16550 2300 16550
+Connection ~ 2300 16000
+Connection ~ 19500 15800
+Wire Wire Line
+ 2300 12300 1700 12300
+Connection ~ 2300 12300
+Wire Wire Line
+ 30550 7550 31250 7550
+Connection ~ 30550 7550
+$Comp
+L PORT U1
+U 7 1 6855587D
+P 1450 12300
+F 0 "U1" H 1500 12400 30 0000 C CNN
+F 1 "PORT" H 1450 12300 30 0000 C CNN
+F 2 "" H 1450 12300 60 0000 C CNN
+F 3 "" H 1450 12300 60 0000 C CNN
+ 7 1450 12300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 68555CF4
+P 31500 7550
+F 0 "U1" H 31550 7650 30 0000 C CNN
+F 1 "PORT" H 31500 7550 30 0000 C CNN
+F 2 "" H 31500 7550 60 0000 C CNN
+F 3 "" H 31500 7550 60 0000 C CNN
+ 14 31500 7550
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011.sub b/library/SubcircuitLibrary/MMC4011/MMC4011.sub
new file mode 100644
index 000000000..0b4f34efa
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/MMC4011.sub
@@ -0,0 +1,48 @@
+* Subcircuit MMC4011
+.subckt MMC4011 /a /b /j /k /c /d /vss /e /f /l /m /g /h /vdd
+* c:\fossee\esim\library\subcircuitlibrary\mmc4011\mmc4011.cir
+.include PMOS-5um.lib
+.include NMOS-5um.lib
+m2 net-_m1-pad1_ /a /vdd /vdd mos_p W=40u L=5u M=8
+m1 net-_m1-pad1_ /a /vss /vss mos_n W=20u L=5u M=4
+m6 net-_m11-pad2_ /b /vdd /vdd mos_p W=40u L=5u M=8
+m5 net-_m11-pad2_ /b /vss /vss mos_n W=20u L=5u M=4
+m9 net-_m11-pad1_ net-_m1-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m12 net-_m12-pad1_ net-_m1-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m13 net-_m11-pad1_ net-_m11-pad2_ net-_m12-pad1_ /vdd mos_p W=40u L=5u M=8
+m11 net-_m11-pad1_ net-_m11-pad2_ /vss /vss mos_n W=20u L=5u M=4
+m18 /j net-_m11-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m17 /j net-_m11-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m22 net-_m21-pad1_ /c /vdd /vdd mos_p W=40u L=5u M=8
+m21 net-_m21-pad1_ /c /vss /vss mos_n W=20u L=5u M=4
+m26 net-_m25-pad1_ /d /vdd /vdd mos_p W=40u L=5u M=8
+m25 net-_m25-pad1_ /d /vss /vss mos_n W=20u L=5u M=4
+m29 net-_m29-pad1_ net-_m21-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m32 net-_m32-pad1_ net-_m21-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m33 net-_m29-pad1_ net-_m25-pad1_ net-_m32-pad1_ /vdd mos_p W=40u L=5u M=8
+m31 net-_m29-pad1_ net-_m25-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m38 /k net-_m29-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m37 /k net-_m29-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m4 net-_m10-pad2_ /e /vdd /vdd mos_p W=40u L=5u M=8
+m3 net-_m10-pad2_ /e /vss /vss mos_n W=20u L=5u M=4
+m8 net-_m14-pad2_ /f /vdd /vdd mos_p W=40u L=5u M=8
+m7 net-_m14-pad2_ /f /vss /vss mos_n W=20u L=5u M=4
+m10 net-_m10-pad1_ net-_m10-pad2_ /vss /vss mos_n W=20u L=5u M=4
+m15 net-_m15-pad1_ net-_m10-pad2_ /vdd /vdd mos_p W=40u L=5u M=8
+m16 net-_m10-pad1_ net-_m14-pad2_ net-_m15-pad1_ /vdd mos_p W=40u L=5u M=8
+m14 net-_m10-pad1_ net-_m14-pad2_ /vss /vss mos_n W=20u L=5u M=4
+m20 /l net-_m10-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m19 /l net-_m10-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m24 net-_m23-pad1_ /g /vdd /vdd mos_p W=40u L=5u M=8
+m23 net-_m23-pad1_ /g /vss /vss mos_n W=20u L=5u M=4
+m28 net-_m27-pad1_ /h /vdd /vdd mos_p W=40u L=5u M=8
+m27 net-_m27-pad1_ /h /vss /vss mos_n W=20u L=5u M=4
+m30 net-_m30-pad1_ net-_m23-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m35 net-_m35-pad1_ net-_m23-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m36 net-_m30-pad1_ net-_m27-pad1_ net-_m35-pad1_ /vdd mos_p W=40u L=5u M=8
+m34 net-_m30-pad1_ net-_m27-pad1_ /vss /vss mos_n W=20u L=5u M=4
+m40 /m net-_m30-pad1_ /vdd /vdd mos_p W=40u L=5u M=8
+m39 /m net-_m30-pad1_ /vss /vss mos_n W=20u L=5u M=4
+* Control Statements
+
+.ends MMC4011
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MMC4011/MMC4011_Previous_Values.xml b/library/SubcircuitLibrary/MMC4011/MMC4011_Previous_Values.xml
new file mode 100644
index 000000000..c736c70cf
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/MMC4011_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecsecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.lib40u5u8C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.lib20u5u4
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/MMC4011/NMOS-5um.lib b/library/SubcircuitLibrary/MMC4011/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/MMC4011/PMOS-5um.lib b/library/SubcircuitLibrary/MMC4011/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/MMC4011/analysis b/library/SubcircuitLibrary/MMC4011/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/MMC4011/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/2_in_and-cache.lib b/library/SubcircuitLibrary/SN54L98/2_in_and-cache.lib
new file mode 100644
index 000000000..cd4456570
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/2_in_and-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NAND_2
+#
+DEF NAND_2 X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "NAND_2" 50 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+C 350 0 50 0 1 0 N
+P 2 0 1 0 -200 200 150 200 N
+P 3 0 1 0 -200 200 -200 -200 150 -200 N
+X in1 1 -400 50 200 R 50 50 1 1 I
+X Gnd 2 -400 -150 200 R 50 50 1 1 I
+X Vdd 3 -400 150 200 R 50 50 1 1 I
+X out 4 600 0 200 L 50 50 1 1 O
+X in2 5 -400 -50 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/2_in_and.bak b/library/SubcircuitLibrary/SN54L98/2_in_and.bak
new file mode 100644
index 000000000..4c88f6efd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/2_in_and.bak
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NAND_2 X1
+U 1 1 686CC211
+P 5400 3000
+F 0 "X1" H 5500 3000 60 0000 C CNN
+F 1 "NAND_2" H 5450 2750 60 0000 C CNN
+F 2 "" H 5400 3000 60 0001 C CNN
+F 3 "" H 5400 3000 60 0001 C CNN
+ 1 5400 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 686CC23B
+P 6400 3000
+F 0 "X2" H 6400 3000 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6450 2800 60 0000 C CNN
+F 2 "" H 6400 3000 60 0001 C CNN
+F 3 "" H 6400 3000 60 0001 C CNN
+ 1 6400 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 2900 6000 2900
+Wire Wire Line
+ 5000 2900 5000 2850
+Wire Wire Line
+ 4950 3100 6000 3100
+Wire Wire Line
+ 5000 3100 5000 3150
+$Comp
+L PORT U1
+U 1 1 686CC270
+P 4600 2850
+F 0 "U1" H 4650 2950 30 0000 C CNN
+F 1 "PORT" H 4600 2850 30 0000 C CNN
+F 2 "" H 4600 2850 60 0000 C CNN
+F 3 "" H 4600 2850 60 0000 C CNN
+ 1 4600 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686CC2D9
+P 4750 2950
+F 0 "U1" H 4800 3050 30 0000 C CNN
+F 1 "PORT" H 4750 2950 30 0000 C CNN
+F 2 "" H 4750 2950 60 0000 C CNN
+F 3 "" H 4750 2950 60 0000 C CNN
+ 3 4750 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686CC2FC
+P 4750 3050
+F 0 "U1" H 4800 3150 30 0000 C CNN
+F 1 "PORT" H 4750 3050 30 0000 C CNN
+F 2 "" H 4750 3050 60 0000 C CNN
+F 3 "" H 4750 3050 60 0000 C CNN
+ 4 4750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686CC31D
+P 4600 3150
+F 0 "U1" H 4650 3250 30 0000 C CNN
+F 1 "PORT" H 4600 3150 30 0000 C CNN
+F 2 "" H 4600 3150 60 0000 C CNN
+F 3 "" H 4600 3150 60 0000 C CNN
+ 2 4600 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686CC342
+P 7200 3000
+F 0 "U1" H 7250 3100 30 0000 C CNN
+F 1 "PORT" H 7200 3000 30 0000 C CNN
+F 2 "" H 7200 3000 60 0000 C CNN
+F 3 "" H 7200 3000 60 0000 C CNN
+ 5 7200 3000
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4850 2850 4950 2850
+Wire Wire Line
+ 4950 2850 4950 2900
+Connection ~ 5000 2900
+Wire Wire Line
+ 4850 3150 4950 3150
+Wire Wire Line
+ 4950 3150 4950 3100
+Connection ~ 5000 3100
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/2_in_and.cir b/library/SubcircuitLibrary/SN54L98/2_in_and.cir
new file mode 100644
index 000000000..8a30412ec
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/2_in_and.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/2_in_and/2_in_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jul 8 12:32:28 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_X1-Pad4_ Net-_U1-Pad4_ NAND_2
+X2 Net-_X1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad5_ CMOS_INVTR
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/2_in_and.cir.out b/library/SubcircuitLibrary/SN54L98/2_in_and.cir.out
new file mode 100644
index 000000000..b2bc03524
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/2_in_and.cir.out
@@ -0,0 +1,18 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/2_in_and/2_in_and.cir
+
+.include CMOS_INVTR.sub
+.include NAND_2.sub
+
+x1 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_x1-pad4_ net-_u1-pad4_ NAND_2
+x2 net-_x1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad5_ CMOS_INVTR
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/2_in_and.pro b/library/SubcircuitLibrary/SN54L98/2_in_and.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/2_in_and.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L98/2_in_and.sch b/library/SubcircuitLibrary/SN54L98/2_in_and.sch
new file mode 100644
index 000000000..e2a29248f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/2_in_and.sch
@@ -0,0 +1,162 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NAND_2 X1
+U 1 1 686CC211
+P 5400 3000
+F 0 "X1" H 5500 3000 60 0000 C CNN
+F 1 "NAND_2" H 5450 2750 60 0000 C CNN
+F 2 "" H 5400 3000 60 0001 C CNN
+F 3 "" H 5400 3000 60 0001 C CNN
+ 1 5400 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 686CC23B
+P 6400 3000
+F 0 "X2" H 6400 3000 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6450 2800 60 0000 C CNN
+F 2 "" H 6400 3000 60 0001 C CNN
+F 3 "" H 6400 3000 60 0001 C CNN
+ 1 6400 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 2900 6000 2900
+Wire Wire Line
+ 5000 2900 5000 2850
+Wire Wire Line
+ 4950 3100 6000 3100
+Wire Wire Line
+ 5000 3100 5000 3150
+$Comp
+L PORT U1
+U 1 1 686CC270
+P 4600 2850
+F 0 "U1" H 4650 2950 30 0000 C CNN
+F 1 "PORT" H 4600 2850 30 0000 C CNN
+F 2 "" H 4600 2850 60 0000 C CNN
+F 3 "" H 4600 2850 60 0000 C CNN
+ 1 4600 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686CC2D9
+P 4750 2950
+F 0 "U1" H 4800 3050 30 0000 C CNN
+F 1 "PORT" H 4750 2950 30 0000 C CNN
+F 2 "" H 4750 2950 60 0000 C CNN
+F 3 "" H 4750 2950 60 0000 C CNN
+ 3 4750 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686CC2FC
+P 4750 3050
+F 0 "U1" H 4800 3150 30 0000 C CNN
+F 1 "PORT" H 4750 3050 30 0000 C CNN
+F 2 "" H 4750 3050 60 0000 C CNN
+F 3 "" H 4750 3050 60 0000 C CNN
+ 4 4750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686CC31D
+P 4600 3150
+F 0 "U1" H 4650 3250 30 0000 C CNN
+F 1 "PORT" H 4600 3150 30 0000 C CNN
+F 2 "" H 4600 3150 60 0000 C CNN
+F 3 "" H 4600 3150 60 0000 C CNN
+ 2 4600 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686CC342
+P 7200 3000
+F 0 "U1" H 7250 3100 30 0000 C CNN
+F 1 "PORT" H 7200 3000 30 0000 C CNN
+F 2 "" H 7200 3000 60 0000 C CNN
+F 3 "" H 7200 3000 60 0000 C CNN
+ 5 7200 3000
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4850 2850 4950 2850
+Wire Wire Line
+ 4950 2850 4950 2900
+Connection ~ 5000 2900
+Wire Wire Line
+ 4850 3150 4950 3150
+Wire Wire Line
+ 4950 3150 4950 3100
+Connection ~ 5000 3100
+$Comp
+L SKY130mode scmode1
+U 1 1 686CC4AC
+P 8250 3200
+F 0 "scmode1" H 8250 3350 98 0000 C CNB
+F 1 "SKY130mode" H 8250 3100 118 0000 C CNB
+F 2 "" H 8250 3350 60 0001 C CNN
+F 3 "" H 8250 3350 60 0001 C CNN
+ 1 8250 3200
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/2_in_and.sub b/library/SubcircuitLibrary/SN54L98/2_in_and.sub
new file mode 100644
index 000000000..6c2a85281
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/2_in_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 2_in_and
+.subckt 2_in_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/2_in_and/2_in_and.cir
+.include CMOS_INVTR.sub
+.include NAND_2.sub
+
+x1 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_x1-pad4_ net-_u1-pad4_ NAND_2
+x2 net-_x1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad5_ CMOS_INVTR
+* s c m o d e
+* Control Statements
+
+.ends 2_in_and
diff --git a/library/SubcircuitLibrary/SN54L98/2_in_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/2_in_and_Previous_Values.xml
new file mode 100644
index 000000000..ecb007d93
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/2_in_and_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_Buf-cache.lib b/library/SubcircuitLibrary/SN54L98/CMOS_Buf-cache.lib
new file mode 100644
index 000000000..a4da279a5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_Buf-cache.lib
@@ -0,0 +1,74 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_Buf-rescue.lib b/library/SubcircuitLibrary/SN54L98/CMOS_Buf-rescue.lib
new file mode 100644
index 000000000..2e8cabd8d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_Buf-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR-RESCUE-CMOS_Buf
+#
+DEF CMOS_INVTR-RESCUE-CMOS_Buf X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR-RESCUE-CMOS_Buf" 100 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -450 250 500 0 N
+P 3 0 1 0 -450 250 -450 -250 500 0 N
+X IN 1 -650 0 200 R 50 50 1 1 I
+X VDD 2 -650 150 200 R 50 50 1 1 I
+X GND 3 -650 -150 200 R 50 50 1 1 I
+X OUT 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_Buf.bak b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.bak
new file mode 100644
index 000000000..18c8ff97d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.bak
@@ -0,0 +1,149 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CMOS_INVTR X1
+U 1 1 68655F03
+P 4950 3300
+F 0 "X1" H 4950 3300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5050 3050 60 0000 C CNN
+F 2 "" H 4950 3300 60 0001 C CNN
+F 3 "" H 4950 3300 60 0001 C CNN
+ 1 4950 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 68655F1A
+P 6500 3300
+F 0 "X2" H 6500 3300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6600 3050 60 0000 C CNN
+F 2 "" H 6500 3300 60 0001 C CNN
+F 3 "" H 6500 3300 60 0001 C CNN
+ 1 6500 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5750 3300 5850 3300
+Wire Wire Line
+ 4300 3150 4300 3050
+Wire Wire Line
+ 4200 3050 5850 3050
+Wire Wire Line
+ 5850 3050 5850 3150
+Wire Wire Line
+ 4300 3450 4300 3550
+Wire Wire Line
+ 4200 3550 5850 3550
+Wire Wire Line
+ 5850 3550 5850 3450
+$Comp
+L PORT U1
+U 1 1 68655FBD
+P 3950 3050
+F 0 "U1" H 4000 3150 30 0000 C CNN
+F 1 "PORT" H 3950 3050 30 0000 C CNN
+F 2 "" H 3950 3050 60 0000 C CNN
+F 3 "" H 3950 3050 60 0000 C CNN
+ 1 3950 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68655FF0
+P 4050 3300
+F 0 "U1" H 4100 3400 30 0000 C CNN
+F 1 "PORT" H 4050 3300 30 0000 C CNN
+F 2 "" H 4050 3300 60 0000 C CNN
+F 3 "" H 4050 3300 60 0000 C CNN
+ 3 4050 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68656163
+P 3950 3550
+F 0 "U1" H 4000 3650 30 0000 C CNN
+F 1 "PORT" H 3950 3550 30 0000 C CNN
+F 2 "" H 3950 3550 60 0000 C CNN
+F 3 "" H 3950 3550 60 0000 C CNN
+ 2 3950 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68656242
+P 7550 3300
+F 0 "U1" H 7600 3400 30 0000 C CNN
+F 1 "PORT" H 7550 3300 30 0000 C CNN
+F 2 "" H 7550 3300 60 0000 C CNN
+F 3 "" H 7550 3300 60 0000 C CNN
+ 4 7550 3300
+ -1 0 0 -1
+$EndComp
+Connection ~ 4300 3050
+Connection ~ 4300 3550
+$Comp
+L SKY130mode scmode1
+U 1 1 68656379
+P 7900 4200
+F 0 "scmode1" H 7900 4350 98 0000 C CNB
+F 1 "SKY130mode" H 7900 4100 118 0000 C CNB
+F 2 "" H 7900 4350 60 0001 C CNN
+F 3 "" H 7900 4350 60 0001 C CNN
+ 1 7900 4200
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_Buf.cir b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.cir
new file mode 100644
index 000000000..a1907752c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_Buf/CMOS_Buf.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jul 6 10:50:24 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+scmode1 SKY130mode
+X1 Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad4_ CMOS_INVTR
+X2 Net-_X1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ CMOS_INVTR
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_Buf.cir.out b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.cir.out
new file mode 100644
index 000000000..c1aedf115
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.cir.out
@@ -0,0 +1,23 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_buf/cmos_buf.cir
+
+.include CMOS_INVTR.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+* s c m o d e
+x1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_x1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ CMOS_INVTR
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_Buf.pro b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.pro
new file mode 100644
index 000000000..78fa1002c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.pro
@@ -0,0 +1,74 @@
+update=Sun Jul 6 10:49:25 2025
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=CMOS_Buf-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_Buf.sch b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.sch
new file mode 100644
index 000000000..0cdb5a05c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:CMOS_Buf-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CMOS_Buf-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L PORT U1
+U 1 1 68655FBD
+P 3950 3050
+F 0 "U1" H 4000 3150 30 0000 C CNN
+F 1 "PORT" H 3950 3050 30 0000 C CNN
+F 2 "" H 3950 3050 60 0000 C CNN
+F 3 "" H 3950 3050 60 0000 C CNN
+ 1 3950 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68655FF0
+P 4050 3300
+F 0 "U1" H 4100 3400 30 0000 C CNN
+F 1 "PORT" H 4050 3300 30 0000 C CNN
+F 2 "" H 4050 3300 60 0000 C CNN
+F 3 "" H 4050 3300 60 0000 C CNN
+ 3 4050 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68656163
+P 3950 3550
+F 0 "U1" H 4000 3650 30 0000 C CNN
+F 1 "PORT" H 3950 3550 30 0000 C CNN
+F 2 "" H 3950 3550 60 0000 C CNN
+F 3 "" H 3950 3550 60 0000 C CNN
+ 2 3950 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68656242
+P 7050 3300
+F 0 "U1" H 7100 3400 30 0000 C CNN
+F 1 "PORT" H 7050 3300 30 0000 C CNN
+F 2 "" H 7050 3300 60 0000 C CNN
+F 3 "" H 7050 3300 60 0000 C CNN
+ 4 7050 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68656379
+P 7900 4200
+F 0 "scmode1" H 7900 4350 98 0000 C CNB
+F 1 "SKY130mode" H 7900 4100 118 0000 C CNB
+F 2 "" H 7900 4350 60 0001 C CNN
+F 3 "" H 7900 4350 60 0001 C CNN
+ 1 7900 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 686A07F2
+P 4700 3300
+F 0 "X1" H 4700 3300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 4750 3100 60 0000 C CNN
+F 2 "" H 4700 3300 60 0001 C CNN
+F 3 "" H 4700 3300 60 0001 C CNN
+ 1 4700 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 686A0855
+P 6250 3300
+F 0 "X2" H 6250 3300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6300 3100 60 0000 C CNN
+F 2 "" H 6250 3300 60 0001 C CNN
+F 3 "" H 6250 3300 60 0001 C CNN
+ 1 6250 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5250 3300 5850 3300
+Wire Wire Line
+ 4300 3050 4300 3200
+Wire Wire Line
+ 4200 3050 5850 3050
+Wire Wire Line
+ 5850 3050 5850 3200
+Wire Wire Line
+ 4300 3400 4300 3550
+Wire Wire Line
+ 5850 3550 4200 3550
+Wire Wire Line
+ 5850 3400 5850 3550
+Connection ~ 4300 3050
+Connection ~ 4300 3550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_Buf.sub b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.sub
new file mode 100644
index 000000000..8d50195f6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_Buf.sub
@@ -0,0 +1,17 @@
+* Subcircuit CMOS_Buf
+.subckt CMOS_Buf net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_buf/cmos_buf.cir
+.include CMOS_INVTR.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* s c m o d e
+x1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_x1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ CMOS_INVTR
+* Control Statements
+
+.ends CMOS_Buf
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_Buf_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/CMOS_Buf_Previous_Values.xml
new file mode 100644
index 000000000..b0e9c717d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_Buf_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_INVTR-cache.lib b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.cir b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.cir
new file mode 100644
index 000000000..d89b6087d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/CMOS_INVTR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 22:03:21 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.cir.out b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.cir.out
new file mode 100644
index 000000000..4058a1829
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.cir.out
@@ -0,0 +1,22 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.pro b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.sch b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.sch
new file mode 100644
index 000000000..aa7a7ee81
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.sch
@@ -0,0 +1,161 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 684B982F
+P 5350 2950
+F 0 "SC1" H 5400 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 3037 50 0000 R CNN
+F 2 "" H 5350 1450 50 0001 C CNN
+F 3 "" H 5350 2950 50 0001 C CNN
+ 1 5350 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684B9856
+P 5350 3800
+F 0 "SC2" H 5400 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5650 3887 50 0000 R CNN
+F 2 "" H 5350 2300 50 0001 C CNN
+F 3 "" H 5350 3800 50 0001 C CNN
+ 1 5350 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B98AD
+P 4550 3300
+F 0 "U1" H 4600 3400 30 0000 C CNN
+F 1 "PORT" H 4550 3300 30 0000 C CNN
+F 2 "" H 4550 3300 60 0000 C CNN
+F 3 "" H 4550 3300 60 0000 C CNN
+ 1 4550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B98D8
+P 6300 3350
+F 0 "U1" H 6350 3450 30 0000 C CNN
+F 1 "PORT" H 6300 3350 30 0000 C CNN
+F 2 "" H 6300 3350 60 0000 C CNN
+F 3 "" H 6300 3350 60 0000 C CNN
+ 4 6300 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B9935
+P 5300 4350
+F 0 "U1" H 5350 4450 30 0000 C CNN
+F 1 "PORT" H 5300 4350 30 0000 C CNN
+F 2 "" H 5300 4350 60 0000 C CNN
+F 3 "" H 5300 4350 60 0000 C CNN
+ 3 5300 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B999A
+P 5300 2350
+F 0 "U1" H 5350 2450 30 0000 C CNN
+F 1 "PORT" H 5300 2350 30 0000 C CNN
+F 2 "" H 5300 2350 60 0000 C CNN
+F 3 "" H 5300 2350 60 0000 C CNN
+ 2 5300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B99CD
+P 7950 3000
+F 0 "scmode1" H 7950 3150 98 0000 C CNB
+F 1 "SKY130mode" H 7950 2900 118 0000 C CNB
+F 2 "" H 7950 3150 60 0001 C CNN
+F 3 "" H 7950 3150 60 0001 C CNN
+ 1 7950 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 2650 5550 2350
+Wire Wire Line
+ 5450 2950 5600 2950
+Wire Wire Line
+ 5600 2950 5600 2550
+Wire Wire Line
+ 5600 2550 5550 2550
+Connection ~ 5550 2550
+Wire Wire Line
+ 5550 3250 5550 3500
+Wire Wire Line
+ 6050 3350 5550 3350
+Connection ~ 5550 3350
+Wire Wire Line
+ 5050 2950 5050 3800
+Wire Wire Line
+ 4800 3300 5050 3300
+Connection ~ 5050 3300
+Wire Wire Line
+ 5450 3800 5600 3800
+Wire Wire Line
+ 5600 3800 5600 4150
+Wire Wire Line
+ 5600 4150 5550 4150
+Wire Wire Line
+ 5550 4100 5550 4350
+Connection ~ 5550 4150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.sub b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.sub
new file mode 100644
index 000000000..9dff1ae3f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR.sub
@@ -0,0 +1,16 @@
+* Subcircuit CMOS_INVTR
+.subckt CMOS_INVTR net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends CMOS_INVTR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/CMOS_INVTR_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR_Previous_Values.xml
new file mode 100644
index 000000000..0fa71b2d4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/CMOS_INVTR_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/DS_blk-cache.lib b/library/SubcircuitLibrary/SN54L98/DS_blk-cache.lib
new file mode 100644
index 000000000..f32a82db2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/DS_blk-cache.lib
@@ -0,0 +1,147 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 2_in_and
+#
+DEF 2_in_and X 0 40 Y Y 1 F N
+F0 "X" 50 0 60 H V C CNN
+F1 "2_in_and" 0 -250 60 H V C CNN
+F2 "" 750 -150 60 H I C CNN
+F3 "" 750 -150 60 H I C CNN
+DRAW
+A 50 0 206 760 -760 0 1 0 N 100 200 100 -200
+P 2 0 1 0 -200 200 100 200 N
+P 3 0 1 0 -200 200 -200 -200 100 -200 N
+X Vdd 1 -400 150 200 R 50 50 1 1 I
+X in1 2 -400 50 200 R 50 50 1 1 I
+X in2 3 -400 -50 200 R 50 50 1 1 I
+X Gnd 4 -400 -150 200 R 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_Buf
+#
+DEF CMOS_Buf X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_Buf" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+P 2 0 1 0 -250 150 250 0 N
+P 3 0 1 0 -250 150 -250 -150 250 0 N
+X Vdd 1 -450 100 200 R 50 50 1 1 I
+X Gnd 2 -450 -100 200 R 50 50 1 1 I
+X in 3 -450 0 200 R 50 50 1 1 I
+X Out 4 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# D_FF
+#
+DEF D_FF X 0 40 Y Y 1 F N
+F0 "X" 100 100 60 H V C CNN
+F1 "D_FF" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -200 200 200 -150 0 1 0 N
+X D 1 -400 50 200 R 50 50 1 1 I
+X Clk 2 -400 -50 200 R 50 50 1 1 I
+X Vdd 3 0 400 200 D 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X Q 5 400 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NOR_2
+#
+DEF NOR_2 X 0 40 Y Y 1 F N
+F0 "X" 50 0 60 H V C CNN
+F1 "NOR_2" 0 -250 60 H V C CNN
+F2 "" -100 0 60 H I C CNN
+F3 "" -100 0 60 H I C CNN
+DRAW
+A -350 0 206 760 -760 0 1 0 N -300 200 -300 -200
+A -226 239 445 -996 -324 0 1 0 N -300 -200 150 0
+A -197 -174 388 1054 266 0 1 0 N -300 200 150 0
+C 200 0 50 0 1 0 N
+X in1 1 -350 50 200 R 50 50 1 1 I
+X Gnd 2 -400 -150 200 R 50 50 1 1 I
+X Vdd 3 -400 150 200 R 50 50 1 1 I
+X in2 4 -350 -50 200 R 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/DS_blk.bak b/library/SubcircuitLibrary/SN54L98/DS_blk.bak
new file mode 100644
index 000000000..367ca003a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/DS_blk.bak
@@ -0,0 +1,280 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DS_blk-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 2_in_and X1
+U 1 1 686E8DA4
+P 4450 2650
+F 0 "X1" H 4500 2650 60 0000 C CNN
+F 1 "2_in_and" H 4450 2400 60 0000 C CNN
+F 2 "" H 5200 2500 60 0001 C CNN
+F 3 "" H 5200 2500 60 0001 C CNN
+ 1 4450 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L 2_in_and X2
+U 1 1 686E8DC5
+P 4450 3500
+F 0 "X2" H 4500 3500 60 0000 C CNN
+F 1 "2_in_and" H 4450 3250 60 0000 C CNN
+F 2 "" H 5200 3350 60 0001 C CNN
+F 3 "" H 5200 3350 60 0001 C CNN
+ 1 4450 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_2 X3
+U 1 1 686E8DDE
+P 5750 3050
+F 0 "X3" H 5800 3050 60 0000 C CNN
+F 1 "NOR_2" H 5750 2800 60 0000 C CNN
+F 2 "" H 5650 3050 60 0001 C CNN
+F 3 "" H 5650 3050 60 0001 C CNN
+ 1 5750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X4
+U 1 1 686E8E0C
+P 7050 3100
+F 0 "X4" H 7150 3200 60 0000 C CNN
+F 1 "D_FF" H 7050 2900 60 0000 C CNN
+F 2 "" H 7050 3100 60 0001 C CNN
+F 3 "" H 7050 3100 60 0001 C CNN
+ 1 7050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686E8E39
+P 8550 4100
+F 0 "scmode1" H 8550 4250 98 0000 C CNB
+F 1 "SKY130mode" H 8550 4000 118 0000 C CNB
+F 2 "" H 8550 4250 60 0001 C CNN
+F 3 "" H 8550 4250 60 0001 C CNN
+ 1 8550 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E8E58
+P 3800 2600
+F 0 "U1" H 3850 2700 30 0000 C CNN
+F 1 "PORT" H 3800 2600 30 0000 C CNN
+F 2 "" H 3800 2600 60 0000 C CNN
+F 3 "" H 3800 2600 60 0000 C CNN
+ 1 3800 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E8F0F
+P 3800 2700
+F 0 "U1" H 3850 2800 30 0000 C CNN
+F 1 "PORT" H 3800 2700 30 0000 C CNN
+F 2 "" H 3800 2700 60 0000 C CNN
+F 3 "" H 3800 2700 60 0000 C CNN
+ 2 3800 2700
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E8F53
+P 3800 3450
+F 0 "U1" H 3850 3550 30 0000 C CNN
+F 1 "PORT" H 3800 3450 30 0000 C CNN
+F 2 "" H 3800 3450 60 0000 C CNN
+F 3 "" H 3800 3450 60 0000 C CNN
+ 3 3800 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E8F80
+P 3800 3550
+F 0 "U1" H 3850 3650 30 0000 C CNN
+F 1 "PORT" H 3800 3550 30 0000 C CNN
+F 2 "" H 3800 3550 60 0000 C CNN
+F 3 "" H 3800 3550 60 0000 C CNN
+ 4 3800 3550
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E901D
+P 6400 3150
+F 0 "U1" H 6450 3250 30 0000 C CNN
+F 1 "PORT" H 6400 3150 30 0000 C CNN
+F 2 "" H 6400 3150 60 0000 C CNN
+F 3 "" H 6400 3150 60 0000 C CNN
+ 5 6400 3150
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686E9099
+P 7700 3150
+F 0 "U1" H 7750 3250 30 0000 C CNN
+F 1 "PORT" H 7700 3150 30 0000 C CNN
+F 2 "" H 7700 3150 60 0000 C CNN
+F 3 "" H 7700 3150 60 0000 C CNN
+ 8 7700 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686E91B5
+P 7300 2400
+F 0 "U1" H 7350 2500 30 0000 C CNN
+F 1 "PORT" H 7300 2400 30 0000 C CNN
+F 2 "" H 7300 2400 60 0000 C CNN
+F 3 "" H 7300 2400 60 0000 C CNN
+ 6 7300 2400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686E922A
+P 7300 3550
+F 0 "U1" H 7350 3650 30 0000 C CNN
+F 1 "PORT" H 7300 3550 30 0000 C CNN
+F 2 "" H 7300 3550 60 0000 C CNN
+F 3 "" H 7300 3550 60 0000 C CNN
+ 7 7300 3550
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4900 2650 4900 3000
+Wire Wire Line
+ 4900 3000 5400 3000
+Wire Wire Line
+ 4900 3500 4900 3100
+Wire Wire Line
+ 4900 3100 5400 3100
+Wire Wire Line
+ 4050 2400 4050 2500
+Wire Wire Line
+ 4050 2400 7050 2400
+Wire Wire Line
+ 7050 2400 7050 2700
+Connection ~ 7050 2400
+Connection ~ 7050 3550
+Wire Wire Line
+ 4050 3650 4050 3800
+Wire Wire Line
+ 4050 3800 7050 3800
+Wire Wire Line
+ 7050 3800 7050 3450
+Wire Wire Line
+ 5350 2900 5350 2400
+Connection ~ 5350 2400
+Wire Wire Line
+ 5350 3200 5350 3800
+Connection ~ 5350 3800
+Wire Wire Line
+ 4050 3350 4050 3200
+Wire Wire Line
+ 4050 3200 5150 3200
+Wire Wire Line
+ 5150 3200 5150 2400
+Connection ~ 5150 2400
+Wire Wire Line
+ 4050 2800 4050 2950
+Wire Wire Line
+ 4050 2950 5200 2950
+Wire Wire Line
+ 5200 2950 5200 3800
+Connection ~ 5200 3800
+$Comp
+L CMOS_Buf X5
+U 1 1 686F47C1
+P 6350 2650
+F 0 "X5" H 6350 2650 60 0000 C CNN
+F 1 "CMOS_Buf" H 6350 2450 60 0000 C CNN
+F 2 "" H 6350 2650 60 0001 C CNN
+F 3 "" H 6350 2650 60 0001 C CNN
+ 1 6350 2650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6200 3050 6200 2900
+Wire Wire Line
+ 6200 2900 5800 2900
+Wire Wire Line
+ 5800 2900 5800 2650
+Wire Wire Line
+ 5800 2650 5900 2650
+Wire Wire Line
+ 6800 2650 6850 2650
+Wire Wire Line
+ 6850 2650 6850 2850
+Wire Wire Line
+ 6850 2850 6650 2850
+Wire Wire Line
+ 6650 2850 6650 3050
+Wire Wire Line
+ 5900 2550 5900 2400
+Connection ~ 5900 2400
+Wire Wire Line
+ 5900 2750 5900 2800
+Wire Wire Line
+ 5900 2800 6300 2800
+Wire Wire Line
+ 6300 2800 6300 3550
+Wire Wire Line
+ 6300 3550 7050 3550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/DS_blk.cir b/library/SubcircuitLibrary/SN54L98/DS_blk.cir
new file mode 100644
index 000000000..a033859ed
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/DS_blk.cir
@@ -0,0 +1,18 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/DS_blk/DS_blk.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jul 10 11:45:04 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad6_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad7_ Net-_X1-Pad5_ 2_in_and
+X2 Net-_U1-Pad6_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad7_ Net-_X2-Pad5_ 2_in_and
+X3 Net-_X1-Pad5_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_X2-Pad5_ Net-_X3-Pad5_ NOR_2
+X4 Net-_X3-Pad5_ Net-_X4-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ D_FF
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT
+X5 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_X5-Pad4_ CMOS_Buf
+X6 Net-_X5-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_X4-Pad2_ CMOS_INVTR
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/DS_blk.cir.out b/library/SubcircuitLibrary/SN54L98/DS_blk.cir.out
new file mode 100644
index 000000000..9cbba8aaf
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/DS_blk.cir.out
@@ -0,0 +1,31 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/ds_blk/ds_blk.cir
+
+.include D_FF.sub
+.include 2_in_and.sub
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+.include CMOS_Buf.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+x1 net-_u1-pad6_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad7_ net-_x1-pad5_ 2_in_and
+x2 net-_u1-pad6_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad7_ net-_x2-pad5_ 2_in_and
+x3 net-_x1-pad5_ net-_u1-pad7_ net-_u1-pad6_ net-_x2-pad5_ net-_x3-pad5_ NOR_2
+x4 net-_x3-pad5_ net-_x4-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ D_FF
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
+x5 net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x5-pad4_ CMOS_Buf
+x6 net-_x5-pad4_ net-_u1-pad6_ net-_u1-pad7_ net-_x4-pad2_ CMOS_INVTR
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/DS_blk.pro b/library/SubcircuitLibrary/SN54L98/DS_blk.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/DS_blk.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L98/DS_blk.sch b/library/SubcircuitLibrary/SN54L98/DS_blk.sch
new file mode 100644
index 000000000..b08a03928
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/DS_blk.sch
@@ -0,0 +1,293 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DS_blk-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 2_in_and X1
+U 1 1 686E8DA4
+P 4450 2650
+F 0 "X1" H 4500 2650 60 0000 C CNN
+F 1 "2_in_and" H 4450 2400 60 0000 C CNN
+F 2 "" H 5200 2500 60 0001 C CNN
+F 3 "" H 5200 2500 60 0001 C CNN
+ 1 4450 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L 2_in_and X2
+U 1 1 686E8DC5
+P 4450 3500
+F 0 "X2" H 4500 3500 60 0000 C CNN
+F 1 "2_in_and" H 4450 3250 60 0000 C CNN
+F 2 "" H 5200 3350 60 0001 C CNN
+F 3 "" H 5200 3350 60 0001 C CNN
+ 1 4450 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_2 X3
+U 1 1 686E8DDE
+P 5750 3050
+F 0 "X3" H 5800 3050 60 0000 C CNN
+F 1 "NOR_2" H 5750 2800 60 0000 C CNN
+F 2 "" H 5650 3050 60 0001 C CNN
+F 3 "" H 5650 3050 60 0001 C CNN
+ 1 5750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X4
+U 1 1 686E8E0C
+P 7050 3100
+F 0 "X4" H 7150 3200 60 0000 C CNN
+F 1 "D_FF" H 7050 2900 60 0000 C CNN
+F 2 "" H 7050 3100 60 0001 C CNN
+F 3 "" H 7050 3100 60 0001 C CNN
+ 1 7050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686E8E39
+P 8550 4100
+F 0 "scmode1" H 8550 4250 98 0000 C CNB
+F 1 "SKY130mode" H 8550 4000 118 0000 C CNB
+F 2 "" H 8550 4250 60 0001 C CNN
+F 3 "" H 8550 4250 60 0001 C CNN
+ 1 8550 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E8E58
+P 3800 2600
+F 0 "U1" H 3850 2700 30 0000 C CNN
+F 1 "PORT" H 3800 2600 30 0000 C CNN
+F 2 "" H 3800 2600 60 0000 C CNN
+F 3 "" H 3800 2600 60 0000 C CNN
+ 1 3800 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E8F0F
+P 3800 2700
+F 0 "U1" H 3850 2800 30 0000 C CNN
+F 1 "PORT" H 3800 2700 30 0000 C CNN
+F 2 "" H 3800 2700 60 0000 C CNN
+F 3 "" H 3800 2700 60 0000 C CNN
+ 2 3800 2700
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E8F53
+P 3800 3450
+F 0 "U1" H 3850 3550 30 0000 C CNN
+F 1 "PORT" H 3800 3450 30 0000 C CNN
+F 2 "" H 3800 3450 60 0000 C CNN
+F 3 "" H 3800 3450 60 0000 C CNN
+ 3 3800 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E8F80
+P 3800 3550
+F 0 "U1" H 3850 3650 30 0000 C CNN
+F 1 "PORT" H 3800 3550 30 0000 C CNN
+F 2 "" H 3800 3550 60 0000 C CNN
+F 3 "" H 3800 3550 60 0000 C CNN
+ 4 3800 3550
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E901D
+P 5200 4200
+F 0 "U1" H 5250 4300 30 0000 C CNN
+F 1 "PORT" H 5200 4200 30 0000 C CNN
+F 2 "" H 5200 4200 60 0000 C CNN
+F 3 "" H 5200 4200 60 0000 C CNN
+ 5 5200 4200
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686E9099
+P 7700 3150
+F 0 "U1" H 7750 3250 30 0000 C CNN
+F 1 "PORT" H 7700 3150 30 0000 C CNN
+F 2 "" H 7700 3150 60 0000 C CNN
+F 3 "" H 7700 3150 60 0000 C CNN
+ 8 7700 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686E91B5
+P 7300 2400
+F 0 "U1" H 7350 2500 30 0000 C CNN
+F 1 "PORT" H 7300 2400 30 0000 C CNN
+F 2 "" H 7300 2400 60 0000 C CNN
+F 3 "" H 7300 2400 60 0000 C CNN
+ 6 7300 2400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686E922A
+P 7300 3550
+F 0 "U1" H 7350 3650 30 0000 C CNN
+F 1 "PORT" H 7300 3550 30 0000 C CNN
+F 2 "" H 7300 3550 60 0000 C CNN
+F 3 "" H 7300 3550 60 0000 C CNN
+ 7 7300 3550
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4900 2650 4900 3000
+Wire Wire Line
+ 4900 3000 5400 3000
+Wire Wire Line
+ 4900 3500 4900 3100
+Wire Wire Line
+ 4900 3100 5400 3100
+Wire Wire Line
+ 4050 2400 4050 2500
+Wire Wire Line
+ 4050 2400 7050 2400
+Wire Wire Line
+ 7050 2400 7050 2700
+Connection ~ 7050 2400
+Connection ~ 7050 3550
+Wire Wire Line
+ 4050 3650 4050 3800
+Wire Wire Line
+ 4050 3800 7050 3800
+Wire Wire Line
+ 7050 3800 7050 3450
+Wire Wire Line
+ 5350 2900 5350 2400
+Connection ~ 5350 2400
+Wire Wire Line
+ 5350 3200 5350 3800
+Connection ~ 5350 3800
+Wire Wire Line
+ 4050 3350 4050 3200
+Wire Wire Line
+ 4050 3200 5150 3200
+Wire Wire Line
+ 5150 3200 5150 2400
+Connection ~ 5150 2400
+Wire Wire Line
+ 4050 2800 4050 2950
+Wire Wire Line
+ 4050 2950 5200 2950
+Wire Wire Line
+ 5200 2950 5200 3800
+Connection ~ 5200 3800
+Wire Wire Line
+ 6200 3050 6650 3050
+$Comp
+L CMOS_Buf X5
+U 1 1 686F5D94
+P 5900 4200
+F 0 "X5" H 5900 4200 60 0000 C CNN
+F 1 "CMOS_Buf" H 5900 4000 60 0000 C CNN
+F 2 "" H 5900 4200 60 0001 C CNN
+F 3 "" H 5900 4200 60 0001 C CNN
+ 1 5900 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X6
+U 1 1 686F5DD5
+P 6750 4200
+F 0 "X6" H 6750 4200 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6800 4000 60 0000 C CNN
+F 2 "" H 6750 4200 60 0001 C CNN
+F 3 "" H 6750 4200 60 0001 C CNN
+ 1 6750 4200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7300 4200 7300 3850
+Wire Wire Line
+ 7300 3850 6650 3850
+Wire Wire Line
+ 6650 3850 6650 3150
+Wire Wire Line
+ 5450 4100 5450 4000
+Wire Wire Line
+ 5450 4000 6350 4000
+Wire Wire Line
+ 6350 2400 6350 4100
+Connection ~ 6350 2400
+Connection ~ 6350 4000
+Wire Wire Line
+ 6350 4300 6350 4400
+Wire Wire Line
+ 5450 4400 7550 4400
+Wire Wire Line
+ 7550 4400 7550 3750
+Wire Wire Line
+ 7550 3750 7050 3750
+Wire Wire Line
+ 7050 3750 7050 3550
+Wire Wire Line
+ 5450 4300 5450 4400
+Connection ~ 6350 4400
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/DS_blk.sub b/library/SubcircuitLibrary/SN54L98/DS_blk.sub
new file mode 100644
index 000000000..6fe4576b5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/DS_blk.sub
@@ -0,0 +1,25 @@
+* Subcircuit DS_blk
+.subckt DS_blk net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/ds_blk/ds_blk.cir
+.include D_FF.sub
+.include 2_in_and.sub
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+.include CMOS_Buf.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+x1 net-_u1-pad6_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad7_ net-_x1-pad5_ 2_in_and
+x2 net-_u1-pad6_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad7_ net-_x2-pad5_ 2_in_and
+x3 net-_x1-pad5_ net-_u1-pad7_ net-_u1-pad6_ net-_x2-pad5_ net-_x3-pad5_ NOR_2
+x4 net-_x3-pad5_ net-_x4-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ D_FF
+* s c m o d e
+x5 net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x5-pad4_ CMOS_Buf
+x6 net-_x5-pad4_ net-_u1-pad6_ net-_u1-pad7_ net-_x4-pad2_ CMOS_INVTR
+* Control Statements
+
+.ends DS_blk
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/DS_blk_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/DS_blk_Previous_Values.xml
new file mode 100644
index 000000000..d06329f5a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/DS_blk_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/2_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/2_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_FF/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_Buf/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/D_FF-cache.lib b/library/SubcircuitLibrary/SN54L98/D_FF-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/D_FF-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/D_FF.bak b/library/SubcircuitLibrary/SN54L98/D_FF.bak
new file mode 100644
index 000000000..61b02ff48
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/D_FF.bak
@@ -0,0 +1,246 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode?
+U 1 1 685A3E76
+P 9400 3200
+F 0 "scmode?" H 9400 3350 98 0000 C CNB
+F 1 "SKY130mode" H 9400 3100 118 0000 C CNB
+F 2 "" H 9400 3350 60 0001 C CNN
+F 3 "" H 9400 3350 60 0001 C CNN
+ 1 9400 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC?
+U 1 1 685A3EBD
+P 4000 3300
+F 0 "SC?" H 4050 3600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 3387 50 0000 R CNN
+F 2 "" H 4000 1800 50 0001 C CNN
+F 3 "" H 4000 3300 50 0001 C CNN
+ 1 4000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3EFC
+P 4000 4100
+F 0 "SC?" H 4050 4400 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4187 50 0000 R CNN
+F 2 "" H 4000 2600 50 0001 C CNN
+F 3 "" H 4000 4100 50 0001 C CNN
+ 1 4000 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3F47
+P 4000 4900
+F 0 "SC?" H 4050 5200 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4987 50 0000 R CNN
+F 2 "" H 4000 3400 50 0001 C CNN
+F 3 "" H 4000 4900 50 0001 C CNN
+ 1 4000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC?
+U 1 1 685A3F7A
+P 4950 3700
+F 0 "SC?" H 5000 4000 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5250 3787 50 0000 R CNN
+F 2 "" H 4950 2200 50 0001 C CNN
+F 3 "" H 4950 3700 50 0001 C CNN
+ 1 4950 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3FCF
+P 4950 4500
+F 0 "SC?" H 5000 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5250 4587 50 0000 R CNN
+F 2 "" H 4950 3000 50 0001 C CNN
+F 3 "" H 4950 4500 50 0001 C CNN
+ 1 4950 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 1 1 685A401A
+P 3250 3550
+F 0 "U?" H 3300 3650 30 0000 C CNN
+F 1 "PORT" H 3250 3550 30 0000 C CNN
+F 2 "" H 3250 3550 60 0000 C CNN
+F 3 "" H 3250 3550 60 0000 C CNN
+ 1 3250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 2 1 685A40FF
+P 3250 4100
+F 0 "U?" H 3300 4200 30 0000 C CNN
+F 1 "PORT" H 3250 4100 30 0000 C CNN
+F 2 "" H 3250 4100 60 0000 C CNN
+F 3 "" H 3250 4100 60 0000 C CNN
+ 2 3250 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 3 1 685A4132
+P 3950 2750
+F 0 "U?" H 4000 2850 30 0000 C CNN
+F 1 "PORT" H 3950 2750 30 0000 C CNN
+F 2 "" H 3950 2750 60 0000 C CNN
+F 3 "" H 3950 2750 60 0000 C CNN
+ 3 3950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 4 1 685A41B1
+P 3950 5350
+F 0 "U?" H 4000 5450 30 0000 C CNN
+F 1 "PORT" H 3950 5350 30 0000 C CNN
+F 2 "" H 3950 5350 60 0000 C CNN
+F 3 "" H 3950 5350 60 0000 C CNN
+ 4 3950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 5 1 685A4206
+P 5700 4100
+F 0 "U?" H 5750 4200 30 0000 C CNN
+F 1 "PORT" H 5700 4100 30 0000 C CNN
+F 2 "" H 5700 4100 60 0000 C CNN
+F 3 "" H 5700 4100 60 0000 C CNN
+ 5 5700 4100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4200 3600 4200 3800
+Wire Wire Line
+ 3700 3300 3600 3300
+Wire Wire Line
+ 3600 3300 3600 4900
+Wire Wire Line
+ 3600 4900 3700 4900
+Wire Wire Line
+ 3500 3550 3600 3550
+Connection ~ 3600 3550
+Wire Wire Line
+ 3500 4100 3700 4100
+Wire Wire Line
+ 4200 2750 4200 3000
+Wire Wire Line
+ 4650 3700 4200 3700
+Connection ~ 4200 3700
+Wire Wire Line
+ 4200 4400 4200 4600
+Wire Wire Line
+ 4650 4500 4200 4500
+Connection ~ 4200 4500
+Wire Wire Line
+ 5150 4000 5150 4200
+Wire Wire Line
+ 5450 4100 5150 4100
+Connection ~ 5150 4100
+Wire Wire Line
+ 4200 5200 4200 5350
+Wire Wire Line
+ 4100 4900 4250 4900
+Wire Wire Line
+ 4250 4900 4250 5250
+Wire Wire Line
+ 4200 5250 5150 5250
+Connection ~ 4200 5250
+Wire Wire Line
+ 5150 5250 5150 4800
+Connection ~ 4250 5250
+Wire Wire Line
+ 5050 4500 5200 4500
+Wire Wire Line
+ 5200 4500 5200 4850
+Wire Wire Line
+ 5200 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 4100 4100 4250 4100
+Wire Wire Line
+ 4250 4100 4250 4500
+Connection ~ 4250 4500
+Wire Wire Line
+ 4100 3300 4250 3300
+Wire Wire Line
+ 4250 3300 4250 2950
+Wire Wire Line
+ 4200 2950 5150 2950
+Connection ~ 4200 2950
+Wire Wire Line
+ 5150 2950 5150 3400
+Connection ~ 4250 2950
+Wire Wire Line
+ 5050 3700 5200 3700
+Wire Wire Line
+ 5200 3700 5200 3350
+Wire Wire Line
+ 5200 3350 5150 3350
+Connection ~ 5150 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/D_FF.cir b/library/SubcircuitLibrary/SN54L98/D_FF.cir
new file mode 100644
index 000000000..7d45c3cd5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/D_FF.cir
@@ -0,0 +1,17 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_FF/D_FF.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jul 6 10:25:49 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+scmode1 SKY130mode
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+SC3 Net-_SC2-Pad3_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC4-Pad1_ Net-_SC1-Pad1_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC5 Net-_SC4-Pad1_ Net-_SC2-Pad3_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC3-Pad3_ Net-_SC4-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/D_FF.cir.out b/library/SubcircuitLibrary/SN54L98/D_FF.cir.out
new file mode 100644
index 000000000..9d076c7f0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/D_FF.cir.out
@@ -0,0 +1,25 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/d_ff/d_ff.cir
+
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+* s c m o d e
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc2-pad3_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc4-pad1_ net-_sc2-pad3_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc4-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/D_FF.pro b/library/SubcircuitLibrary/SN54L98/D_FF.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/D_FF.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L98/D_FF.sch b/library/SubcircuitLibrary/SN54L98/D_FF.sch
new file mode 100644
index 000000000..722069493
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/D_FF.sch
@@ -0,0 +1,246 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 685A3E76
+P 9400 3200
+F 0 "scmode1" H 9400 3350 98 0000 C CNB
+F 1 "SKY130mode" H 9400 3100 118 0000 C CNB
+F 2 "" H 9400 3350 60 0001 C CNN
+F 3 "" H 9400 3350 60 0001 C CNN
+ 1 9400 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 685A3EBD
+P 4000 3300
+F 0 "SC1" H 4050 3600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 3387 50 0000 R CNN
+F 2 "" H 4000 1800 50 0001 C CNN
+F 3 "" H 4000 3300 50 0001 C CNN
+ 1 4000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 685A3EFC
+P 4000 4100
+F 0 "SC2" H 4050 4400 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4187 50 0000 R CNN
+F 2 "" H 4000 2600 50 0001 C CNN
+F 3 "" H 4000 4100 50 0001 C CNN
+ 1 4000 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 685A3F47
+P 4000 4900
+F 0 "SC3" H 4050 5200 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4987 50 0000 R CNN
+F 2 "" H 4000 3400 50 0001 C CNN
+F 3 "" H 4000 4900 50 0001 C CNN
+ 1 4000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 685A3F7A
+P 4950 3700
+F 0 "SC4" H 5000 4000 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5250 3787 50 0000 R CNN
+F 2 "" H 4950 2200 50 0001 C CNN
+F 3 "" H 4950 3700 50 0001 C CNN
+ 1 4950 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 685A3FCF
+P 4950 4500
+F 0 "SC5" H 5000 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5250 4587 50 0000 R CNN
+F 2 "" H 4950 3000 50 0001 C CNN
+F 3 "" H 4950 4500 50 0001 C CNN
+ 1 4950 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A401A
+P 3250 3550
+F 0 "U1" H 3300 3650 30 0000 C CNN
+F 1 "PORT" H 3250 3550 30 0000 C CNN
+F 2 "" H 3250 3550 60 0000 C CNN
+F 3 "" H 3250 3550 60 0000 C CNN
+ 1 3250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685A40FF
+P 3250 4100
+F 0 "U1" H 3300 4200 30 0000 C CNN
+F 1 "PORT" H 3250 4100 30 0000 C CNN
+F 2 "" H 3250 4100 60 0000 C CNN
+F 3 "" H 3250 4100 60 0000 C CNN
+ 2 3250 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685A4132
+P 3950 2750
+F 0 "U1" H 4000 2850 30 0000 C CNN
+F 1 "PORT" H 3950 2750 30 0000 C CNN
+F 2 "" H 3950 2750 60 0000 C CNN
+F 3 "" H 3950 2750 60 0000 C CNN
+ 3 3950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A41B1
+P 3950 5350
+F 0 "U1" H 4000 5450 30 0000 C CNN
+F 1 "PORT" H 3950 5350 30 0000 C CNN
+F 2 "" H 3950 5350 60 0000 C CNN
+F 3 "" H 3950 5350 60 0000 C CNN
+ 4 3950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685A4206
+P 5700 4100
+F 0 "U1" H 5750 4200 30 0000 C CNN
+F 1 "PORT" H 5700 4100 30 0000 C CNN
+F 2 "" H 5700 4100 60 0000 C CNN
+F 3 "" H 5700 4100 60 0000 C CNN
+ 5 5700 4100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4200 3600 4200 3800
+Wire Wire Line
+ 3700 3300 3600 3300
+Wire Wire Line
+ 3600 3300 3600 4900
+Wire Wire Line
+ 3600 4900 3700 4900
+Wire Wire Line
+ 3500 3550 3600 3550
+Connection ~ 3600 3550
+Wire Wire Line
+ 3500 4100 3700 4100
+Wire Wire Line
+ 4200 2750 4200 3000
+Wire Wire Line
+ 4650 3700 4200 3700
+Connection ~ 4200 3700
+Wire Wire Line
+ 4200 4400 4200 4600
+Wire Wire Line
+ 4650 4500 4200 4500
+Connection ~ 4200 4500
+Wire Wire Line
+ 5150 4000 5150 4200
+Wire Wire Line
+ 5450 4100 5150 4100
+Connection ~ 5150 4100
+Wire Wire Line
+ 4200 5200 4200 5350
+Wire Wire Line
+ 4100 4900 4250 4900
+Wire Wire Line
+ 4250 4900 4250 5250
+Wire Wire Line
+ 4200 5250 5150 5250
+Connection ~ 4200 5250
+Wire Wire Line
+ 5150 5250 5150 4800
+Connection ~ 4250 5250
+Wire Wire Line
+ 5050 4500 5200 4500
+Wire Wire Line
+ 5200 4500 5200 4850
+Wire Wire Line
+ 5200 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 4100 4100 4250 4100
+Wire Wire Line
+ 4250 4100 4250 4500
+Connection ~ 4250 4500
+Wire Wire Line
+ 4100 3300 4250 3300
+Wire Wire Line
+ 4250 3300 4250 2950
+Wire Wire Line
+ 4200 2950 5150 2950
+Connection ~ 4200 2950
+Wire Wire Line
+ 5150 2950 5150 3400
+Connection ~ 4250 2950
+Wire Wire Line
+ 5050 3700 5200 3700
+Wire Wire Line
+ 5200 3700 5200 3350
+Wire Wire Line
+ 5200 3350 5150 3350
+Connection ~ 5150 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/D_FF.sub b/library/SubcircuitLibrary/SN54L98/D_FF.sub
new file mode 100644
index 000000000..d686ca626
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/D_FF.sub
@@ -0,0 +1,19 @@
+* Subcircuit D_FF
+.subckt D_FF net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc4-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/d_ff/d_ff.cir
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+* s c m o d e
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc2-pad3_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc4-pad1_ net-_sc2-pad3_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends D_FF
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/D_FF_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/D_FF_Previous_Values.xml
new file mode 100644
index 000000000..87f2534ab
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/D_FF_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/NAND_2-cache.lib b/library/SubcircuitLibrary/SN54L98/NAND_2-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NAND_2-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/NAND_2.bak b/library/SubcircuitLibrary/SN54L98/NAND_2.bak
new file mode 100644
index 000000000..ad9819396
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NAND_2.bak
@@ -0,0 +1,221 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684AF0E9
+P 4750 2050
+F 0 "SC2" H 4800 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5050 2137 50 0000 R CNN
+F 2 "" H 4750 550 50 0001 C CNN
+F 3 "" H 4750 2050 50 0001 C CNN
+ 1 4750 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF14C
+P 5150 2750
+F 0 "SC3" H 5200 3050 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 2837 50 0000 R CNN
+F 2 "" H 5150 1250 50 0001 C CNN
+F 3 "" H 5150 2750 50 0001 C CNN
+ 1 5150 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF1CF
+P 4200 3600
+F 0 "SC1" H 4250 3900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4500 3687 50 0000 R CNN
+F 2 "" H 4200 2100 50 0001 C CNN
+F 3 "" H 4200 3600 50 0001 C CNN
+ 1 4200 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684AF20C
+P 5550 3600
+F 0 "SC4" H 5600 3900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5850 3687 50 0000 R CNN
+F 2 "" H 5550 2100 50 0001 C CNN
+F 3 "" H 5550 3600 50 0001 C CNN
+ 1 5550 3600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF271
+P 4650 1550
+F 0 "U1" H 4700 1650 30 0000 C CNN
+F 1 "PORT" H 4650 1550 30 0000 C CNN
+F 2 "" H 4650 1550 60 0000 C CNN
+F 3 "" H 4650 1550 60 0000 C CNN
+ 3 4650 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF336
+P 3550 2650
+F 0 "U1" H 3600 2750 30 0000 C CNN
+F 1 "PORT" H 3550 2650 30 0000 C CNN
+F 2 "" H 3550 2650 60 0000 C CNN
+F 3 "" H 3550 2650 60 0000 C CNN
+ 1 3550 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AF413
+P 6200 2750
+F 0 "U1" H 6250 2850 30 0000 C CNN
+F 1 "PORT" H 6200 2750 30 0000 C CNN
+F 2 "" H 6200 2750 60 0000 C CNN
+F 3 "" H 6200 2750 60 0000 C CNN
+ 4 6200 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF82C
+P 6200 3150
+F 0 "U1" H 6250 3250 30 0000 C CNN
+F 1 "PORT" H 6200 3150 30 0000 C CNN
+F 2 "" H 6200 3150 60 0000 C CNN
+F 3 "" H 6200 3150 60 0000 C CNN
+ 5 6200 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF895
+P 4550 4050
+F 0 "U1" H 4600 4150 30 0000 C CNN
+F 1 "PORT" H 4550 4050 30 0000 C CNN
+F 2 "" H 4550 4050 60 0000 C CNN
+F 3 "" H 4550 4050 60 0000 C CNN
+ 2 4550 4050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 3900 5350 3900
+Wire Wire Line
+ 4800 4050 4800 3900
+Connection ~ 4800 3900
+Wire Wire Line
+ 4300 3600 4450 3600
+Wire Wire Line
+ 4450 3600 4450 3900
+Connection ~ 4450 3900
+Wire Wire Line
+ 5450 3600 5300 3600
+Wire Wire Line
+ 5300 3600 5300 3900
+Connection ~ 5300 3900
+Wire Wire Line
+ 4400 3300 5350 3300
+Wire Wire Line
+ 4950 3050 4950 3300
+Connection ~ 4950 3300
+Wire Wire Line
+ 5950 3150 4950 3150
+Connection ~ 4950 3150
+Wire Wire Line
+ 5450 2750 5950 2750
+Wire Wire Line
+ 5850 2750 5850 3600
+Wire Wire Line
+ 5050 2750 4900 2750
+Wire Wire Line
+ 4900 2750 4900 2400
+Wire Wire Line
+ 4900 2400 4950 2400
+Wire Wire Line
+ 4950 2350 4950 2450
+Connection ~ 4950 2400
+Wire Wire Line
+ 4450 2050 3900 2050
+Wire Wire Line
+ 3900 2050 3900 3600
+Wire Wire Line
+ 3800 2650 3900 2650
+Connection ~ 3900 2650
+Connection ~ 5850 2750
+Wire Wire Line
+ 4850 2050 5000 2050
+Wire Wire Line
+ 5000 2050 5000 1650
+Wire Wire Line
+ 5000 1650 4950 1650
+Wire Wire Line
+ 4950 1550 4950 1750
+Wire Wire Line
+ 4900 1550 4950 1550
+Connection ~ 4950 1650
+$Comp
+L SKY130mode scmode1
+U 1 1 684AFD6B
+P 7350 2150
+F 0 "scmode1" H 7350 2300 98 0000 C CNB
+F 1 "SKY130mode" H 7350 2050 118 0000 C CNB
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2150
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/NAND_2.cir b/library/SubcircuitLibrary/SN54L98/NAND_2.cir
new file mode 100644
index 000000000..f3da72301
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NAND_2.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/NAND_2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jul 6 17:51:58 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC1-Pad3_ Net-_SC3-Pad2_ Net-_SC4-Pad3_ Net-_SC4-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC4-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ Net-_SC3-Pad2_ PORT
+scmode1 SKY130mode
+SC3 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/NAND_2.cir.out b/library/SubcircuitLibrary/SN54L98/NAND_2.cir.out
new file mode 100644
index 000000000..15401b956
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NAND_2.cir.out
@@ -0,0 +1,18 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_2/nand_2.cir
+
+
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad3_ net-_sc3-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc4-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ net-_sc3-pad2_ port
+* s c m o d e
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/NAND_2.pro b/library/SubcircuitLibrary/SN54L98/NAND_2.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NAND_2.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L98/NAND_2.sch b/library/SubcircuitLibrary/SN54L98/NAND_2.sch
new file mode 100644
index 000000000..ebef1d4c6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NAND_2.sch
@@ -0,0 +1,222 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:NAND_2-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684AF0E9
+P 4200 2050
+F 0 "SC2" H 4250 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4500 2137 50 0000 R CNN
+F 2 "" H 4200 550 50 0001 C CNN
+F 3 "" H 4200 2050 50 0001 C CNN
+ 1 4200 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF1CF
+P 4450 2850
+F 0 "SC1" H 4500 3150 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4750 2937 50 0000 R CNN
+F 2 "" H 4450 1350 50 0001 C CNN
+F 3 "" H 4450 2850 50 0001 C CNN
+ 1 4450 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684AF20C
+P 4850 3550
+F 0 "SC4" H 4900 3850 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5150 3637 50 0000 R CNN
+F 2 "" H 4850 2050 50 0001 C CNN
+F 3 "" H 4850 3550 50 0001 C CNN
+ 1 4850 3550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF271
+P 4350 1550
+F 0 "U1" H 4400 1650 30 0000 C CNN
+F 1 "PORT" H 4350 1550 30 0000 C CNN
+F 2 "" H 4350 1550 60 0000 C CNN
+F 3 "" H 4350 1550 60 0000 C CNN
+ 3 4350 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF336
+P 3550 2650
+F 0 "U1" H 3600 2750 30 0000 C CNN
+F 1 "PORT" H 3550 2650 30 0000 C CNN
+F 2 "" H 3550 2650 60 0000 C CNN
+F 3 "" H 3550 2650 60 0000 C CNN
+ 1 3550 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AF413
+P 5750 2450
+F 0 "U1" H 5800 2550 30 0000 C CNN
+F 1 "PORT" H 5750 2450 30 0000 C CNN
+F 2 "" H 5750 2450 60 0000 C CNN
+F 3 "" H 5750 2450 60 0000 C CNN
+ 4 5750 2450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF82C
+P 5750 3300
+F 0 "U1" H 5800 3400 30 0000 C CNN
+F 1 "PORT" H 5750 3300 30 0000 C CNN
+F 2 "" H 5750 3300 60 0000 C CNN
+F 3 "" H 5750 3300 60 0000 C CNN
+ 5 5750 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF895
+P 4400 4000
+F 0 "U1" H 4450 4100 30 0000 C CNN
+F 1 "PORT" H 4400 4000 30 0000 C CNN
+F 2 "" H 4400 4000 60 0000 C CNN
+F 3 "" H 4400 4000 60 0000 C CNN
+ 2 4400 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684AFD6B
+P 7350 2150
+F 0 "scmode1" H 7350 2300 98 0000 C CNB
+F 1 "SKY130mode" H 7350 2050 118 0000 C CNB
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684CF41D
+P 5000 2050
+F 0 "SC3" H 5050 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5300 2137 50 0000 R CNN
+F 2 "" H 5000 550 50 0001 C CNN
+F 3 "" H 5000 2050 50 0001 C CNN
+ 1 5000 2050
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 1750 4800 1750
+Wire Wire Line
+ 4600 1550 4600 1750
+Connection ~ 4600 1750
+Wire Wire Line
+ 4300 2050 4450 2050
+Wire Wire Line
+ 4450 2050 4450 1750
+Connection ~ 4450 1750
+Wire Wire Line
+ 4900 2050 4750 2050
+Wire Wire Line
+ 4750 2050 4750 1750
+Connection ~ 4750 1750
+Wire Wire Line
+ 4400 2350 4800 2350
+Wire Wire Line
+ 4650 2550 4650 2350
+Connection ~ 4650 2350
+Wire Wire Line
+ 5500 2450 4650 2450
+Connection ~ 4650 2450
+Wire Wire Line
+ 3900 2050 3900 2850
+Wire Wire Line
+ 3900 2850 4150 2850
+Wire Wire Line
+ 3800 2650 3900 2650
+Connection ~ 3900 2650
+Wire Wire Line
+ 5300 2050 5300 3550
+Wire Wire Line
+ 5300 3550 5150 3550
+Wire Wire Line
+ 5500 3300 5300 3300
+Connection ~ 5300 3300
+Wire Wire Line
+ 4550 2850 4700 2850
+Wire Wire Line
+ 4700 2850 4700 3200
+Wire Wire Line
+ 4700 3200 4650 3200
+Wire Wire Line
+ 4650 3150 4650 3250
+Connection ~ 4650 3200
+Wire Wire Line
+ 4650 3850 4650 4000
+Wire Wire Line
+ 4750 3550 4600 3550
+Wire Wire Line
+ 4600 3550 4600 3900
+Wire Wire Line
+ 4600 3900 4650 3900
+Connection ~ 4650 3900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/NAND_2.sub b/library/SubcircuitLibrary/SN54L98/NAND_2.sub
new file mode 100644
index 000000000..aa6beac0d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NAND_2.sub
@@ -0,0 +1,12 @@
+* Subcircuit NAND_2
+.subckt NAND_2 net-_sc1-pad2_ net-_sc4-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ net-_sc3-pad2_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_2/nand_2.cir
+
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad3_ net-_sc3-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+* Control Statements
+
+.ends NAND_2
diff --git a/library/SubcircuitLibrary/SN54L98/NAND_2_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/NAND_2_Previous_Values.xml
new file mode 100644
index 000000000..066d43a60
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NAND_2_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/NOR_2-cache.lib b/library/SubcircuitLibrary/SN54L98/NOR_2-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NOR_2-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/NOR_2.cir b/library/SubcircuitLibrary/SN54L98/NOR_2.cir
new file mode 100644
index 000000000..976cd2f8e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NOR_2.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_2/NOR_2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jul 7 11:47:22 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC2 Net-_SC2-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+SC3 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC2-Pad1_ Net-_SC2-Pad1_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC3-Pad2_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/NOR_2.cir.out b/library/SubcircuitLibrary/SN54L98/NOR_2.cir.out
new file mode 100644
index 000000000..5cf58fd73
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NOR_2.cir.out
@@ -0,0 +1,24 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nor_2/nor_2.cir
+
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc2 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad1_ net-_sc2-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/NOR_2.pro b/library/SubcircuitLibrary/SN54L98/NOR_2.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NOR_2.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L98/NOR_2.sch b/library/SubcircuitLibrary/SN54L98/NOR_2.sch
new file mode 100644
index 000000000..86f7c4bc6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NOR_2.sch
@@ -0,0 +1,219 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684CE7B8
+P 4750 2600
+F 0 "SC2" H 4800 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5050 2687 50 0000 R CNN
+F 2 "" H 4750 1100 50 0001 C CNN
+F 3 "" H 4750 2600 50 0001 C CNN
+ 1 4750 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684CE82E
+P 5150 3400
+F 0 "SC3" H 5200 3700 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 3487 50 0000 R CNN
+F 2 "" H 5150 1900 50 0001 C CNN
+F 3 "" H 5150 3400 50 0001 C CNN
+ 1 5150 3400
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684CE88F
+P 4050 4450
+F 0 "SC1" H 4100 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4350 4537 50 0000 R CNN
+F 2 "" H 4050 2950 50 0001 C CNN
+F 3 "" H 4050 4450 50 0001 C CNN
+ 1 4050 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684CE8CA
+P 5650 4450
+F 0 "SC4" H 5700 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5950 4537 50 0000 R CNN
+F 2 "" H 5650 2950 50 0001 C CNN
+F 3 "" H 5650 4450 50 0001 C CNN
+ 1 5650 4450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684CE919
+P 3100 3450
+F 0 "U1" H 3150 3550 30 0000 C CNN
+F 1 "PORT" H 3100 3450 30 0000 C CNN
+F 2 "" H 3100 3450 60 0000 C CNN
+F 3 "" H 3100 3450 60 0000 C CNN
+ 1 3100 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684CE990
+P 6350 3400
+F 0 "U1" H 6400 3500 30 0000 C CNN
+F 1 "PORT" H 6350 3400 30 0000 C CNN
+F 2 "" H 6350 3400 60 0000 C CNN
+F 3 "" H 6350 3400 60 0000 C CNN
+ 4 6350 3400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684CEA11
+P 6450 3900
+F 0 "U1" H 6500 4000 30 0000 C CNN
+F 1 "PORT" H 6450 3900 30 0000 C CNN
+F 2 "" H 6450 3900 60 0000 C CNN
+F 3 "" H 6450 3900 60 0000 C CNN
+ 5 6450 3900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684CEA84
+P 4700 2150
+F 0 "U1" H 4750 2250 30 0000 C CNN
+F 1 "PORT" H 4700 2150 30 0000 C CNN
+F 2 "" H 4700 2150 60 0000 C CNN
+F 3 "" H 4700 2150 60 0000 C CNN
+ 3 4700 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684CEB11
+P 4650 5100
+F 0 "U1" H 4700 5200 30 0000 C CNN
+F 1 "PORT" H 4650 5100 30 0000 C CNN
+F 2 "" H 4650 5100 60 0000 C CNN
+F 3 "" H 4650 5100 60 0000 C CNN
+ 2 4650 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684CEB6E
+P 8300 2900
+F 0 "scmode1" H 8300 3050 98 0000 C CNB
+F 1 "SKY130mode" H 8300 2800 118 0000 C CNB
+F 2 "" H 8300 3050 60 0001 C CNN
+F 3 "" H 8300 3050 60 0001 C CNN
+ 1 8300 2900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4250 4150 5450 4150
+Wire Wire Line
+ 4950 3700 4950 4150
+Connection ~ 4950 4150
+Wire Wire Line
+ 6200 3900 4950 3900
+Connection ~ 4950 3900
+Wire Wire Line
+ 4250 4750 5450 4750
+Wire Wire Line
+ 5550 4450 5400 4450
+Wire Wire Line
+ 5400 4450 5400 4750
+Connection ~ 5400 4750
+Wire Wire Line
+ 4150 4450 4300 4450
+Wire Wire Line
+ 4300 4450 4300 4750
+Connection ~ 4300 4750
+Wire Wire Line
+ 4900 5100 4900 4750
+Connection ~ 4900 4750
+Wire Wire Line
+ 5450 3400 6100 3400
+Wire Wire Line
+ 5950 3400 5950 4450
+Connection ~ 5950 3400
+Wire Wire Line
+ 4450 2600 3750 2600
+Wire Wire Line
+ 3750 2600 3750 4450
+Wire Wire Line
+ 3350 3450 3750 3450
+Connection ~ 3750 3450
+Wire Wire Line
+ 4950 2150 4950 2300
+Wire Wire Line
+ 4850 2600 5000 2600
+Wire Wire Line
+ 5000 2600 5000 2250
+Wire Wire Line
+ 5000 2250 4950 2250
+Connection ~ 4950 2250
+Wire Wire Line
+ 4950 2900 4950 3100
+Wire Wire Line
+ 5050 3400 4900 3400
+Wire Wire Line
+ 4900 3400 4900 3050
+Wire Wire Line
+ 4900 3050 4950 3050
+Connection ~ 4950 3050
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/NOR_2.sub b/library/SubcircuitLibrary/SN54L98/NOR_2.sub
new file mode 100644
index 000000000..f5a7ff023
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NOR_2.sub
@@ -0,0 +1,18 @@
+* Subcircuit NOR_2
+.subckt NOR_2 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nor_2/nor_2.cir
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc2 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad1_ net-_sc2-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends NOR_2
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/NOR_2_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/NOR_2_Previous_Values.xml
new file mode 100644
index 000000000..62dc0d0a2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/NOR_2_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98-cache.lib b/library/SubcircuitLibrary/SN54L98/SN54L98-cache.lib
new file mode 100644
index 000000000..5d02d5fe4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SN54L98-cache.lib
@@ -0,0 +1,125 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SR_FF1
+#
+DEF SR_FF1 X 0 40 Y Y 1 F N
+F0 "X" 0 -550 60 H V C CNN
+F1 "SR_FF1" 0 250 60 H V C CNN
+F2 "" 0 250 60 H I C CNN
+F3 "" 0 250 60 H I C CNN
+DRAW
+S -250 200 250 -500 0 1 0 N
+X S 1 -450 100 200 R 50 50 1 1 I
+X CLK 2 -450 -100 200 R 50 50 1 1 I
+X R 3 -450 -300 200 R 50 50 1 1 I
+X QBar 4 450 -200 200 L 50 50 1 1 O
+X Q 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.bak b/library/SubcircuitLibrary/SN54L98/SN54L98.bak
new file mode 100644
index 000000000..2b0d7c78d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SN54L98.bak
@@ -0,0 +1,385 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN54L98-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L DS_blk X2
+U 1 1 686F5D03
+P 5150 2200
+F 0 "X2" H 5150 2200 60 0000 C CNN
+F 1 "DS_blk" H 5150 1950 60 0000 C CNN
+F 2 "" H 5150 2200 60 0001 C CNN
+F 3 "" H 5150 2200 60 0001 C CNN
+ 1 5150 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L DS_blk X3
+U 1 1 686F5D60
+P 5150 3150
+F 0 "X3" H 5150 3150 60 0000 C CNN
+F 1 "DS_blk" H 5150 2900 60 0000 C CNN
+F 2 "" H 5150 3150 60 0001 C CNN
+F 3 "" H 5150 3150 60 0001 C CNN
+ 1 5150 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L DS_blk X4
+U 1 1 686F5E27
+P 5150 4100
+F 0 "X4" H 5150 4100 60 0000 C CNN
+F 1 "DS_blk" H 5150 3850 60 0000 C CNN
+F 2 "" H 5150 4100 60 0001 C CNN
+F 3 "" H 5150 4100 60 0001 C CNN
+ 1 5150 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L DS_blk X5
+U 1 1 686F5E96
+P 5150 5150
+F 0 "X5" H 5150 5150 60 0000 C CNN
+F 1 "DS_blk" H 5150 4900 60 0000 C CNN
+F 2 "" H 5150 5150 60 0001 C CNN
+F 3 "" H 5150 5150 60 0001 C CNN
+ 1 5150 5150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5600 2150 5650 2150
+Wire Wire Line
+ 5650 2150 5650 5550
+Wire Wire Line
+ 5650 5550 4400 5550
+Wire Wire Line
+ 5600 5300 5700 5300
+Wire Wire Line
+ 5700 5300 5700 2350
+Wire Wire Line
+ 5700 2350 5600 2350
+Wire Wire Line
+ 5600 3300 5700 3300
+Connection ~ 5700 3300
+Wire Wire Line
+ 5600 3100 5650 3100
+Connection ~ 5650 3100
+Wire Wire Line
+ 5600 4250 5700 4250
+Connection ~ 5700 4250
+Wire Wire Line
+ 5600 4050 5650 4050
+Connection ~ 5650 4050
+Wire Wire Line
+ 5600 5100 5650 5100
+Connection ~ 5650 5100
+Wire Wire Line
+ 5750 5000 5600 5000
+Wire Wire Line
+ 5750 1950 5750 5000
+Wire Wire Line
+ 5750 2050 5600 2050
+Wire Wire Line
+ 5600 3000 5750 3000
+Connection ~ 5750 3000
+Wire Wire Line
+ 5600 3950 5750 3950
+Connection ~ 5750 3950
+Wire Wire Line
+ 4700 2150 4550 2150
+Wire Wire Line
+ 4550 2150 4550 5100
+Wire Wire Line
+ 4550 5100 4700 5100
+Wire Wire Line
+ 4600 5200 4700 5200
+Wire Wire Line
+ 4600 2250 4600 5200
+Wire Wire Line
+ 4600 4150 4700 4150
+Wire Wire Line
+ 4700 4050 4550 4050
+Connection ~ 4550 4050
+Wire Wire Line
+ 4600 3200 4700 3200
+Connection ~ 4600 4150
+Wire Wire Line
+ 4700 3100 4550 3100
+Connection ~ 4550 3100
+Wire Wire Line
+ 4050 2250 4700 2250
+Connection ~ 4600 3200
+$Comp
+L CMOS_INVTR X1
+U 1 1 686F65EF
+P 4000 2150
+F 0 "X1" H 4000 2150 60 0000 C CNN
+F 1 "CMOS_INVTR" H 4050 1950 60 0000 C CNN
+F 2 "" H 4000 2150 60 0001 C CNN
+F 3 "" H 4000 2150 60 0001 C CNN
+ 1 4000 2150
+ 1 0 0 -1
+$EndComp
+Connection ~ 4550 2150
+Connection ~ 4600 2250
+Wire Wire Line
+ 4050 2250 4050 2450
+Wire Wire Line
+ 4050 2450 3450 2450
+Wire Wire Line
+ 3450 2450 3450 2150
+Wire Wire Line
+ 3400 2150 3600 2150
+Wire Wire Line
+ 3600 2050 3600 1950
+Wire Wire Line
+ 3500 1950 5750 1950
+Connection ~ 5750 2050
+Wire Wire Line
+ 3600 2250 3600 2500
+Wire Wire Line
+ 3500 2500 5700 2500
+Connection ~ 5700 2500
+$Comp
+L PORT U1
+U 2 1 686F670F
+P 3250 1950
+F 0 "U1" H 3300 2050 30 0000 C CNN
+F 1 "PORT" H 3250 1950 30 0000 C CNN
+F 2 "" H 3250 1950 60 0000 C CNN
+F 3 "" H 3250 1950 60 0000 C CNN
+ 2 3250 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686F6756
+P 3150 2150
+F 0 "U1" H 3200 2250 30 0000 C CNN
+F 1 "PORT" H 3150 2150 30 0000 C CNN
+F 2 "" H 3150 2150 60 0000 C CNN
+F 3 "" H 3150 2150 60 0000 C CNN
+ 1 3150 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686F6781
+P 3250 2500
+F 0 "U1" H 3300 2600 30 0000 C CNN
+F 1 "PORT" H 3250 2500 30 0000 C CNN
+F 2 "" H 3250 2500 60 0000 C CNN
+F 3 "" H 3250 2500 60 0000 C CNN
+ 3 3250 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686F67D4
+P 4450 2050
+F 0 "U1" H 4500 2150 30 0000 C CNN
+F 1 "PORT" H 4450 2050 30 0000 C CNN
+F 2 "" H 4450 2050 60 0000 C CNN
+F 3 "" H 4450 2050 60 0000 C CNN
+ 5 4450 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686F6822
+P 4450 2350
+F 0 "U1" H 4500 2450 30 0000 C CNN
+F 1 "PORT" H 4450 2350 30 0000 C CNN
+F 2 "" H 4450 2350 60 0000 C CNN
+F 3 "" H 4450 2350 60 0000 C CNN
+ 6 4450 2350
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686F699A
+P 4450 3000
+F 0 "U1" H 4500 3100 30 0000 C CNN
+F 1 "PORT" H 4450 3000 30 0000 C CNN
+F 2 "" H 4450 3000 60 0000 C CNN
+F 3 "" H 4450 3000 60 0000 C CNN
+ 7 4450 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686F6A01
+P 4450 3300
+F 0 "U1" H 4500 3400 30 0000 C CNN
+F 1 "PORT" H 4450 3300 30 0000 C CNN
+F 2 "" H 4450 3300 60 0000 C CNN
+F 3 "" H 4450 3300 60 0000 C CNN
+ 8 4450 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686F6ACC
+P 4450 3950
+F 0 "U1" H 4500 4050 30 0000 C CNN
+F 1 "PORT" H 4450 3950 30 0000 C CNN
+F 2 "" H 4450 3950 60 0000 C CNN
+F 3 "" H 4450 3950 60 0000 C CNN
+ 9 4450 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686F6BE4
+P 4450 4250
+F 0 "U1" H 4500 4350 30 0000 C CNN
+F 1 "PORT" H 4450 4250 30 0000 C CNN
+F 2 "" H 4450 4250 60 0000 C CNN
+F 3 "" H 4450 4250 60 0000 C CNN
+ 10 4450 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686F6C5B
+P 4450 5000
+F 0 "U1" H 4500 5100 30 0000 C CNN
+F 1 "PORT" H 4450 5000 30 0000 C CNN
+F 2 "" H 4450 5000 60 0000 C CNN
+F 3 "" H 4450 5000 60 0000 C CNN
+ 11 4450 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686F6CBC
+P 4450 5300
+F 0 "U1" H 4500 5400 30 0000 C CNN
+F 1 "PORT" H 4450 5300 30 0000 C CNN
+F 2 "" H 4450 5300 60 0000 C CNN
+F 3 "" H 4450 5300 60 0000 C CNN
+ 12 4450 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686F6D53
+P 4150 5550
+F 0 "U1" H 4200 5650 30 0000 C CNN
+F 1 "PORT" H 4150 5550 30 0000 C CNN
+F 2 "" H 4150 5550 60 0000 C CNN
+F 3 "" H 4150 5550 60 0000 C CNN
+ 4 4150 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686F70B5
+P 5850 2250
+F 0 "U1" H 5900 2350 30 0000 C CNN
+F 1 "PORT" H 5850 2250 30 0000 C CNN
+F 2 "" H 5850 2250 60 0000 C CNN
+F 3 "" H 5850 2250 60 0000 C CNN
+ 13 5850 2250
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 686F7112
+P 5850 3200
+F 0 "U1" H 5900 3300 30 0000 C CNN
+F 1 "PORT" H 5850 3200 30 0000 C CNN
+F 2 "" H 5850 3200 60 0000 C CNN
+F 3 "" H 5850 3200 60 0000 C CNN
+ 14 5850 3200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 686F71D8
+P 5850 4150
+F 0 "U1" H 5900 4250 30 0000 C CNN
+F 1 "PORT" H 5850 4150 30 0000 C CNN
+F 2 "" H 5850 4150 60 0000 C CNN
+F 3 "" H 5850 4150 60 0000 C CNN
+ 15 5850 4150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 686F729F
+P 5850 5200
+F 0 "U1" H 5900 5300 30 0000 C CNN
+F 1 "PORT" H 5850 5200 30 0000 C CNN
+F 2 "" H 5850 5200 60 0000 C CNN
+F 3 "" H 5850 5200 60 0000 C CNN
+ 16 5850 5200
+ -1 0 0 -1
+$EndComp
+Connection ~ 3600 1950
+Connection ~ 3450 2150
+Connection ~ 3600 2500
+$Comp
+L SKY130mode scmode1
+U 1 1 686F754B
+P 9550 3300
+F 0 "scmode1" H 9550 3450 98 0000 C CNB
+F 1 "SKY130mode" H 9550 3200 118 0000 C CNB
+F 2 "" H 9550 3450 60 0001 C CNN
+F 3 "" H 9550 3450 60 0001 C CNN
+ 1 9550 3300
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.cir b/library/SubcircuitLibrary/SN54L98/SN54L98.cir
new file mode 100644
index 000000000..6f0602b90
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SN54L98.cir
@@ -0,0 +1,34 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN54L98\SN54L98.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/25 09:28:48
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 /2 Net-_U1-Pad2_ Net-_U12-Pad1_ d_and
+U4 Net-_U10-Pad1_ /1 Net-_U12-Pad2_ d_and
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nor
+U5 Net-_U24-Pad3_ Net-_U1-Pad2_ Net-_U13-Pad1_ d_and
+U6 Net-_U10-Pad1_ /4 Net-_U13-Pad2_ d_and
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nor
+U7 /5 Net-_U1-Pad2_ Net-_U14-Pad1_ d_and
+U8 Net-_U10-Pad1_ /6 Net-_U14-Pad2_ d_and
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nor
+U9 /12 Net-_U1-Pad2_ Net-_U15-Pad1_ d_and
+U10 Net-_U10-Pad1_ /7 Net-_U10-Pad3_ d_and
+U15 Net-_U15-Pad1_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_nor
+U1 /9 Net-_U1-Pad2_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U10-Pad1_ d_inverter
+U16 Net-_U12-Pad3_ Net-_U16-Pad2_ d_inverter
+U17 Net-_U13-Pad3_ Net-_U17-Pad2_ d_inverter
+U18 Net-_U14-Pad3_ Net-_U18-Pad2_ d_inverter
+U19 Net-_U15-Pad3_ Net-_U19-Pad2_ d_inverter
+U11 /10 Net-_U11-Pad2_ d_buffer
+U24 /1 /2 Net-_U24-Pad3_ /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 Net-_U24-Pad15_ ? PORT
+X1 Net-_U16-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad3_ ? Net-_U24-Pad15_ SR_FF1
+X2 Net-_U17-Pad2_ Net-_U11-Pad2_ Net-_U13-Pad3_ ? /14 SR_FF1
+X3 Net-_U18-Pad2_ Net-_U11-Pad2_ Net-_U14-Pad3_ ? /13 SR_FF1
+X4 Net-_U19-Pad2_ Net-_U11-Pad2_ Net-_U15-Pad3_ ? /11 SR_FF1
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.cir.out b/library/SubcircuitLibrary/SN54L98/SN54L98.cir.out
new file mode 100644
index 000000000..ae6b014bc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SN54L98.cir.out
@@ -0,0 +1,93 @@
+* d:\fossee\esim\library\subcircuitlibrary\sn54l98\sn54l98.cir
+
+.include SR_FF1.sub
+* u3 /2 net-_u1-pad2_ net-_u12-pad1_ d_and
+* u4 net-_u10-pad1_ /1 net-_u12-pad2_ d_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor
+* u5 net-_u24-pad3_ net-_u1-pad2_ net-_u13-pad1_ d_and
+* u6 net-_u10-pad1_ /4 net-_u13-pad2_ d_and
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor
+* u7 /5 net-_u1-pad2_ net-_u14-pad1_ d_and
+* u8 net-_u10-pad1_ /6 net-_u14-pad2_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
+* u9 /12 net-_u1-pad2_ net-_u15-pad1_ d_and
+* u10 net-_u10-pad1_ /7 net-_u10-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_nor
+* u1 /9 net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u10-pad1_ d_inverter
+* u16 net-_u12-pad3_ net-_u16-pad2_ d_inverter
+* u17 net-_u13-pad3_ net-_u17-pad2_ d_inverter
+* u18 net-_u14-pad3_ net-_u18-pad2_ d_inverter
+* u19 net-_u15-pad3_ net-_u19-pad2_ d_inverter
+* u11 /10 net-_u11-pad2_ d_buffer
+* u24 /1 /2 net-_u24-pad3_ /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 net-_u24-pad15_ ? port
+x1 net-_u16-pad2_ net-_u11-pad2_ net-_u12-pad3_ ? net-_u24-pad15_ SR_FF1
+x2 net-_u17-pad2_ net-_u11-pad2_ net-_u13-pad3_ ? /14 SR_FF1
+x3 net-_u18-pad2_ net-_u11-pad2_ net-_u14-pad3_ ? /13 SR_FF1
+x4 net-_u19-pad2_ net-_u11-pad2_ net-_u15-pad3_ ? /11 SR_FF1
+a1 [/2 net-_u1-pad2_ ] net-_u12-pad1_ u3
+a2 [net-_u10-pad1_ /1 ] net-_u12-pad2_ u4
+a3 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a4 [net-_u24-pad3_ net-_u1-pad2_ ] net-_u13-pad1_ u5
+a5 [net-_u10-pad1_ /4 ] net-_u13-pad2_ u6
+a6 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a7 [/5 net-_u1-pad2_ ] net-_u14-pad1_ u7
+a8 [net-_u10-pad1_ /6 ] net-_u14-pad2_ u8
+a9 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a10 [/12 net-_u1-pad2_ ] net-_u15-pad1_ u9
+a11 [net-_u10-pad1_ /7 ] net-_u10-pad3_ u10
+a12 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15
+a13 /9 net-_u1-pad2_ u1
+a14 net-_u1-pad2_ net-_u10-pad1_ u2
+a15 net-_u12-pad3_ net-_u16-pad2_ u16
+a16 net-_u13-pad3_ net-_u17-pad2_ u17
+a17 net-_u14-pad3_ net-_u18-pad2_ u18
+a18 net-_u15-pad3_ net-_u19-pad2_ u19
+a19 /10 net-_u11-pad2_ u11
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.pro b/library/SubcircuitLibrary/SN54L98/SN54L98.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SN54L98.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.sch b/library/SubcircuitLibrary/SN54L98/SN54L98.sch
new file mode 100644
index 000000000..8e9c34e38
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SN54L98.sch
@@ -0,0 +1,775 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN54L98-cache
+EELAYER 25 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U3
+U 1 1 684462F9
+P 7050 2750
+F 0 "U3" H 7050 2750 60 0000 C CNN
+F 1 "d_and" H 7100 2850 60 0000 C CNN
+F 2 "" H 7050 2750 60 0000 C CNN
+F 3 "" H 7050 2750 60 0000 C CNN
+ 1 7050 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 6844638C
+P 7050 3150
+F 0 "U4" H 7050 3150 60 0000 C CNN
+F 1 "d_and" H 7100 3250 60 0000 C CNN
+F 2 "" H 7050 3150 60 0000 C CNN
+F 3 "" H 7050 3150 60 0000 C CNN
+ 1 7050 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U12
+U 1 1 684463BD
+P 8300 2950
+F 0 "U12" H 8300 2950 60 0000 C CNN
+F 1 "d_nor" H 8350 3050 60 0000 C CNN
+F 2 "" H 8300 2950 60 0000 C CNN
+F 3 "" H 8300 2950 60 0000 C CNN
+ 1 8300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 684464BF
+P 7050 3700
+F 0 "U5" H 7050 3700 60 0000 C CNN
+F 1 "d_and" H 7100 3800 60 0000 C CNN
+F 2 "" H 7050 3700 60 0000 C CNN
+F 3 "" H 7050 3700 60 0000 C CNN
+ 1 7050 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 684464C5
+P 7050 4100
+F 0 "U6" H 7050 4100 60 0000 C CNN
+F 1 "d_and" H 7100 4200 60 0000 C CNN
+F 2 "" H 7050 4100 60 0000 C CNN
+F 3 "" H 7050 4100 60 0000 C CNN
+ 1 7050 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U13
+U 1 1 684464CB
+P 8300 3900
+F 0 "U13" H 8300 3900 60 0000 C CNN
+F 1 "d_nor" H 8350 4000 60 0000 C CNN
+F 2 "" H 8300 3900 60 0000 C CNN
+F 3 "" H 8300 3900 60 0000 C CNN
+ 1 8300 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U7
+U 1 1 684465EB
+P 7050 4600
+F 0 "U7" H 7050 4600 60 0000 C CNN
+F 1 "d_and" H 7100 4700 60 0000 C CNN
+F 2 "" H 7050 4600 60 0000 C CNN
+F 3 "" H 7050 4600 60 0000 C CNN
+ 1 7050 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U8
+U 1 1 684465F1
+P 7050 5000
+F 0 "U8" H 7050 5000 60 0000 C CNN
+F 1 "d_and" H 7100 5100 60 0000 C CNN
+F 2 "" H 7050 5000 60 0000 C CNN
+F 3 "" H 7050 5000 60 0000 C CNN
+ 1 7050 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U14
+U 1 1 684465F7
+P 8300 4800
+F 0 "U14" H 8300 4800 60 0000 C CNN
+F 1 "d_nor" H 8350 4900 60 0000 C CNN
+F 2 "" H 8300 4800 60 0000 C CNN
+F 3 "" H 8300 4800 60 0000 C CNN
+ 1 8300 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U9
+U 1 1 684465FD
+P 7050 5550
+F 0 "U9" H 7050 5550 60 0000 C CNN
+F 1 "d_and" H 7100 5650 60 0000 C CNN
+F 2 "" H 7050 5550 60 0000 C CNN
+F 3 "" H 7050 5550 60 0000 C CNN
+ 1 7050 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U10
+U 1 1 68446603
+P 7050 5950
+F 0 "U10" H 7050 5950 60 0000 C CNN
+F 1 "d_and" H 7100 6050 60 0000 C CNN
+F 2 "" H 7050 5950 60 0000 C CNN
+F 3 "" H 7050 5950 60 0000 C CNN
+ 1 7050 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U15
+U 1 1 68446609
+P 8300 5750
+F 0 "U15" H 8300 5750 60 0000 C CNN
+F 1 "d_nor" H 8350 5850 60 0000 C CNN
+F 2 "" H 8300 5750 60 0000 C CNN
+F 3 "" H 8300 5750 60 0000 C CNN
+ 1 8300 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U1
+U 1 1 68448362
+P 4050 2800
+F 0 "U1" H 4050 2700 60 0000 C CNN
+F 1 "d_inverter" H 4050 2950 60 0000 C CNN
+F 2 "" H 4100 2750 60 0000 C CNN
+F 3 "" H 4100 2750 60 0000 C CNN
+ 1 4050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 6844844E
+P 4450 3250
+F 0 "U2" H 4450 3150 60 0000 C CNN
+F 1 "d_inverter" H 4450 3400 60 0000 C CNN
+F 2 "" H 4500 3200 60 0000 C CNN
+F 3 "" H 4500 3200 60 0000 C CNN
+ 1 4450 3250
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 68448BC5
+P 9400 2900
+F 0 "U16" H 9400 2800 60 0000 C CNN
+F 1 "d_inverter" H 9400 3050 60 0000 C CNN
+F 2 "" H 9450 2850 60 0000 C CNN
+F 3 "" H 9450 2850 60 0000 C CNN
+ 1 9400 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U17
+U 1 1 68448C3E
+P 9400 3850
+F 0 "U17" H 9400 3750 60 0000 C CNN
+F 1 "d_inverter" H 9400 4000 60 0000 C CNN
+F 2 "" H 9450 3800 60 0000 C CNN
+F 3 "" H 9450 3800 60 0000 C CNN
+ 1 9400 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U18
+U 1 1 68448CDD
+P 9400 4750
+F 0 "U18" H 9400 4650 60 0000 C CNN
+F 1 "d_inverter" H 9400 4900 60 0000 C CNN
+F 2 "" H 9450 4700 60 0000 C CNN
+F 3 "" H 9450 4700 60 0000 C CNN
+ 1 9400 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U19
+U 1 1 68448CE3
+P 9450 5700
+F 0 "U19" H 9450 5600 60 0000 C CNN
+F 1 "d_inverter" H 9450 5850 60 0000 C CNN
+F 2 "" H 9500 5650 60 0000 C CNN
+F 3 "" H 9500 5650 60 0000 C CNN
+ 1 9450 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U11
+U 1 1 6844B65C
+P 7100 7150
+F 0 "U11" H 7100 7100 60 0000 C CNN
+F 1 "d_buffer" H 7100 7200 60 0000 C CNN
+F 2 "" H 7100 7150 60 0000 C CNN
+F 3 "" H 7100 7150 60 0000 C CNN
+ 1 7100 7150
+ 1 0 0 -1
+$EndComp
+NoConn ~ 9500 350
+Text Label 12100 3400 0 60 ~ 0
+14
+Text Label 12200 5050 0 60 ~ 0
+13
+Text Label 12200 6750 0 60 ~ 0
+11
+Text Label 5000 7150 0 60 ~ 0
+10
+Text Label 5200 5950 0 60 ~ 0
+7
+Text Label 5000 5450 0 60 ~ 0
+12
+Text Label 5000 5000 0 60 ~ 0
+6
+Text Label 5000 4500 0 60 ~ 0
+5
+Text Label 5000 4100 0 60 ~ 0
+4
+Text Label 5000 3600 0 60 ~ 0
+3
+Text Label 5000 3150 0 60 ~ 0
+1
+Text Label 5000 2650 0 60 ~ 0
+2
+Text Label 3250 2800 0 60 ~ 0
+9
+$Comp
+L PORT U24
+U 4 1 6845B79C
+P 4750 4100
+F 0 "U24" H 4800 4200 30 0000 C CNN
+F 1 "PORT" H 4750 4100 30 0000 C CNN
+F 2 "" H 4750 4100 60 0000 C CNN
+F 3 "" H 4750 4100 60 0000 C CNN
+ 4 4750 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 8 1 6845B837
+P 7850 1750
+F 0 "U24" H 7900 1850 30 0000 C CNN
+F 1 "PORT" H 7850 1750 30 0000 C CNN
+F 2 "" H 7850 1750 60 0000 C CNN
+F 3 "" H 7850 1750 60 0000 C CNN
+ 8 7850 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 12 1 6845B87E
+P 4750 5450
+F 0 "U24" H 4800 5550 30 0000 C CNN
+F 1 "PORT" H 4750 5450 30 0000 C CNN
+F 2 "" H 4750 5450 60 0000 C CNN
+F 3 "" H 4750 5450 60 0000 C CNN
+ 12 4750 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 2 1 6845B8CB
+P 4750 2650
+F 0 "U24" H 4800 2750 30 0000 C CNN
+F 1 "PORT" H 4750 2650 30 0000 C CNN
+F 2 "" H 4750 2650 60 0000 C CNN
+F 3 "" H 4750 2650 60 0000 C CNN
+ 2 4750 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 7 1 6845B928
+P 4950 5950
+F 0 "U24" H 5000 6050 30 0000 C CNN
+F 1 "PORT" H 4950 5950 30 0000 C CNN
+F 2 "" H 4950 5950 60 0000 C CNN
+F 3 "" H 4950 5950 60 0000 C CNN
+ 7 4950 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 13 1 6845B975
+P 12450 5200
+F 0 "U24" H 12500 5300 30 0000 C CNN
+F 1 "PORT" H 12450 5200 30 0000 C CNN
+F 2 "" H 12450 5200 60 0000 C CNN
+F 3 "" H 12450 5200 60 0000 C CNN
+ 13 12450 5200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U24
+U 5 1 6845B9C6
+P 4750 4500
+F 0 "U24" H 4800 4600 30 0000 C CNN
+F 1 "PORT" H 4750 4500 30 0000 C CNN
+F 2 "" H 4750 4500 60 0000 C CNN
+F 3 "" H 4750 4500 60 0000 C CNN
+ 5 4750 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 10 1 6845BA17
+P 4750 7150
+F 0 "U24" H 4800 7250 30 0000 C CNN
+F 1 "PORT" H 4750 7150 30 0000 C CNN
+F 2 "" H 4750 7150 60 0000 C CNN
+F 3 "" H 4750 7150 60 0000 C CNN
+ 10 4750 7150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 15 1 6845BA6A
+P 11900 1850
+F 0 "U24" H 11950 1950 30 0000 C CNN
+F 1 "PORT" H 11900 1850 30 0000 C CNN
+F 2 "" H 11900 1850 60 0000 C CNN
+F 3 "" H 11900 1850 60 0000 C CNN
+ 15 11900 1850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U24
+U 1 1 6845BABF
+P 4750 3150
+F 0 "U24" H 4800 3250 30 0000 C CNN
+F 1 "PORT" H 4750 3150 30 0000 C CNN
+F 2 "" H 4750 3150 60 0000 C CNN
+F 3 "" H 4750 3150 60 0000 C CNN
+ 1 4750 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 6 1 6845BB3E
+P 4750 5000
+F 0 "U24" H 4800 5100 30 0000 C CNN
+F 1 "PORT" H 4750 5000 30 0000 C CNN
+F 2 "" H 4750 5000 60 0000 C CNN
+F 3 "" H 4750 5000 60 0000 C CNN
+ 6 4750 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 11 1 6845BB97
+P 12450 6750
+F 0 "U24" H 12500 6850 30 0000 C CNN
+F 1 "PORT" H 12450 6750 30 0000 C CNN
+F 2 "" H 12450 6750 60 0000 C CNN
+F 3 "" H 12450 6750 60 0000 C CNN
+ 11 12450 6750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U24
+U 16 1 6845BBF8
+P 7850 1950
+F 0 "U24" H 7900 2050 30 0000 C CNN
+F 1 "PORT" H 7850 1950 30 0000 C CNN
+F 2 "" H 7850 1950 60 0000 C CNN
+F 3 "" H 7850 1950 60 0000 C CNN
+ 16 7850 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 3 1 6845BC55
+P 4800 3650
+F 0 "U24" H 4850 3750 30 0000 C CNN
+F 1 "PORT" H 4800 3650 30 0000 C CNN
+F 2 "" H 4800 3650 60 0000 C CNN
+F 3 "" H 4800 3650 60 0000 C CNN
+ 3 4800 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 9 1 6845BCB4
+P 3000 2800
+F 0 "U24" H 3050 2900 30 0000 C CNN
+F 1 "PORT" H 3000 2800 30 0000 C CNN
+F 2 "" H 3000 2800 60 0000 C CNN
+F 3 "" H 3000 2800 60 0000 C CNN
+ 9 3000 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U24
+U 14 1 6845BD15
+P 12400 3600
+F 0 "U24" H 12450 3700 30 0000 C CNN
+F 1 "PORT" H 12400 3600 30 0000 C CNN
+F 2 "" H 12400 3600 60 0000 C CNN
+F 3 "" H 12400 3600 60 0000 C CNN
+ 14 12400 3600
+ -1 0 0 1
+$EndComp
+NoConn ~ 8100 1750
+NoConn ~ 8100 1950
+NoConn ~ 11350 3650
+NoConn ~ 11450 5250
+NoConn ~ 11650 7000
+$Comp
+L SR_FF1 X1
+U 1 1 6873360B
+P 10900 1850
+F 0 "X1" H 10900 1300 60 0000 C CNN
+F 1 "SR_FF1" H 10900 2100 60 0000 C CNN
+F 2 "" H 10900 2100 60 0001 C CNN
+F 3 "" H 10900 2100 60 0001 C CNN
+ 1 10900 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L SR_FF1 X2
+U 1 1 687336DD
+P 10900 3450
+F 0 "X2" H 10900 2900 60 0000 C CNN
+F 1 "SR_FF1" H 10900 3700 60 0000 C CNN
+F 2 "" H 10900 3700 60 0001 C CNN
+F 3 "" H 10900 3700 60 0001 C CNN
+ 1 10900 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L SR_FF1 X3
+U 1 1 6873377E
+P 11000 5050
+F 0 "X3" H 11000 4500 60 0000 C CNN
+F 1 "SR_FF1" H 11000 5300 60 0000 C CNN
+F 2 "" H 11000 5300 60 0001 C CNN
+F 3 "" H 11000 5300 60 0001 C CNN
+ 1 11000 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L SR_FF1 X4
+U 1 1 68733803
+P 11200 6800
+F 0 "X4" H 11200 6250 60 0000 C CNN
+F 1 "SR_FF1" H 11200 7050 60 0000 C CNN
+F 2 "" H 11200 7050 60 0001 C CNN
+F 3 "" H 11200 7050 60 0001 C CNN
+ 1 11200 6800
+ 1 0 0 -1
+$EndComp
+NoConn ~ 11350 2050
+Wire Wire Line
+ 7500 2700 7650 2700
+Wire Wire Line
+ 7650 2700 7650 2850
+Wire Wire Line
+ 7650 2850 7850 2850
+Wire Wire Line
+ 7500 3100 7650 3100
+Wire Wire Line
+ 7650 3100 7650 2950
+Wire Wire Line
+ 7650 2950 7850 2950
+Wire Wire Line
+ 7500 3650 7600 3650
+Wire Wire Line
+ 7600 3650 7600 3800
+Wire Wire Line
+ 7600 3800 7850 3800
+Wire Wire Line
+ 7500 4050 7600 4050
+Wire Wire Line
+ 7600 4050 7600 3900
+Wire Wire Line
+ 7600 3900 7850 3900
+Wire Wire Line
+ 7500 4550 7650 4550
+Wire Wire Line
+ 7650 4550 7650 4700
+Wire Wire Line
+ 7650 4700 7850 4700
+Wire Wire Line
+ 7500 4950 7650 4950
+Wire Wire Line
+ 7650 4950 7650 4800
+Wire Wire Line
+ 7650 4800 7850 4800
+Wire Wire Line
+ 7500 5500 7650 5500
+Wire Wire Line
+ 7650 5500 7650 5650
+Wire Wire Line
+ 7650 5650 7850 5650
+Wire Wire Line
+ 7500 5900 7650 5900
+Wire Wire Line
+ 7650 5900 7650 5750
+Wire Wire Line
+ 7650 5750 7850 5750
+Wire Wire Line
+ 6600 2650 5000 2650
+Wire Wire Line
+ 5900 2750 6600 2750
+Wire Wire Line
+ 6050 2750 6050 5550
+Wire Wire Line
+ 6050 5550 6600 5550
+Wire Wire Line
+ 5700 5850 6600 5850
+Wire Wire Line
+ 5700 3050 5700 5850
+Wire Wire Line
+ 5700 3050 6600 3050
+Wire Wire Line
+ 6600 5950 5200 5950
+Wire Wire Line
+ 6600 3150 5000 3150
+Wire Wire Line
+ 6600 3700 6050 3700
+Connection ~ 6050 3700
+Wire Wire Line
+ 6600 4000 5700 4000
+Connection ~ 5700 4000
+Wire Wire Line
+ 6600 4100 5000 4100
+Wire Wire Line
+ 6600 4500 5000 4500
+Wire Wire Line
+ 6600 4600 6050 4600
+Connection ~ 6050 4600
+Wire Wire Line
+ 6600 4900 5700 4900
+Connection ~ 5700 4900
+Wire Wire Line
+ 6600 5000 5000 5000
+Wire Wire Line
+ 6600 5450 5000 5450
+Wire Wire Line
+ 4350 2800 5900 2800
+Wire Wire Line
+ 5900 2800 5900 2750
+Connection ~ 6050 2750
+Wire Wire Line
+ 3750 2800 3250 2800
+Wire Wire Line
+ 4450 2950 4450 2800
+Connection ~ 4450 2800
+Wire Wire Line
+ 4450 3550 4800 3550
+Wire Wire Line
+ 4800 3550 4800 3400
+Wire Wire Line
+ 4800 3400 5700 3400
+Connection ~ 5700 3400
+Wire Wire Line
+ 8750 2900 9100 2900
+Wire Wire Line
+ 8750 3850 9100 3850
+Wire Wire Line
+ 8750 4750 9100 4750
+Wire Wire Line
+ 8750 5700 9150 5700
+Wire Wire Line
+ 6600 7150 5000 7150
+Wire Wire Line
+ 7750 7150 10250 7150
+Wire Wire Line
+ 10050 5450 10350 5450
+Wire Wire Line
+ 10050 2100 10050 7150
+Connection ~ 10050 7150
+Wire Wire Line
+ 10050 3800 10250 3800
+Connection ~ 10050 5450
+Wire Wire Line
+ 10100 2100 10050 2100
+Connection ~ 10050 3800
+Wire Wire Line
+ 9700 2900 9800 2900
+Wire Wire Line
+ 9800 2900 9800 1700
+Wire Wire Line
+ 9800 1700 10100 1700
+Wire Wire Line
+ 8900 2900 8900 3100
+Wire Wire Line
+ 8900 3100 10100 3100
+Wire Wire Line
+ 10100 3100 10100 2350
+Connection ~ 8900 2900
+Wire Wire Line
+ 9700 3850 9800 3850
+Wire Wire Line
+ 9800 3850 9800 3400
+Wire Wire Line
+ 9800 3400 10300 3400
+Wire Wire Line
+ 8900 3850 8900 4250
+Wire Wire Line
+ 8900 4250 10350 4250
+Connection ~ 8900 3850
+Wire Wire Line
+ 9700 4750 9700 5050
+Wire Wire Line
+ 9000 4750 9000 5250
+Wire Wire Line
+ 9000 5250 9950 5250
+Wire Wire Line
+ 9950 5250 9950 5900
+Wire Wire Line
+ 9950 5900 10500 5900
+Connection ~ 9000 4750
+Wire Wire Line
+ 9750 5700 9750 6750
+Wire Wire Line
+ 9750 6750 10550 6750
+Wire Wire Line
+ 8900 5700 8900 7600
+Wire Wire Line
+ 8900 7600 10450 7600
+Connection ~ 8900 5700
+Wire Wire Line
+ 11700 3400 12100 3400
+Wire Wire Line
+ 5050 3600 6600 3600
+Wire Wire Line
+ 5050 3650 5050 3600
+Wire Wire Line
+ 12200 5050 12200 5200
+Wire Wire Line
+ 12100 3400 12100 3600
+Wire Wire Line
+ 12100 3600 12150 3600
+Wire Wire Line
+ 10100 1700 10100 1750
+Wire Wire Line
+ 10100 1750 10450 1750
+Wire Wire Line
+ 10100 2100 10100 1900
+Wire Wire Line
+ 10100 1900 10250 1900
+Wire Wire Line
+ 10100 2350 10350 2350
+Wire Wire Line
+ 10250 3800 10250 3550
+Wire Wire Line
+ 10250 3550 10450 3550
+Wire Wire Line
+ 11350 3450 11700 3450
+Wire Wire Line
+ 11700 3450 11700 3400
+Wire Wire Line
+ 11450 5050 12200 5050
+Wire Wire Line
+ 10350 5450 10350 5150
+Wire Wire Line
+ 10350 5150 10550 5150
+Wire Wire Line
+ 10250 6900 10750 6900
+Wire Wire Line
+ 10450 7050 10550 7050
+Wire Wire Line
+ 10250 7150 10250 6900
+Wire Wire Line
+ 10450 7600 10450 7050
+Wire Wire Line
+ 11650 6800 11800 6800
+Wire Wire Line
+ 11800 6800 11800 6750
+Wire Wire Line
+ 11800 6750 12200 6750
+Wire Wire Line
+ 10250 1900 10250 1950
+Wire Wire Line
+ 10250 1950 10450 1950
+Wire Wire Line
+ 10350 2350 10350 2150
+Wire Wire Line
+ 10350 2150 10450 2150
+Wire Wire Line
+ 11350 1850 11650 1850
+Wire Wire Line
+ 10300 3400 10300 3350
+Wire Wire Line
+ 10300 3350 10450 3350
+Wire Wire Line
+ 10350 4250 10350 3750
+Wire Wire Line
+ 10350 3750 10450 3750
+Wire Wire Line
+ 9700 5050 10250 5050
+Wire Wire Line
+ 10250 5050 10250 4950
+Wire Wire Line
+ 10250 4950 10550 4950
+Wire Wire Line
+ 10500 5900 10500 5350
+Wire Wire Line
+ 10500 5350 10550 5350
+Wire Wire Line
+ 10550 7050 10550 7100
+Wire Wire Line
+ 10550 7100 10750 7100
+Wire Wire Line
+ 10550 6750 10550 6700
+Wire Wire Line
+ 10550 6700 10750 6700
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98.sub b/library/SubcircuitLibrary/SN54L98/SN54L98.sub
new file mode 100644
index 000000000..9aea65b5c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SN54L98.sub
@@ -0,0 +1,87 @@
+* Subcircuit SN54L98
+.subckt SN54L98 /1 /2 net-_u24-pad3_ /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 net-_u24-pad15_ ?
+* d:\fossee\esim\library\subcircuitlibrary\sn54l98\sn54l98.cir
+.include SR_FF1.sub
+* u3 /2 net-_u1-pad2_ net-_u12-pad1_ d_and
+* u4 net-_u10-pad1_ /1 net-_u12-pad2_ d_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor
+* u5 net-_u24-pad3_ net-_u1-pad2_ net-_u13-pad1_ d_and
+* u6 net-_u10-pad1_ /4 net-_u13-pad2_ d_and
+* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor
+* u7 /5 net-_u1-pad2_ net-_u14-pad1_ d_and
+* u8 net-_u10-pad1_ /6 net-_u14-pad2_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor
+* u9 /12 net-_u1-pad2_ net-_u15-pad1_ d_and
+* u10 net-_u10-pad1_ /7 net-_u10-pad3_ d_and
+* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_nor
+* u1 /9 net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u10-pad1_ d_inverter
+* u16 net-_u12-pad3_ net-_u16-pad2_ d_inverter
+* u17 net-_u13-pad3_ net-_u17-pad2_ d_inverter
+* u18 net-_u14-pad3_ net-_u18-pad2_ d_inverter
+* u19 net-_u15-pad3_ net-_u19-pad2_ d_inverter
+* u11 /10 net-_u11-pad2_ d_buffer
+x1 net-_u16-pad2_ net-_u11-pad2_ net-_u12-pad3_ ? net-_u24-pad15_ SR_FF1
+x2 net-_u17-pad2_ net-_u11-pad2_ net-_u13-pad3_ ? /14 SR_FF1
+x3 net-_u18-pad2_ net-_u11-pad2_ net-_u14-pad3_ ? /13 SR_FF1
+x4 net-_u19-pad2_ net-_u11-pad2_ net-_u15-pad3_ ? /11 SR_FF1
+a1 [/2 net-_u1-pad2_ ] net-_u12-pad1_ u3
+a2 [net-_u10-pad1_ /1 ] net-_u12-pad2_ u4
+a3 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a4 [net-_u24-pad3_ net-_u1-pad2_ ] net-_u13-pad1_ u5
+a5 [net-_u10-pad1_ /4 ] net-_u13-pad2_ u6
+a6 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a7 [/5 net-_u1-pad2_ ] net-_u14-pad1_ u7
+a8 [net-_u10-pad1_ /6 ] net-_u14-pad2_ u8
+a9 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a10 [/12 net-_u1-pad2_ ] net-_u15-pad1_ u9
+a11 [net-_u10-pad1_ /7 ] net-_u10-pad3_ u10
+a12 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15
+a13 /9 net-_u1-pad2_ u1
+a14 net-_u1-pad2_ net-_u10-pad1_ u2
+a15 net-_u12-pad3_ net-_u16-pad2_ u16
+a16 net-_u13-pad3_ net-_u17-pad2_ u17
+a17 net-_u14-pad3_ net-_u18-pad2_ u18
+a18 net-_u15-pad3_ net-_u19-pad2_ u19
+a19 /10 net-_u11-pad2_ u11
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN54L98
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/SN54L98_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/SN54L98_Previous_Values.xml
new file mode 100644
index 000000000..47003cf75
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SN54L98_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andd_nord_andd_andd_nord_andd_andd_nord_andd_andd_nord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_srffd_srffd_srffd_srffd_bufferD:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF1truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1-cache.lib b/library/SubcircuitLibrary/SN54L98/SR_FF1-cache.lib
new file mode 100644
index 000000000..ce6d8814c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SR_FF1-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.cir b/library/SubcircuitLibrary/SN54L98/SR_FF1.cir
new file mode 100644
index 000000000..ba6a8f971
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.cir
@@ -0,0 +1,15 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF\SR_FF.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 17:59:43
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand
+U4 Net-_U2-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_nand
+U5 Net-_U1-Pad5_ Net-_U3-Pad3_ Net-_U1-Pad4_ d_nand
+U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_nand
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.cir.out b/library/SubcircuitLibrary/SN54L98/SR_FF1.cir.out
new file mode 100644
index 000000000..33d1c4912
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.cir.out
@@ -0,0 +1,28 @@
+* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand
+* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand
+* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4
+a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5
+a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.pro b/library/SubcircuitLibrary/SN54L98/SR_FF1.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.sch b/library/SubcircuitLibrary/SN54L98/SR_FF1.sch
new file mode 100644
index 000000000..58667c880
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.sch
@@ -0,0 +1,198 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nand U2
+U 1 1 686919A7
+P 4350 2800
+F 0 "U2" H 4350 2800 60 0000 C CNN
+F 1 "d_nand" H 4400 2900 60 0000 C CNN
+F 2 "" H 4350 2800 60 0000 C CNN
+F 3 "" H 4350 2800 60 0000 C CNN
+ 1 4350 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 686919EC
+P 5850 2800
+F 0 "U4" H 5850 2800 60 0000 C CNN
+F 1 "d_nand" H 5900 2900 60 0000 C CNN
+F 2 "" H 5850 2800 60 0000 C CNN
+F 3 "" H 5850 2800 60 0000 C CNN
+ 1 5850 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U5
+U 1 1 68691A1F
+P 5900 4000
+F 0 "U5" H 5900 4000 60 0000 C CNN
+F 1 "d_nand" H 5950 4100 60 0000 C CNN
+F 2 "" H 5900 4000 60 0000 C CNN
+F 3 "" H 5900 4000 60 0000 C CNN
+ 1 5900 4000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6300 2750 6800 2750
+Wire Wire Line
+ 6350 3950 7000 3950
+Wire Wire Line
+ 6700 2750 6700 3300
+Wire Wire Line
+ 6700 3300 5200 3300
+Wire Wire Line
+ 5200 3300 5200 3900
+Wire Wire Line
+ 5200 3900 5450 3900
+Connection ~ 6700 2750
+Wire Wire Line
+ 6550 3950 6550 3050
+Wire Wire Line
+ 6550 3050 5250 3050
+Wire Wire Line
+ 5250 3050 5250 2800
+Wire Wire Line
+ 5250 2800 5400 2800
+Connection ~ 6550 3950
+$Comp
+L d_nand U3
+U 1 1 68691A8B
+P 4350 4050
+F 0 "U3" H 4350 4050 60 0000 C CNN
+F 1 "d_nand" H 4400 4150 60 0000 C CNN
+F 2 "" H 4350 4050 60 0000 C CNN
+F 3 "" H 4350 4050 60 0000 C CNN
+ 1 4350 4050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 2750 4900 2750
+Wire Wire Line
+ 4900 2750 4900 2700
+Wire Wire Line
+ 4900 2700 5400 2700
+Wire Wire Line
+ 4800 4000 5450 4000
+Wire Wire Line
+ 3900 2800 3600 2800
+Wire Wire Line
+ 3600 2800 3600 3950
+Wire Wire Line
+ 3600 3950 3900 3950
+Wire Wire Line
+ 3900 2700 3150 2700
+Wire Wire Line
+ 3900 4050 3150 4050
+Wire Wire Line
+ 3600 3350 2400 3350
+Connection ~ 3600 3350
+$Comp
+L PORT U1
+U 4 1 68691B28
+P 7250 3950
+F 0 "U1" H 7300 4050 30 0000 C CNN
+F 1 "PORT" H 7250 3950 30 0000 C CNN
+F 2 "" H 7250 3950 60 0000 C CNN
+F 3 "" H 7250 3950 60 0000 C CNN
+ 4 7250 3950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68691BB8
+P 7050 2750
+F 0 "U1" H 7100 2850 30 0000 C CNN
+F 1 "PORT" H 7050 2750 30 0000 C CNN
+F 2 "" H 7050 2750 60 0000 C CNN
+F 3 "" H 7050 2750 60 0000 C CNN
+ 5 7050 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68691BFB
+P 2900 4050
+F 0 "U1" H 2950 4150 30 0000 C CNN
+F 1 "PORT" H 2900 4050 30 0000 C CNN
+F 2 "" H 2900 4050 60 0000 C CNN
+F 3 "" H 2900 4050 60 0000 C CNN
+ 3 2900 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68691C28
+P 2150 3350
+F 0 "U1" H 2200 3450 30 0000 C CNN
+F 1 "PORT" H 2150 3350 30 0000 C CNN
+F 2 "" H 2150 3350 60 0000 C CNN
+F 3 "" H 2150 3350 60 0000 C CNN
+ 2 2150 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68691C55
+P 2900 2700
+F 0 "U1" H 2950 2800 30 0000 C CNN
+F 1 "PORT" H 2900 2700 30 0000 C CNN
+F 2 "" H 2900 2700 60 0000 C CNN
+F 3 "" H 2900 2700 60 0000 C CNN
+ 1 2900 2700
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1.sub b/library/SubcircuitLibrary/SN54L98/SR_FF1.sub
new file mode 100644
index 000000000..97dd47178
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SR_FF1.sub
@@ -0,0 +1,22 @@
+* Subcircuit SR_FF
+.subckt SR_FF net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand
+* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand
+* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4
+a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5
+a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SR_FF
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/SR_FF1_Previous_Values.xml b/library/SubcircuitLibrary/SN54L98/SR_FF1_Previous_Values.xml
new file mode 100644
index 000000000..d73809c15
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/SR_FF1_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_nandd_nand
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L98/analysis b/library/SubcircuitLibrary/SN54L98/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L98/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/.spiceinit b/library/SubcircuitLibrary/SN54L99/.spiceinit
new file mode 100644
index 000000000..47fd1e960
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/.spiceinit
@@ -0,0 +1,6 @@
+
+set ngbehavior=hsa ; set compatibility for reading PDK libs
+set ng_nomodcheck ; don't check the model parameters
+set num_threads=8 ; CPU hardware threads available
+option noinit ; don't print operating point data
+optran 0 0 0 100p 2n 0 ; don't use dc operating point, but transient op)
diff --git a/library/SubcircuitLibrary/SN54L99/2_in_and-cache.lib b/library/SubcircuitLibrary/SN54L99/2_in_and-cache.lib
new file mode 100644
index 000000000..cd4456570
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/2_in_and-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NAND_2
+#
+DEF NAND_2 X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "NAND_2" 50 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+C 350 0 50 0 1 0 N
+P 2 0 1 0 -200 200 150 200 N
+P 3 0 1 0 -200 200 -200 -200 150 -200 N
+X in1 1 -400 50 200 R 50 50 1 1 I
+X Gnd 2 -400 -150 200 R 50 50 1 1 I
+X Vdd 3 -400 150 200 R 50 50 1 1 I
+X out 4 600 0 200 L 50 50 1 1 O
+X in2 5 -400 -50 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/2_in_and.bak b/library/SubcircuitLibrary/SN54L99/2_in_and.bak
new file mode 100644
index 000000000..4c88f6efd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/2_in_and.bak
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NAND_2 X1
+U 1 1 686CC211
+P 5400 3000
+F 0 "X1" H 5500 3000 60 0000 C CNN
+F 1 "NAND_2" H 5450 2750 60 0000 C CNN
+F 2 "" H 5400 3000 60 0001 C CNN
+F 3 "" H 5400 3000 60 0001 C CNN
+ 1 5400 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 686CC23B
+P 6400 3000
+F 0 "X2" H 6400 3000 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6450 2800 60 0000 C CNN
+F 2 "" H 6400 3000 60 0001 C CNN
+F 3 "" H 6400 3000 60 0001 C CNN
+ 1 6400 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 2900 6000 2900
+Wire Wire Line
+ 5000 2900 5000 2850
+Wire Wire Line
+ 4950 3100 6000 3100
+Wire Wire Line
+ 5000 3100 5000 3150
+$Comp
+L PORT U1
+U 1 1 686CC270
+P 4600 2850
+F 0 "U1" H 4650 2950 30 0000 C CNN
+F 1 "PORT" H 4600 2850 30 0000 C CNN
+F 2 "" H 4600 2850 60 0000 C CNN
+F 3 "" H 4600 2850 60 0000 C CNN
+ 1 4600 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686CC2D9
+P 4750 2950
+F 0 "U1" H 4800 3050 30 0000 C CNN
+F 1 "PORT" H 4750 2950 30 0000 C CNN
+F 2 "" H 4750 2950 60 0000 C CNN
+F 3 "" H 4750 2950 60 0000 C CNN
+ 3 4750 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686CC2FC
+P 4750 3050
+F 0 "U1" H 4800 3150 30 0000 C CNN
+F 1 "PORT" H 4750 3050 30 0000 C CNN
+F 2 "" H 4750 3050 60 0000 C CNN
+F 3 "" H 4750 3050 60 0000 C CNN
+ 4 4750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686CC31D
+P 4600 3150
+F 0 "U1" H 4650 3250 30 0000 C CNN
+F 1 "PORT" H 4600 3150 30 0000 C CNN
+F 2 "" H 4600 3150 60 0000 C CNN
+F 3 "" H 4600 3150 60 0000 C CNN
+ 2 4600 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686CC342
+P 7200 3000
+F 0 "U1" H 7250 3100 30 0000 C CNN
+F 1 "PORT" H 7200 3000 30 0000 C CNN
+F 2 "" H 7200 3000 60 0000 C CNN
+F 3 "" H 7200 3000 60 0000 C CNN
+ 5 7200 3000
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4850 2850 4950 2850
+Wire Wire Line
+ 4950 2850 4950 2900
+Connection ~ 5000 2900
+Wire Wire Line
+ 4850 3150 4950 3150
+Wire Wire Line
+ 4950 3150 4950 3100
+Connection ~ 5000 3100
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/2_in_and.cir b/library/SubcircuitLibrary/SN54L99/2_in_and.cir
new file mode 100644
index 000000000..8a30412ec
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/2_in_and.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/2_in_and/2_in_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jul 8 12:32:28 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_X1-Pad4_ Net-_U1-Pad4_ NAND_2
+X2 Net-_X1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad5_ CMOS_INVTR
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/2_in_and.cir.out b/library/SubcircuitLibrary/SN54L99/2_in_and.cir.out
new file mode 100644
index 000000000..b2bc03524
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/2_in_and.cir.out
@@ -0,0 +1,18 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/2_in_and/2_in_and.cir
+
+.include CMOS_INVTR.sub
+.include NAND_2.sub
+
+x1 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_x1-pad4_ net-_u1-pad4_ NAND_2
+x2 net-_x1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad5_ CMOS_INVTR
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/2_in_and.pro b/library/SubcircuitLibrary/SN54L99/2_in_and.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/2_in_and.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/2_in_and.sch b/library/SubcircuitLibrary/SN54L99/2_in_and.sch
new file mode 100644
index 000000000..e2a29248f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/2_in_and.sch
@@ -0,0 +1,162 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NAND_2 X1
+U 1 1 686CC211
+P 5400 3000
+F 0 "X1" H 5500 3000 60 0000 C CNN
+F 1 "NAND_2" H 5450 2750 60 0000 C CNN
+F 2 "" H 5400 3000 60 0001 C CNN
+F 3 "" H 5400 3000 60 0001 C CNN
+ 1 5400 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 686CC23B
+P 6400 3000
+F 0 "X2" H 6400 3000 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6450 2800 60 0000 C CNN
+F 2 "" H 6400 3000 60 0001 C CNN
+F 3 "" H 6400 3000 60 0001 C CNN
+ 1 6400 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 2900 6000 2900
+Wire Wire Line
+ 5000 2900 5000 2850
+Wire Wire Line
+ 4950 3100 6000 3100
+Wire Wire Line
+ 5000 3100 5000 3150
+$Comp
+L PORT U1
+U 1 1 686CC270
+P 4600 2850
+F 0 "U1" H 4650 2950 30 0000 C CNN
+F 1 "PORT" H 4600 2850 30 0000 C CNN
+F 2 "" H 4600 2850 60 0000 C CNN
+F 3 "" H 4600 2850 60 0000 C CNN
+ 1 4600 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686CC2D9
+P 4750 2950
+F 0 "U1" H 4800 3050 30 0000 C CNN
+F 1 "PORT" H 4750 2950 30 0000 C CNN
+F 2 "" H 4750 2950 60 0000 C CNN
+F 3 "" H 4750 2950 60 0000 C CNN
+ 3 4750 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686CC2FC
+P 4750 3050
+F 0 "U1" H 4800 3150 30 0000 C CNN
+F 1 "PORT" H 4750 3050 30 0000 C CNN
+F 2 "" H 4750 3050 60 0000 C CNN
+F 3 "" H 4750 3050 60 0000 C CNN
+ 4 4750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686CC31D
+P 4600 3150
+F 0 "U1" H 4650 3250 30 0000 C CNN
+F 1 "PORT" H 4600 3150 30 0000 C CNN
+F 2 "" H 4600 3150 60 0000 C CNN
+F 3 "" H 4600 3150 60 0000 C CNN
+ 2 4600 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686CC342
+P 7200 3000
+F 0 "U1" H 7250 3100 30 0000 C CNN
+F 1 "PORT" H 7200 3000 30 0000 C CNN
+F 2 "" H 7200 3000 60 0000 C CNN
+F 3 "" H 7200 3000 60 0000 C CNN
+ 5 7200 3000
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4850 2850 4950 2850
+Wire Wire Line
+ 4950 2850 4950 2900
+Connection ~ 5000 2900
+Wire Wire Line
+ 4850 3150 4950 3150
+Wire Wire Line
+ 4950 3150 4950 3100
+Connection ~ 5000 3100
+$Comp
+L SKY130mode scmode1
+U 1 1 686CC4AC
+P 8250 3200
+F 0 "scmode1" H 8250 3350 98 0000 C CNB
+F 1 "SKY130mode" H 8250 3100 118 0000 C CNB
+F 2 "" H 8250 3350 60 0001 C CNN
+F 3 "" H 8250 3350 60 0001 C CNN
+ 1 8250 3200
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/2_in_and.sub b/library/SubcircuitLibrary/SN54L99/2_in_and.sub
new file mode 100644
index 000000000..6c2a85281
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/2_in_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 2_in_and
+.subckt 2_in_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/2_in_and/2_in_and.cir
+.include CMOS_INVTR.sub
+.include NAND_2.sub
+
+x1 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_x1-pad4_ net-_u1-pad4_ NAND_2
+x2 net-_x1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad5_ CMOS_INVTR
+* s c m o d e
+* Control Statements
+
+.ends 2_in_and
diff --git a/library/SubcircuitLibrary/SN54L99/2_in_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/2_in_and_Previous_Values.xml
new file mode 100644
index 000000000..ecb007d93
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/2_in_and_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/3_in_and-cache.lib b/library/SubcircuitLibrary/SN54L99/3_in_and-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/3_in_and-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/3_in_and.cir b/library/SubcircuitLibrary/SN54L99/3_in_and.cir
new file mode 100644
index 000000000..d5cf8cd48
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/3_in_and.cir
@@ -0,0 +1,20 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/3_in_and/3_in_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 28 01:51:23 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC6 Net-_SC1-Pad1_ Net-_SC5-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC3 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC3-Pad3_ Net-_SC2-Pad2_ Net-_SC4-Pad3_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+SC5 Net-_SC4-Pad3_ Net-_SC5-Pad2_ Net-_SC3-Pad4_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+SC7 Net-_SC1-Pad1_ Net-_SC1-Pad1_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC8 Net-_SC1-Pad1_ Net-_SC1-Pad1_ Net-_SC3-Pad4_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+scmode1 SKY130mode
+U1 Net-_SC1-Pad2_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC3-Pad4_ Net-_SC5-Pad2_ Net-_SC1-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/3_in_and.cir.out b/library/SubcircuitLibrary/SN54L99/3_in_and.cir.out
new file mode 100644
index 000000000..91515569e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/3_in_and.cir.out
@@ -0,0 +1,23 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/3_in_and/3_in_and.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc6 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc2-pad2_ net-_sc4-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc5-pad2_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc1-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc1-pad1_ net-_sc1-pad1_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* u1 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad4_ net-_sc5-pad2_ net-_sc1-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/3_in_and.pro b/library/SubcircuitLibrary/SN54L99/3_in_and.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/3_in_and.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/3_in_and.sch b/library/SubcircuitLibrary/SN54L99/3_in_and.sch
new file mode 100644
index 000000000..413d03374
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/3_in_and.sch
@@ -0,0 +1,324 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 685EFB75
+P 4650 2000
+F 0 "SC1" H 4700 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4950 2087 50 0000 R CNN
+F 2 "" H 4650 500 50 0001 C CNN
+F 3 "" H 4650 2000 50 0001 C CNN
+ 1 4650 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 685EFBB1
+P 6200 2000
+F 0 "SC2" H 6250 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6500 2087 50 0000 R CNN
+F 2 "" H 6200 500 50 0001 C CNN
+F 3 "" H 6200 2000 50 0001 C CNN
+ 1 6200 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC6
+U 1 1 685EFC40
+P 7750 2000
+F 0 "SC6" H 7800 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 8050 2087 50 0000 R CNN
+F 2 "" H 7750 500 50 0001 C CNN
+F 3 "" H 7750 2000 50 0001 C CNN
+ 1 7750 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 685EFDF8
+P 6200 2950
+F 0 "SC3" H 6250 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6500 3037 50 0000 R CNN
+F 2 "" H 6200 1450 50 0001 C CNN
+F 3 "" H 6200 2950 50 0001 C CNN
+ 1 6200 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 685EFE69
+P 6200 3750
+F 0 "SC4" H 6250 4050 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6500 3837 50 0000 R CNN
+F 2 "" H 6200 2250 50 0001 C CNN
+F 3 "" H 6200 3750 50 0001 C CNN
+ 1 6200 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 685EFEFC
+P 6600 4450
+F 0 "SC5" H 6650 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6900 4537 50 0000 R CNN
+F 2 "" H 6600 2950 50 0001 C CNN
+F 3 "" H 6600 4450 50 0001 C CNN
+ 1 6600 4450
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC7
+U 1 1 685F0235
+P 8600 2000
+F 0 "SC7" H 8650 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 8900 2087 50 0000 R CNN
+F 2 "" H 8600 500 50 0001 C CNN
+F 3 "" H 8600 2000 50 0001 C CNN
+ 1 8600 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC8
+U 1 1 685F02AE
+P 8600 4500
+F 0 "SC8" H 8650 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 8900 4587 50 0000 R CNN
+F 2 "" H 8600 3000 50 0001 C CNN
+F 3 "" H 8600 4500 50 0001 C CNN
+ 1 8600 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 685F03F9
+P 10450 6050
+F 0 "scmode1" H 10450 6200 98 0000 C CNB
+F 1 "SKY130mode" H 10450 5950 118 0000 C CNB
+F 2 "" H 10450 6200 60 0001 C CNN
+F 3 "" H 10450 6200 60 0001 C CNN
+ 1 10450 6050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685F046F
+P 3800 2000
+F 0 "U1" H 3850 2100 30 0000 C CNN
+F 1 "PORT" H 3800 2000 30 0000 C CNN
+F 2 "" H 3800 2000 60 0000 C CNN
+F 3 "" H 3800 2000 60 0000 C CNN
+ 1 3800 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685F04F8
+P 5400 2000
+F 0 "U1" H 5450 2100 30 0000 C CNN
+F 1 "PORT" H 5400 2000 30 0000 C CNN
+F 2 "" H 5400 2000 60 0000 C CNN
+F 3 "" H 5400 2000 60 0000 C CNN
+ 2 5400 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685F05AF
+P 6950 2000
+F 0 "U1" H 7000 2100 30 0000 C CNN
+F 1 "PORT" H 6950 2000 30 0000 C CNN
+F 2 "" H 6950 2000 60 0000 C CNN
+F 3 "" H 6950 2000 60 0000 C CNN
+ 5 6950 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685F0660
+P 9350 2950
+F 0 "U1" H 9400 3050 30 0000 C CNN
+F 1 "PORT" H 9350 2950 30 0000 C CNN
+F 2 "" H 9350 2950 60 0000 C CNN
+F 3 "" H 9350 2950 60 0000 C CNN
+ 6 9350 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685F087C
+P 6150 1250
+F 0 "U1" H 6200 1350 30 0000 C CNN
+F 1 "PORT" H 6150 1250 30 0000 C CNN
+F 2 "" H 6150 1250 60 0000 C CNN
+F 3 "" H 6150 1250 60 0000 C CNN
+ 3 6150 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685F095F
+P 6150 5100
+F 0 "U1" H 6200 5200 30 0000 C CNN
+F 1 "PORT" H 6150 5100 30 0000 C CNN
+F 2 "" H 6150 5100 60 0000 C CNN
+F 3 "" H 6150 5100 60 0000 C CNN
+ 4 6150 5100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4850 1700 4850 1600
+Wire Wire Line
+ 4850 1600 8850 1600
+Wire Wire Line
+ 8800 1600 8800 1700
+Wire Wire Line
+ 6400 1250 6400 1700
+Connection ~ 6400 1600
+Wire Wire Line
+ 7950 1700 7950 1600
+Connection ~ 7950 1600
+Wire Wire Line
+ 4850 2300 4850 2350
+Wire Wire Line
+ 4850 2350 8800 2350
+Wire Wire Line
+ 8800 2300 8800 4200
+Wire Wire Line
+ 6400 2300 6400 2650
+Connection ~ 6400 2350
+Wire Wire Line
+ 7950 2300 7950 2350
+Connection ~ 7950 2350
+Wire Wire Line
+ 4750 2000 4950 2000
+Wire Wire Line
+ 4950 2000 4950 1600
+Connection ~ 4950 1600
+Wire Wire Line
+ 6300 2000 6500 2000
+Wire Wire Line
+ 6500 2000 6500 1600
+Connection ~ 6500 1600
+Wire Wire Line
+ 7850 2000 8050 2000
+Wire Wire Line
+ 8050 2000 8050 1600
+Connection ~ 8050 1600
+Wire Wire Line
+ 8700 2000 8850 2000
+Wire Wire Line
+ 8850 2000 8850 1600
+Connection ~ 8800 1600
+Wire Wire Line
+ 4350 2000 4050 2000
+Wire Wire Line
+ 5900 2000 5650 2000
+Wire Wire Line
+ 7450 2000 7200 2000
+Wire Wire Line
+ 8300 2000 8300 4500
+Wire Wire Line
+ 8300 2450 6400 2450
+Connection ~ 6400 2450
+Wire Wire Line
+ 5900 2950 4250 2950
+Wire Wire Line
+ 4250 2950 4250 2000
+Connection ~ 4250 2000
+Wire Wire Line
+ 5900 3750 5700 3750
+Wire Wire Line
+ 5700 3750 5700 2000
+Connection ~ 5700 2000
+Wire Wire Line
+ 6900 4450 7350 4450
+Wire Wire Line
+ 7350 4450 7350 2000
+Connection ~ 7350 2000
+Wire Wire Line
+ 6400 5100 6400 4750
+Wire Wire Line
+ 8700 4500 8900 4500
+Wire Wire Line
+ 8900 4500 8900 4900
+Wire Wire Line
+ 8900 4900 6350 4900
+Connection ~ 6400 4900
+Wire Wire Line
+ 8800 4800 8800 4900
+Connection ~ 8800 4900
+Wire Wire Line
+ 6500 4450 6350 4450
+Wire Wire Line
+ 6350 4450 6350 4900
+Wire Wire Line
+ 6400 4050 6400 4150
+Wire Wire Line
+ 6300 3750 7000 3750
+Wire Wire Line
+ 7000 2950 7000 4900
+Connection ~ 7000 4900
+Wire Wire Line
+ 6400 3250 6400 3450
+Wire Wire Line
+ 6300 2950 7000 2950
+Connection ~ 7000 3750
+Connection ~ 8800 2350
+Connection ~ 8300 2450
+Wire Wire Line
+ 9100 2950 8800 2950
+Connection ~ 8800 2950
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/3_in_and.sub b/library/SubcircuitLibrary/SN54L99/3_in_and.sub
new file mode 100644
index 000000000..be48d3260
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/3_in_and.sub
@@ -0,0 +1,17 @@
+* Subcircuit 3_in_and
+.subckt 3_in_and net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad4_ net-_sc5-pad2_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/3_in_and/3_in_and.cir
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc6 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc2-pad2_ net-_sc4-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc5-pad2_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc1-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc1-pad1_ net-_sc1-pad1_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends 3_in_and
diff --git a/library/SubcircuitLibrary/SN54L99/3_in_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/3_in_and_Previous_Values.xml
new file mode 100644
index 000000000..d3c2ae7ff
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/3_in_and_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=1 l=0.15
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/4_in_and-cache.lib b/library/SubcircuitLibrary/SN54L99/4_in_and-cache.lib
new file mode 100644
index 000000000..dc52f48f5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/4_in_and-cache.lib
@@ -0,0 +1,96 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 2_in_and
+#
+DEF 2_in_and X 0 40 Y Y 1 F N
+F0 "X" 50 0 60 H V C CNN
+F1 "2_in_and" 0 -250 60 H V C CNN
+F2 "" 750 -150 60 H I C CNN
+F3 "" 750 -150 60 H I C CNN
+DRAW
+A 50 0 206 760 -760 0 1 0 N 100 200 100 -200
+P 2 0 1 0 -200 200 100 200 N
+P 3 0 1 0 -200 200 -200 -200 100 -200 N
+X Vdd 1 -400 150 200 R 50 50 1 1 I
+X in1 2 -400 50 200 R 50 50 1 1 I
+X in2 3 -400 -50 200 R 50 50 1 1 I
+X Gnd 4 -400 -150 200 R 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 3_in_and
+#
+DEF 3_in_and X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "3_in_and" 50 -300 60 H V C CNN
+F2 "" 600 -150 60 H I C CNN
+F3 "" 600 -150 60 H I C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+P 2 0 1 0 -150 250 100 250 N
+P 2 0 1 0 150 250 100 250 N
+P 3 0 1 0 -150 250 -150 -250 150 -250 N
+X in1 1 -350 100 200 R 50 50 1 1 I
+X in2 2 -350 0 200 R 50 50 1 1 I
+X Vdd 3 -350 200 200 R 50 50 1 1 I
+X Gnd 4 -350 -200 200 R 50 50 1 1 I
+X in3 5 -350 -100 200 R 50 50 1 1 I
+X out 6 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/4_in_and.cir b/library/SubcircuitLibrary/SN54L99/4_in_and.cir
new file mode 100644
index 000000000..4e996a12a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/4_in_and.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/4_in_and/4_in_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Jul 8 12:53:37 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_X1-Pad6_ 3_in_and
+X2 Net-_U1-Pad1_ Net-_X1-Pad6_ Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad7_ 2_in_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/4_in_and.cir.out b/library/SubcircuitLibrary/SN54L99/4_in_and.cir.out
new file mode 100644
index 000000000..53ad1ee41
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/4_in_and.cir.out
@@ -0,0 +1,24 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/4_in_and/4_in_and.cir
+
+.include 3_in_and.sub
+.include 2_in_and.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_x1-pad6_ 3_in_and
+x2 net-_u1-pad1_ net-_x1-pad6_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad7_ 2_in_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/4_in_and.pro b/library/SubcircuitLibrary/SN54L99/4_in_and.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/4_in_and.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/4_in_and.sch b/library/SubcircuitLibrary/SN54L99/4_in_and.sch
new file mode 100644
index 000000000..db84ffe7b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/4_in_and.sch
@@ -0,0 +1,196 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_in_and X1
+U 1 1 686CC60C
+P 5250 2300
+F 0 "X1" H 5350 2300 60 0000 C CNN
+F 1 "3_in_and" H 5300 2000 60 0000 C CNN
+F 2 "" H 5850 2150 60 0001 C CNN
+F 3 "" H 5850 2150 60 0001 C CNN
+ 1 5250 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L 2_in_and X2
+U 1 1 686CC667
+P 6200 2350
+F 0 "X2" H 6250 2350 60 0000 C CNN
+F 1 "2_in_and" H 6200 2100 60 0000 C CNN
+F 2 "" H 6950 2200 60 0001 C CNN
+F 3 "" H 6950 2200 60 0001 C CNN
+ 1 6200 2350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5800 2150 5800 2200
+Wire Wire Line
+ 4750 2150 5800 2150
+Wire Wire Line
+ 4900 2150 4900 2100
+Wire Wire Line
+ 5800 2450 5800 2500
+Wire Wire Line
+ 4750 2450 5800 2450
+Wire Wire Line
+ 4900 2450 4900 2500
+Wire Wire Line
+ 5800 2400 5650 2400
+Wire Wire Line
+ 5650 2400 5650 2600
+Wire Wire Line
+ 5650 2600 4750 2600
+Wire Wire Line
+ 4900 2400 4750 2400
+Wire Wire Line
+ 4900 2300 4750 2300
+Wire Wire Line
+ 4900 2200 4750 2200
+Connection ~ 4900 2150
+Connection ~ 4900 2450
+$Comp
+L PORT U1
+U 1 1 686CC71D
+P 4500 2100
+F 0 "U1" H 4550 2200 30 0000 C CNN
+F 1 "PORT" H 4500 2100 30 0000 C CNN
+F 2 "" H 4500 2100 60 0000 C CNN
+F 3 "" H 4500 2100 60 0000 C CNN
+ 1 4500 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686CC7AC
+P 4500 2200
+F 0 "U1" H 4550 2300 30 0000 C CNN
+F 1 "PORT" H 4500 2200 30 0000 C CNN
+F 2 "" H 4500 2200 60 0000 C CNN
+F 3 "" H 4500 2200 60 0000 C CNN
+ 2 4500 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686CC80F
+P 4500 2300
+F 0 "U1" H 4550 2400 30 0000 C CNN
+F 1 "PORT" H 4500 2300 30 0000 C CNN
+F 2 "" H 4500 2300 60 0000 C CNN
+F 3 "" H 4500 2300 60 0000 C CNN
+ 3 4500 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686CC8BF
+P 4500 2400
+F 0 "U1" H 4550 2500 30 0000 C CNN
+F 1 "PORT" H 4500 2400 30 0000 C CNN
+F 2 "" H 4500 2400 60 0000 C CNN
+F 3 "" H 4500 2400 60 0000 C CNN
+ 4 4500 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686CC9C0
+P 4500 2500
+F 0 "U1" H 4550 2600 30 0000 C CNN
+F 1 "PORT" H 4500 2500 30 0000 C CNN
+F 2 "" H 4500 2500 60 0000 C CNN
+F 3 "" H 4500 2500 60 0000 C CNN
+ 5 4500 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686CC9F9
+P 4500 2600
+F 0 "U1" H 4550 2700 30 0000 C CNN
+F 1 "PORT" H 4500 2600 30 0000 C CNN
+F 2 "" H 4500 2600 60 0000 C CNN
+F 3 "" H 4500 2600 60 0000 C CNN
+ 6 4500 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686CCA50
+P 6900 2350
+F 0 "U1" H 6950 2450 30 0000 C CNN
+F 1 "PORT" H 6900 2350 30 0000 C CNN
+F 2 "" H 6900 2350 60 0000 C CNN
+F 3 "" H 6900 2350 60 0000 C CNN
+ 7 6900 2350
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4750 2150 4750 2100
+Wire Wire Line
+ 4750 2450 4750 2500
+$Comp
+L SKY130mode scmode1
+U 1 1 686CCB41
+P 7350 3350
+F 0 "scmode1" H 7350 3500 98 0000 C CNB
+F 1 "SKY130mode" H 7350 3250 118 0000 C CNB
+F 2 "" H 7350 3500 60 0001 C CNN
+F 3 "" H 7350 3500 60 0001 C CNN
+ 1 7350 3350
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/4_in_and.sub b/library/SubcircuitLibrary/SN54L99/4_in_and.sub
new file mode 100644
index 000000000..c7be023c0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/4_in_and.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_in_and
+.subckt 4_in_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/4_in_and/4_in_and.cir
+.include 3_in_and.sub
+.include 2_in_and.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_x1-pad6_ 3_in_and
+x2 net-_u1-pad1_ net-_x1-pad6_ net-_u1-pad6_ net-_u1-pad5_ net-_u1-pad7_ 2_in_and
+* s c m o d e
+* Control Statements
+
+.ends 4_in_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/4_in_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/4_in_and_Previous_Values.xml
new file mode 100644
index 000000000..2699e57a6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/4_in_and_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/3_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/2_in_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_Buf-cache.lib b/library/SubcircuitLibrary/SN54L99/CMOS_Buf-cache.lib
new file mode 100644
index 000000000..a4da279a5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_Buf-cache.lib
@@ -0,0 +1,74 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_Buf-rescue.lib b/library/SubcircuitLibrary/SN54L99/CMOS_Buf-rescue.lib
new file mode 100644
index 000000000..2e8cabd8d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_Buf-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR-RESCUE-CMOS_Buf
+#
+DEF CMOS_INVTR-RESCUE-CMOS_Buf X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR-RESCUE-CMOS_Buf" 100 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -450 250 500 0 N
+P 3 0 1 0 -450 250 -450 -250 500 0 N
+X IN 1 -650 0 200 R 50 50 1 1 I
+X VDD 2 -650 150 200 R 50 50 1 1 I
+X GND 3 -650 -150 200 R 50 50 1 1 I
+X OUT 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_Buf.bak b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.bak
new file mode 100644
index 000000000..18c8ff97d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.bak
@@ -0,0 +1,149 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CMOS_INVTR X1
+U 1 1 68655F03
+P 4950 3300
+F 0 "X1" H 4950 3300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5050 3050 60 0000 C CNN
+F 2 "" H 4950 3300 60 0001 C CNN
+F 3 "" H 4950 3300 60 0001 C CNN
+ 1 4950 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 68655F1A
+P 6500 3300
+F 0 "X2" H 6500 3300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6600 3050 60 0000 C CNN
+F 2 "" H 6500 3300 60 0001 C CNN
+F 3 "" H 6500 3300 60 0001 C CNN
+ 1 6500 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5750 3300 5850 3300
+Wire Wire Line
+ 4300 3150 4300 3050
+Wire Wire Line
+ 4200 3050 5850 3050
+Wire Wire Line
+ 5850 3050 5850 3150
+Wire Wire Line
+ 4300 3450 4300 3550
+Wire Wire Line
+ 4200 3550 5850 3550
+Wire Wire Line
+ 5850 3550 5850 3450
+$Comp
+L PORT U1
+U 1 1 68655FBD
+P 3950 3050
+F 0 "U1" H 4000 3150 30 0000 C CNN
+F 1 "PORT" H 3950 3050 30 0000 C CNN
+F 2 "" H 3950 3050 60 0000 C CNN
+F 3 "" H 3950 3050 60 0000 C CNN
+ 1 3950 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68655FF0
+P 4050 3300
+F 0 "U1" H 4100 3400 30 0000 C CNN
+F 1 "PORT" H 4050 3300 30 0000 C CNN
+F 2 "" H 4050 3300 60 0000 C CNN
+F 3 "" H 4050 3300 60 0000 C CNN
+ 3 4050 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68656163
+P 3950 3550
+F 0 "U1" H 4000 3650 30 0000 C CNN
+F 1 "PORT" H 3950 3550 30 0000 C CNN
+F 2 "" H 3950 3550 60 0000 C CNN
+F 3 "" H 3950 3550 60 0000 C CNN
+ 2 3950 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68656242
+P 7550 3300
+F 0 "U1" H 7600 3400 30 0000 C CNN
+F 1 "PORT" H 7550 3300 30 0000 C CNN
+F 2 "" H 7550 3300 60 0000 C CNN
+F 3 "" H 7550 3300 60 0000 C CNN
+ 4 7550 3300
+ -1 0 0 -1
+$EndComp
+Connection ~ 4300 3050
+Connection ~ 4300 3550
+$Comp
+L SKY130mode scmode1
+U 1 1 68656379
+P 7900 4200
+F 0 "scmode1" H 7900 4350 98 0000 C CNB
+F 1 "SKY130mode" H 7900 4100 118 0000 C CNB
+F 2 "" H 7900 4350 60 0001 C CNN
+F 3 "" H 7900 4350 60 0001 C CNN
+ 1 7900 4200
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_Buf.cir b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.cir
new file mode 100644
index 000000000..a1907752c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_Buf/CMOS_Buf.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jul 6 10:50:24 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+scmode1 SKY130mode
+X1 Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_X1-Pad4_ CMOS_INVTR
+X2 Net-_X1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad4_ CMOS_INVTR
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_Buf.cir.out b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.cir.out
new file mode 100644
index 000000000..c1aedf115
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.cir.out
@@ -0,0 +1,23 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_buf/cmos_buf.cir
+
+.include CMOS_INVTR.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+* s c m o d e
+x1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_x1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ CMOS_INVTR
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_Buf.pro b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.pro
new file mode 100644
index 000000000..78fa1002c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.pro
@@ -0,0 +1,74 @@
+update=Sun Jul 6 10:49:25 2025
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=CMOS_Buf-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_Buf.sch b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.sch
new file mode 100644
index 000000000..0cdb5a05c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:CMOS_Buf-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:CMOS_Buf-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L PORT U1
+U 1 1 68655FBD
+P 3950 3050
+F 0 "U1" H 4000 3150 30 0000 C CNN
+F 1 "PORT" H 3950 3050 30 0000 C CNN
+F 2 "" H 3950 3050 60 0000 C CNN
+F 3 "" H 3950 3050 60 0000 C CNN
+ 1 3950 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68655FF0
+P 4050 3300
+F 0 "U1" H 4100 3400 30 0000 C CNN
+F 1 "PORT" H 4050 3300 30 0000 C CNN
+F 2 "" H 4050 3300 60 0000 C CNN
+F 3 "" H 4050 3300 60 0000 C CNN
+ 3 4050 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68656163
+P 3950 3550
+F 0 "U1" H 4000 3650 30 0000 C CNN
+F 1 "PORT" H 3950 3550 30 0000 C CNN
+F 2 "" H 3950 3550 60 0000 C CNN
+F 3 "" H 3950 3550 60 0000 C CNN
+ 2 3950 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68656242
+P 7050 3300
+F 0 "U1" H 7100 3400 30 0000 C CNN
+F 1 "PORT" H 7050 3300 30 0000 C CNN
+F 2 "" H 7050 3300 60 0000 C CNN
+F 3 "" H 7050 3300 60 0000 C CNN
+ 4 7050 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68656379
+P 7900 4200
+F 0 "scmode1" H 7900 4350 98 0000 C CNB
+F 1 "SKY130mode" H 7900 4100 118 0000 C CNB
+F 2 "" H 7900 4350 60 0001 C CNN
+F 3 "" H 7900 4350 60 0001 C CNN
+ 1 7900 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 686A07F2
+P 4700 3300
+F 0 "X1" H 4700 3300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 4750 3100 60 0000 C CNN
+F 2 "" H 4700 3300 60 0001 C CNN
+F 3 "" H 4700 3300 60 0001 C CNN
+ 1 4700 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 686A0855
+P 6250 3300
+F 0 "X2" H 6250 3300 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6300 3100 60 0000 C CNN
+F 2 "" H 6250 3300 60 0001 C CNN
+F 3 "" H 6250 3300 60 0001 C CNN
+ 1 6250 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5250 3300 5850 3300
+Wire Wire Line
+ 4300 3050 4300 3200
+Wire Wire Line
+ 4200 3050 5850 3050
+Wire Wire Line
+ 5850 3050 5850 3200
+Wire Wire Line
+ 4300 3400 4300 3550
+Wire Wire Line
+ 5850 3550 4200 3550
+Wire Wire Line
+ 5850 3400 5850 3550
+Connection ~ 4300 3050
+Connection ~ 4300 3550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_Buf.sub b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.sub
new file mode 100644
index 000000000..8d50195f6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_Buf.sub
@@ -0,0 +1,17 @@
+* Subcircuit CMOS_Buf
+.subckt CMOS_Buf net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_buf/cmos_buf.cir
+.include CMOS_INVTR.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* s c m o d e
+x1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_x1-pad4_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad4_ CMOS_INVTR
+* Control Statements
+
+.ends CMOS_Buf
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_Buf_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/CMOS_Buf_Previous_Values.xml
new file mode 100644
index 000000000..b0e9c717d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_Buf_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_INVTR-cache.lib b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.cir b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.cir
new file mode 100644
index 000000000..d89b6087d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/CMOS_INVTR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 22:03:21 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.cir.out b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.cir.out
new file mode 100644
index 000000000..4058a1829
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.cir.out
@@ -0,0 +1,22 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.pro b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.sch b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.sch
new file mode 100644
index 000000000..aa7a7ee81
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.sch
@@ -0,0 +1,161 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 684B982F
+P 5350 2950
+F 0 "SC1" H 5400 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 3037 50 0000 R CNN
+F 2 "" H 5350 1450 50 0001 C CNN
+F 3 "" H 5350 2950 50 0001 C CNN
+ 1 5350 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684B9856
+P 5350 3800
+F 0 "SC2" H 5400 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5650 3887 50 0000 R CNN
+F 2 "" H 5350 2300 50 0001 C CNN
+F 3 "" H 5350 3800 50 0001 C CNN
+ 1 5350 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B98AD
+P 4550 3300
+F 0 "U1" H 4600 3400 30 0000 C CNN
+F 1 "PORT" H 4550 3300 30 0000 C CNN
+F 2 "" H 4550 3300 60 0000 C CNN
+F 3 "" H 4550 3300 60 0000 C CNN
+ 1 4550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B98D8
+P 6300 3350
+F 0 "U1" H 6350 3450 30 0000 C CNN
+F 1 "PORT" H 6300 3350 30 0000 C CNN
+F 2 "" H 6300 3350 60 0000 C CNN
+F 3 "" H 6300 3350 60 0000 C CNN
+ 4 6300 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B9935
+P 5300 4350
+F 0 "U1" H 5350 4450 30 0000 C CNN
+F 1 "PORT" H 5300 4350 30 0000 C CNN
+F 2 "" H 5300 4350 60 0000 C CNN
+F 3 "" H 5300 4350 60 0000 C CNN
+ 3 5300 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B999A
+P 5300 2350
+F 0 "U1" H 5350 2450 30 0000 C CNN
+F 1 "PORT" H 5300 2350 30 0000 C CNN
+F 2 "" H 5300 2350 60 0000 C CNN
+F 3 "" H 5300 2350 60 0000 C CNN
+ 2 5300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B99CD
+P 7950 3000
+F 0 "scmode1" H 7950 3150 98 0000 C CNB
+F 1 "SKY130mode" H 7950 2900 118 0000 C CNB
+F 2 "" H 7950 3150 60 0001 C CNN
+F 3 "" H 7950 3150 60 0001 C CNN
+ 1 7950 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 2650 5550 2350
+Wire Wire Line
+ 5450 2950 5600 2950
+Wire Wire Line
+ 5600 2950 5600 2550
+Wire Wire Line
+ 5600 2550 5550 2550
+Connection ~ 5550 2550
+Wire Wire Line
+ 5550 3250 5550 3500
+Wire Wire Line
+ 6050 3350 5550 3350
+Connection ~ 5550 3350
+Wire Wire Line
+ 5050 2950 5050 3800
+Wire Wire Line
+ 4800 3300 5050 3300
+Connection ~ 5050 3300
+Wire Wire Line
+ 5450 3800 5600 3800
+Wire Wire Line
+ 5600 3800 5600 4150
+Wire Wire Line
+ 5600 4150 5550 4150
+Wire Wire Line
+ 5550 4100 5550 4350
+Connection ~ 5550 4150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.sub b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.sub
new file mode 100644
index 000000000..9dff1ae3f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR.sub
@@ -0,0 +1,16 @@
+* Subcircuit CMOS_INVTR
+.subckt CMOS_INVTR net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends CMOS_INVTR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/CMOS_INVTR_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR_Previous_Values.xml
new file mode 100644
index 000000000..0fa71b2d4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/CMOS_INVTR_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/DS_blk-cache.lib b/library/SubcircuitLibrary/SN54L99/DS_blk-cache.lib
new file mode 100644
index 000000000..f32a82db2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/DS_blk-cache.lib
@@ -0,0 +1,147 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 2_in_and
+#
+DEF 2_in_and X 0 40 Y Y 1 F N
+F0 "X" 50 0 60 H V C CNN
+F1 "2_in_and" 0 -250 60 H V C CNN
+F2 "" 750 -150 60 H I C CNN
+F3 "" 750 -150 60 H I C CNN
+DRAW
+A 50 0 206 760 -760 0 1 0 N 100 200 100 -200
+P 2 0 1 0 -200 200 100 200 N
+P 3 0 1 0 -200 200 -200 -200 100 -200 N
+X Vdd 1 -400 150 200 R 50 50 1 1 I
+X in1 2 -400 50 200 R 50 50 1 1 I
+X in2 3 -400 -50 200 R 50 50 1 1 I
+X Gnd 4 -400 -150 200 R 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_Buf
+#
+DEF CMOS_Buf X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_Buf" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+P 2 0 1 0 -250 150 250 0 N
+P 3 0 1 0 -250 150 -250 -150 250 0 N
+X Vdd 1 -450 100 200 R 50 50 1 1 I
+X Gnd 2 -450 -100 200 R 50 50 1 1 I
+X in 3 -450 0 200 R 50 50 1 1 I
+X Out 4 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# D_FF
+#
+DEF D_FF X 0 40 Y Y 1 F N
+F0 "X" 100 100 60 H V C CNN
+F1 "D_FF" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -200 200 200 -150 0 1 0 N
+X D 1 -400 50 200 R 50 50 1 1 I
+X Clk 2 -400 -50 200 R 50 50 1 1 I
+X Vdd 3 0 400 200 D 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X Q 5 400 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NOR_2
+#
+DEF NOR_2 X 0 40 Y Y 1 F N
+F0 "X" 50 0 60 H V C CNN
+F1 "NOR_2" 0 -250 60 H V C CNN
+F2 "" -100 0 60 H I C CNN
+F3 "" -100 0 60 H I C CNN
+DRAW
+A -350 0 206 760 -760 0 1 0 N -300 200 -300 -200
+A -226 239 445 -996 -324 0 1 0 N -300 -200 150 0
+A -197 -174 388 1054 266 0 1 0 N -300 200 150 0
+C 200 0 50 0 1 0 N
+X in1 1 -350 50 200 R 50 50 1 1 I
+X Gnd 2 -400 -150 200 R 50 50 1 1 I
+X Vdd 3 -400 150 200 R 50 50 1 1 I
+X in2 4 -350 -50 200 R 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/DS_blk.bak b/library/SubcircuitLibrary/SN54L99/DS_blk.bak
new file mode 100644
index 000000000..367ca003a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/DS_blk.bak
@@ -0,0 +1,280 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DS_blk-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 2_in_and X1
+U 1 1 686E8DA4
+P 4450 2650
+F 0 "X1" H 4500 2650 60 0000 C CNN
+F 1 "2_in_and" H 4450 2400 60 0000 C CNN
+F 2 "" H 5200 2500 60 0001 C CNN
+F 3 "" H 5200 2500 60 0001 C CNN
+ 1 4450 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L 2_in_and X2
+U 1 1 686E8DC5
+P 4450 3500
+F 0 "X2" H 4500 3500 60 0000 C CNN
+F 1 "2_in_and" H 4450 3250 60 0000 C CNN
+F 2 "" H 5200 3350 60 0001 C CNN
+F 3 "" H 5200 3350 60 0001 C CNN
+ 1 4450 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_2 X3
+U 1 1 686E8DDE
+P 5750 3050
+F 0 "X3" H 5800 3050 60 0000 C CNN
+F 1 "NOR_2" H 5750 2800 60 0000 C CNN
+F 2 "" H 5650 3050 60 0001 C CNN
+F 3 "" H 5650 3050 60 0001 C CNN
+ 1 5750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X4
+U 1 1 686E8E0C
+P 7050 3100
+F 0 "X4" H 7150 3200 60 0000 C CNN
+F 1 "D_FF" H 7050 2900 60 0000 C CNN
+F 2 "" H 7050 3100 60 0001 C CNN
+F 3 "" H 7050 3100 60 0001 C CNN
+ 1 7050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686E8E39
+P 8550 4100
+F 0 "scmode1" H 8550 4250 98 0000 C CNB
+F 1 "SKY130mode" H 8550 4000 118 0000 C CNB
+F 2 "" H 8550 4250 60 0001 C CNN
+F 3 "" H 8550 4250 60 0001 C CNN
+ 1 8550 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E8E58
+P 3800 2600
+F 0 "U1" H 3850 2700 30 0000 C CNN
+F 1 "PORT" H 3800 2600 30 0000 C CNN
+F 2 "" H 3800 2600 60 0000 C CNN
+F 3 "" H 3800 2600 60 0000 C CNN
+ 1 3800 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E8F0F
+P 3800 2700
+F 0 "U1" H 3850 2800 30 0000 C CNN
+F 1 "PORT" H 3800 2700 30 0000 C CNN
+F 2 "" H 3800 2700 60 0000 C CNN
+F 3 "" H 3800 2700 60 0000 C CNN
+ 2 3800 2700
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E8F53
+P 3800 3450
+F 0 "U1" H 3850 3550 30 0000 C CNN
+F 1 "PORT" H 3800 3450 30 0000 C CNN
+F 2 "" H 3800 3450 60 0000 C CNN
+F 3 "" H 3800 3450 60 0000 C CNN
+ 3 3800 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E8F80
+P 3800 3550
+F 0 "U1" H 3850 3650 30 0000 C CNN
+F 1 "PORT" H 3800 3550 30 0000 C CNN
+F 2 "" H 3800 3550 60 0000 C CNN
+F 3 "" H 3800 3550 60 0000 C CNN
+ 4 3800 3550
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E901D
+P 6400 3150
+F 0 "U1" H 6450 3250 30 0000 C CNN
+F 1 "PORT" H 6400 3150 30 0000 C CNN
+F 2 "" H 6400 3150 60 0000 C CNN
+F 3 "" H 6400 3150 60 0000 C CNN
+ 5 6400 3150
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686E9099
+P 7700 3150
+F 0 "U1" H 7750 3250 30 0000 C CNN
+F 1 "PORT" H 7700 3150 30 0000 C CNN
+F 2 "" H 7700 3150 60 0000 C CNN
+F 3 "" H 7700 3150 60 0000 C CNN
+ 8 7700 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686E91B5
+P 7300 2400
+F 0 "U1" H 7350 2500 30 0000 C CNN
+F 1 "PORT" H 7300 2400 30 0000 C CNN
+F 2 "" H 7300 2400 60 0000 C CNN
+F 3 "" H 7300 2400 60 0000 C CNN
+ 6 7300 2400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686E922A
+P 7300 3550
+F 0 "U1" H 7350 3650 30 0000 C CNN
+F 1 "PORT" H 7300 3550 30 0000 C CNN
+F 2 "" H 7300 3550 60 0000 C CNN
+F 3 "" H 7300 3550 60 0000 C CNN
+ 7 7300 3550
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4900 2650 4900 3000
+Wire Wire Line
+ 4900 3000 5400 3000
+Wire Wire Line
+ 4900 3500 4900 3100
+Wire Wire Line
+ 4900 3100 5400 3100
+Wire Wire Line
+ 4050 2400 4050 2500
+Wire Wire Line
+ 4050 2400 7050 2400
+Wire Wire Line
+ 7050 2400 7050 2700
+Connection ~ 7050 2400
+Connection ~ 7050 3550
+Wire Wire Line
+ 4050 3650 4050 3800
+Wire Wire Line
+ 4050 3800 7050 3800
+Wire Wire Line
+ 7050 3800 7050 3450
+Wire Wire Line
+ 5350 2900 5350 2400
+Connection ~ 5350 2400
+Wire Wire Line
+ 5350 3200 5350 3800
+Connection ~ 5350 3800
+Wire Wire Line
+ 4050 3350 4050 3200
+Wire Wire Line
+ 4050 3200 5150 3200
+Wire Wire Line
+ 5150 3200 5150 2400
+Connection ~ 5150 2400
+Wire Wire Line
+ 4050 2800 4050 2950
+Wire Wire Line
+ 4050 2950 5200 2950
+Wire Wire Line
+ 5200 2950 5200 3800
+Connection ~ 5200 3800
+$Comp
+L CMOS_Buf X5
+U 1 1 686F47C1
+P 6350 2650
+F 0 "X5" H 6350 2650 60 0000 C CNN
+F 1 "CMOS_Buf" H 6350 2450 60 0000 C CNN
+F 2 "" H 6350 2650 60 0001 C CNN
+F 3 "" H 6350 2650 60 0001 C CNN
+ 1 6350 2650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6200 3050 6200 2900
+Wire Wire Line
+ 6200 2900 5800 2900
+Wire Wire Line
+ 5800 2900 5800 2650
+Wire Wire Line
+ 5800 2650 5900 2650
+Wire Wire Line
+ 6800 2650 6850 2650
+Wire Wire Line
+ 6850 2650 6850 2850
+Wire Wire Line
+ 6850 2850 6650 2850
+Wire Wire Line
+ 6650 2850 6650 3050
+Wire Wire Line
+ 5900 2550 5900 2400
+Connection ~ 5900 2400
+Wire Wire Line
+ 5900 2750 5900 2800
+Wire Wire Line
+ 5900 2800 6300 2800
+Wire Wire Line
+ 6300 2800 6300 3550
+Wire Wire Line
+ 6300 3550 7050 3550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/DS_blk.cir b/library/SubcircuitLibrary/SN54L99/DS_blk.cir
new file mode 100644
index 000000000..a033859ed
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/DS_blk.cir
@@ -0,0 +1,18 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/DS_blk/DS_blk.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jul 10 11:45:04 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad6_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad7_ Net-_X1-Pad5_ 2_in_and
+X2 Net-_U1-Pad6_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad7_ Net-_X2-Pad5_ 2_in_and
+X3 Net-_X1-Pad5_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_X2-Pad5_ Net-_X3-Pad5_ NOR_2
+X4 Net-_X3-Pad5_ Net-_X4-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ D_FF
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT
+X5 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_X5-Pad4_ CMOS_Buf
+X6 Net-_X5-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_X4-Pad2_ CMOS_INVTR
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/DS_blk.cir.out b/library/SubcircuitLibrary/SN54L99/DS_blk.cir.out
new file mode 100644
index 000000000..9cbba8aaf
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/DS_blk.cir.out
@@ -0,0 +1,31 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/ds_blk/ds_blk.cir
+
+.include D_FF.sub
+.include 2_in_and.sub
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+.include CMOS_Buf.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+x1 net-_u1-pad6_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad7_ net-_x1-pad5_ 2_in_and
+x2 net-_u1-pad6_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad7_ net-_x2-pad5_ 2_in_and
+x3 net-_x1-pad5_ net-_u1-pad7_ net-_u1-pad6_ net-_x2-pad5_ net-_x3-pad5_ NOR_2
+x4 net-_x3-pad5_ net-_x4-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ D_FF
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
+x5 net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x5-pad4_ CMOS_Buf
+x6 net-_x5-pad4_ net-_u1-pad6_ net-_u1-pad7_ net-_x4-pad2_ CMOS_INVTR
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/DS_blk.pro b/library/SubcircuitLibrary/SN54L99/DS_blk.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/DS_blk.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/DS_blk.sch b/library/SubcircuitLibrary/SN54L99/DS_blk.sch
new file mode 100644
index 000000000..b08a03928
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/DS_blk.sch
@@ -0,0 +1,293 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DS_blk-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 2_in_and X1
+U 1 1 686E8DA4
+P 4450 2650
+F 0 "X1" H 4500 2650 60 0000 C CNN
+F 1 "2_in_and" H 4450 2400 60 0000 C CNN
+F 2 "" H 5200 2500 60 0001 C CNN
+F 3 "" H 5200 2500 60 0001 C CNN
+ 1 4450 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L 2_in_and X2
+U 1 1 686E8DC5
+P 4450 3500
+F 0 "X2" H 4500 3500 60 0000 C CNN
+F 1 "2_in_and" H 4450 3250 60 0000 C CNN
+F 2 "" H 5200 3350 60 0001 C CNN
+F 3 "" H 5200 3350 60 0001 C CNN
+ 1 4450 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_2 X3
+U 1 1 686E8DDE
+P 5750 3050
+F 0 "X3" H 5800 3050 60 0000 C CNN
+F 1 "NOR_2" H 5750 2800 60 0000 C CNN
+F 2 "" H 5650 3050 60 0001 C CNN
+F 3 "" H 5650 3050 60 0001 C CNN
+ 1 5750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L D_FF X4
+U 1 1 686E8E0C
+P 7050 3100
+F 0 "X4" H 7150 3200 60 0000 C CNN
+F 1 "D_FF" H 7050 2900 60 0000 C CNN
+F 2 "" H 7050 3100 60 0001 C CNN
+F 3 "" H 7050 3100 60 0001 C CNN
+ 1 7050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686E8E39
+P 8550 4100
+F 0 "scmode1" H 8550 4250 98 0000 C CNB
+F 1 "SKY130mode" H 8550 4000 118 0000 C CNB
+F 2 "" H 8550 4250 60 0001 C CNN
+F 3 "" H 8550 4250 60 0001 C CNN
+ 1 8550 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E8E58
+P 3800 2600
+F 0 "U1" H 3850 2700 30 0000 C CNN
+F 1 "PORT" H 3800 2600 30 0000 C CNN
+F 2 "" H 3800 2600 60 0000 C CNN
+F 3 "" H 3800 2600 60 0000 C CNN
+ 1 3800 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E8F0F
+P 3800 2700
+F 0 "U1" H 3850 2800 30 0000 C CNN
+F 1 "PORT" H 3800 2700 30 0000 C CNN
+F 2 "" H 3800 2700 60 0000 C CNN
+F 3 "" H 3800 2700 60 0000 C CNN
+ 2 3800 2700
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E8F53
+P 3800 3450
+F 0 "U1" H 3850 3550 30 0000 C CNN
+F 1 "PORT" H 3800 3450 30 0000 C CNN
+F 2 "" H 3800 3450 60 0000 C CNN
+F 3 "" H 3800 3450 60 0000 C CNN
+ 3 3800 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E8F80
+P 3800 3550
+F 0 "U1" H 3850 3650 30 0000 C CNN
+F 1 "PORT" H 3800 3550 30 0000 C CNN
+F 2 "" H 3800 3550 60 0000 C CNN
+F 3 "" H 3800 3550 60 0000 C CNN
+ 4 3800 3550
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E901D
+P 5200 4200
+F 0 "U1" H 5250 4300 30 0000 C CNN
+F 1 "PORT" H 5200 4200 30 0000 C CNN
+F 2 "" H 5200 4200 60 0000 C CNN
+F 3 "" H 5200 4200 60 0000 C CNN
+ 5 5200 4200
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686E9099
+P 7700 3150
+F 0 "U1" H 7750 3250 30 0000 C CNN
+F 1 "PORT" H 7700 3150 30 0000 C CNN
+F 2 "" H 7700 3150 60 0000 C CNN
+F 3 "" H 7700 3150 60 0000 C CNN
+ 8 7700 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686E91B5
+P 7300 2400
+F 0 "U1" H 7350 2500 30 0000 C CNN
+F 1 "PORT" H 7300 2400 30 0000 C CNN
+F 2 "" H 7300 2400 60 0000 C CNN
+F 3 "" H 7300 2400 60 0000 C CNN
+ 6 7300 2400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686E922A
+P 7300 3550
+F 0 "U1" H 7350 3650 30 0000 C CNN
+F 1 "PORT" H 7300 3550 30 0000 C CNN
+F 2 "" H 7300 3550 60 0000 C CNN
+F 3 "" H 7300 3550 60 0000 C CNN
+ 7 7300 3550
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4900 2650 4900 3000
+Wire Wire Line
+ 4900 3000 5400 3000
+Wire Wire Line
+ 4900 3500 4900 3100
+Wire Wire Line
+ 4900 3100 5400 3100
+Wire Wire Line
+ 4050 2400 4050 2500
+Wire Wire Line
+ 4050 2400 7050 2400
+Wire Wire Line
+ 7050 2400 7050 2700
+Connection ~ 7050 2400
+Connection ~ 7050 3550
+Wire Wire Line
+ 4050 3650 4050 3800
+Wire Wire Line
+ 4050 3800 7050 3800
+Wire Wire Line
+ 7050 3800 7050 3450
+Wire Wire Line
+ 5350 2900 5350 2400
+Connection ~ 5350 2400
+Wire Wire Line
+ 5350 3200 5350 3800
+Connection ~ 5350 3800
+Wire Wire Line
+ 4050 3350 4050 3200
+Wire Wire Line
+ 4050 3200 5150 3200
+Wire Wire Line
+ 5150 3200 5150 2400
+Connection ~ 5150 2400
+Wire Wire Line
+ 4050 2800 4050 2950
+Wire Wire Line
+ 4050 2950 5200 2950
+Wire Wire Line
+ 5200 2950 5200 3800
+Connection ~ 5200 3800
+Wire Wire Line
+ 6200 3050 6650 3050
+$Comp
+L CMOS_Buf X5
+U 1 1 686F5D94
+P 5900 4200
+F 0 "X5" H 5900 4200 60 0000 C CNN
+F 1 "CMOS_Buf" H 5900 4000 60 0000 C CNN
+F 2 "" H 5900 4200 60 0001 C CNN
+F 3 "" H 5900 4200 60 0001 C CNN
+ 1 5900 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X6
+U 1 1 686F5DD5
+P 6750 4200
+F 0 "X6" H 6750 4200 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6800 4000 60 0000 C CNN
+F 2 "" H 6750 4200 60 0001 C CNN
+F 3 "" H 6750 4200 60 0001 C CNN
+ 1 6750 4200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7300 4200 7300 3850
+Wire Wire Line
+ 7300 3850 6650 3850
+Wire Wire Line
+ 6650 3850 6650 3150
+Wire Wire Line
+ 5450 4100 5450 4000
+Wire Wire Line
+ 5450 4000 6350 4000
+Wire Wire Line
+ 6350 2400 6350 4100
+Connection ~ 6350 2400
+Connection ~ 6350 4000
+Wire Wire Line
+ 6350 4300 6350 4400
+Wire Wire Line
+ 5450 4400 7550 4400
+Wire Wire Line
+ 7550 4400 7550 3750
+Wire Wire Line
+ 7550 3750 7050 3750
+Wire Wire Line
+ 7050 3750 7050 3550
+Wire Wire Line
+ 5450 4300 5450 4400
+Connection ~ 6350 4400
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/DS_blk.sub b/library/SubcircuitLibrary/SN54L99/DS_blk.sub
new file mode 100644
index 000000000..6fe4576b5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/DS_blk.sub
@@ -0,0 +1,25 @@
+* Subcircuit DS_blk
+.subckt DS_blk net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/ds_blk/ds_blk.cir
+.include D_FF.sub
+.include 2_in_and.sub
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+.include CMOS_Buf.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+x1 net-_u1-pad6_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad7_ net-_x1-pad5_ 2_in_and
+x2 net-_u1-pad6_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad7_ net-_x2-pad5_ 2_in_and
+x3 net-_x1-pad5_ net-_u1-pad7_ net-_u1-pad6_ net-_x2-pad5_ net-_x3-pad5_ NOR_2
+x4 net-_x3-pad5_ net-_x4-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ D_FF
+* s c m o d e
+x5 net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad5_ net-_x5-pad4_ CMOS_Buf
+x6 net-_x5-pad4_ net-_u1-pad6_ net-_u1-pad7_ net-_x4-pad2_ CMOS_INVTR
+* Control Statements
+
+.ends DS_blk
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/DS_blk_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/DS_blk_Previous_Values.xml
new file mode 100644
index 000000000..d06329f5a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/DS_blk_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/2_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/2_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_FF/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_Buf/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/D_FF-cache.lib b/library/SubcircuitLibrary/SN54L99/D_FF-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/D_FF-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/D_FF.bak b/library/SubcircuitLibrary/SN54L99/D_FF.bak
new file mode 100644
index 000000000..61b02ff48
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/D_FF.bak
@@ -0,0 +1,246 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode?
+U 1 1 685A3E76
+P 9400 3200
+F 0 "scmode?" H 9400 3350 98 0000 C CNB
+F 1 "SKY130mode" H 9400 3100 118 0000 C CNB
+F 2 "" H 9400 3350 60 0001 C CNN
+F 3 "" H 9400 3350 60 0001 C CNN
+ 1 9400 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC?
+U 1 1 685A3EBD
+P 4000 3300
+F 0 "SC?" H 4050 3600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 3387 50 0000 R CNN
+F 2 "" H 4000 1800 50 0001 C CNN
+F 3 "" H 4000 3300 50 0001 C CNN
+ 1 4000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3EFC
+P 4000 4100
+F 0 "SC?" H 4050 4400 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4187 50 0000 R CNN
+F 2 "" H 4000 2600 50 0001 C CNN
+F 3 "" H 4000 4100 50 0001 C CNN
+ 1 4000 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3F47
+P 4000 4900
+F 0 "SC?" H 4050 5200 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4987 50 0000 R CNN
+F 2 "" H 4000 3400 50 0001 C CNN
+F 3 "" H 4000 4900 50 0001 C CNN
+ 1 4000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC?
+U 1 1 685A3F7A
+P 4950 3700
+F 0 "SC?" H 5000 4000 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5250 3787 50 0000 R CNN
+F 2 "" H 4950 2200 50 0001 C CNN
+F 3 "" H 4950 3700 50 0001 C CNN
+ 1 4950 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3FCF
+P 4950 4500
+F 0 "SC?" H 5000 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5250 4587 50 0000 R CNN
+F 2 "" H 4950 3000 50 0001 C CNN
+F 3 "" H 4950 4500 50 0001 C CNN
+ 1 4950 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 1 1 685A401A
+P 3250 3550
+F 0 "U?" H 3300 3650 30 0000 C CNN
+F 1 "PORT" H 3250 3550 30 0000 C CNN
+F 2 "" H 3250 3550 60 0000 C CNN
+F 3 "" H 3250 3550 60 0000 C CNN
+ 1 3250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 2 1 685A40FF
+P 3250 4100
+F 0 "U?" H 3300 4200 30 0000 C CNN
+F 1 "PORT" H 3250 4100 30 0000 C CNN
+F 2 "" H 3250 4100 60 0000 C CNN
+F 3 "" H 3250 4100 60 0000 C CNN
+ 2 3250 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 3 1 685A4132
+P 3950 2750
+F 0 "U?" H 4000 2850 30 0000 C CNN
+F 1 "PORT" H 3950 2750 30 0000 C CNN
+F 2 "" H 3950 2750 60 0000 C CNN
+F 3 "" H 3950 2750 60 0000 C CNN
+ 3 3950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 4 1 685A41B1
+P 3950 5350
+F 0 "U?" H 4000 5450 30 0000 C CNN
+F 1 "PORT" H 3950 5350 30 0000 C CNN
+F 2 "" H 3950 5350 60 0000 C CNN
+F 3 "" H 3950 5350 60 0000 C CNN
+ 4 3950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 5 1 685A4206
+P 5700 4100
+F 0 "U?" H 5750 4200 30 0000 C CNN
+F 1 "PORT" H 5700 4100 30 0000 C CNN
+F 2 "" H 5700 4100 60 0000 C CNN
+F 3 "" H 5700 4100 60 0000 C CNN
+ 5 5700 4100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4200 3600 4200 3800
+Wire Wire Line
+ 3700 3300 3600 3300
+Wire Wire Line
+ 3600 3300 3600 4900
+Wire Wire Line
+ 3600 4900 3700 4900
+Wire Wire Line
+ 3500 3550 3600 3550
+Connection ~ 3600 3550
+Wire Wire Line
+ 3500 4100 3700 4100
+Wire Wire Line
+ 4200 2750 4200 3000
+Wire Wire Line
+ 4650 3700 4200 3700
+Connection ~ 4200 3700
+Wire Wire Line
+ 4200 4400 4200 4600
+Wire Wire Line
+ 4650 4500 4200 4500
+Connection ~ 4200 4500
+Wire Wire Line
+ 5150 4000 5150 4200
+Wire Wire Line
+ 5450 4100 5150 4100
+Connection ~ 5150 4100
+Wire Wire Line
+ 4200 5200 4200 5350
+Wire Wire Line
+ 4100 4900 4250 4900
+Wire Wire Line
+ 4250 4900 4250 5250
+Wire Wire Line
+ 4200 5250 5150 5250
+Connection ~ 4200 5250
+Wire Wire Line
+ 5150 5250 5150 4800
+Connection ~ 4250 5250
+Wire Wire Line
+ 5050 4500 5200 4500
+Wire Wire Line
+ 5200 4500 5200 4850
+Wire Wire Line
+ 5200 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 4100 4100 4250 4100
+Wire Wire Line
+ 4250 4100 4250 4500
+Connection ~ 4250 4500
+Wire Wire Line
+ 4100 3300 4250 3300
+Wire Wire Line
+ 4250 3300 4250 2950
+Wire Wire Line
+ 4200 2950 5150 2950
+Connection ~ 4200 2950
+Wire Wire Line
+ 5150 2950 5150 3400
+Connection ~ 4250 2950
+Wire Wire Line
+ 5050 3700 5200 3700
+Wire Wire Line
+ 5200 3700 5200 3350
+Wire Wire Line
+ 5200 3350 5150 3350
+Connection ~ 5150 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/D_FF.cir b/library/SubcircuitLibrary/SN54L99/D_FF.cir
new file mode 100644
index 000000000..7d45c3cd5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/D_FF.cir
@@ -0,0 +1,17 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_FF/D_FF.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jul 6 10:25:49 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+scmode1 SKY130mode
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+SC3 Net-_SC2-Pad3_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC4-Pad1_ Net-_SC1-Pad1_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC5 Net-_SC4-Pad1_ Net-_SC2-Pad3_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC3-Pad3_ Net-_SC4-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/D_FF.cir.out b/library/SubcircuitLibrary/SN54L99/D_FF.cir.out
new file mode 100644
index 000000000..9d076c7f0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/D_FF.cir.out
@@ -0,0 +1,25 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/d_ff/d_ff.cir
+
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+* s c m o d e
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc2-pad3_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc4-pad1_ net-_sc2-pad3_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc4-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/D_FF.pro b/library/SubcircuitLibrary/SN54L99/D_FF.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/D_FF.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/D_FF.sch b/library/SubcircuitLibrary/SN54L99/D_FF.sch
new file mode 100644
index 000000000..722069493
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/D_FF.sch
@@ -0,0 +1,246 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 685A3E76
+P 9400 3200
+F 0 "scmode1" H 9400 3350 98 0000 C CNB
+F 1 "SKY130mode" H 9400 3100 118 0000 C CNB
+F 2 "" H 9400 3350 60 0001 C CNN
+F 3 "" H 9400 3350 60 0001 C CNN
+ 1 9400 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 685A3EBD
+P 4000 3300
+F 0 "SC1" H 4050 3600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 3387 50 0000 R CNN
+F 2 "" H 4000 1800 50 0001 C CNN
+F 3 "" H 4000 3300 50 0001 C CNN
+ 1 4000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 685A3EFC
+P 4000 4100
+F 0 "SC2" H 4050 4400 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4187 50 0000 R CNN
+F 2 "" H 4000 2600 50 0001 C CNN
+F 3 "" H 4000 4100 50 0001 C CNN
+ 1 4000 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 685A3F47
+P 4000 4900
+F 0 "SC3" H 4050 5200 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4987 50 0000 R CNN
+F 2 "" H 4000 3400 50 0001 C CNN
+F 3 "" H 4000 4900 50 0001 C CNN
+ 1 4000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 685A3F7A
+P 4950 3700
+F 0 "SC4" H 5000 4000 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5250 3787 50 0000 R CNN
+F 2 "" H 4950 2200 50 0001 C CNN
+F 3 "" H 4950 3700 50 0001 C CNN
+ 1 4950 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 685A3FCF
+P 4950 4500
+F 0 "SC5" H 5000 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5250 4587 50 0000 R CNN
+F 2 "" H 4950 3000 50 0001 C CNN
+F 3 "" H 4950 4500 50 0001 C CNN
+ 1 4950 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A401A
+P 3250 3550
+F 0 "U1" H 3300 3650 30 0000 C CNN
+F 1 "PORT" H 3250 3550 30 0000 C CNN
+F 2 "" H 3250 3550 60 0000 C CNN
+F 3 "" H 3250 3550 60 0000 C CNN
+ 1 3250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685A40FF
+P 3250 4100
+F 0 "U1" H 3300 4200 30 0000 C CNN
+F 1 "PORT" H 3250 4100 30 0000 C CNN
+F 2 "" H 3250 4100 60 0000 C CNN
+F 3 "" H 3250 4100 60 0000 C CNN
+ 2 3250 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685A4132
+P 3950 2750
+F 0 "U1" H 4000 2850 30 0000 C CNN
+F 1 "PORT" H 3950 2750 30 0000 C CNN
+F 2 "" H 3950 2750 60 0000 C CNN
+F 3 "" H 3950 2750 60 0000 C CNN
+ 3 3950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A41B1
+P 3950 5350
+F 0 "U1" H 4000 5450 30 0000 C CNN
+F 1 "PORT" H 3950 5350 30 0000 C CNN
+F 2 "" H 3950 5350 60 0000 C CNN
+F 3 "" H 3950 5350 60 0000 C CNN
+ 4 3950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685A4206
+P 5700 4100
+F 0 "U1" H 5750 4200 30 0000 C CNN
+F 1 "PORT" H 5700 4100 30 0000 C CNN
+F 2 "" H 5700 4100 60 0000 C CNN
+F 3 "" H 5700 4100 60 0000 C CNN
+ 5 5700 4100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4200 3600 4200 3800
+Wire Wire Line
+ 3700 3300 3600 3300
+Wire Wire Line
+ 3600 3300 3600 4900
+Wire Wire Line
+ 3600 4900 3700 4900
+Wire Wire Line
+ 3500 3550 3600 3550
+Connection ~ 3600 3550
+Wire Wire Line
+ 3500 4100 3700 4100
+Wire Wire Line
+ 4200 2750 4200 3000
+Wire Wire Line
+ 4650 3700 4200 3700
+Connection ~ 4200 3700
+Wire Wire Line
+ 4200 4400 4200 4600
+Wire Wire Line
+ 4650 4500 4200 4500
+Connection ~ 4200 4500
+Wire Wire Line
+ 5150 4000 5150 4200
+Wire Wire Line
+ 5450 4100 5150 4100
+Connection ~ 5150 4100
+Wire Wire Line
+ 4200 5200 4200 5350
+Wire Wire Line
+ 4100 4900 4250 4900
+Wire Wire Line
+ 4250 4900 4250 5250
+Wire Wire Line
+ 4200 5250 5150 5250
+Connection ~ 4200 5250
+Wire Wire Line
+ 5150 5250 5150 4800
+Connection ~ 4250 5250
+Wire Wire Line
+ 5050 4500 5200 4500
+Wire Wire Line
+ 5200 4500 5200 4850
+Wire Wire Line
+ 5200 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 4100 4100 4250 4100
+Wire Wire Line
+ 4250 4100 4250 4500
+Connection ~ 4250 4500
+Wire Wire Line
+ 4100 3300 4250 3300
+Wire Wire Line
+ 4250 3300 4250 2950
+Wire Wire Line
+ 4200 2950 5150 2950
+Connection ~ 4200 2950
+Wire Wire Line
+ 5150 2950 5150 3400
+Connection ~ 4250 2950
+Wire Wire Line
+ 5050 3700 5200 3700
+Wire Wire Line
+ 5200 3700 5200 3350
+Wire Wire Line
+ 5200 3350 5150 3350
+Connection ~ 5150 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/D_FF.sub b/library/SubcircuitLibrary/SN54L99/D_FF.sub
new file mode 100644
index 000000000..d686ca626
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/D_FF.sub
@@ -0,0 +1,19 @@
+* Subcircuit D_FF
+.subckt D_FF net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc4-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/d_ff/d_ff.cir
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+* s c m o d e
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc2-pad3_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc4-pad1_ net-_sc2-pad3_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends D_FF
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/D_FF_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/D_FF_Previous_Values.xml
new file mode 100644
index 000000000..87f2534ab
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/D_FF_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_2-cache.lib b/library/SubcircuitLibrary/SN54L99/NAND_2-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_2-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_2.bak b/library/SubcircuitLibrary/SN54L99/NAND_2.bak
new file mode 100644
index 000000000..ad9819396
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_2.bak
@@ -0,0 +1,221 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684AF0E9
+P 4750 2050
+F 0 "SC2" H 4800 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5050 2137 50 0000 R CNN
+F 2 "" H 4750 550 50 0001 C CNN
+F 3 "" H 4750 2050 50 0001 C CNN
+ 1 4750 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF14C
+P 5150 2750
+F 0 "SC3" H 5200 3050 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 2837 50 0000 R CNN
+F 2 "" H 5150 1250 50 0001 C CNN
+F 3 "" H 5150 2750 50 0001 C CNN
+ 1 5150 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF1CF
+P 4200 3600
+F 0 "SC1" H 4250 3900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4500 3687 50 0000 R CNN
+F 2 "" H 4200 2100 50 0001 C CNN
+F 3 "" H 4200 3600 50 0001 C CNN
+ 1 4200 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684AF20C
+P 5550 3600
+F 0 "SC4" H 5600 3900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5850 3687 50 0000 R CNN
+F 2 "" H 5550 2100 50 0001 C CNN
+F 3 "" H 5550 3600 50 0001 C CNN
+ 1 5550 3600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF271
+P 4650 1550
+F 0 "U1" H 4700 1650 30 0000 C CNN
+F 1 "PORT" H 4650 1550 30 0000 C CNN
+F 2 "" H 4650 1550 60 0000 C CNN
+F 3 "" H 4650 1550 60 0000 C CNN
+ 3 4650 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF336
+P 3550 2650
+F 0 "U1" H 3600 2750 30 0000 C CNN
+F 1 "PORT" H 3550 2650 30 0000 C CNN
+F 2 "" H 3550 2650 60 0000 C CNN
+F 3 "" H 3550 2650 60 0000 C CNN
+ 1 3550 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AF413
+P 6200 2750
+F 0 "U1" H 6250 2850 30 0000 C CNN
+F 1 "PORT" H 6200 2750 30 0000 C CNN
+F 2 "" H 6200 2750 60 0000 C CNN
+F 3 "" H 6200 2750 60 0000 C CNN
+ 4 6200 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF82C
+P 6200 3150
+F 0 "U1" H 6250 3250 30 0000 C CNN
+F 1 "PORT" H 6200 3150 30 0000 C CNN
+F 2 "" H 6200 3150 60 0000 C CNN
+F 3 "" H 6200 3150 60 0000 C CNN
+ 5 6200 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF895
+P 4550 4050
+F 0 "U1" H 4600 4150 30 0000 C CNN
+F 1 "PORT" H 4550 4050 30 0000 C CNN
+F 2 "" H 4550 4050 60 0000 C CNN
+F 3 "" H 4550 4050 60 0000 C CNN
+ 2 4550 4050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 3900 5350 3900
+Wire Wire Line
+ 4800 4050 4800 3900
+Connection ~ 4800 3900
+Wire Wire Line
+ 4300 3600 4450 3600
+Wire Wire Line
+ 4450 3600 4450 3900
+Connection ~ 4450 3900
+Wire Wire Line
+ 5450 3600 5300 3600
+Wire Wire Line
+ 5300 3600 5300 3900
+Connection ~ 5300 3900
+Wire Wire Line
+ 4400 3300 5350 3300
+Wire Wire Line
+ 4950 3050 4950 3300
+Connection ~ 4950 3300
+Wire Wire Line
+ 5950 3150 4950 3150
+Connection ~ 4950 3150
+Wire Wire Line
+ 5450 2750 5950 2750
+Wire Wire Line
+ 5850 2750 5850 3600
+Wire Wire Line
+ 5050 2750 4900 2750
+Wire Wire Line
+ 4900 2750 4900 2400
+Wire Wire Line
+ 4900 2400 4950 2400
+Wire Wire Line
+ 4950 2350 4950 2450
+Connection ~ 4950 2400
+Wire Wire Line
+ 4450 2050 3900 2050
+Wire Wire Line
+ 3900 2050 3900 3600
+Wire Wire Line
+ 3800 2650 3900 2650
+Connection ~ 3900 2650
+Connection ~ 5850 2750
+Wire Wire Line
+ 4850 2050 5000 2050
+Wire Wire Line
+ 5000 2050 5000 1650
+Wire Wire Line
+ 5000 1650 4950 1650
+Wire Wire Line
+ 4950 1550 4950 1750
+Wire Wire Line
+ 4900 1550 4950 1550
+Connection ~ 4950 1650
+$Comp
+L SKY130mode scmode1
+U 1 1 684AFD6B
+P 7350 2150
+F 0 "scmode1" H 7350 2300 98 0000 C CNB
+F 1 "SKY130mode" H 7350 2050 118 0000 C CNB
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2150
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_2.cir b/library/SubcircuitLibrary/SN54L99/NAND_2.cir
new file mode 100644
index 000000000..f3da72301
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_2.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/NAND_2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jul 6 17:51:58 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC1-Pad3_ Net-_SC3-Pad2_ Net-_SC4-Pad3_ Net-_SC4-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC4-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ Net-_SC3-Pad2_ PORT
+scmode1 SKY130mode
+SC3 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_2.cir.out b/library/SubcircuitLibrary/SN54L99/NAND_2.cir.out
new file mode 100644
index 000000000..15401b956
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_2.cir.out
@@ -0,0 +1,18 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_2/nand_2.cir
+
+
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad3_ net-_sc3-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc4-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ net-_sc3-pad2_ port
+* s c m o d e
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_2.pro b/library/SubcircuitLibrary/SN54L99/NAND_2.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_2.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_2.sch b/library/SubcircuitLibrary/SN54L99/NAND_2.sch
new file mode 100644
index 000000000..ebef1d4c6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_2.sch
@@ -0,0 +1,222 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:NAND_2-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684AF0E9
+P 4200 2050
+F 0 "SC2" H 4250 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4500 2137 50 0000 R CNN
+F 2 "" H 4200 550 50 0001 C CNN
+F 3 "" H 4200 2050 50 0001 C CNN
+ 1 4200 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF1CF
+P 4450 2850
+F 0 "SC1" H 4500 3150 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4750 2937 50 0000 R CNN
+F 2 "" H 4450 1350 50 0001 C CNN
+F 3 "" H 4450 2850 50 0001 C CNN
+ 1 4450 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684AF20C
+P 4850 3550
+F 0 "SC4" H 4900 3850 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5150 3637 50 0000 R CNN
+F 2 "" H 4850 2050 50 0001 C CNN
+F 3 "" H 4850 3550 50 0001 C CNN
+ 1 4850 3550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF271
+P 4350 1550
+F 0 "U1" H 4400 1650 30 0000 C CNN
+F 1 "PORT" H 4350 1550 30 0000 C CNN
+F 2 "" H 4350 1550 60 0000 C CNN
+F 3 "" H 4350 1550 60 0000 C CNN
+ 3 4350 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF336
+P 3550 2650
+F 0 "U1" H 3600 2750 30 0000 C CNN
+F 1 "PORT" H 3550 2650 30 0000 C CNN
+F 2 "" H 3550 2650 60 0000 C CNN
+F 3 "" H 3550 2650 60 0000 C CNN
+ 1 3550 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AF413
+P 5750 2450
+F 0 "U1" H 5800 2550 30 0000 C CNN
+F 1 "PORT" H 5750 2450 30 0000 C CNN
+F 2 "" H 5750 2450 60 0000 C CNN
+F 3 "" H 5750 2450 60 0000 C CNN
+ 4 5750 2450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF82C
+P 5750 3300
+F 0 "U1" H 5800 3400 30 0000 C CNN
+F 1 "PORT" H 5750 3300 30 0000 C CNN
+F 2 "" H 5750 3300 60 0000 C CNN
+F 3 "" H 5750 3300 60 0000 C CNN
+ 5 5750 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF895
+P 4400 4000
+F 0 "U1" H 4450 4100 30 0000 C CNN
+F 1 "PORT" H 4400 4000 30 0000 C CNN
+F 2 "" H 4400 4000 60 0000 C CNN
+F 3 "" H 4400 4000 60 0000 C CNN
+ 2 4400 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684AFD6B
+P 7350 2150
+F 0 "scmode1" H 7350 2300 98 0000 C CNB
+F 1 "SKY130mode" H 7350 2050 118 0000 C CNB
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684CF41D
+P 5000 2050
+F 0 "SC3" H 5050 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5300 2137 50 0000 R CNN
+F 2 "" H 5000 550 50 0001 C CNN
+F 3 "" H 5000 2050 50 0001 C CNN
+ 1 5000 2050
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 1750 4800 1750
+Wire Wire Line
+ 4600 1550 4600 1750
+Connection ~ 4600 1750
+Wire Wire Line
+ 4300 2050 4450 2050
+Wire Wire Line
+ 4450 2050 4450 1750
+Connection ~ 4450 1750
+Wire Wire Line
+ 4900 2050 4750 2050
+Wire Wire Line
+ 4750 2050 4750 1750
+Connection ~ 4750 1750
+Wire Wire Line
+ 4400 2350 4800 2350
+Wire Wire Line
+ 4650 2550 4650 2350
+Connection ~ 4650 2350
+Wire Wire Line
+ 5500 2450 4650 2450
+Connection ~ 4650 2450
+Wire Wire Line
+ 3900 2050 3900 2850
+Wire Wire Line
+ 3900 2850 4150 2850
+Wire Wire Line
+ 3800 2650 3900 2650
+Connection ~ 3900 2650
+Wire Wire Line
+ 5300 2050 5300 3550
+Wire Wire Line
+ 5300 3550 5150 3550
+Wire Wire Line
+ 5500 3300 5300 3300
+Connection ~ 5300 3300
+Wire Wire Line
+ 4550 2850 4700 2850
+Wire Wire Line
+ 4700 2850 4700 3200
+Wire Wire Line
+ 4700 3200 4650 3200
+Wire Wire Line
+ 4650 3150 4650 3250
+Connection ~ 4650 3200
+Wire Wire Line
+ 4650 3850 4650 4000
+Wire Wire Line
+ 4750 3550 4600 3550
+Wire Wire Line
+ 4600 3550 4600 3900
+Wire Wire Line
+ 4600 3900 4650 3900
+Connection ~ 4650 3900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_2.sub b/library/SubcircuitLibrary/SN54L99/NAND_2.sub
new file mode 100644
index 000000000..aa6beac0d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_2.sub
@@ -0,0 +1,12 @@
+* Subcircuit NAND_2
+.subckt NAND_2 net-_sc1-pad2_ net-_sc4-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ net-_sc3-pad2_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_2/nand_2.cir
+
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad3_ net-_sc3-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+* Control Statements
+
+.ends NAND_2
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_2_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/NAND_2_Previous_Values.xml
new file mode 100644
index 000000000..066d43a60
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_2_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_3-cache.lib b/library/SubcircuitLibrary/SN54L99/NAND_3-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_3-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_3.bak b/library/SubcircuitLibrary/SN54L99/NAND_3.bak
new file mode 100644
index 000000000..d9890c5d1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_3.bak
@@ -0,0 +1,287 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF360
+P 5550 2300
+F 0 "SC3" H 5600 2600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5850 2387 50 0000 R CNN
+F 2 "" H 5550 800 50 0001 C CNN
+F 3 "" H 5550 2300 50 0001 C CNN
+ 1 5550 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 684AF39D
+P 5550 3100
+F 0 "SC4" H 5600 3400 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5850 3187 50 0000 R CNN
+F 2 "" H 5550 1600 50 0001 C CNN
+F 3 "" H 5550 3100 50 0001 C CNN
+ 1 5550 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC5
+U 1 1 684AF420
+P 5950 3800
+F 0 "SC5" H 6000 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6250 3887 50 0000 R CNN
+F 2 "" H 5950 2300 50 0001 C CNN
+F 3 "" H 5950 3800 50 0001 C CNN
+ 1 5950 3800
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF50C
+P 4450 4700
+F 0 "SC1" H 4500 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4750 4787 50 0000 R CNN
+F 2 "" H 4450 3200 50 0001 C CNN
+F 3 "" H 4450 4700 50 0001 C CNN
+ 1 4450 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684AF577
+P 5500 4700
+F 0 "SC2" H 5550 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5800 4787 50 0000 R CNN
+F 2 "" H 5500 3200 50 0001 C CNN
+F 3 "" H 5500 4700 50 0001 C CNN
+ 1 5500 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 684AF5EC
+P 6450 4700
+F 0 "SC6" H 6500 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6750 4787 50 0000 R CNN
+F 2 "" H 6450 3200 50 0001 C CNN
+F 3 "" H 6450 4700 50 0001 C CNN
+ 1 6450 4700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF63F
+P 3700 4000
+F 0 "U1" H 3750 4100 30 0000 C CNN
+F 1 "PORT" H 3700 4000 30 0000 C CNN
+F 2 "" H 3700 4000 60 0000 C CNN
+F 3 "" H 3700 4000 60 0000 C CNN
+ 1 3700 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF6CC
+P 4850 3850
+F 0 "U1" H 4900 3950 30 0000 C CNN
+F 1 "PORT" H 4850 3850 30 0000 C CNN
+F 2 "" H 4850 3850 60 0000 C CNN
+F 3 "" H 4850 3850 60 0000 C CNN
+ 2 4850 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF829
+P 7050 3800
+F 0 "U1" H 7100 3900 30 0000 C CNN
+F 1 "PORT" H 7050 3800 30 0000 C CNN
+F 2 "" H 7050 3800 60 0000 C CNN
+F 3 "" H 7050 3800 60 0000 C CNN
+ 5 7050 3800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684AF94D
+P 7150 4200
+F 0 "U1" H 7200 4300 30 0000 C CNN
+F 1 "PORT" H 7150 4200 30 0000 C CNN
+F 2 "" H 7150 4200 60 0000 C CNN
+F 3 "" H 7150 4200 60 0000 C CNN
+ 6 7150 4200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF9FE
+P 5100 5200
+F 0 "U1" H 5150 5300 30 0000 C CNN
+F 1 "PORT" H 5100 5200 30 0000 C CNN
+F 2 "" H 5100 5200 60 0000 C CNN
+F 3 "" H 5100 5200 60 0000 C CNN
+ 3 5100 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AFAE6
+P 5500 1750
+F 0 "U1" H 5550 1850 30 0000 C CNN
+F 1 "PORT" H 5500 1750 30 0000 C CNN
+F 2 "" H 5500 1750 60 0000 C CNN
+F 3 "" H 5500 1750 60 0000 C CNN
+ 4 5500 1750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5650 2300 5800 2300
+Wire Wire Line
+ 5800 2300 5800 1950
+Wire Wire Line
+ 5800 1950 5750 1950
+Wire Wire Line
+ 5750 1750 5750 2000
+Connection ~ 5750 1950
+Wire Wire Line
+ 5750 2600 5750 2800
+Wire Wire Line
+ 5650 3100 5800 3100
+Wire Wire Line
+ 5800 3100 5800 2750
+Wire Wire Line
+ 5800 2750 5750 2750
+Connection ~ 5750 2750
+Wire Wire Line
+ 5750 3500 5750 3400
+Wire Wire Line
+ 5850 3800 5700 3800
+Wire Wire Line
+ 5700 3800 5700 3450
+Wire Wire Line
+ 5700 3450 5750 3450
+Connection ~ 5750 3450
+Wire Wire Line
+ 4650 4400 4650 4300
+Wire Wire Line
+ 4650 4300 6250 4300
+Wire Wire Line
+ 6250 4300 6250 4400
+Wire Wire Line
+ 5700 4400 5700 4300
+Connection ~ 5700 4300
+Wire Wire Line
+ 5750 4100 5750 4300
+Connection ~ 5750 4300
+Wire Wire Line
+ 4650 5000 4650 5050
+Wire Wire Line
+ 4650 5050 6250 5050
+Wire Wire Line
+ 6250 5050 6250 5000
+Wire Wire Line
+ 5700 5000 5700 5050
+Connection ~ 5700 5050
+Wire Wire Line
+ 5350 5200 5350 5050
+Connection ~ 5350 5050
+Wire Wire Line
+ 4550 4700 4700 4700
+Wire Wire Line
+ 4700 4700 4700 5050
+Connection ~ 4700 5050
+Wire Wire Line
+ 5600 4700 5750 4700
+Wire Wire Line
+ 5750 4700 5750 5050
+Connection ~ 5750 5050
+Wire Wire Line
+ 6350 4700 6200 4700
+Wire Wire Line
+ 6200 4700 6200 5050
+Connection ~ 6200 5050
+Wire Wire Line
+ 4150 2300 4150 4700
+Wire Wire Line
+ 3950 4000 4150 4000
+Connection ~ 4150 4000
+Wire Wire Line
+ 5250 2300 4150 2300
+Wire Wire Line
+ 5250 3100 5200 3100
+Wire Wire Line
+ 5200 3100 5200 4700
+Wire Wire Line
+ 6250 3800 6800 3800
+Wire Wire Line
+ 6750 3800 6750 4700
+Connection ~ 6750 3800
+Wire Wire Line
+ 5100 3850 5200 3850
+Connection ~ 5200 3850
+Wire Wire Line
+ 6900 4200 5750 4200
+Connection ~ 5750 4200
+$Comp
+L SKY130mode scmode1
+U 1 1 684B00C1
+P 8250 2900
+F 0 "scmode1" H 8250 3050 98 0000 C CNB
+F 1 "SKY130mode" H 8250 2800 118 0000 C CNB
+F 2 "" H 8250 3050 60 0001 C CNN
+F 3 "" H 8250 3050 60 0001 C CNN
+ 1 8250 2900
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_3.cir b/library/SubcircuitLibrary/SN54L99/NAND_3.cir
new file mode 100644
index 000000000..e4f46e26d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_3.cir
@@ -0,0 +1,18 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/NAND_3.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 09:30:02 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC3 Net-_SC2-Pad1_ Net-_SC2-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC4 Net-_SC2-Pad1_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC5 Net-_SC2-Pad1_ Net-_SC5-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC6 Net-_SC1-Pad3_ Net-_SC5-Pad2_ Net-_SC6-Pad3_ Net-_SC6-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC2-Pad2_ Net-_SC1-Pad2_ Net-_SC6-Pad3_ Net-_SC3-Pad3_ Net-_SC2-Pad1_ Net-_SC5-Pad2_ PORT
+scmode1 SKY130mode
+SC2 Net-_SC2-Pad1_ Net-_SC2-Pad2_ Net-_SC1-Pad1_ Net-_SC1-Pad1_ sky130_fd_pr__nfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_3.cir.out b/library/SubcircuitLibrary/SN54L99/NAND_3.cir.out
new file mode 100644
index 000000000..b08a2163a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_3.cir.out
@@ -0,0 +1,21 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_3/nand_3.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc3 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc2-pad1_ net-_sc5-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc1-pad3_ net-_sc5-pad2_ net-_sc6-pad3_ net-_sc6-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc2-pad2_ net-_sc1-pad2_ net-_sc6-pad3_ net-_sc3-pad3_ net-_sc2-pad1_ net-_sc5-pad2_ port
+* s c m o d e
+xsc2 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_3.pro b/library/SubcircuitLibrary/SN54L99/NAND_3.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_3.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_3.sch b/library/SubcircuitLibrary/SN54L99/NAND_3.sch
new file mode 100644
index 000000000..eb96f8eac
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_3.sch
@@ -0,0 +1,289 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:NAND_3-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF360
+P 4200 2350
+F 0 "SC3" H 4250 2650 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4500 2437 50 0000 R CNN
+F 2 "" H 4200 850 50 0001 C CNN
+F 3 "" H 4200 2350 50 0001 C CNN
+ 1 4200 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 684AF39D
+P 5250 2350
+F 0 "SC4" H 5300 2650 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5550 2437 50 0000 R CNN
+F 2 "" H 5250 850 50 0001 C CNN
+F 3 "" H 5250 2350 50 0001 C CNN
+ 1 5250 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC5
+U 1 1 684AF420
+P 6100 2350
+F 0 "SC5" H 6150 2650 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6400 2437 50 0000 R CNN
+F 2 "" H 6100 850 50 0001 C CNN
+F 3 "" H 6100 2350 50 0001 C CNN
+ 1 6100 2350
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF50C
+P 5250 4000
+F 0 "SC1" H 5300 4300 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5550 4087 50 0000 R CNN
+F 2 "" H 5250 2500 50 0001 C CNN
+F 3 "" H 5250 4000 50 0001 C CNN
+ 1 5250 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 684AF5EC
+P 5650 4700
+F 0 "SC6" H 5700 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5950 4787 50 0000 R CNN
+F 2 "" H 5650 3200 50 0001 C CNN
+F 3 "" H 5650 4700 50 0001 C CNN
+ 1 5650 4700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF63F
+P 3450 2350
+F 0 "U1" H 3500 2450 30 0000 C CNN
+F 1 "PORT" H 3450 2350 30 0000 C CNN
+F 2 "" H 3450 2350 60 0000 C CNN
+F 3 "" H 3450 2350 60 0000 C CNN
+ 1 3450 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF6CC
+P 4500 4000
+F 0 "U1" H 4550 4100 30 0000 C CNN
+F 1 "PORT" H 4500 4000 30 0000 C CNN
+F 2 "" H 4500 4000 60 0000 C CNN
+F 3 "" H 4500 4000 60 0000 C CNN
+ 2 4500 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF829
+P 6300 2800
+F 0 "U1" H 6350 2900 30 0000 C CNN
+F 1 "PORT" H 6300 2800 30 0000 C CNN
+F 2 "" H 6300 2800 60 0000 C CNN
+F 3 "" H 6300 2800 60 0000 C CNN
+ 5 6300 2800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684AF94D
+P 6850 2350
+F 0 "U1" H 6900 2450 30 0000 C CNN
+F 1 "PORT" H 6850 2350 30 0000 C CNN
+F 2 "" H 6850 2350 60 0000 C CNN
+F 3 "" H 6850 2350 60 0000 C CNN
+ 6 6850 2350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF9FE
+P 5100 5200
+F 0 "U1" H 5150 5300 30 0000 C CNN
+F 1 "PORT" H 5100 5200 30 0000 C CNN
+F 2 "" H 5100 5200 60 0000 C CNN
+F 3 "" H 5100 5200 60 0000 C CNN
+ 3 5100 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AFAE6
+P 5500 1750
+F 0 "U1" H 5550 1850 30 0000 C CNN
+F 1 "PORT" H 5500 1750 30 0000 C CNN
+F 2 "" H 5500 1750 60 0000 C CNN
+F 3 "" H 5500 1750 60 0000 C CNN
+ 4 5500 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B00C1
+P 8250 2900
+F 0 "scmode1" H 8250 3050 98 0000 C CNB
+F 1 "SKY130mode" H 8250 2800 118 0000 C CNB
+F 2 "" H 8250 3050 60 0001 C CNN
+F 3 "" H 8250 3050 60 0001 C CNN
+ 1 8250 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684AF577
+P 5250 3250
+F 0 "SC2" H 5300 3550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5550 3337 50 0000 R CNN
+F 2 "" H 5250 1750 50 0001 C CNN
+F 3 "" H 5250 3250 50 0001 C CNN
+ 1 5250 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 2050 4400 2000
+Wire Wire Line
+ 4400 2000 5900 2000
+Wire Wire Line
+ 5900 2000 5900 2050
+Wire Wire Line
+ 5450 2050 5450 2000
+Connection ~ 5450 2000
+Wire Wire Line
+ 5750 1750 5750 2000
+Connection ~ 5750 2000
+Wire Wire Line
+ 4300 2350 4450 2350
+Wire Wire Line
+ 4450 2350 4450 2000
+Connection ~ 4450 2000
+Wire Wire Line
+ 5350 2350 5500 2350
+Wire Wire Line
+ 5500 2350 5500 2000
+Connection ~ 5500 2000
+Wire Wire Line
+ 6000 2350 5850 2350
+Wire Wire Line
+ 5850 2350 5850 2000
+Connection ~ 5850 2000
+Wire Wire Line
+ 4400 2650 4400 2700
+Wire Wire Line
+ 4400 2700 5900 2700
+Wire Wire Line
+ 5900 2700 5900 2650
+Wire Wire Line
+ 5450 2650 5450 2950
+Connection ~ 5450 2700
+Wire Wire Line
+ 6050 2800 5450 2800
+Connection ~ 5450 2800
+Wire Wire Line
+ 3700 2350 3900 2350
+Wire Wire Line
+ 3850 2350 3850 3250
+Wire Wire Line
+ 3850 3250 4950 3250
+Wire Wire Line
+ 4950 2350 4800 2350
+Wire Wire Line
+ 4800 2350 4800 4000
+Wire Wire Line
+ 4750 4000 4950 4000
+Wire Wire Line
+ 5350 3250 5500 3250
+Wire Wire Line
+ 5500 3250 5500 3600
+Wire Wire Line
+ 5500 3600 5450 3600
+Wire Wire Line
+ 5450 3550 5450 3700
+Connection ~ 5450 3600
+Wire Wire Line
+ 6400 2350 6600 2350
+Wire Wire Line
+ 6450 2350 6450 4700
+Wire Wire Line
+ 6450 4700 5950 4700
+Connection ~ 6450 2350
+Wire Wire Line
+ 5350 4000 5500 4000
+Wire Wire Line
+ 5500 4000 5500 4350
+Wire Wire Line
+ 5500 4350 5450 4350
+Wire Wire Line
+ 5450 4300 5450 4400
+Connection ~ 5450 4350
+Connection ~ 4800 4000
+Wire Wire Line
+ 5450 5000 5450 5200
+Wire Wire Line
+ 5450 5200 5350 5200
+Wire Wire Line
+ 5550 4700 5400 4700
+Wire Wire Line
+ 5400 4700 5400 5050
+Wire Wire Line
+ 5400 5050 5450 5050
+Connection ~ 5450 5050
+Connection ~ 3850 2350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_3.sub b/library/SubcircuitLibrary/SN54L99/NAND_3.sub
new file mode 100644
index 000000000..3b4f4b3ff
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_3.sub
@@ -0,0 +1,15 @@
+* Subcircuit NAND_3
+.subckt NAND_3 net-_sc2-pad2_ net-_sc1-pad2_ net-_sc6-pad3_ net-_sc3-pad3_ net-_sc2-pad1_ net-_sc5-pad2_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_3/nand_3.cir
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc3 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc2-pad1_ net-_sc5-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc1-pad3_ net-_sc5-pad2_ net-_sc6-pad3_ net-_sc6-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+xsc2 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends NAND_3
diff --git a/library/SubcircuitLibrary/SN54L99/NAND_3_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/NAND_3_Previous_Values.xml
new file mode 100644
index 000000000..c0934485a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NAND_3_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_2-cache.lib b/library/SubcircuitLibrary/SN54L99/NOR_2-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_2-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_2.cir b/library/SubcircuitLibrary/SN54L99/NOR_2.cir
new file mode 100644
index 000000000..976cd2f8e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_2.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_2/NOR_2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jul 7 11:47:22 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC2 Net-_SC2-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+SC3 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC2-Pad1_ Net-_SC2-Pad1_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC3-Pad2_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_2.cir.out b/library/SubcircuitLibrary/SN54L99/NOR_2.cir.out
new file mode 100644
index 000000000..5cf58fd73
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_2.cir.out
@@ -0,0 +1,24 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nor_2/nor_2.cir
+
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc2 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad1_ net-_sc2-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_2.pro b/library/SubcircuitLibrary/SN54L99/NOR_2.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_2.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_2.sch b/library/SubcircuitLibrary/SN54L99/NOR_2.sch
new file mode 100644
index 000000000..86f7c4bc6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_2.sch
@@ -0,0 +1,219 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684CE7B8
+P 4750 2600
+F 0 "SC2" H 4800 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5050 2687 50 0000 R CNN
+F 2 "" H 4750 1100 50 0001 C CNN
+F 3 "" H 4750 2600 50 0001 C CNN
+ 1 4750 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684CE82E
+P 5150 3400
+F 0 "SC3" H 5200 3700 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 3487 50 0000 R CNN
+F 2 "" H 5150 1900 50 0001 C CNN
+F 3 "" H 5150 3400 50 0001 C CNN
+ 1 5150 3400
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684CE88F
+P 4050 4450
+F 0 "SC1" H 4100 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4350 4537 50 0000 R CNN
+F 2 "" H 4050 2950 50 0001 C CNN
+F 3 "" H 4050 4450 50 0001 C CNN
+ 1 4050 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684CE8CA
+P 5650 4450
+F 0 "SC4" H 5700 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5950 4537 50 0000 R CNN
+F 2 "" H 5650 2950 50 0001 C CNN
+F 3 "" H 5650 4450 50 0001 C CNN
+ 1 5650 4450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684CE919
+P 3100 3450
+F 0 "U1" H 3150 3550 30 0000 C CNN
+F 1 "PORT" H 3100 3450 30 0000 C CNN
+F 2 "" H 3100 3450 60 0000 C CNN
+F 3 "" H 3100 3450 60 0000 C CNN
+ 1 3100 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684CE990
+P 6350 3400
+F 0 "U1" H 6400 3500 30 0000 C CNN
+F 1 "PORT" H 6350 3400 30 0000 C CNN
+F 2 "" H 6350 3400 60 0000 C CNN
+F 3 "" H 6350 3400 60 0000 C CNN
+ 4 6350 3400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684CEA11
+P 6450 3900
+F 0 "U1" H 6500 4000 30 0000 C CNN
+F 1 "PORT" H 6450 3900 30 0000 C CNN
+F 2 "" H 6450 3900 60 0000 C CNN
+F 3 "" H 6450 3900 60 0000 C CNN
+ 5 6450 3900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684CEA84
+P 4700 2150
+F 0 "U1" H 4750 2250 30 0000 C CNN
+F 1 "PORT" H 4700 2150 30 0000 C CNN
+F 2 "" H 4700 2150 60 0000 C CNN
+F 3 "" H 4700 2150 60 0000 C CNN
+ 3 4700 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684CEB11
+P 4650 5100
+F 0 "U1" H 4700 5200 30 0000 C CNN
+F 1 "PORT" H 4650 5100 30 0000 C CNN
+F 2 "" H 4650 5100 60 0000 C CNN
+F 3 "" H 4650 5100 60 0000 C CNN
+ 2 4650 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684CEB6E
+P 8300 2900
+F 0 "scmode1" H 8300 3050 98 0000 C CNB
+F 1 "SKY130mode" H 8300 2800 118 0000 C CNB
+F 2 "" H 8300 3050 60 0001 C CNN
+F 3 "" H 8300 3050 60 0001 C CNN
+ 1 8300 2900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4250 4150 5450 4150
+Wire Wire Line
+ 4950 3700 4950 4150
+Connection ~ 4950 4150
+Wire Wire Line
+ 6200 3900 4950 3900
+Connection ~ 4950 3900
+Wire Wire Line
+ 4250 4750 5450 4750
+Wire Wire Line
+ 5550 4450 5400 4450
+Wire Wire Line
+ 5400 4450 5400 4750
+Connection ~ 5400 4750
+Wire Wire Line
+ 4150 4450 4300 4450
+Wire Wire Line
+ 4300 4450 4300 4750
+Connection ~ 4300 4750
+Wire Wire Line
+ 4900 5100 4900 4750
+Connection ~ 4900 4750
+Wire Wire Line
+ 5450 3400 6100 3400
+Wire Wire Line
+ 5950 3400 5950 4450
+Connection ~ 5950 3400
+Wire Wire Line
+ 4450 2600 3750 2600
+Wire Wire Line
+ 3750 2600 3750 4450
+Wire Wire Line
+ 3350 3450 3750 3450
+Connection ~ 3750 3450
+Wire Wire Line
+ 4950 2150 4950 2300
+Wire Wire Line
+ 4850 2600 5000 2600
+Wire Wire Line
+ 5000 2600 5000 2250
+Wire Wire Line
+ 5000 2250 4950 2250
+Connection ~ 4950 2250
+Wire Wire Line
+ 4950 2900 4950 3100
+Wire Wire Line
+ 5050 3400 4900 3400
+Wire Wire Line
+ 4900 3400 4900 3050
+Wire Wire Line
+ 4900 3050 4950 3050
+Connection ~ 4950 3050
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_2.sub b/library/SubcircuitLibrary/SN54L99/NOR_2.sub
new file mode 100644
index 000000000..f5a7ff023
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_2.sub
@@ -0,0 +1,18 @@
+* Subcircuit NOR_2
+.subckt NOR_2 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nor_2/nor_2.cir
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc2 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad1_ net-_sc2-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends NOR_2
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_2_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/NOR_2_Previous_Values.xml
new file mode 100644
index 000000000..62dc0d0a2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_2_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_3-cache.lib b/library/SubcircuitLibrary/SN54L99/NOR_3-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_3-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_3.cir b/library/SubcircuitLibrary/SN54L99/NOR_3.cir
new file mode 100644
index 000000000..0738ff996
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_3.cir
@@ -0,0 +1,18 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_3/NOR_3.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jul 10 16:42:16 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC3 Net-_SC3-Pad1_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC4 Net-_SC4-Pad1_ Net-_SC2-Pad2_ Net-_SC3-Pad1_ Net-_SC3-Pad1_ sky130_fd_pr__pfet_01v8
+SC5 Net-_SC1-Pad1_ Net-_SC5-Pad2_ Net-_SC4-Pad1_ Net-_SC4-Pad1_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC6 Net-_SC1-Pad1_ Net-_SC5-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+scmode1 SKY130mode
+U1 Net-_SC1-Pad2_ Net-_SC2-Pad2_ Net-_SC1-Pad1_ Net-_SC1-Pad3_ Net-_SC3-Pad3_ Net-_SC5-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_3.cir.out b/library/SubcircuitLibrary/SN54L99/NOR_3.cir.out
new file mode 100644
index 000000000..2b5210432
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_3.cir.out
@@ -0,0 +1,20 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nor_3/nor_3.cir
+
+
+xsc3 net-_sc3-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc2-pad2_ net-_sc3-pad1_ net-_sc3-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc4-pad1_ net-_sc4-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* u1 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc5-pad2_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_3.pro b/library/SubcircuitLibrary/SN54L99/NOR_3.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_3.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_3.sch b/library/SubcircuitLibrary/SN54L99/NOR_3.sch
new file mode 100644
index 000000000..19a2ccb81
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_3.sch
@@ -0,0 +1,278 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 686F9EE9
+P 5700 1900
+F 0 "SC3" H 5750 2200 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6000 1987 50 0000 R CNN
+F 2 "" H 5700 400 50 0001 C CNN
+F 3 "" H 5700 1900 50 0001 C CNN
+ 1 5700 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 686F9F00
+P 5700 2600
+F 0 "SC4" H 5750 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6000 2687 50 0000 R CNN
+F 2 "" H 5700 1100 50 0001 C CNN
+F 3 "" H 5700 2600 50 0001 C CNN
+ 1 5700 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC5
+U 1 1 686F9F3F
+P 6100 3300
+F 0 "SC5" H 6150 3600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6400 3387 50 0000 R CNN
+F 2 "" H 6100 1800 50 0001 C CNN
+F 3 "" H 6100 3300 50 0001 C CNN
+ 1 6100 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 686F9FDA
+P 4700 4250
+F 0 "SC1" H 4750 4550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5000 4337 50 0000 R CNN
+F 2 "" H 4700 2750 50 0001 C CNN
+F 3 "" H 4700 4250 50 0001 C CNN
+ 1 4700 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 686FA080
+P 5650 4250
+F 0 "SC2" H 5700 4550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5950 4337 50 0000 R CNN
+F 2 "" H 5650 2750 50 0001 C CNN
+F 3 "" H 5650 4250 50 0001 C CNN
+ 1 5650 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 686FA290
+P 6650 4250
+F 0 "SC6" H 6700 4550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6950 4337 50 0000 R CNN
+F 2 "" H 6650 2750 50 0001 C CNN
+F 3 "" H 6650 4250 50 0001 C CNN
+ 1 6650 4250
+ -1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686FA309
+P 10350 6000
+F 0 "scmode1" H 10350 6150 98 0000 C CNB
+F 1 "SKY130mode" H 10350 5900 118 0000 C CNB
+F 2 "" H 10350 6150 60 0001 C CNN
+F 3 "" H 10350 6150 60 0001 C CNN
+ 1 10350 6000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4900 3950 4900 3900
+Wire Wire Line
+ 4900 3900 6450 3900
+Wire Wire Line
+ 6450 3900 6450 3950
+Wire Wire Line
+ 5850 3950 5850 3900
+Connection ~ 5850 3900
+Wire Wire Line
+ 5900 3600 5900 3900
+Connection ~ 5900 3900
+Wire Wire Line
+ 4900 4550 4900 4600
+Wire Wire Line
+ 4900 4600 6450 4600
+Wire Wire Line
+ 6450 4600 6450 4550
+Wire Wire Line
+ 5850 4550 5850 4600
+Connection ~ 5850 4600
+Wire Wire Line
+ 4800 4250 4950 4250
+Wire Wire Line
+ 4950 4250 4950 4600
+Connection ~ 4950 4600
+Wire Wire Line
+ 5750 4250 5900 4250
+Wire Wire Line
+ 5900 4250 5900 4600
+Connection ~ 5900 4600
+Wire Wire Line
+ 6550 4250 6400 4250
+Wire Wire Line
+ 6400 4250 6400 4600
+Connection ~ 6400 4600
+Wire Wire Line
+ 6000 3300 5850 3300
+Wire Wire Line
+ 5850 3300 5850 2950
+Wire Wire Line
+ 5850 2950 5900 2950
+Wire Wire Line
+ 5900 2900 5900 3000
+Connection ~ 5900 2950
+Wire Wire Line
+ 5800 2600 5950 2600
+Wire Wire Line
+ 5950 2600 5950 2250
+Wire Wire Line
+ 5950 2250 5900 2250
+Wire Wire Line
+ 5900 2200 5900 2300
+Connection ~ 5900 2250
+Wire Wire Line
+ 5800 1900 5950 1900
+Wire Wire Line
+ 5950 1900 5950 1550
+Wire Wire Line
+ 5950 1550 5900 1550
+Wire Wire Line
+ 5900 1550 5900 1600
+Wire Wire Line
+ 5400 1900 4400 1900
+Wire Wire Line
+ 4400 1900 4400 4250
+Wire Wire Line
+ 5400 2600 5350 2600
+Wire Wire Line
+ 5350 2600 5350 4250
+Wire Wire Line
+ 6400 3300 6950 3300
+Wire Wire Line
+ 6950 3300 6950 4250
+$Comp
+L PORT U1
+U 5 1 686FA7F6
+P 5950 1300
+F 0 "U1" H 6000 1400 30 0000 C CNN
+F 1 "PORT" H 5950 1300 30 0000 C CNN
+F 2 "" H 5950 1300 60 0000 C CNN
+F 3 "" H 5950 1300 60 0000 C CNN
+ 5 5950 1300
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686FA8CF
+P 4150 1900
+F 0 "U1" H 4200 2000 30 0000 C CNN
+F 1 "PORT" H 4150 1900 30 0000 C CNN
+F 2 "" H 4150 1900 60 0000 C CNN
+F 3 "" H 4150 1900 60 0000 C CNN
+ 1 4150 1900
+ 1 0 0 -1
+$EndComp
+Connection ~ 4400 1900
+Connection ~ 5950 1550
+Connection ~ 5350 2600
+Connection ~ 6950 3300
+Connection ~ 5900 3700
+$Comp
+L PORT U1
+U 2 1 686FACDE
+P 5100 2600
+F 0 "U1" H 5150 2700 30 0000 C CNN
+F 1 "PORT" H 5100 2600 30 0000 C CNN
+F 2 "" H 5100 2600 60 0000 C CNN
+F 3 "" H 5100 2600 60 0000 C CNN
+ 2 5100 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686FAD41
+P 5650 3700
+F 0 "U1" H 5700 3800 30 0000 C CNN
+F 1 "PORT" H 5650 3700 30 0000 C CNN
+F 2 "" H 5650 3700 60 0000 C CNN
+F 3 "" H 5650 3700 60 0000 C CNN
+ 3 5650 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686FAD8E
+P 7200 3300
+F 0 "U1" H 7250 3400 30 0000 C CNN
+F 1 "PORT" H 7200 3300 30 0000 C CNN
+F 2 "" H 7200 3300 60 0000 C CNN
+F 3 "" H 7200 3300 60 0000 C CNN
+ 6 7200 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686FAE65
+P 5900 4850
+F 0 "U1" H 5950 4950 30 0000 C CNN
+F 1 "PORT" H 5900 4850 30 0000 C CNN
+F 2 "" H 5900 4850 60 0000 C CNN
+F 3 "" H 5900 4850 60 0000 C CNN
+ 4 5900 4850
+ 0 1 -1 0
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_3.sub b/library/SubcircuitLibrary/SN54L99/NOR_3.sub
new file mode 100644
index 000000000..11cd9a15b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_3.sub
@@ -0,0 +1,14 @@
+* Subcircuit NOR_3
+.subckt NOR_3 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc5-pad2_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nor_3/nor_3.cir
+
+xsc3 net-_sc3-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc2-pad2_ net-_sc3-pad1_ net-_sc3-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc4-pad1_ net-_sc4-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends NOR_3
diff --git a/library/SubcircuitLibrary/SN54L99/NOR_3_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/NOR_3_Previous_Values.xml
new file mode 100644
index 000000000..4c32827f4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/NOR_3_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/SN54L99-cache.lib b/library/SubcircuitLibrary/SN54L99/SN54L99-cache.lib
new file mode 100644
index 000000000..69e245823
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SN54L99-cache.lib
@@ -0,0 +1,153 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 2_in_and
+#
+DEF 2_in_and X 0 40 Y Y 1 F N
+F0 "X" 50 0 60 H V C CNN
+F1 "2_in_and" 0 -250 60 H V C CNN
+F2 "" 750 -150 60 H I C CNN
+F3 "" 750 -150 60 H I C CNN
+DRAW
+A 50 0 206 760 -760 0 1 0 N 100 200 100 -200
+P 2 0 1 0 -200 200 100 200 N
+P 3 0 1 0 -200 200 -200 -200 100 -200 N
+X Vdd 1 -400 150 200 R 50 50 1 1 I
+X in1 2 -400 50 200 R 50 50 1 1 I
+X in2 3 -400 -50 200 R 50 50 1 1 I
+X Gnd 4 -400 -150 200 R 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# DS_blk
+#
+DEF DS_blk X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "DS_blk" 0 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -250 200 250 -200 0 1 0 N
+X in1 1 -450 150 200 R 50 50 1 1 I
+X ws1 2 -450 50 200 R 50 50 1 1 I
+X ws2 3 -450 -50 200 R 50 50 1 1 I
+X in2 4 -450 -150 200 R 50 50 1 1 I
+X Clk 5 450 50 200 L 50 50 1 1 I
+X Vdd 6 450 150 200 L 50 50 1 1 I
+X Gnd 7 450 -150 200 L 50 50 1 1 I
+X Out 8 450 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# SerialParallel_blk
+#
+DEF SerialParallel_blk X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "SerialParallel_blk" 0 -300 60 H V C CNN
+F2 "" -850 300 60 H I C CNN
+F3 "" -850 300 60 H I C CNN
+DRAW
+S -350 250 300 -250 0 1 0 N
+X J 1 500 150 200 L 50 50 1 1 I
+X K 2 500 50 200 L 50 50 1 1 I
+X clk 3 -550 0 200 R 50 50 1 1 I
+X A 4 -550 100 200 R 50 50 1 1 I
+X M 5 -550 -100 200 R 50 50 1 1 I
+X M_bar 6 -550 -200 200 R 50 50 1 1 I
+X Vdd 7 -550 200 200 R 50 50 1 1 I
+X Gnd 8 500 -200 200 L 50 50 1 1 I
+X Qa 9 500 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# or_2
+#
+DEF or_2 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "or_2" 0 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A -400 0 206 760 -760 0 1 0 N -350 200 -350 -200
+A -180 -290 519 1091 340 0 1 0 N -350 200 250 0
+A -175 275 506 -1102 -329 0 1 0 N -350 -200 250 0
+X in1 1 -400 50 200 R 50 50 1 1 I
+X in2 2 -400 -50 200 R 50 50 1 1 I
+X Vdd 3 -450 150 200 R 50 50 1 1 I
+X Gnd 4 -450 -150 200 R 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/SN54L99.bak b/library/SubcircuitLibrary/SN54L99/SN54L99.bak
new file mode 100644
index 000000000..1e73214eb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SN54L99.bak
@@ -0,0 +1,518 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN54L99-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 686FB10F
+P 10500 6100
+F 0 "scmode1" H 10500 6250 98 0000 C CNB
+F 1 "SKY130mode" H 10500 6000 118 0000 C CNB
+F 2 "" H 10500 6250 60 0001 C CNN
+F 3 "" H 10500 6250 60 0001 C CNN
+ 1 10500 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L SerialParallel_blk X4
+U 1 1 686FB703
+P 4200 4050
+F 0 "X4" H 4200 4050 60 0000 C CNN
+F 1 "SerialParallel_blk" H 4200 3750 60 0000 C CNN
+F 2 "" H 3350 4350 60 0001 C CNN
+F 3 "" H 3350 4350 60 0001 C CNN
+ 1 4200 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L DS_blk X6
+U 1 1 686FB752
+P 5600 4050
+F 0 "X6" H 5600 4050 60 0000 C CNN
+F 1 "DS_blk" H 5600 3800 60 0000 C CNN
+F 2 "" H 5600 4050 60 0001 C CNN
+F 3 "" H 5600 4050 60 0001 C CNN
+ 1 5600 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L DS_blk X7
+U 1 1 686FB79D
+P 6850 4050
+F 0 "X7" H 6850 4050 60 0000 C CNN
+F 1 "DS_blk" H 6850 3800 60 0000 C CNN
+F 2 "" H 6850 4050 60 0001 C CNN
+F 3 "" H 6850 4050 60 0001 C CNN
+ 1 6850 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L DS_blk X8
+U 1 1 686FB8BA
+P 8250 4050
+F 0 "X8" H 8250 4050 60 0000 C CNN
+F 1 "DS_blk" H 8250 3800 60 0000 C CNN
+F 2 "" H 8250 4050 60 0001 C CNN
+F 3 "" H 8250 4050 60 0001 C CNN
+ 1 8250 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L 2_in_and X2
+U 1 1 686FB9B6
+P 3900 5800
+F 0 "X2" H 3950 5800 60 0000 C CNN
+F 1 "2_in_and" H 3900 5550 60 0000 C CNN
+F 2 "" H 4650 5650 60 0001 C CNN
+F 3 "" H 4650 5650 60 0001 C CNN
+ 1 3900 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L 2_in_and X3
+U 1 1 686FB9F7
+P 3900 6450
+F 0 "X3" H 3950 6450 60 0000 C CNN
+F 1 "2_in_and" H 3900 6200 60 0000 C CNN
+F 2 "" H 4650 6300 60 0001 C CNN
+F 3 "" H 4650 6300 60 0001 C CNN
+ 1 3900 6450
+ 1 0 0 -1
+$EndComp
+$Comp
+L or_2 X5
+U 1 1 686FBA1C
+P 4950 6150
+F 0 "X5" H 4950 6150 60 0000 C CNN
+F 1 "or_2" H 4950 5900 60 0000 C CNN
+F 2 "" H 4950 6150 60 0001 C CNN
+F 3 "" H 4950 6150 60 0001 C CNN
+ 1 4950 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 686FBA57
+P 3100 5850
+F 0 "X1" H 3100 5850 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3150 5650 60 0000 C CNN
+F 2 "" H 3100 5850 60 0001 C CNN
+F 3 "" H 3100 5850 60 0001 C CNN
+ 1 3100 5850
+ 0 -1 -1 0
+$EndComp
+Text Label 2500 6400 0 60 ~ 0
+mode
+Text Label 2600 5850 0 60 ~ 0
+RS
+Text Label 2600 6500 0 60 ~ 0
+LS
+Wire Wire Line
+ 4350 5800 4350 6100
+Wire Wire Line
+ 4350 6100 4550 6100
+Wire Wire Line
+ 4350 6450 4350 6200
+Wire Wire Line
+ 4350 6200 4550 6200
+Wire Wire Line
+ 3400 5750 3500 5750
+Wire Wire Line
+ 3400 4250 3400 5750
+Wire Wire Line
+ 2400 6400 3500 6400
+Wire Wire Line
+ 3100 6400 3100 6250
+Wire Wire Line
+ 3100 5300 7650 5300
+Connection ~ 3100 6400
+Wire Wire Line
+ 3500 5850 2400 5850
+Wire Wire Line
+ 3500 6500 2400 6500
+Wire Wire Line
+ 3650 4250 3400 4250
+Connection ~ 3400 5300
+Wire Wire Line
+ 3650 4150 2950 4150
+Wire Wire Line
+ 2950 4150 2950 6400
+Connection ~ 2950 6400
+Wire Wire Line
+ 8700 4000 8850 4000
+Wire Wire Line
+ 8850 4000 8850 4550
+Wire Wire Line
+ 8850 4550 3600 4550
+Wire Wire Line
+ 3600 4550 3600 4050
+Wire Wire Line
+ 3600 4050 3650 4050
+Wire Wire Line
+ 6050 4000 6100 4000
+Wire Wire Line
+ 6100 4000 6100 6150
+Connection ~ 6100 4550
+Wire Wire Line
+ 7300 4000 7350 4000
+Wire Wire Line
+ 7350 4000 7350 4550
+Connection ~ 7350 4550
+Wire Wire Line
+ 6100 6150 5400 6150
+Wire Wire Line
+ 4850 4150 4700 4150
+Wire Wire Line
+ 4850 3050 4850 4150
+Wire Wire Line
+ 4850 3900 5150 3900
+Wire Wire Line
+ 6200 4100 6050 4100
+Wire Wire Line
+ 6200 3050 6200 4100
+Wire Wire Line
+ 6200 3900 6400 3900
+Wire Wire Line
+ 7550 4100 7300 4100
+Wire Wire Line
+ 7550 3050 7550 4100
+Wire Wire Line
+ 7550 3900 7800 3900
+Wire Wire Line
+ 5150 4000 4900 4000
+Wire Wire Line
+ 4900 4000 4900 5300
+Wire Wire Line
+ 6400 4000 6300 4000
+Wire Wire Line
+ 6300 4000 6300 5300
+Connection ~ 4900 5300
+Wire Wire Line
+ 7800 4000 7650 4000
+Wire Wire Line
+ 7650 4000 7650 5300
+Connection ~ 6300 5300
+Wire Wire Line
+ 5150 4100 4950 4100
+Wire Wire Line
+ 4950 4100 4950 5100
+Wire Wire Line
+ 2950 5100 7700 5100
+Connection ~ 2950 5100
+Wire Wire Line
+ 6350 5100 6350 4100
+Wire Wire Line
+ 6350 4100 6400 4100
+Connection ~ 4950 5100
+Wire Wire Line
+ 7700 5100 7700 4100
+Wire Wire Line
+ 7700 4100 7800 4100
+Connection ~ 6350 5100
+Wire Wire Line
+ 3650 3850 3650 3750
+Wire Wire Line
+ 3650 3750 8950 3750
+Wire Wire Line
+ 8950 3750 8950 5500
+Wire Wire Line
+ 8950 5500 2900 5500
+Wire Wire Line
+ 2900 5500 2900 6250
+Wire Wire Line
+ 2900 6250 3000 6250
+Wire Wire Line
+ 3500 5650 3500 5500
+Connection ~ 3500 5500
+Wire Wire Line
+ 3500 6300 3300 6300
+Wire Wire Line
+ 3300 6300 3300 5500
+Connection ~ 3300 5500
+Wire Wire Line
+ 4500 6000 4500 5500
+Connection ~ 4500 5500
+Wire Wire Line
+ 8700 3900 8700 3750
+Connection ~ 8700 3750
+Wire Wire Line
+ 7300 3900 7300 3750
+Connection ~ 7300 3750
+Wire Wire Line
+ 6050 3900 6050 3750
+Connection ~ 6050 3750
+Wire Wire Line
+ 3200 6250 3200 6800
+Wire Wire Line
+ 8700 4350 4700 4350
+Wire Wire Line
+ 4700 4350 4700 4250
+Connection ~ 8700 4350
+Wire Wire Line
+ 6050 4200 6050 4350
+Connection ~ 6050 4350
+Wire Wire Line
+ 7300 4200 7300 4350
+Connection ~ 7300 4350
+Wire Wire Line
+ 3500 6600 3500 6800
+Connection ~ 3500 6800
+Wire Wire Line
+ 3500 5950 3400 5950
+Wire Wire Line
+ 3400 5950 3400 6800
+Connection ~ 3400 6800
+Wire Wire Line
+ 4500 6300 4500 6800
+Connection ~ 4500 6800
+Wire Wire Line
+ 8700 4200 8700 5650
+Wire Wire Line
+ 8700 5650 6200 5650
+Wire Wire Line
+ 6200 5650 6200 6800
+Wire Wire Line
+ 6200 6800 3200 6800
+Wire Wire Line
+ 8700 4100 9100 4100
+Wire Wire Line
+ 9100 4100 9100 3050
+Connection ~ 7550 3900
+Connection ~ 6200 3900
+Connection ~ 4850 3900
+Wire Wire Line
+ 3650 3950 3500 3950
+Wire Wire Line
+ 5150 4200 5150 4500
+Wire Wire Line
+ 3500 3950 3500 4500
+Wire Wire Line
+ 6400 4200 6400 4500
+Wire Wire Line
+ 7800 4200 7800 4500
+Wire Wire Line
+ 4700 4000 4750 4000
+Wire Wire Line
+ 4750 4000 4750 4500
+Wire Wire Line
+ 4700 3900 4800 3900
+Wire Wire Line
+ 4800 3900 4800 4500
+$Comp
+L PORT U1
+U 4 1 686FDE79
+P 3500 4750
+F 0 "U1" H 3550 4850 30 0000 C CNN
+F 1 "PORT" H 3500 4750 30 0000 C CNN
+F 2 "" H 3500 4750 60 0000 C CNN
+F 3 "" H 3500 4750 60 0000 C CNN
+ 4 3500 4750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686FDEC4
+P 4750 4750
+F 0 "U1" H 4800 4850 30 0000 C CNN
+F 1 "PORT" H 4750 4750 30 0000 C CNN
+F 2 "" H 4750 4750 60 0000 C CNN
+F 3 "" H 4750 4750 60 0000 C CNN
+ 6 4750 4750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686FDF2F
+P 4800 4750
+F 0 "U1" H 4850 4850 30 0000 C CNN
+F 1 "PORT" H 4800 4750 30 0000 C CNN
+F 2 "" H 4800 4750 60 0000 C CNN
+F 3 "" H 4800 4750 60 0000 C CNN
+ 7 4800 4750
+ 0 1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686FDFA4
+P 5150 4750
+F 0 "U1" H 5200 4850 30 0000 C CNN
+F 1 "PORT" H 5150 4750 30 0000 C CNN
+F 2 "" H 5150 4750 60 0000 C CNN
+F 3 "" H 5150 4750 60 0000 C CNN
+ 8 5150 4750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686FE00E
+P 6400 4750
+F 0 "U1" H 6450 4850 30 0000 C CNN
+F 1 "PORT" H 6400 4750 30 0000 C CNN
+F 2 "" H 6400 4750 60 0000 C CNN
+F 3 "" H 6400 4750 60 0000 C CNN
+ 10 6400 4750
+ 0 1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686FE067
+P 7800 4750
+F 0 "U1" H 7850 4850 30 0000 C CNN
+F 1 "PORT" H 7800 4750 30 0000 C CNN
+F 2 "" H 7800 4750 60 0000 C CNN
+F 3 "" H 7800 4750 60 0000 C CNN
+ 12 7800 4750
+ 0 1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 15 1 686FE0F5
+P 8950 4350
+F 0 "U1" H 9000 4450 30 0000 C CNN
+F 1 "PORT" H 8950 4350 30 0000 C CNN
+F 2 "" H 8950 4350 60 0000 C CNN
+F 3 "" H 8950 4350 60 0000 C CNN
+ 15 8950 4350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686FE22E
+P 8700 3500
+F 0 "U1" H 8750 3600 30 0000 C CNN
+F 1 "PORT" H 8700 3500 30 0000 C CNN
+F 2 "" H 8700 3500 60 0000 C CNN
+F 3 "" H 8700 3500 60 0000 C CNN
+ 13 8700 3500
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 14 1 686FE2E8
+P 8850 3050
+F 0 "U1" H 8900 3150 30 0000 C CNN
+F 1 "PORT" H 8850 3050 30 0000 C CNN
+F 2 "" H 8850 3050 60 0000 C CNN
+F 3 "" H 8850 3050 60 0000 C CNN
+ 14 8850 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686FE34F
+P 7300 3050
+F 0 "U1" H 7350 3150 30 0000 C CNN
+F 1 "PORT" H 7300 3050 30 0000 C CNN
+F 2 "" H 7300 3050 60 0000 C CNN
+F 3 "" H 7300 3050 60 0000 C CNN
+ 11 7300 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686FE474
+P 5950 3050
+F 0 "U1" H 6000 3150 30 0000 C CNN
+F 1 "PORT" H 5950 3050 30 0000 C CNN
+F 2 "" H 5950 3050 60 0000 C CNN
+F 3 "" H 5950 3050 60 0000 C CNN
+ 9 5950 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686FE4E5
+P 4600 3050
+F 0 "U1" H 4650 3150 30 0000 C CNN
+F 1 "PORT" H 4600 3050 30 0000 C CNN
+F 2 "" H 4600 3050 60 0000 C CNN
+F 3 "" H 4600 3050 60 0000 C CNN
+ 5 4600 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686FE646
+P 2150 5850
+F 0 "U1" H 2200 5950 30 0000 C CNN
+F 1 "PORT" H 2150 5850 30 0000 C CNN
+F 2 "" H 2150 5850 60 0000 C CNN
+F 3 "" H 2150 5850 60 0000 C CNN
+ 1 2150 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686FE6B7
+P 2150 6400
+F 0 "U1" H 2200 6500 30 0000 C CNN
+F 1 "PORT" H 2150 6400 30 0000 C CNN
+F 2 "" H 2150 6400 60 0000 C CNN
+F 3 "" H 2150 6400 60 0000 C CNN
+ 2 2150 6400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686FE728
+P 2150 6500
+F 0 "U1" H 2200 6600 30 0000 C CNN
+F 1 "PORT" H 2150 6500 30 0000 C CNN
+F 2 "" H 2150 6500 60 0000 C CNN
+F 3 "" H 2150 6500 60 0000 C CNN
+ 3 2150 6500
+ 1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/SN54L99.cir b/library/SubcircuitLibrary/SN54L99/SN54L99.cir
new file mode 100644
index 000000000..951b7438d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SN54L99.cir
@@ -0,0 +1,20 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SN54L99/SN54L99.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jul 10 18:58:06 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+scmode1 SKY130mode
+X4 Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_X4-Pad3_ Net-_U1-Pad4_ /mode Net-_X1-Pad4_ Net-_U1-Pad13_ Net-_U1-Pad15_ Net-_U1-Pad5_ SerialParallel_blk
+X6 Net-_U1-Pad5_ Net-_X1-Pad4_ /mode Net-_U1-Pad8_ Net-_X4-Pad3_ Net-_U1-Pad13_ Net-_U1-Pad15_ Net-_U1-Pad9_ DS_blk
+X7 Net-_U1-Pad9_ Net-_X1-Pad4_ /mode Net-_U1-Pad10_ Net-_X4-Pad3_ Net-_U1-Pad13_ Net-_U1-Pad15_ Net-_U1-Pad11_ DS_blk
+X8 Net-_U1-Pad11_ Net-_X1-Pad4_ /mode Net-_U1-Pad12_ Net-_X4-Pad3_ Net-_U1-Pad13_ Net-_U1-Pad15_ Net-_U1-Pad14_ DS_blk
+X2 Net-_U1-Pad13_ Net-_X1-Pad4_ /RS Net-_U1-Pad15_ Net-_X2-Pad5_ 2_in_and
+X3 Net-_U1-Pad13_ /mode /LS Net-_U1-Pad15_ Net-_X3-Pad5_ 2_in_and
+X5 Net-_X2-Pad5_ Net-_X3-Pad5_ Net-_U1-Pad13_ Net-_U1-Pad15_ Net-_X4-Pad3_ or_2
+X1 /mode Net-_U1-Pad13_ Net-_U1-Pad15_ Net-_X1-Pad4_ CMOS_INVTR
+U1 /RS /mode /LS Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/SN54L99.cir.out b/library/SubcircuitLibrary/SN54L99/SN54L99.cir.out
new file mode 100644
index 000000000..00a95aafd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SN54L99.cir.out
@@ -0,0 +1,33 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/sn54l99/sn54l99.cir
+
+.include SerialParallel_blk.sub
+.include or_2.sub
+.include DS_blk.sub
+.include CMOS_INVTR.sub
+.include 2_in_and.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* s c m o d e
+x4 net-_u1-pad7_ net-_u1-pad6_ net-_x4-pad3_ net-_u1-pad4_ /mode net-_x1-pad4_ net-_u1-pad13_ net-_u1-pad15_ net-_u1-pad5_ SerialParallel_blk
+x6 net-_u1-pad5_ net-_x1-pad4_ /mode net-_u1-pad8_ net-_x4-pad3_ net-_u1-pad13_ net-_u1-pad15_ net-_u1-pad9_ DS_blk
+x7 net-_u1-pad9_ net-_x1-pad4_ /mode net-_u1-pad10_ net-_x4-pad3_ net-_u1-pad13_ net-_u1-pad15_ net-_u1-pad11_ DS_blk
+x8 net-_u1-pad11_ net-_x1-pad4_ /mode net-_u1-pad12_ net-_x4-pad3_ net-_u1-pad13_ net-_u1-pad15_ net-_u1-pad14_ DS_blk
+x2 net-_u1-pad13_ net-_x1-pad4_ /rs net-_u1-pad15_ net-_x2-pad5_ 2_in_and
+x3 net-_u1-pad13_ /mode /ls net-_u1-pad15_ net-_x3-pad5_ 2_in_and
+x5 net-_x2-pad5_ net-_x3-pad5_ net-_u1-pad13_ net-_u1-pad15_ net-_x4-pad3_ or_2
+x1 /mode net-_u1-pad13_ net-_u1-pad15_ net-_x1-pad4_ CMOS_INVTR
+* u1 /rs /mode /ls net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/SN54L99.pro b/library/SubcircuitLibrary/SN54L99/SN54L99.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SN54L99.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/SN54L99.sch b/library/SubcircuitLibrary/SN54L99/SN54L99.sch
new file mode 100644
index 000000000..e116ec524
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SN54L99.sch
@@ -0,0 +1,518 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN54L99-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 686FB10F
+P 6700 4600
+F 0 "scmode1" H 6700 4750 98 0000 C CNB
+F 1 "SKY130mode" H 6700 4500 118 0000 C CNB
+F 2 "" H 6700 4750 60 0001 C CNN
+F 3 "" H 6700 4750 60 0001 C CNN
+ 1 6700 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L SerialParallel_blk X4
+U 1 1 686FB703
+P 4050 2600
+F 0 "X4" H 4050 2600 60 0000 C CNN
+F 1 "SerialParallel_blk" H 4050 2300 60 0000 C CNN
+F 2 "" H 3200 2900 60 0001 C CNN
+F 3 "" H 3200 2900 60 0001 C CNN
+ 1 4050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L DS_blk X6
+U 1 1 686FB752
+P 5450 2600
+F 0 "X6" H 5450 2600 60 0000 C CNN
+F 1 "DS_blk" H 5450 2350 60 0000 C CNN
+F 2 "" H 5450 2600 60 0001 C CNN
+F 3 "" H 5450 2600 60 0001 C CNN
+ 1 5450 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L DS_blk X7
+U 1 1 686FB79D
+P 6700 2600
+F 0 "X7" H 6700 2600 60 0000 C CNN
+F 1 "DS_blk" H 6700 2350 60 0000 C CNN
+F 2 "" H 6700 2600 60 0001 C CNN
+F 3 "" H 6700 2600 60 0001 C CNN
+ 1 6700 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L DS_blk X8
+U 1 1 686FB8BA
+P 8100 2600
+F 0 "X8" H 8100 2600 60 0000 C CNN
+F 1 "DS_blk" H 8100 2350 60 0000 C CNN
+F 2 "" H 8100 2600 60 0001 C CNN
+F 3 "" H 8100 2600 60 0001 C CNN
+ 1 8100 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L 2_in_and X2
+U 1 1 686FB9B6
+P 3750 4350
+F 0 "X2" H 3800 4350 60 0000 C CNN
+F 1 "2_in_and" H 3750 4100 60 0000 C CNN
+F 2 "" H 4500 4200 60 0001 C CNN
+F 3 "" H 4500 4200 60 0001 C CNN
+ 1 3750 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 2_in_and X3
+U 1 1 686FB9F7
+P 3750 5000
+F 0 "X3" H 3800 5000 60 0000 C CNN
+F 1 "2_in_and" H 3750 4750 60 0000 C CNN
+F 2 "" H 4500 4850 60 0001 C CNN
+F 3 "" H 4500 4850 60 0001 C CNN
+ 1 3750 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L or_2 X5
+U 1 1 686FBA1C
+P 4800 4700
+F 0 "X5" H 4800 4700 60 0000 C CNN
+F 1 "or_2" H 4800 4450 60 0000 C CNN
+F 2 "" H 4800 4700 60 0001 C CNN
+F 3 "" H 4800 4700 60 0001 C CNN
+ 1 4800 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 686FBA57
+P 2950 4400
+F 0 "X1" H 2950 4400 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3000 4200 60 0000 C CNN
+F 2 "" H 2950 4400 60 0001 C CNN
+F 3 "" H 2950 4400 60 0001 C CNN
+ 1 2950 4400
+ 0 -1 -1 0
+$EndComp
+Text Label 2350 4950 0 60 ~ 0
+mode
+Text Label 2450 4400 0 60 ~ 0
+RS
+Text Label 2450 5050 0 60 ~ 0
+LS
+Wire Wire Line
+ 4200 4350 4200 4650
+Wire Wire Line
+ 4200 4650 4400 4650
+Wire Wire Line
+ 4200 5000 4200 4750
+Wire Wire Line
+ 4200 4750 4400 4750
+Wire Wire Line
+ 3250 4300 3350 4300
+Wire Wire Line
+ 3250 2800 3250 4300
+Wire Wire Line
+ 2250 4950 3350 4950
+Wire Wire Line
+ 2950 4950 2950 4800
+Wire Wire Line
+ 2950 3850 7500 3850
+Connection ~ 2950 4950
+Wire Wire Line
+ 3350 4400 2250 4400
+Wire Wire Line
+ 3350 5050 2250 5050
+Wire Wire Line
+ 3500 2800 3250 2800
+Connection ~ 3250 3850
+Wire Wire Line
+ 3500 2700 2800 2700
+Wire Wire Line
+ 2800 2700 2800 4950
+Connection ~ 2800 4950
+Wire Wire Line
+ 8550 2550 8700 2550
+Wire Wire Line
+ 8700 2550 8700 3100
+Wire Wire Line
+ 8700 3100 3450 3100
+Wire Wire Line
+ 3450 3100 3450 2600
+Wire Wire Line
+ 3450 2600 3500 2600
+Wire Wire Line
+ 5900 2550 5950 2550
+Wire Wire Line
+ 5950 2550 5950 4700
+Connection ~ 5950 3100
+Wire Wire Line
+ 7150 2550 7200 2550
+Wire Wire Line
+ 7200 2550 7200 3100
+Connection ~ 7200 3100
+Wire Wire Line
+ 5950 4700 5250 4700
+Wire Wire Line
+ 4700 2700 4550 2700
+Wire Wire Line
+ 4700 1600 4700 2700
+Wire Wire Line
+ 4700 2450 5000 2450
+Wire Wire Line
+ 6050 2650 5900 2650
+Wire Wire Line
+ 6050 1600 6050 2650
+Wire Wire Line
+ 6050 2450 6250 2450
+Wire Wire Line
+ 7400 2650 7150 2650
+Wire Wire Line
+ 7400 1600 7400 2650
+Wire Wire Line
+ 7400 2450 7650 2450
+Wire Wire Line
+ 5000 2550 4750 2550
+Wire Wire Line
+ 4750 2550 4750 3850
+Wire Wire Line
+ 6250 2550 6150 2550
+Wire Wire Line
+ 6150 2550 6150 3850
+Connection ~ 4750 3850
+Wire Wire Line
+ 7650 2550 7500 2550
+Wire Wire Line
+ 7500 2550 7500 3850
+Connection ~ 6150 3850
+Wire Wire Line
+ 5000 2650 4800 2650
+Wire Wire Line
+ 4800 2650 4800 3650
+Wire Wire Line
+ 2800 3650 7550 3650
+Connection ~ 2800 3650
+Wire Wire Line
+ 6200 3650 6200 2650
+Wire Wire Line
+ 6200 2650 6250 2650
+Connection ~ 4800 3650
+Wire Wire Line
+ 7550 3650 7550 2650
+Wire Wire Line
+ 7550 2650 7650 2650
+Connection ~ 6200 3650
+Wire Wire Line
+ 3500 2400 3500 2300
+Wire Wire Line
+ 3500 2300 8800 2300
+Wire Wire Line
+ 8800 2300 8800 4050
+Wire Wire Line
+ 8800 4050 2750 4050
+Wire Wire Line
+ 2750 4050 2750 4800
+Wire Wire Line
+ 2750 4800 2850 4800
+Wire Wire Line
+ 3350 4200 3350 4050
+Connection ~ 3350 4050
+Wire Wire Line
+ 3350 4850 3150 4850
+Wire Wire Line
+ 3150 4850 3150 4050
+Connection ~ 3150 4050
+Wire Wire Line
+ 4350 4550 4350 4050
+Connection ~ 4350 4050
+Wire Wire Line
+ 8550 2450 8550 2300
+Connection ~ 8550 2300
+Wire Wire Line
+ 7150 2450 7150 2300
+Connection ~ 7150 2300
+Wire Wire Line
+ 5900 2450 5900 2300
+Connection ~ 5900 2300
+Wire Wire Line
+ 3050 4800 3050 5350
+Wire Wire Line
+ 8550 2900 4550 2900
+Wire Wire Line
+ 4550 2900 4550 2800
+Connection ~ 8550 2900
+Wire Wire Line
+ 5900 2750 5900 2900
+Connection ~ 5900 2900
+Wire Wire Line
+ 7150 2750 7150 2900
+Connection ~ 7150 2900
+Wire Wire Line
+ 3350 5150 3350 5350
+Connection ~ 3350 5350
+Wire Wire Line
+ 3350 4500 3250 4500
+Wire Wire Line
+ 3250 4500 3250 5350
+Connection ~ 3250 5350
+Wire Wire Line
+ 4350 4850 4350 5350
+Connection ~ 4350 5350
+Wire Wire Line
+ 8550 2750 8550 4200
+Wire Wire Line
+ 8550 4200 6050 4200
+Wire Wire Line
+ 6050 4200 6050 5350
+Wire Wire Line
+ 6050 5350 3050 5350
+Wire Wire Line
+ 8550 2650 8950 2650
+Wire Wire Line
+ 8950 2650 8950 1600
+Connection ~ 7400 2450
+Connection ~ 6050 2450
+Connection ~ 4700 2450
+Wire Wire Line
+ 3500 2500 3350 2500
+Wire Wire Line
+ 5000 2750 5000 3050
+Wire Wire Line
+ 3350 2500 3350 3050
+Wire Wire Line
+ 6250 2750 6250 3050
+Wire Wire Line
+ 7650 2750 7650 3050
+Wire Wire Line
+ 4550 2550 4600 2550
+Wire Wire Line
+ 4600 2550 4600 3050
+Wire Wire Line
+ 4550 2450 4650 2450
+Wire Wire Line
+ 4650 2450 4650 3050
+$Comp
+L PORT U1
+U 4 1 686FDE79
+P 3350 3300
+F 0 "U1" H 3400 3400 30 0000 C CNN
+F 1 "PORT" H 3350 3300 30 0000 C CNN
+F 2 "" H 3350 3300 60 0000 C CNN
+F 3 "" H 3350 3300 60 0000 C CNN
+ 4 3350 3300
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686FDEC4
+P 4600 3300
+F 0 "U1" H 4650 3400 30 0000 C CNN
+F 1 "PORT" H 4600 3300 30 0000 C CNN
+F 2 "" H 4600 3300 60 0000 C CNN
+F 3 "" H 4600 3300 60 0000 C CNN
+ 6 4600 3300
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686FDF2F
+P 4650 3300
+F 0 "U1" H 4700 3400 30 0000 C CNN
+F 1 "PORT" H 4650 3300 30 0000 C CNN
+F 2 "" H 4650 3300 60 0000 C CNN
+F 3 "" H 4650 3300 60 0000 C CNN
+ 7 4650 3300
+ 0 1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686FDFA4
+P 5000 3300
+F 0 "U1" H 5050 3400 30 0000 C CNN
+F 1 "PORT" H 5000 3300 30 0000 C CNN
+F 2 "" H 5000 3300 60 0000 C CNN
+F 3 "" H 5000 3300 60 0000 C CNN
+ 8 5000 3300
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686FE00E
+P 6250 3300
+F 0 "U1" H 6300 3400 30 0000 C CNN
+F 1 "PORT" H 6250 3300 30 0000 C CNN
+F 2 "" H 6250 3300 60 0000 C CNN
+F 3 "" H 6250 3300 60 0000 C CNN
+ 10 6250 3300
+ 0 1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686FE067
+P 7650 3300
+F 0 "U1" H 7700 3400 30 0000 C CNN
+F 1 "PORT" H 7650 3300 30 0000 C CNN
+F 2 "" H 7650 3300 60 0000 C CNN
+F 3 "" H 7650 3300 60 0000 C CNN
+ 12 7650 3300
+ 0 1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 15 1 686FE0F5
+P 8800 2900
+F 0 "U1" H 8850 3000 30 0000 C CNN
+F 1 "PORT" H 8800 2900 30 0000 C CNN
+F 2 "" H 8800 2900 60 0000 C CNN
+F 3 "" H 8800 2900 60 0000 C CNN
+ 15 8800 2900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686FE22E
+P 8550 2050
+F 0 "U1" H 8600 2150 30 0000 C CNN
+F 1 "PORT" H 8550 2050 30 0000 C CNN
+F 2 "" H 8550 2050 60 0000 C CNN
+F 3 "" H 8550 2050 60 0000 C CNN
+ 13 8550 2050
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 14 1 686FE2E8
+P 8700 1600
+F 0 "U1" H 8750 1700 30 0000 C CNN
+F 1 "PORT" H 8700 1600 30 0000 C CNN
+F 2 "" H 8700 1600 60 0000 C CNN
+F 3 "" H 8700 1600 60 0000 C CNN
+ 14 8700 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686FE34F
+P 7150 1600
+F 0 "U1" H 7200 1700 30 0000 C CNN
+F 1 "PORT" H 7150 1600 30 0000 C CNN
+F 2 "" H 7150 1600 60 0000 C CNN
+F 3 "" H 7150 1600 60 0000 C CNN
+ 11 7150 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686FE474
+P 5800 1600
+F 0 "U1" H 5850 1700 30 0000 C CNN
+F 1 "PORT" H 5800 1600 30 0000 C CNN
+F 2 "" H 5800 1600 60 0000 C CNN
+F 3 "" H 5800 1600 60 0000 C CNN
+ 9 5800 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686FE4E5
+P 4450 1600
+F 0 "U1" H 4500 1700 30 0000 C CNN
+F 1 "PORT" H 4450 1600 30 0000 C CNN
+F 2 "" H 4450 1600 60 0000 C CNN
+F 3 "" H 4450 1600 60 0000 C CNN
+ 5 4450 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686FE646
+P 2000 4400
+F 0 "U1" H 2050 4500 30 0000 C CNN
+F 1 "PORT" H 2000 4400 30 0000 C CNN
+F 2 "" H 2000 4400 60 0000 C CNN
+F 3 "" H 2000 4400 60 0000 C CNN
+ 1 2000 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686FE6B7
+P 2000 4950
+F 0 "U1" H 2050 5050 30 0000 C CNN
+F 1 "PORT" H 2000 4950 30 0000 C CNN
+F 2 "" H 2000 4950 60 0000 C CNN
+F 3 "" H 2000 4950 60 0000 C CNN
+ 2 2000 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686FE728
+P 2000 5050
+F 0 "U1" H 2050 5150 30 0000 C CNN
+F 1 "PORT" H 2000 5050 30 0000 C CNN
+F 2 "" H 2000 5050 60 0000 C CNN
+F 3 "" H 2000 5050 60 0000 C CNN
+ 3 2000 5050
+ 1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/SN54L99.sub b/library/SubcircuitLibrary/SN54L99/SN54L99.sub
new file mode 100644
index 000000000..1fc20d442
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SN54L99.sub
@@ -0,0 +1,27 @@
+* Subcircuit SN54L99
+.subckt SN54L99 /rs /mode /ls net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/sn54l99/sn54l99.cir
+.include SerialParallel_blk.sub
+.include or_2.sub
+.include DS_blk.sub
+.include CMOS_INVTR.sub
+.include 2_in_and.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* s c m o d e
+x4 net-_u1-pad7_ net-_u1-pad6_ net-_x4-pad3_ net-_u1-pad4_ /mode net-_x1-pad4_ net-_u1-pad13_ net-_u1-pad15_ net-_u1-pad5_ SerialParallel_blk
+x6 net-_u1-pad5_ net-_x1-pad4_ /mode net-_u1-pad8_ net-_x4-pad3_ net-_u1-pad13_ net-_u1-pad15_ net-_u1-pad9_ DS_blk
+x7 net-_u1-pad9_ net-_x1-pad4_ /mode net-_u1-pad10_ net-_x4-pad3_ net-_u1-pad13_ net-_u1-pad15_ net-_u1-pad11_ DS_blk
+x8 net-_u1-pad11_ net-_x1-pad4_ /mode net-_u1-pad12_ net-_x4-pad3_ net-_u1-pad13_ net-_u1-pad15_ net-_u1-pad14_ DS_blk
+x2 net-_u1-pad13_ net-_x1-pad4_ /rs net-_u1-pad15_ net-_x2-pad5_ 2_in_and
+x3 net-_u1-pad13_ /mode /ls net-_u1-pad15_ net-_x3-pad5_ 2_in_and
+x5 net-_x2-pad5_ net-_x3-pad5_ net-_u1-pad13_ net-_u1-pad15_ net-_x4-pad3_ or_2
+x1 /mode net-_u1-pad13_ net-_u1-pad15_ net-_x1-pad4_ CMOS_INVTR
+* Control Statements
+
+.ends SN54L99
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/SN54L99_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/SN54L99_Previous_Values.xml
new file mode 100644
index 000000000..b4c5d9bf1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SN54L99_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SerialParallel_blk/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/DS_blk/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/DS_blk/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/DS_blk/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/2_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/2_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/or_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/SRFF-cache.lib b/library/SubcircuitLibrary/SN54L99/SRFF-cache.lib
new file mode 100644
index 000000000..eb753a8d1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SRFF-cache.lib
@@ -0,0 +1,76 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# NAND_2
+#
+DEF NAND_2 X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "NAND_2" 50 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+C 350 0 50 0 1 0 N
+P 2 0 1 0 -200 200 150 200 N
+P 3 0 1 0 -200 200 -200 -200 150 -200 N
+X in1 1 -400 50 200 R 50 50 1 1 I
+X Gnd 2 -400 -150 200 R 50 50 1 1 I
+X Vdd 3 -400 150 200 R 50 50 1 1 I
+X out 4 600 0 200 L 50 50 1 1 O
+X in2 5 -400 -50 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/SRFF-rescue.lib b/library/SubcircuitLibrary/SN54L99/SRFF-rescue.lib
new file mode 100644
index 000000000..eb8af4a82
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SRFF-rescue.lib
@@ -0,0 +1,46 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# NAND_2-RESCUE-SRFF
+#
+DEF NAND_2-RESCUE-SRFF X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "NAND_2-RESCUE-SRFF" 400 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 400 0 255 787 -787 0 1 0 N 450 250 450 -250
+C 700 0 0 0 1 0 N
+C 700 0 50 0 1 0 N
+P 2 0 1 0 -300 250 450 250 N
+P 3 0 1 0 -300 250 -300 -250 450 -250 N
+X inA 1 -500 100 200 R 50 50 1 1 I
+X Gnd 2 0 -450 200 U 50 50 1 1 I
+X Vdd 3 0 450 200 D 50 50 1 1 I
+X Out 4 950 0 200 L 50 50 1 1 O
+X inB 5 -500 -100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# NAND_3-RESCUE-SRFF
+#
+DEF NAND_3-RESCUE-SRFF X 0 40 Y Y 1 F N
+F0 "X" 150 0 60 H V C CNN
+F1 "NAND_3-RESCUE-SRFF" 450 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 500 0 255 787 -787 0 1 0 N 550 250 550 -250
+C 800 0 50 0 1 0 N
+P 2 0 1 0 -250 250 550 250 N
+P 3 0 1 0 -250 250 -250 -250 550 -250 N
+X inA 1 -450 150 200 R 50 50 1 1 I
+X inB 2 -450 0 200 R 50 50 1 1 I
+X Gnd 3 0 -450 200 U 50 50 1 1 I
+X Vdd 4 0 450 200 D 50 50 1 1 I
+X Out 5 1050 0 200 L 50 50 1 1 O
+X inC 6 -450 -150 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/SRFF.bak b/library/SubcircuitLibrary/SN54L99/SRFF.bak
new file mode 100644
index 000000000..0b97aaa25
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SRFF.bak
@@ -0,0 +1,255 @@
+EESchema Schematic File Version 2
+LIBS:SRFF-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SRFF-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 685C24CA
+P 10050 1950
+F 0 "scmode1" H 10050 2100 98 0000 C CNB
+F 1 "SKY130mode" H 10050 1850 118 0000 C CNB
+F 2 "" H 10050 2100 60 0001 C CNN
+F 3 "" H 10050 2100 60 0001 C CNN
+ 1 10050 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685C276D
+P 3150 3400
+F 0 "U1" H 3200 3500 30 0000 C CNN
+F 1 "PORT" H 3150 3400 30 0000 C CNN
+F 2 "" H 3150 3400 60 0000 C CNN
+F 3 "" H 3150 3400 60 0000 C CNN
+ 2 3150 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685C27A4
+P 3250 4150
+F 0 "U1" H 3300 4250 30 0000 C CNN
+F 1 "PORT" H 3250 4150 30 0000 C CNN
+F 2 "" H 3250 4150 60 0000 C CNN
+F 3 "" H 3250 4150 60 0000 C CNN
+ 3 3250 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685C27E3
+P 4600 4650
+F 0 "U1" H 4650 4750 30 0000 C CNN
+F 1 "PORT" H 4600 4650 30 0000 C CNN
+F 2 "" H 4600 4650 60 0000 C CNN
+F 3 "" H 4600 4650 60 0000 C CNN
+ 6 4600 4650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685C2893
+P 6200 2700
+F 0 "U1" H 6250 2800 30 0000 C CNN
+F 1 "PORT" H 6200 2700 30 0000 C CNN
+F 2 "" H 6200 2700 60 0000 C CNN
+F 3 "" H 6200 2700 60 0000 C CNN
+ 8 6200 2700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685C28F8
+P 6200 4050
+F 0 "U1" H 6250 4150 30 0000 C CNN
+F 1 "PORT" H 6200 4050 30 0000 C CNN
+F 2 "" H 6200 4050 60 0000 C CNN
+F 3 "" H 6200 4050 60 0000 C CNN
+ 9 6200 4050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685C293F
+P 4350 2150
+F 0 "U1" H 4400 2250 30 0000 C CNN
+F 1 "PORT" H 4350 2150 30 0000 C CNN
+F 2 "" H 4350 2150 60 0000 C CNN
+F 3 "" H 4350 2150 60 0000 C CNN
+ 4 4350 2150
+ 0 1 1 0
+$EndComp
+$Comp
+L NAND_2 X1
+U 1 1 686FA4A9
+P 3900 2650
+F 0 "X1" H 4000 2650 60 0000 C CNN
+F 1 "NAND_2" H 3950 2400 60 0000 C CNN
+F 2 "" H 3900 2650 60 0001 C CNN
+F 3 "" H 3900 2650 60 0001 C CNN
+ 1 3900 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X2
+U 1 1 686FA560
+P 3900 4100
+F 0 "X2" H 4000 4100 60 0000 C CNN
+F 1 "NAND_2" H 3950 3850 60 0000 C CNN
+F 2 "" H 3900 4100 60 0001 C CNN
+F 3 "" H 3900 4100 60 0001 C CNN
+ 1 3900 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X4
+U 1 1 686FA5A9
+P 5250 4050
+F 0 "X4" H 5350 4050 60 0000 C CNN
+F 1 "NAND_2" H 5300 3800 60 0000 C CNN
+F 2 "" H 5250 4050 60 0001 C CNN
+F 3 "" H 5250 4050 60 0001 C CNN
+ 1 5250 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X3
+U 1 1 686FA7E8
+P 5250 2700
+F 0 "X3" H 5350 2700 60 0000 C CNN
+F 1 "NAND_2" H 5300 2450 60 0000 C CNN
+F 2 "" H 5250 2700 60 0001 C CNN
+F 3 "" H 5250 2700 60 0001 C CNN
+ 1 5250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685C2716
+P 3250 2600
+F 0 "U1" H 3300 2700 30 0000 C CNN
+F 1 "PORT" H 3250 2600 30 0000 C CNN
+F 2 "" H 3250 2600 60 0000 C CNN
+F 3 "" H 3250 2600 60 0000 C CNN
+ 1 3250 2600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4850 4000 4750 4000
+Wire Wire Line
+ 4750 4000 4750 3800
+Wire Wire Line
+ 4750 3800 5950 3800
+Wire Wire Line
+ 5950 3800 5950 2700
+Wire Wire Line
+ 5950 2700 5850 2700
+Wire Wire Line
+ 4850 2750 4750 2750
+Wire Wire Line
+ 4750 2750 4750 3000
+Wire Wire Line
+ 4750 3000 5950 3000
+Wire Wire Line
+ 5950 3000 5950 4050
+Wire Wire Line
+ 5950 4050 5850 4050
+Wire Wire Line
+ 4500 2650 4850 2650
+Wire Wire Line
+ 4500 4100 4850 4100
+Wire Wire Line
+ 3400 2700 3500 2700
+Wire Wire Line
+ 3400 2700 3400 4050
+Wire Wire Line
+ 3400 4050 3500 4050
+Connection ~ 3400 3400
+Connection ~ 5950 2700
+Connection ~ 5950 4050
+Wire Wire Line
+ 3500 2500 3500 2400
+Wire Wire Line
+ 3500 2400 4850 2400
+Wire Wire Line
+ 4850 2400 4850 2550
+Wire Wire Line
+ 3500 3750 3500 3950
+Wire Wire Line
+ 3500 3750 4850 3750
+Wire Wire Line
+ 4850 3750 4850 3900
+Wire Wire Line
+ 4850 2850 4850 2950
+Wire Wire Line
+ 4850 2950 3500 2950
+Wire Wire Line
+ 3500 2950 3500 2800
+Wire Wire Line
+ 3500 4250 3500 4400
+Wire Wire Line
+ 3500 4400 4850 4400
+Wire Wire Line
+ 4850 4400 4850 4200
+Wire Wire Line
+ 4350 2400 4350 3750
+Connection ~ 4350 3750
+Connection ~ 4350 2400
+Wire Wire Line
+ 4600 2950 4600 4400
+Connection ~ 4600 4400
+Connection ~ 4600 2950
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/SRFF.cir b/library/SubcircuitLibrary/SN54L99/SRFF.cir
new file mode 100644
index 000000000..9ddfeedb5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SRFF.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SRFF/SRFF.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jul 10 17:19:56 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+X1 Net-_U1-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_X1-Pad4_ Net-_U1-Pad2_ NAND_2
+X2 Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_X2-Pad4_ Net-_U1-Pad3_ NAND_2
+X4 Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad7_ Net-_X2-Pad4_ NAND_2
+X3 Net-_X1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad7_ NAND_2
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/SRFF.cir.out b/library/SubcircuitLibrary/SN54L99/SRFF.cir.out
new file mode 100644
index 000000000..dbe9e83db
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SRFF.cir.out
@@ -0,0 +1,25 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/srff/srff.cir
+
+.include NAND_2.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ port
+x1 net-_u1-pad1_ net-_u1-pad6_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad2_ NAND_2
+x2 net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad4_ net-_u1-pad3_ NAND_2
+x4 net-_u1-pad8_ net-_u1-pad6_ net-_u1-pad4_ net-_u1-pad9_ net-_x2-pad4_ NAND_2
+x3 net-_x1-pad4_ net-_u1-pad6_ net-_u1-pad4_ net-_u1-pad8_ net-_u1-pad9_ NAND_2
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/SRFF.pro b/library/SubcircuitLibrary/SN54L99/SRFF.pro
new file mode 100644
index 000000000..c46505591
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SRFF.pro
@@ -0,0 +1,74 @@
+update=Thu Jul 10 16:57:06 2025
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=SRFF-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/SRFF.sch b/library/SubcircuitLibrary/SN54L99/SRFF.sch
new file mode 100644
index 000000000..1d06e1c86
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SRFF.sch
@@ -0,0 +1,255 @@
+EESchema Schematic File Version 2
+LIBS:SRFF-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SRFF-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 685C24CA
+P 10050 1950
+F 0 "scmode1" H 10050 2100 98 0000 C CNB
+F 1 "SKY130mode" H 10050 1850 118 0000 C CNB
+F 2 "" H 10050 2100 60 0001 C CNN
+F 3 "" H 10050 2100 60 0001 C CNN
+ 1 10050 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685C276D
+P 3150 3400
+F 0 "U1" H 3200 3500 30 0000 C CNN
+F 1 "PORT" H 3150 3400 30 0000 C CNN
+F 2 "" H 3150 3400 60 0000 C CNN
+F 3 "" H 3150 3400 60 0000 C CNN
+ 2 3150 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685C27A4
+P 3250 4150
+F 0 "U1" H 3300 4250 30 0000 C CNN
+F 1 "PORT" H 3250 4150 30 0000 C CNN
+F 2 "" H 3250 4150 60 0000 C CNN
+F 3 "" H 3250 4150 60 0000 C CNN
+ 3 3250 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685C293F
+P 4350 2150
+F 0 "U1" H 4400 2250 30 0000 C CNN
+F 1 "PORT" H 4350 2150 30 0000 C CNN
+F 2 "" H 4350 2150 60 0000 C CNN
+F 3 "" H 4350 2150 60 0000 C CNN
+ 4 4350 2150
+ 0 1 1 0
+$EndComp
+$Comp
+L NAND_2 X1
+U 1 1 686FA4A9
+P 3900 2650
+F 0 "X1" H 4000 2650 60 0000 C CNN
+F 1 "NAND_2" H 3950 2400 60 0000 C CNN
+F 2 "" H 3900 2650 60 0001 C CNN
+F 3 "" H 3900 2650 60 0001 C CNN
+ 1 3900 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X2
+U 1 1 686FA560
+P 3900 4100
+F 0 "X2" H 4000 4100 60 0000 C CNN
+F 1 "NAND_2" H 3950 3850 60 0000 C CNN
+F 2 "" H 3900 4100 60 0001 C CNN
+F 3 "" H 3900 4100 60 0001 C CNN
+ 1 3900 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X4
+U 1 1 686FA5A9
+P 5250 4050
+F 0 "X4" H 5350 4050 60 0000 C CNN
+F 1 "NAND_2" H 5300 3800 60 0000 C CNN
+F 2 "" H 5250 4050 60 0001 C CNN
+F 3 "" H 5250 4050 60 0001 C CNN
+ 1 5250 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X3
+U 1 1 686FA7E8
+P 5250 2700
+F 0 "X3" H 5350 2700 60 0000 C CNN
+F 1 "NAND_2" H 5300 2450 60 0000 C CNN
+F 2 "" H 5250 2700 60 0001 C CNN
+F 3 "" H 5250 2700 60 0001 C CNN
+ 1 5250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685C2716
+P 3250 2600
+F 0 "U1" H 3300 2700 30 0000 C CNN
+F 1 "PORT" H 3250 2600 30 0000 C CNN
+F 2 "" H 3250 2600 60 0000 C CNN
+F 3 "" H 3250 2600 60 0000 C CNN
+ 1 3250 2600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4850 4000 4750 4000
+Wire Wire Line
+ 4750 4000 4750 3800
+Wire Wire Line
+ 4750 3800 5950 3800
+Wire Wire Line
+ 5950 3800 5950 2700
+Wire Wire Line
+ 5950 2700 5850 2700
+Wire Wire Line
+ 4850 2750 4750 2750
+Wire Wire Line
+ 4750 2750 4750 3000
+Wire Wire Line
+ 4750 3000 5950 3000
+Wire Wire Line
+ 5950 3000 5950 4050
+Wire Wire Line
+ 5950 4050 5850 4050
+Wire Wire Line
+ 4500 2650 4850 2650
+Wire Wire Line
+ 4500 4100 4850 4100
+Wire Wire Line
+ 3400 2700 3500 2700
+Wire Wire Line
+ 3400 2700 3400 4050
+Wire Wire Line
+ 3400 4050 3500 4050
+Connection ~ 3400 3400
+Connection ~ 5950 2700
+Connection ~ 5950 4050
+Wire Wire Line
+ 3500 2500 3500 2400
+Wire Wire Line
+ 3500 2400 4850 2400
+Wire Wire Line
+ 4850 2400 4850 2550
+Wire Wire Line
+ 3500 3750 3500 3950
+Wire Wire Line
+ 3500 3750 4850 3750
+Wire Wire Line
+ 4850 3750 4850 3900
+Wire Wire Line
+ 4850 2850 4850 2950
+Wire Wire Line
+ 4850 2950 3500 2950
+Wire Wire Line
+ 3500 2950 3500 2800
+Wire Wire Line
+ 3500 4250 3500 4400
+Wire Wire Line
+ 3500 4400 4850 4400
+Wire Wire Line
+ 4850 4400 4850 4200
+Wire Wire Line
+ 4350 2400 4350 3750
+Connection ~ 4350 3750
+Connection ~ 4350 2400
+Wire Wire Line
+ 4600 2950 4600 4400
+Connection ~ 4600 4400
+Connection ~ 4600 2950
+$Comp
+L PORT U1
+U 5 1 686FC037
+P 4600 4650
+F 0 "U1" H 4650 4750 30 0000 C CNN
+F 1 "PORT" H 4600 4650 30 0000 C CNN
+F 2 "" H 4600 4650 60 0000 C CNN
+F 3 "" H 4600 4650 60 0000 C CNN
+ 5 4600 4650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686FC0E0
+P 6200 2700
+F 0 "U1" H 6250 2800 30 0000 C CNN
+F 1 "PORT" H 6200 2700 30 0000 C CNN
+F 2 "" H 6200 2700 60 0000 C CNN
+F 3 "" H 6200 2700 60 0000 C CNN
+ 6 6200 2700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686FC1DD
+P 6200 4050
+F 0 "U1" H 6250 4150 30 0000 C CNN
+F 1 "PORT" H 6200 4050 30 0000 C CNN
+F 2 "" H 6200 4050 60 0000 C CNN
+F 3 "" H 6200 4050 60 0000 C CNN
+ 7 6200 4050
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/SRFF.sub b/library/SubcircuitLibrary/SN54L99/SRFF.sub
new file mode 100644
index 000000000..31f2380ca
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SRFF.sub
@@ -0,0 +1,19 @@
+* Subcircuit SRFF
+.subckt SRFF net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/srff/srff.cir
+.include NAND_2.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* s c m o d e
+x1 net-_u1-pad1_ net-_u1-pad6_ net-_u1-pad4_ net-_x1-pad4_ net-_u1-pad2_ NAND_2
+x2 net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad4_ net-_x2-pad4_ net-_u1-pad3_ NAND_2
+x4 net-_u1-pad8_ net-_u1-pad6_ net-_u1-pad4_ net-_u1-pad9_ net-_x2-pad4_ NAND_2
+x3 net-_x1-pad4_ net-_u1-pad6_ net-_u1-pad4_ net-_u1-pad8_ net-_u1-pad9_ NAND_2
+* Control Statements
+
+.ends SRFF
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/SRFF_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/SRFF_Previous_Values.xml
new file mode 100644
index 000000000..15c0fb647
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SRFF_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/SerialParallel_blk-cache.lib b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk-cache.lib
new file mode 100644
index 000000000..b32a483e6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk-cache.lib
@@ -0,0 +1,173 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_in_and
+#
+DEF 3_in_and X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "3_in_and" 50 -300 60 H V C CNN
+F2 "" 600 -150 60 H I C CNN
+F3 "" 600 -150 60 H I C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+P 2 0 1 0 -150 250 100 250 N
+P 2 0 1 0 150 250 100 250 N
+P 3 0 1 0 -150 250 -150 -250 150 -250 N
+X in1 1 -350 100 200 R 50 50 1 1 I
+X in2 2 -350 0 200 R 50 50 1 1 I
+X Vdd 3 -350 200 200 R 50 50 1 1 I
+X Gnd 4 -350 -200 200 R 50 50 1 1 I
+X in3 5 -350 -100 200 R 50 50 1 1 I
+X out 6 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_in_and
+#
+DEF 4_in_and X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "4_in_and" -50 -400 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 0 -25 329 813 -813 0 1 0 N 50 300 50 -350
+P 2 0 1 0 -250 300 50 300 N
+P 3 0 1 0 -250 300 -250 -350 50 -350 N
+X Vdd 1 -450 250 200 R 50 50 1 1 I
+X in1 2 -450 150 200 R 50 50 1 1 I
+X in2 3 -450 50 200 R 50 50 1 1 I
+X in3 4 -450 -100 200 R 50 50 1 1 I
+X Gnd 5 -450 -300 200 R 50 50 1 1 I
+X in4 6 -450 -200 200 R 50 50 1 1 I
+X out 7 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_Buf
+#
+DEF CMOS_Buf X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_Buf" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+P 2 0 1 0 -250 150 250 0 N
+P 3 0 1 0 -250 150 -250 -150 250 0 N
+X Vdd 1 -450 100 200 R 50 50 1 1 I
+X Gnd 2 -450 -100 200 R 50 50 1 1 I
+X in 3 -450 0 200 R 50 50 1 1 I
+X Out 4 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NOR_3
+#
+DEF NOR_3 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "NOR_3" -150 -350 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A -600 0 361 563 -563 0 1 0 N -400 300 -400 -300
+A -277 -288 601 1018 287 0 1 0 N -400 300 250 0
+A -277 288 601 -1018 -287 0 1 0 N -400 -300 250 0
+C 300 0 50 0 1 0 N
+X in1 1 -450 100 200 R 50 50 1 1 I
+X in2 2 -450 0 200 R 50 50 1 1 I
+X out 3 550 0 200 L 50 50 1 1 O
+X Gnd 4 -500 -200 200 R 50 50 1 1 I
+X Vdd 5 -500 200 200 R 50 50 1 1 I
+X in3 6 -450 -100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# SRFF
+#
+DEF SRFF X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "SRFF" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 250 300 -150 0 1 0 N
+X S 1 -500 100 200 R 50 50 1 1 I
+X clk 2 -500 0 200 R 50 50 1 1 I
+X R 3 -500 -100 200 R 50 50 1 1 I
+X Vdd 4 -500 200 200 R 50 50 1 1 I
+X Gnd 5 500 -100 200 L 50 50 1 1 I
+X Q 6 500 150 200 L 50 50 1 1 O
+X Qn 7 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.bak b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.bak
new file mode 100644
index 000000000..4784ac42c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.bak
@@ -0,0 +1,557 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4_in_and X5
+U 1 1 686FAC82
+P 4850 2050
+F 0 "X5" H 4850 2050 60 0000 C CNN
+F 1 "4_in_and" H 4800 1650 60 0000 C CNN
+F 2 "" H 4850 2050 60 0001 C CNN
+F 3 "" H 4850 2050 60 0001 C CNN
+ 1 4850 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_in_and X3
+U 1 1 686FACB3
+P 4750 3000
+F 0 "X3" H 4850 3000 60 0000 C CNN
+F 1 "3_in_and" H 4800 2700 60 0000 C CNN
+F 2 "" H 5350 2850 60 0001 C CNN
+F 3 "" H 5350 2850 60 0001 C CNN
+ 1 4750 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_3 X8
+U 1 1 686FAE68
+P 6400 2550
+F 0 "X8" H 6400 2550 60 0000 C CNN
+F 1 "NOR_3" H 6250 2200 60 0000 C CNN
+F 2 "" H 6400 2550 60 0001 C CNN
+F 3 "" H 6400 2550 60 0001 C CNN
+ 1 6400 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_in_and X6
+U 1 1 686FB0C6
+P 4850 4300
+F 0 "X6" H 4850 4300 60 0000 C CNN
+F 1 "4_in_and" H 4800 3900 60 0000 C CNN
+F 2 "" H 4850 4300 60 0001 C CNN
+F 3 "" H 4850 4300 60 0001 C CNN
+ 1 4850 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_in_and X4
+U 1 1 686FB0CD
+P 4750 5250
+F 0 "X4" H 4850 5250 60 0000 C CNN
+F 1 "3_in_and" H 4800 4950 60 0000 C CNN
+F 2 "" H 5350 5100 60 0001 C CNN
+F 3 "" H 5350 5100 60 0001 C CNN
+ 1 4750 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_3 X9
+U 1 1 686FB0D4
+P 6400 4800
+F 0 "X9" H 6400 4800 60 0000 C CNN
+F 1 "NOR_3" H 6250 4450 60 0000 C CNN
+F 2 "" H 6400 4800 60 0001 C CNN
+F 3 "" H 6400 4800 60 0001 C CNN
+ 1 6400 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_Buf X10
+U 1 1 686FB13D
+P 6750 3250
+F 0 "X10" H 6750 3250 60 0000 C CNN
+F 1 "CMOS_Buf" H 6750 3050 60 0000 C CNN
+F 2 "" H 6750 3250 60 0001 C CNN
+F 3 "" H 6750 3250 60 0001 C CNN
+ 1 6750 3250
+ -1 0 0 1
+$EndComp
+$Comp
+L CMOS_Buf X11
+U 1 1 686FB1A8
+P 6750 4000
+F 0 "X11" H 6750 4000 60 0000 C CNN
+F 1 "CMOS_Buf" H 6750 3800 60 0000 C CNN
+F 2 "" H 6750 4000 60 0001 C CNN
+F 3 "" H 6750 4000 60 0001 C CNN
+ 1 6750 4000
+ -1 0 0 1
+$EndComp
+$Comp
+L CMOS_INVTR X12
+U 1 1 686FB1FB
+P 7200 3600
+F 0 "X12" H 7200 3600 60 0000 C CNN
+F 1 "CMOS_INVTR" H 7250 3400 60 0000 C CNN
+F 2 "" H 7200 3600 60 0001 C CNN
+F 3 "" H 7200 3600 60 0001 C CNN
+ 1 7200 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_Buf X7
+U 1 1 686FB24C
+P 6350 3600
+F 0 "X7" H 6350 3600 60 0000 C CNN
+F 1 "CMOS_Buf" H 6350 3400 60 0000 C CNN
+F 2 "" H 6350 3600 60 0001 C CNN
+F 3 "" H 6350 3600 60 0001 C CNN
+ 1 6350 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L SRFF X13
+U 1 1 686FB30D
+P 8800 3600
+F 0 "X13" H 8800 3600 60 0000 C CNN
+F 1 "SRFF" H 8800 3400 60 0000 C CNN
+F 2 "" H 8800 3600 60 0001 C CNN
+F 3 "" H 8800 3600 60 0001 C CNN
+ 1 8800 3600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5350 2050 5350 2450
+Wire Wire Line
+ 5350 2450 5950 2450
+Wire Wire Line
+ 5300 3000 5350 3000
+Wire Wire Line
+ 5350 3000 5350 2550
+Wire Wire Line
+ 5350 2550 5950 2550
+Wire Wire Line
+ 6300 3250 5400 3250
+Wire Wire Line
+ 5400 3250 5400 2650
+Wire Wire Line
+ 5400 2650 5950 2650
+Wire Wire Line
+ 5350 4300 5350 4800
+Wire Wire Line
+ 5350 4800 5950 4800
+Wire Wire Line
+ 5300 5250 5350 5250
+Wire Wire Line
+ 5350 5250 5350 4900
+Wire Wire Line
+ 5350 4900 5950 4900
+Wire Wire Line
+ 6300 4000 5400 4000
+Wire Wire Line
+ 5400 4000 5400 4700
+Wire Wire Line
+ 5400 4700 5950 4700
+Wire Wire Line
+ 4400 2150 4200 2150
+Wire Wire Line
+ 4200 2150 4200 5150
+Wire Wire Line
+ 4200 4400 4400 4400
+Wire Wire Line
+ 4200 5150 4400 5150
+Connection ~ 4200 4400
+Wire Wire Line
+ 4400 2900 4200 2900
+Connection ~ 4200 2900
+Wire Wire Line
+ 7200 3250 8150 3250
+Wire Wire Line
+ 7750 3600 8300 3600
+Wire Wire Line
+ 8150 3250 8150 3500
+Wire Wire Line
+ 8150 3500 8300 3500
+Wire Wire Line
+ 7200 4000 8150 4000
+Wire Wire Line
+ 8150 4000 8150 3700
+Wire Wire Line
+ 8150 3700 8300 3700
+Wire Wire Line
+ 6950 4800 8000 4800
+Wire Wire Line
+ 8000 4800 8000 3250
+Connection ~ 8000 3250
+Wire Wire Line
+ 8050 4000 8050 2550
+Connection ~ 8050 4000
+Wire Wire Line
+ 8050 2550 6950 2550
+Wire Wire Line
+ 4400 1900 4200 1900
+Wire Wire Line
+ 4200 1900 4200 1650
+Wire Wire Line
+ 4200 1650 9550 1650
+Wire Wire Line
+ 9550 1650 9550 3550
+Wire Wire Line
+ 9550 3550 9300 3550
+Wire Wire Line
+ 9300 3450 10150 3450
+Wire Wire Line
+ 9600 3450 9600 5600
+Wire Wire Line
+ 9600 5600 4100 5600
+Wire Wire Line
+ 4100 5600 4100 4250
+Wire Wire Line
+ 4100 4250 4400 4250
+Connection ~ 9600 3450
+Wire Wire Line
+ 2800 2000 4400 2000
+Wire Wire Line
+ 4400 2250 4300 2250
+Wire Wire Line
+ 4300 2250 4300 6250
+Wire Wire Line
+ 4300 6250 4200 6250
+Wire Wire Line
+ 4400 4500 4300 4500
+Connection ~ 4300 4500
+$Comp
+L CMOS_INVTR X1
+U 1 1 686FBB09
+P 3850 4150
+F 0 "X1" H 3850 4150 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3900 3950 60 0000 C CNN
+F 2 "" H 3850 4150 60 0001 C CNN
+F 3 "" H 3850 4150 60 0001 C CNN
+ 1 3850 4150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3450 4150 2800 4150
+Text Label 2900 4150 0 60 ~ 0
+K
+Text Label 2950 2000 0 60 ~ 0
+J
+$Comp
+L CMOS_INVTR X2
+U 1 1 686FBC8F
+P 3850 5350
+F 0 "X2" H 3850 5350 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3900 5150 60 0000 C CNN
+F 2 "" H 3850 5350 60 0001 C CNN
+F 3 "" H 3850 5350 60 0001 C CNN
+ 1 3850 5350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3450 5350 2850 5350
+Text Label 2950 5350 0 60 ~ 0
+A
+Wire Wire Line
+ 3300 5350 3300 3100
+Wire Wire Line
+ 3300 3100 4400 3100
+Connection ~ 3300 5350
+Wire Wire Line
+ 4400 3000 3750 3000
+Wire Wire Line
+ 3750 3000 3750 6250
+Wire Wire Line
+ 3750 6250 3650 6250
+Text Label 4300 5900 0 60 ~ 0
+M_bar
+Text Label 3750 5900 0 60 ~ 0
+M
+Wire Wire Line
+ 4400 5250 3850 5250
+Wire Wire Line
+ 3850 5250 3850 5150
+Wire Wire Line
+ 3850 5150 3750 5150
+Connection ~ 3750 5150
+Wire Wire Line
+ 4400 1800 4400 1700
+Wire Wire Line
+ 3450 1700 8300 1700
+Wire Wire Line
+ 8300 1700 8300 3400
+Wire Wire Line
+ 5900 2350 5900 1700
+Connection ~ 5900 1700
+Wire Wire Line
+ 7200 3350 8300 3350
+Connection ~ 8300 3350
+Wire Wire Line
+ 6800 3500 6800 3400
+Wire Wire Line
+ 5450 3400 7300 3400
+Wire Wire Line
+ 7300 3400 7300 3350
+Connection ~ 7300 3350
+Wire Wire Line
+ 5900 3500 5900 3400
+Connection ~ 6800 3400
+Wire Wire Line
+ 4400 2700 4400 2800
+Wire Wire Line
+ 4400 2700 5450 2700
+Wire Wire Line
+ 5450 2700 5450 3400
+Connection ~ 5900 3400
+Wire Wire Line
+ 7200 4100 7550 4100
+Wire Wire Line
+ 7550 4100 7550 3350
+Connection ~ 7550 3350
+Wire Wire Line
+ 4400 4050 4400 4000
+Wire Wire Line
+ 4400 4000 3450 4000
+Wire Wire Line
+ 3450 1700 3450 4050
+Wire Wire Line
+ 4400 5050 3450 5050
+Wire Wire Line
+ 3450 5050 3450 5250
+Wire Wire Line
+ 3900 5050 3900 4000
+Connection ~ 3900 4000
+Connection ~ 3900 5050
+Wire Wire Line
+ 5900 4600 5250 4600
+Wire Wire Line
+ 5250 4600 5250 4850
+Wire Wire Line
+ 5250 4850 3900 4850
+Connection ~ 3900 4850
+Connection ~ 4400 1700
+Connection ~ 3450 4000
+Wire Wire Line
+ 4400 2350 4350 2350
+Wire Wire Line
+ 4350 2350 4350 5650
+Wire Wire Line
+ 4350 3200 4400 3200
+Wire Wire Line
+ 3450 4600 4400 4600
+Connection ~ 4350 3200
+Wire Wire Line
+ 4350 5450 4400 5450
+Connection ~ 4350 4600
+Wire Wire Line
+ 3450 4600 3450 4250
+Wire Wire Line
+ 3450 5450 3450 5650
+Wire Wire Line
+ 3450 5650 9300 5650
+Connection ~ 4350 5450
+Wire Wire Line
+ 5900 5650 5900 5000
+Connection ~ 4350 5650
+Wire Wire Line
+ 9300 5650 9300 3700
+Connection ~ 5900 5650
+Wire Wire Line
+ 5900 2750 5650 2750
+Wire Wire Line
+ 5650 2750 5650 5650
+Connection ~ 5650 5650
+Wire Wire Line
+ 5900 3700 5650 3700
+Connection ~ 5650 3700
+Wire Wire Line
+ 7200 3150 7200 3050
+Wire Wire Line
+ 7200 3050 5650 3050
+Connection ~ 5650 3050
+Wire Wire Line
+ 7200 3900 7200 3850
+Wire Wire Line
+ 7200 3850 7100 3850
+Wire Wire Line
+ 7100 3850 7100 3050
+Connection ~ 7100 3050
+Wire Wire Line
+ 6800 3700 6800 3750
+Wire Wire Line
+ 6800 3750 7100 3750
+Connection ~ 7100 3750
+Wire Wire Line
+ 5900 3600 2850 3600
+Text Label 3050 3600 0 60 ~ 0
+clk
+Text Label 9950 3450 0 60 ~ 0
+Qa
+$Comp
+L PORT U1
+U 1 1 686FD4D2
+P 2550 2000
+F 0 "U1" H 2600 2100 30 0000 C CNN
+F 1 "PORT" H 2550 2000 30 0000 C CNN
+F 2 "" H 2550 2000 60 0000 C CNN
+F 3 "" H 2550 2000 60 0000 C CNN
+ 1 2550 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686FD5E7
+P 2600 3600
+F 0 "U1" H 2650 3700 30 0000 C CNN
+F 1 "PORT" H 2600 3600 30 0000 C CNN
+F 2 "" H 2600 3600 60 0000 C CNN
+F 3 "" H 2600 3600 60 0000 C CNN
+ 3 2600 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686FD6BF
+P 2550 4150
+F 0 "U1" H 2600 4250 30 0000 C CNN
+F 1 "PORT" H 2550 4150 30 0000 C CNN
+F 2 "" H 2550 4150 60 0000 C CNN
+F 3 "" H 2550 4150 60 0000 C CNN
+ 2 2550 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686FD754
+P 2600 5350
+F 0 "U1" H 2650 5450 30 0000 C CNN
+F 1 "PORT" H 2600 5350 30 0000 C CNN
+F 2 "" H 2600 5350 60 0000 C CNN
+F 3 "" H 2600 5350 60 0000 C CNN
+ 4 2600 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686FD7DF
+P 3400 6250
+F 0 "U1" H 3450 6350 30 0000 C CNN
+F 1 "PORT" H 3400 6250 30 0000 C CNN
+F 2 "" H 3400 6250 60 0000 C CNN
+F 3 "" H 3400 6250 60 0000 C CNN
+ 5 3400 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686FD820
+P 3950 6250
+F 0 "U1" H 4000 6350 30 0000 C CNN
+F 1 "PORT" H 3950 6250 30 0000 C CNN
+F 2 "" H 3950 6250 60 0000 C CNN
+F 3 "" H 3950 6250 60 0000 C CNN
+ 6 3950 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686FD956
+P 10400 3450
+F 0 "U1" H 10450 3550 30 0000 C CNN
+F 1 "PORT" H 10400 3450 30 0000 C CNN
+F 2 "" H 10400 3450 60 0000 C CNN
+F 3 "" H 10400 3450 60 0000 C CNN
+ 9 10400 3450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686FDA9B
+P 8550 3150
+F 0 "U1" H 8600 3250 30 0000 C CNN
+F 1 "PORT" H 8550 3150 30 0000 C CNN
+F 2 "" H 8550 3150 60 0000 C CNN
+F 3 "" H 8550 3150 60 0000 C CNN
+ 7 8550 3150
+ -1 0 0 1
+$EndComp
+Connection ~ 8300 3150
+Connection ~ 9300 4000
+$Comp
+L PORT U1
+U 8 1 686FDB8D
+P 9050 4000
+F 0 "U1" H 9100 4100 30 0000 C CNN
+F 1 "PORT" H 9050 4000 30 0000 C CNN
+F 2 "" H 9050 4000 60 0000 C CNN
+F 3 "" H 9050 4000 60 0000 C CNN
+ 8 9050 4000
+ 1 0 0 -1
+$EndComp
+Connection ~ 4200 3600
+$Comp
+L SKY130mode scmode1
+U 1 1 686FE421
+P 6300 6600
+F 0 "scmode1" H 6300 6750 98 0000 C CNB
+F 1 "SKY130mode" H 6300 6500 118 0000 C CNB
+F 2 "" H 6300 6750 60 0001 C CNN
+F 3 "" H 6300 6750 60 0001 C CNN
+ 1 6300 6600
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.cir b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.cir
new file mode 100644
index 000000000..059a1c5d0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.cir
@@ -0,0 +1,25 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SerialParallel_blk/SerialParallel_blk.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jul 10 18:13:44 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X5 Net-_U1-Pad7_ Net-_X13-Pad7_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad6_ Net-_X5-Pad7_ 4_in_and
+X3 Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad4_ Net-_X3-Pad6_ 3_in_and
+X8 Net-_X5-Pad7_ Net-_X3-Pad6_ Net-_X11-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_X10-Pad4_ NOR_3
+X6 Net-_U1-Pad7_ Net-_X1-Pad4_ Net-_U1-Pad9_ Net-_U1-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad6_ Net-_X6-Pad7_ 4_in_and
+X4 Net-_U1-Pad3_ Net-_U1-Pad5_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_X2-Pad4_ Net-_X4-Pad6_ 3_in_and
+X9 Net-_X11-Pad4_ Net-_X6-Pad7_ Net-_X10-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_X4-Pad6_ NOR_3
+X10 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_X10-Pad3_ Net-_X10-Pad4_ CMOS_Buf
+X11 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_X11-Pad3_ Net-_X11-Pad4_ CMOS_Buf
+X12 Net-_X12-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_X12-Pad4_ CMOS_INVTR
+X7 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad3_ Net-_X12-Pad1_ CMOS_Buf
+X13 Net-_X10-Pad3_ Net-_X12-Pad4_ Net-_X11-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_X13-Pad7_ SRFF
+X1 Net-_U1-Pad2_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_X1-Pad4_ CMOS_INVTR
+X2 Net-_U1-Pad4_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_X2-Pad4_ CMOS_INVTR
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.cir.out b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.cir.out
new file mode 100644
index 000000000..e080aa9f9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.cir.out
@@ -0,0 +1,39 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/serialparallel_blk/serialparallel_blk.cir
+
+.include CMOS_Buf.sub
+.include 4_in_and.sub
+.include SRFF.sub
+.include 3_in_and.sub
+.include CMOS_INVTR.sub
+.include NOR_3.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+x5 net-_u1-pad7_ net-_x13-pad7_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad8_ net-_u1-pad6_ net-_x5-pad7_ 4_in_and
+x3 net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad4_ net-_x3-pad6_ 3_in_and
+x8 net-_x5-pad7_ net-_x3-pad6_ net-_x11-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_x10-pad4_ NOR_3
+x6 net-_u1-pad7_ net-_x1-pad4_ net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad8_ net-_u1-pad6_ net-_x6-pad7_ 4_in_and
+x4 net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad7_ net-_u1-pad8_ net-_x2-pad4_ net-_x4-pad6_ 3_in_and
+x9 net-_x11-pad4_ net-_x6-pad7_ net-_x10-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_x4-pad6_ NOR_3
+x10 net-_u1-pad7_ net-_u1-pad8_ net-_x10-pad3_ net-_x10-pad4_ CMOS_Buf
+x11 net-_u1-pad7_ net-_u1-pad8_ net-_x11-pad3_ net-_x11-pad4_ CMOS_Buf
+x12 net-_x12-pad1_ net-_u1-pad7_ net-_u1-pad8_ net-_x12-pad4_ CMOS_INVTR
+x7 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad3_ net-_x12-pad1_ CMOS_Buf
+x13 net-_x10-pad3_ net-_x12-pad4_ net-_x11-pad3_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_x13-pad7_ SRFF
+x1 net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad8_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_u1-pad4_ net-_u1-pad7_ net-_u1-pad8_ net-_x2-pad4_ CMOS_INVTR
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.pro b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.sch b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.sch
new file mode 100644
index 000000000..650c73878
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.sch
@@ -0,0 +1,543 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4_in_and X5
+U 1 1 686FAC82
+P 4850 2050
+F 0 "X5" H 4850 2050 60 0000 C CNN
+F 1 "4_in_and" H 4800 1650 60 0000 C CNN
+F 2 "" H 4850 2050 60 0001 C CNN
+F 3 "" H 4850 2050 60 0001 C CNN
+ 1 4850 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_in_and X3
+U 1 1 686FACB3
+P 4750 3000
+F 0 "X3" H 4850 3000 60 0000 C CNN
+F 1 "3_in_and" H 4800 2700 60 0000 C CNN
+F 2 "" H 5350 2850 60 0001 C CNN
+F 3 "" H 5350 2850 60 0001 C CNN
+ 1 4750 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_3 X8
+U 1 1 686FAE68
+P 6400 2550
+F 0 "X8" H 6400 2550 60 0000 C CNN
+F 1 "NOR_3" H 6250 2200 60 0000 C CNN
+F 2 "" H 6400 2550 60 0001 C CNN
+F 3 "" H 6400 2550 60 0001 C CNN
+ 1 6400 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_in_and X6
+U 1 1 686FB0C6
+P 4850 4300
+F 0 "X6" H 4850 4300 60 0000 C CNN
+F 1 "4_in_and" H 4800 3900 60 0000 C CNN
+F 2 "" H 4850 4300 60 0001 C CNN
+F 3 "" H 4850 4300 60 0001 C CNN
+ 1 4850 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_in_and X4
+U 1 1 686FB0CD
+P 4750 5250
+F 0 "X4" H 4850 5250 60 0000 C CNN
+F 1 "3_in_and" H 4800 4950 60 0000 C CNN
+F 2 "" H 5350 5100 60 0001 C CNN
+F 3 "" H 5350 5100 60 0001 C CNN
+ 1 4750 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_3 X9
+U 1 1 686FB0D4
+P 6400 4800
+F 0 "X9" H 6400 4800 60 0000 C CNN
+F 1 "NOR_3" H 6250 4450 60 0000 C CNN
+F 2 "" H 6400 4800 60 0001 C CNN
+F 3 "" H 6400 4800 60 0001 C CNN
+ 1 6400 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_Buf X10
+U 1 1 686FB13D
+P 6750 3250
+F 0 "X10" H 6750 3250 60 0000 C CNN
+F 1 "CMOS_Buf" H 6750 3050 60 0000 C CNN
+F 2 "" H 6750 3250 60 0001 C CNN
+F 3 "" H 6750 3250 60 0001 C CNN
+ 1 6750 3250
+ -1 0 0 1
+$EndComp
+$Comp
+L CMOS_Buf X11
+U 1 1 686FB1A8
+P 6750 4000
+F 0 "X11" H 6750 4000 60 0000 C CNN
+F 1 "CMOS_Buf" H 6750 3800 60 0000 C CNN
+F 2 "" H 6750 4000 60 0001 C CNN
+F 3 "" H 6750 4000 60 0001 C CNN
+ 1 6750 4000
+ -1 0 0 1
+$EndComp
+$Comp
+L CMOS_INVTR X12
+U 1 1 686FB1FB
+P 7200 3600
+F 0 "X12" H 7200 3600 60 0000 C CNN
+F 1 "CMOS_INVTR" H 7250 3400 60 0000 C CNN
+F 2 "" H 7200 3600 60 0001 C CNN
+F 3 "" H 7200 3600 60 0001 C CNN
+ 1 7200 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_Buf X7
+U 1 1 686FB24C
+P 6350 3600
+F 0 "X7" H 6350 3600 60 0000 C CNN
+F 1 "CMOS_Buf" H 6350 3400 60 0000 C CNN
+F 2 "" H 6350 3600 60 0001 C CNN
+F 3 "" H 6350 3600 60 0001 C CNN
+ 1 6350 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L SRFF X13
+U 1 1 686FB30D
+P 8800 3600
+F 0 "X13" H 8800 3600 60 0000 C CNN
+F 1 "SRFF" H 8800 3400 60 0000 C CNN
+F 2 "" H 8800 3600 60 0001 C CNN
+F 3 "" H 8800 3600 60 0001 C CNN
+ 1 8800 3600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5350 2050 5350 2450
+Wire Wire Line
+ 5350 2450 5950 2450
+Wire Wire Line
+ 5300 3000 5350 3000
+Wire Wire Line
+ 5350 3000 5350 2550
+Wire Wire Line
+ 5350 2550 5950 2550
+Wire Wire Line
+ 6300 3250 5400 3250
+Wire Wire Line
+ 5400 3250 5400 2650
+Wire Wire Line
+ 5400 2650 5950 2650
+Wire Wire Line
+ 5350 4300 5350 4800
+Wire Wire Line
+ 5350 4800 5950 4800
+Wire Wire Line
+ 5300 5250 5350 5250
+Wire Wire Line
+ 5350 5250 5350 4900
+Wire Wire Line
+ 5350 4900 5950 4900
+Wire Wire Line
+ 6300 4000 5400 4000
+Wire Wire Line
+ 5400 4000 5400 4700
+Wire Wire Line
+ 5400 4700 5950 4700
+Wire Wire Line
+ 4400 2150 4200 2150
+Wire Wire Line
+ 4200 2150 4200 5150
+Wire Wire Line
+ 4200 4400 4400 4400
+Wire Wire Line
+ 4200 5150 4400 5150
+Connection ~ 4200 4400
+Wire Wire Line
+ 4400 2900 4200 2900
+Connection ~ 4200 2900
+Wire Wire Line
+ 7200 3250 8150 3250
+Wire Wire Line
+ 7750 3600 8300 3600
+Wire Wire Line
+ 8150 3250 8150 3500
+Wire Wire Line
+ 8150 3500 8300 3500
+Wire Wire Line
+ 7200 4000 8150 4000
+Wire Wire Line
+ 8150 4000 8150 3700
+Wire Wire Line
+ 8150 3700 8300 3700
+Wire Wire Line
+ 6950 4800 8000 4800
+Wire Wire Line
+ 8000 4800 8000 3250
+Connection ~ 8000 3250
+Wire Wire Line
+ 8050 4000 8050 2550
+Connection ~ 8050 4000
+Wire Wire Line
+ 8050 2550 6950 2550
+Wire Wire Line
+ 4400 1900 4200 1900
+Wire Wire Line
+ 4200 1900 4200 1650
+Wire Wire Line
+ 4200 1650 9550 1650
+Wire Wire Line
+ 9550 1650 9550 3550
+Wire Wire Line
+ 9550 3550 9300 3550
+Wire Wire Line
+ 9300 3450 10150 3450
+Wire Wire Line
+ 9600 3450 9600 5600
+Wire Wire Line
+ 9600 5600 4100 5600
+Wire Wire Line
+ 4100 5600 4100 4250
+Wire Wire Line
+ 4100 4250 4400 4250
+Connection ~ 9600 3450
+Wire Wire Line
+ 2800 2000 4400 2000
+Wire Wire Line
+ 4400 2250 4300 2250
+Wire Wire Line
+ 4300 2250 4300 6250
+Wire Wire Line
+ 4300 6250 4200 6250
+Wire Wire Line
+ 4400 4500 4300 4500
+Connection ~ 4300 4500
+$Comp
+L CMOS_INVTR X1
+U 1 1 686FBB09
+P 3850 4150
+F 0 "X1" H 3850 4150 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3900 3950 60 0000 C CNN
+F 2 "" H 3850 4150 60 0001 C CNN
+F 3 "" H 3850 4150 60 0001 C CNN
+ 1 3850 4150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3450 4150 2800 4150
+$Comp
+L CMOS_INVTR X2
+U 1 1 686FBC8F
+P 3850 5350
+F 0 "X2" H 3850 5350 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3900 5150 60 0000 C CNN
+F 2 "" H 3850 5350 60 0001 C CNN
+F 3 "" H 3850 5350 60 0001 C CNN
+ 1 3850 5350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3450 5350 2850 5350
+Wire Wire Line
+ 3300 5350 3300 3100
+Wire Wire Line
+ 3300 3100 4400 3100
+Connection ~ 3300 5350
+Wire Wire Line
+ 4400 3000 3750 3000
+Wire Wire Line
+ 3750 3000 3750 6250
+Wire Wire Line
+ 3750 6250 3650 6250
+Wire Wire Line
+ 4400 5250 3850 5250
+Wire Wire Line
+ 3850 5250 3850 5150
+Wire Wire Line
+ 3850 5150 3750 5150
+Connection ~ 3750 5150
+Wire Wire Line
+ 4400 1800 4400 1700
+Wire Wire Line
+ 3450 1700 8300 1700
+Wire Wire Line
+ 8300 1700 8300 3400
+Wire Wire Line
+ 5900 2350 5900 1700
+Connection ~ 5900 1700
+Wire Wire Line
+ 7200 3350 8300 3350
+Connection ~ 8300 3350
+Wire Wire Line
+ 6800 3500 6800 3400
+Wire Wire Line
+ 5450 3400 7300 3400
+Wire Wire Line
+ 7300 3400 7300 3350
+Connection ~ 7300 3350
+Wire Wire Line
+ 5900 3500 5900 3400
+Connection ~ 6800 3400
+Wire Wire Line
+ 4400 2700 4400 2800
+Wire Wire Line
+ 4400 2700 5450 2700
+Wire Wire Line
+ 5450 2700 5450 3400
+Connection ~ 5900 3400
+Wire Wire Line
+ 7200 4100 7550 4100
+Wire Wire Line
+ 7550 4100 7550 3350
+Connection ~ 7550 3350
+Wire Wire Line
+ 4400 4050 4400 4000
+Wire Wire Line
+ 4400 4000 3450 4000
+Wire Wire Line
+ 3450 1700 3450 4050
+Wire Wire Line
+ 4400 5050 3450 5050
+Wire Wire Line
+ 3450 5050 3450 5250
+Wire Wire Line
+ 3900 5050 3900 4000
+Connection ~ 3900 4000
+Connection ~ 3900 5050
+Wire Wire Line
+ 5900 4600 5250 4600
+Wire Wire Line
+ 5250 4600 5250 4850
+Wire Wire Line
+ 5250 4850 3900 4850
+Connection ~ 3900 4850
+Connection ~ 4400 1700
+Connection ~ 3450 4000
+Wire Wire Line
+ 4400 2350 4350 2350
+Wire Wire Line
+ 4350 2350 4350 5650
+Wire Wire Line
+ 4350 3200 4400 3200
+Wire Wire Line
+ 3450 4600 4400 4600
+Connection ~ 4350 3200
+Wire Wire Line
+ 4350 5450 4400 5450
+Connection ~ 4350 4600
+Wire Wire Line
+ 3450 4600 3450 4250
+Wire Wire Line
+ 3450 5450 3450 5650
+Wire Wire Line
+ 3450 5650 9300 5650
+Connection ~ 4350 5450
+Wire Wire Line
+ 5900 5650 5900 5000
+Connection ~ 4350 5650
+Wire Wire Line
+ 9300 5650 9300 3700
+Connection ~ 5900 5650
+Wire Wire Line
+ 5900 2750 5650 2750
+Wire Wire Line
+ 5650 2750 5650 5650
+Connection ~ 5650 5650
+Wire Wire Line
+ 5900 3700 5650 3700
+Connection ~ 5650 3700
+Wire Wire Line
+ 7200 3150 7200 3050
+Wire Wire Line
+ 7200 3050 5650 3050
+Connection ~ 5650 3050
+Wire Wire Line
+ 7200 3900 7200 3850
+Wire Wire Line
+ 7200 3850 7100 3850
+Wire Wire Line
+ 7100 3850 7100 3050
+Connection ~ 7100 3050
+Wire Wire Line
+ 6800 3700 6800 3750
+Wire Wire Line
+ 6800 3750 7100 3750
+Connection ~ 7100 3750
+Wire Wire Line
+ 5900 3600 2850 3600
+$Comp
+L PORT U1
+U 1 1 686FD4D2
+P 2550 2000
+F 0 "U1" H 2600 2100 30 0000 C CNN
+F 1 "PORT" H 2550 2000 30 0000 C CNN
+F 2 "" H 2550 2000 60 0000 C CNN
+F 3 "" H 2550 2000 60 0000 C CNN
+ 1 2550 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686FD5E7
+P 2600 3600
+F 0 "U1" H 2650 3700 30 0000 C CNN
+F 1 "PORT" H 2600 3600 30 0000 C CNN
+F 2 "" H 2600 3600 60 0000 C CNN
+F 3 "" H 2600 3600 60 0000 C CNN
+ 3 2600 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686FD6BF
+P 2550 4150
+F 0 "U1" H 2600 4250 30 0000 C CNN
+F 1 "PORT" H 2550 4150 30 0000 C CNN
+F 2 "" H 2550 4150 60 0000 C CNN
+F 3 "" H 2550 4150 60 0000 C CNN
+ 2 2550 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686FD754
+P 2600 5350
+F 0 "U1" H 2650 5450 30 0000 C CNN
+F 1 "PORT" H 2600 5350 30 0000 C CNN
+F 2 "" H 2600 5350 60 0000 C CNN
+F 3 "" H 2600 5350 60 0000 C CNN
+ 4 2600 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686FD7DF
+P 3400 6250
+F 0 "U1" H 3450 6350 30 0000 C CNN
+F 1 "PORT" H 3400 6250 30 0000 C CNN
+F 2 "" H 3400 6250 60 0000 C CNN
+F 3 "" H 3400 6250 60 0000 C CNN
+ 5 3400 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686FD820
+P 3950 6250
+F 0 "U1" H 4000 6350 30 0000 C CNN
+F 1 "PORT" H 3950 6250 30 0000 C CNN
+F 2 "" H 3950 6250 60 0000 C CNN
+F 3 "" H 3950 6250 60 0000 C CNN
+ 6 3950 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686FD956
+P 10400 3450
+F 0 "U1" H 10450 3550 30 0000 C CNN
+F 1 "PORT" H 10400 3450 30 0000 C CNN
+F 2 "" H 10400 3450 60 0000 C CNN
+F 3 "" H 10400 3450 60 0000 C CNN
+ 9 10400 3450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686FDA9B
+P 8550 3150
+F 0 "U1" H 8600 3250 30 0000 C CNN
+F 1 "PORT" H 8550 3150 30 0000 C CNN
+F 2 "" H 8550 3150 60 0000 C CNN
+F 3 "" H 8550 3150 60 0000 C CNN
+ 7 8550 3150
+ -1 0 0 1
+$EndComp
+Connection ~ 8300 3150
+Connection ~ 9300 4000
+$Comp
+L PORT U1
+U 8 1 686FDB8D
+P 9050 4000
+F 0 "U1" H 9100 4100 30 0000 C CNN
+F 1 "PORT" H 9050 4000 30 0000 C CNN
+F 2 "" H 9050 4000 60 0000 C CNN
+F 3 "" H 9050 4000 60 0000 C CNN
+ 8 9050 4000
+ 1 0 0 -1
+$EndComp
+Connection ~ 4200 3600
+$Comp
+L SKY130mode scmode1
+U 1 1 686FE421
+P 6300 6600
+F 0 "scmode1" H 6300 6750 98 0000 C CNB
+F 1 "SKY130mode" H 6300 6500 118 0000 C CNB
+F 2 "" H 6300 6750 60 0001 C CNN
+F 3 "" H 6300 6750 60 0001 C CNN
+ 1 6300 6600
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.sub b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.sub
new file mode 100644
index 000000000..683b229ba
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk.sub
@@ -0,0 +1,33 @@
+* Subcircuit SerialParallel_blk
+.subckt SerialParallel_blk net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/serialparallel_blk/serialparallel_blk.cir
+.include CMOS_Buf.sub
+.include 4_in_and.sub
+.include SRFF.sub
+.include 3_in_and.sub
+.include CMOS_INVTR.sub
+.include NOR_3.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+x5 net-_u1-pad7_ net-_x13-pad7_ net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad8_ net-_u1-pad6_ net-_x5-pad7_ 4_in_and
+x3 net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad4_ net-_x3-pad6_ 3_in_and
+x8 net-_x5-pad7_ net-_x3-pad6_ net-_x11-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_x10-pad4_ NOR_3
+x6 net-_u1-pad7_ net-_x1-pad4_ net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad8_ net-_u1-pad6_ net-_x6-pad7_ 4_in_and
+x4 net-_u1-pad3_ net-_u1-pad5_ net-_u1-pad7_ net-_u1-pad8_ net-_x2-pad4_ net-_x4-pad6_ 3_in_and
+x9 net-_x11-pad4_ net-_x6-pad7_ net-_x10-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_x4-pad6_ NOR_3
+x10 net-_u1-pad7_ net-_u1-pad8_ net-_x10-pad3_ net-_x10-pad4_ CMOS_Buf
+x11 net-_u1-pad7_ net-_u1-pad8_ net-_x11-pad3_ net-_x11-pad4_ CMOS_Buf
+x12 net-_x12-pad1_ net-_u1-pad7_ net-_u1-pad8_ net-_x12-pad4_ CMOS_INVTR
+x7 net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad3_ net-_x12-pad1_ CMOS_Buf
+x13 net-_x10-pad3_ net-_x12-pad4_ net-_x11-pad3_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_x13-pad7_ SRFF
+x1 net-_u1-pad2_ net-_u1-pad7_ net-_u1-pad8_ net-_x1-pad4_ CMOS_INVTR
+x2 net-_u1-pad4_ net-_u1-pad7_ net-_u1-pad8_ net-_x2-pad4_ CMOS_INVTR
+* s c m o d e
+* Control Statements
+
+.ends SerialParallel_blk
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/SerialParallel_blk_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk_Previous_Values.xml
new file mode 100644
index 000000000..e8cf97a6a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/SerialParallel_blk_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/4_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/3_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/4_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/3_in_and/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_Buf/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_Buf/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_Buf/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SRFF/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/analysis b/library/SubcircuitLibrary/SN54L99/analysis
new file mode 100644
index 000000000..a278481ce
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
diff --git a/library/SubcircuitLibrary/SN54L99/or_2-cache.lib b/library/SubcircuitLibrary/SN54L99/or_2-cache.lib
new file mode 100644
index 000000000..5f359bfb9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/or_2-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NOR_2
+#
+DEF NOR_2 X 0 40 Y Y 1 F N
+F0 "X" 50 0 60 H V C CNN
+F1 "NOR_2" 0 -250 60 H V C CNN
+F2 "" -100 0 60 H I C CNN
+F3 "" -100 0 60 H I C CNN
+DRAW
+A -350 0 206 760 -760 0 1 0 N -300 200 -300 -200
+A -226 239 445 -996 -324 0 1 0 N -300 -200 150 0
+A -197 -174 388 1054 266 0 1 0 N -300 200 150 0
+C 200 0 50 0 1 0 N
+X in1 1 -350 50 200 R 50 50 1 1 I
+X Gnd 2 -400 -150 200 R 50 50 1 1 I
+X Vdd 3 -400 150 200 R 50 50 1 1 I
+X in2 4 -350 -50 200 R 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54L99/or_2.bak b/library/SubcircuitLibrary/SN54L99/or_2.bak
new file mode 100644
index 000000000..f2ca541e9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/or_2.bak
@@ -0,0 +1,154 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NOR_2 X1
+U 1 1 685C27CC
+P 5650 2350
+F 0 "X1" H 5650 2350 60 0000 C CNN
+F 1 "NOR_2" H 5900 2350 60 0000 C CNN
+F 2 "" H 5650 2350 60 0001 C CNN
+F 3 "" H 5650 2350 60 0001 C CNN
+ 1 5650 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 685C2805
+P 7100 2350
+F 0 "X2" H 7100 2350 60 0000 C CNN
+F 1 "CMOS_INVTR" H 7200 2100 60 0000 C CNN
+F 2 "" H 7100 2350 60 0001 C CNN
+F 3 "" H 7100 2350 60 0001 C CNN
+ 1 7100 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685C28CA
+P 5050 2200
+F 0 "U1" H 5100 2300 30 0000 C CNN
+F 1 "PORT" H 5050 2200 30 0000 C CNN
+F 2 "" H 5050 2200 60 0000 C CNN
+F 3 "" H 5050 2200 60 0000 C CNN
+ 1 5050 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685C2911
+P 5050 2500
+F 0 "U1" H 5100 2600 30 0000 C CNN
+F 1 "PORT" H 5050 2500 30 0000 C CNN
+F 2 "" H 5050 2500 60 0000 C CNN
+F 3 "" H 5050 2500 60 0000 C CNN
+ 2 5050 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685C2946
+P 8150 2350
+F 0 "U1" H 8200 2450 30 0000 C CNN
+F 1 "PORT" H 8150 2350 30 0000 C CNN
+F 2 "" H 8150 2350 60 0000 C CNN
+F 3 "" H 8150 2350 60 0000 C CNN
+ 5 8150 2350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685C2985
+P 6200 1800
+F 0 "U1" H 6250 1900 30 0000 C CNN
+F 1 "PORT" H 6200 1800 30 0000 C CNN
+F 2 "" H 6200 1800 60 0000 C CNN
+F 3 "" H 6200 1800 60 0000 C CNN
+ 3 6200 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685C2A3C
+P 6200 2900
+F 0 "U1" H 6250 3000 30 0000 C CNN
+F 1 "PORT" H 6200 2900 30 0000 C CNN
+F 2 "" H 6200 2900 60 0000 C CNN
+F 3 "" H 6200 2900 60 0000 C CNN
+ 4 6200 2900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5750 1900 6450 1900
+Wire Wire Line
+ 6450 1800 6450 2200
+Wire Wire Line
+ 5750 2800 6450 2800
+Wire Wire Line
+ 6450 2500 6450 2900
+Connection ~ 6450 1900
+Connection ~ 6450 2800
+$Comp
+L SKY130mode scmode1
+U 1 1 685C2B66
+P 9500 1400
+F 0 "scmode1" H 9500 1550 98 0000 C CNB
+F 1 "SKY130mode" H 9500 1300 118 0000 C CNB
+F 2 "" H 9500 1550 60 0001 C CNN
+F 3 "" H 9500 1550 60 0001 C CNN
+ 1 9500 1400
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/or_2.cir b/library/SubcircuitLibrary/SN54L99/or_2.cir
new file mode 100644
index 000000000..dfdaa9c89
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/or_2.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/or_2/or_2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Jul 10 18:26:57 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+scmode1 SKY130mode
+X1 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_X1-Pad5_ NOR_2
+X2 Net-_X1-Pad5_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ CMOS_INVTR
+
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/or_2.cir.out b/library/SubcircuitLibrary/SN54L99/or_2.cir.out
new file mode 100644
index 000000000..c1803c3b8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/or_2.cir.out
@@ -0,0 +1,24 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/or_2/or_2.cir
+
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+* s c m o d e
+x1 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_x1-pad5_ NOR_2
+x2 net-_x1-pad5_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ CMOS_INVTR
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54L99/or_2.pro b/library/SubcircuitLibrary/SN54L99/or_2.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/or_2.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN54L99/or_2.sch b/library/SubcircuitLibrary/SN54L99/or_2.sch
new file mode 100644
index 000000000..9adf421b2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/or_2.sch
@@ -0,0 +1,159 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:or_2-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L PORT U1
+U 1 1 685C28CA
+P 5400 2300
+F 0 "U1" H 5450 2400 30 0000 C CNN
+F 1 "PORT" H 5400 2300 30 0000 C CNN
+F 2 "" H 5400 2300 60 0000 C CNN
+F 3 "" H 5400 2300 60 0000 C CNN
+ 1 5400 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685C2911
+P 5400 2400
+F 0 "U1" H 5450 2500 30 0000 C CNN
+F 1 "PORT" H 5400 2400 30 0000 C CNN
+F 2 "" H 5400 2400 60 0000 C CNN
+F 3 "" H 5400 2400 60 0000 C CNN
+ 2 5400 2400
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685C2946
+P 7650 2350
+F 0 "U1" H 7700 2450 30 0000 C CNN
+F 1 "PORT" H 7650 2350 30 0000 C CNN
+F 2 "" H 7650 2350 60 0000 C CNN
+F 3 "" H 7650 2350 60 0000 C CNN
+ 5 7650 2350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685C2985
+P 6200 1800
+F 0 "U1" H 6250 1900 30 0000 C CNN
+F 1 "PORT" H 6200 1800 30 0000 C CNN
+F 2 "" H 6200 1800 60 0000 C CNN
+F 3 "" H 6200 1800 60 0000 C CNN
+ 3 6200 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685C2A3C
+P 6200 2900
+F 0 "U1" H 6250 3000 30 0000 C CNN
+F 1 "PORT" H 6200 2900 30 0000 C CNN
+F 2 "" H 6200 2900 60 0000 C CNN
+F 3 "" H 6200 2900 60 0000 C CNN
+ 4 6200 2900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5600 1900 6450 1900
+Wire Wire Line
+ 6450 1800 6450 2250
+Wire Wire Line
+ 5600 2800 6450 2800
+Wire Wire Line
+ 6450 2450 6450 2900
+Connection ~ 6450 1900
+Connection ~ 6450 2800
+$Comp
+L SKY130mode scmode1
+U 1 1 685C2B66
+P 9500 1400
+F 0 "scmode1" H 9500 1550 98 0000 C CNB
+F 1 "SKY130mode" H 9500 1300 118 0000 C CNB
+F 2 "" H 9500 1550 60 0001 C CNN
+F 3 "" H 9500 1550 60 0001 C CNN
+ 1 9500 1400
+ 1 0 0 -1
+$EndComp
+$Comp
+L NOR_2 X1
+U 1 1 686FB89E
+P 6000 2350
+F 0 "X1" H 6050 2350 60 0000 C CNN
+F 1 "NOR_2" H 6000 2100 60 0000 C CNN
+F 2 "" H 5900 2350 60 0001 C CNN
+F 3 "" H 5900 2350 60 0001 C CNN
+ 1 6000 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 686FB8DF
+P 6850 2350
+F 0 "X2" H 6850 2350 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6900 2150 60 0000 C CNN
+F 2 "" H 6850 2350 60 0001 C CNN
+F 3 "" H 6850 2350 60 0001 C CNN
+ 1 6850 2350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5600 1900 5600 2200
+Wire Wire Line
+ 5600 2800 5600 2500
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54L99/or_2.sub b/library/SubcircuitLibrary/SN54L99/or_2.sub
new file mode 100644
index 000000000..2e9b374f8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/or_2.sub
@@ -0,0 +1,18 @@
+* Subcircuit or_2
+.subckt or_2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/or_2/or_2.cir
+.include CMOS_INVTR.sub
+.include NOR_2.sub
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+* s c m o d e
+x1 net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_x1-pad5_ NOR_2
+x2 net-_x1-pad5_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ CMOS_INVTR
+* Control Statements
+
+.ends or_2
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN54L99/or_2_Previous_Values.xml b/library/SubcircuitLibrary/SN54L99/or_2_Previous_Values.xml
new file mode 100644
index 000000000..cddf0d6af
--- /dev/null
+++ b/library/SubcircuitLibrary/SN54L99/or_2_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NOR_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7407/D.lib b/library/SubcircuitLibrary/SN7407/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/SN7407/NPN.lib b/library/SubcircuitLibrary/SN7407/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/SN7407/SN7407-cache.lib b/library/SubcircuitLibrary/SN7407/SN7407-cache.lib
new file mode 100644
index 000000000..7e9c6731b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/SN7407-cache.lib
@@ -0,0 +1,107 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7407/SN7407.cir b/library/SubcircuitLibrary/SN7407/SN7407.cir
new file mode 100644
index 000000000..fe735a2cd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/SN7407.cir
@@ -0,0 +1,71 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7407\SN7407.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/06/25 11:06:26
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_Q2-Pad3_ eSim_NPN
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D1-Pad1_ eSim_NPN
+Q4 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ eSim_NPN
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 6K
+R2 Net-_R1-Pad1_ Net-_Q2-Pad1_ 3.4K
+R3 Net-_Q2-Pad3_ Net-_Q3-Pad2_ 100
+R4 Net-_Q3-Pad2_ Net-_D1-Pad1_ 1K
+R5 Net-_R1-Pad1_ Net-_Q3-Pad1_ 1.6K
+Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_D2-Pad2_ eSim_NPN
+Q6 Net-_Q6-Pad1_ Net-_Q5-Pad1_ Net-_Q6-Pad3_ eSim_NPN
+Q7 Net-_Q7-Pad1_ Net-_Q7-Pad2_ Net-_D1-Pad1_ eSim_NPN
+Q8 Net-_Q8-Pad1_ Net-_Q7-Pad1_ Net-_D1-Pad1_ eSim_NPN
+D2 Net-_D1-Pad1_ Net-_D2-Pad2_ eSim_Diode
+R6 Net-_R1-Pad1_ Net-_Q5-Pad2_ 6K
+R7 Net-_R1-Pad1_ Net-_Q6-Pad1_ 3.4K
+R8 Net-_Q6-Pad3_ Net-_Q7-Pad2_ 100
+R9 Net-_Q7-Pad2_ Net-_D1-Pad1_ 1K
+R10 Net-_R1-Pad1_ Net-_Q7-Pad1_ 1.6K
+Q9 Net-_Q11-Pad2_ Net-_Q9-Pad2_ Net-_D3-Pad2_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_D1-Pad1_ eSim_NPN
+Q15 Net-_Q15-Pad1_ Net-_Q13-Pad1_ Net-_D1-Pad1_ eSim_NPN
+D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode
+R11 Net-_R1-Pad1_ Net-_Q9-Pad2_ 6K
+R13 Net-_R1-Pad1_ Net-_Q11-Pad1_ 3.4K
+R14 Net-_Q11-Pad3_ Net-_Q13-Pad2_ 100
+R15 Net-_Q13-Pad2_ Net-_D1-Pad1_ 1K
+R19 Net-_R1-Pad1_ Net-_Q13-Pad1_ 1.6K
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_D4-Pad2_ eSim_NPN
+Q12 Net-_Q12-Pad1_ Net-_Q10-Pad1_ Net-_Q12-Pad3_ eSim_NPN
+Q14 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_D1-Pad1_ eSim_NPN
+Q16 Net-_Q16-Pad1_ Net-_Q14-Pad1_ Net-_D1-Pad1_ eSim_NPN
+D4 Net-_D1-Pad1_ Net-_D4-Pad2_ eSim_Diode
+R12 Net-_R1-Pad1_ Net-_Q10-Pad2_ 6K
+R16 Net-_R1-Pad1_ Net-_Q12-Pad1_ 3.4K
+R17 Net-_Q12-Pad3_ Net-_Q14-Pad2_ 100
+R18 Net-_Q14-Pad2_ Net-_D1-Pad1_ 1K
+R20 Net-_R1-Pad1_ Net-_Q14-Pad1_ 1.6K
+Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_D5-Pad2_ eSim_NPN
+Q19 Net-_Q19-Pad1_ Net-_Q17-Pad1_ Net-_Q19-Pad3_ eSim_NPN
+Q21 Net-_Q21-Pad1_ Net-_Q21-Pad2_ Net-_D1-Pad1_ eSim_NPN
+Q23 Net-_Q23-Pad1_ Net-_Q21-Pad1_ Net-_D1-Pad1_ eSim_NPN
+D5 Net-_D1-Pad1_ Net-_D5-Pad2_ eSim_Diode
+R21 Net-_R1-Pad1_ Net-_Q17-Pad2_ 6K
+R23 Net-_R1-Pad1_ Net-_Q19-Pad1_ 3.4K
+R24 Net-_Q19-Pad3_ Net-_Q21-Pad2_ 100
+R25 Net-_Q21-Pad2_ Net-_D1-Pad1_ 1K
+R29 Net-_R1-Pad1_ Net-_Q21-Pad1_ 1.6K
+Q18 Net-_Q18-Pad1_ Net-_Q18-Pad2_ Net-_D6-Pad2_ eSim_NPN
+Q20 Net-_Q20-Pad1_ Net-_Q18-Pad1_ Net-_Q20-Pad3_ eSim_NPN
+Q22 Net-_Q22-Pad1_ Net-_Q22-Pad2_ Net-_D1-Pad1_ eSim_NPN
+Q24 Net-_Q24-Pad1_ Net-_Q22-Pad1_ Net-_D1-Pad1_ eSim_NPN
+D6 Net-_D1-Pad1_ Net-_D6-Pad2_ eSim_Diode
+R22 Net-_R1-Pad1_ Net-_Q18-Pad2_ 6K
+R26 Net-_R1-Pad1_ Net-_Q20-Pad1_ 3.4K
+R27 Net-_Q20-Pad3_ Net-_Q22-Pad2_ 100
+R28 Net-_Q22-Pad2_ Net-_D1-Pad1_ 1K
+R30 Net-_R1-Pad1_ Net-_Q22-Pad1_ 1.6K
+U1 Net-_D1-Pad2_ Net-_Q4-Pad1_ Net-_D2-Pad2_ Net-_Q8-Pad1_ Net-_D3-Pad2_ Net-_Q15-Pad1_ Net-_D1-Pad1_ Net-_Q16-Pad1_ Net-_D4-Pad2_ Net-_Q23-Pad1_ Net-_D5-Pad2_ Net-_Q24-Pad1_ Net-_D6-Pad2_ Net-_R1-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7407/SN7407.cir.out b/library/SubcircuitLibrary/SN7407/SN7407.cir.out
new file mode 100644
index 000000000..f8d1823e0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/SN7407.cir.out
@@ -0,0 +1,74 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn7407\sn7407.cir
+
+.include D.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q2-pad1_ net-_q1-pad1_ net-_q2-pad3_ Q2N2222
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d1-pad1_ Q2N2222
+q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 6k
+r2 net-_r1-pad1_ net-_q2-pad1_ 3.4k
+r3 net-_q2-pad3_ net-_q3-pad2_ 100
+r4 net-_q3-pad2_ net-_d1-pad1_ 1k
+r5 net-_r1-pad1_ net-_q3-pad1_ 1.6k
+q5 net-_q5-pad1_ net-_q5-pad2_ net-_d2-pad2_ Q2N2222
+q6 net-_q6-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2222
+q7 net-_q7-pad1_ net-_q7-pad2_ net-_d1-pad1_ Q2N2222
+q8 net-_q8-pad1_ net-_q7-pad1_ net-_d1-pad1_ Q2N2222
+d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148
+r6 net-_r1-pad1_ net-_q5-pad2_ 6k
+r7 net-_r1-pad1_ net-_q6-pad1_ 3.4k
+r8 net-_q6-pad3_ net-_q7-pad2_ 100
+r9 net-_q7-pad2_ net-_d1-pad1_ 1k
+r10 net-_r1-pad1_ net-_q7-pad1_ 1.6k
+q9 net-_q11-pad2_ net-_q9-pad2_ net-_d3-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_d1-pad1_ Q2N2222
+q15 net-_q15-pad1_ net-_q13-pad1_ net-_d1-pad1_ Q2N2222
+d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148
+r11 net-_r1-pad1_ net-_q9-pad2_ 6k
+r13 net-_r1-pad1_ net-_q11-pad1_ 3.4k
+r14 net-_q11-pad3_ net-_q13-pad2_ 100
+r15 net-_q13-pad2_ net-_d1-pad1_ 1k
+r19 net-_r1-pad1_ net-_q13-pad1_ 1.6k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_d4-pad2_ Q2N2222
+q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222
+q14 net-_q14-pad1_ net-_q14-pad2_ net-_d1-pad1_ Q2N2222
+q16 net-_q16-pad1_ net-_q14-pad1_ net-_d1-pad1_ Q2N2222
+d4 net-_d1-pad1_ net-_d4-pad2_ 1N4148
+r12 net-_r1-pad1_ net-_q10-pad2_ 6k
+r16 net-_r1-pad1_ net-_q12-pad1_ 3.4k
+r17 net-_q12-pad3_ net-_q14-pad2_ 100
+r18 net-_q14-pad2_ net-_d1-pad1_ 1k
+r20 net-_r1-pad1_ net-_q14-pad1_ 1.6k
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d5-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q17-pad1_ net-_q19-pad3_ Q2N2222
+q21 net-_q21-pad1_ net-_q21-pad2_ net-_d1-pad1_ Q2N2222
+q23 net-_q23-pad1_ net-_q21-pad1_ net-_d1-pad1_ Q2N2222
+d5 net-_d1-pad1_ net-_d5-pad2_ 1N4148
+r21 net-_r1-pad1_ net-_q17-pad2_ 6k
+r23 net-_r1-pad1_ net-_q19-pad1_ 3.4k
+r24 net-_q19-pad3_ net-_q21-pad2_ 100
+r25 net-_q21-pad2_ net-_d1-pad1_ 1k
+r29 net-_r1-pad1_ net-_q21-pad1_ 1.6k
+q18 net-_q18-pad1_ net-_q18-pad2_ net-_d6-pad2_ Q2N2222
+q20 net-_q20-pad1_ net-_q18-pad1_ net-_q20-pad3_ Q2N2222
+q22 net-_q22-pad1_ net-_q22-pad2_ net-_d1-pad1_ Q2N2222
+q24 net-_q24-pad1_ net-_q22-pad1_ net-_d1-pad1_ Q2N2222
+d6 net-_d1-pad1_ net-_d6-pad2_ 1N4148
+r22 net-_r1-pad1_ net-_q18-pad2_ 6k
+r26 net-_r1-pad1_ net-_q20-pad1_ 3.4k
+r27 net-_q20-pad3_ net-_q22-pad2_ 100
+r28 net-_q22-pad2_ net-_d1-pad1_ 1k
+r30 net-_r1-pad1_ net-_q22-pad1_ 1.6k
+* u1 net-_d1-pad2_ net-_q4-pad1_ net-_d2-pad2_ net-_q8-pad1_ net-_d3-pad2_ net-_q15-pad1_ net-_d1-pad1_ net-_q16-pad1_ net-_d4-pad2_ net-_q23-pad1_ net-_d5-pad2_ net-_q24-pad1_ net-_d6-pad2_ net-_r1-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7407/SN7407.pro b/library/SubcircuitLibrary/SN7407/SN7407.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/SN7407.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN7407/SN7407.sch b/library/SubcircuitLibrary/SN7407/SN7407.sch
new file mode 100644
index 000000000..ce193792e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/SN7407.sch
@@ -0,0 +1,1243 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN7407-cache
+EELAYER 25 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q1
+U 1 1 68468E27
+P 2050 3200
+F 0 "Q1" H 1950 3250 50 0000 R CNN
+F 1 "eSim_NPN" H 2000 3350 50 0000 R CNN
+F 2 "" H 2250 3300 29 0000 C CNN
+F 3 "" H 2050 3200 60 0000 C CNN
+ 1 2050 3200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 68468E68
+P 2650 3450
+F 0 "Q2" H 2550 3500 50 0000 R CNN
+F 1 "eSim_NPN" H 2600 3600 50 0000 R CNN
+F 2 "" H 2850 3550 29 0000 C CNN
+F 3 "" H 2650 3450 60 0000 C CNN
+ 1 2650 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 68468EC9
+P 3000 4350
+F 0 "Q3" H 2900 4400 50 0000 R CNN
+F 1 "eSim_NPN" H 2950 4500 50 0000 R CNN
+F 2 "" H 3200 4450 29 0000 C CNN
+F 3 "" H 3000 4350 60 0000 C CNN
+ 1 3000 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 68468F2E
+P 3850 4000
+F 0 "Q4" H 3750 4050 50 0000 R CNN
+F 1 "eSim_NPN" H 3800 4150 50 0000 R CNN
+F 2 "" H 4050 4100 29 0000 C CNN
+F 3 "" H 3850 4000 60 0000 C CNN
+ 1 3850 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D1
+U 1 1 68468F62
+P 1700 3850
+F 0 "D1" H 1700 3950 50 0000 C CNN
+F 1 "eSim_Diode" H 1700 3750 50 0000 C CNN
+F 2 "" H 1700 3850 60 0000 C CNN
+F 3 "" H 1700 3850 60 0000 C CNN
+ 1 1700 3850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R1
+U 1 1 68468FE4
+P 2000 2550
+F 0 "R1" H 2050 2680 50 0000 C CNN
+F 1 "6K" H 2050 2500 50 0000 C CNN
+F 2 "" H 2050 2530 30 0000 C CNN
+F 3 "" V 2050 2600 30 0000 C CNN
+ 1 2000 2550
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R2
+U 1 1 68469074
+P 2700 2700
+F 0 "R2" H 2750 2830 50 0000 C CNN
+F 1 "3.4K" H 2750 2650 50 0000 C CNN
+F 2 "" H 2750 2680 30 0000 C CNN
+F 3 "" V 2750 2750 30 0000 C CNN
+ 1 2700 2700
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R3
+U 1 1 684690C1
+P 2700 3900
+F 0 "R3" H 2750 4030 50 0000 C CNN
+F 1 "100" H 2750 3850 50 0000 C CNN
+F 2 "" H 2750 3880 30 0000 C CNN
+F 3 "" V 2750 3950 30 0000 C CNN
+ 1 2700 3900
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 68469109
+P 2700 4600
+F 0 "R4" H 2750 4730 50 0000 C CNN
+F 1 "1K" H 2750 4550 50 0000 C CNN
+F 2 "" H 2750 4580 30 0000 C CNN
+F 3 "" V 2750 4650 30 0000 C CNN
+ 1 2700 4600
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R5
+U 1 1 68469152
+P 3400 2850
+F 0 "R5" H 3450 2980 50 0000 C CNN
+F 1 "1.6K" H 3450 2800 50 0000 C CNN
+F 2 "" H 3450 2830 30 0000 C CNN
+F 3 "" V 3450 2900 30 0000 C CNN
+ 1 3400 2850
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 6864E1C9
+P 2050 6300
+F 0 "Q5" H 1950 6350 50 0000 R CNN
+F 1 "eSim_NPN" H 2000 6450 50 0000 R CNN
+F 2 "" H 2250 6400 29 0000 C CNN
+F 3 "" H 2050 6300 60 0000 C CNN
+ 1 2050 6300
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 6864E1CF
+P 2650 6550
+F 0 "Q6" H 2550 6600 50 0000 R CNN
+F 1 "eSim_NPN" H 2600 6700 50 0000 R CNN
+F 2 "" H 2850 6650 29 0000 C CNN
+F 3 "" H 2650 6550 60 0000 C CNN
+ 1 2650 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 6864E1D5
+P 3000 7450
+F 0 "Q7" H 2900 7500 50 0000 R CNN
+F 1 "eSim_NPN" H 2950 7600 50 0000 R CNN
+F 2 "" H 3200 7550 29 0000 C CNN
+F 3 "" H 3000 7450 60 0000 C CNN
+ 1 3000 7450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 6864E1DB
+P 3850 7100
+F 0 "Q8" H 3750 7150 50 0000 R CNN
+F 1 "eSim_NPN" H 3800 7250 50 0000 R CNN
+F 2 "" H 4050 7200 29 0000 C CNN
+F 3 "" H 3850 7100 60 0000 C CNN
+ 1 3850 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 6864E1E1
+P 1700 6950
+F 0 "D2" H 1700 7050 50 0000 C CNN
+F 1 "eSim_Diode" H 1700 6850 50 0000 C CNN
+F 2 "" H 1700 6950 60 0000 C CNN
+F 3 "" H 1700 6950 60 0000 C CNN
+ 1 1700 6950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R6
+U 1 1 6864E1E7
+P 2000 5650
+F 0 "R6" H 2050 5780 50 0000 C CNN
+F 1 "6K" H 2050 5600 50 0000 C CNN
+F 2 "" H 2050 5630 30 0000 C CNN
+F 3 "" V 2050 5700 30 0000 C CNN
+ 1 2000 5650
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R7
+U 1 1 6864E1ED
+P 2700 5800
+F 0 "R7" H 2750 5930 50 0000 C CNN
+F 1 "3.4K" H 2750 5750 50 0000 C CNN
+F 2 "" H 2750 5780 30 0000 C CNN
+F 3 "" V 2750 5850 30 0000 C CNN
+ 1 2700 5800
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R8
+U 1 1 6864E1F3
+P 2700 7000
+F 0 "R8" H 2750 7130 50 0000 C CNN
+F 1 "100" H 2750 6950 50 0000 C CNN
+F 2 "" H 2750 6980 30 0000 C CNN
+F 3 "" V 2750 7050 30 0000 C CNN
+ 1 2700 7000
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R9
+U 1 1 6864E1F9
+P 2700 7700
+F 0 "R9" H 2750 7830 50 0000 C CNN
+F 1 "1K" H 2750 7650 50 0000 C CNN
+F 2 "" H 2750 7680 30 0000 C CNN
+F 3 "" V 2750 7750 30 0000 C CNN
+ 1 2700 7700
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R10
+U 1 1 6864E1FF
+P 3400 5950
+F 0 "R10" H 3450 6080 50 0000 C CNN
+F 1 "1.6K" H 3450 5900 50 0000 C CNN
+F 2 "" H 3450 5930 30 0000 C CNN
+F 3 "" V 3450 6000 30 0000 C CNN
+ 1 3400 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 6864E579
+P 6300 3200
+F 0 "Q9" H 6200 3250 50 0000 R CNN
+F 1 "eSim_NPN" H 6250 3350 50 0000 R CNN
+F 2 "" H 6500 3300 29 0000 C CNN
+F 3 "" H 6300 3200 60 0000 C CNN
+ 1 6300 3200
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q11
+U 1 1 6864E57F
+P 6900 3450
+F 0 "Q11" H 6800 3500 50 0000 R CNN
+F 1 "eSim_NPN" H 6850 3600 50 0000 R CNN
+F 2 "" H 7100 3550 29 0000 C CNN
+F 3 "" H 6900 3450 60 0000 C CNN
+ 1 6900 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q13
+U 1 1 6864E585
+P 7250 4350
+F 0 "Q13" H 7150 4400 50 0000 R CNN
+F 1 "eSim_NPN" H 7200 4500 50 0000 R CNN
+F 2 "" H 7450 4450 29 0000 C CNN
+F 3 "" H 7250 4350 60 0000 C CNN
+ 1 7250 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q15
+U 1 1 6864E58B
+P 8100 4000
+F 0 "Q15" H 8000 4050 50 0000 R CNN
+F 1 "eSim_NPN" H 8050 4150 50 0000 R CNN
+F 2 "" H 8300 4100 29 0000 C CNN
+F 3 "" H 8100 4000 60 0000 C CNN
+ 1 8100 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D3
+U 1 1 6864E591
+P 5950 3850
+F 0 "D3" H 5950 3950 50 0000 C CNN
+F 1 "eSim_Diode" H 5950 3750 50 0000 C CNN
+F 2 "" H 5950 3850 60 0000 C CNN
+F 3 "" H 5950 3850 60 0000 C CNN
+ 1 5950 3850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R11
+U 1 1 6864E597
+P 6250 2550
+F 0 "R11" H 6300 2680 50 0000 C CNN
+F 1 "6K" H 6300 2500 50 0000 C CNN
+F 2 "" H 6300 2530 30 0000 C CNN
+F 3 "" V 6300 2600 30 0000 C CNN
+ 1 6250 2550
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R13
+U 1 1 6864E59D
+P 6950 2700
+F 0 "R13" H 7000 2830 50 0000 C CNN
+F 1 "3.4K" H 7000 2650 50 0000 C CNN
+F 2 "" H 7000 2680 30 0000 C CNN
+F 3 "" V 7000 2750 30 0000 C CNN
+ 1 6950 2700
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R14
+U 1 1 6864E5A3
+P 6950 3900
+F 0 "R14" H 7000 4030 50 0000 C CNN
+F 1 "100" H 7000 3850 50 0000 C CNN
+F 2 "" H 7000 3880 30 0000 C CNN
+F 3 "" V 7000 3950 30 0000 C CNN
+ 1 6950 3900
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R15
+U 1 1 6864E5A9
+P 6950 4600
+F 0 "R15" H 7000 4730 50 0000 C CNN
+F 1 "1K" H 7000 4550 50 0000 C CNN
+F 2 "" H 7000 4580 30 0000 C CNN
+F 3 "" V 7000 4650 30 0000 C CNN
+ 1 6950 4600
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R19
+U 1 1 6864E5AF
+P 7650 2850
+F 0 "R19" H 7700 2980 50 0000 C CNN
+F 1 "1.6K" H 7700 2800 50 0000 C CNN
+F 2 "" H 7700 2830 30 0000 C CNN
+F 3 "" V 7700 2900 30 0000 C CNN
+ 1 7650 2850
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q10
+U 1 1 6864E839
+P 6300 6300
+F 0 "Q10" H 6200 6350 50 0000 R CNN
+F 1 "eSim_NPN" H 6250 6450 50 0000 R CNN
+F 2 "" H 6500 6400 29 0000 C CNN
+F 3 "" H 6300 6300 60 0000 C CNN
+ 1 6300 6300
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q12
+U 1 1 6864E83F
+P 6900 6550
+F 0 "Q12" H 6800 6600 50 0000 R CNN
+F 1 "eSim_NPN" H 6850 6700 50 0000 R CNN
+F 2 "" H 7100 6650 29 0000 C CNN
+F 3 "" H 6900 6550 60 0000 C CNN
+ 1 6900 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q14
+U 1 1 6864E845
+P 7250 7450
+F 0 "Q14" H 7150 7500 50 0000 R CNN
+F 1 "eSim_NPN" H 7200 7600 50 0000 R CNN
+F 2 "" H 7450 7550 29 0000 C CNN
+F 3 "" H 7250 7450 60 0000 C CNN
+ 1 7250 7450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q16
+U 1 1 6864E84B
+P 8100 7100
+F 0 "Q16" H 8000 7150 50 0000 R CNN
+F 1 "eSim_NPN" H 8050 7250 50 0000 R CNN
+F 2 "" H 8300 7200 29 0000 C CNN
+F 3 "" H 8100 7100 60 0000 C CNN
+ 1 8100 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D4
+U 1 1 6864E851
+P 5950 6950
+F 0 "D4" H 5950 7050 50 0000 C CNN
+F 1 "eSim_Diode" H 5950 6850 50 0000 C CNN
+F 2 "" H 5950 6950 60 0000 C CNN
+F 3 "" H 5950 6950 60 0000 C CNN
+ 1 5950 6950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R12
+U 1 1 6864E857
+P 6250 5650
+F 0 "R12" H 6300 5780 50 0000 C CNN
+F 1 "6K" H 6300 5600 50 0000 C CNN
+F 2 "" H 6300 5630 30 0000 C CNN
+F 3 "" V 6300 5700 30 0000 C CNN
+ 1 6250 5650
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R16
+U 1 1 6864E85D
+P 6950 5800
+F 0 "R16" H 7000 5930 50 0000 C CNN
+F 1 "3.4K" H 7000 5750 50 0000 C CNN
+F 2 "" H 7000 5780 30 0000 C CNN
+F 3 "" V 7000 5850 30 0000 C CNN
+ 1 6950 5800
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R17
+U 1 1 6864E863
+P 6950 7000
+F 0 "R17" H 7000 7130 50 0000 C CNN
+F 1 "100" H 7000 6950 50 0000 C CNN
+F 2 "" H 7000 6980 30 0000 C CNN
+F 3 "" V 7000 7050 30 0000 C CNN
+ 1 6950 7000
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R18
+U 1 1 6864E869
+P 6950 7700
+F 0 "R18" H 7000 7830 50 0000 C CNN
+F 1 "1K" H 7000 7650 50 0000 C CNN
+F 2 "" H 7000 7680 30 0000 C CNN
+F 3 "" V 7000 7750 30 0000 C CNN
+ 1 6950 7700
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R20
+U 1 1 6864E86F
+P 7650 5950
+F 0 "R20" H 7700 6080 50 0000 C CNN
+F 1 "1.6K" H 7700 5900 50 0000 C CNN
+F 2 "" H 7700 5930 30 0000 C CNN
+F 3 "" V 7700 6000 30 0000 C CNN
+ 1 7650 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 6864EB35
+P 10900 3300
+F 0 "Q17" H 10800 3350 50 0000 R CNN
+F 1 "eSim_NPN" H 10850 3450 50 0000 R CNN
+F 2 "" H 11100 3400 29 0000 C CNN
+F 3 "" H 10900 3300 60 0000 C CNN
+ 1 10900 3300
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q19
+U 1 1 6864EB3B
+P 11500 3550
+F 0 "Q19" H 11400 3600 50 0000 R CNN
+F 1 "eSim_NPN" H 11450 3700 50 0000 R CNN
+F 2 "" H 11700 3650 29 0000 C CNN
+F 3 "" H 11500 3550 60 0000 C CNN
+ 1 11500 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q21
+U 1 1 6864EB41
+P 11850 4450
+F 0 "Q21" H 11750 4500 50 0000 R CNN
+F 1 "eSim_NPN" H 11800 4600 50 0000 R CNN
+F 2 "" H 12050 4550 29 0000 C CNN
+F 3 "" H 11850 4450 60 0000 C CNN
+ 1 11850 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q23
+U 1 1 6864EB47
+P 12700 4100
+F 0 "Q23" H 12600 4150 50 0000 R CNN
+F 1 "eSim_NPN" H 12650 4250 50 0000 R CNN
+F 2 "" H 12900 4200 29 0000 C CNN
+F 3 "" H 12700 4100 60 0000 C CNN
+ 1 12700 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D5
+U 1 1 6864EB4D
+P 10550 3950
+F 0 "D5" H 10550 4050 50 0000 C CNN
+F 1 "eSim_Diode" H 10550 3850 50 0000 C CNN
+F 2 "" H 10550 3950 60 0000 C CNN
+F 3 "" H 10550 3950 60 0000 C CNN
+ 1 10550 3950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R21
+U 1 1 6864EB53
+P 10850 2650
+F 0 "R21" H 10900 2780 50 0000 C CNN
+F 1 "6K" H 10900 2600 50 0000 C CNN
+F 2 "" H 10900 2630 30 0000 C CNN
+F 3 "" V 10900 2700 30 0000 C CNN
+ 1 10850 2650
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R23
+U 1 1 6864EB59
+P 11550 2800
+F 0 "R23" H 11600 2930 50 0000 C CNN
+F 1 "3.4K" H 11600 2750 50 0000 C CNN
+F 2 "" H 11600 2780 30 0000 C CNN
+F 3 "" V 11600 2850 30 0000 C CNN
+ 1 11550 2800
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R24
+U 1 1 6864EB5F
+P 11550 4000
+F 0 "R24" H 11600 4130 50 0000 C CNN
+F 1 "100" H 11600 3950 50 0000 C CNN
+F 2 "" H 11600 3980 30 0000 C CNN
+F 3 "" V 11600 4050 30 0000 C CNN
+ 1 11550 4000
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R25
+U 1 1 6864EB65
+P 11550 4700
+F 0 "R25" H 11600 4830 50 0000 C CNN
+F 1 "1K" H 11600 4650 50 0000 C CNN
+F 2 "" H 11600 4680 30 0000 C CNN
+F 3 "" V 11600 4750 30 0000 C CNN
+ 1 11550 4700
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R29
+U 1 1 6864EB6B
+P 12250 2950
+F 0 "R29" H 12300 3080 50 0000 C CNN
+F 1 "1.6K" H 12300 2900 50 0000 C CNN
+F 2 "" H 12300 2930 30 0000 C CNN
+F 3 "" V 12300 3000 30 0000 C CNN
+ 1 12250 2950
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q18
+U 1 1 6864ED19
+P 10900 6350
+F 0 "Q18" H 10800 6400 50 0000 R CNN
+F 1 "eSim_NPN" H 10850 6500 50 0000 R CNN
+F 2 "" H 11100 6450 29 0000 C CNN
+F 3 "" H 10900 6350 60 0000 C CNN
+ 1 10900 6350
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q20
+U 1 1 6864ED1F
+P 11500 6600
+F 0 "Q20" H 11400 6650 50 0000 R CNN
+F 1 "eSim_NPN" H 11450 6750 50 0000 R CNN
+F 2 "" H 11700 6700 29 0000 C CNN
+F 3 "" H 11500 6600 60 0000 C CNN
+ 1 11500 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q22
+U 1 1 6864ED25
+P 11850 7500
+F 0 "Q22" H 11750 7550 50 0000 R CNN
+F 1 "eSim_NPN" H 11800 7650 50 0000 R CNN
+F 2 "" H 12050 7600 29 0000 C CNN
+F 3 "" H 11850 7500 60 0000 C CNN
+ 1 11850 7500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q24
+U 1 1 6864ED2B
+P 12700 7150
+F 0 "Q24" H 12600 7200 50 0000 R CNN
+F 1 "eSim_NPN" H 12650 7300 50 0000 R CNN
+F 2 "" H 12900 7250 29 0000 C CNN
+F 3 "" H 12700 7150 60 0000 C CNN
+ 1 12700 7150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D6
+U 1 1 6864ED31
+P 10550 7000
+F 0 "D6" H 10550 7100 50 0000 C CNN
+F 1 "eSim_Diode" H 10550 6900 50 0000 C CNN
+F 2 "" H 10550 7000 60 0000 C CNN
+F 3 "" H 10550 7000 60 0000 C CNN
+ 1 10550 7000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R22
+U 1 1 6864ED37
+P 10850 5700
+F 0 "R22" H 10900 5830 50 0000 C CNN
+F 1 "6K" H 10900 5650 50 0000 C CNN
+F 2 "" H 10900 5680 30 0000 C CNN
+F 3 "" V 10900 5750 30 0000 C CNN
+ 1 10850 5700
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R26
+U 1 1 6864ED3D
+P 11550 5850
+F 0 "R26" H 11600 5980 50 0000 C CNN
+F 1 "3.4K" H 11600 5800 50 0000 C CNN
+F 2 "" H 11600 5830 30 0000 C CNN
+F 3 "" V 11600 5900 30 0000 C CNN
+ 1 11550 5850
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R27
+U 1 1 6864ED43
+P 11550 7050
+F 0 "R27" H 11600 7180 50 0000 C CNN
+F 1 "100" H 11600 7000 50 0000 C CNN
+F 2 "" H 11600 7030 30 0000 C CNN
+F 3 "" V 11600 7100 30 0000 C CNN
+ 1 11550 7050
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R28
+U 1 1 6864ED49
+P 11550 7750
+F 0 "R28" H 11600 7880 50 0000 C CNN
+F 1 "1K" H 11600 7700 50 0000 C CNN
+F 2 "" H 11600 7730 30 0000 C CNN
+F 3 "" V 11600 7800 30 0000 C CNN
+ 1 11550 7750
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R30
+U 1 1 6864ED4F
+P 12250 6000
+F 0 "R30" H 12300 6130 50 0000 C CNN
+F 1 "1.6K" H 12300 5950 50 0000 C CNN
+F 2 "" H 12300 5980 30 0000 C CNN
+F 3 "" V 12300 6050 30 0000 C CNN
+ 1 12250 6000
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68654139
+P 1300 3400
+F 0 "U1" H 1350 3500 30 0000 C CNN
+F 1 "PORT" H 1300 3400 30 0000 C CNN
+F 2 "" H 1300 3400 60 0000 C CNN
+F 3 "" H 1300 3400 60 0000 C CNN
+ 1 1300 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686541C8
+P 4250 3600
+F 0 "U1" H 4300 3700 30 0000 C CNN
+F 1 "PORT" H 4250 3600 30 0000 C CNN
+F 2 "" H 4250 3600 60 0000 C CNN
+F 3 "" H 4250 3600 60 0000 C CNN
+ 2 4250 3600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68654289
+P 1300 6600
+F 0 "U1" H 1350 6700 30 0000 C CNN
+F 1 "PORT" H 1300 6600 30 0000 C CNN
+F 2 "" H 1300 6600 60 0000 C CNN
+F 3 "" H 1300 6600 60 0000 C CNN
+ 3 1300 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6865431C
+P 4250 6650
+F 0 "U1" H 4300 6750 30 0000 C CNN
+F 1 "PORT" H 4250 6650 30 0000 C CNN
+F 2 "" H 4250 6650 60 0000 C CNN
+F 3 "" H 4250 6650 60 0000 C CNN
+ 4 4250 6650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686543D7
+P 5550 3550
+F 0 "U1" H 5600 3650 30 0000 C CNN
+F 1 "PORT" H 5550 3550 30 0000 C CNN
+F 2 "" H 5550 3550 60 0000 C CNN
+F 3 "" H 5550 3550 60 0000 C CNN
+ 5 5550 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68654470
+P 8500 3500
+F 0 "U1" H 8550 3600 30 0000 C CNN
+F 1 "PORT" H 8500 3500 30 0000 C CNN
+F 2 "" H 8500 3500 60 0000 C CNN
+F 3 "" H 8500 3500 60 0000 C CNN
+ 6 8500 3500
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68654509
+P 14800 8600
+F 0 "U1" H 14850 8700 30 0000 C CNN
+F 1 "PORT" H 14800 8600 30 0000 C CNN
+F 2 "" H 14800 8600 60 0000 C CNN
+F 3 "" H 14800 8600 60 0000 C CNN
+ 7 14800 8600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686545A4
+P 8500 6650
+F 0 "U1" H 8550 6750 30 0000 C CNN
+F 1 "PORT" H 8500 6650 30 0000 C CNN
+F 2 "" H 8500 6650 60 0000 C CNN
+F 3 "" H 8500 6650 60 0000 C CNN
+ 8 8500 6650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68654641
+P 5550 6550
+F 0 "U1" H 5600 6650 30 0000 C CNN
+F 1 "PORT" H 5550 6550 30 0000 C CNN
+F 2 "" H 5550 6550 60 0000 C CNN
+F 3 "" H 5550 6550 60 0000 C CNN
+ 9 5550 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686546F0
+P 13100 3650
+F 0 "U1" H 13150 3750 30 0000 C CNN
+F 1 "PORT" H 13100 3650 30 0000 C CNN
+F 2 "" H 13100 3650 60 0000 C CNN
+F 3 "" H 13100 3650 60 0000 C CNN
+ 10 13100 3650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68654791
+P 10150 3550
+F 0 "U1" H 10200 3650 30 0000 C CNN
+F 1 "PORT" H 10150 3550 30 0000 C CNN
+F 2 "" H 10150 3550 60 0000 C CNN
+F 3 "" H 10150 3550 60 0000 C CNN
+ 11 10150 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6865483C
+P 13100 6650
+F 0 "U1" H 13150 6750 30 0000 C CNN
+F 1 "PORT" H 13100 6650 30 0000 C CNN
+F 2 "" H 13100 6650 60 0000 C CNN
+F 3 "" H 13100 6650 60 0000 C CNN
+ 12 13100 6650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686548E1
+P 10200 6600
+F 0 "U1" H 10250 6700 30 0000 C CNN
+F 1 "PORT" H 10200 6600 30 0000 C CNN
+F 2 "" H 10200 6600 60 0000 C CNN
+F 3 "" H 10200 6600 60 0000 C CNN
+ 13 10200 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 68654988
+P 14850 2200
+F 0 "U1" H 14900 2300 30 0000 C CNN
+F 1 "PORT" H 14850 2200 30 0000 C CNN
+F 2 "" H 14850 2200 60 0000 C CNN
+F 3 "" H 14850 2200 60 0000 C CNN
+ 14 14850 2200
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 1700 3300 1700 3700
+Wire Wire Line
+ 1700 3300 1850 3300
+Wire Wire Line
+ 2250 3300 2250 3450
+Wire Wire Line
+ 2250 3450 2450 3450
+Wire Wire Line
+ 2750 3650 2750 3800
+Wire Wire Line
+ 2750 4100 2750 4500
+Wire Wire Line
+ 2750 4350 2800 4350
+Connection ~ 2750 4350
+Wire Wire Line
+ 3100 4150 3100 4000
+Wire Wire Line
+ 3100 4000 3650 4000
+Wire Wire Line
+ 3450 3050 3450 4000
+Connection ~ 3450 4000
+Wire Wire Line
+ 2050 2750 2050 3000
+Wire Wire Line
+ 2750 2900 2750 3250
+Wire Wire Line
+ 1700 4000 1700 5000
+Wire Wire Line
+ 1700 5000 5350 5000
+Wire Wire Line
+ 2750 4800 2750 5000
+Connection ~ 2750 5000
+Wire Wire Line
+ 3100 4550 3100 5000
+Connection ~ 3100 5000
+Wire Wire Line
+ 3950 4200 3950 5000
+Connection ~ 3950 5000
+Wire Wire Line
+ 2050 2450 2050 2300
+Wire Wire Line
+ 2050 2300 3450 2300
+Wire Wire Line
+ 3450 2200 3450 2750
+Wire Wire Line
+ 2750 2300 2750 2600
+Connection ~ 2750 2300
+Wire Wire Line
+ 1700 6800 1700 6400
+Wire Wire Line
+ 1700 6400 1850 6400
+Wire Wire Line
+ 2250 6400 2250 6550
+Wire Wire Line
+ 2250 6550 2450 6550
+Wire Wire Line
+ 2750 6750 2750 6900
+Wire Wire Line
+ 2750 7200 2750 7600
+Wire Wire Line
+ 2750 7450 2800 7450
+Connection ~ 2750 7450
+Wire Wire Line
+ 3100 7250 3100 7100
+Wire Wire Line
+ 3100 7100 3650 7100
+Wire Wire Line
+ 3450 6150 3450 7100
+Connection ~ 3450 7100
+Wire Wire Line
+ 2050 5850 2050 6100
+Wire Wire Line
+ 2750 6000 2750 6350
+Wire Wire Line
+ 1700 7100 1700 8100
+Wire Wire Line
+ 1700 8100 5000 8100
+Wire Wire Line
+ 5000 8100 5000 8600
+Wire Wire Line
+ 2750 7900 2750 8100
+Connection ~ 2750 8100
+Wire Wire Line
+ 3100 7650 3100 8100
+Connection ~ 3100 8100
+Wire Wire Line
+ 3950 7300 3950 8100
+Connection ~ 3950 8100
+Wire Wire Line
+ 2050 5550 2050 5400
+Wire Wire Line
+ 2050 5400 5000 5400
+Wire Wire Line
+ 3450 5400 3450 5850
+Wire Wire Line
+ 2750 5400 2750 5700
+Connection ~ 2750 5400
+Wire Wire Line
+ 5950 3300 5950 3700
+Wire Wire Line
+ 5950 3300 6100 3300
+Wire Wire Line
+ 6500 3300 6500 3450
+Wire Wire Line
+ 6500 3450 6700 3450
+Wire Wire Line
+ 7000 3650 7000 3800
+Wire Wire Line
+ 7000 4100 7000 4500
+Wire Wire Line
+ 7000 4350 7050 4350
+Connection ~ 7000 4350
+Wire Wire Line
+ 7350 4150 7350 4000
+Wire Wire Line
+ 7350 4000 7900 4000
+Wire Wire Line
+ 7700 3050 7700 4000
+Connection ~ 7700 4000
+Wire Wire Line
+ 6300 2750 6300 3000
+Wire Wire Line
+ 7000 2900 7000 3250
+Wire Wire Line
+ 5950 4000 5950 5000
+Wire Wire Line
+ 5950 5000 9850 5000
+Wire Wire Line
+ 7000 4800 7000 5000
+Connection ~ 7000 5000
+Wire Wire Line
+ 7350 4550 7350 5000
+Connection ~ 7350 5000
+Wire Wire Line
+ 8200 4200 8200 5000
+Connection ~ 8200 5000
+Wire Wire Line
+ 6300 2450 6300 2300
+Wire Wire Line
+ 6300 2300 8150 2300
+Wire Wire Line
+ 7700 2300 7700 2750
+Wire Wire Line
+ 7000 2300 7000 2600
+Connection ~ 7000 2300
+Wire Wire Line
+ 5950 6400 5950 6800
+Wire Wire Line
+ 5950 6400 6100 6400
+Wire Wire Line
+ 6500 6400 6500 6550
+Wire Wire Line
+ 6500 6550 6700 6550
+Wire Wire Line
+ 7000 6750 7000 6900
+Wire Wire Line
+ 7000 7200 7000 7600
+Wire Wire Line
+ 7000 7450 7050 7450
+Connection ~ 7000 7450
+Wire Wire Line
+ 7350 7250 7350 7100
+Wire Wire Line
+ 7350 7100 7900 7100
+Wire Wire Line
+ 7700 6150 7700 7100
+Connection ~ 7700 7100
+Wire Wire Line
+ 6300 5850 6300 6100
+Wire Wire Line
+ 7000 6000 7000 6350
+Wire Wire Line
+ 5950 7100 5950 8100
+Wire Wire Line
+ 5950 8100 9250 8100
+Wire Wire Line
+ 9250 8100 9250 8600
+Wire Wire Line
+ 7000 7900 7000 8100
+Connection ~ 7000 8100
+Wire Wire Line
+ 7350 7650 7350 8100
+Connection ~ 7350 8100
+Wire Wire Line
+ 8200 7300 8200 8100
+Connection ~ 8200 8100
+Wire Wire Line
+ 6300 5550 6300 5400
+Wire Wire Line
+ 6300 5400 9500 5400
+Wire Wire Line
+ 7700 5400 7700 5850
+Wire Wire Line
+ 7000 5400 7000 5700
+Connection ~ 7000 5400
+Wire Wire Line
+ 10550 3400 10550 3800
+Wire Wire Line
+ 10550 3400 10700 3400
+Wire Wire Line
+ 11100 3400 11100 3550
+Wire Wire Line
+ 11100 3550 11300 3550
+Wire Wire Line
+ 11600 3750 11600 3900
+Wire Wire Line
+ 11600 4200 11600 4600
+Wire Wire Line
+ 11600 4450 11650 4450
+Connection ~ 11600 4450
+Wire Wire Line
+ 11950 4250 11950 4100
+Wire Wire Line
+ 11950 4100 12500 4100
+Wire Wire Line
+ 12300 3150 12300 4100
+Connection ~ 12300 4100
+Wire Wire Line
+ 10900 2850 10900 3100
+Wire Wire Line
+ 11600 3000 11600 3350
+Wire Wire Line
+ 10550 4100 10550 5100
+Wire Wire Line
+ 10550 5100 14250 5100
+Wire Wire Line
+ 11600 4900 11600 5100
+Connection ~ 11600 5100
+Wire Wire Line
+ 11950 4650 11950 5100
+Connection ~ 11950 5100
+Wire Wire Line
+ 12800 4300 12800 5100
+Connection ~ 12800 5100
+Wire Wire Line
+ 10900 2550 10900 2400
+Wire Wire Line
+ 10900 2400 12800 2400
+Wire Wire Line
+ 12300 2400 12300 2850
+Wire Wire Line
+ 11600 2400 11600 2700
+Connection ~ 11600 2400
+Wire Wire Line
+ 10550 6450 10550 6850
+Wire Wire Line
+ 10550 6450 10700 6450
+Wire Wire Line
+ 11100 6450 11100 6600
+Wire Wire Line
+ 11100 6600 11300 6600
+Wire Wire Line
+ 11600 6800 11600 6950
+Wire Wire Line
+ 11600 7250 11600 7650
+Wire Wire Line
+ 11600 7500 11650 7500
+Connection ~ 11600 7500
+Wire Wire Line
+ 11950 7300 11950 7150
+Wire Wire Line
+ 11950 7150 12500 7150
+Wire Wire Line
+ 12300 6200 12300 7150
+Connection ~ 12300 7150
+Wire Wire Line
+ 10900 5900 10900 6150
+Wire Wire Line
+ 11600 6050 11600 6400
+Wire Wire Line
+ 10550 7150 10550 8150
+Wire Wire Line
+ 10550 8150 13850 8150
+Wire Wire Line
+ 13850 8150 13850 8600
+Wire Wire Line
+ 11600 7950 11600 8150
+Connection ~ 11600 8150
+Wire Wire Line
+ 11950 7700 11950 8150
+Connection ~ 11950 8150
+Wire Wire Line
+ 12800 7350 12800 8150
+Connection ~ 12800 8150
+Wire Wire Line
+ 10900 5600 10900 5450
+Wire Wire Line
+ 10900 5450 13800 5450
+Wire Wire Line
+ 12300 5450 12300 5900
+Wire Wire Line
+ 11600 5450 11600 5750
+Connection ~ 11600 5450
+Wire Wire Line
+ 5350 5000 5350 8600
+Wire Wire Line
+ 5000 8600 14550 8600
+Wire Wire Line
+ 9850 5000 9850 8600
+Connection ~ 9850 8600
+Wire Wire Line
+ 14250 5100 14250 8600
+Connection ~ 14250 8600
+Connection ~ 13850 8600
+Connection ~ 9250 8600
+Connection ~ 5350 8600
+Wire Wire Line
+ 5000 5400 5000 2200
+Wire Wire Line
+ 3450 2200 14600 2200
+Connection ~ 3450 5400
+Wire Wire Line
+ 12800 2400 12800 2200
+Connection ~ 12800 2200
+Connection ~ 12300 2400
+Wire Wire Line
+ 8150 2300 8150 2200
+Connection ~ 8150 2200
+Connection ~ 7700 2300
+Connection ~ 5000 2200
+Connection ~ 3450 2300
+Wire Wire Line
+ 9500 5400 9500 2200
+Connection ~ 9500 2200
+Connection ~ 7700 5400
+Wire Wire Line
+ 13800 5450 13800 2200
+Connection ~ 13800 2200
+Connection ~ 12300 5450
+Wire Wire Line
+ 1550 3400 1700 3400
+Connection ~ 1700 3400
+Wire Wire Line
+ 3950 3800 3950 3600
+Wire Wire Line
+ 3950 3600 4000 3600
+Wire Wire Line
+ 3950 6900 3950 6650
+Wire Wire Line
+ 3950 6650 4000 6650
+Wire Wire Line
+ 5800 3550 5950 3550
+Connection ~ 5950 3550
+Wire Wire Line
+ 8200 3800 8200 3500
+Wire Wire Line
+ 8200 3500 8250 3500
+Wire Wire Line
+ 5800 6550 5950 6550
+Connection ~ 5950 6550
+Wire Wire Line
+ 8200 6900 8200 6650
+Wire Wire Line
+ 8200 6650 8250 6650
+Wire Wire Line
+ 10400 3550 10550 3550
+Connection ~ 10550 3550
+Wire Wire Line
+ 12800 3900 12800 3650
+Wire Wire Line
+ 12800 3650 12850 3650
+Wire Wire Line
+ 10450 6600 10550 6600
+Connection ~ 10550 6600
+Wire Wire Line
+ 12800 6950 12800 6650
+Wire Wire Line
+ 12800 6650 12850 6650
+Wire Wire Line
+ 1550 6600 1700 6600
+Connection ~ 1700 6600
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7407/SN7407.sub b/library/SubcircuitLibrary/SN7407/SN7407.sub
new file mode 100644
index 000000000..52ea34539
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/SN7407.sub
@@ -0,0 +1,68 @@
+* Subcircuit SN7407
+.subckt SN7407 net-_d1-pad2_ net-_q4-pad1_ net-_d2-pad2_ net-_q8-pad1_ net-_d3-pad2_ net-_q15-pad1_ net-_d1-pad1_ net-_q16-pad1_ net-_d4-pad2_ net-_q23-pad1_ net-_d5-pad2_ net-_q24-pad1_ net-_d6-pad2_ net-_r1-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\sn7407\sn7407.cir
+.include D.lib
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q2-pad1_ net-_q1-pad1_ net-_q2-pad3_ Q2N2222
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d1-pad1_ Q2N2222
+q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 6k
+r2 net-_r1-pad1_ net-_q2-pad1_ 3.4k
+r3 net-_q2-pad3_ net-_q3-pad2_ 100
+r4 net-_q3-pad2_ net-_d1-pad1_ 1k
+r5 net-_r1-pad1_ net-_q3-pad1_ 1.6k
+q5 net-_q5-pad1_ net-_q5-pad2_ net-_d2-pad2_ Q2N2222
+q6 net-_q6-pad1_ net-_q5-pad1_ net-_q6-pad3_ Q2N2222
+q7 net-_q7-pad1_ net-_q7-pad2_ net-_d1-pad1_ Q2N2222
+q8 net-_q8-pad1_ net-_q7-pad1_ net-_d1-pad1_ Q2N2222
+d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148
+r6 net-_r1-pad1_ net-_q5-pad2_ 6k
+r7 net-_r1-pad1_ net-_q6-pad1_ 3.4k
+r8 net-_q6-pad3_ net-_q7-pad2_ 100
+r9 net-_q7-pad2_ net-_d1-pad1_ 1k
+r10 net-_r1-pad1_ net-_q7-pad1_ 1.6k
+q9 net-_q11-pad2_ net-_q9-pad2_ net-_d3-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_d1-pad1_ Q2N2222
+q15 net-_q15-pad1_ net-_q13-pad1_ net-_d1-pad1_ Q2N2222
+d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148
+r11 net-_r1-pad1_ net-_q9-pad2_ 6k
+r13 net-_r1-pad1_ net-_q11-pad1_ 3.4k
+r14 net-_q11-pad3_ net-_q13-pad2_ 100
+r15 net-_q13-pad2_ net-_d1-pad1_ 1k
+r19 net-_r1-pad1_ net-_q13-pad1_ 1.6k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_d4-pad2_ Q2N2222
+q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222
+q14 net-_q14-pad1_ net-_q14-pad2_ net-_d1-pad1_ Q2N2222
+q16 net-_q16-pad1_ net-_q14-pad1_ net-_d1-pad1_ Q2N2222
+d4 net-_d1-pad1_ net-_d4-pad2_ 1N4148
+r12 net-_r1-pad1_ net-_q10-pad2_ 6k
+r16 net-_r1-pad1_ net-_q12-pad1_ 3.4k
+r17 net-_q12-pad3_ net-_q14-pad2_ 100
+r18 net-_q14-pad2_ net-_d1-pad1_ 1k
+r20 net-_r1-pad1_ net-_q14-pad1_ 1.6k
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d5-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q17-pad1_ net-_q19-pad3_ Q2N2222
+q21 net-_q21-pad1_ net-_q21-pad2_ net-_d1-pad1_ Q2N2222
+q23 net-_q23-pad1_ net-_q21-pad1_ net-_d1-pad1_ Q2N2222
+d5 net-_d1-pad1_ net-_d5-pad2_ 1N4148
+r21 net-_r1-pad1_ net-_q17-pad2_ 6k
+r23 net-_r1-pad1_ net-_q19-pad1_ 3.4k
+r24 net-_q19-pad3_ net-_q21-pad2_ 100
+r25 net-_q21-pad2_ net-_d1-pad1_ 1k
+r29 net-_r1-pad1_ net-_q21-pad1_ 1.6k
+q18 net-_q18-pad1_ net-_q18-pad2_ net-_d6-pad2_ Q2N2222
+q20 net-_q20-pad1_ net-_q18-pad1_ net-_q20-pad3_ Q2N2222
+q22 net-_q22-pad1_ net-_q22-pad2_ net-_d1-pad1_ Q2N2222
+q24 net-_q24-pad1_ net-_q22-pad1_ net-_d1-pad1_ Q2N2222
+d6 net-_d1-pad1_ net-_d6-pad2_ 1N4148
+r22 net-_r1-pad1_ net-_q18-pad2_ 6k
+r26 net-_r1-pad1_ net-_q20-pad1_ 3.4k
+r27 net-_q20-pad3_ net-_q22-pad2_ 100
+r28 net-_q22-pad2_ net-_d1-pad1_ 1k
+r30 net-_r1-pad1_ net-_q22-pad1_ 1.6k
+* Control Statements
+
+.ends SN7407
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7407/SN7407_Previous_Values.xml b/library/SubcircuitLibrary/SN7407/SN7407_Previous_Values.xml
new file mode 100644
index 000000000..1ade3ec19
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/SN7407_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7407/analysis b/library/SubcircuitLibrary/SN7407/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7407/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74116/SN74116-cache.lib b/library/SubcircuitLibrary/SN74116/SN74116-cache.lib
new file mode 100644
index 000000000..af784f684
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74116/SN74116-cache.lib
@@ -0,0 +1,111 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74116/SN74116.cir b/library/SubcircuitLibrary/SN74116/SN74116.cir
new file mode 100644
index 000000000..367c4ea10
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74116/SN74116.cir
@@ -0,0 +1,127 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74116\SN74116.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 18:51:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U3-Pad1_ Net-_U3-Pad2_ d_inverter
+U4 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U10-Pad1_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ d_inverter
+U6 Net-_U10-Pad1_ Net-_U14-Pad2_ d_inverter
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nand
+U16 Net-_U10-Pad1_ Net-_U15-Pad2_ Net-_U16-Pad3_ d_and
+U15 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_and
+U30 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U30-Pad3_ d_nor
+U36 Net-_U14-Pad3_ Net-_U30-Pad3_ Net-_U36-Pad3_ d_and
+U54 Net-_U43-Pad2_ Net-_U44-Pad2_ Net-_U14-Pad1_ d_and
+U44 Net-_U36-Pad3_ Net-_U44-Pad2_ d_inverter
+U5 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand
+U13 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U13-Pad3_ d_and
+U12 Net-_U11-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and
+U29 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U29-Pad3_ d_nor
+U35 Net-_U11-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_and
+U53 Net-_U41-Pad2_ Net-_U42-Pad2_ Net-_U11-Pad1_ d_and
+U41 Net-_U3-Pad2_ Net-_U41-Pad2_ d_inverter
+U42 Net-_U35-Pad3_ Net-_U42-Pad2_ d_inverter
+U9 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U23 Net-_U23-Pad1_ Net-_U10-Pad2_ Net-_U23-Pad3_ d_nand
+U27 Net-_U10-Pad1_ Net-_U25-Pad2_ Net-_U27-Pad3_ d_and
+U25 Net-_U23-Pad1_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_and
+U33 Net-_U25-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_nor
+U39 Net-_U23-Pad3_ Net-_U33-Pad3_ Net-_U39-Pad3_ d_and
+U57 Net-_U49-Pad2_ Net-_U51-Pad2_ Net-_U23-Pad1_ d_and
+U49 Net-_U3-Pad2_ Net-_U49-Pad2_ d_inverter
+U51 Net-_U39-Pad3_ Net-_U51-Pad2_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U24 Net-_U23-Pad1_ Net-_U10-Pad2_ Net-_U23-Pad3_ d_nand
+U28 Net-_U10-Pad1_ Net-_U25-Pad2_ Net-_U27-Pad3_ d_and
+U26 Net-_U23-Pad1_ Net-_U25-Pad2_ Net-_U25-Pad3_ d_and
+U34 Net-_U25-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_nor
+U40 Net-_U23-Pad3_ Net-_U33-Pad3_ Net-_U39-Pad3_ d_and
+U58 Net-_U49-Pad2_ Net-_U51-Pad2_ Net-_U23-Pad1_ d_and
+U50 Net-_U3-Pad2_ Net-_U49-Pad2_ d_inverter
+U52 Net-_U39-Pad3_ Net-_U51-Pad2_ d_inverter
+U7 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter
+U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_nand
+U21 Net-_U10-Pad1_ Net-_U19-Pad2_ Net-_U21-Pad3_ d_and
+U19 Net-_U17-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and
+U31 Net-_U19-Pad3_ Net-_U21-Pad3_ Net-_U31-Pad3_ d_nor
+U37 Net-_U17-Pad3_ Net-_U31-Pad3_ Net-_U37-Pad3_ d_and
+U55 Net-_U45-Pad2_ Net-_U47-Pad2_ Net-_U17-Pad1_ d_and
+U45 Net-_U3-Pad2_ Net-_U45-Pad2_ d_inverter
+U47 Net-_U37-Pad3_ Net-_U47-Pad2_ d_inverter
+U8 Net-_U10-Pad1_ Net-_U17-Pad2_ d_inverter
+U18 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_nand
+U22 Net-_U10-Pad1_ Net-_U19-Pad2_ Net-_U21-Pad3_ d_and
+U20 Net-_U17-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_and
+U32 Net-_U19-Pad3_ Net-_U21-Pad3_ Net-_U31-Pad3_ d_nor
+U38 Net-_U17-Pad3_ Net-_U31-Pad3_ Net-_U37-Pad3_ d_and
+U56 Net-_U45-Pad2_ Net-_U47-Pad2_ Net-_U17-Pad1_ d_and
+U46 Net-_U3-Pad2_ Net-_U45-Pad2_ d_inverter
+U48 Net-_U37-Pad3_ Net-_U47-Pad2_ d_inverter
+U43 Net-_U3-Pad2_ Net-_U43-Pad2_ d_inverter
+U62 Net-_U59-Pad13_ Net-_U100-Pad1_ d_inverter
+U63 Net-_U60-Pad2_ Net-_U61-Pad2_ Net-_U63-Pad3_ d_and
+U60 Net-_U59-Pad14_ Net-_U60-Pad2_ d_inverter
+U61 Net-_U59-Pad15_ Net-_U61-Pad2_ d_inverter
+U65 Net-_U63-Pad3_ Net-_U65-Pad2_ d_inverter
+U73 Net-_U113-Pad3_ Net-_U65-Pad2_ Net-_U73-Pad3_ d_nand
+U75 Net-_U63-Pad3_ Net-_U59-Pad16_ Net-_U75-Pad3_ d_and
+U74 Net-_U113-Pad3_ Net-_U59-Pad16_ Net-_U74-Pad3_ d_and
+U89 Net-_U74-Pad3_ Net-_U75-Pad3_ Net-_U89-Pad3_ d_nor
+U95 Net-_U73-Pad3_ Net-_U89-Pad3_ Net-_U103-Pad1_ d_and
+U113 Net-_U102-Pad2_ Net-_U103-Pad2_ Net-_U113-Pad3_ d_and
+U103 Net-_U103-Pad1_ Net-_U103-Pad2_ d_inverter
+U64 Net-_U63-Pad3_ Net-_U64-Pad2_ d_inverter
+U70 Net-_U112-Pad3_ Net-_U64-Pad2_ Net-_U70-Pad3_ d_nand
+U72 Net-_U63-Pad3_ Net-_U59-Pad18_ Net-_U72-Pad3_ d_and
+U71 Net-_U112-Pad3_ Net-_U59-Pad18_ Net-_U71-Pad3_ d_and
+U88 Net-_U71-Pad3_ Net-_U72-Pad3_ Net-_U88-Pad3_ d_nor
+U94 Net-_U70-Pad3_ Net-_U88-Pad3_ Net-_U101-Pad1_ d_and
+U112 Net-_U100-Pad2_ Net-_U101-Pad2_ Net-_U112-Pad3_ d_and
+U100 Net-_U100-Pad1_ Net-_U100-Pad2_ d_inverter
+U101 Net-_U101-Pad1_ Net-_U101-Pad2_ d_inverter
+U68 Net-_U63-Pad3_ Net-_U68-Pad2_ d_inverter
+U82 Net-_U116-Pad3_ Net-_U68-Pad2_ Net-_U82-Pad3_ d_nand
+U86 Net-_U63-Pad3_ Net-_U59-Pad22_ Net-_U86-Pad3_ d_and
+U84 Net-_U116-Pad3_ Net-_U59-Pad22_ Net-_U84-Pad3_ d_and
+U92 Net-_U84-Pad3_ Net-_U86-Pad3_ Net-_U92-Pad3_ d_nor
+U98 Net-_U82-Pad3_ Net-_U92-Pad3_ Net-_U110-Pad1_ d_and
+U116 Net-_U108-Pad2_ Net-_U110-Pad2_ Net-_U116-Pad3_ d_and
+U108 Net-_U100-Pad1_ Net-_U108-Pad2_ d_inverter
+U110 Net-_U110-Pad1_ Net-_U110-Pad2_ d_inverter
+U69 Net-_U63-Pad3_ Net-_U68-Pad2_ d_inverter
+U83 Net-_U116-Pad3_ Net-_U68-Pad2_ Net-_U82-Pad3_ d_nand
+U87 Net-_U63-Pad3_ Net-_U59-Pad22_ Net-_U86-Pad3_ d_and
+U85 Net-_U116-Pad3_ Net-_U59-Pad22_ Net-_U84-Pad3_ d_and
+U93 Net-_U84-Pad3_ Net-_U86-Pad3_ Net-_U92-Pad3_ d_nor
+U99 Net-_U82-Pad3_ Net-_U92-Pad3_ Net-_U110-Pad1_ d_and
+U117 Net-_U108-Pad2_ Net-_U110-Pad2_ Net-_U116-Pad3_ d_and
+U109 Net-_U100-Pad1_ Net-_U108-Pad2_ d_inverter
+U111 Net-_U110-Pad1_ Net-_U110-Pad2_ d_inverter
+U66 Net-_U63-Pad3_ Net-_U66-Pad2_ d_inverter
+U76 Net-_U114-Pad3_ Net-_U66-Pad2_ Net-_U76-Pad3_ d_nand
+U80 Net-_U63-Pad3_ Net-_U59-Pad20_ Net-_U80-Pad3_ d_and
+U78 Net-_U114-Pad3_ Net-_U59-Pad20_ Net-_U78-Pad3_ d_and
+U90 Net-_U78-Pad3_ Net-_U80-Pad3_ Net-_U90-Pad3_ d_nor
+U96 Net-_U76-Pad3_ Net-_U90-Pad3_ Net-_U106-Pad1_ d_and
+U114 Net-_U104-Pad2_ Net-_U106-Pad2_ Net-_U114-Pad3_ d_and
+U104 Net-_U100-Pad1_ Net-_U104-Pad2_ d_inverter
+U106 Net-_U106-Pad1_ Net-_U106-Pad2_ d_inverter
+U67 Net-_U63-Pad3_ Net-_U66-Pad2_ d_inverter
+U77 Net-_U114-Pad3_ Net-_U66-Pad2_ Net-_U76-Pad3_ d_nand
+U81 Net-_U63-Pad3_ Net-_U59-Pad20_ Net-_U80-Pad3_ d_and
+U79 Net-_U114-Pad3_ Net-_U59-Pad20_ Net-_U78-Pad3_ d_and
+U91 Net-_U78-Pad3_ Net-_U80-Pad3_ Net-_U90-Pad3_ d_nor
+U97 Net-_U76-Pad3_ Net-_U90-Pad3_ Net-_U106-Pad1_ d_and
+U115 Net-_U104-Pad2_ Net-_U106-Pad2_ Net-_U114-Pad3_ d_and
+U105 Net-_U100-Pad1_ Net-_U104-Pad2_ d_inverter
+U107 Net-_U106-Pad1_ Net-_U106-Pad2_ d_inverter
+U102 Net-_U100-Pad1_ Net-_U102-Pad2_ d_inverter
+U59 Net-_U3-Pad1_ Net-_U1-Pad1_ Net-_U2-Pad1_ Net-_U15-Pad2_ Net-_U14-Pad1_ Net-_U12-Pad2_ Net-_U11-Pad1_ Net-_U19-Pad2_ Net-_U17-Pad1_ Net-_U25-Pad2_ Net-_U23-Pad1_ ? Net-_U59-Pad13_ Net-_U59-Pad14_ Net-_U59-Pad15_ Net-_U59-Pad16_ Net-_U113-Pad3_ Net-_U59-Pad18_ Net-_U112-Pad3_ Net-_U59-Pad20_ Net-_U114-Pad3_ Net-_U59-Pad22_ Net-_U116-Pad3_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74116/SN74116.cir.out b/library/SubcircuitLibrary/SN74116/SN74116.cir.out
new file mode 100644
index 000000000..4eb44c919
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74116/SN74116.cir.out
@@ -0,0 +1,476 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74116\sn74116.cir
+
+* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter
+* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u10-pad1_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter
+* u6 net-_u10-pad1_ net-_u14-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nand
+* u16 net-_u10-pad1_ net-_u15-pad2_ net-_u16-pad3_ d_and
+* u15 net-_u14-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and
+* u30 net-_u15-pad3_ net-_u16-pad3_ net-_u30-pad3_ d_nor
+* u36 net-_u14-pad3_ net-_u30-pad3_ net-_u36-pad3_ d_and
+* u54 net-_u43-pad2_ net-_u44-pad2_ net-_u14-pad1_ d_and
+* u44 net-_u36-pad3_ net-_u44-pad2_ d_inverter
+* u5 net-_u10-pad1_ net-_u11-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u13 net-_u10-pad1_ net-_u12-pad2_ net-_u13-pad3_ d_and
+* u12 net-_u11-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u29 net-_u12-pad3_ net-_u13-pad3_ net-_u29-pad3_ d_nor
+* u35 net-_u11-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and
+* u53 net-_u41-pad2_ net-_u42-pad2_ net-_u11-pad1_ d_and
+* u41 net-_u3-pad2_ net-_u41-pad2_ d_inverter
+* u42 net-_u35-pad3_ net-_u42-pad2_ d_inverter
+* u9 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u23 net-_u23-pad1_ net-_u10-pad2_ net-_u23-pad3_ d_nand
+* u27 net-_u10-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_and
+* u25 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and
+* u33 net-_u25-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_nor
+* u39 net-_u23-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_and
+* u57 net-_u49-pad2_ net-_u51-pad2_ net-_u23-pad1_ d_and
+* u49 net-_u3-pad2_ net-_u49-pad2_ d_inverter
+* u51 net-_u39-pad3_ net-_u51-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u24 net-_u23-pad1_ net-_u10-pad2_ net-_u23-pad3_ d_nand
+* u28 net-_u10-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_and
+* u26 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and
+* u34 net-_u25-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_nor
+* u40 net-_u23-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_and
+* u58 net-_u49-pad2_ net-_u51-pad2_ net-_u23-pad1_ d_and
+* u50 net-_u3-pad2_ net-_u49-pad2_ d_inverter
+* u52 net-_u39-pad3_ net-_u51-pad2_ d_inverter
+* u7 net-_u10-pad1_ net-_u17-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand
+* u21 net-_u10-pad1_ net-_u19-pad2_ net-_u21-pad3_ d_and
+* u19 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_and
+* u31 net-_u19-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_nor
+* u37 net-_u17-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_and
+* u55 net-_u45-pad2_ net-_u47-pad2_ net-_u17-pad1_ d_and
+* u45 net-_u3-pad2_ net-_u45-pad2_ d_inverter
+* u47 net-_u37-pad3_ net-_u47-pad2_ d_inverter
+* u8 net-_u10-pad1_ net-_u17-pad2_ d_inverter
+* u18 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand
+* u22 net-_u10-pad1_ net-_u19-pad2_ net-_u21-pad3_ d_and
+* u20 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_and
+* u32 net-_u19-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_nor
+* u38 net-_u17-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_and
+* u56 net-_u45-pad2_ net-_u47-pad2_ net-_u17-pad1_ d_and
+* u46 net-_u3-pad2_ net-_u45-pad2_ d_inverter
+* u48 net-_u37-pad3_ net-_u47-pad2_ d_inverter
+* u43 net-_u3-pad2_ net-_u43-pad2_ d_inverter
+* u62 net-_u59-pad13_ net-_u100-pad1_ d_inverter
+* u63 net-_u60-pad2_ net-_u61-pad2_ net-_u63-pad3_ d_and
+* u60 net-_u59-pad14_ net-_u60-pad2_ d_inverter
+* u61 net-_u59-pad15_ net-_u61-pad2_ d_inverter
+* u65 net-_u63-pad3_ net-_u65-pad2_ d_inverter
+* u73 net-_u113-pad3_ net-_u65-pad2_ net-_u73-pad3_ d_nand
+* u75 net-_u63-pad3_ net-_u59-pad16_ net-_u75-pad3_ d_and
+* u74 net-_u113-pad3_ net-_u59-pad16_ net-_u74-pad3_ d_and
+* u89 net-_u74-pad3_ net-_u75-pad3_ net-_u89-pad3_ d_nor
+* u95 net-_u73-pad3_ net-_u89-pad3_ net-_u103-pad1_ d_and
+* u113 net-_u102-pad2_ net-_u103-pad2_ net-_u113-pad3_ d_and
+* u103 net-_u103-pad1_ net-_u103-pad2_ d_inverter
+* u64 net-_u63-pad3_ net-_u64-pad2_ d_inverter
+* u70 net-_u112-pad3_ net-_u64-pad2_ net-_u70-pad3_ d_nand
+* u72 net-_u63-pad3_ net-_u59-pad18_ net-_u72-pad3_ d_and
+* u71 net-_u112-pad3_ net-_u59-pad18_ net-_u71-pad3_ d_and
+* u88 net-_u71-pad3_ net-_u72-pad3_ net-_u88-pad3_ d_nor
+* u94 net-_u70-pad3_ net-_u88-pad3_ net-_u101-pad1_ d_and
+* u112 net-_u100-pad2_ net-_u101-pad2_ net-_u112-pad3_ d_and
+* u100 net-_u100-pad1_ net-_u100-pad2_ d_inverter
+* u101 net-_u101-pad1_ net-_u101-pad2_ d_inverter
+* u68 net-_u63-pad3_ net-_u68-pad2_ d_inverter
+* u82 net-_u116-pad3_ net-_u68-pad2_ net-_u82-pad3_ d_nand
+* u86 net-_u63-pad3_ net-_u59-pad22_ net-_u86-pad3_ d_and
+* u84 net-_u116-pad3_ net-_u59-pad22_ net-_u84-pad3_ d_and
+* u92 net-_u84-pad3_ net-_u86-pad3_ net-_u92-pad3_ d_nor
+* u98 net-_u82-pad3_ net-_u92-pad3_ net-_u110-pad1_ d_and
+* u116 net-_u108-pad2_ net-_u110-pad2_ net-_u116-pad3_ d_and
+* u108 net-_u100-pad1_ net-_u108-pad2_ d_inverter
+* u110 net-_u110-pad1_ net-_u110-pad2_ d_inverter
+* u69 net-_u63-pad3_ net-_u68-pad2_ d_inverter
+* u83 net-_u116-pad3_ net-_u68-pad2_ net-_u82-pad3_ d_nand
+* u87 net-_u63-pad3_ net-_u59-pad22_ net-_u86-pad3_ d_and
+* u85 net-_u116-pad3_ net-_u59-pad22_ net-_u84-pad3_ d_and
+* u93 net-_u84-pad3_ net-_u86-pad3_ net-_u92-pad3_ d_nor
+* u99 net-_u82-pad3_ net-_u92-pad3_ net-_u110-pad1_ d_and
+* u117 net-_u108-pad2_ net-_u110-pad2_ net-_u116-pad3_ d_and
+* u109 net-_u100-pad1_ net-_u108-pad2_ d_inverter
+* u111 net-_u110-pad1_ net-_u110-pad2_ d_inverter
+* u66 net-_u63-pad3_ net-_u66-pad2_ d_inverter
+* u76 net-_u114-pad3_ net-_u66-pad2_ net-_u76-pad3_ d_nand
+* u80 net-_u63-pad3_ net-_u59-pad20_ net-_u80-pad3_ d_and
+* u78 net-_u114-pad3_ net-_u59-pad20_ net-_u78-pad3_ d_and
+* u90 net-_u78-pad3_ net-_u80-pad3_ net-_u90-pad3_ d_nor
+* u96 net-_u76-pad3_ net-_u90-pad3_ net-_u106-pad1_ d_and
+* u114 net-_u104-pad2_ net-_u106-pad2_ net-_u114-pad3_ d_and
+* u104 net-_u100-pad1_ net-_u104-pad2_ d_inverter
+* u106 net-_u106-pad1_ net-_u106-pad2_ d_inverter
+* u67 net-_u63-pad3_ net-_u66-pad2_ d_inverter
+* u77 net-_u114-pad3_ net-_u66-pad2_ net-_u76-pad3_ d_nand
+* u81 net-_u63-pad3_ net-_u59-pad20_ net-_u80-pad3_ d_and
+* u79 net-_u114-pad3_ net-_u59-pad20_ net-_u78-pad3_ d_and
+* u91 net-_u78-pad3_ net-_u80-pad3_ net-_u90-pad3_ d_nor
+* u97 net-_u76-pad3_ net-_u90-pad3_ net-_u106-pad1_ d_and
+* u115 net-_u104-pad2_ net-_u106-pad2_ net-_u114-pad3_ d_and
+* u105 net-_u100-pad1_ net-_u104-pad2_ d_inverter
+* u107 net-_u106-pad1_ net-_u106-pad2_ d_inverter
+* u102 net-_u100-pad1_ net-_u102-pad2_ d_inverter
+* u59 net-_u3-pad1_ net-_u1-pad1_ net-_u2-pad1_ net-_u15-pad2_ net-_u14-pad1_ net-_u12-pad2_ net-_u11-pad1_ net-_u19-pad2_ net-_u17-pad1_ net-_u25-pad2_ net-_u23-pad1_ ? net-_u59-pad13_ net-_u59-pad14_ net-_u59-pad15_ net-_u59-pad16_ net-_u113-pad3_ net-_u59-pad18_ net-_u112-pad3_ net-_u59-pad20_ net-_u114-pad3_ net-_u59-pad22_ net-_u116-pad3_ ? port
+a1 net-_u3-pad1_ net-_u3-pad2_ u3
+a2 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u10-pad1_ u4
+a3 net-_u1-pad1_ net-_u1-pad2_ u1
+a4 net-_u2-pad1_ net-_u2-pad2_ u2
+a5 net-_u10-pad1_ net-_u14-pad2_ u6
+a6 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a7 [net-_u10-pad1_ net-_u15-pad2_ ] net-_u16-pad3_ u16
+a8 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u30-pad3_ u30
+a10 [net-_u14-pad3_ net-_u30-pad3_ ] net-_u36-pad3_ u36
+a11 [net-_u43-pad2_ net-_u44-pad2_ ] net-_u14-pad1_ u54
+a12 net-_u36-pad3_ net-_u44-pad2_ u44
+a13 net-_u10-pad1_ net-_u11-pad2_ u5
+a14 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a15 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u13-pad3_ u13
+a16 [net-_u11-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a17 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u29-pad3_ u29
+a18 [net-_u11-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35
+a19 [net-_u41-pad2_ net-_u42-pad2_ ] net-_u11-pad1_ u53
+a20 net-_u3-pad2_ net-_u41-pad2_ u41
+a21 net-_u35-pad3_ net-_u42-pad2_ u42
+a22 net-_u10-pad1_ net-_u10-pad2_ u9
+a23 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u23-pad3_ u23
+a24 [net-_u10-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u27
+a25 [net-_u23-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u25
+a26 [net-_u25-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33
+a27 [net-_u23-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39
+a28 [net-_u49-pad2_ net-_u51-pad2_ ] net-_u23-pad1_ u57
+a29 net-_u3-pad2_ net-_u49-pad2_ u49
+a30 net-_u39-pad3_ net-_u51-pad2_ u51
+a31 net-_u10-pad1_ net-_u10-pad2_ u10
+a32 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u23-pad3_ u24
+a33 [net-_u10-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u28
+a34 [net-_u23-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u26
+a35 [net-_u25-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u34
+a36 [net-_u23-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u40
+a37 [net-_u49-pad2_ net-_u51-pad2_ ] net-_u23-pad1_ u58
+a38 net-_u3-pad2_ net-_u49-pad2_ u50
+a39 net-_u39-pad3_ net-_u51-pad2_ u52
+a40 net-_u10-pad1_ net-_u17-pad2_ u7
+a41 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a42 [net-_u10-pad1_ net-_u19-pad2_ ] net-_u21-pad3_ u21
+a43 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a44 [net-_u19-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u31
+a45 [net-_u17-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37
+a46 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u17-pad1_ u55
+a47 net-_u3-pad2_ net-_u45-pad2_ u45
+a48 net-_u37-pad3_ net-_u47-pad2_ u47
+a49 net-_u10-pad1_ net-_u17-pad2_ u8
+a50 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u18
+a51 [net-_u10-pad1_ net-_u19-pad2_ ] net-_u21-pad3_ u22
+a52 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u20
+a53 [net-_u19-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u32
+a54 [net-_u17-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u38
+a55 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u17-pad1_ u56
+a56 net-_u3-pad2_ net-_u45-pad2_ u46
+a57 net-_u37-pad3_ net-_u47-pad2_ u48
+a58 net-_u3-pad2_ net-_u43-pad2_ u43
+a59 net-_u59-pad13_ net-_u100-pad1_ u62
+a60 [net-_u60-pad2_ net-_u61-pad2_ ] net-_u63-pad3_ u63
+a61 net-_u59-pad14_ net-_u60-pad2_ u60
+a62 net-_u59-pad15_ net-_u61-pad2_ u61
+a63 net-_u63-pad3_ net-_u65-pad2_ u65
+a64 [net-_u113-pad3_ net-_u65-pad2_ ] net-_u73-pad3_ u73
+a65 [net-_u63-pad3_ net-_u59-pad16_ ] net-_u75-pad3_ u75
+a66 [net-_u113-pad3_ net-_u59-pad16_ ] net-_u74-pad3_ u74
+a67 [net-_u74-pad3_ net-_u75-pad3_ ] net-_u89-pad3_ u89
+a68 [net-_u73-pad3_ net-_u89-pad3_ ] net-_u103-pad1_ u95
+a69 [net-_u102-pad2_ net-_u103-pad2_ ] net-_u113-pad3_ u113
+a70 net-_u103-pad1_ net-_u103-pad2_ u103
+a71 net-_u63-pad3_ net-_u64-pad2_ u64
+a72 [net-_u112-pad3_ net-_u64-pad2_ ] net-_u70-pad3_ u70
+a73 [net-_u63-pad3_ net-_u59-pad18_ ] net-_u72-pad3_ u72
+a74 [net-_u112-pad3_ net-_u59-pad18_ ] net-_u71-pad3_ u71
+a75 [net-_u71-pad3_ net-_u72-pad3_ ] net-_u88-pad3_ u88
+a76 [net-_u70-pad3_ net-_u88-pad3_ ] net-_u101-pad1_ u94
+a77 [net-_u100-pad2_ net-_u101-pad2_ ] net-_u112-pad3_ u112
+a78 net-_u100-pad1_ net-_u100-pad2_ u100
+a79 net-_u101-pad1_ net-_u101-pad2_ u101
+a80 net-_u63-pad3_ net-_u68-pad2_ u68
+a81 [net-_u116-pad3_ net-_u68-pad2_ ] net-_u82-pad3_ u82
+a82 [net-_u63-pad3_ net-_u59-pad22_ ] net-_u86-pad3_ u86
+a83 [net-_u116-pad3_ net-_u59-pad22_ ] net-_u84-pad3_ u84
+a84 [net-_u84-pad3_ net-_u86-pad3_ ] net-_u92-pad3_ u92
+a85 [net-_u82-pad3_ net-_u92-pad3_ ] net-_u110-pad1_ u98
+a86 [net-_u108-pad2_ net-_u110-pad2_ ] net-_u116-pad3_ u116
+a87 net-_u100-pad1_ net-_u108-pad2_ u108
+a88 net-_u110-pad1_ net-_u110-pad2_ u110
+a89 net-_u63-pad3_ net-_u68-pad2_ u69
+a90 [net-_u116-pad3_ net-_u68-pad2_ ] net-_u82-pad3_ u83
+a91 [net-_u63-pad3_ net-_u59-pad22_ ] net-_u86-pad3_ u87
+a92 [net-_u116-pad3_ net-_u59-pad22_ ] net-_u84-pad3_ u85
+a93 [net-_u84-pad3_ net-_u86-pad3_ ] net-_u92-pad3_ u93
+a94 [net-_u82-pad3_ net-_u92-pad3_ ] net-_u110-pad1_ u99
+a95 [net-_u108-pad2_ net-_u110-pad2_ ] net-_u116-pad3_ u117
+a96 net-_u100-pad1_ net-_u108-pad2_ u109
+a97 net-_u110-pad1_ net-_u110-pad2_ u111
+a98 net-_u63-pad3_ net-_u66-pad2_ u66
+a99 [net-_u114-pad3_ net-_u66-pad2_ ] net-_u76-pad3_ u76
+a100 [net-_u63-pad3_ net-_u59-pad20_ ] net-_u80-pad3_ u80
+a101 [net-_u114-pad3_ net-_u59-pad20_ ] net-_u78-pad3_ u78
+a102 [net-_u78-pad3_ net-_u80-pad3_ ] net-_u90-pad3_ u90
+a103 [net-_u76-pad3_ net-_u90-pad3_ ] net-_u106-pad1_ u96
+a104 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u114-pad3_ u114
+a105 net-_u100-pad1_ net-_u104-pad2_ u104
+a106 net-_u106-pad1_ net-_u106-pad2_ u106
+a107 net-_u63-pad3_ net-_u66-pad2_ u67
+a108 [net-_u114-pad3_ net-_u66-pad2_ ] net-_u76-pad3_ u77
+a109 [net-_u63-pad3_ net-_u59-pad20_ ] net-_u80-pad3_ u81
+a110 [net-_u114-pad3_ net-_u59-pad20_ ] net-_u78-pad3_ u79
+a111 [net-_u78-pad3_ net-_u80-pad3_ ] net-_u90-pad3_ u91
+a112 [net-_u76-pad3_ net-_u90-pad3_ ] net-_u106-pad1_ u97
+a113 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u114-pad3_ u115
+a114 net-_u100-pad1_ net-_u104-pad2_ u105
+a115 net-_u106-pad1_ net-_u106-pad2_ u107
+a116 net-_u100-pad1_ net-_u102-pad2_ u102
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u63 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u61 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u73 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u75 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u74 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u89 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u95 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u113 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u103 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u72 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u71 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u88 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u94 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u112 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u100 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u101 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u68 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u82 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u86 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u84 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u92 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u98 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u116 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u108 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u110 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u69 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u83 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u87 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u85 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u93 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u99 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u117 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u109 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u111 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u66 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u76 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u80 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u78 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u90 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u96 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u114 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u104 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u106 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u67 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u77 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u81 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u79 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u91 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u97 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u115 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u105 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u107 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u102 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74116/SN74116.pro b/library/SubcircuitLibrary/SN74116/SN74116.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74116/SN74116.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74116/SN74116.sch b/library/SubcircuitLibrary/SN74116/SN74116.sch
new file mode 100644
index 000000000..59063a388
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74116/SN74116.sch
@@ -0,0 +1,2087 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74116-cache
+EELAYER 25 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U3
+U 1 1 68690CB4
+P 4100 3850
+F 0 "U3" H 4100 3750 60 0000 C CNN
+F 1 "d_inverter" H 4100 4000 60 0000 C CNN
+F 2 "" H 4150 3800 60 0000 C CNN
+F 3 "" H 4150 3800 60 0000 C CNN
+ 1 4100 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 68690DA8
+P 4250 4400
+F 0 "U4" H 4250 4400 60 0000 C CNN
+F 1 "d_and" H 4300 4500 60 0000 C CNN
+F 2 "" H 4250 4400 60 0000 C CNN
+F 3 "" H 4250 4400 60 0000 C CNN
+ 1 4250 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U1
+U 1 1 68690E39
+P 3350 4200
+F 0 "U1" H 3350 4100 60 0000 C CNN
+F 1 "d_inverter" H 3350 4350 60 0000 C CNN
+F 2 "" H 3400 4150 60 0000 C CNN
+F 3 "" H 3400 4150 60 0000 C CNN
+ 1 3350 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 68690E58
+P 3350 4400
+F 0 "U2" H 3350 4300 60 0000 C CNN
+F 1 "d_inverter" H 3350 4550 60 0000 C CNN
+F 2 "" H 3400 4350 60 0000 C CNN
+F 3 "" H 3400 4350 60 0000 C CNN
+ 1 3350 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 68690EFC
+P 5200 4350
+F 0 "U6" H 5200 4250 60 0000 C CNN
+F 1 "d_inverter" H 5200 4500 60 0000 C CNN
+F 2 "" H 5250 4300 60 0000 C CNN
+F 3 "" H 5250 4300 60 0000 C CNN
+ 1 5200 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U14
+U 1 1 68690F7B
+P 6050 4350
+F 0 "U14" H 6050 4350 60 0000 C CNN
+F 1 "d_nand" H 6100 4450 60 0000 C CNN
+F 2 "" H 6050 4350 60 0000 C CNN
+F 3 "" H 6050 4350 60 0000 C CNN
+ 1 6050 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U16
+U 1 1 6869108F
+P 6050 5000
+F 0 "U16" H 6050 5000 60 0000 C CNN
+F 1 "d_and" H 6100 5100 60 0000 C CNN
+F 2 "" H 6050 5000 60 0000 C CNN
+F 3 "" H 6050 5000 60 0000 C CNN
+ 1 6050 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U15
+U 1 1 686910CF
+P 6050 4700
+F 0 "U15" H 6050 4700 60 0000 C CNN
+F 1 "d_and" H 6100 4800 60 0000 C CNN
+F 2 "" H 6050 4700 60 0000 C CNN
+F 3 "" H 6050 4700 60 0000 C CNN
+ 1 6050 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U30
+U 1 1 68691206
+P 7050 4850
+F 0 "U30" H 7050 4850 60 0000 C CNN
+F 1 "d_nor" H 7100 4950 60 0000 C CNN
+F 2 "" H 7050 4850 60 0000 C CNN
+F 3 "" H 7050 4850 60 0000 C CNN
+ 1 7050 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U36
+U 1 1 686912C9
+P 8050 4450
+F 0 "U36" H 8050 4450 60 0000 C CNN
+F 1 "d_and" H 8100 4550 60 0000 C CNN
+F 2 "" H 8050 4450 60 0000 C CNN
+F 3 "" H 8050 4450 60 0000 C CNN
+ 1 8050 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U54
+U 1 1 68691AAE
+P 9850 4400
+F 0 "U54" H 9850 4400 60 0000 C CNN
+F 1 "d_and" H 9900 4500 60 0000 C CNN
+F 2 "" H 9850 4400 60 0000 C CNN
+F 3 "" H 9850 4400 60 0000 C CNN
+ 1 9850 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U44
+U 1 1 68691ABA
+P 8950 4400
+F 0 "U44" H 8950 4300 60 0000 C CNN
+F 1 "d_inverter" H 8950 4550 60 0000 C CNN
+F 2 "" H 9000 4350 60 0000 C CNN
+F 3 "" H 9000 4350 60 0000 C CNN
+ 1 8950 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 68692CC3
+P 5150 5650
+F 0 "U5" H 5150 5550 60 0000 C CNN
+F 1 "d_inverter" H 5150 5800 60 0000 C CNN
+F 2 "" H 5200 5600 60 0000 C CNN
+F 3 "" H 5200 5600 60 0000 C CNN
+ 1 5150 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U11
+U 1 1 68692CC9
+P 6000 5650
+F 0 "U11" H 6000 5650 60 0000 C CNN
+F 1 "d_nand" H 6050 5750 60 0000 C CNN
+F 2 "" H 6000 5650 60 0000 C CNN
+F 3 "" H 6000 5650 60 0000 C CNN
+ 1 6000 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 68692CCF
+P 6000 6300
+F 0 "U13" H 6000 6300 60 0000 C CNN
+F 1 "d_and" H 6050 6400 60 0000 C CNN
+F 2 "" H 6000 6300 60 0000 C CNN
+F 3 "" H 6000 6300 60 0000 C CNN
+ 1 6000 6300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 68692CD5
+P 6000 6000
+F 0 "U12" H 6000 6000 60 0000 C CNN
+F 1 "d_and" H 6050 6100 60 0000 C CNN
+F 2 "" H 6000 6000 60 0000 C CNN
+F 3 "" H 6000 6000 60 0000 C CNN
+ 1 6000 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U29
+U 1 1 68692CDB
+P 7000 6150
+F 0 "U29" H 7000 6150 60 0000 C CNN
+F 1 "d_nor" H 7050 6250 60 0000 C CNN
+F 2 "" H 7000 6150 60 0000 C CNN
+F 3 "" H 7000 6150 60 0000 C CNN
+ 1 7000 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U35
+U 1 1 68692CE1
+P 8000 5750
+F 0 "U35" H 8000 5750 60 0000 C CNN
+F 1 "d_and" H 8050 5850 60 0000 C CNN
+F 2 "" H 8000 5750 60 0000 C CNN
+F 3 "" H 8000 5750 60 0000 C CNN
+ 1 8000 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U53
+U 1 1 68692CE7
+P 9800 5700
+F 0 "U53" H 9800 5700 60 0000 C CNN
+F 1 "d_and" H 9850 5800 60 0000 C CNN
+F 2 "" H 9800 5700 60 0000 C CNN
+F 3 "" H 9800 5700 60 0000 C CNN
+ 1 9800 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U41
+U 1 1 68692CED
+P 8900 5500
+F 0 "U41" H 8900 5400 60 0000 C CNN
+F 1 "d_inverter" H 8900 5650 60 0000 C CNN
+F 2 "" H 8950 5450 60 0000 C CNN
+F 3 "" H 8950 5450 60 0000 C CNN
+ 1 8900 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U42
+U 1 1 68692CF3
+P 8900 5700
+F 0 "U42" H 8900 5600 60 0000 C CNN
+F 1 "d_inverter" H 8900 5850 60 0000 C CNN
+F 2 "" H 8950 5650 60 0000 C CNN
+F 3 "" H 8950 5650 60 0000 C CNN
+ 1 8900 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 68693622
+P 5250 8100
+F 0 "U9" H 5250 8000 60 0000 C CNN
+F 1 "d_inverter" H 5250 8250 60 0000 C CNN
+F 2 "" H 5300 8050 60 0000 C CNN
+F 3 "" H 5300 8050 60 0000 C CNN
+ 1 5250 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U23
+U 1 1 68693628
+P 6100 8100
+F 0 "U23" H 6100 8100 60 0000 C CNN
+F 1 "d_nand" H 6150 8200 60 0000 C CNN
+F 2 "" H 6100 8100 60 0000 C CNN
+F 3 "" H 6100 8100 60 0000 C CNN
+ 1 6100 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U27
+U 1 1 6869362E
+P 6100 8750
+F 0 "U27" H 6100 8750 60 0000 C CNN
+F 1 "d_and" H 6150 8850 60 0000 C CNN
+F 2 "" H 6100 8750 60 0000 C CNN
+F 3 "" H 6100 8750 60 0000 C CNN
+ 1 6100 8750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U25
+U 1 1 68693634
+P 6100 8450
+F 0 "U25" H 6100 8450 60 0000 C CNN
+F 1 "d_and" H 6150 8550 60 0000 C CNN
+F 2 "" H 6100 8450 60 0000 C CNN
+F 3 "" H 6100 8450 60 0000 C CNN
+ 1 6100 8450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U33
+U 1 1 6869363A
+P 7100 8600
+F 0 "U33" H 7100 8600 60 0000 C CNN
+F 1 "d_nor" H 7150 8700 60 0000 C CNN
+F 2 "" H 7100 8600 60 0000 C CNN
+F 3 "" H 7100 8600 60 0000 C CNN
+ 1 7100 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U39
+U 1 1 68693640
+P 8100 8200
+F 0 "U39" H 8100 8200 60 0000 C CNN
+F 1 "d_and" H 8150 8300 60 0000 C CNN
+F 2 "" H 8100 8200 60 0000 C CNN
+F 3 "" H 8100 8200 60 0000 C CNN
+ 1 8100 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U57
+U 1 1 68693646
+P 9900 8150
+F 0 "U57" H 9900 8150 60 0000 C CNN
+F 1 "d_and" H 9950 8250 60 0000 C CNN
+F 2 "" H 9900 8150 60 0000 C CNN
+F 3 "" H 9900 8150 60 0000 C CNN
+ 1 9900 8150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U49
+U 1 1 6869364C
+P 9000 7950
+F 0 "U49" H 9000 7850 60 0000 C CNN
+F 1 "d_inverter" H 9000 8100 60 0000 C CNN
+F 2 "" H 9050 7900 60 0000 C CNN
+F 3 "" H 9050 7900 60 0000 C CNN
+ 1 9000 7950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U51
+U 1 1 68693652
+P 9000 8150
+F 0 "U51" H 9000 8050 60 0000 C CNN
+F 1 "d_inverter" H 9000 8300 60 0000 C CNN
+F 2 "" H 9050 8100 60 0000 C CNN
+F 3 "" H 9050 8100 60 0000 C CNN
+ 1 9000 8150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 68693BE5
+P 5250 8100
+F 0 "U10" H 5250 8000 60 0000 C CNN
+F 1 "d_inverter" H 5250 8250 60 0000 C CNN
+F 2 "" H 5300 8050 60 0000 C CNN
+F 3 "" H 5300 8050 60 0000 C CNN
+ 1 5250 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U24
+U 1 1 68693BEB
+P 6100 8100
+F 0 "U24" H 6100 8100 60 0000 C CNN
+F 1 "d_nand" H 6150 8200 60 0000 C CNN
+F 2 "" H 6100 8100 60 0000 C CNN
+F 3 "" H 6100 8100 60 0000 C CNN
+ 1 6100 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U28
+U 1 1 68693BF1
+P 6100 8750
+F 0 "U28" H 6100 8750 60 0000 C CNN
+F 1 "d_and" H 6150 8850 60 0000 C CNN
+F 2 "" H 6100 8750 60 0000 C CNN
+F 3 "" H 6100 8750 60 0000 C CNN
+ 1 6100 8750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U26
+U 1 1 68693BF7
+P 6100 8450
+F 0 "U26" H 6100 8450 60 0000 C CNN
+F 1 "d_and" H 6150 8550 60 0000 C CNN
+F 2 "" H 6100 8450 60 0000 C CNN
+F 3 "" H 6100 8450 60 0000 C CNN
+ 1 6100 8450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U34
+U 1 1 68693BFD
+P 7100 8600
+F 0 "U34" H 7100 8600 60 0000 C CNN
+F 1 "d_nor" H 7150 8700 60 0000 C CNN
+F 2 "" H 7100 8600 60 0000 C CNN
+F 3 "" H 7100 8600 60 0000 C CNN
+ 1 7100 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U40
+U 1 1 68693C03
+P 8100 8200
+F 0 "U40" H 8100 8200 60 0000 C CNN
+F 1 "d_and" H 8150 8300 60 0000 C CNN
+F 2 "" H 8100 8200 60 0000 C CNN
+F 3 "" H 8100 8200 60 0000 C CNN
+ 1 8100 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U58
+U 1 1 68693C09
+P 9900 8150
+F 0 "U58" H 9900 8150 60 0000 C CNN
+F 1 "d_and" H 9950 8250 60 0000 C CNN
+F 2 "" H 9900 8150 60 0000 C CNN
+F 3 "" H 9900 8150 60 0000 C CNN
+ 1 9900 8150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U50
+U 1 1 68693C0F
+P 9000 7950
+F 0 "U50" H 9000 7850 60 0000 C CNN
+F 1 "d_inverter" H 9000 8100 60 0000 C CNN
+F 2 "" H 9050 7900 60 0000 C CNN
+F 3 "" H 9050 7900 60 0000 C CNN
+ 1 9000 7950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U52
+U 1 1 68693C15
+P 9000 8150
+F 0 "U52" H 9000 8050 60 0000 C CNN
+F 1 "d_inverter" H 9000 8300 60 0000 C CNN
+F 2 "" H 9050 8100 60 0000 C CNN
+F 3 "" H 9050 8100 60 0000 C CNN
+ 1 9000 8150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 686942A3
+P 5200 6900
+F 0 "U7" H 5200 6800 60 0000 C CNN
+F 1 "d_inverter" H 5200 7050 60 0000 C CNN
+F 2 "" H 5250 6850 60 0000 C CNN
+F 3 "" H 5250 6850 60 0000 C CNN
+ 1 5200 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U17
+U 1 1 686942A9
+P 6050 6900
+F 0 "U17" H 6050 6900 60 0000 C CNN
+F 1 "d_nand" H 6100 7000 60 0000 C CNN
+F 2 "" H 6050 6900 60 0000 C CNN
+F 3 "" H 6050 6900 60 0000 C CNN
+ 1 6050 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U21
+U 1 1 686942AF
+P 6050 7550
+F 0 "U21" H 6050 7550 60 0000 C CNN
+F 1 "d_and" H 6100 7650 60 0000 C CNN
+F 2 "" H 6050 7550 60 0000 C CNN
+F 3 "" H 6050 7550 60 0000 C CNN
+ 1 6050 7550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U19
+U 1 1 686942B5
+P 6050 7250
+F 0 "U19" H 6050 7250 60 0000 C CNN
+F 1 "d_and" H 6100 7350 60 0000 C CNN
+F 2 "" H 6050 7250 60 0000 C CNN
+F 3 "" H 6050 7250 60 0000 C CNN
+ 1 6050 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U31
+U 1 1 686942BB
+P 7050 7400
+F 0 "U31" H 7050 7400 60 0000 C CNN
+F 1 "d_nor" H 7100 7500 60 0000 C CNN
+F 2 "" H 7050 7400 60 0000 C CNN
+F 3 "" H 7050 7400 60 0000 C CNN
+ 1 7050 7400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U37
+U 1 1 686942C1
+P 8050 7000
+F 0 "U37" H 8050 7000 60 0000 C CNN
+F 1 "d_and" H 8100 7100 60 0000 C CNN
+F 2 "" H 8050 7000 60 0000 C CNN
+F 3 "" H 8050 7000 60 0000 C CNN
+ 1 8050 7000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U55
+U 1 1 686942C7
+P 9850 6950
+F 0 "U55" H 9850 6950 60 0000 C CNN
+F 1 "d_and" H 9900 7050 60 0000 C CNN
+F 2 "" H 9850 6950 60 0000 C CNN
+F 3 "" H 9850 6950 60 0000 C CNN
+ 1 9850 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U45
+U 1 1 686942CD
+P 8950 6750
+F 0 "U45" H 8950 6650 60 0000 C CNN
+F 1 "d_inverter" H 8950 6900 60 0000 C CNN
+F 2 "" H 9000 6700 60 0000 C CNN
+F 3 "" H 9000 6700 60 0000 C CNN
+ 1 8950 6750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U47
+U 1 1 686942D3
+P 8950 6950
+F 0 "U47" H 8950 6850 60 0000 C CNN
+F 1 "d_inverter" H 8950 7100 60 0000 C CNN
+F 2 "" H 9000 6900 60 0000 C CNN
+F 3 "" H 9000 6900 60 0000 C CNN
+ 1 8950 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 686942D9
+P 5200 6900
+F 0 "U8" H 5200 6800 60 0000 C CNN
+F 1 "d_inverter" H 5200 7050 60 0000 C CNN
+F 2 "" H 5250 6850 60 0000 C CNN
+F 3 "" H 5250 6850 60 0000 C CNN
+ 1 5200 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U18
+U 1 1 686942DF
+P 6050 6900
+F 0 "U18" H 6050 6900 60 0000 C CNN
+F 1 "d_nand" H 6100 7000 60 0000 C CNN
+F 2 "" H 6050 6900 60 0000 C CNN
+F 3 "" H 6050 6900 60 0000 C CNN
+ 1 6050 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U22
+U 1 1 686942E5
+P 6050 7550
+F 0 "U22" H 6050 7550 60 0000 C CNN
+F 1 "d_and" H 6100 7650 60 0000 C CNN
+F 2 "" H 6050 7550 60 0000 C CNN
+F 3 "" H 6050 7550 60 0000 C CNN
+ 1 6050 7550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U20
+U 1 1 686942EB
+P 6050 7250
+F 0 "U20" H 6050 7250 60 0000 C CNN
+F 1 "d_and" H 6100 7350 60 0000 C CNN
+F 2 "" H 6050 7250 60 0000 C CNN
+F 3 "" H 6050 7250 60 0000 C CNN
+ 1 6050 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U32
+U 1 1 686942F1
+P 7050 7400
+F 0 "U32" H 7050 7400 60 0000 C CNN
+F 1 "d_nor" H 7100 7500 60 0000 C CNN
+F 2 "" H 7050 7400 60 0000 C CNN
+F 3 "" H 7050 7400 60 0000 C CNN
+ 1 7050 7400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U38
+U 1 1 686942F7
+P 8050 7000
+F 0 "U38" H 8050 7000 60 0000 C CNN
+F 1 "d_and" H 8100 7100 60 0000 C CNN
+F 2 "" H 8050 7000 60 0000 C CNN
+F 3 "" H 8050 7000 60 0000 C CNN
+ 1 8050 7000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U56
+U 1 1 686942FD
+P 9850 6950
+F 0 "U56" H 9850 6950 60 0000 C CNN
+F 1 "d_and" H 9900 7050 60 0000 C CNN
+F 2 "" H 9850 6950 60 0000 C CNN
+F 3 "" H 9850 6950 60 0000 C CNN
+ 1 9850 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U46
+U 1 1 68694303
+P 8950 6750
+F 0 "U46" H 8950 6650 60 0000 C CNN
+F 1 "d_inverter" H 8950 6900 60 0000 C CNN
+F 2 "" H 9000 6700 60 0000 C CNN
+F 3 "" H 9000 6700 60 0000 C CNN
+ 1 8950 6750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U48
+U 1 1 68694309
+P 8950 6950
+F 0 "U48" H 8950 6850 60 0000 C CNN
+F 1 "d_inverter" H 8950 7100 60 0000 C CNN
+F 2 "" H 9000 6900 60 0000 C CNN
+F 3 "" H 9000 6900 60 0000 C CNN
+ 1 8950 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U43
+U 1 1 68691AB4
+P 8950 4200
+F 0 "U43" H 8950 4100 60 0000 C CNN
+F 1 "d_inverter" H 8950 4350 60 0000 C CNN
+F 2 "" H 9000 4150 60 0000 C CNN
+F 3 "" H 9000 4150 60 0000 C CNN
+ 1 8950 4200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3650 4200 3800 4200
+Wire Wire Line
+ 3800 4200 3800 4300
+Wire Wire Line
+ 3650 4400 3800 4400
+Wire Wire Line
+ 4700 4350 4900 4350
+Wire Wire Line
+ 5500 4350 5600 4350
+Wire Wire Line
+ 5600 4250 5500 4250
+Wire Wire Line
+ 5500 3750 5500 4600
+Wire Wire Line
+ 5500 4600 5600 4600
+Wire Wire Line
+ 5600 4700 5500 4700
+Wire Wire Line
+ 5500 4700 5500 5000
+Wire Wire Line
+ 3900 5000 5600 5000
+Wire Wire Line
+ 4800 4350 4800 8650
+Wire Wire Line
+ 4800 4900 5600 4900
+Connection ~ 4800 4350
+Wire Wire Line
+ 6500 4650 6600 4650
+Wire Wire Line
+ 6600 4650 6600 4750
+Wire Wire Line
+ 6500 4950 6600 4950
+Wire Wire Line
+ 6600 4950 6600 4850
+Wire Wire Line
+ 7500 4800 7600 4800
+Wire Wire Line
+ 7600 4800 7600 4450
+Wire Wire Line
+ 6500 4300 7600 4300
+Wire Wire Line
+ 7600 4300 7600 4350
+Wire Wire Line
+ 8500 4400 8650 4400
+Wire Wire Line
+ 9250 4400 9400 4400
+Wire Wire Line
+ 9250 4200 9400 4200
+Wire Wire Line
+ 9400 4200 9400 4300
+Wire Wire Line
+ 4400 3850 8650 3850
+Wire Wire Line
+ 10300 4350 10900 4350
+Wire Wire Line
+ 10450 4350 10450 3750
+Wire Wire Line
+ 10450 3750 5500 3750
+Connection ~ 5500 4250
+Connection ~ 5500 5000
+Wire Wire Line
+ 4800 5650 4850 5650
+Connection ~ 4800 4900
+Wire Wire Line
+ 5450 5650 5550 5650
+Wire Wire Line
+ 6450 5600 7550 5600
+Wire Wire Line
+ 7550 5600 7550 5650
+Wire Wire Line
+ 5550 5550 5450 5550
+Wire Wire Line
+ 5450 5250 5450 5900
+Wire Wire Line
+ 5450 5900 5550 5900
+Wire Wire Line
+ 5550 6000 5450 6000
+Wire Wire Line
+ 5450 6000 5450 6300
+Wire Wire Line
+ 3850 6300 5550 6300
+Wire Wire Line
+ 6450 5950 6550 5950
+Wire Wire Line
+ 6550 5950 6550 6050
+Wire Wire Line
+ 6450 6250 6550 6250
+Wire Wire Line
+ 6550 6250 6550 6150
+Wire Wire Line
+ 7450 6100 7550 6100
+Wire Wire Line
+ 7550 6100 7550 5750
+Wire Wire Line
+ 8450 5700 8600 5700
+Wire Wire Line
+ 8650 3850 8650 4000
+Wire Wire Line
+ 8650 4000 8500 4000
+Wire Wire Line
+ 8500 4000 8500 7950
+Wire Wire Line
+ 8500 4200 8650 4200
+Wire Wire Line
+ 8500 5500 8600 5500
+Connection ~ 8500 4200
+Wire Wire Line
+ 9200 5500 9350 5500
+Wire Wire Line
+ 9350 5500 9350 5600
+Wire Wire Line
+ 9200 5700 9350 5700
+Wire Wire Line
+ 10250 5650 10900 5650
+Wire Wire Line
+ 10450 5650 10450 5250
+Wire Wire Line
+ 10450 5250 5450 5250
+Connection ~ 5450 5550
+Connection ~ 5450 6300
+Wire Wire Line
+ 4800 6200 5550 6200
+Connection ~ 4800 5650
+Wire Wire Line
+ 4800 6900 4900 6900
+Connection ~ 4800 6200
+Wire Wire Line
+ 5500 6900 5600 6900
+Wire Wire Line
+ 6500 6850 7600 6850
+Wire Wire Line
+ 7600 6850 7600 6900
+Wire Wire Line
+ 6500 7200 6600 7200
+Wire Wire Line
+ 6600 7200 6600 7300
+Wire Wire Line
+ 6500 7500 6600 7500
+Wire Wire Line
+ 6600 7500 6600 7400
+Wire Wire Line
+ 7500 7350 7600 7350
+Wire Wire Line
+ 7600 7350 7600 7000
+Wire Wire Line
+ 8500 6950 8650 6950
+Wire Wire Line
+ 8500 6750 8650 6750
+Connection ~ 8500 5500
+Wire Wire Line
+ 9400 6750 9400 6850
+Wire Wire Line
+ 9250 6950 9400 6950
+Wire Wire Line
+ 9250 6750 9400 6750
+Wire Wire Line
+ 10300 6900 11000 6900
+Wire Wire Line
+ 10450 6900 10450 6500
+Wire Wire Line
+ 10450 6500 5500 6500
+Wire Wire Line
+ 5500 6500 5500 7150
+Wire Wire Line
+ 5500 6800 5600 6800
+Wire Wire Line
+ 5500 7150 5600 7150
+Connection ~ 5500 6800
+Wire Wire Line
+ 5600 7250 5500 7250
+Wire Wire Line
+ 5500 7250 5500 7550
+Wire Wire Line
+ 3850 7550 5600 7550
+Connection ~ 5500 7550
+Wire Wire Line
+ 4800 7450 5600 7450
+Connection ~ 4800 6900
+Wire Wire Line
+ 4800 8100 4950 8100
+Connection ~ 4800 7450
+Wire Wire Line
+ 5550 8100 5650 8100
+Wire Wire Line
+ 7650 8050 7650 8100
+Wire Wire Line
+ 6550 8050 7650 8050
+Wire Wire Line
+ 6550 8400 6650 8400
+Wire Wire Line
+ 6650 8400 6650 8500
+Wire Wire Line
+ 6550 8700 6650 8700
+Wire Wire Line
+ 6650 8700 6650 8600
+Wire Wire Line
+ 7550 8550 7650 8550
+Wire Wire Line
+ 7650 8550 7650 8200
+Wire Wire Line
+ 8550 8150 8700 8150
+Wire Wire Line
+ 9300 8150 9450 8150
+Wire Wire Line
+ 9300 7950 9450 7950
+Wire Wire Line
+ 9450 7950 9450 8050
+Wire Wire Line
+ 8500 7950 8700 7950
+Connection ~ 8500 6750
+Wire Wire Line
+ 10350 8100 11050 8100
+Wire Wire Line
+ 10450 8100 10450 7800
+Wire Wire Line
+ 10450 7800 5500 7800
+Wire Wire Line
+ 5500 7800 5500 8350
+Wire Wire Line
+ 5500 8000 5650 8000
+Wire Wire Line
+ 5500 8350 5650 8350
+Connection ~ 5500 8000
+Wire Wire Line
+ 5650 8450 5500 8450
+Wire Wire Line
+ 5500 8450 5500 8750
+Wire Wire Line
+ 3850 8750 5650 8750
+Wire Wire Line
+ 4800 8650 5650 8650
+Connection ~ 4800 8100
+Connection ~ 5500 8750
+Connection ~ 10450 4350
+Connection ~ 10450 5650
+Connection ~ 10450 6900
+Connection ~ 10450 8100
+Wire Wire Line
+ 2700 4400 3050 4400
+Wire Wire Line
+ 2700 4200 3050 4200
+Wire Wire Line
+ 3100 3850 3800 3850
+$Comp
+L d_inverter U62
+U 1 1 686ABC95
+P 13450 3750
+F 0 "U62" H 13450 3650 60 0000 C CNN
+F 1 "d_inverter" H 13450 3900 60 0000 C CNN
+F 2 "" H 13500 3700 60 0000 C CNN
+F 3 "" H 13500 3700 60 0000 C CNN
+ 1 13450 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U63
+U 1 1 686ABC9B
+P 13600 4300
+F 0 "U63" H 13600 4300 60 0000 C CNN
+F 1 "d_and" H 13650 4400 60 0000 C CNN
+F 2 "" H 13600 4300 60 0000 C CNN
+F 3 "" H 13600 4300 60 0000 C CNN
+ 1 13600 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U60
+U 1 1 686ABCA1
+P 12700 4100
+F 0 "U60" H 12700 4000 60 0000 C CNN
+F 1 "d_inverter" H 12700 4250 60 0000 C CNN
+F 2 "" H 12750 4050 60 0000 C CNN
+F 3 "" H 12750 4050 60 0000 C CNN
+ 1 12700 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U61
+U 1 1 686ABCA7
+P 12700 4300
+F 0 "U61" H 12700 4200 60 0000 C CNN
+F 1 "d_inverter" H 12700 4450 60 0000 C CNN
+F 2 "" H 12750 4250 60 0000 C CNN
+F 3 "" H 12750 4250 60 0000 C CNN
+ 1 12700 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U65
+U 1 1 686ABCAD
+P 14550 4250
+F 0 "U65" H 14550 4150 60 0000 C CNN
+F 1 "d_inverter" H 14550 4400 60 0000 C CNN
+F 2 "" H 14600 4200 60 0000 C CNN
+F 3 "" H 14600 4200 60 0000 C CNN
+ 1 14550 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U73
+U 1 1 686ABCB3
+P 15400 4250
+F 0 "U73" H 15400 4250 60 0000 C CNN
+F 1 "d_nand" H 15450 4350 60 0000 C CNN
+F 2 "" H 15400 4250 60 0000 C CNN
+F 3 "" H 15400 4250 60 0000 C CNN
+ 1 15400 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U75
+U 1 1 686ABCB9
+P 15400 4900
+F 0 "U75" H 15400 4900 60 0000 C CNN
+F 1 "d_and" H 15450 5000 60 0000 C CNN
+F 2 "" H 15400 4900 60 0000 C CNN
+F 3 "" H 15400 4900 60 0000 C CNN
+ 1 15400 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U74
+U 1 1 686ABCBF
+P 15400 4600
+F 0 "U74" H 15400 4600 60 0000 C CNN
+F 1 "d_and" H 15450 4700 60 0000 C CNN
+F 2 "" H 15400 4600 60 0000 C CNN
+F 3 "" H 15400 4600 60 0000 C CNN
+ 1 15400 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U89
+U 1 1 686ABCC5
+P 16400 4750
+F 0 "U89" H 16400 4750 60 0000 C CNN
+F 1 "d_nor" H 16450 4850 60 0000 C CNN
+F 2 "" H 16400 4750 60 0000 C CNN
+F 3 "" H 16400 4750 60 0000 C CNN
+ 1 16400 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U95
+U 1 1 686ABCCB
+P 17400 4350
+F 0 "U95" H 17400 4350 60 0000 C CNN
+F 1 "d_and" H 17450 4450 60 0000 C CNN
+F 2 "" H 17400 4350 60 0000 C CNN
+F 3 "" H 17400 4350 60 0000 C CNN
+ 1 17400 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U113
+U 1 1 686ABCD1
+P 19200 4300
+F 0 "U113" H 19200 4300 60 0000 C CNN
+F 1 "d_and" H 19250 4400 60 0000 C CNN
+F 2 "" H 19200 4300 60 0000 C CNN
+F 3 "" H 19200 4300 60 0000 C CNN
+ 1 19200 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U103
+U 1 1 686ABCD7
+P 18300 4300
+F 0 "U103" H 18300 4200 60 0000 C CNN
+F 1 "d_inverter" H 18300 4450 60 0000 C CNN
+F 2 "" H 18350 4250 60 0000 C CNN
+F 3 "" H 18350 4250 60 0000 C CNN
+ 1 18300 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U64
+U 1 1 686ABCDD
+P 14500 5550
+F 0 "U64" H 14500 5450 60 0000 C CNN
+F 1 "d_inverter" H 14500 5700 60 0000 C CNN
+F 2 "" H 14550 5500 60 0000 C CNN
+F 3 "" H 14550 5500 60 0000 C CNN
+ 1 14500 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U70
+U 1 1 686ABCE3
+P 15350 5550
+F 0 "U70" H 15350 5550 60 0000 C CNN
+F 1 "d_nand" H 15400 5650 60 0000 C CNN
+F 2 "" H 15350 5550 60 0000 C CNN
+F 3 "" H 15350 5550 60 0000 C CNN
+ 1 15350 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U72
+U 1 1 686ABCE9
+P 15350 6200
+F 0 "U72" H 15350 6200 60 0000 C CNN
+F 1 "d_and" H 15400 6300 60 0000 C CNN
+F 2 "" H 15350 6200 60 0000 C CNN
+F 3 "" H 15350 6200 60 0000 C CNN
+ 1 15350 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U71
+U 1 1 686ABCEF
+P 15350 5900
+F 0 "U71" H 15350 5900 60 0000 C CNN
+F 1 "d_and" H 15400 6000 60 0000 C CNN
+F 2 "" H 15350 5900 60 0000 C CNN
+F 3 "" H 15350 5900 60 0000 C CNN
+ 1 15350 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U88
+U 1 1 686ABCF5
+P 16350 6050
+F 0 "U88" H 16350 6050 60 0000 C CNN
+F 1 "d_nor" H 16400 6150 60 0000 C CNN
+F 2 "" H 16350 6050 60 0000 C CNN
+F 3 "" H 16350 6050 60 0000 C CNN
+ 1 16350 6050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U94
+U 1 1 686ABCFB
+P 17350 5650
+F 0 "U94" H 17350 5650 60 0000 C CNN
+F 1 "d_and" H 17400 5750 60 0000 C CNN
+F 2 "" H 17350 5650 60 0000 C CNN
+F 3 "" H 17350 5650 60 0000 C CNN
+ 1 17350 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U112
+U 1 1 686ABD01
+P 19150 5600
+F 0 "U112" H 19150 5600 60 0000 C CNN
+F 1 "d_and" H 19200 5700 60 0000 C CNN
+F 2 "" H 19150 5600 60 0000 C CNN
+F 3 "" H 19150 5600 60 0000 C CNN
+ 1 19150 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U100
+U 1 1 686ABD07
+P 18250 5400
+F 0 "U100" H 18250 5300 60 0000 C CNN
+F 1 "d_inverter" H 18250 5550 60 0000 C CNN
+F 2 "" H 18300 5350 60 0000 C CNN
+F 3 "" H 18300 5350 60 0000 C CNN
+ 1 18250 5400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U101
+U 1 1 686ABD0D
+P 18250 5600
+F 0 "U101" H 18250 5500 60 0000 C CNN
+F 1 "d_inverter" H 18250 5750 60 0000 C CNN
+F 2 "" H 18300 5550 60 0000 C CNN
+F 3 "" H 18300 5550 60 0000 C CNN
+ 1 18250 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U68
+U 1 1 686ABD13
+P 14600 8000
+F 0 "U68" H 14600 7900 60 0000 C CNN
+F 1 "d_inverter" H 14600 8150 60 0000 C CNN
+F 2 "" H 14650 7950 60 0000 C CNN
+F 3 "" H 14650 7950 60 0000 C CNN
+ 1 14600 8000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U82
+U 1 1 686ABD19
+P 15450 8000
+F 0 "U82" H 15450 8000 60 0000 C CNN
+F 1 "d_nand" H 15500 8100 60 0000 C CNN
+F 2 "" H 15450 8000 60 0000 C CNN
+F 3 "" H 15450 8000 60 0000 C CNN
+ 1 15450 8000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U86
+U 1 1 686ABD1F
+P 15450 8650
+F 0 "U86" H 15450 8650 60 0000 C CNN
+F 1 "d_and" H 15500 8750 60 0000 C CNN
+F 2 "" H 15450 8650 60 0000 C CNN
+F 3 "" H 15450 8650 60 0000 C CNN
+ 1 15450 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U84
+U 1 1 686ABD25
+P 15450 8350
+F 0 "U84" H 15450 8350 60 0000 C CNN
+F 1 "d_and" H 15500 8450 60 0000 C CNN
+F 2 "" H 15450 8350 60 0000 C CNN
+F 3 "" H 15450 8350 60 0000 C CNN
+ 1 15450 8350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U92
+U 1 1 686ABD2B
+P 16450 8500
+F 0 "U92" H 16450 8500 60 0000 C CNN
+F 1 "d_nor" H 16500 8600 60 0000 C CNN
+F 2 "" H 16450 8500 60 0000 C CNN
+F 3 "" H 16450 8500 60 0000 C CNN
+ 1 16450 8500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U98
+U 1 1 686ABD31
+P 17450 8100
+F 0 "U98" H 17450 8100 60 0000 C CNN
+F 1 "d_and" H 17500 8200 60 0000 C CNN
+F 2 "" H 17450 8100 60 0000 C CNN
+F 3 "" H 17450 8100 60 0000 C CNN
+ 1 17450 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U116
+U 1 1 686ABD37
+P 19250 8050
+F 0 "U116" H 19250 8050 60 0000 C CNN
+F 1 "d_and" H 19300 8150 60 0000 C CNN
+F 2 "" H 19250 8050 60 0000 C CNN
+F 3 "" H 19250 8050 60 0000 C CNN
+ 1 19250 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U108
+U 1 1 686ABD3D
+P 18350 7850
+F 0 "U108" H 18350 7750 60 0000 C CNN
+F 1 "d_inverter" H 18350 8000 60 0000 C CNN
+F 2 "" H 18400 7800 60 0000 C CNN
+F 3 "" H 18400 7800 60 0000 C CNN
+ 1 18350 7850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U110
+U 1 1 686ABD43
+P 18350 8050
+F 0 "U110" H 18350 7950 60 0000 C CNN
+F 1 "d_inverter" H 18350 8200 60 0000 C CNN
+F 2 "" H 18400 8000 60 0000 C CNN
+F 3 "" H 18400 8000 60 0000 C CNN
+ 1 18350 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U69
+U 1 1 686ABD49
+P 14600 8000
+F 0 "U69" H 14600 7900 60 0000 C CNN
+F 1 "d_inverter" H 14600 8150 60 0000 C CNN
+F 2 "" H 14650 7950 60 0000 C CNN
+F 3 "" H 14650 7950 60 0000 C CNN
+ 1 14600 8000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U83
+U 1 1 686ABD4F
+P 15450 8000
+F 0 "U83" H 15450 8000 60 0000 C CNN
+F 1 "d_nand" H 15500 8100 60 0000 C CNN
+F 2 "" H 15450 8000 60 0000 C CNN
+F 3 "" H 15450 8000 60 0000 C CNN
+ 1 15450 8000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U87
+U 1 1 686ABD55
+P 15450 8650
+F 0 "U87" H 15450 8650 60 0000 C CNN
+F 1 "d_and" H 15500 8750 60 0000 C CNN
+F 2 "" H 15450 8650 60 0000 C CNN
+F 3 "" H 15450 8650 60 0000 C CNN
+ 1 15450 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U85
+U 1 1 686ABD5B
+P 15450 8350
+F 0 "U85" H 15450 8350 60 0000 C CNN
+F 1 "d_and" H 15500 8450 60 0000 C CNN
+F 2 "" H 15450 8350 60 0000 C CNN
+F 3 "" H 15450 8350 60 0000 C CNN
+ 1 15450 8350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U93
+U 1 1 686ABD61
+P 16450 8500
+F 0 "U93" H 16450 8500 60 0000 C CNN
+F 1 "d_nor" H 16500 8600 60 0000 C CNN
+F 2 "" H 16450 8500 60 0000 C CNN
+F 3 "" H 16450 8500 60 0000 C CNN
+ 1 16450 8500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U99
+U 1 1 686ABD67
+P 17450 8100
+F 0 "U99" H 17450 8100 60 0000 C CNN
+F 1 "d_and" H 17500 8200 60 0000 C CNN
+F 2 "" H 17450 8100 60 0000 C CNN
+F 3 "" H 17450 8100 60 0000 C CNN
+ 1 17450 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U117
+U 1 1 686ABD6D
+P 19250 8050
+F 0 "U117" H 19250 8050 60 0000 C CNN
+F 1 "d_and" H 19300 8150 60 0000 C CNN
+F 2 "" H 19250 8050 60 0000 C CNN
+F 3 "" H 19250 8050 60 0000 C CNN
+ 1 19250 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U109
+U 1 1 686ABD73
+P 18350 7850
+F 0 "U109" H 18350 7750 60 0000 C CNN
+F 1 "d_inverter" H 18350 8000 60 0000 C CNN
+F 2 "" H 18400 7800 60 0000 C CNN
+F 3 "" H 18400 7800 60 0000 C CNN
+ 1 18350 7850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U111
+U 1 1 686ABD79
+P 18350 8050
+F 0 "U111" H 18350 7950 60 0000 C CNN
+F 1 "d_inverter" H 18350 8200 60 0000 C CNN
+F 2 "" H 18400 8000 60 0000 C CNN
+F 3 "" H 18400 8000 60 0000 C CNN
+ 1 18350 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U66
+U 1 1 686ABD7F
+P 14550 6800
+F 0 "U66" H 14550 6700 60 0000 C CNN
+F 1 "d_inverter" H 14550 6950 60 0000 C CNN
+F 2 "" H 14600 6750 60 0000 C CNN
+F 3 "" H 14600 6750 60 0000 C CNN
+ 1 14550 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U76
+U 1 1 686ABD85
+P 15400 6800
+F 0 "U76" H 15400 6800 60 0000 C CNN
+F 1 "d_nand" H 15450 6900 60 0000 C CNN
+F 2 "" H 15400 6800 60 0000 C CNN
+F 3 "" H 15400 6800 60 0000 C CNN
+ 1 15400 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U80
+U 1 1 686ABD8B
+P 15400 7450
+F 0 "U80" H 15400 7450 60 0000 C CNN
+F 1 "d_and" H 15450 7550 60 0000 C CNN
+F 2 "" H 15400 7450 60 0000 C CNN
+F 3 "" H 15400 7450 60 0000 C CNN
+ 1 15400 7450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U78
+U 1 1 686ABD91
+P 15400 7150
+F 0 "U78" H 15400 7150 60 0000 C CNN
+F 1 "d_and" H 15450 7250 60 0000 C CNN
+F 2 "" H 15400 7150 60 0000 C CNN
+F 3 "" H 15400 7150 60 0000 C CNN
+ 1 15400 7150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U90
+U 1 1 686ABD97
+P 16400 7300
+F 0 "U90" H 16400 7300 60 0000 C CNN
+F 1 "d_nor" H 16450 7400 60 0000 C CNN
+F 2 "" H 16400 7300 60 0000 C CNN
+F 3 "" H 16400 7300 60 0000 C CNN
+ 1 16400 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U96
+U 1 1 686ABD9D
+P 17400 6900
+F 0 "U96" H 17400 6900 60 0000 C CNN
+F 1 "d_and" H 17450 7000 60 0000 C CNN
+F 2 "" H 17400 6900 60 0000 C CNN
+F 3 "" H 17400 6900 60 0000 C CNN
+ 1 17400 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U114
+U 1 1 686ABDA3
+P 19200 6850
+F 0 "U114" H 19200 6850 60 0000 C CNN
+F 1 "d_and" H 19250 6950 60 0000 C CNN
+F 2 "" H 19200 6850 60 0000 C CNN
+F 3 "" H 19200 6850 60 0000 C CNN
+ 1 19200 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U104
+U 1 1 686ABDA9
+P 18300 6650
+F 0 "U104" H 18300 6550 60 0000 C CNN
+F 1 "d_inverter" H 18300 6800 60 0000 C CNN
+F 2 "" H 18350 6600 60 0000 C CNN
+F 3 "" H 18350 6600 60 0000 C CNN
+ 1 18300 6650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U106
+U 1 1 686ABDAF
+P 18300 6850
+F 0 "U106" H 18300 6750 60 0000 C CNN
+F 1 "d_inverter" H 18300 7000 60 0000 C CNN
+F 2 "" H 18350 6800 60 0000 C CNN
+F 3 "" H 18350 6800 60 0000 C CNN
+ 1 18300 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U67
+U 1 1 686ABDB5
+P 14550 6800
+F 0 "U67" H 14550 6700 60 0000 C CNN
+F 1 "d_inverter" H 14550 6950 60 0000 C CNN
+F 2 "" H 14600 6750 60 0000 C CNN
+F 3 "" H 14600 6750 60 0000 C CNN
+ 1 14550 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U77
+U 1 1 686ABDBB
+P 15400 6800
+F 0 "U77" H 15400 6800 60 0000 C CNN
+F 1 "d_nand" H 15450 6900 60 0000 C CNN
+F 2 "" H 15400 6800 60 0000 C CNN
+F 3 "" H 15400 6800 60 0000 C CNN
+ 1 15400 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U81
+U 1 1 686ABDC1
+P 15400 7450
+F 0 "U81" H 15400 7450 60 0000 C CNN
+F 1 "d_and" H 15450 7550 60 0000 C CNN
+F 2 "" H 15400 7450 60 0000 C CNN
+F 3 "" H 15400 7450 60 0000 C CNN
+ 1 15400 7450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U79
+U 1 1 686ABDC7
+P 15400 7150
+F 0 "U79" H 15400 7150 60 0000 C CNN
+F 1 "d_and" H 15450 7250 60 0000 C CNN
+F 2 "" H 15400 7150 60 0000 C CNN
+F 3 "" H 15400 7150 60 0000 C CNN
+ 1 15400 7150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U91
+U 1 1 686ABDCD
+P 16400 7300
+F 0 "U91" H 16400 7300 60 0000 C CNN
+F 1 "d_nor" H 16450 7400 60 0000 C CNN
+F 2 "" H 16400 7300 60 0000 C CNN
+F 3 "" H 16400 7300 60 0000 C CNN
+ 1 16400 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U97
+U 1 1 686ABDD3
+P 17400 6900
+F 0 "U97" H 17400 6900 60 0000 C CNN
+F 1 "d_and" H 17450 7000 60 0000 C CNN
+F 2 "" H 17400 6900 60 0000 C CNN
+F 3 "" H 17400 6900 60 0000 C CNN
+ 1 17400 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U115
+U 1 1 686ABDD9
+P 19200 6850
+F 0 "U115" H 19200 6850 60 0000 C CNN
+F 1 "d_and" H 19250 6950 60 0000 C CNN
+F 2 "" H 19200 6850 60 0000 C CNN
+F 3 "" H 19200 6850 60 0000 C CNN
+ 1 19200 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U105
+U 1 1 686ABDDF
+P 18300 6650
+F 0 "U105" H 18300 6550 60 0000 C CNN
+F 1 "d_inverter" H 18300 6800 60 0000 C CNN
+F 2 "" H 18350 6600 60 0000 C CNN
+F 3 "" H 18350 6600 60 0000 C CNN
+ 1 18300 6650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U107
+U 1 1 686ABDE5
+P 18300 6850
+F 0 "U107" H 18300 6750 60 0000 C CNN
+F 1 "d_inverter" H 18300 7000 60 0000 C CNN
+F 2 "" H 18350 6800 60 0000 C CNN
+F 3 "" H 18350 6800 60 0000 C CNN
+ 1 18300 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U102
+U 1 1 686ABDEB
+P 18300 4100
+F 0 "U102" H 18300 4000 60 0000 C CNN
+F 1 "d_inverter" H 18300 4250 60 0000 C CNN
+F 2 "" H 18350 4050 60 0000 C CNN
+F 3 "" H 18350 4050 60 0000 C CNN
+ 1 18300 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 13000 4100 13150 4100
+Wire Wire Line
+ 13150 4100 13150 4200
+Wire Wire Line
+ 13000 4300 13150 4300
+Wire Wire Line
+ 14050 4250 14250 4250
+Wire Wire Line
+ 14850 4250 14950 4250
+Wire Wire Line
+ 14950 4150 14850 4150
+Wire Wire Line
+ 14850 3650 14850 4500
+Wire Wire Line
+ 14850 4500 14950 4500
+Wire Wire Line
+ 14950 4600 14850 4600
+Wire Wire Line
+ 14850 4600 14850 4900
+Wire Wire Line
+ 12900 4900 14950 4900
+Wire Wire Line
+ 14150 4250 14150 8550
+Wire Wire Line
+ 14150 4800 14950 4800
+Connection ~ 14150 4250
+Wire Wire Line
+ 15850 4550 15950 4550
+Wire Wire Line
+ 15950 4550 15950 4650
+Wire Wire Line
+ 15850 4850 15950 4850
+Wire Wire Line
+ 15950 4850 15950 4750
+Wire Wire Line
+ 16850 4700 16950 4700
+Wire Wire Line
+ 16950 4700 16950 4350
+Wire Wire Line
+ 15850 4200 16950 4200
+Wire Wire Line
+ 16950 4200 16950 4250
+Wire Wire Line
+ 17850 4300 18000 4300
+Wire Wire Line
+ 18600 4300 18750 4300
+Wire Wire Line
+ 18600 4100 18750 4100
+Wire Wire Line
+ 18750 4100 18750 4200
+Wire Wire Line
+ 13750 3750 18000 3750
+Wire Wire Line
+ 19650 4250 20400 4250
+Wire Wire Line
+ 19800 4250 19800 3650
+Wire Wire Line
+ 19800 3650 14850 3650
+Connection ~ 14850 4150
+Connection ~ 14850 4900
+Wire Wire Line
+ 14150 5550 14200 5550
+Connection ~ 14150 4800
+Wire Wire Line
+ 14800 5550 14900 5550
+Wire Wire Line
+ 15800 5500 16900 5500
+Wire Wire Line
+ 16900 5500 16900 5550
+Wire Wire Line
+ 14900 5450 14800 5450
+Wire Wire Line
+ 14800 5150 14800 5800
+Wire Wire Line
+ 14800 5800 14900 5800
+Wire Wire Line
+ 14900 5900 14800 5900
+Wire Wire Line
+ 14800 5900 14800 6200
+Wire Wire Line
+ 12850 6200 14900 6200
+Wire Wire Line
+ 15800 5850 15900 5850
+Wire Wire Line
+ 15900 5850 15900 5950
+Wire Wire Line
+ 15800 6150 15900 6150
+Wire Wire Line
+ 15900 6150 15900 6050
+Wire Wire Line
+ 16800 6000 16900 6000
+Wire Wire Line
+ 16900 6000 16900 5650
+Wire Wire Line
+ 17800 5600 17950 5600
+Wire Wire Line
+ 18000 3750 18000 3900
+Wire Wire Line
+ 18000 3900 17850 3900
+Wire Wire Line
+ 17850 3900 17850 7850
+Wire Wire Line
+ 17850 4100 18000 4100
+Wire Wire Line
+ 17850 5400 17950 5400
+Connection ~ 17850 4100
+Wire Wire Line
+ 18550 5400 18700 5400
+Wire Wire Line
+ 18700 5400 18700 5500
+Wire Wire Line
+ 18550 5600 18700 5600
+Wire Wire Line
+ 19600 5550 20450 5550
+Wire Wire Line
+ 19800 5550 19800 5150
+Wire Wire Line
+ 19800 5150 14800 5150
+Connection ~ 14800 5450
+Connection ~ 14800 6200
+Wire Wire Line
+ 14150 6100 14900 6100
+Connection ~ 14150 5550
+Wire Wire Line
+ 14150 6800 14250 6800
+Connection ~ 14150 6100
+Wire Wire Line
+ 14850 6800 14950 6800
+Wire Wire Line
+ 15850 6750 16950 6750
+Wire Wire Line
+ 16950 6750 16950 6800
+Wire Wire Line
+ 15850 7100 15950 7100
+Wire Wire Line
+ 15950 7100 15950 7200
+Wire Wire Line
+ 15850 7400 15950 7400
+Wire Wire Line
+ 15950 7400 15950 7300
+Wire Wire Line
+ 16850 7250 16950 7250
+Wire Wire Line
+ 16950 7250 16950 6900
+Wire Wire Line
+ 17850 6850 18000 6850
+Wire Wire Line
+ 17850 6650 18000 6650
+Connection ~ 17850 5400
+Wire Wire Line
+ 18750 6650 18750 6750
+Wire Wire Line
+ 18600 6850 18750 6850
+Wire Wire Line
+ 18600 6650 18750 6650
+Wire Wire Line
+ 19650 6800 20450 6800
+Wire Wire Line
+ 19800 6800 19800 6400
+Wire Wire Line
+ 19800 6400 14850 6400
+Wire Wire Line
+ 14850 6400 14850 7050
+Wire Wire Line
+ 14850 6700 14950 6700
+Wire Wire Line
+ 14850 7050 14950 7050
+Connection ~ 14850 6700
+Wire Wire Line
+ 14950 7150 14850 7150
+Wire Wire Line
+ 14850 7150 14850 7450
+Wire Wire Line
+ 12850 7450 14950 7450
+Connection ~ 14850 7450
+Wire Wire Line
+ 14150 7350 14950 7350
+Connection ~ 14150 6800
+Wire Wire Line
+ 14150 8000 14300 8000
+Connection ~ 14150 7350
+Wire Wire Line
+ 14900 8000 15000 8000
+Wire Wire Line
+ 17000 7950 17000 8000
+Wire Wire Line
+ 15900 7950 17000 7950
+Wire Wire Line
+ 15900 8300 16000 8300
+Wire Wire Line
+ 16000 8300 16000 8400
+Wire Wire Line
+ 15900 8600 16000 8600
+Wire Wire Line
+ 16000 8600 16000 8500
+Wire Wire Line
+ 16900 8450 17000 8450
+Wire Wire Line
+ 17000 8450 17000 8100
+Wire Wire Line
+ 17900 8050 18050 8050
+Wire Wire Line
+ 18650 8050 18800 8050
+Wire Wire Line
+ 18650 7850 18800 7850
+Wire Wire Line
+ 18800 7850 18800 7950
+Wire Wire Line
+ 17850 7850 18050 7850
+Connection ~ 17850 6650
+Wire Wire Line
+ 19700 8000 20450 8000
+Wire Wire Line
+ 19800 8000 19800 7700
+Wire Wire Line
+ 19800 7700 14850 7700
+Wire Wire Line
+ 14850 7700 14850 8250
+Wire Wire Line
+ 14850 7900 15000 7900
+Wire Wire Line
+ 14850 8250 15000 8250
+Connection ~ 14850 7900
+Wire Wire Line
+ 15000 8350 14850 8350
+Wire Wire Line
+ 14850 8350 14850 8650
+Wire Wire Line
+ 12800 8650 15000 8650
+Wire Wire Line
+ 14150 8550 15000 8550
+Connection ~ 14150 8000
+Connection ~ 14850 8650
+Connection ~ 19800 4250
+Connection ~ 19800 5550
+Connection ~ 19800 6800
+Connection ~ 19800 8000
+Wire Wire Line
+ 12000 4300 12400 4300
+Wire Wire Line
+ 12000 4100 12400 4100
+Wire Wire Line
+ 12400 3750 13150 3750
+$Comp
+L PORT U59
+U 1 1 686ABEEC
+P 2850 3850
+F 0 "U59" H 2900 3950 30 0000 C CNN
+F 1 "PORT" H 2850 3850 30 0000 C CNN
+F 2 "" H 2850 3850 60 0000 C CNN
+F 3 "" H 2850 3850 60 0000 C CNN
+ 1 2850 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 2 1 686AC02D
+P 2450 4200
+F 0 "U59" H 2500 4300 30 0000 C CNN
+F 1 "PORT" H 2450 4200 30 0000 C CNN
+F 2 "" H 2450 4200 60 0000 C CNN
+F 3 "" H 2450 4200 60 0000 C CNN
+ 2 2450 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 3 1 686AC12E
+P 2450 4400
+F 0 "U59" H 2500 4500 30 0000 C CNN
+F 1 "PORT" H 2450 4400 30 0000 C CNN
+F 2 "" H 2450 4400 60 0000 C CNN
+F 3 "" H 2450 4400 60 0000 C CNN
+ 3 2450 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 14 1 686AC241
+P 11750 4100
+F 0 "U59" H 11800 4200 30 0000 C CNN
+F 1 "PORT" H 11750 4100 30 0000 C CNN
+F 2 "" H 11750 4100 60 0000 C CNN
+F 3 "" H 11750 4100 60 0000 C CNN
+ 14 11750 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 4 1 686AC346
+P 3650 5000
+F 0 "U59" H 3700 5100 30 0000 C CNN
+F 1 "PORT" H 3650 5000 30 0000 C CNN
+F 2 "" H 3650 5000 60 0000 C CNN
+F 3 "" H 3650 5000 60 0000 C CNN
+ 4 3650 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 5 1 686AC44D
+P 11150 4350
+F 0 "U59" H 11200 4450 30 0000 C CNN
+F 1 "PORT" H 11150 4350 30 0000 C CNN
+F 2 "" H 11150 4350 60 0000 C CNN
+F 3 "" H 11150 4350 60 0000 C CNN
+ 5 11150 4350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U59
+U 6 1 686AC556
+P 3600 6300
+F 0 "U59" H 3650 6400 30 0000 C CNN
+F 1 "PORT" H 3600 6300 30 0000 C CNN
+F 2 "" H 3600 6300 60 0000 C CNN
+F 3 "" H 3600 6300 60 0000 C CNN
+ 6 3600 6300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 7 1 686AC661
+P 11150 5650
+F 0 "U59" H 11200 5750 30 0000 C CNN
+F 1 "PORT" H 11150 5650 30 0000 C CNN
+F 2 "" H 11150 5650 60 0000 C CNN
+F 3 "" H 11150 5650 60 0000 C CNN
+ 7 11150 5650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U59
+U 8 1 686AC76E
+P 3600 7550
+F 0 "U59" H 3650 7650 30 0000 C CNN
+F 1 "PORT" H 3600 7550 30 0000 C CNN
+F 2 "" H 3600 7550 60 0000 C CNN
+F 3 "" H 3600 7550 60 0000 C CNN
+ 8 3600 7550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 9 1 686AC87D
+P 11250 6900
+F 0 "U59" H 11300 7000 30 0000 C CNN
+F 1 "PORT" H 11250 6900 30 0000 C CNN
+F 2 "" H 11250 6900 60 0000 C CNN
+F 3 "" H 11250 6900 60 0000 C CNN
+ 9 11250 6900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U59
+U 15 1 686AC98E
+P 11750 4300
+F 0 "U59" H 11800 4400 30 0000 C CNN
+F 1 "PORT" H 11750 4300 30 0000 C CNN
+F 2 "" H 11750 4300 60 0000 C CNN
+F 3 "" H 11750 4300 60 0000 C CNN
+ 15 11750 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 10 1 686ACAA3
+P 3600 8750
+F 0 "U59" H 3650 8850 30 0000 C CNN
+F 1 "PORT" H 3600 8750 30 0000 C CNN
+F 2 "" H 3600 8750 60 0000 C CNN
+F 3 "" H 3600 8750 60 0000 C CNN
+ 10 3600 8750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 16 1 686ACBBE
+P 12650 4900
+F 0 "U59" H 12700 5000 30 0000 C CNN
+F 1 "PORT" H 12650 4900 30 0000 C CNN
+F 2 "" H 12650 4900 60 0000 C CNN
+F 3 "" H 12650 4900 60 0000 C CNN
+ 16 12650 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 17 1 686ACCD5
+P 20650 4250
+F 0 "U59" H 20700 4350 30 0000 C CNN
+F 1 "PORT" H 20650 4250 30 0000 C CNN
+F 2 "" H 20650 4250 60 0000 C CNN
+F 3 "" H 20650 4250 60 0000 C CNN
+ 17 20650 4250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U59
+U 18 1 686ACDF0
+P 12600 6200
+F 0 "U59" H 12650 6300 30 0000 C CNN
+F 1 "PORT" H 12600 6200 30 0000 C CNN
+F 2 "" H 12600 6200 60 0000 C CNN
+F 3 "" H 12600 6200 60 0000 C CNN
+ 18 12600 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 19 1 686ACF0B
+P 20700 5550
+F 0 "U59" H 20750 5650 30 0000 C CNN
+F 1 "PORT" H 20700 5550 30 0000 C CNN
+F 2 "" H 20700 5550 60 0000 C CNN
+F 3 "" H 20700 5550 60 0000 C CNN
+ 19 20700 5550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U59
+U 20 1 686AD028
+P 12600 7450
+F 0 "U59" H 12650 7550 30 0000 C CNN
+F 1 "PORT" H 12600 7450 30 0000 C CNN
+F 2 "" H 12600 7450 60 0000 C CNN
+F 3 "" H 12600 7450 60 0000 C CNN
+ 20 12600 7450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 23 1 686AD149
+P 20700 8000
+F 0 "U59" H 20750 8100 30 0000 C CNN
+F 1 "PORT" H 20700 8000 30 0000 C CNN
+F 2 "" H 20700 8000 60 0000 C CNN
+F 3 "" H 20700 8000 60 0000 C CNN
+ 23 20700 8000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U59
+U 11 1 686AD26A
+P 11300 8100
+F 0 "U59" H 11350 8200 30 0000 C CNN
+F 1 "PORT" H 11300 8100 30 0000 C CNN
+F 2 "" H 11300 8100 60 0000 C CNN
+F 3 "" H 11300 8100 60 0000 C CNN
+ 11 11300 8100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U59
+U 24 1 686AD38D
+P 11800 3450
+F 0 "U59" H 11850 3550 30 0000 C CNN
+F 1 "PORT" H 11800 3450 30 0000 C CNN
+F 2 "" H 11800 3450 60 0000 C CNN
+F 3 "" H 11800 3450 60 0000 C CNN
+ 24 11800 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 21 1 686AD4B4
+P 20700 6800
+F 0 "U59" H 20750 6900 30 0000 C CNN
+F 1 "PORT" H 20700 6800 30 0000 C CNN
+F 2 "" H 20700 6800 60 0000 C CNN
+F 3 "" H 20700 6800 60 0000 C CNN
+ 21 20700 6800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U59
+U 12 1 686AD5DB
+P 11800 3250
+F 0 "U59" H 11850 3350 30 0000 C CNN
+F 1 "PORT" H 11800 3250 30 0000 C CNN
+F 2 "" H 11800 3250 60 0000 C CNN
+F 3 "" H 11800 3250 60 0000 C CNN
+ 12 11800 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 22 1 686AD704
+P 12550 8650
+F 0 "U59" H 12600 8750 30 0000 C CNN
+F 1 "PORT" H 12550 8650 30 0000 C CNN
+F 2 "" H 12550 8650 60 0000 C CNN
+F 3 "" H 12550 8650 60 0000 C CNN
+ 22 12550 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U59
+U 13 1 686AD82F
+P 12150 3750
+F 0 "U59" H 12200 3850 30 0000 C CNN
+F 1 "PORT" H 12150 3750 30 0000 C CNN
+F 2 "" H 12150 3750 60 0000 C CNN
+F 3 "" H 12150 3750 60 0000 C CNN
+ 13 12150 3750
+ 1 0 0 -1
+$EndComp
+NoConn ~ 12050 3450
+NoConn ~ 12050 3250
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74116/SN74116.sub b/library/SubcircuitLibrary/SN74116/SN74116.sub
new file mode 100644
index 000000000..6580feed4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74116/SN74116.sub
@@ -0,0 +1,470 @@
+* Subcircuit SN74116
+.subckt SN74116 net-_u3-pad1_ net-_u1-pad1_ net-_u2-pad1_ net-_u15-pad2_ net-_u14-pad1_ net-_u12-pad2_ net-_u11-pad1_ net-_u19-pad2_ net-_u17-pad1_ net-_u25-pad2_ net-_u23-pad1_ ? net-_u59-pad13_ net-_u59-pad14_ net-_u59-pad15_ net-_u59-pad16_ net-_u113-pad3_ net-_u59-pad18_ net-_u112-pad3_ net-_u59-pad20_ net-_u114-pad3_ net-_u59-pad22_ net-_u116-pad3_ ?
+* c:\fossee\esim\library\subcircuitlibrary\sn74116\sn74116.cir
+* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter
+* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u10-pad1_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter
+* u6 net-_u10-pad1_ net-_u14-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nand
+* u16 net-_u10-pad1_ net-_u15-pad2_ net-_u16-pad3_ d_and
+* u15 net-_u14-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_and
+* u30 net-_u15-pad3_ net-_u16-pad3_ net-_u30-pad3_ d_nor
+* u36 net-_u14-pad3_ net-_u30-pad3_ net-_u36-pad3_ d_and
+* u54 net-_u43-pad2_ net-_u44-pad2_ net-_u14-pad1_ d_and
+* u44 net-_u36-pad3_ net-_u44-pad2_ d_inverter
+* u5 net-_u10-pad1_ net-_u11-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand
+* u13 net-_u10-pad1_ net-_u12-pad2_ net-_u13-pad3_ d_and
+* u12 net-_u11-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+* u29 net-_u12-pad3_ net-_u13-pad3_ net-_u29-pad3_ d_nor
+* u35 net-_u11-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and
+* u53 net-_u41-pad2_ net-_u42-pad2_ net-_u11-pad1_ d_and
+* u41 net-_u3-pad2_ net-_u41-pad2_ d_inverter
+* u42 net-_u35-pad3_ net-_u42-pad2_ d_inverter
+* u9 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u23 net-_u23-pad1_ net-_u10-pad2_ net-_u23-pad3_ d_nand
+* u27 net-_u10-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_and
+* u25 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and
+* u33 net-_u25-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_nor
+* u39 net-_u23-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_and
+* u57 net-_u49-pad2_ net-_u51-pad2_ net-_u23-pad1_ d_and
+* u49 net-_u3-pad2_ net-_u49-pad2_ d_inverter
+* u51 net-_u39-pad3_ net-_u51-pad2_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u24 net-_u23-pad1_ net-_u10-pad2_ net-_u23-pad3_ d_nand
+* u28 net-_u10-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_and
+* u26 net-_u23-pad1_ net-_u25-pad2_ net-_u25-pad3_ d_and
+* u34 net-_u25-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_nor
+* u40 net-_u23-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_and
+* u58 net-_u49-pad2_ net-_u51-pad2_ net-_u23-pad1_ d_and
+* u50 net-_u3-pad2_ net-_u49-pad2_ d_inverter
+* u52 net-_u39-pad3_ net-_u51-pad2_ d_inverter
+* u7 net-_u10-pad1_ net-_u17-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand
+* u21 net-_u10-pad1_ net-_u19-pad2_ net-_u21-pad3_ d_and
+* u19 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_and
+* u31 net-_u19-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_nor
+* u37 net-_u17-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_and
+* u55 net-_u45-pad2_ net-_u47-pad2_ net-_u17-pad1_ d_and
+* u45 net-_u3-pad2_ net-_u45-pad2_ d_inverter
+* u47 net-_u37-pad3_ net-_u47-pad2_ d_inverter
+* u8 net-_u10-pad1_ net-_u17-pad2_ d_inverter
+* u18 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nand
+* u22 net-_u10-pad1_ net-_u19-pad2_ net-_u21-pad3_ d_and
+* u20 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_and
+* u32 net-_u19-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_nor
+* u38 net-_u17-pad3_ net-_u31-pad3_ net-_u37-pad3_ d_and
+* u56 net-_u45-pad2_ net-_u47-pad2_ net-_u17-pad1_ d_and
+* u46 net-_u3-pad2_ net-_u45-pad2_ d_inverter
+* u48 net-_u37-pad3_ net-_u47-pad2_ d_inverter
+* u43 net-_u3-pad2_ net-_u43-pad2_ d_inverter
+* u62 net-_u59-pad13_ net-_u100-pad1_ d_inverter
+* u63 net-_u60-pad2_ net-_u61-pad2_ net-_u63-pad3_ d_and
+* u60 net-_u59-pad14_ net-_u60-pad2_ d_inverter
+* u61 net-_u59-pad15_ net-_u61-pad2_ d_inverter
+* u65 net-_u63-pad3_ net-_u65-pad2_ d_inverter
+* u73 net-_u113-pad3_ net-_u65-pad2_ net-_u73-pad3_ d_nand
+* u75 net-_u63-pad3_ net-_u59-pad16_ net-_u75-pad3_ d_and
+* u74 net-_u113-pad3_ net-_u59-pad16_ net-_u74-pad3_ d_and
+* u89 net-_u74-pad3_ net-_u75-pad3_ net-_u89-pad3_ d_nor
+* u95 net-_u73-pad3_ net-_u89-pad3_ net-_u103-pad1_ d_and
+* u113 net-_u102-pad2_ net-_u103-pad2_ net-_u113-pad3_ d_and
+* u103 net-_u103-pad1_ net-_u103-pad2_ d_inverter
+* u64 net-_u63-pad3_ net-_u64-pad2_ d_inverter
+* u70 net-_u112-pad3_ net-_u64-pad2_ net-_u70-pad3_ d_nand
+* u72 net-_u63-pad3_ net-_u59-pad18_ net-_u72-pad3_ d_and
+* u71 net-_u112-pad3_ net-_u59-pad18_ net-_u71-pad3_ d_and
+* u88 net-_u71-pad3_ net-_u72-pad3_ net-_u88-pad3_ d_nor
+* u94 net-_u70-pad3_ net-_u88-pad3_ net-_u101-pad1_ d_and
+* u112 net-_u100-pad2_ net-_u101-pad2_ net-_u112-pad3_ d_and
+* u100 net-_u100-pad1_ net-_u100-pad2_ d_inverter
+* u101 net-_u101-pad1_ net-_u101-pad2_ d_inverter
+* u68 net-_u63-pad3_ net-_u68-pad2_ d_inverter
+* u82 net-_u116-pad3_ net-_u68-pad2_ net-_u82-pad3_ d_nand
+* u86 net-_u63-pad3_ net-_u59-pad22_ net-_u86-pad3_ d_and
+* u84 net-_u116-pad3_ net-_u59-pad22_ net-_u84-pad3_ d_and
+* u92 net-_u84-pad3_ net-_u86-pad3_ net-_u92-pad3_ d_nor
+* u98 net-_u82-pad3_ net-_u92-pad3_ net-_u110-pad1_ d_and
+* u116 net-_u108-pad2_ net-_u110-pad2_ net-_u116-pad3_ d_and
+* u108 net-_u100-pad1_ net-_u108-pad2_ d_inverter
+* u110 net-_u110-pad1_ net-_u110-pad2_ d_inverter
+* u69 net-_u63-pad3_ net-_u68-pad2_ d_inverter
+* u83 net-_u116-pad3_ net-_u68-pad2_ net-_u82-pad3_ d_nand
+* u87 net-_u63-pad3_ net-_u59-pad22_ net-_u86-pad3_ d_and
+* u85 net-_u116-pad3_ net-_u59-pad22_ net-_u84-pad3_ d_and
+* u93 net-_u84-pad3_ net-_u86-pad3_ net-_u92-pad3_ d_nor
+* u99 net-_u82-pad3_ net-_u92-pad3_ net-_u110-pad1_ d_and
+* u117 net-_u108-pad2_ net-_u110-pad2_ net-_u116-pad3_ d_and
+* u109 net-_u100-pad1_ net-_u108-pad2_ d_inverter
+* u111 net-_u110-pad1_ net-_u110-pad2_ d_inverter
+* u66 net-_u63-pad3_ net-_u66-pad2_ d_inverter
+* u76 net-_u114-pad3_ net-_u66-pad2_ net-_u76-pad3_ d_nand
+* u80 net-_u63-pad3_ net-_u59-pad20_ net-_u80-pad3_ d_and
+* u78 net-_u114-pad3_ net-_u59-pad20_ net-_u78-pad3_ d_and
+* u90 net-_u78-pad3_ net-_u80-pad3_ net-_u90-pad3_ d_nor
+* u96 net-_u76-pad3_ net-_u90-pad3_ net-_u106-pad1_ d_and
+* u114 net-_u104-pad2_ net-_u106-pad2_ net-_u114-pad3_ d_and
+* u104 net-_u100-pad1_ net-_u104-pad2_ d_inverter
+* u106 net-_u106-pad1_ net-_u106-pad2_ d_inverter
+* u67 net-_u63-pad3_ net-_u66-pad2_ d_inverter
+* u77 net-_u114-pad3_ net-_u66-pad2_ net-_u76-pad3_ d_nand
+* u81 net-_u63-pad3_ net-_u59-pad20_ net-_u80-pad3_ d_and
+* u79 net-_u114-pad3_ net-_u59-pad20_ net-_u78-pad3_ d_and
+* u91 net-_u78-pad3_ net-_u80-pad3_ net-_u90-pad3_ d_nor
+* u97 net-_u76-pad3_ net-_u90-pad3_ net-_u106-pad1_ d_and
+* u115 net-_u104-pad2_ net-_u106-pad2_ net-_u114-pad3_ d_and
+* u105 net-_u100-pad1_ net-_u104-pad2_ d_inverter
+* u107 net-_u106-pad1_ net-_u106-pad2_ d_inverter
+* u102 net-_u100-pad1_ net-_u102-pad2_ d_inverter
+a1 net-_u3-pad1_ net-_u3-pad2_ u3
+a2 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u10-pad1_ u4
+a3 net-_u1-pad1_ net-_u1-pad2_ u1
+a4 net-_u2-pad1_ net-_u2-pad2_ u2
+a5 net-_u10-pad1_ net-_u14-pad2_ u6
+a6 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a7 [net-_u10-pad1_ net-_u15-pad2_ ] net-_u16-pad3_ u16
+a8 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a9 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u30-pad3_ u30
+a10 [net-_u14-pad3_ net-_u30-pad3_ ] net-_u36-pad3_ u36
+a11 [net-_u43-pad2_ net-_u44-pad2_ ] net-_u14-pad1_ u54
+a12 net-_u36-pad3_ net-_u44-pad2_ u44
+a13 net-_u10-pad1_ net-_u11-pad2_ u5
+a14 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a15 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u13-pad3_ u13
+a16 [net-_u11-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a17 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u29-pad3_ u29
+a18 [net-_u11-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35
+a19 [net-_u41-pad2_ net-_u42-pad2_ ] net-_u11-pad1_ u53
+a20 net-_u3-pad2_ net-_u41-pad2_ u41
+a21 net-_u35-pad3_ net-_u42-pad2_ u42
+a22 net-_u10-pad1_ net-_u10-pad2_ u9
+a23 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u23-pad3_ u23
+a24 [net-_u10-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u27
+a25 [net-_u23-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u25
+a26 [net-_u25-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33
+a27 [net-_u23-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39
+a28 [net-_u49-pad2_ net-_u51-pad2_ ] net-_u23-pad1_ u57
+a29 net-_u3-pad2_ net-_u49-pad2_ u49
+a30 net-_u39-pad3_ net-_u51-pad2_ u51
+a31 net-_u10-pad1_ net-_u10-pad2_ u10
+a32 [net-_u23-pad1_ net-_u10-pad2_ ] net-_u23-pad3_ u24
+a33 [net-_u10-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u28
+a34 [net-_u23-pad1_ net-_u25-pad2_ ] net-_u25-pad3_ u26
+a35 [net-_u25-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u34
+a36 [net-_u23-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u40
+a37 [net-_u49-pad2_ net-_u51-pad2_ ] net-_u23-pad1_ u58
+a38 net-_u3-pad2_ net-_u49-pad2_ u50
+a39 net-_u39-pad3_ net-_u51-pad2_ u52
+a40 net-_u10-pad1_ net-_u17-pad2_ u7
+a41 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a42 [net-_u10-pad1_ net-_u19-pad2_ ] net-_u21-pad3_ u21
+a43 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a44 [net-_u19-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u31
+a45 [net-_u17-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u37
+a46 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u17-pad1_ u55
+a47 net-_u3-pad2_ net-_u45-pad2_ u45
+a48 net-_u37-pad3_ net-_u47-pad2_ u47
+a49 net-_u10-pad1_ net-_u17-pad2_ u8
+a50 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u18
+a51 [net-_u10-pad1_ net-_u19-pad2_ ] net-_u21-pad3_ u22
+a52 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u20
+a53 [net-_u19-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u32
+a54 [net-_u17-pad3_ net-_u31-pad3_ ] net-_u37-pad3_ u38
+a55 [net-_u45-pad2_ net-_u47-pad2_ ] net-_u17-pad1_ u56
+a56 net-_u3-pad2_ net-_u45-pad2_ u46
+a57 net-_u37-pad3_ net-_u47-pad2_ u48
+a58 net-_u3-pad2_ net-_u43-pad2_ u43
+a59 net-_u59-pad13_ net-_u100-pad1_ u62
+a60 [net-_u60-pad2_ net-_u61-pad2_ ] net-_u63-pad3_ u63
+a61 net-_u59-pad14_ net-_u60-pad2_ u60
+a62 net-_u59-pad15_ net-_u61-pad2_ u61
+a63 net-_u63-pad3_ net-_u65-pad2_ u65
+a64 [net-_u113-pad3_ net-_u65-pad2_ ] net-_u73-pad3_ u73
+a65 [net-_u63-pad3_ net-_u59-pad16_ ] net-_u75-pad3_ u75
+a66 [net-_u113-pad3_ net-_u59-pad16_ ] net-_u74-pad3_ u74
+a67 [net-_u74-pad3_ net-_u75-pad3_ ] net-_u89-pad3_ u89
+a68 [net-_u73-pad3_ net-_u89-pad3_ ] net-_u103-pad1_ u95
+a69 [net-_u102-pad2_ net-_u103-pad2_ ] net-_u113-pad3_ u113
+a70 net-_u103-pad1_ net-_u103-pad2_ u103
+a71 net-_u63-pad3_ net-_u64-pad2_ u64
+a72 [net-_u112-pad3_ net-_u64-pad2_ ] net-_u70-pad3_ u70
+a73 [net-_u63-pad3_ net-_u59-pad18_ ] net-_u72-pad3_ u72
+a74 [net-_u112-pad3_ net-_u59-pad18_ ] net-_u71-pad3_ u71
+a75 [net-_u71-pad3_ net-_u72-pad3_ ] net-_u88-pad3_ u88
+a76 [net-_u70-pad3_ net-_u88-pad3_ ] net-_u101-pad1_ u94
+a77 [net-_u100-pad2_ net-_u101-pad2_ ] net-_u112-pad3_ u112
+a78 net-_u100-pad1_ net-_u100-pad2_ u100
+a79 net-_u101-pad1_ net-_u101-pad2_ u101
+a80 net-_u63-pad3_ net-_u68-pad2_ u68
+a81 [net-_u116-pad3_ net-_u68-pad2_ ] net-_u82-pad3_ u82
+a82 [net-_u63-pad3_ net-_u59-pad22_ ] net-_u86-pad3_ u86
+a83 [net-_u116-pad3_ net-_u59-pad22_ ] net-_u84-pad3_ u84
+a84 [net-_u84-pad3_ net-_u86-pad3_ ] net-_u92-pad3_ u92
+a85 [net-_u82-pad3_ net-_u92-pad3_ ] net-_u110-pad1_ u98
+a86 [net-_u108-pad2_ net-_u110-pad2_ ] net-_u116-pad3_ u116
+a87 net-_u100-pad1_ net-_u108-pad2_ u108
+a88 net-_u110-pad1_ net-_u110-pad2_ u110
+a89 net-_u63-pad3_ net-_u68-pad2_ u69
+a90 [net-_u116-pad3_ net-_u68-pad2_ ] net-_u82-pad3_ u83
+a91 [net-_u63-pad3_ net-_u59-pad22_ ] net-_u86-pad3_ u87
+a92 [net-_u116-pad3_ net-_u59-pad22_ ] net-_u84-pad3_ u85
+a93 [net-_u84-pad3_ net-_u86-pad3_ ] net-_u92-pad3_ u93
+a94 [net-_u82-pad3_ net-_u92-pad3_ ] net-_u110-pad1_ u99
+a95 [net-_u108-pad2_ net-_u110-pad2_ ] net-_u116-pad3_ u117
+a96 net-_u100-pad1_ net-_u108-pad2_ u109
+a97 net-_u110-pad1_ net-_u110-pad2_ u111
+a98 net-_u63-pad3_ net-_u66-pad2_ u66
+a99 [net-_u114-pad3_ net-_u66-pad2_ ] net-_u76-pad3_ u76
+a100 [net-_u63-pad3_ net-_u59-pad20_ ] net-_u80-pad3_ u80
+a101 [net-_u114-pad3_ net-_u59-pad20_ ] net-_u78-pad3_ u78
+a102 [net-_u78-pad3_ net-_u80-pad3_ ] net-_u90-pad3_ u90
+a103 [net-_u76-pad3_ net-_u90-pad3_ ] net-_u106-pad1_ u96
+a104 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u114-pad3_ u114
+a105 net-_u100-pad1_ net-_u104-pad2_ u104
+a106 net-_u106-pad1_ net-_u106-pad2_ u106
+a107 net-_u63-pad3_ net-_u66-pad2_ u67
+a108 [net-_u114-pad3_ net-_u66-pad2_ ] net-_u76-pad3_ u77
+a109 [net-_u63-pad3_ net-_u59-pad20_ ] net-_u80-pad3_ u81
+a110 [net-_u114-pad3_ net-_u59-pad20_ ] net-_u78-pad3_ u79
+a111 [net-_u78-pad3_ net-_u80-pad3_ ] net-_u90-pad3_ u91
+a112 [net-_u76-pad3_ net-_u90-pad3_ ] net-_u106-pad1_ u97
+a113 [net-_u104-pad2_ net-_u106-pad2_ ] net-_u114-pad3_ u115
+a114 net-_u100-pad1_ net-_u104-pad2_ u105
+a115 net-_u106-pad1_ net-_u106-pad2_ u107
+a116 net-_u100-pad1_ net-_u102-pad2_ u102
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u54 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u29 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u53 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u57 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u58 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u50 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u55 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u56 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u48 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u62 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u63 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u60 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u61 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u65 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u73 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u75 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u74 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u89 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u95 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u113 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u103 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u64 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u70 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u72 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u71 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u88 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u94 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u112 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u100 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u101 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u68 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u82 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u86 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u84 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u92 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u98 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u116 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u108 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u110 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u69 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u83 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u87 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u85 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u93 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u99 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u117 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u109 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u111 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u66 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u76 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u80 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u78 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u90 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u96 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u114 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u104 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u106 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u67 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u77 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u81 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u79 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u91 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u97 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u115 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u105 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u107 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u102 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74116
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74116/SN74116_Previous_Values.xml b/library/SubcircuitLibrary/SN74116/SN74116_Previous_Values.xml
new file mode 100644
index 000000000..6f6d32daf
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74116/SN74116_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_inverterd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverterd_nandd_andd_andd_nord_andd_andd_inverterd_inverterd_inverter
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74116/analysis b/library/SubcircuitLibrary/SN74116/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74116/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74177/SN74177-cache.lib b/library/SubcircuitLibrary/SN74177/SN74177-cache.lib
new file mode 100644
index 000000000..527395529
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/SN74177-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# tff_1
+#
+DEF tff_1 X 0 40 Y Y 1 F N
+F0 "X" -500 -600 60 H V C CNN
+F1 "tff_1" -500 -500 60 H V C CNN
+F2 "" -500 -600 60 H I C CNN
+F3 "" -500 -600 60 H I C CNN
+DRAW
+S -250 200 200 -500 0 1 0 N
+X T 1 -450 50 200 R 50 50 1 1 I
+X CLK 2 -450 -200 200 R 50 50 1 1 I
+X CLR 3 0 -700 200 U 50 50 1 1 I
+X QBar 4 400 -200 200 L 50 50 1 1 O
+X Q 5 400 50 200 L 50 50 1 1 O
+X Set 6 0 400 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74177/SN74177-rescue.lib b/library/SubcircuitLibrary/SN74177/SN74177-rescue.lib
new file mode 100644
index 000000000..c6c3ec84c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/SN74177-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# tff-RESCUE-SN74177
+#
+DEF tff-RESCUE-SN74177 X 0 40 Y Y 1 F N
+F0 "X" -300 -450 39 H V C CNN
+F1 "tff-RESCUE-SN74177" -300 -400 39 H V C CNN
+F2 "" -300 -450 60 H I C CNN
+F3 "" -300 -450 60 H I C CNN
+DRAW
+S -150 100 150 -400 0 1 0 N
+X T 1 -350 0 200 R 50 39 1 1 I
+X CLK 2 -350 -200 200 R 50 33 1 1 I
+X CLR 3 0 -600 200 U 50 33 1 1 I
+X QBar 4 350 -200 200 L 50 33 1 1 O
+X Preset 5 0 300 200 D 50 33 1 1 I
+X Q 5 350 0 200 L 50 33 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74177/SN74177.cir b/library/SubcircuitLibrary/SN74177/SN74177.cir
new file mode 100644
index 000000000..13f72a3ae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/SN74177.cir
@@ -0,0 +1,29 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74177\SN74177.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/25 09:20:10
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U6 Net-_U16-Pad3_ Net-_U14-Pad2_ Net-_U6-Pad3_ d_nand
+U7 Net-_U17-Pad3_ Net-_U14-Pad2_ Net-_U7-Pad3_ d_nand
+U8 Net-_U19-Pad3_ Net-_U14-Pad2_ Net-_U8-Pad3_ d_nand
+U9 Net-_U18-Pad3_ Net-_U14-Pad2_ Net-_U9-Pad3_ d_nand
+U2 /13 Net-_U16-Pad2_ d_buffer
+U3 /1 /13 Net-_U14-Pad2_ d_nand
+U1 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 /11 /12 /13 ? PORT
+U4 /4 Net-_U14-Pad2_ Net-_U16-Pad1_ d_and
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nand
+U5 /10 Net-_U14-Pad2_ Net-_U17-Pad1_ d_and
+U17 Net-_U17-Pad1_ Net-_U16-Pad2_ Net-_U17-Pad3_ d_nand
+U15 /3 Net-_U14-Pad2_ Net-_U15-Pad3_ d_and
+U19 Net-_U15-Pad3_ Net-_U16-Pad2_ Net-_U19-Pad3_ d_nand
+U14 /11 Net-_U14-Pad2_ Net-_U14-Pad3_ d_and
+U18 Net-_U14-Pad3_ Net-_U16-Pad2_ Net-_U18-Pad3_ d_nand
+X1 ? /8 Net-_U6-Pad3_ ? /5 Net-_U16-Pad3_ tff_1
+X4 ? /2 Net-_U9-Pad3_ ? /12 Net-_U18-Pad3_ tff_1
+X3 ? /9 Net-_U8-Pad3_ ? /2 Net-_U19-Pad3_ tff_1
+X2 ? /6 Net-_U7-Pad3_ ? /9 Net-_U17-Pad3_ tff_1
+
+.end
diff --git a/library/SubcircuitLibrary/SN74177/SN74177.cir.out b/library/SubcircuitLibrary/SN74177/SN74177.cir.out
new file mode 100644
index 000000000..a6231dae6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/SN74177.cir.out
@@ -0,0 +1,73 @@
+* d:\fossee\esim\library\subcircuitlibrary\sn74177\sn74177.cir
+
+.include tff_1.sub
+* u6 net-_u16-pad3_ net-_u14-pad2_ net-_u6-pad3_ d_nand
+* u7 net-_u17-pad3_ net-_u14-pad2_ net-_u7-pad3_ d_nand
+* u8 net-_u19-pad3_ net-_u14-pad2_ net-_u8-pad3_ d_nand
+* u9 net-_u18-pad3_ net-_u14-pad2_ net-_u9-pad3_ d_nand
+* u2 /13 net-_u16-pad2_ d_buffer
+* u3 /1 /13 net-_u14-pad2_ d_nand
+* u1 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 /11 /12 /13 ? port
+* u4 /4 net-_u14-pad2_ net-_u16-pad1_ d_and
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nand
+* u5 /10 net-_u14-pad2_ net-_u17-pad1_ d_and
+* u17 net-_u17-pad1_ net-_u16-pad2_ net-_u17-pad3_ d_nand
+* u15 /3 net-_u14-pad2_ net-_u15-pad3_ d_and
+* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand
+* u14 /11 net-_u14-pad2_ net-_u14-pad3_ d_and
+* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand
+x1 ? /8 net-_u6-pad3_ ? /5 net-_u16-pad3_ tff_1
+x4 ? /2 net-_u9-pad3_ ? /12 net-_u18-pad3_ tff_1
+x3 ? /9 net-_u8-pad3_ ? /2 net-_u19-pad3_ tff_1
+x2 ? /6 net-_u7-pad3_ ? /9 net-_u17-pad3_ tff_1
+a1 [net-_u16-pad3_ net-_u14-pad2_ ] net-_u6-pad3_ u6
+a2 [net-_u17-pad3_ net-_u14-pad2_ ] net-_u7-pad3_ u7
+a3 [net-_u19-pad3_ net-_u14-pad2_ ] net-_u8-pad3_ u8
+a4 [net-_u18-pad3_ net-_u14-pad2_ ] net-_u9-pad3_ u9
+a5 /13 net-_u16-pad2_ u2
+a6 [/1 /13 ] net-_u14-pad2_ u3
+a7 [/4 net-_u14-pad2_ ] net-_u16-pad1_ u4
+a8 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a9 [/10 net-_u14-pad2_ ] net-_u17-pad1_ u5
+a10 [net-_u17-pad1_ net-_u16-pad2_ ] net-_u17-pad3_ u17
+a11 [/3 net-_u14-pad2_ ] net-_u15-pad3_ u15
+a12 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19
+a13 [/11 net-_u14-pad2_ ] net-_u14-pad3_ u14
+a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74177/SN74177.pro b/library/SubcircuitLibrary/SN74177/SN74177.pro
new file mode 100644
index 000000000..933444565
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/SN74177.pro
@@ -0,0 +1,74 @@
+update=06/17/25 10:45:53
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=SN74177-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74177/SN74177.sch b/library/SubcircuitLibrary/SN74177/SN74177.sch
new file mode 100644
index 000000000..1d5c854c6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/SN74177.sch
@@ -0,0 +1,716 @@
+EESchema Schematic File Version 2
+LIBS:SN74177-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74177-cache
+EELAYER 25 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nand U6
+U 1 1 6849445D
+P 9050 2800
+F 0 "U6" H 9050 2800 60 0000 C CNN
+F 1 "d_nand" H 9100 2900 60 0000 C CNN
+F 2 "" H 9050 2800 60 0000 C CNN
+F 3 "" H 9050 2800 60 0000 C CNN
+ 1 9050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U7
+U 1 1 6849452A
+P 9050 4350
+F 0 "U7" H 9050 4350 60 0000 C CNN
+F 1 "d_nand" H 9100 4450 60 0000 C CNN
+F 2 "" H 9050 4350 60 0000 C CNN
+F 3 "" H 9050 4350 60 0000 C CNN
+ 1 9050 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U8
+U 1 1 68494579
+P 9100 5900
+F 0 "U8" H 9100 5900 60 0000 C CNN
+F 1 "d_nand" H 9150 6000 60 0000 C CNN
+F 2 "" H 9100 5900 60 0000 C CNN
+F 3 "" H 9100 5900 60 0000 C CNN
+ 1 9100 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U9
+U 1 1 684945BE
+P 9150 7600
+F 0 "U9" H 9150 7600 60 0000 C CNN
+F 1 "d_nand" H 9200 7700 60 0000 C CNN
+F 2 "" H 9150 7600 60 0000 C CNN
+F 3 "" H 9150 7600 60 0000 C CNN
+ 1 9150 7600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U2
+U 1 1 6849849D
+P 4150 2400
+F 0 "U2" H 4150 2350 60 0000 C CNN
+F 1 "d_buffer" H 4150 2450 60 0000 C CNN
+F 2 "" H 4150 2400 60 0000 C CNN
+F 3 "" H 4150 2400 60 0000 C CNN
+ 1 4150 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U3
+U 1 1 6849882C
+P 4700 1750
+F 0 "U3" H 4700 1750 60 0000 C CNN
+F 1 "d_nand" H 4750 1850 60 0000 C CNN
+F 2 "" H 4700 1750 60 0000 C CNN
+F 3 "" H 4700 1750 60 0000 C CNN
+ 1 4700 1750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7500 1700 10650 1700
+Wire Wire Line
+ 10650 1700 10650 1750
+Wire Wire Line
+ 7600 3150 10650 3150
+Wire Wire Line
+ 10650 3150 10650 3350
+Wire Wire Line
+ 7600 4550 10650 4550
+Wire Wire Line
+ 10650 4550 10650 4700
+Wire Wire Line
+ 7600 6050 10650 6050
+Wire Wire Line
+ 10650 6050 10650 6250
+Wire Wire Line
+ 9550 5850 10650 5850
+Wire Wire Line
+ 10650 7550 9600 7550
+Wire Wire Line
+ 10650 7350 10650 7550
+Wire Wire Line
+ 9500 4300 10100 4300
+Wire Wire Line
+ 10100 4300 10100 4450
+Wire Wire Line
+ 10100 4450 10650 4450
+Wire Wire Line
+ 9500 2750 9500 3050
+Wire Wire Line
+ 9500 3050 10650 3050
+Wire Wire Line
+ 8600 2700 8100 2700
+Wire Wire Line
+ 8100 2700 8100 1700
+Connection ~ 8100 1700
+Wire Wire Line
+ 6400 1650 5950 1650
+Wire Wire Line
+ 5950 1650 5950 7600
+Wire Wire Line
+ 5950 4550 6400 4550
+Connection ~ 5950 3150
+Wire Wire Line
+ 5950 6050 6400 6050
+Connection ~ 5950 4550
+Wire Wire Line
+ 5950 7600 8700 7600
+Connection ~ 5950 6050
+Wire Wire Line
+ 7850 6050 7850 7500
+Wire Wire Line
+ 7850 7500 8700 7500
+Connection ~ 7850 6050
+Wire Wire Line
+ 5950 5750 7950 5750
+Wire Wire Line
+ 7950 5750 7950 5900
+Wire Wire Line
+ 7950 5900 8650 5900
+Connection ~ 5950 5750
+Wire Wire Line
+ 8650 5800 8100 5800
+Wire Wire Line
+ 8100 5800 8100 4550
+Connection ~ 8100 4550
+Wire Wire Line
+ 5950 4250 8100 4250
+Wire Wire Line
+ 8100 4250 8100 4350
+Wire Wire Line
+ 8100 4350 8600 4350
+Connection ~ 5950 4250
+Wire Wire Line
+ 8600 4250 8250 4250
+Wire Wire Line
+ 8250 4250 8250 3150
+Connection ~ 8250 3150
+Wire Wire Line
+ 8600 2800 6900 2800
+Wire Wire Line
+ 6900 2800 6900 2550
+Wire Wire Line
+ 6900 2550 5950 2550
+Connection ~ 5950 2550
+Wire Wire Line
+ 6400 1850 5550 1850
+Wire Wire Line
+ 5550 1850 5550 6200
+Wire Wire Line
+ 5550 3300 6400 3300
+Wire Wire Line
+ 5550 4700 6450 4700
+Connection ~ 5550 3300
+Wire Wire Line
+ 5550 6200 6400 6200
+Connection ~ 5550 4700
+Wire Wire Line
+ 6400 1550 5650 1550
+Wire Wire Line
+ 5550 2400 4800 2400
+Connection ~ 5550 2400
+Wire Wire Line
+ 3450 2400 3650 2400
+Wire Wire Line
+ 3550 2400 3550 1750
+Wire Wire Line
+ 3550 1750 4250 1750
+Connection ~ 3550 2400
+Wire Wire Line
+ 4250 1650 3350 1650
+Wire Wire Line
+ 5150 1700 5150 2050
+Wire Wire Line
+ 5150 2050 5950 2050
+Connection ~ 5950 2050
+Wire Wire Line
+ 5300 3000 6500 3000
+Wire Wire Line
+ 5350 4400 6550 4400
+Wire Wire Line
+ 5400 5900 6500 5900
+Wire Wire Line
+ 10100 4150 10100 3700
+Wire Wire Line
+ 10100 3700 7750 3700
+Wire Wire Line
+ 11100 3500 11800 3500
+Wire Wire Line
+ 11050 2100 11850 2100
+Wire Wire Line
+ 11650 3500 11650 4500
+Wire Wire Line
+ 11650 4500 9750 4500
+Wire Wire Line
+ 9750 4500 9750 5550
+Wire Wire Line
+ 9750 5550 10100 5550
+Connection ~ 11650 3500
+Wire Wire Line
+ 11100 4900 11800 4900
+Wire Wire Line
+ 11650 4900 11650 6000
+Wire Wire Line
+ 11650 6000 9650 6000
+Wire Wire Line
+ 9650 6000 9650 7050
+Wire Wire Line
+ 9650 7050 10100 7050
+Connection ~ 11650 4900
+Wire Wire Line
+ 11050 6400 11950 6400
+Text Label 5650 1550 0 60 ~ 0
+4
+Text Label 3350 1650 0 60 ~ 0
+1
+Text Label 3450 2400 0 60 ~ 0
+13
+Text Label 7450 2150 0 60 ~ 0
+8
+Text Label 5300 3000 0 60 ~ 0
+10
+Text Label 7750 3700 0 60 ~ 0
+6
+Text Label 5350 4400 0 60 ~ 0
+3
+Text Label 5400 5900 0 60 ~ 0
+11
+Text Label 11850 2100 0 60 ~ 0
+5
+Text Label 11800 3500 0 60 ~ 0
+9
+Text Label 11800 4900 0 60 ~ 0
+2
+Text Label 11950 6400 0 60 ~ 0
+12
+NoConn ~ 11000 2250
+$Comp
+L PORT U1
+U 3 1 6849FC73
+P 5100 4400
+F 0 "U1" H 5150 4500 30 0000 C CNN
+F 1 "PORT" H 5100 4400 30 0000 C CNN
+F 2 "" H 5100 4400 60 0000 C CNN
+F 3 "" H 5100 4400 60 0000 C CNN
+ 3 5100 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6849FCA6
+P 3100 1650
+F 0 "U1" H 3150 1750 30 0000 C CNN
+F 1 "PORT" H 3100 1650 30 0000 C CNN
+F 2 "" H 3100 1650 60 0000 C CNN
+F 3 "" H 3100 1650 60 0000 C CNN
+ 1 3100 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6849FCDB
+P 12050 4900
+F 0 "U1" H 12100 5000 30 0000 C CNN
+F 1 "PORT" H 12050 4900 30 0000 C CNN
+F 2 "" H 12050 4900 60 0000 C CNN
+F 3 "" H 12050 4900 60 0000 C CNN
+ 2 12050 4900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6849FD18
+P 5400 1550
+F 0 "U1" H 5450 1650 30 0000 C CNN
+F 1 "PORT" H 5400 1550 30 0000 C CNN
+F 2 "" H 5400 1550 60 0000 C CNN
+F 3 "" H 5400 1550 60 0000 C CNN
+ 4 5400 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6849FD51
+P 12100 2100
+F 0 "U1" H 12150 2200 30 0000 C CNN
+F 1 "PORT" H 12100 2100 30 0000 C CNN
+F 2 "" H 12100 2100 60 0000 C CNN
+F 3 "" H 12100 2100 60 0000 C CNN
+ 5 12100 2100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6849FD94
+P 7500 3700
+F 0 "U1" H 7550 3800 30 0000 C CNN
+F 1 "PORT" H 7500 3700 30 0000 C CNN
+F 2 "" H 7500 3700 60 0000 C CNN
+F 3 "" H 7500 3700 60 0000 C CNN
+ 6 7500 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6849FDD1
+P 3900 4200
+F 0 "U1" H 3950 4300 30 0000 C CNN
+F 1 "PORT" H 3900 4200 30 0000 C CNN
+F 2 "" H 3900 4200 60 0000 C CNN
+F 3 "" H 3900 4200 60 0000 C CNN
+ 7 3900 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6849FE10
+P 7200 2150
+F 0 "U1" H 7250 2250 30 0000 C CNN
+F 1 "PORT" H 7200 2150 30 0000 C CNN
+F 2 "" H 7200 2150 60 0000 C CNN
+F 3 "" H 7200 2150 60 0000 C CNN
+ 8 7200 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6849FE53
+P 12050 3500
+F 0 "U1" H 12100 3600 30 0000 C CNN
+F 1 "PORT" H 12050 3500 30 0000 C CNN
+F 2 "" H 12050 3500 60 0000 C CNN
+F 3 "" H 12050 3500 60 0000 C CNN
+ 9 12050 3500
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6849FE96
+P 5050 3000
+F 0 "U1" H 5100 3100 30 0000 C CNN
+F 1 "PORT" H 5050 3000 30 0000 C CNN
+F 2 "" H 5050 3000 60 0000 C CNN
+F 3 "" H 5050 3000 60 0000 C CNN
+ 10 5050 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6849FEDB
+P 5150 5900
+F 0 "U1" H 5200 6000 30 0000 C CNN
+F 1 "PORT" H 5150 5900 30 0000 C CNN
+F 2 "" H 5150 5900 60 0000 C CNN
+F 3 "" H 5150 5900 60 0000 C CNN
+ 11 5150 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6849FF48
+P 12200 6400
+F 0 "U1" H 12250 6500 30 0000 C CNN
+F 1 "PORT" H 12200 6400 30 0000 C CNN
+F 2 "" H 12200 6400 60 0000 C CNN
+F 3 "" H 12200 6400 60 0000 C CNN
+ 12 12200 6400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6849FF91
+P 3200 2400
+F 0 "U1" H 3250 2500 30 0000 C CNN
+F 1 "PORT" H 3200 2400 30 0000 C CNN
+F 2 "" H 3200 2400 60 0000 C CNN
+F 3 "" H 3200 2400 60 0000 C CNN
+ 13 3200 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6849FFDC
+P 3900 4450
+F 0 "U1" H 3950 4550 30 0000 C CNN
+F 1 "PORT" H 3900 4450 30 0000 C CNN
+F 2 "" H 3900 4450 60 0000 C CNN
+F 3 "" H 3900 4450 60 0000 C CNN
+ 14 3900 4450
+ 1 0 0 -1
+$EndComp
+NoConn ~ 4150 4450
+NoConn ~ 4150 4200
+$Comp
+L d_and U4
+U 1 1 684AB3EF
+P 6850 1650
+F 0 "U4" H 6850 1650 60 0000 C CNN
+F 1 "d_and" H 6900 1750 60 0000 C CNN
+F 2 "" H 6850 1650 60 0000 C CNN
+F 3 "" H 6850 1650 60 0000 C CNN
+ 1 6850 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U16
+U 1 1 684AB4DB
+P 7200 1950
+F 0 "U16" H 7200 1950 60 0000 C CNN
+F 1 "d_nand" H 7250 2050 60 0000 C CNN
+F 2 "" H 7200 1950 60 0000 C CNN
+F 3 "" H 7200 1950 60 0000 C CNN
+ 1 7200 1950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7300 1600 7300 1750
+Wire Wire Line
+ 7300 1750 6600 1750
+Wire Wire Line
+ 6600 1750 6600 1850
+Wire Wire Line
+ 6600 1850 6750 1850
+Wire Wire Line
+ 6400 1850 6400 1950
+Wire Wire Line
+ 6400 1950 6750 1950
+Wire Wire Line
+ 7650 1900 7650 1800
+Wire Wire Line
+ 7650 1800 7500 1800
+Wire Wire Line
+ 7500 1800 7500 1700
+$Comp
+L d_and U5
+U 1 1 684AC28B
+P 6950 3100
+F 0 "U5" H 6950 3100 60 0000 C CNN
+F 1 "d_and" H 7000 3200 60 0000 C CNN
+F 2 "" H 6950 3100 60 0000 C CNN
+F 3 "" H 6950 3100 60 0000 C CNN
+ 1 6950 3100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5950 3150 6150 3150
+Wire Wire Line
+ 6150 3150 6150 3100
+Wire Wire Line
+ 6150 3100 6500 3100
+$Comp
+L d_nand U17
+U 1 1 684AC80D
+P 7250 3450
+F 0 "U17" H 7250 3450 60 0000 C CNN
+F 1 "d_nand" H 7300 3550 60 0000 C CNN
+F 2 "" H 7250 3450 60 0000 C CNN
+F 3 "" H 7250 3450 60 0000 C CNN
+ 1 7250 3450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6400 3300 6400 3450
+Wire Wire Line
+ 6400 3450 6800 3450
+Wire Wire Line
+ 7400 3050 7400 3250
+Wire Wire Line
+ 7400 3250 6600 3250
+Wire Wire Line
+ 6600 3250 6600 3350
+Wire Wire Line
+ 6600 3350 6800 3350
+Wire Wire Line
+ 7600 3150 7600 3300
+Wire Wire Line
+ 7600 3300 7700 3300
+Wire Wire Line
+ 7700 3300 7700 3400
+$Comp
+L d_and U15
+U 1 1 684AD635
+P 7000 4500
+F 0 "U15" H 7000 4500 60 0000 C CNN
+F 1 "d_and" H 7050 4600 60 0000 C CNN
+F 2 "" H 7000 4500 60 0000 C CNN
+F 3 "" H 7000 4500 60 0000 C CNN
+ 1 7000 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U19
+U 1 1 684AD63B
+P 7300 4850
+F 0 "U19" H 7300 4850 60 0000 C CNN
+F 1 "d_nand" H 7350 4950 60 0000 C CNN
+F 2 "" H 7300 4850 60 0000 C CNN
+F 3 "" H 7300 4850 60 0000 C CNN
+ 1 7300 4850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6450 4850 6850 4850
+Wire Wire Line
+ 7450 4650 6650 4650
+Wire Wire Line
+ 6650 4750 6850 4750
+Wire Wire Line
+ 6400 4550 6400 4500
+Wire Wire Line
+ 6400 4500 6550 4500
+Wire Wire Line
+ 7450 4450 7450 4650
+Wire Wire Line
+ 6650 4650 6650 4750
+Wire Wire Line
+ 6450 4700 6450 4850
+Wire Wire Line
+ 7600 4550 7600 4650
+Wire Wire Line
+ 7600 4650 7750 4650
+Wire Wire Line
+ 7750 4650 7750 4800
+$Comp
+L d_and U14
+U 1 1 684AEDCD
+P 6950 6000
+F 0 "U14" H 6950 6000 60 0000 C CNN
+F 1 "d_and" H 7000 6100 60 0000 C CNN
+F 2 "" H 6950 6000 60 0000 C CNN
+F 3 "" H 6950 6000 60 0000 C CNN
+ 1 6950 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U18
+U 1 1 684AEDD3
+P 7250 6350
+F 0 "U18" H 7250 6350 60 0000 C CNN
+F 1 "d_nand" H 7300 6450 60 0000 C CNN
+F 2 "" H 7250 6350 60 0000 C CNN
+F 3 "" H 7250 6350 60 0000 C CNN
+ 1 7250 6350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7400 6150 6600 6150
+Wire Wire Line
+ 7400 5950 7400 6150
+Wire Wire Line
+ 6400 6050 6400 6000
+Wire Wire Line
+ 6400 6000 6500 6000
+Wire Wire Line
+ 6600 6150 6600 6250
+Wire Wire Line
+ 6600 6250 6800 6250
+Wire Wire Line
+ 6400 6200 6400 6350
+Wire Wire Line
+ 6400 6350 6800 6350
+Wire Wire Line
+ 7700 6300 7700 6150
+Wire Wire Line
+ 7700 6150 7600 6150
+Wire Wire Line
+ 7600 6150 7600 6050
+Wire Wire Line
+ 11100 3500 11100 3700
+Wire Wire Line
+ 10100 4150 10200 4150
+Wire Wire Line
+ 10200 4150 10200 3950
+Wire Wire Line
+ 10100 5550 10100 5300
+Wire Wire Line
+ 11100 4900 11100 5050
+Wire Wire Line
+ 10100 7050 10100 6850
+Wire Wire Line
+ 11050 6400 11050 6600
+$Comp
+L tff_1 X?
+U 1 1 687343EE
+P 10650 2150
+F 0 "X?" H 10150 1550 60 0000 C CNN
+F 1 "tff_1" H 10150 1650 60 0000 C CNN
+F 2 "" H 10150 1550 60 0001 C CNN
+F 3 "" H 10150 1550 60 0001 C CNN
+ 1 10650 2150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10650 3050 10650 2850
+NoConn ~ 10200 2100
+NoConn ~ 11050 2350
+Wire Wire Line
+ 7450 2150 9800 2150
+Wire Wire Line
+ 9800 2150 9800 2350
+Wire Wire Line
+ 9800 2350 10200 2350
+$Comp
+L tff_1 X?
+U 1 1 68735EDB
+P 10650 6650
+F 0 "X?" H 10150 6050 60 0000 C CNN
+F 1 "tff_1" H 10150 6150 60 0000 C CNN
+F 2 "" H 10150 6050 60 0001 C CNN
+F 3 "" H 10150 6050 60 0001 C CNN
+ 1 10650 6650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10100 6850 10200 6850
+NoConn ~ 11050 6850
+NoConn ~ 10200 6600
+$Comp
+L tff_1 X?
+U 1 1 6873690C
+P 10650 5100
+F 0 "X?" H 10150 4500 60 0000 C CNN
+F 1 "tff_1" H 10150 4600 60 0000 C CNN
+F 2 "" H 10150 4500 60 0001 C CNN
+F 3 "" H 10150 4500 60 0001 C CNN
+ 1 10650 5100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10650 5850 10650 5800
+Wire Wire Line
+ 11100 5050 11050 5050
+Wire Wire Line
+ 10100 5300 10200 5300
+NoConn ~ 11050 5300
+NoConn ~ 10200 5050
+$Comp
+L tff_1 X?
+U 1 1 687373FE
+P 10650 3750
+F 0 "X?" H 10150 3150 60 0000 C CNN
+F 1 "tff_1" H 10150 3250 60 0000 C CNN
+F 2 "" H 10150 3150 60 0001 C CNN
+F 3 "" H 10150 3150 60 0001 C CNN
+ 1 10650 3750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 11100 3700 11050 3700
+NoConn ~ 11050 3950
+NoConn ~ 10200 3700
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74177/SN74177.sub b/library/SubcircuitLibrary/SN74177/SN74177.sub
new file mode 100644
index 000000000..a20eabc56
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/SN74177.sub
@@ -0,0 +1,67 @@
+* Subcircuit SN74177
+.subckt SN74177 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 /11 /12 /13 ?
+* d:\fossee\esim\library\subcircuitlibrary\sn74177\sn74177.cir
+.include tff_1.sub
+* u6 net-_u16-pad3_ net-_u14-pad2_ net-_u6-pad3_ d_nand
+* u7 net-_u17-pad3_ net-_u14-pad2_ net-_u7-pad3_ d_nand
+* u8 net-_u19-pad3_ net-_u14-pad2_ net-_u8-pad3_ d_nand
+* u9 net-_u18-pad3_ net-_u14-pad2_ net-_u9-pad3_ d_nand
+* u2 /13 net-_u16-pad2_ d_buffer
+* u3 /1 /13 net-_u14-pad2_ d_nand
+* u4 /4 net-_u14-pad2_ net-_u16-pad1_ d_and
+* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_nand
+* u5 /10 net-_u14-pad2_ net-_u17-pad1_ d_and
+* u17 net-_u17-pad1_ net-_u16-pad2_ net-_u17-pad3_ d_nand
+* u15 /3 net-_u14-pad2_ net-_u15-pad3_ d_and
+* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand
+* u14 /11 net-_u14-pad2_ net-_u14-pad3_ d_and
+* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand
+x1 ? /8 net-_u6-pad3_ ? /5 net-_u16-pad3_ tff_1
+x4 ? /2 net-_u9-pad3_ ? /12 net-_u18-pad3_ tff_1
+x3 ? /9 net-_u8-pad3_ ? /2 net-_u19-pad3_ tff_1
+x2 ? /6 net-_u7-pad3_ ? /9 net-_u17-pad3_ tff_1
+a1 [net-_u16-pad3_ net-_u14-pad2_ ] net-_u6-pad3_ u6
+a2 [net-_u17-pad3_ net-_u14-pad2_ ] net-_u7-pad3_ u7
+a3 [net-_u19-pad3_ net-_u14-pad2_ ] net-_u8-pad3_ u8
+a4 [net-_u18-pad3_ net-_u14-pad2_ ] net-_u9-pad3_ u9
+a5 /13 net-_u16-pad2_ u2
+a6 [/1 /13 ] net-_u14-pad2_ u3
+a7 [/4 net-_u14-pad2_ ] net-_u16-pad1_ u4
+a8 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16
+a9 [/10 net-_u14-pad2_ ] net-_u17-pad1_ u5
+a10 [net-_u17-pad1_ net-_u16-pad2_ ] net-_u17-pad3_ u17
+a11 [/3 net-_u14-pad2_ ] net-_u15-pad3_ u15
+a12 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19
+a13 [/11 net-_u14-pad2_ ] net-_u14-pad3_ u14
+a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74177
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74177/SN74177_Previous_Values.xml b/library/SubcircuitLibrary/SN74177/SN74177_Previous_Values.xml
new file mode 100644
index 000000000..3b8f93288
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/SN74177_Previous_Values.xml
@@ -0,0 +1 @@
+d_tffd_tffd_tffd_tffd_nandd_nandd_nandd_nandd_bufferd_nandd_andd_nandd_andd_nandd_andd_nandd_andd_nandD:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74177/analysis b/library/SubcircuitLibrary/SN74177/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74177/tff-cache.lib b/library/SubcircuitLibrary/SN74177/tff-cache.lib
new file mode 100644
index 000000000..c07ae5124
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/tff-cache.lib
@@ -0,0 +1,78 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74177/tff_1-cache.lib b/library/SubcircuitLibrary/SN74177/tff_1-cache.lib
new file mode 100644
index 000000000..c07ae5124
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/tff_1-cache.lib
@@ -0,0 +1,78 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74177/tff_1.cir b/library/SubcircuitLibrary/SN74177/tff_1.cir
new file mode 100644
index 000000000..5a146818a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/tff_1.cir
@@ -0,0 +1,19 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1\tff_1.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 12:05:50
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and
+U3 Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U3-Pad3_ d_and
+U4 Net-_U1-Pad3_ Net-_U2-Pad4_ Net-_U4-Pad3_ d_nand
+U5 Net-_U2-Pad5_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_nand
+U6 Net-_U2-Pad6_ Net-_U4-Pad3_ Net-_U6-Pad3_ d_and
+U7 Net-_U5-Pad3_ Net-_U2-Pad3_ Net-_U7-Pad3_ d_and
+U8 Net-_U6-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ d_nand
+U9 Net-_U2-Pad5_ Net-_U7-Pad3_ Net-_U2-Pad4_ d_nand
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74177/tff_1.cir.out b/library/SubcircuitLibrary/SN74177/tff_1.cir.out
new file mode 100644
index 000000000..eb1d38f67
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/tff_1.cir.out
@@ -0,0 +1,44 @@
+* d:\fossee\esim\library\subcircuitlibrary\tff_1\tff_1.cir
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and
+* u3 net-_u1-pad2_ net-_u1-pad1_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad3_ net-_u2-pad4_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad5_ net-_u3-pad3_ net-_u5-pad3_ d_nand
+* u6 net-_u2-pad6_ net-_u4-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u5-pad3_ net-_u2-pad3_ net-_u7-pad3_ d_and
+* u8 net-_u6-pad3_ net-_u2-pad4_ net-_u2-pad5_ d_nand
+* u9 net-_u2-pad5_ net-_u7-pad3_ net-_u2-pad4_ d_nand
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad3_ net-_u2-pad4_ ] net-_u4-pad3_ u4
+a4 [net-_u2-pad5_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a5 [net-_u2-pad6_ net-_u4-pad3_ ] net-_u6-pad3_ u6
+a6 [net-_u5-pad3_ net-_u2-pad3_ ] net-_u7-pad3_ u7
+a7 [net-_u6-pad3_ net-_u2-pad4_ ] net-_u2-pad5_ u8
+a8 [net-_u2-pad5_ net-_u7-pad3_ ] net-_u2-pad4_ u9
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74177/tff_1.pro b/library/SubcircuitLibrary/SN74177/tff_1.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/tff_1.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74177/tff_1.sch b/library/SubcircuitLibrary/SN74177/tff_1.sch
new file mode 100644
index 000000000..467a8221e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/tff_1.sch
@@ -0,0 +1,299 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:tff_1-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U1
+U 1 1 68510BDF
+P 3350 2450
+F 0 "U1" H 3350 2450 60 0000 C CNN
+F 1 "d_and" H 3400 2550 60 0000 C CNN
+F 2 "" H 3350 2450 60 0000 C CNN
+F 3 "" H 3350 2450 60 0000 C CNN
+ 1 3350 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 68510C68
+P 3400 3750
+F 0 "U3" H 3400 3750 60 0000 C CNN
+F 1 "d_and" H 3450 3850 60 0000 C CNN
+F 2 "" H 3400 3750 60 0000 C CNN
+F 3 "" H 3400 3750 60 0000 C CNN
+ 1 3400 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 68510CCF
+P 5300 2450
+F 0 "U4" H 5300 2450 60 0000 C CNN
+F 1 "d_nand" H 5350 2550 60 0000 C CNN
+F 2 "" H 5300 2450 60 0000 C CNN
+F 3 "" H 5300 2450 60 0000 C CNN
+ 1 5300 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U5
+U 1 1 68510D24
+P 5350 3700
+F 0 "U5" H 5350 3700 60 0000 C CNN
+F 1 "d_nand" H 5400 3800 60 0000 C CNN
+F 2 "" H 5350 3700 60 0000 C CNN
+F 3 "" H 5350 3700 60 0000 C CNN
+ 1 5350 3700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3800 2400 4600 2400
+Wire Wire Line
+ 4600 2400 4600 2350
+Wire Wire Line
+ 4600 2350 4850 2350
+Wire Wire Line
+ 3850 3700 4900 3700
+$Comp
+L d_and U6
+U 1 1 685111F3
+P 6600 2400
+F 0 "U6" H 6600 2400 60 0000 C CNN
+F 1 "d_and" H 6650 2500 60 0000 C CNN
+F 2 "" H 6600 2400 60 0000 C CNN
+F 3 "" H 6600 2400 60 0000 C CNN
+ 1 6600 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U7
+U 1 1 685111F9
+P 6650 3700
+F 0 "U7" H 6650 3700 60 0000 C CNN
+F 1 "d_and" H 6700 3800 60 0000 C CNN
+F 2 "" H 6650 3700 60 0000 C CNN
+F 3 "" H 6650 3700 60 0000 C CNN
+ 1 6650 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U8
+U 1 1 685111FF
+P 8550 2400
+F 0 "U8" H 8550 2400 60 0000 C CNN
+F 1 "d_nand" H 8600 2500 60 0000 C CNN
+F 2 "" H 8550 2400 60 0000 C CNN
+F 3 "" H 8550 2400 60 0000 C CNN
+ 1 8550 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U9
+U 1 1 68511205
+P 8600 3650
+F 0 "U9" H 8600 3650 60 0000 C CNN
+F 1 "d_nand" H 8650 3750 60 0000 C CNN
+F 2 "" H 8600 3650 60 0000 C CNN
+F 3 "" H 8600 3650 60 0000 C CNN
+ 1 8600 3650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7050 2350 7850 2350
+Wire Wire Line
+ 7850 2350 7850 2300
+Wire Wire Line
+ 7850 2300 8100 2300
+Wire Wire Line
+ 7100 3650 8150 3650
+Wire Wire Line
+ 5800 3650 5900 3650
+Wire Wire Line
+ 5900 3650 5900 3600
+Wire Wire Line
+ 5900 3600 6200 3600
+Wire Wire Line
+ 5750 2400 6150 2400
+Wire Wire Line
+ 6150 2300 5850 2300
+Wire Wire Line
+ 5850 2300 5850 1900
+Wire Wire Line
+ 6200 3700 6050 3700
+Wire Wire Line
+ 6050 3700 6050 4250
+Wire Wire Line
+ 9000 2350 9700 2350
+Wire Wire Line
+ 9050 3600 9900 3600
+Wire Wire Line
+ 9450 2350 9450 3050
+Wire Wire Line
+ 9450 3050 7750 3050
+Wire Wire Line
+ 7750 3050 7750 3550
+Wire Wire Line
+ 7750 3550 8150 3550
+Connection ~ 9450 2350
+Wire Wire Line
+ 9350 3600 9350 2700
+Wire Wire Line
+ 9350 2700 8000 2700
+Wire Wire Line
+ 8000 2700 8000 2400
+Wire Wire Line
+ 8000 2400 8100 2400
+Connection ~ 9350 3600
+Wire Wire Line
+ 7750 3200 4550 3200
+Wire Wire Line
+ 4550 3200 4550 3600
+Wire Wire Line
+ 4550 3600 4900 3600
+Connection ~ 7750 3200
+Wire Wire Line
+ 8000 2600 4700 2600
+Wire Wire Line
+ 4700 2600 4700 2450
+Wire Wire Line
+ 4700 2450 4850 2450
+Connection ~ 8000 2600
+Wire Wire Line
+ 2900 2450 2550 2450
+Wire Wire Line
+ 2550 2450 2550 3650
+Wire Wire Line
+ 2550 3650 2950 3650
+Wire Wire Line
+ 2550 3050 2050 3050
+Wire Wire Line
+ 2050 3050 2050 4200
+Connection ~ 2550 3050
+Wire Wire Line
+ 2900 2350 1800 2350
+Wire Wire Line
+ 1800 2350 1800 2300
+Wire Wire Line
+ 2150 2350 2150 3750
+Wire Wire Line
+ 2150 3750 2950 3750
+Connection ~ 2150 2350
+$Comp
+L PORT U2
+U 1 1 68512107
+P 1550 2300
+F 0 "U2" H 1600 2400 30 0000 C CNN
+F 1 "PORT" H 1550 2300 30 0000 C CNN
+F 2 "" H 1550 2300 60 0000 C CNN
+F 3 "" H 1550 2300 60 0000 C CNN
+ 1 1550 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 4 1 6851219B
+P 9900 3850
+F 0 "U2" H 9950 3950 30 0000 C CNN
+F 1 "PORT" H 9900 3850 30 0000 C CNN
+F 2 "" H 9900 3850 60 0000 C CNN
+F 3 "" H 9900 3850 60 0000 C CNN
+ 4 9900 3850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 5 1 685121CC
+P 9700 2600
+F 0 "U2" H 9750 2700 30 0000 C CNN
+F 1 "PORT" H 9700 2600 30 0000 C CNN
+F 2 "" H 9700 2600 60 0000 C CNN
+F 3 "" H 9700 2600 60 0000 C CNN
+ 5 9700 2600
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 6 1 68512212
+P 5600 1900
+F 0 "U2" H 5650 2000 30 0000 C CNN
+F 1 "PORT" H 5600 1900 30 0000 C CNN
+F 2 "" H 5600 1900 60 0000 C CNN
+F 3 "" H 5600 1900 60 0000 C CNN
+ 6 5600 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 2 1 68512275
+P 1800 4200
+F 0 "U2" H 1850 4300 30 0000 C CNN
+F 1 "PORT" H 1800 4200 30 0000 C CNN
+F 2 "" H 1800 4200 60 0000 C CNN
+F 3 "" H 1800 4200 60 0000 C CNN
+ 2 1800 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 3 1 685122C6
+P 5800 4250
+F 0 "U2" H 5850 4350 30 0000 C CNN
+F 1 "PORT" H 5800 4250 30 0000 C CNN
+F 2 "" H 5800 4250 60 0000 C CNN
+F 3 "" H 5800 4250 60 0000 C CNN
+ 3 5800 4250
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74177/tff_1.sub b/library/SubcircuitLibrary/SN74177/tff_1.sub
new file mode 100644
index 000000000..c7f567e0c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/tff_1.sub
@@ -0,0 +1,38 @@
+* Subcircuit tff_1
+.subckt tff_1 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_
+* d:\fossee\esim\library\subcircuitlibrary\tff_1\tff_1.cir
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and
+* u3 net-_u1-pad2_ net-_u1-pad1_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad3_ net-_u2-pad4_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad5_ net-_u3-pad3_ net-_u5-pad3_ d_nand
+* u6 net-_u2-pad6_ net-_u4-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u5-pad3_ net-_u2-pad3_ net-_u7-pad3_ d_and
+* u8 net-_u6-pad3_ net-_u2-pad4_ net-_u2-pad5_ d_nand
+* u9 net-_u2-pad5_ net-_u7-pad3_ net-_u2-pad4_ d_nand
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad3_ net-_u2-pad4_ ] net-_u4-pad3_ u4
+a4 [net-_u2-pad5_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a5 [net-_u2-pad6_ net-_u4-pad3_ ] net-_u6-pad3_ u6
+a6 [net-_u5-pad3_ net-_u2-pad3_ ] net-_u7-pad3_ u7
+a7 [net-_u6-pad3_ net-_u2-pad4_ ] net-_u2-pad5_ u8
+a8 [net-_u2-pad5_ net-_u7-pad3_ ] net-_u2-pad4_ u9
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends tff_1
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74177/tff_1_Previous_Values.xml b/library/SubcircuitLibrary/SN74177/tff_1_Previous_Values.xml
new file mode 100644
index 000000000..ab6605eb4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/tff_1_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_nandd_nandd_andd_andd_nandd_nand
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74177/tff_Previous_Values.xml b/library/SubcircuitLibrary/SN74177/tff_Previous_Values.xml
new file mode 100644
index 000000000..f6a8820fd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74177/tff_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_andd_nandd_andd_nandd_andd_nandd_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74182/3_and-cache.lib b/library/SubcircuitLibrary/SN74182/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74182/3_and.cir b/library/SubcircuitLibrary/SN74182/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74182/3_and.cir.out b/library/SubcircuitLibrary/SN74182/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74182/3_and.pro b/library/SubcircuitLibrary/SN74182/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74182/3_and.sch b/library/SubcircuitLibrary/SN74182/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74182/3_and.sub b/library/SubcircuitLibrary/SN74182/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74182/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74182/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74182/4_OR-cache.lib b/library/SubcircuitLibrary/SN74182/4_OR-cache.lib
new file mode 100644
index 000000000..155f5e601
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74182/4_OR.cir b/library/SubcircuitLibrary/SN74182/4_OR.cir
new file mode 100644
index 000000000..b338b7b5f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74182/4_OR.cir.out b/library/SubcircuitLibrary/SN74182/4_OR.cir.out
new file mode 100644
index 000000000..adb6b01be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74182/4_OR.pro b/library/SubcircuitLibrary/SN74182/4_OR.pro
new file mode 100644
index 000000000..881563ebd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74182/4_OR.sch b/library/SubcircuitLibrary/SN74182/4_OR.sch
new file mode 100644
index 000000000..118968656
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74182/4_OR.sub b/library/SubcircuitLibrary/SN74182/4_OR.sub
new file mode 100644
index 000000000..d1fd3a241
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74182/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74182/4_OR_Previous_Values.xml
new file mode 100644
index 000000000..0683d9eb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74182/4_and-cache.lib b/library/SubcircuitLibrary/SN74182/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74182/4_and-rescue.lib b/library/SubcircuitLibrary/SN74182/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74182/4_and.cir b/library/SubcircuitLibrary/SN74182/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74182/4_and.cir.out b/library/SubcircuitLibrary/SN74182/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74182/4_and.pro b/library/SubcircuitLibrary/SN74182/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/SN74182/4_and.sch b/library/SubcircuitLibrary/SN74182/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74182/4_and.sub b/library/SubcircuitLibrary/SN74182/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74182/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74182/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74182/SN74182.cir b/library/SubcircuitLibrary/SN74182/SN74182.cir
new file mode 100644
index 000000000..d02a06377
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/SN74182.cir
@@ -0,0 +1,33 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74182\SN74182.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/07/25 14:25:56
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad6_ Net-_U1-Pad15_ Net-_U1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad7_ 4_OR
+X6 Net-_U1-Pad5_ Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_X10-Pad1_ 4_and
+X2 Net-_U1-Pad15_ Net-_U1-Pad5_ Net-_U1-Pad14_ Net-_X10-Pad3_ 3_and
+X7 Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_X10-Pad2_ 4_and
+U3 Net-_U1-Pad6_ Net-_U1-Pad5_ Net-_U3-Pad3_ d_and
+X10 Net-_X10-Pad1_ Net-_X10-Pad2_ Net-_X10-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad10_ 4_OR
+X8 Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_X11-Pad1_ 4_and
+X3 Net-_U1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_X11-Pad3_ 3_and
+X9 Net-_U1-Pad4_ Net-_U1-Pad14_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_X11-Pad2_ 4_and
+U4 Net-_U1-Pad15_ Net-_U1-Pad14_ Net-_U4-Pad3_ d_and
+X11 Net-_X11-Pad1_ Net-_X11-Pad2_ Net-_X11-Pad3_ Net-_U4-Pad3_ Net-_U11-Pad1_ 4_OR
+U11 Net-_U11-Pad1_ Net-_U1-Pad9_ d_inverter
+X4 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_U8-Pad1_ 3_and
+X5 Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U8-Pad2_ 3_and
+U5 Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U10-Pad2_ d_and
+U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U10-Pad1_ d_or
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or
+U12 Net-_U10-Pad3_ Net-_U1-Pad11_ d_inverter
+U2 Net-_U1-Pad13_ Net-_U2-Pad2_ d_inverter
+U6 Net-_U1-Pad3_ Net-_U2-Pad2_ Net-_U6-Pad3_ d_and
+U7 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U7-Pad3_ d_and
+U9 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U1-Pad12_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74182/SN74182.cir.out b/library/SubcircuitLibrary/SN74182/SN74182.cir.out
new file mode 100644
index 000000000..e9263b114
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/SN74182.cir.out
@@ -0,0 +1,70 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74182\sn74182.cir
+
+.include 4_and.sub
+.include 4_OR.sub
+.include 3_and.sub
+x1 net-_u1-pad6_ net-_u1-pad15_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad7_ 4_OR
+x6 net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_x10-pad1_ 4_and
+x2 net-_u1-pad15_ net-_u1-pad5_ net-_u1-pad14_ net-_x10-pad3_ 3_and
+x7 net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad1_ net-_x10-pad2_ 4_and
+* u3 net-_u1-pad6_ net-_u1-pad5_ net-_u3-pad3_ d_and
+x10 net-_x10-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_u3-pad3_ net-_u1-pad10_ 4_OR
+x8 net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_u2-pad2_ net-_x11-pad1_ 4_and
+x3 net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad1_ net-_x11-pad3_ 3_and
+x9 net-_u1-pad4_ net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_x11-pad2_ 4_and
+* u4 net-_u1-pad15_ net-_u1-pad14_ net-_u4-pad3_ d_and
+x11 net-_x11-pad1_ net-_x11-pad2_ net-_x11-pad3_ net-_u4-pad3_ net-_u11-pad1_ 4_OR
+* u11 net-_u11-pad1_ net-_u1-pad9_ d_inverter
+x4 net-_u1-pad1_ net-_u1-pad3_ net-_u2-pad2_ net-_u8-pad1_ 3_and
+x5 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad3_ net-_u8-pad2_ 3_and
+* u5 net-_u1-pad2_ net-_u1-pad1_ net-_u10-pad2_ d_and
+* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u10-pad1_ d_or
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
+* u12 net-_u10-pad3_ net-_u1-pad11_ d_inverter
+* u2 net-_u1-pad13_ net-_u2-pad2_ d_inverter
+* u6 net-_u1-pad3_ net-_u2-pad2_ net-_u6-pad3_ d_and
+* u7 net-_u1-pad4_ net-_u1-pad3_ net-_u7-pad3_ d_and
+* u9 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad12_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
+a1 [net-_u1-pad6_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a2 [net-_u1-pad15_ net-_u1-pad14_ ] net-_u4-pad3_ u4
+a3 net-_u11-pad1_ net-_u1-pad9_ u11
+a4 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u10-pad2_ u5
+a5 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u10-pad1_ u8
+a6 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a7 net-_u10-pad3_ net-_u1-pad11_ u12
+a8 net-_u1-pad13_ net-_u2-pad2_ u2
+a9 [net-_u1-pad3_ net-_u2-pad2_ ] net-_u6-pad3_ u6
+a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u7-pad3_ u7
+a11 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad12_ u9
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74182/SN74182.pro b/library/SubcircuitLibrary/SN74182/SN74182.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/SN74182.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74182/SN74182.sch b/library/SubcircuitLibrary/SN74182/SN74182.sch
new file mode 100644
index 000000000..3fc2a37a9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/SN74182.sch
@@ -0,0 +1,706 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:Lookahead_carry-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4_OR X1
+U 1 1 6836CAB2
+P 5100 850
+F 0 "X1" H 5250 750 60 0000 C CNN
+F 1 "4_OR" H 5250 950 60 0000 C CNN
+F 2 "" H 5100 850 60 0000 C CNN
+F 3 "" H 5100 850 60 0000 C CNN
+ 1 5100 850
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X6
+U 1 1 6836CB1D
+P 5950 1300
+F 0 "X6" H 6000 1250 60 0000 C CNN
+F 1 "4_and" H 6050 1400 60 0000 C CNN
+F 2 "" H 5950 1300 60 0000 C CNN
+F 3 "" H 5950 1300 60 0000 C CNN
+ 1 5950 1300
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 6836CBE8
+P 5900 2350
+F 0 "X2" H 6000 2300 60 0000 C CNN
+F 1 "3_and" H 6050 2500 60 0000 C CNN
+F 2 "" H 5900 2350 60 0000 C CNN
+F 3 "" H 5900 2350 60 0000 C CNN
+ 1 5900 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X7
+U 1 1 6836CC5D
+P 5950 1800
+F 0 "X7" H 6000 1750 60 0000 C CNN
+F 1 "4_and" H 6050 1900 60 0000 C CNN
+F 2 "" H 5950 1800 60 0000 C CNN
+F 3 "" H 5950 1800 60 0000 C CNN
+ 1 5950 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 6836CC8F
+P 6000 2700
+F 0 "U3" H 6000 2700 60 0000 C CNN
+F 1 "d_and" H 6050 2800 60 0000 C CNN
+F 2 "" H 6000 2700 60 0000 C CNN
+F 3 "" H 6000 2700 60 0000 C CNN
+ 1 6000 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X10
+U 1 1 6836CCE1
+P 7450 1800
+F 0 "X10" H 7600 1700 60 0000 C CNN
+F 1 "4_OR" H 7600 1900 60 0000 C CNN
+F 2 "" H 7450 1800 60 0000 C CNN
+F 3 "" H 7450 1800 60 0000 C CNN
+ 1 7450 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X8
+U 1 1 6836D08B
+P 5950 3100
+F 0 "X8" H 6000 3050 60 0000 C CNN
+F 1 "4_and" H 6050 3200 60 0000 C CNN
+F 2 "" H 5950 3100 60 0000 C CNN
+F 3 "" H 5950 3100 60 0000 C CNN
+ 1 5950 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X3
+U 1 1 6836D091
+P 5900 4150
+F 0 "X3" H 6000 4100 60 0000 C CNN
+F 1 "3_and" H 6050 4300 60 0000 C CNN
+F 2 "" H 5900 4150 60 0000 C CNN
+F 3 "" H 5900 4150 60 0000 C CNN
+ 1 5900 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X9
+U 1 1 6836D097
+P 5950 3600
+F 0 "X9" H 6000 3550 60 0000 C CNN
+F 1 "4_and" H 6050 3700 60 0000 C CNN
+F 2 "" H 5950 3600 60 0000 C CNN
+F 3 "" H 5950 3600 60 0000 C CNN
+ 1 5950 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 6836D09D
+P 6000 4500
+F 0 "U4" H 6000 4500 60 0000 C CNN
+F 1 "d_and" H 6050 4600 60 0000 C CNN
+F 2 "" H 6000 4500 60 0000 C CNN
+F 3 "" H 6000 4500 60 0000 C CNN
+ 1 6000 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X11
+U 1 1 6836D0A3
+P 7450 3600
+F 0 "X11" H 7600 3500 60 0000 C CNN
+F 1 "4_OR" H 7600 3700 60 0000 C CNN
+F 2 "" H 7450 3600 60 0000 C CNN
+F 3 "" H 7450 3600 60 0000 C CNN
+ 1 7450 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U11
+U 1 1 6836D362
+P 8500 3600
+F 0 "U11" H 8500 3500 60 0000 C CNN
+F 1 "d_inverter" H 8500 3750 60 0000 C CNN
+F 2 "" H 8550 3550 60 0000 C CNN
+F 3 "" H 8550 3550 60 0000 C CNN
+ 1 8500 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X4
+U 1 1 6836D3B1
+P 5900 4950
+F 0 "X4" H 6000 4900 60 0000 C CNN
+F 1 "3_and" H 6050 5100 60 0000 C CNN
+F 2 "" H 5900 4950 60 0000 C CNN
+F 3 "" H 5900 4950 60 0000 C CNN
+ 1 5900 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X5
+U 1 1 6836D42F
+P 5900 5350
+F 0 "X5" H 6000 5300 60 0000 C CNN
+F 1 "3_and" H 6050 5500 60 0000 C CNN
+F 2 "" H 5900 5350 60 0000 C CNN
+F 3 "" H 5900 5350 60 0000 C CNN
+ 1 5900 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 6836D475
+P 6000 5700
+F 0 "U5" H 6000 5700 60 0000 C CNN
+F 1 "d_and" H 6050 5800 60 0000 C CNN
+F 2 "" H 6000 5700 60 0000 C CNN
+F 3 "" H 6000 5700 60 0000 C CNN
+ 1 6000 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U8
+U 1 1 6836D4DF
+P 7150 5150
+F 0 "U8" H 7150 5150 60 0000 C CNN
+F 1 "d_or" H 7150 5250 60 0000 C CNN
+F 2 "" H 7150 5150 60 0000 C CNN
+F 3 "" H 7150 5150 60 0000 C CNN
+ 1 7150 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U10
+U 1 1 6836D53E
+P 8050 5300
+F 0 "U10" H 8050 5300 60 0000 C CNN
+F 1 "d_or" H 8050 5400 60 0000 C CNN
+F 2 "" H 8050 5300 60 0000 C CNN
+F 3 "" H 8050 5300 60 0000 C CNN
+ 1 8050 5300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 6836D5B9
+P 8950 5250
+F 0 "U12" H 8950 5150 60 0000 C CNN
+F 1 "d_inverter" H 8950 5400 60 0000 C CNN
+F 2 "" H 9000 5200 60 0000 C CNN
+F 3 "" H 9000 5200 60 0000 C CNN
+ 1 8950 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 6836D63B
+P 4250 6950
+F 0 "U2" H 4250 6850 60 0000 C CNN
+F 1 "d_inverter" H 4250 7100 60 0000 C CNN
+F 2 "" H 4300 6900 60 0000 C CNN
+F 3 "" H 4300 6900 60 0000 C CNN
+ 1 4250 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 6836D6CC
+P 6000 6050
+F 0 "U6" H 6000 6050 60 0000 C CNN
+F 1 "d_and" H 6050 6150 60 0000 C CNN
+F 2 "" H 6000 6050 60 0000 C CNN
+F 3 "" H 6000 6050 60 0000 C CNN
+ 1 6000 6050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U7
+U 1 1 6836D726
+P 6000 6400
+F 0 "U7" H 6000 6400 60 0000 C CNN
+F 1 "d_and" H 6050 6500 60 0000 C CNN
+F 2 "" H 6000 6400 60 0000 C CNN
+F 3 "" H 6000 6400 60 0000 C CNN
+ 1 6000 6400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U9
+U 1 1 6836D796
+P 7250 6250
+F 0 "U9" H 7250 6250 60 0000 C CNN
+F 1 "d_nor" H 7300 6350 60 0000 C CNN
+F 2 "" H 7250 6250 60 0000 C CNN
+F 3 "" H 7250 6250 60 0000 C CNN
+ 1 7250 6250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6450 1300 6450 1650
+Wire Wire Line
+ 6450 1650 7100 1650
+Wire Wire Line
+ 6500 1800 6500 1750
+Wire Wire Line
+ 6400 2300 6400 1850
+Wire Wire Line
+ 6400 1850 7100 1850
+Wire Wire Line
+ 6450 2650 6550 2650
+Wire Wire Line
+ 6550 2650 6550 1950
+Wire Wire Line
+ 6550 1950 7100 1950
+Wire Wire Line
+ 6450 3100 6450 3450
+Wire Wire Line
+ 6450 3450 7100 3450
+Wire Wire Line
+ 6450 3600 6450 3550
+Wire Wire Line
+ 6450 3550 7100 3550
+Wire Wire Line
+ 6400 4100 6400 3650
+Wire Wire Line
+ 6400 3650 7100 3650
+Wire Wire Line
+ 6450 4450 6450 3750
+Wire Wire Line
+ 6450 3750 7100 3750
+Wire Wire Line
+ 8000 3600 8200 3600
+Wire Wire Line
+ 6400 4900 6400 5050
+Wire Wire Line
+ 6400 5050 6700 5050
+Wire Wire Line
+ 6400 5300 6400 5150
+Wire Wire Line
+ 6400 5150 6700 5150
+Wire Wire Line
+ 6450 5650 6450 5300
+Wire Wire Line
+ 7600 5100 7600 5200
+Wire Wire Line
+ 8500 5250 8650 5250
+Wire Wire Line
+ 6450 6000 6450 6150
+Wire Wire Line
+ 6450 6150 6800 6150
+Wire Wire Line
+ 6450 6350 6450 6250
+Wire Wire Line
+ 6450 6250 6800 6250
+$Comp
+L PORT U1
+U 1 1 6837324D
+P 2550 5850
+F 0 "U1" H 2600 5950 30 0000 C CNN
+F 1 "PORT" H 2550 5850 30 0000 C CNN
+F 2 "" H 2550 5850 60 0000 C CNN
+F 3 "" H 2550 5850 60 0000 C CNN
+ 1 2550 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68373298
+P 2550 5700
+F 0 "U1" H 2600 5800 30 0000 C CNN
+F 1 "PORT" H 2550 5700 30 0000 C CNN
+F 2 "" H 2550 5700 60 0000 C CNN
+F 3 "" H 2550 5700 60 0000 C CNN
+ 2 2550 5700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2800 2650 5550 2650
+Wire Wire Line
+ 5550 2650 5550 2700
+Wire Wire Line
+ 2800 2450 2800 2600
+Wire Wire Line
+ 2800 2600 5550 2600
+Wire Wire Line
+ 4000 2600 4000 700
+Wire Wire Line
+ 4000 700 4750 700
+Connection ~ 4000 2600
+$Comp
+L PORT U1
+U 10 1 68375C57
+P 9500 1800
+F 0 "U1" H 9550 1900 30 0000 C CNN
+F 1 "PORT" H 9500 1800 30 0000 C CNN
+F 2 "" H 9500 1800 60 0000 C CNN
+F 3 "" H 9500 1800 60 0000 C CNN
+ 10 9500 1800
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 5650 850 9250 850
+Wire Wire Line
+ 5400 1150 5400 2650
+Wire Wire Line
+ 5400 1150 5550 1150
+Connection ~ 5400 2650
+Wire Wire Line
+ 5400 1750 5550 1750
+Connection ~ 5400 1750
+Wire Wire Line
+ 5400 2300 5550 2300
+Connection ~ 5400 2300
+$Comp
+L PORT U1
+U 7 1 6837832B
+P 9500 850
+F 0 "U1" H 9550 950 30 0000 C CNN
+F 1 "PORT" H 9500 850 30 0000 C CNN
+F 2 "" H 9500 850 60 0000 C CNN
+F 3 "" H 9500 850 60 0000 C CNN
+ 7 9500 850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68378B12
+P 9500 5250
+F 0 "U1" H 9550 5350 30 0000 C CNN
+F 1 "PORT" H 9500 5250 30 0000 C CNN
+F 2 "" H 9500 5250 60 0000 C CNN
+F 3 "" H 9500 5250 60 0000 C CNN
+ 11 9500 5250
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 8000 1800 9250 1800
+$Comp
+L PORT U1
+U 12 1 6837A4A8
+P 9500 6200
+F 0 "U1" H 9550 6300 30 0000 C CNN
+F 1 "PORT" H 9500 6200 30 0000 C CNN
+F 2 "" H 9500 6200 60 0000 C CNN
+F 3 "" H 9500 6200 60 0000 C CNN
+ 12 9500 6200
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 6450 5300 7600 5300
+$Comp
+L PORT U1
+U 13 1 6837A6FA
+P 2650 6950
+F 0 "U1" H 2700 7050 30 0000 C CNN
+F 1 "PORT" H 2650 6950 30 0000 C CNN
+F 2 "" H 2650 6950 60 0000 C CNN
+F 3 "" H 2650 6950 60 0000 C CNN
+ 13 2650 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6837D04B
+P 2600 4500
+F 0 "U1" H 2650 4600 30 0000 C CNN
+F 1 "PORT" H 2600 4500 30 0000 C CNN
+F 2 "" H 2600 4500 60 0000 C CNN
+F 3 "" H 2600 4500 60 0000 C CNN
+ 14 2600 4500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7700 6200 9250 6200
+Wire Wire Line
+ 5400 6950 4550 6950
+Wire Wire Line
+ 5400 3250 5400 6950
+Wire Wire Line
+ 5400 6050 5550 6050
+Wire Wire Line
+ 5400 5000 5550 5000
+Connection ~ 5400 6050
+Wire Wire Line
+ 5400 3250 5550 3250
+Connection ~ 5400 5000
+$Comp
+L PORT U1
+U 9 1 6837E103
+P 9500 3600
+F 0 "U1" H 9550 3700 30 0000 C CNN
+F 1 "PORT" H 9500 3600 30 0000 C CNN
+F 2 "" H 9500 3600 60 0000 C CNN
+F 3 "" H 9500 3600 60 0000 C CNN
+ 9 9500 3600
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 2900 6950 3950 6950
+$Comp
+L PORT U1
+U 6 1 6837E252
+P 2550 2450
+F 0 "U1" H 2600 2550 30 0000 C CNN
+F 1 "PORT" H 2550 2450 30 0000 C CNN
+F 2 "" H 2550 2450 60 0000 C CNN
+F 3 "" H 2550 2450 60 0000 C CNN
+ 6 2550 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6837E2CB
+P 2550 2650
+F 0 "U1" H 2600 2750 30 0000 C CNN
+F 1 "PORT" H 2550 2650 30 0000 C CNN
+F 2 "" H 2550 2650 60 0000 C CNN
+F 3 "" H 2550 2650 60 0000 C CNN
+ 5 2550 2650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2800 6700 5350 6700
+Wire Wire Line
+ 5350 6700 5350 6400
+Wire Wire Line
+ 5350 6400 5550 6400
+Wire Wire Line
+ 2800 6500 5250 6500
+Wire Wire Line
+ 5250 6500 5250 6300
+Wire Wire Line
+ 5250 6300 5550 6300
+Wire Wire Line
+ 4800 1450 4800 6700
+Wire Wire Line
+ 4800 5950 5550 5950
+Connection ~ 4800 6700
+Wire Wire Line
+ 4800 5400 5550 5400
+Connection ~ 4800 5950
+Wire Wire Line
+ 4800 4900 5550 4900
+Connection ~ 4800 5400
+Wire Wire Line
+ 3300 1000 3300 6500
+Wire Wire Line
+ 3300 5200 5550 5200
+Connection ~ 3300 6500
+$Comp
+L PORT U1
+U 3 1 6837FEF1
+P 2550 6700
+F 0 "U1" H 2600 6800 30 0000 C CNN
+F 1 "PORT" H 2550 6700 30 0000 C CNN
+F 2 "" H 2550 6700 60 0000 C CNN
+F 3 "" H 2550 6700 60 0000 C CNN
+ 3 2550 6700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6837FFA2
+P 2550 6500
+F 0 "U1" H 2600 6600 30 0000 C CNN
+F 1 "PORT" H 2550 6500 30 0000 C CNN
+F 2 "" H 2550 6500 60 0000 C CNN
+F 3 "" H 2550 6500 60 0000 C CNN
+ 4 2550 6500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5200 5850 2800 5850
+Wire Wire Line
+ 5200 1350 5200 5850
+Wire Wire Line
+ 5200 5700 5550 5700
+Wire Wire Line
+ 2800 5650 5550 5650
+Wire Wire Line
+ 5550 5650 5550 5600
+Wire Wire Line
+ 5200 5300 5550 5300
+Connection ~ 5200 5700
+Wire Wire Line
+ 5200 4800 5550 4800
+Connection ~ 5200 5300
+Wire Wire Line
+ 3300 3450 5550 3450
+Connection ~ 3300 5200
+Wire Wire Line
+ 3300 1000 4750 1000
+Connection ~ 3300 3450
+Wire Wire Line
+ 2850 4500 5550 4500
+Wire Wire Line
+ 2850 4300 2850 4400
+Wire Wire Line
+ 2850 4400 5550 4400
+Wire Wire Line
+ 3450 900 3450 5650
+Wire Wire Line
+ 3450 4000 5550 4000
+Connection ~ 3450 5650
+Wire Wire Line
+ 3450 1650 5550 1650
+Connection ~ 3450 4000
+Wire Wire Line
+ 3450 900 4750 900
+Connection ~ 3450 1650
+Wire Wire Line
+ 3600 800 3600 4400
+Wire Wire Line
+ 3600 2200 5550 2200
+Connection ~ 3600 4400
+Wire Wire Line
+ 3600 800 4750 800
+Connection ~ 3600 2200
+Wire Wire Line
+ 5250 1250 5250 4500
+Wire Wire Line
+ 5250 4100 5550 4100
+Connection ~ 5250 4500
+Wire Wire Line
+ 5200 4200 5550 4200
+Connection ~ 5200 4800
+Wire Wire Line
+ 5200 3650 5550 3650
+Connection ~ 5200 4200
+Wire Wire Line
+ 5200 3050 5550 3050
+Connection ~ 5200 3650
+Wire Wire Line
+ 5200 1950 5550 1950
+Connection ~ 5200 3050
+Wire Wire Line
+ 5200 1350 5550 1350
+Connection ~ 5200 1950
+Wire Wire Line
+ 5250 3550 5550 3550
+Connection ~ 5250 4100
+Wire Wire Line
+ 5250 2950 5550 2950
+Connection ~ 5250 3550
+Wire Wire Line
+ 5250 2400 5550 2400
+Connection ~ 5250 2950
+Wire Wire Line
+ 5250 1850 5550 1850
+Connection ~ 5250 2400
+Wire Wire Line
+ 5250 1250 5550 1250
+Connection ~ 5250 1850
+Wire Wire Line
+ 4800 3750 5550 3750
+Connection ~ 4800 4900
+Wire Wire Line
+ 4800 3150 5550 3150
+Connection ~ 4800 3750
+Wire Wire Line
+ 4800 1450 5550 1450
+Connection ~ 4800 3150
+Wire Wire Line
+ 2800 5650 2800 5700
+$Comp
+L PORT U1
+U 8 1 683AA1B3
+P 10500 2350
+F 0 "U1" H 10550 2450 30 0000 C CNN
+F 1 "PORT" H 10500 2350 30 0000 C CNN
+F 2 "" H 10500 2350 60 0000 C CNN
+F 3 "" H 10500 2350 60 0000 C CNN
+ 8 10500 2350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8800 3600 9250 3600
+$Comp
+L PORT U1
+U 16 1 683BD0F1
+P 10500 2700
+F 0 "U1" H 10550 2800 30 0000 C CNN
+F 1 "PORT" H 10500 2700 30 0000 C CNN
+F 2 "" H 10500 2700 60 0000 C CNN
+F 3 "" H 10500 2700 60 0000 C CNN
+ 16 10500 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 683BD1F3
+P 2600 4300
+F 0 "U1" H 2650 4400 30 0000 C CNN
+F 1 "PORT" H 2600 4300 30 0000 C CNN
+F 2 "" H 2600 4300 60 0000 C CNN
+F 3 "" H 2600 4300 60 0000 C CNN
+ 15 2600 4300
+ 1 0 0 -1
+$EndComp
+NoConn ~ 10750 2350
+NoConn ~ 10750 2700
+Wire Wire Line
+ 6500 1750 7100 1750
+Wire Wire Line
+ 6450 1800 6500 1800
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74182/SN74182.sub b/library/SubcircuitLibrary/SN74182/SN74182.sub
new file mode 100644
index 000000000..705a68536
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/SN74182.sub
@@ -0,0 +1,64 @@
+* Subcircuit SN74182
+.subckt SN74182 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ?
+* c:\fossee\esim\library\subcircuitlibrary\sn74182\sn74182.cir
+.include 4_and.sub
+.include 4_OR.sub
+.include 3_and.sub
+x1 net-_u1-pad6_ net-_u1-pad15_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad7_ 4_OR
+x6 net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_x10-pad1_ 4_and
+x2 net-_u1-pad15_ net-_u1-pad5_ net-_u1-pad14_ net-_x10-pad3_ 3_and
+x7 net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad1_ net-_x10-pad2_ 4_and
+* u3 net-_u1-pad6_ net-_u1-pad5_ net-_u3-pad3_ d_and
+x10 net-_x10-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_u3-pad3_ net-_u1-pad10_ 4_OR
+x8 net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_u2-pad2_ net-_x11-pad1_ 4_and
+x3 net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad1_ net-_x11-pad3_ 3_and
+x9 net-_u1-pad4_ net-_u1-pad14_ net-_u1-pad1_ net-_u1-pad3_ net-_x11-pad2_ 4_and
+* u4 net-_u1-pad15_ net-_u1-pad14_ net-_u4-pad3_ d_and
+x11 net-_x11-pad1_ net-_x11-pad2_ net-_x11-pad3_ net-_u4-pad3_ net-_u11-pad1_ 4_OR
+* u11 net-_u11-pad1_ net-_u1-pad9_ d_inverter
+x4 net-_u1-pad1_ net-_u1-pad3_ net-_u2-pad2_ net-_u8-pad1_ 3_and
+x5 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad3_ net-_u8-pad2_ 3_and
+* u5 net-_u1-pad2_ net-_u1-pad1_ net-_u10-pad2_ d_and
+* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u10-pad1_ d_or
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
+* u12 net-_u10-pad3_ net-_u1-pad11_ d_inverter
+* u2 net-_u1-pad13_ net-_u2-pad2_ d_inverter
+* u6 net-_u1-pad3_ net-_u2-pad2_ net-_u6-pad3_ d_and
+* u7 net-_u1-pad4_ net-_u1-pad3_ net-_u7-pad3_ d_and
+* u9 net-_u6-pad3_ net-_u7-pad3_ net-_u1-pad12_ d_nor
+a1 [net-_u1-pad6_ net-_u1-pad5_ ] net-_u3-pad3_ u3
+a2 [net-_u1-pad15_ net-_u1-pad14_ ] net-_u4-pad3_ u4
+a3 net-_u11-pad1_ net-_u1-pad9_ u11
+a4 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u10-pad2_ u5
+a5 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u10-pad1_ u8
+a6 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a7 net-_u10-pad3_ net-_u1-pad11_ u12
+a8 net-_u1-pad13_ net-_u2-pad2_ u2
+a9 [net-_u1-pad3_ net-_u2-pad2_ ] net-_u6-pad3_ u6
+a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u7-pad3_ u7
+a11 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u1-pad12_ u9
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74182
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74182/SN74182_Previous_Values.xml b/library/SubcircuitLibrary/SN74182/SN74182_Previous_Values.xml
new file mode 100644
index 000000000..233e79324
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/SN74182_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_inverterd_andd_ord_ord_inverterd_inverterd_andd_andd_norC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74182/analysis b/library/SubcircuitLibrary/SN74182/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74182/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74199/3_and-cache.lib b/library/SubcircuitLibrary/SN74199/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74199/3_and.cir b/library/SubcircuitLibrary/SN74199/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74199/3_and.cir.out b/library/SubcircuitLibrary/SN74199/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74199/3_and.pro b/library/SubcircuitLibrary/SN74199/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74199/3_and.sch b/library/SubcircuitLibrary/SN74199/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74199/3_and.sub b/library/SubcircuitLibrary/SN74199/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74199/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74199/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74199/SN74199-cache.lib b/library/SubcircuitLibrary/SN74199/SN74199-cache.lib
new file mode 100644
index 000000000..51aa3e9b1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/SN74199-cache.lib
@@ -0,0 +1,150 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_srff
+#
+DEF d_srff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_srff" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 600 550 -600 -600 0 1 0 N
+X S 1 -800 400 200 R 50 50 1 1 I
+X R 2 -800 -450 200 R 50 50 1 1 I
+X Clk 3 -800 0 200 R 50 50 1 1 I C
+X Set 4 0 750 200 D 50 50 1 1 I
+X Reset 5 0 -800 200 U 50 50 1 1 I
+X Out 6 800 400 200 L 50 50 1 1 O
+X Nout 7 800 -450 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74199/SN74199.cir b/library/SubcircuitLibrary/SN74199/SN74199.cir
new file mode 100644
index 000000000..b022f897a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/SN74199.cir
@@ -0,0 +1,59 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74199\SN74199.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 22:57:27
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 /13 /11 Net-_U3-Pad3_ d_nor
+U5 Net-_U1-Pad2_ /3 Net-_U5-Pad3_ d_and
+U7 Net-_U6-Pad3_ Net-_U7-Pad2_ Net-_U36-Pad1_ d_nor
+U6 Net-_U6-Pad1_ Net-_U5-Pad3_ Net-_U6-Pad3_ d_or
+U2 Net-_U1-Pad2_ ? d_inverter
+U1 /23 Net-_U1-Pad2_ d_inverter
+X1 /1 Net-_U10-Pad2_ /4 Net-_U7-Pad2_ 3_and
+U8 /4 Net-_U10-Pad2_ Net-_U22-Pad1_ d_and
+U9 Net-_U1-Pad2_ /5 Net-_U22-Pad2_ d_and
+U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_nor
+U10 /6 Net-_U10-Pad2_ Net-_U10-Pad3_ d_and
+U11 Net-_U1-Pad2_ /7 Net-_U11-Pad3_ d_and
+U23 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U23-Pad3_ d_nor
+U12 /8 Net-_U10-Pad2_ Net-_U12-Pad3_ d_and
+U13 Net-_U1-Pad2_ /9 Net-_U13-Pad3_ d_and
+U14 /10 Net-_U10-Pad2_ Net-_U14-Pad3_ d_and
+U15 Net-_U1-Pad2_ /16 Net-_U15-Pad3_ d_and
+U16 /15 Net-_U10-Pad2_ Net-_U16-Pad3_ d_and
+U17 Net-_U1-Pad2_ /18 Net-_U17-Pad3_ d_and
+U18 /17 Net-_U10-Pad2_ Net-_U18-Pad3_ d_and
+U19 Net-_U1-Pad2_ /20 Net-_U19-Pad3_ d_and
+U20 /19 Net-_U10-Pad2_ Net-_U20-Pad3_ d_and
+U21 Net-_U1-Pad2_ /22 Net-_U21-Pad3_ d_and
+U24 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U24-Pad3_ d_nor
+U25 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U25-Pad3_ d_nor
+U26 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U26-Pad3_ d_nor
+U27 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U27-Pad3_ d_nor
+U28 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U28-Pad3_ d_nor
+U29 Net-_U22-Pad3_ Net-_U29-Pad2_ d_inverter
+U36 Net-_U36-Pad1_ ? d_inverter
+U30 Net-_U23-Pad3_ Net-_U30-Pad2_ d_inverter
+U31 Net-_U24-Pad3_ Net-_U31-Pad2_ d_inverter
+U32 Net-_U25-Pad3_ Net-_U32-Pad2_ d_inverter
+U33 Net-_U26-Pad3_ Net-_U33-Pad2_ d_inverter
+U34 Net-_U27-Pad3_ Net-_U34-Pad2_ d_inverter
+U42 ? Net-_U36-Pad1_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /4 Net-_U42-Pad7_ d_srff
+U39 Net-_U29-Pad2_ Net-_U22-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /6 ? d_srff
+U46 Net-_U30-Pad2_ Net-_U23-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /8 ? d_srff
+U38 Net-_U31-Pad2_ Net-_U24-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /10 ? d_srff
+U40 Net-_U33-Pad2_ Net-_U26-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /17 ? d_srff
+U44 Net-_U32-Pad2_ Net-_U41-Pad2_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /15 ? d_srff
+U37 Net-_U35-Pad2_ Net-_U28-Pad3_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /21 ? d_srff
+U35 Net-_U28-Pad3_ Net-_U35-Pad2_ d_inverter
+X2 /2 Net-_U10-Pad2_ Net-_U42-Pad7_ Net-_U6-Pad1_ 3_and
+U41 Net-_U32-Pad2_ Net-_U41-Pad2_ d_inverter
+U45 Net-_U34-Pad2_ Net-_U43-Pad2_ Net-_U3-Pad3_ ? Net-_U37-Pad5_ /19 ? d_srff
+U43 Net-_U34-Pad2_ Net-_U43-Pad2_ d_inverter
+U47 /14 Net-_U37-Pad5_ d_inverter
+U4 /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 ? /13 /14 /15 /16 /17 /18 /19 /20 /21 /22 /23 ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74199/SN74199.cir.out b/library/SubcircuitLibrary/SN74199/SN74199.cir.out
new file mode 100644
index 000000000..0a11f23ea
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/SN74199.cir.out
@@ -0,0 +1,199 @@
+* d:\fossee\esim\library\subcircuitlibrary\sn74198\sn74198.cir
+
+.include 3_and.sub
+* u3 /13 /11 net-_u3-pad3_ d_nor
+* u5 net-_u1-pad2_ /3 net-_u5-pad3_ d_and
+* u7 net-_u6-pad3_ net-_u7-pad2_ net-_u36-pad1_ d_nor
+* u6 net-_u6-pad1_ net-_u5-pad3_ net-_u6-pad3_ d_or
+* u2 net-_u1-pad2_ ? d_inverter
+* u1 /23 net-_u1-pad2_ d_inverter
+x1 /1 net-_u10-pad2_ /4 net-_u7-pad2_ 3_and
+* u8 /4 net-_u10-pad2_ net-_u22-pad1_ d_and
+* u9 net-_u1-pad2_ /5 net-_u22-pad2_ d_and
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nor
+* u10 /6 net-_u10-pad2_ net-_u10-pad3_ d_and
+* u11 net-_u1-pad2_ /7 net-_u11-pad3_ d_and
+* u23 net-_u10-pad3_ net-_u11-pad3_ net-_u23-pad3_ d_nor
+* u12 /8 net-_u10-pad2_ net-_u12-pad3_ d_and
+* u13 net-_u1-pad2_ /9 net-_u13-pad3_ d_and
+* u14 /10 net-_u10-pad2_ net-_u14-pad3_ d_and
+* u15 net-_u1-pad2_ /16 net-_u15-pad3_ d_and
+* u16 /15 net-_u10-pad2_ net-_u16-pad3_ d_and
+* u17 net-_u1-pad2_ /18 net-_u17-pad3_ d_and
+* u18 /17 net-_u10-pad2_ net-_u18-pad3_ d_and
+* u19 net-_u1-pad2_ /20 net-_u19-pad3_ d_and
+* u20 /19 net-_u10-pad2_ net-_u20-pad3_ d_and
+* u21 net-_u1-pad2_ /22 net-_u21-pad3_ d_and
+* u24 net-_u12-pad3_ net-_u13-pad3_ net-_u24-pad3_ d_nor
+* u25 net-_u14-pad3_ net-_u15-pad3_ net-_u25-pad3_ d_nor
+* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_nor
+* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_nor
+* u28 net-_u20-pad3_ net-_u21-pad3_ net-_u28-pad3_ d_nor
+* u29 net-_u22-pad3_ net-_u29-pad2_ d_inverter
+* u36 net-_u36-pad1_ ? d_inverter
+* u30 net-_u23-pad3_ net-_u30-pad2_ d_inverter
+* u31 net-_u24-pad3_ net-_u31-pad2_ d_inverter
+* u32 net-_u25-pad3_ net-_u32-pad2_ d_inverter
+* u33 net-_u26-pad3_ net-_u33-pad2_ d_inverter
+* u34 net-_u27-pad3_ net-_u34-pad2_ d_inverter
+* u42 ? net-_u36-pad1_ net-_u3-pad3_ ? net-_u37-pad5_ /4 net-_u42-pad7_ d_srff
+* u39 net-_u29-pad2_ net-_u22-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /6 ? d_srff
+* u46 net-_u30-pad2_ net-_u23-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /8 ? d_srff
+* u38 net-_u31-pad2_ net-_u24-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /10 ? d_srff
+* u40 net-_u33-pad2_ net-_u26-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /17 ? d_srff
+* u44 net-_u32-pad2_ net-_u41-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /15 ? d_srff
+* u37 net-_u35-pad2_ net-_u28-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /21 ? d_srff
+* u35 net-_u28-pad3_ net-_u35-pad2_ d_inverter
+x2 /2 net-_u10-pad2_ net-_u42-pad7_ net-_u6-pad1_ 3_and
+* u41 net-_u32-pad2_ net-_u41-pad2_ d_inverter
+* u45 net-_u34-pad2_ net-_u43-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /19 ? d_srff
+* u43 net-_u34-pad2_ net-_u43-pad2_ d_inverter
+* u47 /14 net-_u37-pad5_ d_inverter
+* u4 /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 ? /13 /14 /15 /16 /17 /18 /19 /20 /21 /22 /23 ? port
+a1 [/13 /11 ] net-_u3-pad3_ u3
+a2 [net-_u1-pad2_ /3 ] net-_u5-pad3_ u5
+a3 [net-_u6-pad3_ net-_u7-pad2_ ] net-_u36-pad1_ u7
+a4 [net-_u6-pad1_ net-_u5-pad3_ ] net-_u6-pad3_ u6
+a5 net-_u1-pad2_ ? u2
+a6 /23 net-_u1-pad2_ u1
+a7 [/4 net-_u10-pad2_ ] net-_u22-pad1_ u8
+a8 [net-_u1-pad2_ /5 ] net-_u22-pad2_ u9
+a9 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a10 [/6 net-_u10-pad2_ ] net-_u10-pad3_ u10
+a11 [net-_u1-pad2_ /7 ] net-_u11-pad3_ u11
+a12 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u23-pad3_ u23
+a13 [/8 net-_u10-pad2_ ] net-_u12-pad3_ u12
+a14 [net-_u1-pad2_ /9 ] net-_u13-pad3_ u13
+a15 [/10 net-_u10-pad2_ ] net-_u14-pad3_ u14
+a16 [net-_u1-pad2_ /16 ] net-_u15-pad3_ u15
+a17 [/15 net-_u10-pad2_ ] net-_u16-pad3_ u16
+a18 [net-_u1-pad2_ /18 ] net-_u17-pad3_ u17
+a19 [/17 net-_u10-pad2_ ] net-_u18-pad3_ u18
+a20 [net-_u1-pad2_ /20 ] net-_u19-pad3_ u19
+a21 [/19 net-_u10-pad2_ ] net-_u20-pad3_ u20
+a22 [net-_u1-pad2_ /22 ] net-_u21-pad3_ u21
+a23 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u24-pad3_ u24
+a24 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u25-pad3_ u25
+a25 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26
+a26 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27
+a27 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u28-pad3_ u28
+a28 net-_u22-pad3_ net-_u29-pad2_ u29
+a29 net-_u36-pad1_ ? u36
+a30 net-_u23-pad3_ net-_u30-pad2_ u30
+a31 net-_u24-pad3_ net-_u31-pad2_ u31
+a32 net-_u25-pad3_ net-_u32-pad2_ u32
+a33 net-_u26-pad3_ net-_u33-pad2_ u33
+a34 net-_u27-pad3_ net-_u34-pad2_ u34
+a35 ? net-_u36-pad1_ net-_u3-pad3_ ? net-_u37-pad5_ /4 net-_u42-pad7_ u42
+a36 net-_u29-pad2_ net-_u22-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /6 ? u39
+a37 net-_u30-pad2_ net-_u23-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /8 ? u46
+a38 net-_u31-pad2_ net-_u24-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /10 ? u38
+a39 net-_u33-pad2_ net-_u26-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /17 ? u40
+a40 net-_u32-pad2_ net-_u41-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /15 ? u44
+a41 net-_u35-pad2_ net-_u28-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /21 ? u37
+a42 net-_u28-pad3_ net-_u35-pad2_ u35
+a43 net-_u32-pad2_ net-_u41-pad2_ u41
+a44 net-_u34-pad2_ net-_u43-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /19 ? u45
+a45 net-_u34-pad2_ net-_u43-pad2_ u43
+a46 /14 net-_u37-pad5_ u47
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u42 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u39 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u46 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u38 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u40 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u44 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u37 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u45 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74199/SN74199.pro b/library/SubcircuitLibrary/SN74199/SN74199.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/SN74199.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74199/SN74199.sch b/library/SubcircuitLibrary/SN74199/SN74199.sch
new file mode 100644
index 000000000..e680b193d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/SN74199.sch
@@ -0,0 +1,1400 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74199-cache
+EELAYER 25 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nor U3
+U 1 1 68346397
+P 3900 1500
+F 0 "U3" H 3900 1500 60 0000 C CNN
+F 1 "d_nor" H 3950 1600 60 0000 C CNN
+F 2 "" H 3900 1500 60 0000 C CNN
+F 3 "" H 3900 1500 60 0000 C CNN
+ 1 3900 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 683464C0
+P 4500 2450
+F 0 "U5" H 4500 2450 60 0000 C CNN
+F 1 "d_and" H 4550 2550 60 0000 C CNN
+F 2 "" H 4500 2450 60 0000 C CNN
+F 3 "" H 4500 2450 60 0000 C CNN
+ 1 4500 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 683464F9
+P 6800 2400
+F 0 "U7" H 6800 2400 60 0000 C CNN
+F 1 "d_nor" H 6850 2500 60 0000 C CNN
+F 2 "" H 6800 2400 60 0000 C CNN
+F 3 "" H 6800 2400 60 0000 C CNN
+ 1 6800 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U6
+U 1 1 68346560
+P 5650 2300
+F 0 "U6" H 5650 2300 60 0000 C CNN
+F 1 "d_or" H 5650 2400 60 0000 C CNN
+F 2 "" H 5650 2300 60 0000 C CNN
+F 3 "" H 5650 2300 60 0000 C CNN
+ 1 5650 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 683466ED
+P 3600 2100
+F 0 "U2" H 3600 2000 60 0000 C CNN
+F 1 "d_inverter" H 3600 2250 60 0000 C CNN
+F 2 "" H 3650 2050 60 0000 C CNN
+F 3 "" H 3650 2050 60 0000 C CNN
+ 1 3600 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U1
+U 1 1 6834680B
+P 2950 2100
+F 0 "U1" H 2950 2000 60 0000 C CNN
+F 1 "d_inverter" H 2950 2250 60 0000 C CNN
+F 2 "" H 3000 2050 60 0000 C CNN
+F 3 "" H 3000 2050 60 0000 C CNN
+ 1 2950 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 68346CB0
+P 4400 2800
+F 0 "X1" H 4500 2750 60 0000 C CNN
+F 1 "3_and" H 4550 2950 60 0000 C CNN
+F 2 "" H 4400 2800 60 0000 C CNN
+F 3 "" H 4400 2800 60 0000 C CNN
+ 1 4400 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U8
+U 1 1 68346DFB
+P 4500 3250
+F 0 "U8" H 4500 3250 60 0000 C CNN
+F 1 "d_and" H 4550 3350 60 0000 C CNN
+F 2 "" H 4500 3250 60 0000 C CNN
+F 3 "" H 4500 3250 60 0000 C CNN
+ 1 4500 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U9
+U 1 1 683472E7
+P 4500 3650
+F 0 "U9" H 4500 3650 60 0000 C CNN
+F 1 "d_and" H 4550 3750 60 0000 C CNN
+F 2 "" H 4500 3650 60 0000 C CNN
+F 3 "" H 4500 3650 60 0000 C CNN
+ 1 4500 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U22
+U 1 1 6834733A
+P 5650 3400
+F 0 "U22" H 5650 3400 60 0000 C CNN
+F 1 "d_nor" H 5700 3500 60 0000 C CNN
+F 2 "" H 5650 3400 60 0000 C CNN
+F 3 "" H 5650 3400 60 0000 C CNN
+ 1 5650 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U10
+U 1 1 68347CF2
+P 4500 4000
+F 0 "U10" H 4500 4000 60 0000 C CNN
+F 1 "d_and" H 4550 4100 60 0000 C CNN
+F 2 "" H 4500 4000 60 0000 C CNN
+F 3 "" H 4500 4000 60 0000 C CNN
+ 1 4500 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U11
+U 1 1 68347D65
+P 4500 4400
+F 0 "U11" H 4500 4400 60 0000 C CNN
+F 1 "d_and" H 4550 4500 60 0000 C CNN
+F 2 "" H 4500 4400 60 0000 C CNN
+F 3 "" H 4500 4400 60 0000 C CNN
+ 1 4500 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U23
+U 1 1 68348207
+P 5650 4150
+F 0 "U23" H 5650 4150 60 0000 C CNN
+F 1 "d_nor" H 5700 4250 60 0000 C CNN
+F 2 "" H 5650 4150 60 0000 C CNN
+F 3 "" H 5650 4150 60 0000 C CNN
+ 1 5650 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 6834C1B3
+P 4500 4800
+F 0 "U12" H 4500 4800 60 0000 C CNN
+F 1 "d_and" H 4550 4900 60 0000 C CNN
+F 2 "" H 4500 4800 60 0000 C CNN
+F 3 "" H 4500 4800 60 0000 C CNN
+ 1 4500 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 6834C1FC
+P 4500 5100
+F 0 "U13" H 4500 5100 60 0000 C CNN
+F 1 "d_and" H 4550 5200 60 0000 C CNN
+F 2 "" H 4500 5100 60 0000 C CNN
+F 3 "" H 4500 5100 60 0000 C CNN
+ 1 4500 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 6834C297
+P 4500 5500
+F 0 "U14" H 4500 5500 60 0000 C CNN
+F 1 "d_and" H 4550 5600 60 0000 C CNN
+F 2 "" H 4500 5500 60 0000 C CNN
+F 3 "" H 4500 5500 60 0000 C CNN
+ 1 4500 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U15
+U 1 1 6834C29D
+P 4500 5800
+F 0 "U15" H 4500 5800 60 0000 C CNN
+F 1 "d_and" H 4550 5900 60 0000 C CNN
+F 2 "" H 4500 5800 60 0000 C CNN
+F 3 "" H 4500 5800 60 0000 C CNN
+ 1 4500 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U16
+U 1 1 6834CD3B
+P 4500 6250
+F 0 "U16" H 4500 6250 60 0000 C CNN
+F 1 "d_and" H 4550 6350 60 0000 C CNN
+F 2 "" H 4500 6250 60 0000 C CNN
+F 3 "" H 4500 6250 60 0000 C CNN
+ 1 4500 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U17
+U 1 1 6834CD41
+P 4500 6550
+F 0 "U17" H 4500 6550 60 0000 C CNN
+F 1 "d_and" H 4550 6650 60 0000 C CNN
+F 2 "" H 4500 6550 60 0000 C CNN
+F 3 "" H 4500 6550 60 0000 C CNN
+ 1 4500 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U18
+U 1 1 6834CDB5
+P 4500 7050
+F 0 "U18" H 4500 7050 60 0000 C CNN
+F 1 "d_and" H 4550 7150 60 0000 C CNN
+F 2 "" H 4500 7050 60 0000 C CNN
+F 3 "" H 4500 7050 60 0000 C CNN
+ 1 4500 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U19
+U 1 1 6834CDBB
+P 4500 7350
+F 0 "U19" H 4500 7350 60 0000 C CNN
+F 1 "d_and" H 4550 7450 60 0000 C CNN
+F 2 "" H 4500 7350 60 0000 C CNN
+F 3 "" H 4500 7350 60 0000 C CNN
+ 1 4500 7350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U20
+U 1 1 6834CE63
+P 4550 7800
+F 0 "U20" H 4550 7800 60 0000 C CNN
+F 1 "d_and" H 4600 7900 60 0000 C CNN
+F 2 "" H 4550 7800 60 0000 C CNN
+F 3 "" H 4550 7800 60 0000 C CNN
+ 1 4550 7800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U21
+U 1 1 6834CE69
+P 4550 8100
+F 0 "U21" H 4550 8100 60 0000 C CNN
+F 1 "d_and" H 4600 8200 60 0000 C CNN
+F 2 "" H 4550 8100 60 0000 C CNN
+F 3 "" H 4550 8100 60 0000 C CNN
+ 1 4550 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U24
+U 1 1 6834D111
+P 5750 4950
+F 0 "U24" H 5750 4950 60 0000 C CNN
+F 1 "d_nor" H 5800 5050 60 0000 C CNN
+F 2 "" H 5750 4950 60 0000 C CNN
+F 3 "" H 5750 4950 60 0000 C CNN
+ 1 5750 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U25
+U 1 1 6834D1A4
+P 5800 5650
+F 0 "U25" H 5800 5650 60 0000 C CNN
+F 1 "d_nor" H 5850 5750 60 0000 C CNN
+F 2 "" H 5800 5650 60 0000 C CNN
+F 3 "" H 5800 5650 60 0000 C CNN
+ 1 5800 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U26
+U 1 1 6834D201
+P 5800 6400
+F 0 "U26" H 5800 6400 60 0000 C CNN
+F 1 "d_nor" H 5850 6500 60 0000 C CNN
+F 2 "" H 5800 6400 60 0000 C CNN
+F 3 "" H 5800 6400 60 0000 C CNN
+ 1 5800 6400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U27
+U 1 1 6834D26A
+P 5800 7200
+F 0 "U27" H 5800 7200 60 0000 C CNN
+F 1 "d_nor" H 5850 7300 60 0000 C CNN
+F 2 "" H 5800 7200 60 0000 C CNN
+F 3 "" H 5800 7200 60 0000 C CNN
+ 1 5800 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U28
+U 1 1 6834D2CD
+P 5800 7950
+F 0 "U28" H 5800 7950 60 0000 C CNN
+F 1 "d_nor" H 5850 8050 60 0000 C CNN
+F 2 "" H 5800 7950 60 0000 C CNN
+F 3 "" H 5800 7950 60 0000 C CNN
+ 1 5800 7950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U29
+U 1 1 68351927
+P 6500 3350
+F 0 "U29" H 6500 3250 60 0000 C CNN
+F 1 "d_inverter" H 6500 3500 60 0000 C CNN
+F 2 "" H 6550 3300 60 0000 C CNN
+F 3 "" H 6550 3300 60 0000 C CNN
+ 1 6500 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U36
+U 1 1 683535B3
+P 7650 2350
+F 0 "U36" H 7650 2250 60 0000 C CNN
+F 1 "d_inverter" H 7650 2500 60 0000 C CNN
+F 2 "" H 7700 2300 60 0000 C CNN
+F 3 "" H 7700 2300 60 0000 C CNN
+ 1 7650 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U30
+U 1 1 6835609F
+P 6500 4100
+F 0 "U30" H 6500 4000 60 0000 C CNN
+F 1 "d_inverter" H 6500 4250 60 0000 C CNN
+F 2 "" H 6550 4050 60 0000 C CNN
+F 3 "" H 6550 4050 60 0000 C CNN
+ 1 6500 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U31
+U 1 1 68356112
+P 6600 4900
+F 0 "U31" H 6600 4800 60 0000 C CNN
+F 1 "d_inverter" H 6600 5050 60 0000 C CNN
+F 2 "" H 6650 4850 60 0000 C CNN
+F 3 "" H 6650 4850 60 0000 C CNN
+ 1 6600 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U32
+U 1 1 6835617F
+P 6650 5600
+F 0 "U32" H 6650 5500 60 0000 C CNN
+F 1 "d_inverter" H 6650 5750 60 0000 C CNN
+F 2 "" H 6700 5550 60 0000 C CNN
+F 3 "" H 6700 5550 60 0000 C CNN
+ 1 6650 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U33
+U 1 1 68356204
+P 6650 6350
+F 0 "U33" H 6650 6250 60 0000 C CNN
+F 1 "d_inverter" H 6650 6500 60 0000 C CNN
+F 2 "" H 6700 6300 60 0000 C CNN
+F 3 "" H 6700 6300 60 0000 C CNN
+ 1 6650 6350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U34
+U 1 1 68356279
+P 6650 7150
+F 0 "U34" H 6650 7050 60 0000 C CNN
+F 1 "d_inverter" H 6650 7300 60 0000 C CNN
+F 2 "" H 6700 7100 60 0000 C CNN
+F 3 "" H 6700 7100 60 0000 C CNN
+ 1 6650 7150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_srff U42
+U 1 1 68357B65
+P 10550 2100
+F 0 "U42" H 10550 2100 60 0000 C CNN
+F 1 "d_srff" H 10600 2250 60 0000 C CNN
+F 2 "" H 10550 2100 60 0000 C CNN
+F 3 "" H 10550 2100 60 0000 C CNN
+ 1 10550 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_srff U39
+U 1 1 68358194
+P 8650 3250
+F 0 "U39" H 8650 3250 60 0000 C CNN
+F 1 "d_srff" H 8700 3400 60 0000 C CNN
+F 2 "" H 8650 3250 60 0000 C CNN
+F 3 "" H 8650 3250 60 0000 C CNN
+ 1 8650 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_srff U46
+U 1 1 6835823F
+P 12000 3400
+F 0 "U46" H 12000 3400 60 0000 C CNN
+F 1 "d_srff" H 12050 3550 60 0000 C CNN
+F 2 "" H 12000 3400 60 0000 C CNN
+F 3 "" H 12000 3400 60 0000 C CNN
+ 1 12000 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_srff U38
+U 1 1 68359666
+P 8500 4700
+F 0 "U38" H 8500 4700 60 0000 C CNN
+F 1 "d_srff" H 8550 4850 60 0000 C CNN
+F 2 "" H 8500 4700 60 0000 C CNN
+F 3 "" H 8500 4700 60 0000 C CNN
+ 1 8500 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_srff U40
+U 1 1 6835DD4B
+P 8650 6200
+F 0 "U40" H 8650 6200 60 0000 C CNN
+F 1 "d_srff" H 8700 6350 60 0000 C CNN
+F 2 "" H 8650 6200 60 0000 C CNN
+F 3 "" H 8650 6200 60 0000 C CNN
+ 1 8650 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_srff U44
+U 1 1 68359E63
+P 11650 5000
+F 0 "U44" H 11650 5000 60 0000 C CNN
+F 1 "d_srff" H 11700 5150 60 0000 C CNN
+F 2 "" H 11650 5000 60 0000 C CNN
+F 3 "" H 11650 5000 60 0000 C CNN
+ 1 11650 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_srff U37
+U 1 1 6835E89A
+P 7950 7600
+F 0 "U37" H 7950 7600 60 0000 C CNN
+F 1 "d_srff" H 8000 7750 60 0000 C CNN
+F 2 "" H 7950 7600 60 0000 C CNN
+F 3 "" H 7950 7600 60 0000 C CNN
+ 1 7950 7600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U35
+U 1 1 6835F4A2
+P 6650 7900
+F 0 "U35" H 6650 7800 60 0000 C CNN
+F 1 "d_inverter" H 6650 8050 60 0000 C CNN
+F 2 "" H 6700 7850 60 0000 C CNN
+F 3 "" H 6700 7850 60 0000 C CNN
+ 1 6650 7900
+ 1 0 0 -1
+$EndComp
+NoConn ~ 10550 1350
+NoConn ~ 8650 2500
+NoConn ~ 8500 3950
+NoConn ~ 11650 4250
+NoConn ~ 8650 5450
+NoConn ~ 7950 6850
+NoConn ~ 12000 2650
+$Comp
+L 3_and X2
+U 1 1 68393400
+P 4400 2150
+F 0 "X2" H 4500 2100 60 0000 C CNN
+F 1 "3_and" H 4550 2300 60 0000 C CNN
+F 2 "" H 4400 2150 60 0000 C CNN
+F 3 "" H 4400 2150 60 0000 C CNN
+ 1 4400 2150
+ 1 0 0 -1
+$EndComp
+Text Label 11950 1700 0 60 ~ 0
+4
+Text Label 9950 2850 0 60 ~ 0
+6
+Text Label 13050 2750 0 60 ~ 0
+8
+Text Label 9550 4300 0 60 ~ 0
+10
+$Comp
+L d_inverter U41
+U 1 1 6839AFAA
+P 10500 5850
+F 0 "U41" H 10500 5750 60 0000 C CNN
+F 1 "d_inverter" H 10500 6000 60 0000 C CNN
+F 2 "" H 10550 5800 60 0000 C CNN
+F 3 "" H 10550 5800 60 0000 C CNN
+ 1 10500 5850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4900 2100 5000 2100
+Wire Wire Line
+ 5000 2100 5050 2200
+Wire Wire Line
+ 5050 2200 5200 2200
+Wire Wire Line
+ 4950 2400 5050 2400
+Wire Wire Line
+ 5050 2400 5050 2300
+Wire Wire Line
+ 5050 2300 5200 2300
+Wire Wire Line
+ 6100 2250 6100 2300
+Wire Wire Line
+ 6100 2300 6350 2300
+Wire Wire Line
+ 4900 2750 5950 2750
+Wire Wire Line
+ 5950 2750 5950 2400
+Wire Wire Line
+ 5950 2400 6350 2400
+Wire Wire Line
+ 4050 2000 3900 2000
+Wire Wire Line
+ 3900 2000 3900 1700
+Wire Wire Line
+ 3900 1700 2850 1700
+Wire Wire Line
+ 3450 1500 2850 1500
+Wire Wire Line
+ 3650 2100 4050 2100
+Wire Wire Line
+ 3250 2100 3300 2100
+Wire Wire Line
+ 2650 2100 2500 2100
+Wire Wire Line
+ 4050 2650 3850 2650
+Wire Wire Line
+ 3850 2650 3850 1800
+Wire Wire Line
+ 3850 1800 2850 1800
+Wire Wire Line
+ 3300 2100 3300 8000
+Wire Wire Line
+ 3300 2350 4050 2350
+Wire Wire Line
+ 4050 2450 2700 2450
+Wire Wire Line
+ 4050 2750 3800 2750
+Wire Wire Line
+ 3800 2100 3800 7800
+Connection ~ 3800 2100
+Wire Wire Line
+ 4050 2850 3950 2850
+Wire Wire Line
+ 3950 2850 3950 3150
+Wire Wire Line
+ 3950 3150 4050 3150
+Wire Wire Line
+ 3800 3250 4050 3250
+Connection ~ 3800 2750
+Wire Wire Line
+ 3300 3550 4050 3550
+Connection ~ 3300 2350
+Wire Wire Line
+ 4050 3650 2700 3650
+Wire Wire Line
+ 4950 3200 5050 3200
+Wire Wire Line
+ 5050 3200 5050 3300
+Wire Wire Line
+ 5050 3300 5200 3300
+Wire Wire Line
+ 4950 3600 5100 3600
+Wire Wire Line
+ 5100 3600 5100 3400
+Wire Wire Line
+ 5100 3400 5200 3400
+Wire Wire Line
+ 4950 3950 5050 3950
+Wire Wire Line
+ 5050 3950 5050 4050
+Wire Wire Line
+ 5050 4050 5200 4050
+Wire Wire Line
+ 4950 4350 5050 4350
+Wire Wire Line
+ 5050 4350 5050 4150
+Wire Wire Line
+ 5050 4150 5200 4150
+Wire Wire Line
+ 3800 4000 4050 4000
+Connection ~ 3800 3250
+Wire Wire Line
+ 3300 4300 4050 4300
+Connection ~ 3300 3550
+Wire Wire Line
+ 4050 4400 2700 4400
+Wire Wire Line
+ 3800 4800 4050 4800
+Connection ~ 3800 4000
+Wire Wire Line
+ 3300 5000 4050 5000
+Connection ~ 3300 4300
+Wire Wire Line
+ 4050 5100 2700 5100
+Wire Wire Line
+ 3800 5500 4050 5500
+Connection ~ 3800 4800
+Wire Wire Line
+ 3300 5700 4050 5700
+Connection ~ 3300 5000
+Wire Wire Line
+ 4050 5800 2700 5800
+Wire Wire Line
+ 3800 6250 4050 6250
+Connection ~ 3800 5500
+Wire Wire Line
+ 3300 6450 4050 6450
+Connection ~ 3300 5700
+Wire Wire Line
+ 4050 6550 2700 6550
+Wire Wire Line
+ 3800 7050 4050 7050
+Connection ~ 3800 6250
+Wire Wire Line
+ 3300 7250 4050 7250
+Connection ~ 3300 6450
+Wire Wire Line
+ 3800 7800 4100 7800
+Connection ~ 3800 7050
+Wire Wire Line
+ 4050 7350 2700 7350
+Wire Wire Line
+ 3300 8000 4100 8000
+Connection ~ 3300 7250
+Wire Wire Line
+ 4100 8100 2700 8100
+Wire Wire Line
+ 4950 4750 5100 4750
+Wire Wire Line
+ 5100 4750 5100 4850
+Wire Wire Line
+ 5100 4850 5300 4850
+Wire Wire Line
+ 4950 5050 5100 5050
+Wire Wire Line
+ 5100 5050 5100 4950
+Wire Wire Line
+ 5100 4950 5300 4950
+Wire Wire Line
+ 4950 5450 5200 5450
+Wire Wire Line
+ 5200 5450 5200 5550
+Wire Wire Line
+ 5200 5550 5350 5550
+Wire Wire Line
+ 4950 5750 5200 5750
+Wire Wire Line
+ 5200 5750 5200 5650
+Wire Wire Line
+ 5200 5650 5350 5650
+Wire Wire Line
+ 4950 6200 5250 6200
+Wire Wire Line
+ 5250 6200 5250 6300
+Wire Wire Line
+ 5250 6300 5350 6300
+Wire Wire Line
+ 4950 6500 5200 6500
+Wire Wire Line
+ 5200 6500 5200 6400
+Wire Wire Line
+ 5200 6400 5350 6400
+Wire Wire Line
+ 4950 7000 5250 7000
+Wire Wire Line
+ 5250 7000 5250 7100
+Wire Wire Line
+ 5250 7100 5350 7100
+Wire Wire Line
+ 4950 7300 5250 7300
+Wire Wire Line
+ 5250 7300 5250 7200
+Wire Wire Line
+ 5250 7200 5350 7200
+Wire Wire Line
+ 5000 7750 5250 7750
+Wire Wire Line
+ 5250 7750 5250 7850
+Wire Wire Line
+ 5250 7850 5350 7850
+Wire Wire Line
+ 5000 8050 5250 8050
+Wire Wire Line
+ 5250 8050 5250 7950
+Wire Wire Line
+ 5250 7950 5350 7950
+Wire Wire Line
+ 6250 5600 6350 5600
+Wire Wire Line
+ 6250 6350 6350 6350
+Wire Wire Line
+ 6350 7150 6250 7150
+Wire Wire Line
+ 6250 7900 6350 7900
+Wire Wire Line
+ 6100 4100 6200 4100
+Wire Wire Line
+ 6200 4900 6300 4900
+Wire Wire Line
+ 6100 3350 6200 3350
+Wire Wire Line
+ 7250 2350 7350 2350
+Wire Wire Line
+ 3450 1400 2850 1400
+Wire Wire Line
+ 4350 1450 9450 1450
+Wire Wire Line
+ 9450 1450 9450 2700
+Wire Wire Line
+ 9450 2100 9750 2100
+Wire Wire Line
+ 9450 2700 9800 2700
+Wire Wire Line
+ 9800 2700 9800 5000
+Connection ~ 9450 2100
+Connection ~ 9800 3750
+Wire Wire Line
+ 9200 1450 9200 2350
+Wire Wire Line
+ 9200 2350 8250 2350
+Wire Wire Line
+ 8250 2350 8250 2650
+Wire Wire Line
+ 8250 2650 7600 2650
+Wire Wire Line
+ 7600 2650 7600 6950
+Wire Wire Line
+ 7600 3250 7850 3250
+Connection ~ 9200 1450
+Wire Wire Line
+ 7600 4700 7700 4700
+Connection ~ 7600 3250
+Wire Wire Line
+ 7600 6200 7850 6200
+Connection ~ 7600 4700
+Wire Wire Line
+ 9800 5000 10850 5000
+Wire Wire Line
+ 7600 6950 7050 6950
+Wire Wire Line
+ 7050 6950 7050 7600
+Wire Wire Line
+ 7050 7600 7150 7600
+Connection ~ 7600 6200
+Wire Wire Line
+ 7900 2350 8050 2350
+Wire Wire Line
+ 8050 2350 8050 1700
+Wire Wire Line
+ 8050 1700 9750 1700
+Wire Wire Line
+ 7300 2350 7300 2550
+Connection ~ 7300 2550
+Connection ~ 7300 2350
+Wire Wire Line
+ 7300 2550 9750 2550
+Wire Wire Line
+ 4050 2200 4050 1650
+Wire Wire Line
+ 4050 1650 7600 1650
+Wire Wire Line
+ 7600 1650 7600 1300
+Wire Wire Line
+ 7600 1300 11700 1300
+Wire Wire Line
+ 11700 1300 11700 2550
+Wire Wire Line
+ 11700 2550 11350 2550
+Wire Wire Line
+ 3950 3000 6300 3000
+Wire Wire Line
+ 6300 3000 6300 1500
+Wire Wire Line
+ 6300 1500 11550 1500
+Wire Wire Line
+ 11550 1500 11550 1700
+Wire Wire Line
+ 11350 1700 11950 1700
+Connection ~ 3950 3000
+Wire Wire Line
+ 6800 3350 7100 3350
+Wire Wire Line
+ 7100 3350 7100 2850
+Wire Wire Line
+ 7100 2850 7850 2850
+Wire Wire Line
+ 6150 3350 6150 3700
+Wire Wire Line
+ 6150 3700 7850 3700
+Connection ~ 6150 3350
+Wire Wire Line
+ 4050 3900 4050 3800
+Wire Wire Line
+ 4050 3800 7300 3800
+Wire Wire Line
+ 7300 3800 7300 2600
+Wire Wire Line
+ 7300 2600 9550 2600
+Wire Wire Line
+ 9550 2600 9550 2850
+Wire Wire Line
+ 9450 2850 9950 2850
+Wire Wire Line
+ 9800 3750 10900 3750
+Wire Wire Line
+ 10900 3750 10900 3400
+Wire Wire Line
+ 10900 3400 11200 3400
+Wire Wire Line
+ 6800 4100 10700 4100
+Wire Wire Line
+ 10700 4100 10700 3000
+Wire Wire Line
+ 10700 3000 11200 3000
+Wire Wire Line
+ 6150 4100 6150 4350
+Wire Wire Line
+ 6150 4350 11050 4350
+Wire Wire Line
+ 11050 4350 11050 3850
+Wire Wire Line
+ 11050 3850 11200 3850
+Connection ~ 6150 4100
+Wire Wire Line
+ 4050 4700 3900 4700
+Wire Wire Line
+ 3900 4700 3900 4500
+Wire Wire Line
+ 3900 4500 13050 4500
+Wire Wire Line
+ 13050 4500 13050 2750
+Wire Wire Line
+ 13050 3000 12800 3000
+Connection ~ 11550 1700
+Connection ~ 9550 2850
+Connection ~ 13050 3000
+Wire Wire Line
+ 6900 4900 7350 4900
+Wire Wire Line
+ 7350 4900 7350 4300
+Wire Wire Line
+ 7350 4300 7700 4300
+Wire Wire Line
+ 6250 4900 6250 5150
+Wire Wire Line
+ 6250 5150 7700 5150
+Connection ~ 6250 4900
+Wire Wire Line
+ 3900 5400 9450 5400
+Wire Wire Line
+ 9450 5400 9450 4300
+Wire Wire Line
+ 9300 4300 9550 4300
+Connection ~ 4050 5400
+Connection ~ 9450 4300
+Wire Wire Line
+ 6950 5600 10050 5600
+Wire Wire Line
+ 10050 4600 10050 5850
+Wire Wire Line
+ 10050 4600 10850 4600
+Wire Wire Line
+ 10050 5850 10200 5850
+Connection ~ 10050 5600
+Wire Wire Line
+ 10800 5850 10800 5450
+Wire Wire Line
+ 10800 5450 10850 5450
+Wire Wire Line
+ 4050 6150 3900 6150
+Wire Wire Line
+ 3900 6150 3900 5950
+Wire Wire Line
+ 3900 5950 12650 5950
+Wire Wire Line
+ 12650 5950 12650 4600
+Wire Wire Line
+ 12450 4600 12850 4600
+Connection ~ 12650 4600
+Text Label 12850 4600 0 60 ~ 0
+15
+$Comp
+L d_srff U45
+U 1 1 6839FD74
+P 11800 6500
+F 0 "U45" H 11800 6500 60 0000 C CNN
+F 1 "d_srff" H 11850 6650 60 0000 C CNN
+F 2 "" H 11800 6500 60 0000 C CNN
+F 3 "" H 11800 6500 60 0000 C CNN
+ 1 11800 6500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6950 6350 7350 6350
+Wire Wire Line
+ 7350 6350 7350 5800
+Wire Wire Line
+ 7350 5800 7850 5800
+Wire Wire Line
+ 7850 6650 6300 6650
+Wire Wire Line
+ 6300 6650 6300 6350
+Connection ~ 6300 6350
+Wire Wire Line
+ 4050 6950 4050 6750
+Wire Wire Line
+ 4050 6750 9650 6750
+Wire Wire Line
+ 9650 6750 9650 5800
+Wire Wire Line
+ 9450 5800 9800 5800
+Connection ~ 9650 5800
+Text Label 9800 5800 0 60 ~ 0
+17
+Wire Wire Line
+ 6950 7150 6950 6900
+Wire Wire Line
+ 6950 6900 10100 6900
+Wire Wire Line
+ 10100 6100 10100 6950
+Wire Wire Line
+ 10100 6100 11000 6100
+$Comp
+L d_inverter U43
+U 1 1 683A03BB
+P 10550 6950
+F 0 "U43" H 10550 6850 60 0000 C CNN
+F 1 "d_inverter" H 10550 7100 60 0000 C CNN
+F 2 "" H 10600 6900 60 0000 C CNN
+F 3 "" H 10600 6900 60 0000 C CNN
+ 1 10550 6950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10100 6950 10250 6950
+Connection ~ 10100 6900
+Wire Wire Line
+ 10850 6950 11000 6950
+Wire Wire Line
+ 4100 7700 4100 7450
+Wire Wire Line
+ 4100 7450 12850 7450
+Wire Wire Line
+ 12850 7450 12850 6100
+Wire Wire Line
+ 12600 6100 12950 6100
+Connection ~ 12850 6100
+Wire Wire Line
+ 6950 7900 6950 7200
+Wire Wire Line
+ 6950 7200 7150 7200
+Wire Wire Line
+ 6300 7900 6300 8050
+Wire Wire Line
+ 6300 8050 7150 8050
+Connection ~ 6300 7900
+Wire Wire Line
+ 8750 7200 8900 7200
+Text Label 8900 7200 0 60 ~ 0
+21
+NoConn ~ 11800 5750
+Wire Wire Line
+ 9950 5000 9950 6500
+Wire Wire Line
+ 9950 6500 11000 6500
+Connection ~ 9950 5000
+Text Label 12950 6100 0 60 ~ 0
+19
+Wire Wire Line
+ 9700 2900 11300 2900
+Wire Wire Line
+ 11300 2900 11300 2650
+Wire Wire Line
+ 11300 2650 11900 2650
+Wire Wire Line
+ 11900 2650 11900 2150
+Wire Wire Line
+ 11900 2150 12550 2150
+Wire Wire Line
+ 8650 4050 9700 4050
+Wire Wire Line
+ 9700 2900 9700 5550
+Connection ~ 10550 2900
+Wire Wire Line
+ 12000 4200 12900 4200
+Wire Wire Line
+ 12900 2450 12900 7300
+Wire Wire Line
+ 12900 2450 12350 2450
+Wire Wire Line
+ 12350 2450 12350 2150
+Connection ~ 12350 2150
+Wire Wire Line
+ 9700 5500 8500 5500
+Connection ~ 9700 4050
+Wire Wire Line
+ 12900 5800 11650 5800
+Connection ~ 12900 4200
+Wire Wire Line
+ 8650 7000 9750 7000
+Wire Wire Line
+ 9750 5550 9750 8400
+Wire Wire Line
+ 9700 5550 9750 5550
+Connection ~ 9700 5500
+Wire Wire Line
+ 12900 7300 11800 7300
+Connection ~ 12900 5800
+Wire Wire Line
+ 9750 8400 7950 8400
+Connection ~ 9750 7000
+$Comp
+L d_inverter U47
+U 1 1 683BD72A
+P 12550 1850
+F 0 "U47" H 12550 1750 60 0000 C CNN
+F 1 "d_inverter" H 12550 2000 60 0000 C CNN
+F 2 "" H 12600 1800 60 0000 C CNN
+F 3 "" H 12600 1800 60 0000 C CNN
+ 1 12550 1850
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 12550 1550 12550 1450
+Wire Wire Line
+ 12550 1450 12700 1450
+Text Label 12700 1450 0 60 ~ 0
+14
+Text Label 2850 1400 0 60 ~ 0
+13
+Text Label 2850 1500 0 60 ~ 0
+11
+Text Label 2850 1700 0 60 ~ 0
+2
+Text Label 2850 1800 0 60 ~ 0
+1
+Text Label 2500 2100 0 60 ~ 0
+23
+Text Label 2700 2450 0 60 ~ 0
+3
+Text Label 2700 3650 0 60 ~ 0
+5
+Text Label 2700 4400 0 60 ~ 0
+7
+Text Label 2700 5100 0 60 ~ 0
+9
+Text Label 2700 5800 0 60 ~ 0
+16
+Text Label 2700 6550 0 60 ~ 0
+18
+Text Label 2700 7350 0 60 ~ 0
+20
+Text Label 2700 8100 0 60 ~ 0
+22
+$Comp
+L PORT U4
+U 1 1 683C1ED9
+P 2600 1800
+F 0 "U4" H 2650 1900 30 0000 C CNN
+F 1 "PORT" H 2600 1800 30 0000 C CNN
+F 2 "" H 2600 1800 60 0000 C CNN
+F 3 "" H 2600 1800 60 0000 C CNN
+ 1 2600 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U4
+U 3 1 683C39FE
+P 2700 2700
+F 0 "U4" H 2750 2800 30 0000 C CNN
+F 1 "PORT" H 2700 2700 30 0000 C CNN
+F 2 "" H 2700 2700 60 0000 C CNN
+F 3 "" H 2700 2700 60 0000 C CNN
+ 3 2700 2700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U4
+U 5 1 683C3A97
+P 2700 3400
+F 0 "U4" H 2750 3500 30 0000 C CNN
+F 1 "PORT" H 2700 3400 30 0000 C CNN
+F 2 "" H 2700 3400 60 0000 C CNN
+F 3 "" H 2700 3400 60 0000 C CNN
+ 5 2700 3400
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U4
+U 7 1 683C3B1E
+P 2700 4150
+F 0 "U4" H 2750 4250 30 0000 C CNN
+F 1 "PORT" H 2700 4150 30 0000 C CNN
+F 2 "" H 2700 4150 60 0000 C CNN
+F 3 "" H 2700 4150 60 0000 C CNN
+ 7 2700 4150
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U4
+U 9 1 683C3BB7
+P 2700 4850
+F 0 "U4" H 2750 4950 30 0000 C CNN
+F 1 "PORT" H 2700 4850 30 0000 C CNN
+F 2 "" H 2700 4850 60 0000 C CNN
+F 3 "" H 2700 4850 60 0000 C CNN
+ 9 2700 4850
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U4
+U 11 1 683C3C46
+P 2600 1500
+F 0 "U4" H 2650 1600 30 0000 C CNN
+F 1 "PORT" H 2600 1500 30 0000 C CNN
+F 2 "" H 2600 1500 60 0000 C CNN
+F 3 "" H 2600 1500 60 0000 C CNN
+ 11 2600 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U4
+U 13 1 683C3CC7
+P 2600 1400
+F 0 "U4" H 2650 1500 30 0000 C CNN
+F 1 "PORT" H 2600 1400 30 0000 C CNN
+F 2 "" H 2600 1400 60 0000 C CNN
+F 3 "" H 2600 1400 60 0000 C CNN
+ 13 2600 1400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U4
+U 15 1 683C3D8E
+P 12850 4850
+F 0 "U4" H 12900 4950 30 0000 C CNN
+F 1 "PORT" H 12850 4850 30 0000 C CNN
+F 2 "" H 12850 4850 60 0000 C CNN
+F 3 "" H 12850 4850 60 0000 C CNN
+ 15 12850 4850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U4
+U 17 1 683C3E29
+P 9800 6050
+F 0 "U4" H 9850 6150 30 0000 C CNN
+F 1 "PORT" H 9800 6050 30 0000 C CNN
+F 2 "" H 9800 6050 60 0000 C CNN
+F 3 "" H 9800 6050 60 0000 C CNN
+ 17 9800 6050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U4
+U 19 1 683C3EB8
+P 12950 6350
+F 0 "U4" H 13000 6450 30 0000 C CNN
+F 1 "PORT" H 12950 6350 30 0000 C CNN
+F 2 "" H 12950 6350 60 0000 C CNN
+F 3 "" H 12950 6350 60 0000 C CNN
+ 19 12950 6350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U4
+U 2 1 683C3F41
+P 2600 1700
+F 0 "U4" H 2650 1800 30 0000 C CNN
+F 1 "PORT" H 2600 1700 30 0000 C CNN
+F 2 "" H 2600 1700 60 0000 C CNN
+F 3 "" H 2600 1700 60 0000 C CNN
+ 2 2600 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U4
+U 4 1 683C3FEA
+P 11950 1450
+F 0 "U4" H 12000 1550 30 0000 C CNN
+F 1 "PORT" H 11950 1450 30 0000 C CNN
+F 2 "" H 11950 1450 60 0000 C CNN
+F 3 "" H 11950 1450 60 0000 C CNN
+ 4 11950 1450
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U4
+U 6 1 683C7571
+P 9950 3100
+F 0 "U4" H 10000 3200 30 0000 C CNN
+F 1 "PORT" H 9950 3100 30 0000 C CNN
+F 2 "" H 9950 3100 60 0000 C CNN
+F 3 "" H 9950 3100 60 0000 C CNN
+ 6 9950 3100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U4
+U 8 1 683C7614
+P 13050 2500
+F 0 "U4" H 13100 2600 30 0000 C CNN
+F 1 "PORT" H 13050 2500 30 0000 C CNN
+F 2 "" H 13050 2500 60 0000 C CNN
+F 3 "" H 13050 2500 60 0000 C CNN
+ 8 13050 2500
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U4
+U 10 1 683C76B3
+P 9550 4550
+F 0 "U4" H 9600 4650 30 0000 C CNN
+F 1 "PORT" H 9550 4550 30 0000 C CNN
+F 2 "" H 9550 4550 60 0000 C CNN
+F 3 "" H 9550 4550 60 0000 C CNN
+ 10 9550 4550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U4
+U 12 1 683C7748
+P 11950 1950
+F 0 "U4" H 12000 2050 30 0000 C CNN
+F 1 "PORT" H 11950 1950 30 0000 C CNN
+F 2 "" H 11950 1950 60 0000 C CNN
+F 3 "" H 11950 1950 60 0000 C CNN
+ 12 11950 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U4
+U 14 1 683C821F
+P 12950 1450
+F 0 "U4" H 13000 1550 30 0000 C CNN
+F 1 "PORT" H 12950 1450 30 0000 C CNN
+F 2 "" H 12950 1450 60 0000 C CNN
+F 3 "" H 12950 1450 60 0000 C CNN
+ 14 12950 1450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U4
+U 16 1 683C82B6
+P 2700 5550
+F 0 "U4" H 2750 5650 30 0000 C CNN
+F 1 "PORT" H 2700 5550 30 0000 C CNN
+F 2 "" H 2700 5550 60 0000 C CNN
+F 3 "" H 2700 5550 60 0000 C CNN
+ 16 2700 5550
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U4
+U 18 1 683C834F
+P 2700 6300
+F 0 "U4" H 2750 6400 30 0000 C CNN
+F 1 "PORT" H 2700 6300 30 0000 C CNN
+F 2 "" H 2700 6300 60 0000 C CNN
+F 3 "" H 2700 6300 60 0000 C CNN
+ 18 2700 6300
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U4
+U 20 1 683C83EA
+P 2700 7100
+F 0 "U4" H 2750 7200 30 0000 C CNN
+F 1 "PORT" H 2700 7100 30 0000 C CNN
+F 2 "" H 2700 7100 60 0000 C CNN
+F 3 "" H 2700 7100 60 0000 C CNN
+ 20 2700 7100
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U4
+U 22 1 683C848B
+P 2700 7850
+F 0 "U4" H 2750 7950 30 0000 C CNN
+F 1 "PORT" H 2700 7850 30 0000 C CNN
+F 2 "" H 2700 7850 60 0000 C CNN
+F 3 "" H 2700 7850 60 0000 C CNN
+ 22 2700 7850
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U4
+U 23 1 683C8536
+P 2500 2350
+F 0 "U4" H 2550 2450 30 0000 C CNN
+F 1 "PORT" H 2500 2350 30 0000 C CNN
+F 2 "" H 2500 2350 60 0000 C CNN
+F 3 "" H 2500 2350 60 0000 C CNN
+ 23 2500 2350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U4
+U 21 1 683C8623
+P 9150 7200
+F 0 "U4" H 9200 7300 30 0000 C CNN
+F 1 "PORT" H 9150 7200 30 0000 C CNN
+F 2 "" H 9150 7200 60 0000 C CNN
+F 3 "" H 9150 7200 60 0000 C CNN
+ 21 9150 7200
+ -1 0 0 1
+$EndComp
+NoConn ~ 12200 1950
+$Comp
+L PORT U4
+U 24 1 6834EAAC
+P 12550 2250
+F 0 "U4" H 12600 2350 30 0000 C CNN
+F 1 "PORT" H 12550 2250 30 0000 C CNN
+F 2 "" H 12550 2250 60 0000 C CNN
+F 3 "" H 12550 2250 60 0000 C CNN
+ 24 12550 2250
+ 1 0 0 -1
+$EndComp
+NoConn ~ 12800 2250
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74199/SN74199.sub b/library/SubcircuitLibrary/SN74199/SN74199.sub
new file mode 100644
index 000000000..ae511c800
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/SN74199.sub
@@ -0,0 +1,193 @@
+* Subcircuit SN74198
+.subckt SN74198 /1 /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 ? /13 /14 /15 /16 /17 /18 /19 /20 /21 /22 /23 ?
+* d:\fossee\esim\library\subcircuitlibrary\sn74198\sn74198.cir
+.include 3_and.sub
+* u3 /13 /11 net-_u3-pad3_ d_nor
+* u5 net-_u1-pad2_ /3 net-_u5-pad3_ d_and
+* u7 net-_u6-pad3_ net-_u7-pad2_ net-_u36-pad1_ d_nor
+* u6 net-_u6-pad1_ net-_u5-pad3_ net-_u6-pad3_ d_or
+* u2 net-_u1-pad2_ ? d_inverter
+* u1 /23 net-_u1-pad2_ d_inverter
+x1 /1 net-_u10-pad2_ /4 net-_u7-pad2_ 3_and
+* u8 /4 net-_u10-pad2_ net-_u22-pad1_ d_and
+* u9 net-_u1-pad2_ /5 net-_u22-pad2_ d_and
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nor
+* u10 /6 net-_u10-pad2_ net-_u10-pad3_ d_and
+* u11 net-_u1-pad2_ /7 net-_u11-pad3_ d_and
+* u23 net-_u10-pad3_ net-_u11-pad3_ net-_u23-pad3_ d_nor
+* u12 /8 net-_u10-pad2_ net-_u12-pad3_ d_and
+* u13 net-_u1-pad2_ /9 net-_u13-pad3_ d_and
+* u14 /10 net-_u10-pad2_ net-_u14-pad3_ d_and
+* u15 net-_u1-pad2_ /16 net-_u15-pad3_ d_and
+* u16 /15 net-_u10-pad2_ net-_u16-pad3_ d_and
+* u17 net-_u1-pad2_ /18 net-_u17-pad3_ d_and
+* u18 /17 net-_u10-pad2_ net-_u18-pad3_ d_and
+* u19 net-_u1-pad2_ /20 net-_u19-pad3_ d_and
+* u20 /19 net-_u10-pad2_ net-_u20-pad3_ d_and
+* u21 net-_u1-pad2_ /22 net-_u21-pad3_ d_and
+* u24 net-_u12-pad3_ net-_u13-pad3_ net-_u24-pad3_ d_nor
+* u25 net-_u14-pad3_ net-_u15-pad3_ net-_u25-pad3_ d_nor
+* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_nor
+* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_nor
+* u28 net-_u20-pad3_ net-_u21-pad3_ net-_u28-pad3_ d_nor
+* u29 net-_u22-pad3_ net-_u29-pad2_ d_inverter
+* u36 net-_u36-pad1_ ? d_inverter
+* u30 net-_u23-pad3_ net-_u30-pad2_ d_inverter
+* u31 net-_u24-pad3_ net-_u31-pad2_ d_inverter
+* u32 net-_u25-pad3_ net-_u32-pad2_ d_inverter
+* u33 net-_u26-pad3_ net-_u33-pad2_ d_inverter
+* u34 net-_u27-pad3_ net-_u34-pad2_ d_inverter
+* u42 ? net-_u36-pad1_ net-_u3-pad3_ ? net-_u37-pad5_ /4 net-_u42-pad7_ d_srff
+* u39 net-_u29-pad2_ net-_u22-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /6 ? d_srff
+* u46 net-_u30-pad2_ net-_u23-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /8 ? d_srff
+* u38 net-_u31-pad2_ net-_u24-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /10 ? d_srff
+* u40 net-_u33-pad2_ net-_u26-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /17 ? d_srff
+* u44 net-_u32-pad2_ net-_u41-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /15 ? d_srff
+* u37 net-_u35-pad2_ net-_u28-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /21 ? d_srff
+* u35 net-_u28-pad3_ net-_u35-pad2_ d_inverter
+x2 /2 net-_u10-pad2_ net-_u42-pad7_ net-_u6-pad1_ 3_and
+* u41 net-_u32-pad2_ net-_u41-pad2_ d_inverter
+* u45 net-_u34-pad2_ net-_u43-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /19 ? d_srff
+* u43 net-_u34-pad2_ net-_u43-pad2_ d_inverter
+* u47 /14 net-_u37-pad5_ d_inverter
+a1 [/13 /11 ] net-_u3-pad3_ u3
+a2 [net-_u1-pad2_ /3 ] net-_u5-pad3_ u5
+a3 [net-_u6-pad3_ net-_u7-pad2_ ] net-_u36-pad1_ u7
+a4 [net-_u6-pad1_ net-_u5-pad3_ ] net-_u6-pad3_ u6
+a5 net-_u1-pad2_ ? u2
+a6 /23 net-_u1-pad2_ u1
+a7 [/4 net-_u10-pad2_ ] net-_u22-pad1_ u8
+a8 [net-_u1-pad2_ /5 ] net-_u22-pad2_ u9
+a9 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a10 [/6 net-_u10-pad2_ ] net-_u10-pad3_ u10
+a11 [net-_u1-pad2_ /7 ] net-_u11-pad3_ u11
+a12 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u23-pad3_ u23
+a13 [/8 net-_u10-pad2_ ] net-_u12-pad3_ u12
+a14 [net-_u1-pad2_ /9 ] net-_u13-pad3_ u13
+a15 [/10 net-_u10-pad2_ ] net-_u14-pad3_ u14
+a16 [net-_u1-pad2_ /16 ] net-_u15-pad3_ u15
+a17 [/15 net-_u10-pad2_ ] net-_u16-pad3_ u16
+a18 [net-_u1-pad2_ /18 ] net-_u17-pad3_ u17
+a19 [/17 net-_u10-pad2_ ] net-_u18-pad3_ u18
+a20 [net-_u1-pad2_ /20 ] net-_u19-pad3_ u19
+a21 [/19 net-_u10-pad2_ ] net-_u20-pad3_ u20
+a22 [net-_u1-pad2_ /22 ] net-_u21-pad3_ u21
+a23 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u24-pad3_ u24
+a24 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u25-pad3_ u25
+a25 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26
+a26 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27
+a27 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u28-pad3_ u28
+a28 net-_u22-pad3_ net-_u29-pad2_ u29
+a29 net-_u36-pad1_ ? u36
+a30 net-_u23-pad3_ net-_u30-pad2_ u30
+a31 net-_u24-pad3_ net-_u31-pad2_ u31
+a32 net-_u25-pad3_ net-_u32-pad2_ u32
+a33 net-_u26-pad3_ net-_u33-pad2_ u33
+a34 net-_u27-pad3_ net-_u34-pad2_ u34
+a35 ? net-_u36-pad1_ net-_u3-pad3_ ? net-_u37-pad5_ /4 net-_u42-pad7_ u42
+a36 net-_u29-pad2_ net-_u22-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /6 ? u39
+a37 net-_u30-pad2_ net-_u23-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /8 ? u46
+a38 net-_u31-pad2_ net-_u24-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /10 ? u38
+a39 net-_u33-pad2_ net-_u26-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /17 ? u40
+a40 net-_u32-pad2_ net-_u41-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /15 ? u44
+a41 net-_u35-pad2_ net-_u28-pad3_ net-_u3-pad3_ ? net-_u37-pad5_ /21 ? u37
+a42 net-_u28-pad3_ net-_u35-pad2_ u35
+a43 net-_u32-pad2_ net-_u41-pad2_ u41
+a44 net-_u34-pad2_ net-_u43-pad2_ net-_u3-pad3_ ? net-_u37-pad5_ /19 ? u45
+a45 net-_u34-pad2_ net-_u43-pad2_ u43
+a46 /14 net-_u37-pad5_ u47
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u42 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u39 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u46 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u38 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u40 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u44 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u37 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_srff, NgSpice Name: d_srff
+.model u45 d_srff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 sr_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74198
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74199/SN74199_Previous_Values.xml b/library/SubcircuitLibrary/SN74199/SN74199_Previous_Values.xml
new file mode 100644
index 000000000..24ef83e14
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/SN74199_Previous_Values.xml
@@ -0,0 +1 @@
+d_nord_andd_nord_ord_inverterd_inverterd_andd_andd_nord_andd_andd_nord_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_nord_nord_nord_nord_nord_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_srffd_srffd_srffd_srffd_srffd_srffd_srffd_inverterd_inverterd_srffd_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74199/analysis b/library/SubcircuitLibrary/SN74199/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74199/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1-cache.lib b/library/SubcircuitLibrary/SN74278_1/SN74278_1-cache.lib
new file mode 100644
index 000000000..3e8d471c7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1-cache.lib
@@ -0,0 +1,113 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir b/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir
new file mode 100644
index 000000000..eae044b5f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir
@@ -0,0 +1,45 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74278_1\SN74278_1.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/25 08:52:19
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U3-Pad1_ /1 Net-_U3-Pad3_ d_and
+U9 /3 /1 Net-_U8-Pad1_ d_and
+U13 Net-_U13-Pad1_ /1 Net-_U13-Pad3_ d_and
+U18 /2 /1 Net-_U17-Pad1_ d_and
+U22 Net-_U22-Pad1_ /1 Net-_U22-Pad3_ d_and
+U28 /13 /1 Net-_U26-Pad1_ d_and
+U29 Net-_U29-Pad1_ /1 Net-_U29-Pad3_ d_and
+U34 /12 /1 Net-_U33-Pad1_ d_and
+U7 /3 Net-_U3-Pad1_ d_inverter
+U16 /2 Net-_U13-Pad1_ d_inverter
+U31 /12 Net-_U29-Pad1_ d_inverter
+U25 /13 Net-_U22-Pad1_ d_inverter
+U5 Net-_U11-Pad2_ Net-_U3-Pad3_ Net-_U2-Pad2_ d_nor
+U8 Net-_U8-Pad1_ Net-_U2-Pad2_ Net-_U11-Pad2_ d_nor
+U15 Net-_U15-Pad1_ Net-_U13-Pad3_ Net-_U11-Pad1_ d_nor
+U17 Net-_U17-Pad1_ Net-_U11-Pad1_ Net-_U15-Pad1_ d_nor
+U24 Net-_U24-Pad1_ Net-_U22-Pad3_ Net-_U14-Pad2_ d_nor
+U26 Net-_U26-Pad1_ Net-_U14-Pad2_ Net-_U24-Pad1_ d_nor
+U30 Net-_U30-Pad1_ Net-_U29-Pad3_ Net-_U14-Pad1_ d_nor
+U33 Net-_U33-Pad1_ Net-_U14-Pad1_ Net-_U30-Pad1_ d_nor
+U32 Net-_U30-Pad1_ /4 /10 d_nor
+U12 Net-_U12-Pad1_ Net-_U11-Pad3_ Net-_U10-Pad1_ d_or
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U12-Pad1_ d_or
+U4 Net-_U4-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad1_ d_or
+U2 Net-_U11-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_or
+U6 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U4-Pad1_ d_or
+U1 Net-_U1-Pad1_ /4 /5 d_or
+U10 Net-_U10-Pad1_ /4 /6 d_nor
+U20 Net-_U20-Pad1_ Net-_U19-Pad3_ /8 d_nor
+U19 Net-_U15-Pad1_ /4 Net-_U19-Pad3_ d_or
+U21 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U20-Pad1_ d_or
+U23 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 ? /12 /13 ? PORT
+U35 Net-_U14-Pad1_ Net-_U24-Pad1_ Net-_U27-Pad1_ d_or
+U27 Net-_U27-Pad1_ /4 /9 d_nor
+
+.end
diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir.out b/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir.out
new file mode 100644
index 000000000..372b6a953
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.cir.out
@@ -0,0 +1,148 @@
+* d:\fossee\esim\library\subcircuitlibrary\sn74278_1\sn74278_1.cir
+
+* u3 net-_u3-pad1_ /1 net-_u3-pad3_ d_and
+* u9 /3 /1 net-_u8-pad1_ d_and
+* u13 net-_u13-pad1_ /1 net-_u13-pad3_ d_and
+* u18 /2 /1 net-_u17-pad1_ d_and
+* u22 net-_u22-pad1_ /1 net-_u22-pad3_ d_and
+* u28 /13 /1 net-_u26-pad1_ d_and
+* u29 net-_u29-pad1_ /1 net-_u29-pad3_ d_and
+* u34 /12 /1 net-_u33-pad1_ d_and
+* u7 /3 net-_u3-pad1_ d_inverter
+* u16 /2 net-_u13-pad1_ d_inverter
+* u31 /12 net-_u29-pad1_ d_inverter
+* u25 /13 net-_u22-pad1_ d_inverter
+* u5 net-_u11-pad2_ net-_u3-pad3_ net-_u2-pad2_ d_nor
+* u8 net-_u8-pad1_ net-_u2-pad2_ net-_u11-pad2_ d_nor
+* u15 net-_u15-pad1_ net-_u13-pad3_ net-_u11-pad1_ d_nor
+* u17 net-_u17-pad1_ net-_u11-pad1_ net-_u15-pad1_ d_nor
+* u24 net-_u24-pad1_ net-_u22-pad3_ net-_u14-pad2_ d_nor
+* u26 net-_u26-pad1_ net-_u14-pad2_ net-_u24-pad1_ d_nor
+* u30 net-_u30-pad1_ net-_u29-pad3_ net-_u14-pad1_ d_nor
+* u33 net-_u33-pad1_ net-_u14-pad1_ net-_u30-pad1_ d_nor
+* u32 net-_u30-pad1_ /4 /10 d_nor
+* u12 net-_u12-pad1_ net-_u11-pad3_ net-_u10-pad1_ d_or
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u12-pad1_ d_or
+* u4 net-_u4-pad1_ net-_u2-pad3_ net-_u1-pad1_ d_or
+* u2 net-_u11-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or
+* u6 net-_u14-pad1_ net-_u14-pad2_ net-_u4-pad1_ d_or
+* u1 net-_u1-pad1_ /4 /5 d_or
+* u10 net-_u10-pad1_ /4 /6 d_nor
+* u20 net-_u20-pad1_ net-_u19-pad3_ /8 d_nor
+* u19 net-_u15-pad1_ /4 net-_u19-pad3_ d_or
+* u21 net-_u14-pad1_ net-_u14-pad2_ net-_u20-pad1_ d_or
+* u23 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 ? /12 /13 ? port
+* u35 net-_u14-pad1_ net-_u24-pad1_ net-_u27-pad1_ d_or
+* u27 net-_u27-pad1_ /4 /9 d_nor
+a1 [net-_u3-pad1_ /1 ] net-_u3-pad3_ u3
+a2 [/3 /1 ] net-_u8-pad1_ u9
+a3 [net-_u13-pad1_ /1 ] net-_u13-pad3_ u13
+a4 [/2 /1 ] net-_u17-pad1_ u18
+a5 [net-_u22-pad1_ /1 ] net-_u22-pad3_ u22
+a6 [/13 /1 ] net-_u26-pad1_ u28
+a7 [net-_u29-pad1_ /1 ] net-_u29-pad3_ u29
+a8 [/12 /1 ] net-_u33-pad1_ u34
+a9 /3 net-_u3-pad1_ u7
+a10 /2 net-_u13-pad1_ u16
+a11 /12 net-_u29-pad1_ u31
+a12 /13 net-_u22-pad1_ u25
+a13 [net-_u11-pad2_ net-_u3-pad3_ ] net-_u2-pad2_ u5
+a14 [net-_u8-pad1_ net-_u2-pad2_ ] net-_u11-pad2_ u8
+a15 [net-_u15-pad1_ net-_u13-pad3_ ] net-_u11-pad1_ u15
+a16 [net-_u17-pad1_ net-_u11-pad1_ ] net-_u15-pad1_ u17
+a17 [net-_u24-pad1_ net-_u22-pad3_ ] net-_u14-pad2_ u24
+a18 [net-_u26-pad1_ net-_u14-pad2_ ] net-_u24-pad1_ u26
+a19 [net-_u30-pad1_ net-_u29-pad3_ ] net-_u14-pad1_ u30
+a20 [net-_u33-pad1_ net-_u14-pad1_ ] net-_u30-pad1_ u33
+a21 [net-_u30-pad1_ /4 ] /10 u32
+a22 [net-_u12-pad1_ net-_u11-pad3_ ] net-_u10-pad1_ u12
+a23 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a24 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u12-pad1_ u14
+a25 [net-_u4-pad1_ net-_u2-pad3_ ] net-_u1-pad1_ u4
+a26 [net-_u11-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
+a27 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u4-pad1_ u6
+a28 [net-_u1-pad1_ /4 ] /5 u1
+a29 [net-_u10-pad1_ /4 ] /6 u10
+a30 [net-_u20-pad1_ net-_u19-pad3_ ] /8 u20
+a31 [net-_u15-pad1_ /4 ] net-_u19-pad3_ u19
+a32 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u20-pad1_ u21
+a33 [net-_u14-pad1_ net-_u24-pad1_ ] net-_u27-pad1_ u35
+a34 [net-_u27-pad1_ /4 ] /9 u27
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u1 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.pro b/library/SubcircuitLibrary/SN74278_1/SN74278_1.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.sch b/library/SubcircuitLibrary/SN74278_1/SN74278_1.sch
new file mode 100644
index 000000000..ee1081b74
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.sch
@@ -0,0 +1,909 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74278_1-cache
+EELAYER 25 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U3
+U 1 1 6832A9C3
+P 3750 2750
+F 0 "U3" H 3750 2750 60 0000 C CNN
+F 1 "d_and" H 3800 2850 60 0000 C CNN
+F 2 "" H 3750 2750 60 0000 C CNN
+F 3 "" H 3750 2750 60 0000 C CNN
+ 1 3750 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U9
+U 1 1 6832AA54
+P 5200 2750
+F 0 "U9" H 5200 2750 60 0000 C CNN
+F 1 "d_and" H 5250 2850 60 0000 C CNN
+F 2 "" H 5200 2750 60 0000 C CNN
+F 3 "" H 5200 2750 60 0000 C CNN
+ 1 5200 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U13
+U 1 1 6832AB57
+P 6250 2750
+F 0 "U13" H 6250 2750 60 0000 C CNN
+F 1 "d_and" H 6300 2850 60 0000 C CNN
+F 2 "" H 6250 2750 60 0000 C CNN
+F 3 "" H 6250 2750 60 0000 C CNN
+ 1 6250 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U18
+U 1 1 6832AB5D
+P 7700 2750
+F 0 "U18" H 7700 2750 60 0000 C CNN
+F 1 "d_and" H 7750 2850 60 0000 C CNN
+F 2 "" H 7700 2750 60 0000 C CNN
+F 3 "" H 7700 2750 60 0000 C CNN
+ 1 7700 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U22
+U 1 1 6832AC9F
+P 8950 2750
+F 0 "U22" H 8950 2750 60 0000 C CNN
+F 1 "d_and" H 9000 2850 60 0000 C CNN
+F 2 "" H 8950 2750 60 0000 C CNN
+F 3 "" H 8950 2750 60 0000 C CNN
+ 1 8950 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U28
+U 1 1 6832ACA5
+P 10400 2750
+F 0 "U28" H 10400 2750 60 0000 C CNN
+F 1 "d_and" H 10450 2850 60 0000 C CNN
+F 2 "" H 10400 2750 60 0000 C CNN
+F 3 "" H 10400 2750 60 0000 C CNN
+ 1 10400 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U29
+U 1 1 6832ACAB
+P 11450 2750
+F 0 "U29" H 11450 2750 60 0000 C CNN
+F 1 "d_and" H 11500 2850 60 0000 C CNN
+F 2 "" H 11450 2750 60 0000 C CNN
+F 3 "" H 11450 2750 60 0000 C CNN
+ 1 11450 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_and U34
+U 1 1 6832ACB1
+P 12900 2750
+F 0 "U34" H 12900 2750 60 0000 C CNN
+F 1 "d_and" H 12950 2850 60 0000 C CNN
+F 2 "" H 12900 2750 60 0000 C CNN
+F 3 "" H 12900 2750 60 0000 C CNN
+ 1 12900 2750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 6832B0FA
+P 4450 2250
+F 0 "U7" H 4450 2150 60 0000 C CNN
+F 1 "d_inverter" H 4450 2400 60 0000 C CNN
+F 2 "" H 4500 2200 60 0000 C CNN
+F 3 "" H 4500 2200 60 0000 C CNN
+ 1 4450 2250
+ -1 0 0 1
+$EndComp
+$Comp
+L d_inverter U16
+U 1 1 6832BED3
+P 6850 2150
+F 0 "U16" H 6850 2050 60 0000 C CNN
+F 1 "d_inverter" H 6850 2300 60 0000 C CNN
+F 2 "" H 6900 2100 60 0000 C CNN
+F 3 "" H 6900 2100 60 0000 C CNN
+ 1 6850 2150
+ -1 0 0 1
+$EndComp
+$Comp
+L d_inverter U31
+U 1 1 6832BF42
+P 12150 2200
+F 0 "U31" H 12150 2100 60 0000 C CNN
+F 1 "d_inverter" H 12150 2350 60 0000 C CNN
+F 2 "" H 12200 2150 60 0000 C CNN
+F 3 "" H 12200 2150 60 0000 C CNN
+ 1 12150 2200
+ -1 0 0 1
+$EndComp
+$Comp
+L d_inverter U25
+U 1 1 6832C475
+P 9700 2150
+F 0 "U25" H 9700 2050 60 0000 C CNN
+F 1 "d_inverter" H 9700 2300 60 0000 C CNN
+F 2 "" H 9750 2100 60 0000 C CNN
+F 3 "" H 9750 2100 60 0000 C CNN
+ 1 9700 2150
+ -1 0 0 1
+$EndComp
+$Comp
+L d_nor U5
+U 1 1 6832C8C3
+P 4150 3800
+F 0 "U5" H 4150 3800 60 0000 C CNN
+F 1 "d_nor" H 4200 3900 60 0000 C CNN
+F 2 "" H 4150 3800 60 0000 C CNN
+F 3 "" H 4150 3800 60 0000 C CNN
+ 1 4150 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U8
+U 1 1 6832C9B0
+P 4700 3800
+F 0 "U8" H 4700 3800 60 0000 C CNN
+F 1 "d_nor" H 4750 3900 60 0000 C CNN
+F 2 "" H 4700 3800 60 0000 C CNN
+F 3 "" H 4700 3800 60 0000 C CNN
+ 1 4700 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U15
+U 1 1 6832CA6C
+P 6700 3800
+F 0 "U15" H 6700 3800 60 0000 C CNN
+F 1 "d_nor" H 6750 3900 60 0000 C CNN
+F 2 "" H 6700 3800 60 0000 C CNN
+F 3 "" H 6700 3800 60 0000 C CNN
+ 1 6700 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U17
+U 1 1 6832CA72
+P 7250 3800
+F 0 "U17" H 7250 3800 60 0000 C CNN
+F 1 "d_nor" H 7300 3900 60 0000 C CNN
+F 2 "" H 7250 3800 60 0000 C CNN
+F 3 "" H 7250 3800 60 0000 C CNN
+ 1 7250 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U24
+U 1 1 6832CB06
+P 9450 3800
+F 0 "U24" H 9450 3800 60 0000 C CNN
+F 1 "d_nor" H 9500 3900 60 0000 C CNN
+F 2 "" H 9450 3800 60 0000 C CNN
+F 3 "" H 9450 3800 60 0000 C CNN
+ 1 9450 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U26
+U 1 1 6832CB0C
+P 10000 3800
+F 0 "U26" H 10000 3800 60 0000 C CNN
+F 1 "d_nor" H 10050 3900 60 0000 C CNN
+F 2 "" H 10000 3800 60 0000 C CNN
+F 3 "" H 10000 3800 60 0000 C CNN
+ 1 10000 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U30
+U 1 1 6832CB94
+P 11900 3800
+F 0 "U30" H 11900 3800 60 0000 C CNN
+F 1 "d_nor" H 11950 3900 60 0000 C CNN
+F 2 "" H 11900 3800 60 0000 C CNN
+F 3 "" H 11900 3800 60 0000 C CNN
+ 1 11900 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U33
+U 1 1 6832CB9A
+P 12450 3800
+F 0 "U33" H 12450 3800 60 0000 C CNN
+F 1 "d_nor" H 12500 3900 60 0000 C CNN
+F 2 "" H 12450 3800 60 0000 C CNN
+F 3 "" H 12450 3800 60 0000 C CNN
+ 1 12450 3800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U32
+U 1 1 6832D913
+P 12400 5750
+F 0 "U32" H 12400 5750 60 0000 C CNN
+F 1 "d_nor" H 12450 5850 60 0000 C CNN
+F 2 "" H 12400 5750 60 0000 C CNN
+F 3 "" H 12400 5750 60 0000 C CNN
+ 1 12400 5750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_or U12
+U 1 1 68332BBE
+P 6100 7000
+F 0 "U12" H 6100 7000 60 0000 C CNN
+F 1 "d_or" H 6100 7100 60 0000 C CNN
+F 2 "" H 6100 7000 60 0000 C CNN
+F 3 "" H 6100 7000 60 0000 C CNN
+ 1 6100 7000
+ 0 1 1 0
+$EndComp
+$Comp
+L d_or U11
+U 1 1 68332CD2
+P 5700 5800
+F 0 "U11" H 5700 5800 60 0000 C CNN
+F 1 "d_or" H 5700 5900 60 0000 C CNN
+F 2 "" H 5700 5800 60 0000 C CNN
+F 3 "" H 5700 5800 60 0000 C CNN
+ 1 5700 5800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_or U14
+U 1 1 68332D3D
+P 6350 5800
+F 0 "U14" H 6350 5800 60 0000 C CNN
+F 1 "d_or" H 6350 5900 60 0000 C CNN
+F 2 "" H 6350 5800 60 0000 C CNN
+F 3 "" H 6350 5800 60 0000 C CNN
+ 1 6350 5800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_or U4
+U 1 1 683362DD
+P 4050 6950
+F 0 "U4" H 4050 6950 60 0000 C CNN
+F 1 "d_or" H 4050 7050 60 0000 C CNN
+F 2 "" H 4050 6950 60 0000 C CNN
+F 3 "" H 4050 6950 60 0000 C CNN
+ 1 4050 6950
+ 0 1 1 0
+$EndComp
+$Comp
+L d_or U2
+U 1 1 683362E3
+P 3650 5750
+F 0 "U2" H 3650 5750 60 0000 C CNN
+F 1 "d_or" H 3650 5850 60 0000 C CNN
+F 2 "" H 3650 5750 60 0000 C CNN
+F 3 "" H 3650 5750 60 0000 C CNN
+ 1 3650 5750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_or U6
+U 1 1 683362E9
+P 4300 5750
+F 0 "U6" H 4300 5750 60 0000 C CNN
+F 1 "d_or" H 4300 5850 60 0000 C CNN
+F 2 "" H 4300 5750 60 0000 C CNN
+F 3 "" H 4300 5750 60 0000 C CNN
+ 1 4300 5750
+ 0 1 1 0
+$EndComp
+$Comp
+L d_or U1
+U 1 1 683362F1
+P 3400 7850
+F 0 "U1" H 3400 7850 60 0000 C CNN
+F 1 "d_or" H 3400 7950 60 0000 C CNN
+F 2 "" H 3400 7850 60 0000 C CNN
+F 3 "" H 3400 7850 60 0000 C CNN
+ 1 3400 7850
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U10
+U 1 1 683364B9
+P 5450 7900
+F 0 "U10" H 5450 7900 60 0000 C CNN
+F 1 "d_nor" H 5500 8000 60 0000 C CNN
+F 2 "" H 5450 7900 60 0000 C CNN
+F 3 "" H 5450 7900 60 0000 C CNN
+ 1 5450 7900
+ 0 1 1 0
+$EndComp
+$Comp
+L d_nor U20
+U 1 1 68332822
+P 8150 7100
+F 0 "U20" H 8150 7100 60 0000 C CNN
+F 1 "d_nor" H 8200 7200 60 0000 C CNN
+F 2 "" H 8150 7100 60 0000 C CNN
+F 3 "" H 8150 7100 60 0000 C CNN
+ 1 8150 7100
+ 0 1 1 0
+$EndComp
+$Comp
+L d_or U19
+U 1 1 683426AE
+P 7750 5800
+F 0 "U19" H 7750 5800 60 0000 C CNN
+F 1 "d_or" H 7750 5900 60 0000 C CNN
+F 2 "" H 7750 5800 60 0000 C CNN
+F 3 "" H 7750 5800 60 0000 C CNN
+ 1 7750 5800
+ 0 1 1 0
+$EndComp
+$Comp
+L d_or U21
+U 1 1 683426B4
+P 8400 5800
+F 0 "U21" H 8400 5800 60 0000 C CNN
+F 1 "d_or" H 8400 5900 60 0000 C CNN
+F 2 "" H 8400 5800 60 0000 C CNN
+F 3 "" H 8400 5800 60 0000 C CNN
+ 1 8400 5800
+ 0 1 1 0
+$EndComp
+Text Label 4550 1550 0 60 ~ 0
+1
+Text Label 5300 1350 0 60 ~ 0
+3
+Text Label 3400 1900 0 60 ~ 0
+4
+Text Label 7800 1350 0 60 ~ 0
+2
+Text Label 10500 1350 0 60 ~ 0
+13
+Text Label 13000 1350 0 60 ~ 0
+12
+Text Label 12450 6400 0 60 ~ 0
+10
+Text Label 9450 6950 3 60 ~ 0
+9
+Text Label 8200 7700 0 60 ~ 0
+8
+Text Label 5750 8350 0 60 ~ 0
+6
+Wire Wire Line
+ 12900 1800 12900 2300
+Wire Wire Line
+ 3750 1800 12900 1800
+Wire Wire Line
+ 3750 1800 3750 2300
+Wire Wire Line
+ 5200 2300 5200 1800
+Connection ~ 5200 1800
+Wire Wire Line
+ 6250 2300 6250 1800
+Connection ~ 6250 1800
+Wire Wire Line
+ 7700 2300 7700 1800
+Connection ~ 7700 1800
+Wire Wire Line
+ 8950 2300 8950 1800
+Connection ~ 8950 1800
+Wire Wire Line
+ 10400 2300 10400 1800
+Connection ~ 10400 1800
+Wire Wire Line
+ 11450 2300 11450 1800
+Connection ~ 11450 1800
+Wire Wire Line
+ 4150 2250 3850 2250
+Wire Wire Line
+ 3850 2250 3850 2300
+Wire Wire Line
+ 4750 2250 5300 2250
+Wire Wire Line
+ 5300 1350 5300 2300
+Wire Wire Line
+ 9050 2150 9400 2150
+Wire Wire Line
+ 11850 2200 11550 2200
+Connection ~ 5300 2250
+Wire Wire Line
+ 7800 1350 7800 2300
+Wire Wire Line
+ 10500 1350 10500 2300
+Wire Wire Line
+ 13000 1350 13000 2300
+Wire Wire Line
+ 12450 2200 13000 2200
+Connection ~ 13000 2200
+Wire Wire Line
+ 11550 2200 11550 2300
+Wire Wire Line
+ 9050 2150 9050 2300
+Wire Wire Line
+ 7150 2150 7800 2150
+Connection ~ 10500 2150
+Connection ~ 7800 2150
+Wire Wire Line
+ 6550 2150 6350 2150
+Wire Wire Line
+ 6350 2150 6350 2300
+Wire Wire Line
+ 10000 2150 10500 2150
+Wire Wire Line
+ 3800 3200 4150 3200
+Wire Wire Line
+ 4150 3200 4150 3350
+Wire Wire Line
+ 5250 3200 4800 3200
+Wire Wire Line
+ 4800 3200 4800 3350
+Wire Wire Line
+ 6300 3200 6300 3300
+Wire Wire Line
+ 6300 3300 6700 3300
+Wire Wire Line
+ 6700 3300 6700 3350
+Wire Wire Line
+ 7750 3200 7350 3200
+Wire Wire Line
+ 7350 3200 7350 3350
+Wire Wire Line
+ 9000 3200 9450 3200
+Wire Wire Line
+ 9450 3200 9450 3350
+Wire Wire Line
+ 10450 3200 10100 3200
+Wire Wire Line
+ 10100 3200 10100 3350
+Wire Wire Line
+ 11500 3200 11900 3200
+Wire Wire Line
+ 11900 3200 11900 3350
+Wire Wire Line
+ 12950 3200 12550 3200
+Wire Wire Line
+ 12550 3200 12550 3350
+Wire Wire Line
+ 4750 4250 4750 4450
+Wire Wire Line
+ 4200 4250 4200 4550
+Wire Wire Line
+ 6750 4800 6750 4250
+Wire Wire Line
+ 9500 4900 9500 4250
+Wire Wire Line
+ 10050 4250 10050 5450
+Wire Wire Line
+ 11950 5150 11950 4250
+Wire Wire Line
+ 12500 4250 12500 5300
+Wire Wire Line
+ 4250 3350 4250 3300
+Wire Wire Line
+ 4250 3300 4450 3300
+Wire Wire Line
+ 4450 3300 4450 4350
+Wire Wire Line
+ 4450 4350 4750 4350
+Connection ~ 4750 4350
+Wire Wire Line
+ 4700 3350 4700 3300
+Wire Wire Line
+ 4700 3300 4500 3300
+Wire Wire Line
+ 4500 3300 4500 4450
+Wire Wire Line
+ 4500 4450 4200 4450
+Connection ~ 4200 4450
+Wire Wire Line
+ 6800 3350 7100 3350
+Wire Wire Line
+ 7100 3350 7100 4350
+Wire Wire Line
+ 7100 4350 7850 4350
+Connection ~ 7300 4350
+Wire Wire Line
+ 7250 3350 7250 3250
+Wire Wire Line
+ 7250 3250 6900 3250
+Wire Wire Line
+ 6900 3250 6900 4350
+Wire Wire Line
+ 6900 4350 6750 4350
+Connection ~ 6750 4350
+Wire Wire Line
+ 9550 3350 9550 3250
+Wire Wire Line
+ 9550 3250 9850 3250
+Wire Wire Line
+ 9850 3250 9850 4350
+Wire Wire Line
+ 9850 4350 10050 4350
+Connection ~ 10050 4350
+Wire Wire Line
+ 10000 3350 9700 3350
+Wire Wire Line
+ 9700 3350 9700 4350
+Wire Wire Line
+ 9700 4350 9500 4350
+Connection ~ 9500 4350
+Wire Wire Line
+ 12000 3350 12000 3250
+Wire Wire Line
+ 12000 3250 12300 3250
+Wire Wire Line
+ 12300 3250 12300 4300
+Wire Wire Line
+ 12300 4300 12500 4300
+Connection ~ 12500 4300
+Wire Wire Line
+ 12450 3350 12150 3350
+Wire Wire Line
+ 12150 3350 12150 4300
+Wire Wire Line
+ 12150 4300 11950 4300
+Connection ~ 11950 4300
+Wire Wire Line
+ 6400 6450 6200 6450
+Wire Wire Line
+ 6200 6450 6200 6550
+Wire Wire Line
+ 5750 6450 6100 6450
+Wire Wire Line
+ 6100 6450 6100 6550
+Wire Wire Line
+ 6400 6250 6400 6450
+Wire Wire Line
+ 5750 6250 5750 6450
+Wire Wire Line
+ 5550 7450 6150 7450
+Wire Wire Line
+ 4350 6400 4150 6400
+Wire Wire Line
+ 4150 6400 4150 6500
+Wire Wire Line
+ 3700 6400 4050 6400
+Wire Wire Line
+ 4050 6400 4050 6500
+Wire Wire Line
+ 4350 6200 4350 6400
+Wire Wire Line
+ 3700 6200 3700 6400
+Wire Wire Line
+ 3500 7400 4100 7400
+Wire Wire Line
+ 3400 1900 3400 7400
+Wire Wire Line
+ 8150 6450 8150 6650
+Wire Wire Line
+ 8250 6450 8250 6650
+Wire Wire Line
+ 3650 4550 3650 5300
+Wire Wire Line
+ 3750 4800 3750 5300
+Wire Wire Line
+ 4300 4900 4300 5300
+Wire Wire Line
+ 8450 6450 8250 6450
+Wire Wire Line
+ 7800 6450 8150 6450
+Wire Wire Line
+ 8450 6250 8450 6450
+Wire Wire Line
+ 7800 6250 7800 6450
+Wire Wire Line
+ 4200 4550 3650 4550
+Wire Wire Line
+ 4400 5300 4400 5150
+Wire Wire Line
+ 3750 4800 6750 4800
+Wire Wire Line
+ 4300 4900 9500 4900
+Wire Wire Line
+ 4400 5150 11950 5150
+Wire Wire Line
+ 5450 6600 5450 7450
+Wire Wire Line
+ 5800 5350 5800 4800
+Connection ~ 5800 4800
+Wire Wire Line
+ 6350 5350 6350 4900
+Connection ~ 6350 4900
+Wire Wire Line
+ 6450 5350 6450 5150
+Connection ~ 6450 5150
+Wire Wire Line
+ 4750 4450 5700 4450
+Wire Wire Line
+ 5700 4450 5700 5350
+Wire Wire Line
+ 8400 5350 8400 4900
+Connection ~ 8400 4900
+Wire Wire Line
+ 8500 5350 8500 5150
+Connection ~ 8500 5150
+Wire Wire Line
+ 7300 4350 7300 4250
+Wire Wire Line
+ 7850 4350 7850 5350
+Wire Wire Line
+ 10200 5150 10200 5450
+Connection ~ 10200 5150
+Wire Wire Line
+ 3400 6600 7250 6600
+Connection ~ 3400 6600
+Wire Wire Line
+ 7250 6600 7250 5300
+Wire Wire Line
+ 7250 5300 12400 5300
+Wire Wire Line
+ 7750 5300 7750 5350
+Connection ~ 5450 6600
+Connection ~ 7750 5300
+Connection ~ 9900 5300
+Wire Wire Line
+ 4550 1800 4550 1550
+Connection ~ 4550 1800
+Wire Wire Line
+ 12450 6200 12450 6400
+Wire Wire Line
+ 9600 6950 9450 6950
+Wire Wire Line
+ 8200 7550 8200 7700
+Wire Wire Line
+ 5500 8350 5750 8350
+Wire Wire Line
+ 3450 8300 3650 8300
+Text Label 3650 8300 0 60 ~ 0
+5
+$Comp
+L PORT U23
+U 6 1 68353778
+P 6000 8350
+F 0 "U23" H 6050 8450 30 0000 C CNN
+F 1 "PORT" H 6000 8350 30 0000 C CNN
+F 2 "" H 6000 8350 60 0000 C CNN
+F 3 "" H 6000 8350 60 0000 C CNN
+ 6 6000 8350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U23
+U 7 1 6835381D
+P 11400 1250
+F 0 "U23" H 11450 1350 30 0000 C CNN
+F 1 "PORT" H 11400 1250 30 0000 C CNN
+F 2 "" H 11400 1250 60 0000 C CNN
+F 3 "" H 11400 1250 60 0000 C CNN
+ 7 11400 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U23
+U 8 1 68353892
+P 8200 7950
+F 0 "U23" H 8250 8050 30 0000 C CNN
+F 1 "PORT" H 8200 7950 30 0000 C CNN
+F 2 "" H 8200 7950 60 0000 C CNN
+F 3 "" H 8200 7950 60 0000 C CNN
+ 8 8200 7950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U23
+U 9 1 683538F1
+P 9200 6950
+F 0 "U23" H 9250 7050 30 0000 C CNN
+F 1 "PORT" H 9200 6950 30 0000 C CNN
+F 2 "" H 9200 6950 60 0000 C CNN
+F 3 "" H 9200 6950 60 0000 C CNN
+ 9 9200 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U23
+U 10 1 68353952
+P 12450 6650
+F 0 "U23" H 12500 6750 30 0000 C CNN
+F 1 "PORT" H 12450 6650 30 0000 C CNN
+F 2 "" H 12450 6650 60 0000 C CNN
+F 3 "" H 12450 6650 60 0000 C CNN
+ 10 12450 6650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U23
+U 11 1 683539B7
+P 12000 1250
+F 0 "U23" H 12050 1350 30 0000 C CNN
+F 1 "PORT" H 12000 1250 30 0000 C CNN
+F 2 "" H 12000 1250 60 0000 C CNN
+F 3 "" H 12000 1250 60 0000 C CNN
+ 11 12000 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U23
+U 12 1 68353A1A
+P 12750 1350
+F 0 "U23" H 12800 1450 30 0000 C CNN
+F 1 "PORT" H 12750 1350 30 0000 C CNN
+F 2 "" H 12750 1350 60 0000 C CNN
+F 3 "" H 12750 1350 60 0000 C CNN
+ 12 12750 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U23
+U 13 1 68353A83
+P 10250 1350
+F 0 "U23" H 10300 1450 30 0000 C CNN
+F 1 "PORT" H 10250 1350 30 0000 C CNN
+F 2 "" H 10250 1350 60 0000 C CNN
+F 3 "" H 10250 1350 60 0000 C CNN
+ 13 10250 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U23
+U 1 1 68353AEC
+P 4300 1550
+F 0 "U23" H 4350 1650 30 0000 C CNN
+F 1 "PORT" H 4300 1550 30 0000 C CNN
+F 2 "" H 4300 1550 60 0000 C CNN
+F 3 "" H 4300 1550 60 0000 C CNN
+ 1 4300 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U23
+U 2 1 68353B71
+P 7550 1350
+F 0 "U23" H 7600 1450 30 0000 C CNN
+F 1 "PORT" H 7550 1350 30 0000 C CNN
+F 2 "" H 7550 1350 60 0000 C CNN
+F 3 "" H 7550 1350 60 0000 C CNN
+ 2 7550 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U23
+U 3 1 68353BDC
+P 5050 1350
+F 0 "U23" H 5100 1450 30 0000 C CNN
+F 1 "PORT" H 5050 1350 30 0000 C CNN
+F 2 "" H 5050 1350 60 0000 C CNN
+F 3 "" H 5050 1350 60 0000 C CNN
+ 3 5050 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U23
+U 4 1 68353C4F
+P 3150 1900
+F 0 "U23" H 3200 2000 30 0000 C CNN
+F 1 "PORT" H 3150 1900 30 0000 C CNN
+F 2 "" H 3150 1900 60 0000 C CNN
+F 3 "" H 3150 1900 60 0000 C CNN
+ 4 3150 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U23
+U 5 1 68353CC6
+P 3900 8300
+F 0 "U23" H 3950 8400 30 0000 C CNN
+F 1 "PORT" H 3900 8300 30 0000 C CNN
+F 2 "" H 3900 8300 60 0000 C CNN
+F 3 "" H 3900 8300 60 0000 C CNN
+ 5 3900 8300
+ -1 0 0 1
+$EndComp
+NoConn ~ 12250 1250
+NoConn ~ 11650 1250
+$Comp
+L d_or U35
+U 1 1 6837FE79
+P 10100 5900
+F 0 "U35" H 10100 5900 60 0000 C CNN
+F 1 "d_or" H 10100 6000 60 0000 C CNN
+F 2 "" H 10100 5900 60 0000 C CNN
+F 3 "" H 10100 5900 60 0000 C CNN
+ 1 10100 5900
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 10050 5450 10100 5450
+$Comp
+L d_nor U27
+U 1 1 68380747
+P 9550 6500
+F 0 "U27" H 9550 6500 60 0000 C CNN
+F 1 "d_nor" H 9600 6600 60 0000 C CNN
+F 2 "" H 9550 6500 60 0000 C CNN
+F 3 "" H 9550 6500 60 0000 C CNN
+ 1 9550 6500
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 10150 6350 9850 6350
+Wire Wire Line
+ 9850 6350 9850 6050
+Wire Wire Line
+ 9850 6050 9650 6050
+Wire Wire Line
+ 9900 5300 9900 5800
+Wire Wire Line
+ 9900 5800 9550 5800
+Wire Wire Line
+ 9550 5800 9550 6050
+$Comp
+L PORT U23
+U 14 1 6838B657
+P 11850 1500
+F 0 "U23" H 11900 1600 30 0000 C CNN
+F 1 "PORT" H 11850 1500 30 0000 C CNN
+F 2 "" H 11850 1500 60 0000 C CNN
+F 3 "" H 11850 1500 60 0000 C CNN
+ 14 11850 1500
+ 1 0 0 -1
+$EndComp
+NoConn ~ 12100 1500
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1.sub b/library/SubcircuitLibrary/SN74278_1/SN74278_1.sub
new file mode 100644
index 000000000..fcbcbc279
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1.sub
@@ -0,0 +1,142 @@
+* Subcircuit SN74278_1
+.subckt SN74278_1 /1 /2 /3 /4 /5 /6 ? /8 /9 /10 ? /12 /13 ?
+* d:\fossee\esim\library\subcircuitlibrary\sn74278_1\sn74278_1.cir
+* u3 net-_u3-pad1_ /1 net-_u3-pad3_ d_and
+* u9 /3 /1 net-_u8-pad1_ d_and
+* u13 net-_u13-pad1_ /1 net-_u13-pad3_ d_and
+* u18 /2 /1 net-_u17-pad1_ d_and
+* u22 net-_u22-pad1_ /1 net-_u22-pad3_ d_and
+* u28 /13 /1 net-_u26-pad1_ d_and
+* u29 net-_u29-pad1_ /1 net-_u29-pad3_ d_and
+* u34 /12 /1 net-_u33-pad1_ d_and
+* u7 /3 net-_u3-pad1_ d_inverter
+* u16 /2 net-_u13-pad1_ d_inverter
+* u31 /12 net-_u29-pad1_ d_inverter
+* u25 /13 net-_u22-pad1_ d_inverter
+* u5 net-_u11-pad2_ net-_u3-pad3_ net-_u2-pad2_ d_nor
+* u8 net-_u8-pad1_ net-_u2-pad2_ net-_u11-pad2_ d_nor
+* u15 net-_u15-pad1_ net-_u13-pad3_ net-_u11-pad1_ d_nor
+* u17 net-_u17-pad1_ net-_u11-pad1_ net-_u15-pad1_ d_nor
+* u24 net-_u24-pad1_ net-_u22-pad3_ net-_u14-pad2_ d_nor
+* u26 net-_u26-pad1_ net-_u14-pad2_ net-_u24-pad1_ d_nor
+* u30 net-_u30-pad1_ net-_u29-pad3_ net-_u14-pad1_ d_nor
+* u33 net-_u33-pad1_ net-_u14-pad1_ net-_u30-pad1_ d_nor
+* u32 net-_u30-pad1_ /4 /10 d_nor
+* u12 net-_u12-pad1_ net-_u11-pad3_ net-_u10-pad1_ d_or
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u12-pad1_ d_or
+* u4 net-_u4-pad1_ net-_u2-pad3_ net-_u1-pad1_ d_or
+* u2 net-_u11-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or
+* u6 net-_u14-pad1_ net-_u14-pad2_ net-_u4-pad1_ d_or
+* u1 net-_u1-pad1_ /4 /5 d_or
+* u10 net-_u10-pad1_ /4 /6 d_nor
+* u20 net-_u20-pad1_ net-_u19-pad3_ /8 d_nor
+* u19 net-_u15-pad1_ /4 net-_u19-pad3_ d_or
+* u21 net-_u14-pad1_ net-_u14-pad2_ net-_u20-pad1_ d_or
+* u35 net-_u14-pad1_ net-_u24-pad1_ net-_u27-pad1_ d_or
+* u27 net-_u27-pad1_ /4 /9 d_nor
+a1 [net-_u3-pad1_ /1 ] net-_u3-pad3_ u3
+a2 [/3 /1 ] net-_u8-pad1_ u9
+a3 [net-_u13-pad1_ /1 ] net-_u13-pad3_ u13
+a4 [/2 /1 ] net-_u17-pad1_ u18
+a5 [net-_u22-pad1_ /1 ] net-_u22-pad3_ u22
+a6 [/13 /1 ] net-_u26-pad1_ u28
+a7 [net-_u29-pad1_ /1 ] net-_u29-pad3_ u29
+a8 [/12 /1 ] net-_u33-pad1_ u34
+a9 /3 net-_u3-pad1_ u7
+a10 /2 net-_u13-pad1_ u16
+a11 /12 net-_u29-pad1_ u31
+a12 /13 net-_u22-pad1_ u25
+a13 [net-_u11-pad2_ net-_u3-pad3_ ] net-_u2-pad2_ u5
+a14 [net-_u8-pad1_ net-_u2-pad2_ ] net-_u11-pad2_ u8
+a15 [net-_u15-pad1_ net-_u13-pad3_ ] net-_u11-pad1_ u15
+a16 [net-_u17-pad1_ net-_u11-pad1_ ] net-_u15-pad1_ u17
+a17 [net-_u24-pad1_ net-_u22-pad3_ ] net-_u14-pad2_ u24
+a18 [net-_u26-pad1_ net-_u14-pad2_ ] net-_u24-pad1_ u26
+a19 [net-_u30-pad1_ net-_u29-pad3_ ] net-_u14-pad1_ u30
+a20 [net-_u33-pad1_ net-_u14-pad1_ ] net-_u30-pad1_ u33
+a21 [net-_u30-pad1_ /4 ] /10 u32
+a22 [net-_u12-pad1_ net-_u11-pad3_ ] net-_u10-pad1_ u12
+a23 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a24 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u12-pad1_ u14
+a25 [net-_u4-pad1_ net-_u2-pad3_ ] net-_u1-pad1_ u4
+a26 [net-_u11-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
+a27 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u4-pad1_ u6
+a28 [net-_u1-pad1_ /4 ] /5 u1
+a29 [net-_u10-pad1_ /4 ] /6 u10
+a30 [net-_u20-pad1_ net-_u19-pad3_ ] /8 u20
+a31 [net-_u15-pad1_ /4 ] net-_u19-pad3_ u19
+a32 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u20-pad1_ u21
+a33 [net-_u14-pad1_ net-_u24-pad1_ ] net-_u27-pad1_ u35
+a34 [net-_u27-pad1_ /4 ] /9 u27
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u30 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u32 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u1 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74278_1
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74278_1/SN74278_1_Previous_Values.xml b/library/SubcircuitLibrary/SN74278_1/SN74278_1_Previous_Values.xml
new file mode 100644
index 000000000..d169382b6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74278_1/SN74278_1_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andd_andd_andd_andd_andd_andd_andd_inverterd_inverterd_inverterd_inverterd_nord_nord_nord_nord_nord_nord_nord_nord_nord_ord_ord_ord_ord_ord_ord_ord_nord_nord_ord_ord_ord_nortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74278_1/analysis b/library/SubcircuitLibrary/SN74278_1/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74278_1/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74279/3_and-cache.lib b/library/SubcircuitLibrary/SN74279/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74279/3_and.cir b/library/SubcircuitLibrary/SN74279/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74279/3_and.cir.out b/library/SubcircuitLibrary/SN74279/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74279/3_and.pro b/library/SubcircuitLibrary/SN74279/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74279/3_and.sch b/library/SubcircuitLibrary/SN74279/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74279/3_and.sub b/library/SubcircuitLibrary/SN74279/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74279/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74279/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74279/SN74279-cache.lib b/library/SubcircuitLibrary/SN74279/SN74279-cache.lib
new file mode 100644
index 000000000..cecf21613
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/SN74279-cache.lib
@@ -0,0 +1,93 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74279/SN74279.cir b/library/SubcircuitLibrary/SN74279/SN74279.cir
new file mode 100644
index 000000000..e454794a6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/SN74279.cir
@@ -0,0 +1,21 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74279\SN74279.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/05/25 18:55:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U2-Pad3_ d_nand
+X1 Net-_U2-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U8-Pad1_ 3_and
+U8 Net-_U8-Pad1_ Net-_U1-Pad4_ d_inverter
+U3 Net-_U1-Pad5_ Net-_U1-Pad7_ Net-_U3-Pad3_ d_nand
+U4 Net-_U3-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad7_ d_nand
+U5 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U5-Pad3_ d_nand
+X2 Net-_U5-Pad3_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U9-Pad1_ 3_and
+U9 Net-_U9-Pad1_ Net-_U1-Pad9_ d_inverter
+U6 Net-_U1-Pad14_ Net-_U1-Pad13_ Net-_U6-Pad3_ d_nand
+U7 Net-_U6-Pad3_ Net-_U1-Pad15_ Net-_U1-Pad13_ d_nand
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74279/SN74279.cir.out b/library/SubcircuitLibrary/SN74279/SN74279.cir.out
new file mode 100644
index 000000000..534e59b45
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/SN74279.cir.out
@@ -0,0 +1,47 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74279\sn74279.cir
+
+.include 3_and.sub
+* u2 net-_u1-pad1_ net-_u1-pad4_ net-_u2-pad3_ d_nand
+x1 net-_u2-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u8-pad1_ 3_and
+* u8 net-_u8-pad1_ net-_u1-pad4_ d_inverter
+* u3 net-_u1-pad5_ net-_u1-pad7_ net-_u3-pad3_ d_nand
+* u4 net-_u3-pad3_ net-_u1-pad6_ net-_u1-pad7_ d_nand
+* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u5-pad3_ d_nand
+x2 net-_u5-pad3_ net-_u1-pad11_ net-_u1-pad12_ net-_u9-pad1_ 3_and
+* u9 net-_u9-pad1_ net-_u1-pad9_ d_inverter
+* u6 net-_u1-pad14_ net-_u1-pad13_ net-_u6-pad3_ d_nand
+* u7 net-_u6-pad3_ net-_u1-pad15_ net-_u1-pad13_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
+a1 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u2-pad3_ u2
+a2 net-_u8-pad1_ net-_u1-pad4_ u8
+a3 [net-_u1-pad5_ net-_u1-pad7_ ] net-_u3-pad3_ u3
+a4 [net-_u3-pad3_ net-_u1-pad6_ ] net-_u1-pad7_ u4
+a5 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u5-pad3_ u5
+a6 net-_u9-pad1_ net-_u1-pad9_ u9
+a7 [net-_u1-pad14_ net-_u1-pad13_ ] net-_u6-pad3_ u6
+a8 [net-_u6-pad3_ net-_u1-pad15_ ] net-_u1-pad13_ u7
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74279/SN74279.pro b/library/SubcircuitLibrary/SN74279/SN74279.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/SN74279.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74279/SN74279.sch b/library/SubcircuitLibrary/SN74279/SN74279.sch
new file mode 100644
index 000000000..9f5ebe03e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/SN74279.sch
@@ -0,0 +1,440 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nand U2
+U 1 1 6841981C
+P 4200 1250
+F 0 "U2" H 4200 1250 60 0000 C CNN
+F 1 "d_nand" H 4250 1350 60 0000 C CNN
+F 2 "" H 4200 1250 60 0000 C CNN
+F 3 "" H 4200 1250 60 0000 C CNN
+ 1 4200 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 6841985F
+P 4150 1850
+F 0 "X1" H 4250 1800 60 0000 C CNN
+F 1 "3_and" H 4300 2000 60 0000 C CNN
+F 2 "" H 4150 1850 60 0000 C CNN
+F 3 "" H 4150 1850 60 0000 C CNN
+ 1 4150 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 68419888
+P 5000 1800
+F 0 "U8" H 5000 1700 60 0000 C CNN
+F 1 "d_inverter" H 5000 1950 60 0000 C CNN
+F 2 "" H 5050 1750 60 0000 C CNN
+F 3 "" H 5050 1750 60 0000 C CNN
+ 1 5000 1800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4650 1800 4700 1800
+Wire Wire Line
+ 3750 1250 3750 1450
+Wire Wire Line
+ 3750 1450 5550 1450
+Wire Wire Line
+ 5550 1450 5550 1800
+Wire Wire Line
+ 5300 1800 5800 1800
+Wire Wire Line
+ 3800 1700 3800 1500
+Wire Wire Line
+ 3800 1500 4850 1500
+Wire Wire Line
+ 4850 1500 4850 1200
+Wire Wire Line
+ 4850 1200 4650 1200
+$Comp
+L d_nand U3
+U 1 1 684198D9
+P 4250 2500
+F 0 "U3" H 4250 2500 60 0000 C CNN
+F 1 "d_nand" H 4300 2600 60 0000 C CNN
+F 2 "" H 4250 2500 60 0000 C CNN
+F 3 "" H 4250 2500 60 0000 C CNN
+ 1 4250 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 68419903
+P 4250 3050
+F 0 "U4" H 4250 3050 60 0000 C CNN
+F 1 "d_nand" H 4300 3150 60 0000 C CNN
+F 2 "" H 4250 3050 60 0000 C CNN
+F 3 "" H 4250 3050 60 0000 C CNN
+ 1 4250 3050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3800 2500 3800 2700
+Wire Wire Line
+ 3800 2700 5050 2700
+Wire Wire Line
+ 5050 2700 5050 3000
+Wire Wire Line
+ 4700 3000 5800 3000
+Wire Wire Line
+ 3800 2950 3800 2750
+Wire Wire Line
+ 3800 2750 4850 2750
+Wire Wire Line
+ 4850 2750 4850 2450
+Wire Wire Line
+ 4850 2450 4700 2450
+$Comp
+L d_nand U5
+U 1 1 68419BA1
+P 4300 3700
+F 0 "U5" H 4300 3700 60 0000 C CNN
+F 1 "d_nand" H 4350 3800 60 0000 C CNN
+F 2 "" H 4300 3700 60 0000 C CNN
+F 3 "" H 4300 3700 60 0000 C CNN
+ 1 4300 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 68419BA7
+P 4250 4300
+F 0 "X2" H 4350 4250 60 0000 C CNN
+F 1 "3_and" H 4400 4450 60 0000 C CNN
+F 2 "" H 4250 4300 60 0000 C CNN
+F 3 "" H 4250 4300 60 0000 C CNN
+ 1 4250 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 68419BAD
+P 5100 4250
+F 0 "U9" H 5100 4150 60 0000 C CNN
+F 1 "d_inverter" H 5100 4400 60 0000 C CNN
+F 2 "" H 5150 4200 60 0000 C CNN
+F 3 "" H 5150 4200 60 0000 C CNN
+ 1 5100 4250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4750 4250 4800 4250
+Wire Wire Line
+ 3850 3700 3850 3900
+Wire Wire Line
+ 3850 3900 5650 3900
+Wire Wire Line
+ 5650 3900 5650 4250
+Wire Wire Line
+ 5400 4250 5850 4250
+Wire Wire Line
+ 3900 4150 3900 3950
+Wire Wire Line
+ 3900 3950 4950 3950
+Wire Wire Line
+ 4950 3950 4950 3650
+Wire Wire Line
+ 4950 3650 4750 3650
+$Comp
+L d_nand U6
+U 1 1 68419CF4
+P 4400 5050
+F 0 "U6" H 4400 5050 60 0000 C CNN
+F 1 "d_nand" H 4450 5150 60 0000 C CNN
+F 2 "" H 4400 5050 60 0000 C CNN
+F 3 "" H 4400 5050 60 0000 C CNN
+ 1 4400 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U7
+U 1 1 68419CFA
+P 4400 5600
+F 0 "U7" H 4400 5600 60 0000 C CNN
+F 1 "d_nand" H 4450 5700 60 0000 C CNN
+F 2 "" H 4400 5600 60 0000 C CNN
+F 3 "" H 4400 5600 60 0000 C CNN
+ 1 4400 5600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3950 5050 3950 5250
+Wire Wire Line
+ 3950 5250 5200 5250
+Wire Wire Line
+ 5200 5250 5200 5550
+Wire Wire Line
+ 4850 5550 5850 5550
+Wire Wire Line
+ 3950 5500 3950 5300
+Wire Wire Line
+ 3950 5300 5000 5300
+Wire Wire Line
+ 5000 5300 5000 5000
+Wire Wire Line
+ 5000 5000 4850 5000
+$Comp
+L PORT U1
+U 8 1 6841A17E
+P 6700 1250
+F 0 "U1" H 6750 1350 30 0000 C CNN
+F 1 "PORT" H 6700 1250 30 0000 C CNN
+F 2 "" H 6700 1250 60 0000 C CNN
+F 3 "" H 6700 1250 60 0000 C CNN
+ 8 6700 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6841A1E5
+P 3250 4400
+F 0 "U1" H 3300 4500 30 0000 C CNN
+F 1 "PORT" H 3250 4400 30 0000 C CNN
+F 2 "" H 3250 4400 60 0000 C CNN
+F 3 "" H 3250 4400 60 0000 C CNN
+ 12 3250 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6841A216
+P 6100 5550
+F 0 "U1" H 6150 5650 30 0000 C CNN
+F 1 "PORT" H 6100 5550 30 0000 C CNN
+F 2 "" H 6100 5550 60 0000 C CNN
+F 3 "" H 6100 5550 60 0000 C CNN
+ 13 6100 5550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 6841A245
+P 3250 5600
+F 0 "U1" H 3300 5700 30 0000 C CNN
+F 1 "PORT" H 3250 5600 30 0000 C CNN
+F 2 "" H 3250 5600 60 0000 C CNN
+F 3 "" H 3250 5600 60 0000 C CNN
+ 15 3250 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6841A276
+P 3200 1800
+F 0 "U1" H 3250 1900 30 0000 C CNN
+F 1 "PORT" H 3200 1800 30 0000 C CNN
+F 2 "" H 3200 1800 60 0000 C CNN
+F 3 "" H 3200 1800 60 0000 C CNN
+ 2 3200 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6841A2B7
+P 3200 3600
+F 0 "U1" H 3250 3700 30 0000 C CNN
+F 1 "PORT" H 3200 3600 30 0000 C CNN
+F 2 "" H 3200 3600 60 0000 C CNN
+F 3 "" H 3200 3600 60 0000 C CNN
+ 10 3200 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6841A2F4
+P 3200 1950
+F 0 "U1" H 3250 2050 30 0000 C CNN
+F 1 "PORT" H 3200 1950 30 0000 C CNN
+F 2 "" H 3200 1950 60 0000 C CNN
+F 3 "" H 3200 1950 60 0000 C CNN
+ 3 3200 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6841A33F
+P 6100 4250
+F 0 "U1" H 6150 4350 30 0000 C CNN
+F 1 "PORT" H 6100 4250 30 0000 C CNN
+F 2 "" H 6100 4250 60 0000 C CNN
+F 3 "" H 6100 4250 60 0000 C CNN
+ 9 6100 4250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6841A384
+P 6050 1800
+F 0 "U1" H 6100 1900 30 0000 C CNN
+F 1 "PORT" H 6050 1800 30 0000 C CNN
+F 2 "" H 6050 1800 60 0000 C CNN
+F 3 "" H 6050 1800 60 0000 C CNN
+ 4 6050 1800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6841A3C9
+P 3200 1150
+F 0 "U1" H 3250 1250 30 0000 C CNN
+F 1 "PORT" H 3200 1150 30 0000 C CNN
+F 2 "" H 3200 1150 60 0000 C CNN
+F 3 "" H 3200 1150 60 0000 C CNN
+ 1 3200 1150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6841A414
+P 3200 2400
+F 0 "U1" H 3250 2500 30 0000 C CNN
+F 1 "PORT" H 3200 2400 30 0000 C CNN
+F 2 "" H 3200 2400 60 0000 C CNN
+F 3 "" H 3200 2400 60 0000 C CNN
+ 5 3200 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6841A45D
+P 3200 3050
+F 0 "U1" H 3250 3150 30 0000 C CNN
+F 1 "PORT" H 3200 3050 30 0000 C CNN
+F 2 "" H 3200 3050 60 0000 C CNN
+F 3 "" H 3200 3050 60 0000 C CNN
+ 6 3200 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6841A4A8
+P 6050 3000
+F 0 "U1" H 6100 3100 30 0000 C CNN
+F 1 "PORT" H 6050 3000 30 0000 C CNN
+F 2 "" H 6050 3000 60 0000 C CNN
+F 3 "" H 6050 3000 60 0000 C CNN
+ 7 6050 3000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6841A4F7
+P 3250 4950
+F 0 "U1" H 3300 5050 30 0000 C CNN
+F 1 "PORT" H 3250 4950 30 0000 C CNN
+F 2 "" H 3250 4950 60 0000 C CNN
+F 3 "" H 3250 4950 60 0000 C CNN
+ 14 3250 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6841A53C
+P 3250 4250
+F 0 "U1" H 3300 4350 30 0000 C CNN
+F 1 "PORT" H 3250 4250 30 0000 C CNN
+F 2 "" H 3250 4250 60 0000 C CNN
+F 3 "" H 3250 4250 60 0000 C CNN
+ 11 3250 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 6841A59F
+P 6700 1450
+F 0 "U1" H 6750 1550 30 0000 C CNN
+F 1 "PORT" H 6700 1450 30 0000 C CNN
+F 2 "" H 6700 1450 60 0000 C CNN
+F 3 "" H 6700 1450 60 0000 C CNN
+ 16 6700 1450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3450 1150 3750 1150
+Wire Wire Line
+ 3450 1800 3800 1800
+Wire Wire Line
+ 3450 1950 3800 1950
+Wire Wire Line
+ 3800 1950 3800 1900
+Wire Wire Line
+ 3450 2400 3800 2400
+Wire Wire Line
+ 3450 3050 3800 3050
+Wire Wire Line
+ 3450 3600 3850 3600
+Wire Wire Line
+ 3500 4250 3900 4250
+Wire Wire Line
+ 3500 4400 3900 4400
+Wire Wire Line
+ 3900 4400 3900 4350
+Wire Wire Line
+ 3500 4950 3950 4950
+Wire Wire Line
+ 3500 5600 3950 5600
+Connection ~ 5200 5550
+Connection ~ 5650 4250
+Connection ~ 5050 3000
+Connection ~ 5550 1800
+NoConn ~ 6950 1250
+NoConn ~ 6950 1450
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74279/SN74279.sub b/library/SubcircuitLibrary/SN74279/SN74279.sub
new file mode 100644
index 000000000..5443375e5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/SN74279.sub
@@ -0,0 +1,41 @@
+* Subcircuit SN74279
+.subckt SN74279 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ?
+* c:\fossee\esim\library\subcircuitlibrary\sn74279\sn74279.cir
+.include 3_and.sub
+* u2 net-_u1-pad1_ net-_u1-pad4_ net-_u2-pad3_ d_nand
+x1 net-_u2-pad3_ net-_u1-pad2_ net-_u1-pad3_ net-_u8-pad1_ 3_and
+* u8 net-_u8-pad1_ net-_u1-pad4_ d_inverter
+* u3 net-_u1-pad5_ net-_u1-pad7_ net-_u3-pad3_ d_nand
+* u4 net-_u3-pad3_ net-_u1-pad6_ net-_u1-pad7_ d_nand
+* u5 net-_u1-pad10_ net-_u1-pad9_ net-_u5-pad3_ d_nand
+x2 net-_u5-pad3_ net-_u1-pad11_ net-_u1-pad12_ net-_u9-pad1_ 3_and
+* u9 net-_u9-pad1_ net-_u1-pad9_ d_inverter
+* u6 net-_u1-pad14_ net-_u1-pad13_ net-_u6-pad3_ d_nand
+* u7 net-_u6-pad3_ net-_u1-pad15_ net-_u1-pad13_ d_nand
+a1 [net-_u1-pad1_ net-_u1-pad4_ ] net-_u2-pad3_ u2
+a2 net-_u8-pad1_ net-_u1-pad4_ u8
+a3 [net-_u1-pad5_ net-_u1-pad7_ ] net-_u3-pad3_ u3
+a4 [net-_u3-pad3_ net-_u1-pad6_ ] net-_u1-pad7_ u4
+a5 [net-_u1-pad10_ net-_u1-pad9_ ] net-_u5-pad3_ u5
+a6 net-_u9-pad1_ net-_u1-pad9_ u9
+a7 [net-_u1-pad14_ net-_u1-pad13_ ] net-_u6-pad3_ u6
+a8 [net-_u6-pad3_ net-_u1-pad15_ ] net-_u1-pad13_ u7
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74279
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74279/SN74279_Previous_Values.xml b/library/SubcircuitLibrary/SN74279/SN74279_Previous_Values.xml
new file mode 100644
index 000000000..2f2686b12
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/SN74279_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_inverterd_nandd_nandd_nandd_inverterd_nandd_nandC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74279/analysis b/library/SubcircuitLibrary/SN74279/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74279/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7482/3_and-cache.lib b/library/SubcircuitLibrary/SN7482/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7482/3_and.cir b/library/SubcircuitLibrary/SN7482/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7482/3_and.cir.out b/library/SubcircuitLibrary/SN7482/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7482/3_and.pro b/library/SubcircuitLibrary/SN7482/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN7482/3_and.sch b/library/SubcircuitLibrary/SN7482/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7482/3_and.sub b/library/SubcircuitLibrary/SN7482/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7482/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN7482/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7482/SN7482-cache.lib b/library/SubcircuitLibrary/SN7482/SN7482-cache.lib
new file mode 100644
index 000000000..339f033c7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/SN7482-cache.lib
@@ -0,0 +1,131 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7482/SN7482.cir b/library/SubcircuitLibrary/SN7482/SN7482.cir
new file mode 100644
index 000000000..8aaed7063
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/SN7482.cir
@@ -0,0 +1,38 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN7482\SN7482.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/25 08:56:10
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 /5 Net-_U12-Pad1_ Net-_U19-Pad1_ d_and
+U4 /2 Net-_U12-Pad1_ Net-_U19-Pad2_ d_and
+U5 /3 Net-_U12-Pad1_ Net-_U20-Pad1_ d_and
+X1 /5 /2 /3 Net-_U20-Pad2_ 3_and
+U6 /5 /2 Net-_U15-Pad1_ d_and
+U7 /5 /3 Net-_U15-Pad2_ d_and
+U8 /3 /2 Net-_U22-Pad2_ d_and
+U9 Net-_U12-Pad1_ /10 Net-_U16-Pad1_ d_and
+U10 Net-_U1-Pad2_ /10 Net-_U10-Pad3_ d_and
+U11 Net-_U11-Pad1_ /10 Net-_U11-Pad3_ d_and
+X2 Net-_U12-Pad1_ Net-_U1-Pad2_ Net-_U11-Pad1_ Net-_U17-Pad2_ 3_and
+U12 Net-_U12-Pad1_ Net-_U1-Pad2_ Net-_U12-Pad3_ d_and
+U13 Net-_U12-Pad1_ Net-_U11-Pad1_ Net-_U13-Pad3_ d_and
+U14 Net-_U1-Pad2_ Net-_U11-Pad1_ Net-_U14-Pad3_ d_and
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_or
+U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_or
+U24 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U24-Pad3_ d_nor
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_or
+U22 Net-_U15-Pad3_ Net-_U22-Pad2_ Net-_U12-Pad1_ d_nor
+U16 Net-_U16-Pad1_ Net-_U10-Pad3_ Net-_U16-Pad3_ d_or
+U17 Net-_U11-Pad3_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_or
+U21 Net-_U16-Pad3_ Net-_U17-Pad3_ /12 d_nor
+U18 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U18-Pad3_ d_or
+U23 Net-_U18-Pad3_ Net-_U14-Pad3_ /10 d_nor
+U25 Net-_U24-Pad3_ /1 d_inverter
+U2 /13 Net-_U11-Pad1_ d_inverter
+U1 /14 Net-_U1-Pad2_ d_inverter
+U26 /1 /2 /3 ? /5 ? ? ? ? /10 ? /12 /13 /14 PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7482/SN7482.cir.out b/library/SubcircuitLibrary/SN7482/SN7482.cir.out
new file mode 100644
index 000000000..a677d1c7c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/SN7482.cir.out
@@ -0,0 +1,115 @@
+* d:\fossee\esim\library\subcircuitlibrary\sn7482\sn7482.cir
+
+.include 3_and.sub
+* u3 /5 net-_u12-pad1_ net-_u19-pad1_ d_and
+* u4 /2 net-_u12-pad1_ net-_u19-pad2_ d_and
+* u5 /3 net-_u12-pad1_ net-_u20-pad1_ d_and
+x1 /5 /2 /3 net-_u20-pad2_ 3_and
+* u6 /5 /2 net-_u15-pad1_ d_and
+* u7 /5 /3 net-_u15-pad2_ d_and
+* u8 /3 /2 net-_u22-pad2_ d_and
+* u9 net-_u12-pad1_ /10 net-_u16-pad1_ d_and
+* u10 net-_u1-pad2_ /10 net-_u10-pad3_ d_and
+* u11 net-_u11-pad1_ /10 net-_u11-pad3_ d_and
+x2 net-_u12-pad1_ net-_u1-pad2_ net-_u11-pad1_ net-_u17-pad2_ 3_and
+* u12 net-_u12-pad1_ net-_u1-pad2_ net-_u12-pad3_ d_and
+* u13 net-_u12-pad1_ net-_u11-pad1_ net-_u13-pad3_ d_and
+* u14 net-_u1-pad2_ net-_u11-pad1_ net-_u14-pad3_ d_and
+* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_or
+* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_or
+* u24 net-_u19-pad3_ net-_u20-pad3_ net-_u24-pad3_ d_nor
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u22 net-_u15-pad3_ net-_u22-pad2_ net-_u12-pad1_ d_nor
+* u16 net-_u16-pad1_ net-_u10-pad3_ net-_u16-pad3_ d_or
+* u17 net-_u11-pad3_ net-_u17-pad2_ net-_u17-pad3_ d_or
+* u21 net-_u16-pad3_ net-_u17-pad3_ /12 d_nor
+* u18 net-_u12-pad3_ net-_u13-pad3_ net-_u18-pad3_ d_or
+* u23 net-_u18-pad3_ net-_u14-pad3_ /10 d_nor
+* u25 net-_u24-pad3_ /1 d_inverter
+* u2 /13 net-_u11-pad1_ d_inverter
+* u1 /14 net-_u1-pad2_ d_inverter
+* u26 /1 /2 /3 ? /5 ? ? ? ? /10 ? /12 /13 /14 port
+a1 [/5 net-_u12-pad1_ ] net-_u19-pad1_ u3
+a2 [/2 net-_u12-pad1_ ] net-_u19-pad2_ u4
+a3 [/3 net-_u12-pad1_ ] net-_u20-pad1_ u5
+a4 [/5 /2 ] net-_u15-pad1_ u6
+a5 [/5 /3 ] net-_u15-pad2_ u7
+a6 [/3 /2 ] net-_u22-pad2_ u8
+a7 [net-_u12-pad1_ /10 ] net-_u16-pad1_ u9
+a8 [net-_u1-pad2_ /10 ] net-_u10-pad3_ u10
+a9 [net-_u11-pad1_ /10 ] net-_u11-pad3_ u11
+a10 [net-_u12-pad1_ net-_u1-pad2_ ] net-_u12-pad3_ u12
+a11 [net-_u12-pad1_ net-_u11-pad1_ ] net-_u13-pad3_ u13
+a12 [net-_u1-pad2_ net-_u11-pad1_ ] net-_u14-pad3_ u14
+a13 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a14 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a15 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u24-pad3_ u24
+a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a17 [net-_u15-pad3_ net-_u22-pad2_ ] net-_u12-pad1_ u22
+a18 [net-_u16-pad1_ net-_u10-pad3_ ] net-_u16-pad3_ u16
+a19 [net-_u11-pad3_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a20 [net-_u16-pad3_ net-_u17-pad3_ ] /12 u21
+a21 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u18-pad3_ u18
+a22 [net-_u18-pad3_ net-_u14-pad3_ ] /10 u23
+a23 net-_u24-pad3_ /1 u25
+a24 /13 net-_u11-pad1_ u2
+a25 /14 net-_u1-pad2_ u1
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7482/SN7482.pro b/library/SubcircuitLibrary/SN7482/SN7482.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/SN7482.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN7482/SN7482.sch b/library/SubcircuitLibrary/SN7482/SN7482.sch
new file mode 100644
index 000000000..14f55b344
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/SN7482.sch
@@ -0,0 +1,754 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U3
+U 1 1 68430FAC
+P 5050 1050
+F 0 "U3" H 5050 1050 60 0000 C CNN
+F 1 "d_and" H 5100 1150 60 0000 C CNN
+F 2 "" H 5050 1050 60 0000 C CNN
+F 3 "" H 5050 1050 60 0000 C CNN
+ 1 5050 1050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 684310EA
+P 5050 1350
+F 0 "U4" H 5050 1350 60 0000 C CNN
+F 1 "d_and" H 5100 1450 60 0000 C CNN
+F 2 "" H 5050 1350 60 0000 C CNN
+F 3 "" H 5050 1350 60 0000 C CNN
+ 1 5050 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 68431109
+P 5050 1650
+F 0 "U5" H 5050 1650 60 0000 C CNN
+F 1 "d_and" H 5100 1750 60 0000 C CNN
+F 2 "" H 5050 1650 60 0000 C CNN
+F 3 "" H 5050 1650 60 0000 C CNN
+ 1 5050 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 68431114
+P 4950 2050
+F 0 "X1" H 5050 2000 60 0000 C CNN
+F 1 "3_and" H 5100 2200 60 0000 C CNN
+F 2 "" H 4950 2050 60 0000 C CNN
+F 3 "" H 4950 2050 60 0000 C CNN
+ 1 4950 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 684311E6
+P 5050 2650
+F 0 "U6" H 5050 2650 60 0000 C CNN
+F 1 "d_and" H 5100 2750 60 0000 C CNN
+F 2 "" H 5050 2650 60 0000 C CNN
+F 3 "" H 5050 2650 60 0000 C CNN
+ 1 5050 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U7
+U 1 1 684311EC
+P 5050 2950
+F 0 "U7" H 5050 2950 60 0000 C CNN
+F 1 "d_and" H 5100 3050 60 0000 C CNN
+F 2 "" H 5050 2950 60 0000 C CNN
+F 3 "" H 5050 2950 60 0000 C CNN
+ 1 5050 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U8
+U 1 1 684311F2
+P 5050 3250
+F 0 "U8" H 5050 3250 60 0000 C CNN
+F 1 "d_and" H 5100 3350 60 0000 C CNN
+F 2 "" H 5050 3250 60 0000 C CNN
+F 3 "" H 5050 3250 60 0000 C CNN
+ 1 5050 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U9
+U 1 1 68431293
+P 5050 3850
+F 0 "U9" H 5050 3850 60 0000 C CNN
+F 1 "d_and" H 5100 3950 60 0000 C CNN
+F 2 "" H 5050 3850 60 0000 C CNN
+F 3 "" H 5050 3850 60 0000 C CNN
+ 1 5050 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U10
+U 1 1 68431299
+P 5050 4150
+F 0 "U10" H 5050 4150 60 0000 C CNN
+F 1 "d_and" H 5100 4250 60 0000 C CNN
+F 2 "" H 5050 4150 60 0000 C CNN
+F 3 "" H 5050 4150 60 0000 C CNN
+ 1 5050 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U11
+U 1 1 6843129F
+P 5050 4450
+F 0 "U11" H 5050 4450 60 0000 C CNN
+F 1 "d_and" H 5100 4550 60 0000 C CNN
+F 2 "" H 5050 4450 60 0000 C CNN
+F 3 "" H 5050 4450 60 0000 C CNN
+ 1 5050 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 68431324
+P 4950 4850
+F 0 "X2" H 5050 4800 60 0000 C CNN
+F 1 "3_and" H 5100 5000 60 0000 C CNN
+F 2 "" H 4950 4850 60 0000 C CNN
+F 3 "" H 4950 4850 60 0000 C CNN
+ 1 4950 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 684313DF
+P 5050 5600
+F 0 "U12" H 5050 5600 60 0000 C CNN
+F 1 "d_and" H 5100 5700 60 0000 C CNN
+F 2 "" H 5050 5600 60 0000 C CNN
+F 3 "" H 5050 5600 60 0000 C CNN
+ 1 5050 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 684313E5
+P 5050 5900
+F 0 "U13" H 5050 5900 60 0000 C CNN
+F 1 "d_and" H 5100 6000 60 0000 C CNN
+F 2 "" H 5050 5900 60 0000 C CNN
+F 3 "" H 5050 5900 60 0000 C CNN
+ 1 5050 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 684313EB
+P 5050 6200
+F 0 "U14" H 5050 6200 60 0000 C CNN
+F 1 "d_and" H 5100 6300 60 0000 C CNN
+F 2 "" H 5050 6200 60 0000 C CNN
+F 3 "" H 5050 6200 60 0000 C CNN
+ 1 5050 6200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U19
+U 1 1 6843300B
+P 6450 1200
+F 0 "U19" H 6450 1200 60 0000 C CNN
+F 1 "d_or" H 6450 1300 60 0000 C CNN
+F 2 "" H 6450 1200 60 0000 C CNN
+F 3 "" H 6450 1200 60 0000 C CNN
+ 1 6450 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U20
+U 1 1 684330D8
+P 6450 1850
+F 0 "U20" H 6450 1850 60 0000 C CNN
+F 1 "d_or" H 6450 1950 60 0000 C CNN
+F 2 "" H 6450 1850 60 0000 C CNN
+F 3 "" H 6450 1850 60 0000 C CNN
+ 1 6450 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U24
+U 1 1 684330F0
+P 7750 1450
+F 0 "U24" H 7750 1450 60 0000 C CNN
+F 1 "d_nor" H 7800 1550 60 0000 C CNN
+F 2 "" H 7750 1450 60 0000 C CNN
+F 3 "" H 7750 1450 60 0000 C CNN
+ 1 7750 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U15
+U 1 1 68433CA7
+P 6350 2800
+F 0 "U15" H 6350 2800 60 0000 C CNN
+F 1 "d_or" H 6350 2900 60 0000 C CNN
+F 2 "" H 6350 2800 60 0000 C CNN
+F 3 "" H 6350 2800 60 0000 C CNN
+ 1 6350 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U22
+U 1 1 68433D40
+P 7550 2850
+F 0 "U22" H 7550 2850 60 0000 C CNN
+F 1 "d_nor" H 7600 2950 60 0000 C CNN
+F 2 "" H 7550 2850 60 0000 C CNN
+F 3 "" H 7550 2850 60 0000 C CNN
+ 1 7550 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U16
+U 1 1 68434EA1
+P 6350 4000
+F 0 "U16" H 6350 4000 60 0000 C CNN
+F 1 "d_or" H 6350 4100 60 0000 C CNN
+F 2 "" H 6350 4000 60 0000 C CNN
+F 3 "" H 6350 4000 60 0000 C CNN
+ 1 6350 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U17
+U 1 1 68435248
+P 6350 4650
+F 0 "U17" H 6350 4650 60 0000 C CNN
+F 1 "d_or" H 6350 4750 60 0000 C CNN
+F 2 "" H 6350 4650 60 0000 C CNN
+F 3 "" H 6350 4650 60 0000 C CNN
+ 1 6350 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U21
+U 1 1 68435A61
+P 7500 4300
+F 0 "U21" H 7500 4300 60 0000 C CNN
+F 1 "d_nor" H 7550 4400 60 0000 C CNN
+F 2 "" H 7500 4300 60 0000 C CNN
+F 3 "" H 7500 4300 60 0000 C CNN
+ 1 7500 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U18
+U 1 1 68436162
+P 6400 5700
+F 0 "U18" H 6400 5700 60 0000 C CNN
+F 1 "d_or" H 6400 5800 60 0000 C CNN
+F 2 "" H 6400 5700 60 0000 C CNN
+F 3 "" H 6400 5700 60 0000 C CNN
+ 1 6400 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U23
+U 1 1 68436248
+P 7550 5900
+F 0 "U23" H 7550 5900 60 0000 C CNN
+F 1 "d_nor" H 7600 6000 60 0000 C CNN
+F 2 "" H 7550 5900 60 0000 C CNN
+F 3 "" H 7550 5900 60 0000 C CNN
+ 1 7550 5900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U25
+U 1 1 68437AE2
+P 8750 1400
+F 0 "U25" H 8750 1300 60 0000 C CNN
+F 1 "d_inverter" H 8750 1550 60 0000 C CNN
+F 2 "" H 8800 1350 60 0000 C CNN
+F 3 "" H 8800 1350 60 0000 C CNN
+ 1 8750 1400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5500 1000 5800 1000
+Wire Wire Line
+ 5800 1000 5800 1100
+Wire Wire Line
+ 5800 1100 6000 1100
+Wire Wire Line
+ 5800 1300 5500 1300
+Wire Wire Line
+ 5800 1200 5800 1300
+Wire Wire Line
+ 5800 1200 6000 1200
+Wire Wire Line
+ 5500 1600 5750 1600
+Wire Wire Line
+ 5750 1600 5750 1750
+Wire Wire Line
+ 5750 1750 6000 1750
+Wire Wire Line
+ 5450 2000 5750 2000
+Wire Wire Line
+ 5750 2000 5750 1850
+Wire Wire Line
+ 5750 1850 6000 1850
+Wire Wire Line
+ 6900 1150 6900 1350
+Wire Wire Line
+ 6900 1350 7300 1350
+Wire Wire Line
+ 6900 1800 6900 1450
+Wire Wire Line
+ 6900 1450 7300 1450
+Wire Wire Line
+ 5500 2600 5700 2600
+Wire Wire Line
+ 5700 2600 5700 2700
+Wire Wire Line
+ 5700 2700 5900 2700
+Wire Wire Line
+ 5500 2900 5700 2900
+Wire Wire Line
+ 5700 2900 5700 2800
+Wire Wire Line
+ 5700 2800 5900 2800
+Wire Wire Line
+ 6800 2750 7100 2750
+Wire Wire Line
+ 5500 3200 6850 3200
+Wire Wire Line
+ 6850 3200 6850 2850
+Wire Wire Line
+ 6850 2850 7100 2850
+Wire Wire Line
+ 5500 3800 5650 3800
+Wire Wire Line
+ 5650 3800 5650 3900
+Wire Wire Line
+ 5650 3900 5900 3900
+Wire Wire Line
+ 5500 4100 5650 4100
+Wire Wire Line
+ 5650 4100 5650 4000
+Wire Wire Line
+ 5650 4000 5900 4000
+Wire Wire Line
+ 5500 4400 5700 4400
+Wire Wire Line
+ 5700 4400 5700 4550
+Wire Wire Line
+ 5700 4550 5900 4550
+Wire Wire Line
+ 5450 4800 5700 4800
+Wire Wire Line
+ 5700 4800 5700 4650
+Wire Wire Line
+ 5700 4650 5900 4650
+Wire Wire Line
+ 6800 3950 6800 4200
+Wire Wire Line
+ 6800 4200 7050 4200
+Wire Wire Line
+ 6800 4600 6800 4300
+Wire Wire Line
+ 6800 4300 7050 4300
+Wire Wire Line
+ 5500 5550 5700 5550
+Wire Wire Line
+ 5700 5550 5700 5600
+Wire Wire Line
+ 5700 5600 5950 5600
+Wire Wire Line
+ 5500 5850 5700 5850
+Wire Wire Line
+ 5700 5850 5700 5700
+Wire Wire Line
+ 5700 5700 5950 5700
+Wire Wire Line
+ 6850 5650 6850 5800
+Wire Wire Line
+ 6850 5800 7100 5800
+Wire Wire Line
+ 5500 6150 6750 6150
+Wire Wire Line
+ 6750 6150 6750 5900
+Wire Wire Line
+ 6750 5900 7100 5900
+Wire Wire Line
+ 8000 5850 8500 5850
+Wire Wire Line
+ 7950 4250 8750 4250
+Wire Wire Line
+ 8200 1400 8450 1400
+Wire Wire Line
+ 9050 1400 9300 1400
+Wire Wire Line
+ 3200 950 4600 950
+Wire Wire Line
+ 8000 2800 8450 2800
+Wire Wire Line
+ 8450 2800 8450 3600
+Wire Wire Line
+ 8450 3600 4000 3600
+Wire Wire Line
+ 4000 1050 4000 5800
+Wire Wire Line
+ 4000 1050 4600 1050
+Wire Wire Line
+ 3200 1250 4600 1250
+Wire Wire Line
+ 3200 1550 4600 1550
+Wire Wire Line
+ 4600 1350 4000 1350
+Connection ~ 4000 1350
+Wire Wire Line
+ 4600 1650 4000 1650
+Connection ~ 4000 1650
+Wire Wire Line
+ 4350 2850 4600 2850
+Wire Wire Line
+ 4350 950 4350 2850
+Connection ~ 4350 950
+Wire Wire Line
+ 4600 1900 4350 1900
+Connection ~ 4350 1900
+Wire Wire Line
+ 4100 1250 4100 3250
+Wire Wire Line
+ 4100 2000 4600 2000
+Connection ~ 4100 1250
+Wire Wire Line
+ 4600 2100 3550 2100
+Wire Wire Line
+ 3550 1550 3550 3150
+Connection ~ 3550 1550
+Wire Wire Line
+ 4600 2550 4350 2550
+Connection ~ 4350 2550
+Wire Wire Line
+ 4100 2650 4600 2650
+Connection ~ 4100 2000
+Wire Wire Line
+ 3550 2950 4600 2950
+Connection ~ 3550 2100
+Wire Wire Line
+ 4100 3250 4600 3250
+Connection ~ 4100 2650
+Wire Wire Line
+ 3550 3150 4600 3150
+Connection ~ 3550 2950
+Wire Wire Line
+ 4000 3750 4600 3750
+Connection ~ 4000 3600
+Wire Wire Line
+ 4600 3850 4300 3850
+Wire Wire Line
+ 4300 3850 4300 5100
+Wire Wire Line
+ 4300 5100 8200 5100
+Wire Wire Line
+ 8200 5100 8200 5850
+Connection ~ 8200 5850
+Wire Wire Line
+ 4600 4050 4150 4050
+Wire Wire Line
+ 4150 4050 4150 6100
+Wire Wire Line
+ 4150 6100 4600 6100
+Wire Wire Line
+ 4600 4150 4300 4150
+Connection ~ 4300 4150
+Wire Wire Line
+ 3300 4350 4600 4350
+Wire Wire Line
+ 4600 4450 4300 4450
+Connection ~ 4300 4450
+Wire Wire Line
+ 4000 4700 4600 4700
+Connection ~ 4000 3750
+Wire Wire Line
+ 3150 4800 4600 4800
+Connection ~ 4150 4800
+Wire Wire Line
+ 3800 4350 3800 6200
+Wire Wire Line
+ 3800 6200 4600 6200
+Connection ~ 3800 4350
+Wire Wire Line
+ 4600 4900 3800 4900
+Connection ~ 3800 4900
+Wire Wire Line
+ 4600 5600 4150 5600
+Connection ~ 4150 5600
+Wire Wire Line
+ 4000 5800 4600 5800
+Connection ~ 4000 4700
+Wire Wire Line
+ 4600 5900 3800 5900
+Connection ~ 3800 5900
+Wire Wire Line
+ 4600 5500 4000 5500
+Connection ~ 4000 5500
+$Comp
+L d_inverter U2
+U 1 1 68440F50
+P 3000 4350
+F 0 "U2" H 3000 4250 60 0000 C CNN
+F 1 "d_inverter" H 3000 4500 60 0000 C CNN
+F 2 "" H 3050 4300 60 0000 C CNN
+F 3 "" H 3050 4300 60 0000 C CNN
+ 1 3000 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2400 4350 2700 4350
+$Comp
+L d_inverter U1
+U 1 1 684410EB
+P 2850 4800
+F 0 "U1" H 2850 4700 60 0000 C CNN
+F 1 "d_inverter" H 2850 4950 60 0000 C CNN
+F 2 "" H 2900 4750 60 0000 C CNN
+F 3 "" H 2900 4750 60 0000 C CNN
+ 1 2850 4800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2400 4800 2550 4800
+Text Label 2400 4800 0 60 ~ 0
+14
+Text Label 2400 4350 0 60 ~ 0
+13
+Text Label 3200 1550 0 60 ~ 0
+3
+Text Label 3200 1250 0 60 ~ 0
+2
+Text Label 3200 950 0 60 ~ 0
+5
+Text Label 9300 1400 0 60 ~ 0
+1
+Text Label 8750 4250 0 60 ~ 0
+12
+Text Label 8500 5850 0 60 ~ 0
+10
+$Comp
+L PORT U26
+U 3 1 6844A2B5
+P 2950 1550
+F 0 "U26" H 3000 1650 30 0000 C CNN
+F 1 "PORT" H 2950 1550 30 0000 C CNN
+F 2 "" H 2950 1550 60 0000 C CNN
+F 3 "" H 2950 1550 60 0000 C CNN
+ 3 2950 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 6 1 6844A352
+P 1850 2300
+F 0 "U26" H 1900 2400 30 0000 C CNN
+F 1 "PORT" H 1850 2300 30 0000 C CNN
+F 2 "" H 1850 2300 60 0000 C CNN
+F 3 "" H 1850 2300 60 0000 C CNN
+ 6 1850 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 10 1 6844A3A3
+P 8750 5850
+F 0 "U26" H 8800 5950 30 0000 C CNN
+F 1 "PORT" H 8750 5850 30 0000 C CNN
+F 2 "" H 8750 5850 60 0000 C CNN
+F 3 "" H 8750 5850 60 0000 C CNN
+ 10 8750 5850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U26
+U 14 1 6844A41A
+P 2150 4800
+F 0 "U26" H 2200 4900 30 0000 C CNN
+F 1 "PORT" H 2150 4800 30 0000 C CNN
+F 2 "" H 2150 4800 60 0000 C CNN
+F 3 "" H 2150 4800 60 0000 C CNN
+ 14 2150 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 1 1 6844A493
+P 9550 1400
+F 0 "U26" H 9600 1500 30 0000 C CNN
+F 1 "PORT" H 9550 1400 30 0000 C CNN
+F 2 "" H 9550 1400 60 0000 C CNN
+F 3 "" H 9550 1400 60 0000 C CNN
+ 1 9550 1400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U26
+U 7 1 6844A4F0
+P 1850 2550
+F 0 "U26" H 1900 2650 30 0000 C CNN
+F 1 "PORT" H 1850 2550 30 0000 C CNN
+F 2 "" H 1850 2550 60 0000 C CNN
+F 3 "" H 1850 2550 60 0000 C CNN
+ 7 1850 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 11 1 6844A54D
+P 2350 2550
+F 0 "U26" H 2400 2650 30 0000 C CNN
+F 1 "PORT" H 2350 2550 30 0000 C CNN
+F 2 "" H 2350 2550 60 0000 C CNN
+F 3 "" H 2350 2550 60 0000 C CNN
+ 11 2350 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 12 1 6844A5A6
+P 9000 4250
+F 0 "U26" H 9050 4350 30 0000 C CNN
+F 1 "PORT" H 9000 4250 30 0000 C CNN
+F 2 "" H 9000 4250 60 0000 C CNN
+F 3 "" H 9000 4250 60 0000 C CNN
+ 12 9000 4250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U26
+U 2 1 6844A601
+P 2950 1250
+F 0 "U26" H 3000 1350 30 0000 C CNN
+F 1 "PORT" H 2950 1250 30 0000 C CNN
+F 2 "" H 2950 1250 60 0000 C CNN
+F 3 "" H 2950 1250 60 0000 C CNN
+ 2 2950 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 5 1 6844A674
+P 2950 950
+F 0 "U26" H 3000 1050 30 0000 C CNN
+F 1 "PORT" H 2950 950 30 0000 C CNN
+F 2 "" H 2950 950 60 0000 C CNN
+F 3 "" H 2950 950 60 0000 C CNN
+ 5 2950 950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 9 1 6844A6D3
+P 2200 2850
+F 0 "U26" H 2250 2950 30 0000 C CNN
+F 1 "PORT" H 2200 2850 30 0000 C CNN
+F 2 "" H 2200 2850 60 0000 C CNN
+F 3 "" H 2200 2850 60 0000 C CNN
+ 9 2200 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 13 1 6844A734
+P 2150 4350
+F 0 "U26" H 2200 4450 30 0000 C CNN
+F 1 "PORT" H 2150 4350 30 0000 C CNN
+F 2 "" H 2150 4350 60 0000 C CNN
+F 3 "" H 2150 4350 60 0000 C CNN
+ 13 2150 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 4 1 6844A797
+P 1450 3050
+F 0 "U26" H 1500 3150 30 0000 C CNN
+F 1 "PORT" H 1450 3050 30 0000 C CNN
+F 2 "" H 1450 3050 60 0000 C CNN
+F 3 "" H 1450 3050 60 0000 C CNN
+ 4 1450 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U26
+U 8 1 6844A80A
+P 2000 3100
+F 0 "U26" H 2050 3200 30 0000 C CNN
+F 1 "PORT" H 2000 3100 30 0000 C CNN
+F 2 "" H 2000 3100 60 0000 C CNN
+F 3 "" H 2000 3100 60 0000 C CNN
+ 8 2000 3100
+ 1 0 0 -1
+$EndComp
+NoConn ~ 1700 3050
+NoConn ~ 2250 3100
+NoConn ~ 2450 2850
+NoConn ~ 2600 2550
+NoConn ~ 2100 2550
+NoConn ~ 2100 2300
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7482/SN7482.sub b/library/SubcircuitLibrary/SN7482/SN7482.sub
new file mode 100644
index 000000000..9668175ef
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/SN7482.sub
@@ -0,0 +1,109 @@
+* Subcircuit SN7482
+.subckt SN7482 /1 /2 /3 ? /5 ? ? ? ? /10 ? /12 /13 /14
+* d:\fossee\esim\library\subcircuitlibrary\sn7482\sn7482.cir
+.include 3_and.sub
+* u3 /5 net-_u12-pad1_ net-_u19-pad1_ d_and
+* u4 /2 net-_u12-pad1_ net-_u19-pad2_ d_and
+* u5 /3 net-_u12-pad1_ net-_u20-pad1_ d_and
+x1 /5 /2 /3 net-_u20-pad2_ 3_and
+* u6 /5 /2 net-_u15-pad1_ d_and
+* u7 /5 /3 net-_u15-pad2_ d_and
+* u8 /3 /2 net-_u22-pad2_ d_and
+* u9 net-_u12-pad1_ /10 net-_u16-pad1_ d_and
+* u10 net-_u1-pad2_ /10 net-_u10-pad3_ d_and
+* u11 net-_u11-pad1_ /10 net-_u11-pad3_ d_and
+x2 net-_u12-pad1_ net-_u1-pad2_ net-_u11-pad1_ net-_u17-pad2_ 3_and
+* u12 net-_u12-pad1_ net-_u1-pad2_ net-_u12-pad3_ d_and
+* u13 net-_u12-pad1_ net-_u11-pad1_ net-_u13-pad3_ d_and
+* u14 net-_u1-pad2_ net-_u11-pad1_ net-_u14-pad3_ d_and
+* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_or
+* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_or
+* u24 net-_u19-pad3_ net-_u20-pad3_ net-_u24-pad3_ d_nor
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u22 net-_u15-pad3_ net-_u22-pad2_ net-_u12-pad1_ d_nor
+* u16 net-_u16-pad1_ net-_u10-pad3_ net-_u16-pad3_ d_or
+* u17 net-_u11-pad3_ net-_u17-pad2_ net-_u17-pad3_ d_or
+* u21 net-_u16-pad3_ net-_u17-pad3_ /12 d_nor
+* u18 net-_u12-pad3_ net-_u13-pad3_ net-_u18-pad3_ d_or
+* u23 net-_u18-pad3_ net-_u14-pad3_ /10 d_nor
+* u25 net-_u24-pad3_ /1 d_inverter
+* u2 /13 net-_u11-pad1_ d_inverter
+* u1 /14 net-_u1-pad2_ d_inverter
+a1 [/5 net-_u12-pad1_ ] net-_u19-pad1_ u3
+a2 [/2 net-_u12-pad1_ ] net-_u19-pad2_ u4
+a3 [/3 net-_u12-pad1_ ] net-_u20-pad1_ u5
+a4 [/5 /2 ] net-_u15-pad1_ u6
+a5 [/5 /3 ] net-_u15-pad2_ u7
+a6 [/3 /2 ] net-_u22-pad2_ u8
+a7 [net-_u12-pad1_ /10 ] net-_u16-pad1_ u9
+a8 [net-_u1-pad2_ /10 ] net-_u10-pad3_ u10
+a9 [net-_u11-pad1_ /10 ] net-_u11-pad3_ u11
+a10 [net-_u12-pad1_ net-_u1-pad2_ ] net-_u12-pad3_ u12
+a11 [net-_u12-pad1_ net-_u11-pad1_ ] net-_u13-pad3_ u13
+a12 [net-_u1-pad2_ net-_u11-pad1_ ] net-_u14-pad3_ u14
+a13 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a14 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a15 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u24-pad3_ u24
+a16 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a17 [net-_u15-pad3_ net-_u22-pad2_ ] net-_u12-pad1_ u22
+a18 [net-_u16-pad1_ net-_u10-pad3_ ] net-_u16-pad3_ u16
+a19 [net-_u11-pad3_ net-_u17-pad2_ ] net-_u17-pad3_ u17
+a20 [net-_u16-pad3_ net-_u17-pad3_ ] /12 u21
+a21 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u18-pad3_ u18
+a22 [net-_u18-pad3_ net-_u14-pad3_ ] /10 u23
+a23 net-_u24-pad3_ /1 u25
+a24 /13 net-_u11-pad1_ u2
+a25 /14 net-_u1-pad2_ u1
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u24 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u23 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN7482
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7482/SN7482_Previous_Values.xml b/library/SubcircuitLibrary/SN7482/SN7482_Previous_Values.xml
new file mode 100644
index 000000000..3da4f386e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/SN7482_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_andd_ord_ord_nord_ord_nord_ord_ord_nord_ord_nord_inverterd_inverterd_inverterD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andD:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN7482/analysis b/library/SubcircuitLibrary/SN7482/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN7482/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ABT337/NAND_3-cache.lib b/library/SubcircuitLibrary/SN74ABT337/NAND_3-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/NAND_3-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ABT337/NAND_3.bak b/library/SubcircuitLibrary/SN74ABT337/NAND_3.bak
new file mode 100644
index 000000000..d9890c5d1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/NAND_3.bak
@@ -0,0 +1,287 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF360
+P 5550 2300
+F 0 "SC3" H 5600 2600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5850 2387 50 0000 R CNN
+F 2 "" H 5550 800 50 0001 C CNN
+F 3 "" H 5550 2300 50 0001 C CNN
+ 1 5550 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 684AF39D
+P 5550 3100
+F 0 "SC4" H 5600 3400 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5850 3187 50 0000 R CNN
+F 2 "" H 5550 1600 50 0001 C CNN
+F 3 "" H 5550 3100 50 0001 C CNN
+ 1 5550 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC5
+U 1 1 684AF420
+P 5950 3800
+F 0 "SC5" H 6000 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6250 3887 50 0000 R CNN
+F 2 "" H 5950 2300 50 0001 C CNN
+F 3 "" H 5950 3800 50 0001 C CNN
+ 1 5950 3800
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF50C
+P 4450 4700
+F 0 "SC1" H 4500 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4750 4787 50 0000 R CNN
+F 2 "" H 4450 3200 50 0001 C CNN
+F 3 "" H 4450 4700 50 0001 C CNN
+ 1 4450 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684AF577
+P 5500 4700
+F 0 "SC2" H 5550 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5800 4787 50 0000 R CNN
+F 2 "" H 5500 3200 50 0001 C CNN
+F 3 "" H 5500 4700 50 0001 C CNN
+ 1 5500 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 684AF5EC
+P 6450 4700
+F 0 "SC6" H 6500 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6750 4787 50 0000 R CNN
+F 2 "" H 6450 3200 50 0001 C CNN
+F 3 "" H 6450 4700 50 0001 C CNN
+ 1 6450 4700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF63F
+P 3700 4000
+F 0 "U1" H 3750 4100 30 0000 C CNN
+F 1 "PORT" H 3700 4000 30 0000 C CNN
+F 2 "" H 3700 4000 60 0000 C CNN
+F 3 "" H 3700 4000 60 0000 C CNN
+ 1 3700 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF6CC
+P 4850 3850
+F 0 "U1" H 4900 3950 30 0000 C CNN
+F 1 "PORT" H 4850 3850 30 0000 C CNN
+F 2 "" H 4850 3850 60 0000 C CNN
+F 3 "" H 4850 3850 60 0000 C CNN
+ 2 4850 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF829
+P 7050 3800
+F 0 "U1" H 7100 3900 30 0000 C CNN
+F 1 "PORT" H 7050 3800 30 0000 C CNN
+F 2 "" H 7050 3800 60 0000 C CNN
+F 3 "" H 7050 3800 60 0000 C CNN
+ 5 7050 3800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684AF94D
+P 7150 4200
+F 0 "U1" H 7200 4300 30 0000 C CNN
+F 1 "PORT" H 7150 4200 30 0000 C CNN
+F 2 "" H 7150 4200 60 0000 C CNN
+F 3 "" H 7150 4200 60 0000 C CNN
+ 6 7150 4200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF9FE
+P 5100 5200
+F 0 "U1" H 5150 5300 30 0000 C CNN
+F 1 "PORT" H 5100 5200 30 0000 C CNN
+F 2 "" H 5100 5200 60 0000 C CNN
+F 3 "" H 5100 5200 60 0000 C CNN
+ 3 5100 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AFAE6
+P 5500 1750
+F 0 "U1" H 5550 1850 30 0000 C CNN
+F 1 "PORT" H 5500 1750 30 0000 C CNN
+F 2 "" H 5500 1750 60 0000 C CNN
+F 3 "" H 5500 1750 60 0000 C CNN
+ 4 5500 1750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5650 2300 5800 2300
+Wire Wire Line
+ 5800 2300 5800 1950
+Wire Wire Line
+ 5800 1950 5750 1950
+Wire Wire Line
+ 5750 1750 5750 2000
+Connection ~ 5750 1950
+Wire Wire Line
+ 5750 2600 5750 2800
+Wire Wire Line
+ 5650 3100 5800 3100
+Wire Wire Line
+ 5800 3100 5800 2750
+Wire Wire Line
+ 5800 2750 5750 2750
+Connection ~ 5750 2750
+Wire Wire Line
+ 5750 3500 5750 3400
+Wire Wire Line
+ 5850 3800 5700 3800
+Wire Wire Line
+ 5700 3800 5700 3450
+Wire Wire Line
+ 5700 3450 5750 3450
+Connection ~ 5750 3450
+Wire Wire Line
+ 4650 4400 4650 4300
+Wire Wire Line
+ 4650 4300 6250 4300
+Wire Wire Line
+ 6250 4300 6250 4400
+Wire Wire Line
+ 5700 4400 5700 4300
+Connection ~ 5700 4300
+Wire Wire Line
+ 5750 4100 5750 4300
+Connection ~ 5750 4300
+Wire Wire Line
+ 4650 5000 4650 5050
+Wire Wire Line
+ 4650 5050 6250 5050
+Wire Wire Line
+ 6250 5050 6250 5000
+Wire Wire Line
+ 5700 5000 5700 5050
+Connection ~ 5700 5050
+Wire Wire Line
+ 5350 5200 5350 5050
+Connection ~ 5350 5050
+Wire Wire Line
+ 4550 4700 4700 4700
+Wire Wire Line
+ 4700 4700 4700 5050
+Connection ~ 4700 5050
+Wire Wire Line
+ 5600 4700 5750 4700
+Wire Wire Line
+ 5750 4700 5750 5050
+Connection ~ 5750 5050
+Wire Wire Line
+ 6350 4700 6200 4700
+Wire Wire Line
+ 6200 4700 6200 5050
+Connection ~ 6200 5050
+Wire Wire Line
+ 4150 2300 4150 4700
+Wire Wire Line
+ 3950 4000 4150 4000
+Connection ~ 4150 4000
+Wire Wire Line
+ 5250 2300 4150 2300
+Wire Wire Line
+ 5250 3100 5200 3100
+Wire Wire Line
+ 5200 3100 5200 4700
+Wire Wire Line
+ 6250 3800 6800 3800
+Wire Wire Line
+ 6750 3800 6750 4700
+Connection ~ 6750 3800
+Wire Wire Line
+ 5100 3850 5200 3850
+Connection ~ 5200 3850
+Wire Wire Line
+ 6900 4200 5750 4200
+Connection ~ 5750 4200
+$Comp
+L SKY130mode scmode1
+U 1 1 684B00C1
+P 8250 2900
+F 0 "scmode1" H 8250 3050 98 0000 C CNB
+F 1 "SKY130mode" H 8250 2800 118 0000 C CNB
+F 2 "" H 8250 3050 60 0001 C CNN
+F 3 "" H 8250 3050 60 0001 C CNN
+ 1 8250 2900
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ABT337/NAND_3.cir b/library/SubcircuitLibrary/SN74ABT337/NAND_3.cir
new file mode 100644
index 000000000..d9a4458ce
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/NAND_3.cir
@@ -0,0 +1,18 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/NAND_3.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Jul 6 17:55:34 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC3 Net-_SC2-Pad1_ Net-_SC2-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC4 Net-_SC2-Pad1_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC5 Net-_SC2-Pad1_ Net-_SC5-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC6 Net-_SC1-Pad3_ Net-_SC5-Pad2_ Net-_SC6-Pad3_ Net-_SC6-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC2-Pad2_ Net-_SC1-Pad2_ Net-_SC6-Pad3_ Net-_SC3-Pad3_ Net-_SC2-Pad1_ Net-_SC5-Pad2_ PORT
+scmode1 SKY130mode
+SC2 Net-_SC2-Pad1_ Net-_SC2-Pad2_ Net-_SC1-Pad1_ Net-_SC1-Pad1_ sky130_fd_pr__nfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ABT337/NAND_3.cir.out b/library/SubcircuitLibrary/SN74ABT337/NAND_3.cir.out
new file mode 100644
index 000000000..bcb009b3c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/NAND_3.cir.out
@@ -0,0 +1,26 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_3/nand_3.cir
+
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+xsc3 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc2-pad1_ net-_sc5-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc1-pad3_ net-_sc5-pad2_ net-_sc6-pad3_ net-_sc6-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc2-pad2_ net-_sc1-pad2_ net-_sc6-pad3_ net-_sc3-pad3_ net-_sc2-pad1_ net-_sc5-pad2_ port
+* s c m o d e
+xsc2 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ABT337/NAND_3.pro b/library/SubcircuitLibrary/SN74ABT337/NAND_3.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/NAND_3.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74ABT337/NAND_3.sch b/library/SubcircuitLibrary/SN74ABT337/NAND_3.sch
new file mode 100644
index 000000000..eb96f8eac
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/NAND_3.sch
@@ -0,0 +1,289 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:NAND_3-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF360
+P 4200 2350
+F 0 "SC3" H 4250 2650 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4500 2437 50 0000 R CNN
+F 2 "" H 4200 850 50 0001 C CNN
+F 3 "" H 4200 2350 50 0001 C CNN
+ 1 4200 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 684AF39D
+P 5250 2350
+F 0 "SC4" H 5300 2650 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5550 2437 50 0000 R CNN
+F 2 "" H 5250 850 50 0001 C CNN
+F 3 "" H 5250 2350 50 0001 C CNN
+ 1 5250 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC5
+U 1 1 684AF420
+P 6100 2350
+F 0 "SC5" H 6150 2650 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6400 2437 50 0000 R CNN
+F 2 "" H 6100 850 50 0001 C CNN
+F 3 "" H 6100 2350 50 0001 C CNN
+ 1 6100 2350
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF50C
+P 5250 4000
+F 0 "SC1" H 5300 4300 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5550 4087 50 0000 R CNN
+F 2 "" H 5250 2500 50 0001 C CNN
+F 3 "" H 5250 4000 50 0001 C CNN
+ 1 5250 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 684AF5EC
+P 5650 4700
+F 0 "SC6" H 5700 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5950 4787 50 0000 R CNN
+F 2 "" H 5650 3200 50 0001 C CNN
+F 3 "" H 5650 4700 50 0001 C CNN
+ 1 5650 4700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF63F
+P 3450 2350
+F 0 "U1" H 3500 2450 30 0000 C CNN
+F 1 "PORT" H 3450 2350 30 0000 C CNN
+F 2 "" H 3450 2350 60 0000 C CNN
+F 3 "" H 3450 2350 60 0000 C CNN
+ 1 3450 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF6CC
+P 4500 4000
+F 0 "U1" H 4550 4100 30 0000 C CNN
+F 1 "PORT" H 4500 4000 30 0000 C CNN
+F 2 "" H 4500 4000 60 0000 C CNN
+F 3 "" H 4500 4000 60 0000 C CNN
+ 2 4500 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF829
+P 6300 2800
+F 0 "U1" H 6350 2900 30 0000 C CNN
+F 1 "PORT" H 6300 2800 30 0000 C CNN
+F 2 "" H 6300 2800 60 0000 C CNN
+F 3 "" H 6300 2800 60 0000 C CNN
+ 5 6300 2800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684AF94D
+P 6850 2350
+F 0 "U1" H 6900 2450 30 0000 C CNN
+F 1 "PORT" H 6850 2350 30 0000 C CNN
+F 2 "" H 6850 2350 60 0000 C CNN
+F 3 "" H 6850 2350 60 0000 C CNN
+ 6 6850 2350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF9FE
+P 5100 5200
+F 0 "U1" H 5150 5300 30 0000 C CNN
+F 1 "PORT" H 5100 5200 30 0000 C CNN
+F 2 "" H 5100 5200 60 0000 C CNN
+F 3 "" H 5100 5200 60 0000 C CNN
+ 3 5100 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AFAE6
+P 5500 1750
+F 0 "U1" H 5550 1850 30 0000 C CNN
+F 1 "PORT" H 5500 1750 30 0000 C CNN
+F 2 "" H 5500 1750 60 0000 C CNN
+F 3 "" H 5500 1750 60 0000 C CNN
+ 4 5500 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B00C1
+P 8250 2900
+F 0 "scmode1" H 8250 3050 98 0000 C CNB
+F 1 "SKY130mode" H 8250 2800 118 0000 C CNB
+F 2 "" H 8250 3050 60 0001 C CNN
+F 3 "" H 8250 3050 60 0001 C CNN
+ 1 8250 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684AF577
+P 5250 3250
+F 0 "SC2" H 5300 3550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5550 3337 50 0000 R CNN
+F 2 "" H 5250 1750 50 0001 C CNN
+F 3 "" H 5250 3250 50 0001 C CNN
+ 1 5250 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 2050 4400 2000
+Wire Wire Line
+ 4400 2000 5900 2000
+Wire Wire Line
+ 5900 2000 5900 2050
+Wire Wire Line
+ 5450 2050 5450 2000
+Connection ~ 5450 2000
+Wire Wire Line
+ 5750 1750 5750 2000
+Connection ~ 5750 2000
+Wire Wire Line
+ 4300 2350 4450 2350
+Wire Wire Line
+ 4450 2350 4450 2000
+Connection ~ 4450 2000
+Wire Wire Line
+ 5350 2350 5500 2350
+Wire Wire Line
+ 5500 2350 5500 2000
+Connection ~ 5500 2000
+Wire Wire Line
+ 6000 2350 5850 2350
+Wire Wire Line
+ 5850 2350 5850 2000
+Connection ~ 5850 2000
+Wire Wire Line
+ 4400 2650 4400 2700
+Wire Wire Line
+ 4400 2700 5900 2700
+Wire Wire Line
+ 5900 2700 5900 2650
+Wire Wire Line
+ 5450 2650 5450 2950
+Connection ~ 5450 2700
+Wire Wire Line
+ 6050 2800 5450 2800
+Connection ~ 5450 2800
+Wire Wire Line
+ 3700 2350 3900 2350
+Wire Wire Line
+ 3850 2350 3850 3250
+Wire Wire Line
+ 3850 3250 4950 3250
+Wire Wire Line
+ 4950 2350 4800 2350
+Wire Wire Line
+ 4800 2350 4800 4000
+Wire Wire Line
+ 4750 4000 4950 4000
+Wire Wire Line
+ 5350 3250 5500 3250
+Wire Wire Line
+ 5500 3250 5500 3600
+Wire Wire Line
+ 5500 3600 5450 3600
+Wire Wire Line
+ 5450 3550 5450 3700
+Connection ~ 5450 3600
+Wire Wire Line
+ 6400 2350 6600 2350
+Wire Wire Line
+ 6450 2350 6450 4700
+Wire Wire Line
+ 6450 4700 5950 4700
+Connection ~ 6450 2350
+Wire Wire Line
+ 5350 4000 5500 4000
+Wire Wire Line
+ 5500 4000 5500 4350
+Wire Wire Line
+ 5500 4350 5450 4350
+Wire Wire Line
+ 5450 4300 5450 4400
+Connection ~ 5450 4350
+Connection ~ 4800 4000
+Wire Wire Line
+ 5450 5000 5450 5200
+Wire Wire Line
+ 5450 5200 5350 5200
+Wire Wire Line
+ 5550 4700 5400 4700
+Wire Wire Line
+ 5400 4700 5400 5050
+Wire Wire Line
+ 5400 5050 5450 5050
+Connection ~ 5450 5050
+Connection ~ 3850 2350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ABT337/NAND_3.sub b/library/SubcircuitLibrary/SN74ABT337/NAND_3.sub
new file mode 100644
index 000000000..5d17f8353
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/NAND_3.sub
@@ -0,0 +1,20 @@
+* Subcircuit NAND_3
+.subckt NAND_3 net-_sc2-pad2_ net-_sc1-pad2_ net-_sc6-pad3_ net-_sc3-pad3_ net-_sc2-pad1_ net-_sc5-pad2_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_3/nand_3.cir
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+xsc3 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc2-pad1_ net-_sc5-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc1-pad3_ net-_sc5-pad2_ net-_sc6-pad3_ net-_sc6-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+xsc2 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends NAND_3
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ABT337/NAND_3_Previous_Values.xml b/library/SubcircuitLibrary/SN74ABT337/NAND_3_Previous_Values.xml
new file mode 100644
index 000000000..c0934485a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/NAND_3_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ABT337/SN74ABT337-cache.lib b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337-cache.lib
new file mode 100644
index 000000000..bec1446a2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337-cache.lib
@@ -0,0 +1,95 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# TFF_SR
+#
+DEF TFF_SR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "TFF_SR" 50 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -250 200 350 -200 0 1 0 N
+X Vdd 1 -450 150 200 R 50 50 1 1 I
+X T 2 -450 50 200 R 50 50 1 1 I
+X clk 3 -450 -50 200 R 50 50 1 1 I
+X Gnd 4 550 -150 200 L 50 50 1 1 I
+X set 5 550 150 200 L 50 50 1 1 I
+X Rst 6 -450 -150 200 R 50 50 1 1 I
+X Q 7 550 50 200 L 50 50 1 1 O
+X Q_bar 8 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# tri_state
+#
+DEF tri_state X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "tri_state" 50 -200 60 H V C CNN
+F2 "" 1450 -500 60 H I C CNN
+F3 "" 1450 -500 60 H I C CNN
+DRAW
+C -50 150 50 0 1 0 N
+P 2 0 1 0 -250 150 250 0 N
+P 3 0 1 0 -250 150 -250 -150 250 0 N
+X in 1 -450 0 200 R 50 50 1 1 I
+X Vdd 2 -450 100 200 R 50 50 1 1 I
+X Gnd 3 -450 -100 200 R 50 50 1 1 I
+X En 4 -50 400 200 D 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.bak b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.bak
new file mode 100644
index 000000000..ac9943764
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.bak
@@ -0,0 +1,546 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74ABT337-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L TFF_SR X4
+U 1 1 686E156C
+P 3200 6550
+F 0 "X4" H 3200 6550 60 0000 C CNN
+F 1 "TFF_SR" H 3250 6300 60 0000 C CNN
+F 2 "" H 3200 6550 60 0001 C CNN
+F 3 "" H 3200 6550 60 0001 C CNN
+ 1 3200 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L TFF_SR X3
+U 1 1 686E15A5
+P 3200 5850
+F 0 "X3" H 3200 5850 60 0000 C CNN
+F 1 "TFF_SR" H 3250 5600 60 0000 C CNN
+F 2 "" H 3200 5850 60 0001 C CNN
+F 3 "" H 3200 5850 60 0001 C CNN
+ 1 3200 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L TFF_SR X2
+U 1 1 686E1626
+P 3200 5150
+F 0 "X2" H 3200 5150 60 0000 C CNN
+F 1 "TFF_SR" H 3250 4900 60 0000 C CNN
+F 2 "" H 3200 5150 60 0001 C CNN
+F 3 "" H 3200 5150 60 0001 C CNN
+ 1 3200 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L TFF_SR X1
+U 1 1 686E167B
+P 3200 4400
+F 0 "X1" H 3200 4400 60 0000 C CNN
+F 1 "TFF_SR" H 3250 4150 60 0000 C CNN
+F 2 "" H 3200 4400 60 0001 C CNN
+F 3 "" H 3200 4400 60 0001 C CNN
+ 1 3200 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3750 6500 4250 6500
+Wire Wire Line
+ 4250 6500 4250 6550
+Wire Wire Line
+ 4250 6550 4600 6550
+Wire Wire Line
+ 3750 5800 4600 5800
+Wire Wire Line
+ 3750 5100 4600 5100
+Wire Wire Line
+ 3750 4350 4350 4350
+Wire Wire Line
+ 4350 4350 4350 4400
+Wire Wire Line
+ 4350 4400 4600 4400
+Wire Wire Line
+ 2750 4550 2000 4550
+Wire Wire Line
+ 2750 5300 2550 5300
+Wire Wire Line
+ 2550 4550 2550 6700
+Connection ~ 2550 4550
+Wire Wire Line
+ 2550 6000 2750 6000
+Connection ~ 2550 5300
+Wire Wire Line
+ 2550 6700 2750 6700
+Connection ~ 2550 6000
+Wire Wire Line
+ 2750 4450 2000 4450
+Wire Wire Line
+ 2750 5200 2450 5200
+Wire Wire Line
+ 2450 1600 2450 6600
+Connection ~ 2450 4450
+Wire Wire Line
+ 2450 5900 2750 5900
+Connection ~ 2450 5200
+Wire Wire Line
+ 2450 6600 2750 6600
+Connection ~ 2450 5900
+Wire Wire Line
+ 4600 3700 2450 3700
+Wire Wire Line
+ 4600 3000 2450 3000
+Connection ~ 2450 3700
+Wire Wire Line
+ 4600 2300 2450 2300
+Connection ~ 2450 3000
+Wire Wire Line
+ 4550 1600 2450 1600
+Connection ~ 2450 2300
+Wire Wire Line
+ 4950 1200 1950 1200
+Wire Wire Line
+ 5000 1900 4200 1900
+Wire Wire Line
+ 4200 1200 4200 6150
+Connection ~ 4200 1200
+Wire Wire Line
+ 4200 2600 5000 2600
+Connection ~ 4200 1900
+Wire Wire Line
+ 4200 3300 5000 3300
+Connection ~ 4200 2600
+Wire Wire Line
+ 4200 4000 5000 4000
+Connection ~ 4200 3300
+Wire Wire Line
+ 4200 4700 5000 4700
+Connection ~ 4200 4000
+Wire Wire Line
+ 4200 5400 5000 5400
+Connection ~ 4200 4700
+Wire Wire Line
+ 4200 6150 5000 6150
+Connection ~ 4200 5400
+Wire Wire Line
+ 4550 1500 1950 1500
+Wire Wire Line
+ 4600 2200 4350 2200
+Wire Wire Line
+ 4350 1500 4350 6450
+Connection ~ 4350 1500
+Wire Wire Line
+ 4350 2900 4600 2900
+Connection ~ 4350 2200
+Wire Wire Line
+ 4350 3600 4600 3600
+Connection ~ 4350 2900
+Wire Wire Line
+ 4050 4300 4600 4300
+Connection ~ 4350 3600
+Wire Wire Line
+ 4050 5000 4600 5000
+Connection ~ 4350 4300
+Wire Wire Line
+ 3950 5700 4600 5700
+Connection ~ 4350 5000
+Wire Wire Line
+ 4100 6450 4600 6450
+Connection ~ 4350 5700
+Wire Wire Line
+ 2750 4250 2750 4100
+Wire Wire Line
+ 2750 4100 4050 4100
+Wire Wire Line
+ 4050 4100 4050 4300
+Wire Wire Line
+ 2750 5000 2750 4900
+Wire Wire Line
+ 2750 4900 4050 4900
+Wire Wire Line
+ 4050 4900 4050 5000
+Wire Wire Line
+ 2750 5700 2750 5600
+Wire Wire Line
+ 2750 5600 3950 5600
+Wire Wire Line
+ 3950 5600 3950 5700
+Wire Wire Line
+ 2750 6400 2750 6250
+Wire Wire Line
+ 2750 6250 4100 6250
+Wire Wire Line
+ 4100 6250 4100 6450
+Connection ~ 4350 6450
+Wire Wire Line
+ 4550 1700 4450 1700
+Wire Wire Line
+ 4450 1700 4450 7000
+Wire Wire Line
+ 4450 7000 2000 7000
+Wire Wire Line
+ 4600 6650 4450 6650
+Connection ~ 4450 6650
+Wire Wire Line
+ 3750 6700 4450 6700
+Connection ~ 4450 6700
+Wire Wire Line
+ 4600 5900 4450 5900
+Connection ~ 4450 5900
+Wire Wire Line
+ 3750 6000 4450 6000
+Connection ~ 4450 6000
+Wire Wire Line
+ 4600 5200 4450 5200
+Connection ~ 4450 5200
+Wire Wire Line
+ 3750 5300 4450 5300
+Connection ~ 4450 5300
+Wire Wire Line
+ 4600 4500 4450 4500
+Connection ~ 4450 4500
+Wire Wire Line
+ 3750 4550 4450 4550
+Connection ~ 4450 4550
+Wire Wire Line
+ 4600 3800 4450 3800
+Connection ~ 4450 3800
+Wire Wire Line
+ 4600 3100 4450 3100
+Connection ~ 4450 3100
+Wire Wire Line
+ 4600 2400 4450 2400
+Connection ~ 4450 2400
+Wire Wire Line
+ 2750 5100 2700 5100
+Wire Wire Line
+ 2750 5800 2650 5800
+Wire Wire Line
+ 2750 6500 2650 6500
+$Comp
+L SKY130mode scmode1
+U 1 1 686E2E86
+P 10300 5750
+F 0 "scmode1" H 10300 5900 98 0000 C CNB
+F 1 "SKY130mode" H 10300 5650 118 0000 C CNB
+F 2 "" H 10300 5900 60 0001 C CNN
+F 3 "" H 10300 5900 60 0001 C CNN
+ 1 10300 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E2F88
+P 1700 1200
+F 0 "U1" H 1750 1300 30 0000 C CNN
+F 1 "PORT" H 1700 1200 30 0000 C CNN
+F 2 "" H 1700 1200 60 0000 C CNN
+F 3 "" H 1700 1200 60 0000 C CNN
+ 1 1700 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E2FC9
+P 1700 1500
+F 0 "U1" H 1750 1600 30 0000 C CNN
+F 1 "PORT" H 1700 1500 30 0000 C CNN
+F 2 "" H 1700 1500 60 0000 C CNN
+F 3 "" H 1700 1500 60 0000 C CNN
+ 2 1700 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E3231
+P 1750 4450
+F 0 "U1" H 1800 4550 30 0000 C CNN
+F 1 "PORT" H 1750 4450 30 0000 C CNN
+F 2 "" H 1750 4450 60 0000 C CNN
+F 3 "" H 1750 4450 60 0000 C CNN
+ 3 1750 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E3286
+P 1750 4550
+F 0 "U1" H 1800 4650 30 0000 C CNN
+F 1 "PORT" H 1750 4550 30 0000 C CNN
+F 2 "" H 1750 4550 60 0000 C CNN
+F 3 "" H 1750 4550 60 0000 C CNN
+ 4 1750 4550
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E3374
+P 1750 7000
+F 0 "U1" H 1800 7100 30 0000 C CNN
+F 1 "PORT" H 1750 7000 30 0000 C CNN
+F 2 "" H 1750 7000 60 0000 C CNN
+F 3 "" H 1750 7000 60 0000 C CNN
+ 5 1750 7000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686E3583
+P 5700 1600
+F 0 "U1" H 5750 1700 30 0000 C CNN
+F 1 "PORT" H 5700 1600 30 0000 C CNN
+F 2 "" H 5700 1600 60 0000 C CNN
+F 3 "" H 5700 1600 60 0000 C CNN
+ 6 5700 1600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686E365C
+P 5750 2300
+F 0 "U1" H 5800 2400 30 0000 C CNN
+F 1 "PORT" H 5750 2300 30 0000 C CNN
+F 2 "" H 5750 2300 60 0000 C CNN
+F 3 "" H 5750 2300 60 0000 C CNN
+ 7 5750 2300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686E38DF
+P 5750 3000
+F 0 "U1" H 5800 3100 30 0000 C CNN
+F 1 "PORT" H 5750 3000 30 0000 C CNN
+F 2 "" H 5750 3000 60 0000 C CNN
+F 3 "" H 5750 3000 60 0000 C CNN
+ 8 5750 3000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686E3947
+P 5750 3700
+F 0 "U1" H 5800 3800 30 0000 C CNN
+F 1 "PORT" H 5750 3700 30 0000 C CNN
+F 2 "" H 5750 3700 60 0000 C CNN
+F 3 "" H 5750 3700 60 0000 C CNN
+ 9 5750 3700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686E3A12
+P 5750 4400
+F 0 "U1" H 5800 4500 30 0000 C CNN
+F 1 "PORT" H 5750 4400 30 0000 C CNN
+F 2 "" H 5750 4400 60 0000 C CNN
+F 3 "" H 5750 4400 60 0000 C CNN
+ 10 5750 4400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686E3A91
+P 5750 5100
+F 0 "U1" H 5800 5200 30 0000 C CNN
+F 1 "PORT" H 5750 5100 30 0000 C CNN
+F 2 "" H 5750 5100 60 0000 C CNN
+F 3 "" H 5750 5100 60 0000 C CNN
+ 11 5750 5100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686E3B2C
+P 5750 5800
+F 0 "U1" H 5800 5900 30 0000 C CNN
+F 1 "PORT" H 5750 5800 30 0000 C CNN
+F 2 "" H 5750 5800 60 0000 C CNN
+F 3 "" H 5750 5800 60 0000 C CNN
+ 12 5750 5800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686E3C15
+P 5750 6550
+F 0 "U1" H 5800 6650 30 0000 C CNN
+F 1 "PORT" H 5750 6550 30 0000 C CNN
+F 2 "" H 5750 6550 60 0000 C CNN
+F 3 "" H 5750 6550 60 0000 C CNN
+ 13 5750 6550
+ -1 0 0 -1
+$EndComp
+NoConn ~ 3750 4250
+NoConn ~ 3750 4450
+NoConn ~ 3750 5000
+NoConn ~ 3750 5200
+NoConn ~ 3750 5700
+NoConn ~ 3750 5900
+NoConn ~ 3750 6400
+NoConn ~ 3750 6600
+$Comp
+L tri_state X5
+U 1 1 686E8300
+P 5000 1600
+F 0 "X5" H 5000 1600 60 0000 C CNN
+F 1 "tri_state" H 5050 1400 60 0000 C CNN
+F 2 "" H 6450 1100 60 0001 C CNN
+F 3 "" H 6450 1100 60 0001 C CNN
+ 1 5000 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X6
+U 1 1 686E8345
+P 5050 2300
+F 0 "X6" H 5050 2300 60 0000 C CNN
+F 1 "tri_state" H 5100 2100 60 0000 C CNN
+F 2 "" H 6500 1800 60 0001 C CNN
+F 3 "" H 6500 1800 60 0001 C CNN
+ 1 5050 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X7
+U 1 1 686E83D8
+P 5050 3000
+F 0 "X7" H 5050 3000 60 0000 C CNN
+F 1 "tri_state" H 5100 2800 60 0000 C CNN
+F 2 "" H 6500 2500 60 0001 C CNN
+F 3 "" H 6500 2500 60 0001 C CNN
+ 1 5050 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X8
+U 1 1 686E844B
+P 5050 3700
+F 0 "X8" H 5050 3700 60 0000 C CNN
+F 1 "tri_state" H 5100 3500 60 0000 C CNN
+F 2 "" H 6500 3200 60 0001 C CNN
+F 3 "" H 6500 3200 60 0001 C CNN
+ 1 5050 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X9
+U 1 1 686E84D2
+P 5050 4400
+F 0 "X9" H 5050 4400 60 0000 C CNN
+F 1 "tri_state" H 5100 4200 60 0000 C CNN
+F 2 "" H 6500 3900 60 0001 C CNN
+F 3 "" H 6500 3900 60 0001 C CNN
+ 1 5050 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X10
+U 1 1 686E852F
+P 5050 5100
+F 0 "X10" H 5050 5100 60 0000 C CNN
+F 1 "tri_state" H 5100 4900 60 0000 C CNN
+F 2 "" H 6500 4600 60 0001 C CNN
+F 3 "" H 6500 4600 60 0001 C CNN
+ 1 5050 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X11
+U 1 1 686E85EE
+P 5050 5800
+F 0 "X11" H 5050 5800 60 0000 C CNN
+F 1 "tri_state" H 5100 5600 60 0000 C CNN
+F 2 "" H 6500 5300 60 0001 C CNN
+F 3 "" H 6500 5300 60 0001 C CNN
+ 1 5050 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X12
+U 1 1 686E865B
+P 5050 6550
+F 0 "X12" H 5050 6550 60 0000 C CNN
+F 1 "tri_state" H 5100 6350 60 0000 C CNN
+F 2 "" H 6500 6050 60 0001 C CNN
+F 3 "" H 6500 6050 60 0001 C CNN
+ 1 5050 6550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2650 6500 2650 6300
+Wire Wire Line
+ 2650 6300 2750 6300
+Connection ~ 2750 6300
+Wire Wire Line
+ 2650 5800 2650 5650
+Wire Wire Line
+ 2650 5650 2750 5650
+Connection ~ 2750 5650
+Wire Wire Line
+ 2700 5100 2700 4950
+Wire Wire Line
+ 2700 4950 2750 4950
+Connection ~ 2750 4950
+Wire Wire Line
+ 2750 4350 2700 4350
+Wire Wire Line
+ 2700 4350 2700 4200
+Wire Wire Line
+ 2700 4200 2750 4200
+Connection ~ 2750 4200
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.cir b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.cir
new file mode 100644
index 000000000..75fa83172
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.cir
@@ -0,0 +1,24 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jul 9 20:43:25 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X4 Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ ? Net-_U1-Pad4_ Net-_X12-Pad1_ ? TFF_SR
+X3 Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ ? Net-_U1-Pad4_ Net-_X11-Pad1_ ? TFF_SR
+X2 Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ ? Net-_U1-Pad4_ Net-_X10-Pad1_ ? TFF_SR
+X1 Net-_U1-Pad2_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad5_ ? Net-_U1-Pad4_ Net-_X1-Pad7_ ? TFF_SR
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT
+X5 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad6_ tri_state
+X6 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad7_ tri_state
+X7 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad8_ tri_state
+X8 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad9_ tri_state
+X9 Net-_X1-Pad7_ Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad10_ tri_state
+X10 Net-_X10-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad11_ tri_state
+X11 Net-_X11-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad12_ tri_state
+X12 Net-_X12-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad5_ Net-_U1-Pad1_ Net-_U1-Pad13_ tri_state
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.cir.out b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.cir.out
new file mode 100644
index 000000000..3aa5188f9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.cir.out
@@ -0,0 +1,34 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/sn74abt337/sn74abt337.cir
+
+.include TFF_SR.sub
+.include tri_state.sub
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+x4 net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ ? net-_u1-pad4_ net-_x12-pad1_ ? TFF_SR
+x3 net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ ? net-_u1-pad4_ net-_x11-pad1_ ? TFF_SR
+x2 net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ ? net-_u1-pad4_ net-_x10-pad1_ ? TFF_SR
+x1 net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ ? net-_u1-pad4_ net-_x1-pad7_ ? TFF_SR
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port
+x5 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad6_ tri_state
+x6 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad7_ tri_state
+x7 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad8_ tri_state
+x8 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad9_ tri_state
+x9 net-_x1-pad7_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad10_ tri_state
+x10 net-_x10-pad1_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad11_ tri_state
+x11 net-_x11-pad1_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad12_ tri_state
+x12 net-_x12-pad1_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad13_ tri_state
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.pro b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.sch b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.sch
new file mode 100644
index 000000000..0345b9554
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.sch
@@ -0,0 +1,546 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74ABT337-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L TFF_SR X4
+U 1 1 686E156C
+P 3200 6550
+F 0 "X4" H 3200 6550 60 0000 C CNN
+F 1 "TFF_SR" H 3250 6300 60 0000 C CNN
+F 2 "" H 3200 6550 60 0001 C CNN
+F 3 "" H 3200 6550 60 0001 C CNN
+ 1 3200 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L TFF_SR X3
+U 1 1 686E15A5
+P 3200 5850
+F 0 "X3" H 3200 5850 60 0000 C CNN
+F 1 "TFF_SR" H 3250 5600 60 0000 C CNN
+F 2 "" H 3200 5850 60 0001 C CNN
+F 3 "" H 3200 5850 60 0001 C CNN
+ 1 3200 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L TFF_SR X2
+U 1 1 686E1626
+P 3200 5150
+F 0 "X2" H 3200 5150 60 0000 C CNN
+F 1 "TFF_SR" H 3250 4900 60 0000 C CNN
+F 2 "" H 3200 5150 60 0001 C CNN
+F 3 "" H 3200 5150 60 0001 C CNN
+ 1 3200 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L TFF_SR X1
+U 1 1 686E167B
+P 3200 4400
+F 0 "X1" H 3200 4400 60 0000 C CNN
+F 1 "TFF_SR" H 3250 4150 60 0000 C CNN
+F 2 "" H 3200 4400 60 0001 C CNN
+F 3 "" H 3200 4400 60 0001 C CNN
+ 1 3200 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3750 6500 4250 6500
+Wire Wire Line
+ 4250 6500 4250 6550
+Wire Wire Line
+ 4250 6550 4600 6550
+Wire Wire Line
+ 3750 5800 4600 5800
+Wire Wire Line
+ 3750 5100 4600 5100
+Wire Wire Line
+ 3750 4350 4350 4350
+Wire Wire Line
+ 4350 4350 4350 4400
+Wire Wire Line
+ 4350 4400 4600 4400
+Wire Wire Line
+ 2750 4550 2000 4550
+Wire Wire Line
+ 2750 5300 2550 5300
+Wire Wire Line
+ 2550 4550 2550 6700
+Connection ~ 2550 4550
+Wire Wire Line
+ 2550 6000 2750 6000
+Connection ~ 2550 5300
+Wire Wire Line
+ 2550 6700 2750 6700
+Connection ~ 2550 6000
+Wire Wire Line
+ 2750 4450 2000 4450
+Wire Wire Line
+ 2750 5200 2450 5200
+Wire Wire Line
+ 2450 1600 2450 6600
+Connection ~ 2450 4450
+Wire Wire Line
+ 2450 5900 2750 5900
+Connection ~ 2450 5200
+Wire Wire Line
+ 2450 6600 2750 6600
+Connection ~ 2450 5900
+Wire Wire Line
+ 4600 3700 2450 3700
+Wire Wire Line
+ 4600 3000 2450 3000
+Connection ~ 2450 3700
+Wire Wire Line
+ 4600 2300 2450 2300
+Connection ~ 2450 3000
+Wire Wire Line
+ 4550 1600 2450 1600
+Connection ~ 2450 2300
+Wire Wire Line
+ 4950 1200 1950 1200
+Wire Wire Line
+ 5000 1900 4200 1900
+Wire Wire Line
+ 4200 1200 4200 6150
+Connection ~ 4200 1200
+Wire Wire Line
+ 4200 2600 5000 2600
+Connection ~ 4200 1900
+Wire Wire Line
+ 4200 3300 5000 3300
+Connection ~ 4200 2600
+Wire Wire Line
+ 4200 4000 5000 4000
+Connection ~ 4200 3300
+Wire Wire Line
+ 4200 4700 5000 4700
+Connection ~ 4200 4000
+Wire Wire Line
+ 4200 5400 5000 5400
+Connection ~ 4200 4700
+Wire Wire Line
+ 4200 6150 5000 6150
+Connection ~ 4200 5400
+Wire Wire Line
+ 4550 1500 1950 1500
+Wire Wire Line
+ 4600 2200 4350 2200
+Wire Wire Line
+ 4350 1500 4350 6450
+Connection ~ 4350 1500
+Wire Wire Line
+ 4350 2900 4600 2900
+Connection ~ 4350 2200
+Wire Wire Line
+ 4350 3600 4600 3600
+Connection ~ 4350 2900
+Wire Wire Line
+ 4050 4300 4600 4300
+Connection ~ 4350 3600
+Wire Wire Line
+ 4050 5000 4600 5000
+Connection ~ 4350 4300
+Wire Wire Line
+ 3950 5700 4600 5700
+Connection ~ 4350 5000
+Wire Wire Line
+ 4100 6450 4600 6450
+Connection ~ 4350 5700
+Wire Wire Line
+ 2750 4250 2750 4100
+Wire Wire Line
+ 2750 4100 4050 4100
+Wire Wire Line
+ 4050 4100 4050 4300
+Wire Wire Line
+ 2750 5000 2750 4900
+Wire Wire Line
+ 2750 4900 4050 4900
+Wire Wire Line
+ 4050 4900 4050 5000
+Wire Wire Line
+ 2750 5700 2750 5600
+Wire Wire Line
+ 2750 5600 3950 5600
+Wire Wire Line
+ 3950 5600 3950 5700
+Wire Wire Line
+ 2750 6400 2750 6250
+Wire Wire Line
+ 2750 6250 4100 6250
+Wire Wire Line
+ 4100 6250 4100 6450
+Connection ~ 4350 6450
+Wire Wire Line
+ 4550 1700 4450 1700
+Wire Wire Line
+ 4450 1700 4450 7000
+Wire Wire Line
+ 4450 7000 2000 7000
+Wire Wire Line
+ 4600 6650 4450 6650
+Connection ~ 4450 6650
+Wire Wire Line
+ 3750 6700 4450 6700
+Connection ~ 4450 6700
+Wire Wire Line
+ 4600 5900 4450 5900
+Connection ~ 4450 5900
+Wire Wire Line
+ 3750 6000 4450 6000
+Connection ~ 4450 6000
+Wire Wire Line
+ 4600 5200 4450 5200
+Connection ~ 4450 5200
+Wire Wire Line
+ 3750 5300 4450 5300
+Connection ~ 4450 5300
+Wire Wire Line
+ 4600 4500 4450 4500
+Connection ~ 4450 4500
+Wire Wire Line
+ 3750 4550 4450 4550
+Connection ~ 4450 4550
+Wire Wire Line
+ 4600 3800 4450 3800
+Connection ~ 4450 3800
+Wire Wire Line
+ 4600 3100 4450 3100
+Connection ~ 4450 3100
+Wire Wire Line
+ 4600 2400 4450 2400
+Connection ~ 4450 2400
+Wire Wire Line
+ 2750 5100 2700 5100
+Wire Wire Line
+ 2750 5800 2650 5800
+Wire Wire Line
+ 2750 6500 2650 6500
+$Comp
+L SKY130mode scmode1
+U 1 1 686E2E86
+P 1800 3350
+F 0 "scmode1" H 1800 3500 98 0000 C CNB
+F 1 "SKY130mode" H 1800 3250 118 0000 C CNB
+F 2 "" H 1800 3500 60 0001 C CNN
+F 3 "" H 1800 3500 60 0001 C CNN
+ 1 1800 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E2F88
+P 1700 1200
+F 0 "U1" H 1750 1300 30 0000 C CNN
+F 1 "PORT" H 1700 1200 30 0000 C CNN
+F 2 "" H 1700 1200 60 0000 C CNN
+F 3 "" H 1700 1200 60 0000 C CNN
+ 1 1700 1200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E2FC9
+P 1700 1500
+F 0 "U1" H 1750 1600 30 0000 C CNN
+F 1 "PORT" H 1700 1500 30 0000 C CNN
+F 2 "" H 1700 1500 60 0000 C CNN
+F 3 "" H 1700 1500 60 0000 C CNN
+ 2 1700 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E3231
+P 1750 4450
+F 0 "U1" H 1800 4550 30 0000 C CNN
+F 1 "PORT" H 1750 4450 30 0000 C CNN
+F 2 "" H 1750 4450 60 0000 C CNN
+F 3 "" H 1750 4450 60 0000 C CNN
+ 3 1750 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E3286
+P 1750 4550
+F 0 "U1" H 1800 4650 30 0000 C CNN
+F 1 "PORT" H 1750 4550 30 0000 C CNN
+F 2 "" H 1750 4550 60 0000 C CNN
+F 3 "" H 1750 4550 60 0000 C CNN
+ 4 1750 4550
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E3374
+P 1750 7000
+F 0 "U1" H 1800 7100 30 0000 C CNN
+F 1 "PORT" H 1750 7000 30 0000 C CNN
+F 2 "" H 1750 7000 60 0000 C CNN
+F 3 "" H 1750 7000 60 0000 C CNN
+ 5 1750 7000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686E3583
+P 5700 1600
+F 0 "U1" H 5750 1700 30 0000 C CNN
+F 1 "PORT" H 5700 1600 30 0000 C CNN
+F 2 "" H 5700 1600 60 0000 C CNN
+F 3 "" H 5700 1600 60 0000 C CNN
+ 6 5700 1600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686E365C
+P 5750 2300
+F 0 "U1" H 5800 2400 30 0000 C CNN
+F 1 "PORT" H 5750 2300 30 0000 C CNN
+F 2 "" H 5750 2300 60 0000 C CNN
+F 3 "" H 5750 2300 60 0000 C CNN
+ 7 5750 2300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686E38DF
+P 5750 3000
+F 0 "U1" H 5800 3100 30 0000 C CNN
+F 1 "PORT" H 5750 3000 30 0000 C CNN
+F 2 "" H 5750 3000 60 0000 C CNN
+F 3 "" H 5750 3000 60 0000 C CNN
+ 8 5750 3000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686E3947
+P 5750 3700
+F 0 "U1" H 5800 3800 30 0000 C CNN
+F 1 "PORT" H 5750 3700 30 0000 C CNN
+F 2 "" H 5750 3700 60 0000 C CNN
+F 3 "" H 5750 3700 60 0000 C CNN
+ 9 5750 3700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686E3A12
+P 5750 4400
+F 0 "U1" H 5800 4500 30 0000 C CNN
+F 1 "PORT" H 5750 4400 30 0000 C CNN
+F 2 "" H 5750 4400 60 0000 C CNN
+F 3 "" H 5750 4400 60 0000 C CNN
+ 10 5750 4400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686E3A91
+P 5750 5100
+F 0 "U1" H 5800 5200 30 0000 C CNN
+F 1 "PORT" H 5750 5100 30 0000 C CNN
+F 2 "" H 5750 5100 60 0000 C CNN
+F 3 "" H 5750 5100 60 0000 C CNN
+ 11 5750 5100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686E3B2C
+P 5750 5800
+F 0 "U1" H 5800 5900 30 0000 C CNN
+F 1 "PORT" H 5750 5800 30 0000 C CNN
+F 2 "" H 5750 5800 60 0000 C CNN
+F 3 "" H 5750 5800 60 0000 C CNN
+ 12 5750 5800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686E3C15
+P 5750 6550
+F 0 "U1" H 5800 6650 30 0000 C CNN
+F 1 "PORT" H 5750 6550 30 0000 C CNN
+F 2 "" H 5750 6550 60 0000 C CNN
+F 3 "" H 5750 6550 60 0000 C CNN
+ 13 5750 6550
+ -1 0 0 -1
+$EndComp
+NoConn ~ 3750 4250
+NoConn ~ 3750 4450
+NoConn ~ 3750 5000
+NoConn ~ 3750 5200
+NoConn ~ 3750 5700
+NoConn ~ 3750 5900
+NoConn ~ 3750 6400
+NoConn ~ 3750 6600
+$Comp
+L tri_state X5
+U 1 1 686E8300
+P 5000 1600
+F 0 "X5" H 5000 1600 60 0000 C CNN
+F 1 "tri_state" H 5050 1400 60 0000 C CNN
+F 2 "" H 6450 1100 60 0001 C CNN
+F 3 "" H 6450 1100 60 0001 C CNN
+ 1 5000 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X6
+U 1 1 686E8345
+P 5050 2300
+F 0 "X6" H 5050 2300 60 0000 C CNN
+F 1 "tri_state" H 5100 2100 60 0000 C CNN
+F 2 "" H 6500 1800 60 0001 C CNN
+F 3 "" H 6500 1800 60 0001 C CNN
+ 1 5050 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X7
+U 1 1 686E83D8
+P 5050 3000
+F 0 "X7" H 5050 3000 60 0000 C CNN
+F 1 "tri_state" H 5100 2800 60 0000 C CNN
+F 2 "" H 6500 2500 60 0001 C CNN
+F 3 "" H 6500 2500 60 0001 C CNN
+ 1 5050 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X8
+U 1 1 686E844B
+P 5050 3700
+F 0 "X8" H 5050 3700 60 0000 C CNN
+F 1 "tri_state" H 5100 3500 60 0000 C CNN
+F 2 "" H 6500 3200 60 0001 C CNN
+F 3 "" H 6500 3200 60 0001 C CNN
+ 1 5050 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X9
+U 1 1 686E84D2
+P 5050 4400
+F 0 "X9" H 5050 4400 60 0000 C CNN
+F 1 "tri_state" H 5100 4200 60 0000 C CNN
+F 2 "" H 6500 3900 60 0001 C CNN
+F 3 "" H 6500 3900 60 0001 C CNN
+ 1 5050 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X10
+U 1 1 686E852F
+P 5050 5100
+F 0 "X10" H 5050 5100 60 0000 C CNN
+F 1 "tri_state" H 5100 4900 60 0000 C CNN
+F 2 "" H 6500 4600 60 0001 C CNN
+F 3 "" H 6500 4600 60 0001 C CNN
+ 1 5050 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X11
+U 1 1 686E85EE
+P 5050 5800
+F 0 "X11" H 5050 5800 60 0000 C CNN
+F 1 "tri_state" H 5100 5600 60 0000 C CNN
+F 2 "" H 6500 5300 60 0001 C CNN
+F 3 "" H 6500 5300 60 0001 C CNN
+ 1 5050 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X12
+U 1 1 686E865B
+P 5050 6550
+F 0 "X12" H 5050 6550 60 0000 C CNN
+F 1 "tri_state" H 5100 6350 60 0000 C CNN
+F 2 "" H 6500 6050 60 0001 C CNN
+F 3 "" H 6500 6050 60 0001 C CNN
+ 1 5050 6550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2650 6500 2650 6300
+Wire Wire Line
+ 2650 6300 2750 6300
+Connection ~ 2750 6300
+Wire Wire Line
+ 2650 5800 2650 5650
+Wire Wire Line
+ 2650 5650 2750 5650
+Connection ~ 2750 5650
+Wire Wire Line
+ 2700 5100 2700 4950
+Wire Wire Line
+ 2700 4950 2750 4950
+Connection ~ 2750 4950
+Wire Wire Line
+ 2750 4350 2700 4350
+Wire Wire Line
+ 2700 4350 2700 4200
+Wire Wire Line
+ 2700 4200 2750 4200
+Connection ~ 2750 4200
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.sub b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.sub
new file mode 100644
index 000000000..2db5c09eb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337.sub
@@ -0,0 +1,28 @@
+* Subcircuit SN74ABT337
+.subckt SN74ABT337 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/sn74abt337/sn74abt337.cir
+.include TFF_SR.sub
+.include tri_state.sub
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+x4 net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ ? net-_u1-pad4_ net-_x12-pad1_ ? TFF_SR
+x3 net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ ? net-_u1-pad4_ net-_x11-pad1_ ? TFF_SR
+x2 net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ ? net-_u1-pad4_ net-_x10-pad1_ ? TFF_SR
+x1 net-_u1-pad2_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad5_ ? net-_u1-pad4_ net-_x1-pad7_ ? TFF_SR
+* s c m o d e
+x5 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad6_ tri_state
+x6 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad7_ tri_state
+x7 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad8_ tri_state
+x8 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad9_ tri_state
+x9 net-_x1-pad7_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad10_ tri_state
+x10 net-_x10-pad1_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad11_ tri_state
+x11 net-_x11-pad1_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad12_ tri_state
+x12 net-_x12-pad1_ net-_u1-pad2_ net-_u1-pad5_ net-_u1-pad1_ net-_u1-pad13_ tri_state
+* Control Statements
+
+.ends SN74ABT337
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ABT337/SN74ABT337_Previous_Values.xml b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337_Previous_Values.xml
new file mode 100644
index 000000000..a30490a42
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/SN74ABT337_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/TFF_SR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/TFF_SR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/TFF_SR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/TFF_SR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/tri_state/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/tri_state/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/tri_state/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/tri_state/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/tri_state/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/tri_state/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/tri_state/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/tri_statetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ABT337/TFF_SR-cache.lib b/library/SubcircuitLibrary/SN74ABT337/TFF_SR-cache.lib
new file mode 100644
index 000000000..ea3ce275e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/TFF_SR-cache.lib
@@ -0,0 +1,77 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# NAND_3
+#
+DEF NAND_3 X 0 40 Y Y 1 F N
+F0 "X" 150 0 60 H V C CNN
+F1 "NAND_3" 50 -300 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+C 400 0 50 0 1 0 N
+P 2 0 1 0 -250 250 150 250 N
+P 3 0 1 0 -250 250 -250 -250 150 -250 N
+X in1 1 -450 100 200 R 50 50 1 1 I
+X in2 2 -450 0 200 R 50 50 1 1 I
+X Gnd 3 -450 -200 200 R 50 50 1 1 I
+X Vdd 4 -450 200 200 R 50 50 1 1 I
+X out 5 650 0 200 L 50 50 1 1 O
+X in3 6 -450 -100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ABT337/TFF_SR.cir b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.cir
new file mode 100644
index 000000000..ccd8c470d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/TFF_SR/TFF_SR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jul 9 11:21:42 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad8_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_X1-Pad5_ Net-_U1-Pad3_ NAND_3
+X3 Net-_U1-Pad5_ Net-_X1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad8_ NAND_3
+X2 Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_X2-Pad5_ Net-_U1-Pad2_ NAND_3
+X4 Net-_U1-Pad7_ Net-_X2-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad8_ Net-_U1-Pad6_ NAND_3
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ABT337/TFF_SR.cir.out b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.cir.out
new file mode 100644
index 000000000..df845ba8f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.cir.out
@@ -0,0 +1,25 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tff_sr/tff_sr.cir
+
+.include NAND_3.sub
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+x1 net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad4_ net-_u1-pad1_ net-_x1-pad5_ net-_u1-pad3_ NAND_3
+x3 net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad8_ NAND_3
+x2 net-_u1-pad3_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad1_ net-_x2-pad5_ net-_u1-pad2_ NAND_3
+x4 net-_u1-pad7_ net-_x2-pad5_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad8_ net-_u1-pad6_ NAND_3
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ABT337/TFF_SR.pro b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74ABT337/TFF_SR.sch b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.sch
new file mode 100644
index 000000000..f777e5c3c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.sch
@@ -0,0 +1,301 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NAND_3 X1
+U 1 1 686E01E6
+P 4550 2450
+F 0 "X1" H 4700 2450 60 0000 C CNN
+F 1 "NAND_3" H 4600 2150 60 0000 C CNN
+F 2 "" H 4550 2450 60 0001 C CNN
+F 3 "" H 4550 2450 60 0001 C CNN
+ 1 4550 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X3
+U 1 1 686E0269
+P 6600 2450
+F 0 "X3" H 6750 2450 60 0000 C CNN
+F 1 "NAND_3" H 6650 2150 60 0000 C CNN
+F 2 "" H 6600 2450 60 0001 C CNN
+F 3 "" H 6600 2450 60 0001 C CNN
+ 1 6600 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X2
+U 1 1 686E03FC
+P 4550 3400
+F 0 "X2" H 4700 3400 60 0000 C CNN
+F 1 "NAND_3" H 4600 3100 60 0000 C CNN
+F 2 "" H 4550 3400 60 0001 C CNN
+F 3 "" H 4550 3400 60 0001 C CNN
+ 1 4550 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X4
+U 1 1 686E047D
+P 6600 3400
+F 0 "X4" H 6750 3400 60 0000 C CNN
+F 1 "NAND_3" H 6650 3100 60 0000 C CNN
+F 2 "" H 6600 3400 60 0001 C CNN
+F 3 "" H 6600 3400 60 0001 C CNN
+ 1 6600 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686E050A
+P 10400 4900
+F 0 "scmode1" H 10400 5050 98 0000 C CNB
+F 1 "SKY130mode" H 10400 4800 118 0000 C CNB
+F 2 "" H 10400 5050 60 0001 C CNN
+F 3 "" H 10400 5050 60 0001 C CNN
+ 1 10400 4900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4100 2550 3900 2550
+Wire Wire Line
+ 3900 2550 3900 3300
+Wire Wire Line
+ 3900 3300 4100 3300
+Wire Wire Line
+ 4100 2350 3850 2350
+Wire Wire Line
+ 3850 2350 3850 3500
+Wire Wire Line
+ 3850 2750 3200 2750
+Connection ~ 3850 2750
+Wire Wire Line
+ 3900 2900 3200 2900
+Connection ~ 3900 2900
+Wire Wire Line
+ 3850 3500 4100 3500
+Wire Wire Line
+ 6150 2350 5950 2350
+Wire Wire Line
+ 5950 2350 5950 1800
+Wire Wire Line
+ 6150 3500 5950 3500
+Wire Wire Line
+ 5950 3500 5950 3950
+Wire Wire Line
+ 6150 2550 6050 2550
+Wire Wire Line
+ 6050 2550 6050 2750
+Wire Wire Line
+ 4000 2750 7350 2750
+Wire Wire Line
+ 7350 2750 7350 3400
+Wire Wire Line
+ 7250 3400 7700 3400
+Wire Wire Line
+ 6150 3300 6050 3300
+Wire Wire Line
+ 6050 3300 6050 3100
+Wire Wire Line
+ 4000 3100 7350 3100
+Wire Wire Line
+ 7350 3100 7350 2450
+Wire Wire Line
+ 7250 2450 7700 2450
+Wire Wire Line
+ 5200 2450 6150 2450
+Wire Wire Line
+ 5200 3400 6150 3400
+Wire Wire Line
+ 4100 2450 4000 2450
+Wire Wire Line
+ 4000 2450 4000 2750
+Connection ~ 6050 2750
+Wire Wire Line
+ 4100 3400 4000 3400
+Wire Wire Line
+ 4000 3400 4000 3100
+Connection ~ 6050 3100
+Wire Wire Line
+ 4100 2250 3200 2250
+Wire Wire Line
+ 6150 2250 6150 2150
+Wire Wire Line
+ 6150 2150 4000 2150
+Wire Wire Line
+ 4000 2150 4000 2250
+Connection ~ 4000 2250
+Wire Wire Line
+ 4100 3600 3200 3600
+Wire Wire Line
+ 6150 3600 6150 3750
+Wire Wire Line
+ 6150 3750 3850 3750
+Wire Wire Line
+ 3850 3750 3850 3550
+Connection ~ 3850 3600
+Wire Wire Line
+ 6150 3200 5850 3200
+Wire Wire Line
+ 5850 3200 5850 2150
+Connection ~ 5850 2150
+Wire Wire Line
+ 4100 3200 3950 3200
+Wire Wire Line
+ 3950 3200 3950 2250
+Wire Wire Line
+ 3950 2250 4000 2250
+Wire Wire Line
+ 6150 2650 5750 2650
+Wire Wire Line
+ 5750 2650 5750 3750
+Connection ~ 5750 3750
+Wire Wire Line
+ 4100 2650 3800 2650
+Wire Wire Line
+ 3800 2650 3800 3550
+Wire Wire Line
+ 3800 3550 3850 3550
+Connection ~ 7350 2450
+Connection ~ 7350 3400
+$Comp
+L PORT U1
+U 1 1 686E09C4
+P 2950 2250
+F 0 "U1" H 3000 2350 30 0000 C CNN
+F 1 "PORT" H 2950 2250 30 0000 C CNN
+F 2 "" H 2950 2250 60 0000 C CNN
+F 3 "" H 2950 2250 60 0000 C CNN
+ 1 2950 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E0A05
+P 2950 2750
+F 0 "U1" H 3000 2850 30 0000 C CNN
+F 1 "PORT" H 2950 2750 30 0000 C CNN
+F 2 "" H 2950 2750 60 0000 C CNN
+F 3 "" H 2950 2750 60 0000 C CNN
+ 2 2950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E0A30
+P 2950 2900
+F 0 "U1" H 3000 3000 30 0000 C CNN
+F 1 "PORT" H 2950 2900 30 0000 C CNN
+F 2 "" H 2950 2900 60 0000 C CNN
+F 3 "" H 2950 2900 60 0000 C CNN
+ 3 2950 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E0A61
+P 2950 3600
+F 0 "U1" H 3000 3700 30 0000 C CNN
+F 1 "PORT" H 2950 3600 30 0000 C CNN
+F 2 "" H 2950 3600 60 0000 C CNN
+F 3 "" H 2950 3600 60 0000 C CNN
+ 4 2950 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E0AA4
+P 5700 1800
+F 0 "U1" H 5750 1900 30 0000 C CNN
+F 1 "PORT" H 5700 1800 30 0000 C CNN
+F 2 "" H 5700 1800 60 0000 C CNN
+F 3 "" H 5700 1800 60 0000 C CNN
+ 5 5700 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686E0AE1
+P 5700 3950
+F 0 "U1" H 5750 4050 30 0000 C CNN
+F 1 "PORT" H 5700 3950 30 0000 C CNN
+F 2 "" H 5700 3950 60 0000 C CNN
+F 3 "" H 5700 3950 60 0000 C CNN
+ 6 5700 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686E0B10
+P 7950 2450
+F 0 "U1" H 8000 2550 30 0000 C CNN
+F 1 "PORT" H 7950 2450 30 0000 C CNN
+F 2 "" H 7950 2450 60 0000 C CNN
+F 3 "" H 7950 2450 60 0000 C CNN
+ 7 7950 2450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686E0BAD
+P 7950 3400
+F 0 "U1" H 8000 3500 30 0000 C CNN
+F 1 "PORT" H 7950 3400 30 0000 C CNN
+F 2 "" H 7950 3400 60 0000 C CNN
+F 3 "" H 7950 3400 60 0000 C CNN
+ 8 7950 3400
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ABT337/TFF_SR.sub b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.sub
new file mode 100644
index 000000000..d099db6b1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/TFF_SR.sub
@@ -0,0 +1,19 @@
+* Subcircuit TFF_SR
+.subckt TFF_SR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tff_sr/tff_sr.cir
+.include NAND_3.sub
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+x1 net-_u1-pad2_ net-_u1-pad8_ net-_u1-pad4_ net-_u1-pad1_ net-_x1-pad5_ net-_u1-pad3_ NAND_3
+x3 net-_u1-pad5_ net-_x1-pad5_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad8_ NAND_3
+x2 net-_u1-pad3_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad1_ net-_x2-pad5_ net-_u1-pad2_ NAND_3
+x4 net-_u1-pad7_ net-_x2-pad5_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad8_ net-_u1-pad6_ NAND_3
+* s c m o d e
+* Control Statements
+
+.ends TFF_SR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ABT337/TFF_SR_Previous_Values.xml b/library/SubcircuitLibrary/SN74ABT337/TFF_SR_Previous_Values.xml
new file mode 100644
index 000000000..d8e2f2340
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/TFF_SR_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ABT337/analysis b/library/SubcircuitLibrary/SN74ABT337/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ABT337/tri_state-cache.lib b/library/SubcircuitLibrary/SN74ABT337/tri_state-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/tri_state-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ABT337/tri_state.bak b/library/SubcircuitLibrary/SN74ABT337/tri_state.bak
new file mode 100644
index 000000000..ead3208dc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/tri_state.bak
@@ -0,0 +1,194 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 686E04ED
+P 5150 2450
+F 0 "SC1" H 5200 2750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 2537 50 0000 R CNN
+F 2 "" H 5150 950 50 0001 C CNN
+F 3 "" H 5150 2450 50 0001 C CNN
+ 1 5150 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 686E0554
+P 5150 3250
+F 0 "SC2" H 5200 3550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5450 3337 50 0000 R CNN
+F 2 "" H 5150 1750 50 0001 C CNN
+F 3 "" H 5150 3250 50 0001 C CNN
+ 1 5150 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 686E0577
+P 5950 2600
+F 0 "SC3" H 6000 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6250 2687 50 0000 R CNN
+F 2 "" H 5950 1100 50 0001 C CNN
+F 3 "" H 5950 2600 50 0001 C CNN
+ 1 5950 2600
+ 0 -1 1 0
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686E05B6
+P 9300 2250
+F 0 "scmode1" H 9300 2400 98 0000 C CNB
+F 1 "SKY130mode" H 9300 2150 118 0000 C CNB
+F 2 "" H 9300 2400 60 0001 C CNN
+F 3 "" H 9300 2400 60 0001 C CNN
+ 1 9300 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E061D
+P 4200 2800
+F 0 "U1" H 4250 2900 30 0000 C CNN
+F 1 "PORT" H 4200 2800 30 0000 C CNN
+F 2 "" H 4200 2800 60 0000 C CNN
+F 3 "" H 4200 2800 60 0000 C CNN
+ 1 4200 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E069C
+P 5050 1900
+F 0 "U1" H 5100 2000 30 0000 C CNN
+F 1 "PORT" H 5050 1900 30 0000 C CNN
+F 2 "" H 5050 1900 60 0000 C CNN
+F 3 "" H 5050 1900 60 0000 C CNN
+ 2 5050 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E0725
+P 5100 3750
+F 0 "U1" H 5150 3850 30 0000 C CNN
+F 1 "PORT" H 5100 3750 30 0000 C CNN
+F 2 "" H 5100 3750 60 0000 C CNN
+F 3 "" H 5100 3750 60 0000 C CNN
+ 3 5100 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E0750
+P 6800 2800
+F 0 "U1" H 6850 2900 30 0000 C CNN
+F 1 "PORT" H 6800 2800 30 0000 C CNN
+F 2 "" H 6800 2800 60 0000 C CNN
+F 3 "" H 6800 2800 60 0000 C CNN
+ 5 6800 2800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E0793
+P 6200 2150
+F 0 "U1" H 6250 2250 30 0000 C CNN
+F 1 "PORT" H 6200 2150 30 0000 C CNN
+F 2 "" H 6200 2150 60 0000 C CNN
+F 3 "" H 6200 2150 60 0000 C CNN
+ 4 6200 2150
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4850 2450 4850 3250
+Wire Wire Line
+ 4450 2800 4850 2800
+Connection ~ 4850 2800
+Wire Wire Line
+ 5350 2750 5350 2950
+Wire Wire Line
+ 5400 2450 5250 2450
+Wire Wire Line
+ 5400 1900 5400 2450
+Wire Wire Line
+ 5400 2150 5350 2150
+Wire Wire Line
+ 5300 1900 5400 1900
+Connection ~ 5400 2150
+Wire Wire Line
+ 5250 3250 5400 3250
+Wire Wire Line
+ 5400 3250 5400 3750
+Wire Wire Line
+ 5400 3550 5350 3550
+Wire Wire Line
+ 5400 3750 5350 3750
+Connection ~ 5400 3550
+Wire Wire Line
+ 5650 2800 5350 2800
+Connection ~ 5350 2800
+Wire Wire Line
+ 5950 2850 5950 2700
+Wire Wire Line
+ 5550 2850 5950 2850
+Wire Wire Line
+ 5550 2850 5550 2800
+Connection ~ 5550 2800
+Wire Wire Line
+ 6250 2800 6550 2800
+Wire Wire Line
+ 5950 2300 5950 2150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ABT337/tri_state.cir b/library/SubcircuitLibrary/SN74ABT337/tri_state.cir
new file mode 100644
index 000000000..9a1bd9419
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/tri_state.cir
@@ -0,0 +1,15 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/tri_state/tri_state.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jul 9 20:18:58 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+scmode1 SKY130mode
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC3-Pad2_ Net-_SC3-Pad1_ PORT
+SC3 Net-_SC3-Pad1_ Net-_SC3-Pad2_ Net-_SC1-Pad1_ Net-_SC1-Pad1_ sky130_fd_pr__nfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ABT337/tri_state.cir.out b/library/SubcircuitLibrary/SN74ABT337/tri_state.cir.out
new file mode 100644
index 000000000..31969d0e5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/tri_state.cir.out
@@ -0,0 +1,23 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tri_state/tri_state.cir
+
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc3-pad1_ port
+xsc3 net-_sc3-pad1_ net-_sc3-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ABT337/tri_state.pro b/library/SubcircuitLibrary/SN74ABT337/tri_state.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/tri_state.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74ABT337/tri_state.sch b/library/SubcircuitLibrary/SN74ABT337/tri_state.sch
new file mode 100644
index 000000000..33449dcff
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/tri_state.sch
@@ -0,0 +1,195 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:tri_state-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 686E04ED
+P 5150 2450
+F 0 "SC1" H 5200 2750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 2537 50 0000 R CNN
+F 2 "" H 5150 950 50 0001 C CNN
+F 3 "" H 5150 2450 50 0001 C CNN
+ 1 5150 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 686E0554
+P 5150 3250
+F 0 "SC2" H 5200 3550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5450 3337 50 0000 R CNN
+F 2 "" H 5150 1750 50 0001 C CNN
+F 3 "" H 5150 3250 50 0001 C CNN
+ 1 5150 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686E05B6
+P 9300 2250
+F 0 "scmode1" H 9300 2400 98 0000 C CNB
+F 1 "SKY130mode" H 9300 2150 118 0000 C CNB
+F 2 "" H 9300 2400 60 0001 C CNN
+F 3 "" H 9300 2400 60 0001 C CNN
+ 1 9300 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E061D
+P 4200 2800
+F 0 "U1" H 4250 2900 30 0000 C CNN
+F 1 "PORT" H 4200 2800 30 0000 C CNN
+F 2 "" H 4200 2800 60 0000 C CNN
+F 3 "" H 4200 2800 60 0000 C CNN
+ 1 4200 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E069C
+P 5050 1900
+F 0 "U1" H 5100 2000 30 0000 C CNN
+F 1 "PORT" H 5050 1900 30 0000 C CNN
+F 2 "" H 5050 1900 60 0000 C CNN
+F 3 "" H 5050 1900 60 0000 C CNN
+ 2 5050 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E0725
+P 5100 3750
+F 0 "U1" H 5150 3850 30 0000 C CNN
+F 1 "PORT" H 5100 3750 30 0000 C CNN
+F 2 "" H 5100 3750 60 0000 C CNN
+F 3 "" H 5100 3750 60 0000 C CNN
+ 3 5100 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E0750
+P 6800 2800
+F 0 "U1" H 6850 2900 30 0000 C CNN
+F 1 "PORT" H 6800 2800 30 0000 C CNN
+F 2 "" H 6800 2800 60 0000 C CNN
+F 3 "" H 6800 2800 60 0000 C CNN
+ 5 6800 2800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E0793
+P 6200 2150
+F 0 "U1" H 6250 2250 30 0000 C CNN
+F 1 "PORT" H 6200 2150 30 0000 C CNN
+F 2 "" H 6200 2150 60 0000 C CNN
+F 3 "" H 6200 2150 60 0000 C CNN
+ 4 6200 2150
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4850 2450 4850 3250
+Wire Wire Line
+ 4450 2800 4850 2800
+Connection ~ 4850 2800
+Wire Wire Line
+ 5350 2750 5350 2950
+Wire Wire Line
+ 5400 2450 5250 2450
+Wire Wire Line
+ 5400 1900 5400 2450
+Wire Wire Line
+ 5400 2150 5350 2150
+Wire Wire Line
+ 5300 1900 5400 1900
+Connection ~ 5400 2150
+Wire Wire Line
+ 5250 3250 5400 3250
+Wire Wire Line
+ 5400 3250 5400 3750
+Wire Wire Line
+ 5400 3550 5350 3550
+Wire Wire Line
+ 5400 3750 5350 3750
+Connection ~ 5400 3550
+Wire Wire Line
+ 5650 2800 5350 2800
+Connection ~ 5350 2800
+Wire Wire Line
+ 5950 2850 5950 2700
+Wire Wire Line
+ 5550 2850 5950 2850
+Wire Wire Line
+ 5550 2850 5550 2800
+Connection ~ 5550 2800
+Wire Wire Line
+ 6250 2800 6550 2800
+Wire Wire Line
+ 5950 2300 5950 2150
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 686E7F5A
+P 5950 2600
+F 0 "SC3" H 6000 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6250 2687 50 0000 R CNN
+F 2 "" H 5950 1100 50 0001 C CNN
+F 3 "" H 5950 2600 50 0001 C CNN
+ 1 5950 2600
+ 0 1 1 0
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ABT337/tri_state.sub b/library/SubcircuitLibrary/SN74ABT337/tri_state.sub
new file mode 100644
index 000000000..9669589c3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/tri_state.sub
@@ -0,0 +1,17 @@
+* Subcircuit tri_state
+.subckt tri_state net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc3-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tri_state/tri_state.cir
+.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__pnp.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__linear.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__r+c.model.spice"
+.include "/usr/share/local/sky130_fd_pr/models/sky130_fd_pr__model__inductors.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+xsc3 net-_sc3-pad1_ net-_sc3-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends tri_state
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ABT337/tri_state_Previous_Values.xml b/library/SubcircuitLibrary/SN74ABT337/tri_state_Previous_Values.xml
new file mode 100644
index 000000000..bba801349
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ABT337/tri_state_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/3_in_and-cache.lib b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.cir b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.cir
new file mode 100644
index 000000000..a1633ce81
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.cir
@@ -0,0 +1,20 @@
+* H:\esim\eSim\library\SubcircuitLibrary\3_in_and\3_in_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/16/25 13:08:42
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC6 Net-_SC1-Pad1_ Net-_SC5-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC3 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC3-Pad3_ Net-_SC2-Pad2_ Net-_SC4-Pad3_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+SC5 Net-_SC4-Pad3_ Net-_SC5-Pad2_ Net-_SC3-Pad4_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+SC7 Net-_SC1-Pad1_ Net-_SC1-Pad1_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC8 Net-_SC1-Pad1_ Net-_SC1-Pad1_ Net-_SC3-Pad4_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+scmode1 SKY130mode
+U1 Net-_SC1-Pad2_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC3-Pad4_ Net-_SC5-Pad2_ Net-_SC1-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.cir.out b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.cir.out
new file mode 100644
index 000000000..e7d08eafc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.cir.out
@@ -0,0 +1,28 @@
+* h:\esim\esim\library\subcircuitlibrary\3_in_and\3_in_and.cir
+
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__r+c.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__linear.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__inductors.model.spice"
+.lib "H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spice" tt
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__pnp.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc6 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc2-pad2_ net-_sc4-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc5-pad2_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc1-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc1-pad1_ net-_sc1-pad1_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* u1 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad4_ net-_sc5-pad2_ net-_sc1-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.pro b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.sch b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.sch
new file mode 100644
index 000000000..413d03374
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.sch
@@ -0,0 +1,324 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 685EFB75
+P 4650 2000
+F 0 "SC1" H 4700 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4950 2087 50 0000 R CNN
+F 2 "" H 4650 500 50 0001 C CNN
+F 3 "" H 4650 2000 50 0001 C CNN
+ 1 4650 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 685EFBB1
+P 6200 2000
+F 0 "SC2" H 6250 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6500 2087 50 0000 R CNN
+F 2 "" H 6200 500 50 0001 C CNN
+F 3 "" H 6200 2000 50 0001 C CNN
+ 1 6200 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC6
+U 1 1 685EFC40
+P 7750 2000
+F 0 "SC6" H 7800 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 8050 2087 50 0000 R CNN
+F 2 "" H 7750 500 50 0001 C CNN
+F 3 "" H 7750 2000 50 0001 C CNN
+ 1 7750 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 685EFDF8
+P 6200 2950
+F 0 "SC3" H 6250 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6500 3037 50 0000 R CNN
+F 2 "" H 6200 1450 50 0001 C CNN
+F 3 "" H 6200 2950 50 0001 C CNN
+ 1 6200 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 685EFE69
+P 6200 3750
+F 0 "SC4" H 6250 4050 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6500 3837 50 0000 R CNN
+F 2 "" H 6200 2250 50 0001 C CNN
+F 3 "" H 6200 3750 50 0001 C CNN
+ 1 6200 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 685EFEFC
+P 6600 4450
+F 0 "SC5" H 6650 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6900 4537 50 0000 R CNN
+F 2 "" H 6600 2950 50 0001 C CNN
+F 3 "" H 6600 4450 50 0001 C CNN
+ 1 6600 4450
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC7
+U 1 1 685F0235
+P 8600 2000
+F 0 "SC7" H 8650 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 8900 2087 50 0000 R CNN
+F 2 "" H 8600 500 50 0001 C CNN
+F 3 "" H 8600 2000 50 0001 C CNN
+ 1 8600 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC8
+U 1 1 685F02AE
+P 8600 4500
+F 0 "SC8" H 8650 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 8900 4587 50 0000 R CNN
+F 2 "" H 8600 3000 50 0001 C CNN
+F 3 "" H 8600 4500 50 0001 C CNN
+ 1 8600 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 685F03F9
+P 10450 6050
+F 0 "scmode1" H 10450 6200 98 0000 C CNB
+F 1 "SKY130mode" H 10450 5950 118 0000 C CNB
+F 2 "" H 10450 6200 60 0001 C CNN
+F 3 "" H 10450 6200 60 0001 C CNN
+ 1 10450 6050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685F046F
+P 3800 2000
+F 0 "U1" H 3850 2100 30 0000 C CNN
+F 1 "PORT" H 3800 2000 30 0000 C CNN
+F 2 "" H 3800 2000 60 0000 C CNN
+F 3 "" H 3800 2000 60 0000 C CNN
+ 1 3800 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685F04F8
+P 5400 2000
+F 0 "U1" H 5450 2100 30 0000 C CNN
+F 1 "PORT" H 5400 2000 30 0000 C CNN
+F 2 "" H 5400 2000 60 0000 C CNN
+F 3 "" H 5400 2000 60 0000 C CNN
+ 2 5400 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685F05AF
+P 6950 2000
+F 0 "U1" H 7000 2100 30 0000 C CNN
+F 1 "PORT" H 6950 2000 30 0000 C CNN
+F 2 "" H 6950 2000 60 0000 C CNN
+F 3 "" H 6950 2000 60 0000 C CNN
+ 5 6950 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685F0660
+P 9350 2950
+F 0 "U1" H 9400 3050 30 0000 C CNN
+F 1 "PORT" H 9350 2950 30 0000 C CNN
+F 2 "" H 9350 2950 60 0000 C CNN
+F 3 "" H 9350 2950 60 0000 C CNN
+ 6 9350 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685F087C
+P 6150 1250
+F 0 "U1" H 6200 1350 30 0000 C CNN
+F 1 "PORT" H 6150 1250 30 0000 C CNN
+F 2 "" H 6150 1250 60 0000 C CNN
+F 3 "" H 6150 1250 60 0000 C CNN
+ 3 6150 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685F095F
+P 6150 5100
+F 0 "U1" H 6200 5200 30 0000 C CNN
+F 1 "PORT" H 6150 5100 30 0000 C CNN
+F 2 "" H 6150 5100 60 0000 C CNN
+F 3 "" H 6150 5100 60 0000 C CNN
+ 4 6150 5100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4850 1700 4850 1600
+Wire Wire Line
+ 4850 1600 8850 1600
+Wire Wire Line
+ 8800 1600 8800 1700
+Wire Wire Line
+ 6400 1250 6400 1700
+Connection ~ 6400 1600
+Wire Wire Line
+ 7950 1700 7950 1600
+Connection ~ 7950 1600
+Wire Wire Line
+ 4850 2300 4850 2350
+Wire Wire Line
+ 4850 2350 8800 2350
+Wire Wire Line
+ 8800 2300 8800 4200
+Wire Wire Line
+ 6400 2300 6400 2650
+Connection ~ 6400 2350
+Wire Wire Line
+ 7950 2300 7950 2350
+Connection ~ 7950 2350
+Wire Wire Line
+ 4750 2000 4950 2000
+Wire Wire Line
+ 4950 2000 4950 1600
+Connection ~ 4950 1600
+Wire Wire Line
+ 6300 2000 6500 2000
+Wire Wire Line
+ 6500 2000 6500 1600
+Connection ~ 6500 1600
+Wire Wire Line
+ 7850 2000 8050 2000
+Wire Wire Line
+ 8050 2000 8050 1600
+Connection ~ 8050 1600
+Wire Wire Line
+ 8700 2000 8850 2000
+Wire Wire Line
+ 8850 2000 8850 1600
+Connection ~ 8800 1600
+Wire Wire Line
+ 4350 2000 4050 2000
+Wire Wire Line
+ 5900 2000 5650 2000
+Wire Wire Line
+ 7450 2000 7200 2000
+Wire Wire Line
+ 8300 2000 8300 4500
+Wire Wire Line
+ 8300 2450 6400 2450
+Connection ~ 6400 2450
+Wire Wire Line
+ 5900 2950 4250 2950
+Wire Wire Line
+ 4250 2950 4250 2000
+Connection ~ 4250 2000
+Wire Wire Line
+ 5900 3750 5700 3750
+Wire Wire Line
+ 5700 3750 5700 2000
+Connection ~ 5700 2000
+Wire Wire Line
+ 6900 4450 7350 4450
+Wire Wire Line
+ 7350 4450 7350 2000
+Connection ~ 7350 2000
+Wire Wire Line
+ 6400 5100 6400 4750
+Wire Wire Line
+ 8700 4500 8900 4500
+Wire Wire Line
+ 8900 4500 8900 4900
+Wire Wire Line
+ 8900 4900 6350 4900
+Connection ~ 6400 4900
+Wire Wire Line
+ 8800 4800 8800 4900
+Connection ~ 8800 4900
+Wire Wire Line
+ 6500 4450 6350 4450
+Wire Wire Line
+ 6350 4450 6350 4900
+Wire Wire Line
+ 6400 4050 6400 4150
+Wire Wire Line
+ 6300 3750 7000 3750
+Wire Wire Line
+ 7000 2950 7000 4900
+Connection ~ 7000 4900
+Wire Wire Line
+ 6400 3250 6400 3450
+Wire Wire Line
+ 6300 2950 7000 2950
+Connection ~ 7000 3750
+Connection ~ 8800 2350
+Connection ~ 8300 2450
+Wire Wire Line
+ 9100 2950 8800 2950
+Connection ~ 8800 2950
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.sub b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.sub
new file mode 100644
index 000000000..a88c47594
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and.sub
@@ -0,0 +1,22 @@
+* Subcircuit 3_in_and
+.subckt 3_in_and net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad4_ net-_sc5-pad2_ net-_sc1-pad1_
+* h:\esim\esim\library\subcircuitlibrary\3_in_and\3_in_and.cir
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__r+c.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__linear.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__inductors.model.spice"
+.lib "H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spice" tt
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__pnp.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc6 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc2-pad2_ net-_sc4-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc5-pad2_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc1-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc1-pad1_ net-_sc1-pad1_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends 3_in_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/3_in_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and_Previous_Values.xml
new file mode 100644
index 000000000..f78519633
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/3_in_and_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR-cache.lib b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.cir b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.cir
new file mode 100644
index 000000000..798338152
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.cir
@@ -0,0 +1,14 @@
+* H:\esim\eSim\library\SubcircuitLibrary\CMOS_INVTR\CMOS_INVTR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/12/25 16:02:08
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.cir.out b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.cir.out
new file mode 100644
index 000000000..268de8701
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.cir.out
@@ -0,0 +1,16 @@
+* h:\esim\esim\library\subcircuitlibrary\cmos_invtr\cmos_invtr.cir
+
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.pro b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.sch b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.sch
new file mode 100644
index 000000000..aa7a7ee81
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.sch
@@ -0,0 +1,161 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 684B982F
+P 5350 2950
+F 0 "SC1" H 5400 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 3037 50 0000 R CNN
+F 2 "" H 5350 1450 50 0001 C CNN
+F 3 "" H 5350 2950 50 0001 C CNN
+ 1 5350 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684B9856
+P 5350 3800
+F 0 "SC2" H 5400 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5650 3887 50 0000 R CNN
+F 2 "" H 5350 2300 50 0001 C CNN
+F 3 "" H 5350 3800 50 0001 C CNN
+ 1 5350 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B98AD
+P 4550 3300
+F 0 "U1" H 4600 3400 30 0000 C CNN
+F 1 "PORT" H 4550 3300 30 0000 C CNN
+F 2 "" H 4550 3300 60 0000 C CNN
+F 3 "" H 4550 3300 60 0000 C CNN
+ 1 4550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B98D8
+P 6300 3350
+F 0 "U1" H 6350 3450 30 0000 C CNN
+F 1 "PORT" H 6300 3350 30 0000 C CNN
+F 2 "" H 6300 3350 60 0000 C CNN
+F 3 "" H 6300 3350 60 0000 C CNN
+ 4 6300 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B9935
+P 5300 4350
+F 0 "U1" H 5350 4450 30 0000 C CNN
+F 1 "PORT" H 5300 4350 30 0000 C CNN
+F 2 "" H 5300 4350 60 0000 C CNN
+F 3 "" H 5300 4350 60 0000 C CNN
+ 3 5300 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B999A
+P 5300 2350
+F 0 "U1" H 5350 2450 30 0000 C CNN
+F 1 "PORT" H 5300 2350 30 0000 C CNN
+F 2 "" H 5300 2350 60 0000 C CNN
+F 3 "" H 5300 2350 60 0000 C CNN
+ 2 5300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B99CD
+P 7950 3000
+F 0 "scmode1" H 7950 3150 98 0000 C CNB
+F 1 "SKY130mode" H 7950 2900 118 0000 C CNB
+F 2 "" H 7950 3150 60 0001 C CNN
+F 3 "" H 7950 3150 60 0001 C CNN
+ 1 7950 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 2650 5550 2350
+Wire Wire Line
+ 5450 2950 5600 2950
+Wire Wire Line
+ 5600 2950 5600 2550
+Wire Wire Line
+ 5600 2550 5550 2550
+Connection ~ 5550 2550
+Wire Wire Line
+ 5550 3250 5550 3500
+Wire Wire Line
+ 6050 3350 5550 3350
+Connection ~ 5550 3350
+Wire Wire Line
+ 5050 2950 5050 3800
+Wire Wire Line
+ 4800 3300 5050 3300
+Connection ~ 5050 3300
+Wire Wire Line
+ 5450 3800 5600 3800
+Wire Wire Line
+ 5600 3800 5600 4150
+Wire Wire Line
+ 5600 4150 5550 4150
+Wire Wire Line
+ 5550 4100 5550 4350
+Connection ~ 5550 4150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.sub b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.sub
new file mode 100644
index 000000000..dfe6de3e5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR.sub
@@ -0,0 +1,10 @@
+* Subcircuit CMOS_INVTR
+.subckt CMOS_INVTR net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_
+* h:\esim\esim\library\subcircuitlibrary\cmos_invtr\cmos_invtr.cir
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends CMOS_INVTR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR_Previous_Values.xml
new file mode 100644
index 000000000..af4904616
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/CMOS_INVTR_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettw=3 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A-cache.lib b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A-cache.lib
new file mode 100644
index 000000000..be1f74a53
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 250 0 50 0 1 0 N
+P 2 0 1 0 -250 150 200 0 N
+P 3 0 1 0 -250 150 -250 -150 200 0 N
+X IN 1 -450 0 200 R 50 50 1 1 I
+X VDD 2 -450 100 200 R 50 50 1 1 I
+X GND 3 -450 -100 200 R 50 50 1 1 I
+X OUT 4 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A-rescue.lib b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A-rescue.lib
new file mode 100644
index 000000000..f0524b5d5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A-rescue.lib
@@ -0,0 +1,25 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_in_and-RESCUE-SN74ALS1011A
+#
+DEF 3_in_and-RESCUE-SN74ALS1011A X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "3_in_and-RESCUE-SN74ALS1011A" 50 -300 60 H V C CNN
+F2 "" 600 -150 60 H I C CNN
+F3 "" 600 -150 60 H I C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+P 2 0 1 0 -150 250 100 250 N
+P 2 0 1 0 150 250 100 250 N
+P 3 0 1 0 -150 250 -150 -250 150 -250 N
+X in1 1 -350 100 200 R 50 50 1 1 I
+X in2 2 -350 0 200 R 50 50 1 1 I
+X Vdd 3 -350 200 200 R 50 50 1 1 I
+X Gnd 4 -350 -200 200 R 50 50 1 1 I
+X in3 5 -350 -100 200 R 50 50 1 1 I
+X out 6 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.bak b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.bak
new file mode 100644
index 000000000..158dcae59
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.bak
@@ -0,0 +1,300 @@
+EESchema Schematic File Version 2
+LIBS:SN74ALS1011A-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74ALS1011A-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 4450 2150 3550 2150
+Wire Wire Line
+ 4450 2250 3550 2250
+Wire Wire Line
+ 4450 2350 3550 2350
+Wire Wire Line
+ 4450 2450 3550 2450
+Wire Wire Line
+ 4450 2550 3550 2550
+Wire Wire Line
+ 4450 2850 4350 2850
+Wire Wire Line
+ 4350 2150 4350 3550
+Connection ~ 4350 2150
+Wire Wire Line
+ 4450 2950 3550 2950
+Wire Wire Line
+ 4450 3050 3550 3050
+Wire Wire Line
+ 4450 3150 3550 3150
+Wire Wire Line
+ 4450 3250 4250 3250
+Wire Wire Line
+ 4250 2550 4250 3950
+Connection ~ 4250 2550
+Wire Wire Line
+ 4350 3550 4450 3550
+Connection ~ 4350 2850
+Wire Wire Line
+ 4450 3650 3550 3650
+Wire Wire Line
+ 4450 3750 3550 3750
+Wire Wire Line
+ 4450 3850 3550 3850
+Wire Wire Line
+ 4250 3950 4450 3950
+Connection ~ 4250 3250
+Wire Wire Line
+ 5350 2350 5700 2350
+Wire Wire Line
+ 5350 3050 5700 3050
+Wire Wire Line
+ 5350 3750 5700 3750
+$Comp
+L PORT U1
+U 1 1 686CB9D2
+P 3300 2150
+F 0 "U1" H 3350 2250 30 0000 C CNN
+F 1 "PORT" H 3300 2150 30 0000 C CNN
+F 2 "" H 3300 2150 60 0000 C CNN
+F 3 "" H 3300 2150 60 0000 C CNN
+ 1 3300 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686CBAC3
+P 3300 2250
+F 0 "U1" H 3350 2350 30 0000 C CNN
+F 1 "PORT" H 3300 2250 30 0000 C CNN
+F 2 "" H 3300 2250 60 0000 C CNN
+F 3 "" H 3300 2250 60 0000 C CNN
+ 2 3300 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686CBB69
+P 3300 2350
+F 0 "U1" H 3350 2450 30 0000 C CNN
+F 1 "PORT" H 3300 2350 30 0000 C CNN
+F 2 "" H 3300 2350 60 0000 C CNN
+F 3 "" H 3300 2350 60 0000 C CNN
+ 3 3300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686CBB98
+P 3300 2450
+F 0 "U1" H 3350 2550 30 0000 C CNN
+F 1 "PORT" H 3300 2450 30 0000 C CNN
+F 2 "" H 3300 2450 60 0000 C CNN
+F 3 "" H 3300 2450 60 0000 C CNN
+ 4 3300 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686CBBD5
+P 3300 2550
+F 0 "U1" H 3350 2650 30 0000 C CNN
+F 1 "PORT" H 3300 2550 30 0000 C CNN
+F 2 "" H 3300 2550 60 0000 C CNN
+F 3 "" H 3300 2550 60 0000 C CNN
+ 5 3300 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686CBCFE
+P 3300 2950
+F 0 "U1" H 3350 3050 30 0000 C CNN
+F 1 "PORT" H 3300 2950 30 0000 C CNN
+F 2 "" H 3300 2950 60 0000 C CNN
+F 3 "" H 3300 2950 60 0000 C CNN
+ 6 3300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686CBDC7
+P 3300 3050
+F 0 "U1" H 3350 3150 30 0000 C CNN
+F 1 "PORT" H 3300 3050 30 0000 C CNN
+F 2 "" H 3300 3050 60 0000 C CNN
+F 3 "" H 3300 3050 60 0000 C CNN
+ 7 3300 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686CBE16
+P 3300 3150
+F 0 "U1" H 3350 3250 30 0000 C CNN
+F 1 "PORT" H 3300 3150 30 0000 C CNN
+F 2 "" H 3300 3150 60 0000 C CNN
+F 3 "" H 3300 3150 60 0000 C CNN
+ 8 3300 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686CBEA9
+P 3300 3650
+F 0 "U1" H 3350 3750 30 0000 C CNN
+F 1 "PORT" H 3300 3650 30 0000 C CNN
+F 2 "" H 3300 3650 60 0000 C CNN
+F 3 "" H 3300 3650 60 0000 C CNN
+ 9 3300 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686CC052
+P 3300 3750
+F 0 "U1" H 3350 3850 30 0000 C CNN
+F 1 "PORT" H 3300 3750 30 0000 C CNN
+F 2 "" H 3300 3750 60 0000 C CNN
+F 3 "" H 3300 3750 60 0000 C CNN
+ 10 3300 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686CC0CC
+P 3300 3850
+F 0 "U1" H 3350 3950 30 0000 C CNN
+F 1 "PORT" H 3300 3850 30 0000 C CNN
+F 2 "" H 3300 3850 60 0000 C CNN
+F 3 "" H 3300 3850 60 0000 C CNN
+ 11 3300 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686CC1BD
+P 5950 2350
+F 0 "U1" H 6000 2450 30 0000 C CNN
+F 1 "PORT" H 5950 2350 30 0000 C CNN
+F 2 "" H 5950 2350 60 0000 C CNN
+F 3 "" H 5950 2350 60 0000 C CNN
+ 12 5950 2350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686CC2BA
+P 5950 3050
+F 0 "U1" H 6000 3150 30 0000 C CNN
+F 1 "PORT" H 5950 3050 30 0000 C CNN
+F 2 "" H 5950 3050 60 0000 C CNN
+F 3 "" H 5950 3050 60 0000 C CNN
+ 13 5950 3050
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 686CC54C
+P 5950 3750
+F 0 "U1" H 6000 3850 30 0000 C CNN
+F 1 "PORT" H 5950 3750 30 0000 C CNN
+F 2 "" H 5950 3750 60 0000 C CNN
+F 3 "" H 5950 3750 60 0000 C CNN
+ 14 5950 3750
+ -1 0 0 1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686CC7EC
+P 7950 3000
+F 0 "scmode1" H 7950 3150 98 0000 C CNB
+F 1 "SKY130mode" H 7950 2900 118 0000 C CNB
+F 2 "" H 7950 3150 60 0001 C CNN
+F 3 "" H 7950 3150 60 0001 C CNN
+ 1 7950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_in_and X1
+U 1 1 6877598F
+P 4900 2350
+F 0 "X1" H 4900 2350 60 0000 C CNN
+F 1 "3_in_and" H 4900 2050 60 0000 C CNN
+F 2 "" H 4900 2350 60 0001 C CNN
+F 3 "" H 4900 2350 60 0001 C CNN
+ 1 4900 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_in_and X2
+U 1 1 687759D6
+P 4900 3050
+F 0 "X2" H 4900 3050 60 0000 C CNN
+F 1 "3_in_and" H 4900 2750 60 0000 C CNN
+F 2 "" H 4900 3050 60 0001 C CNN
+F 3 "" H 4900 3050 60 0001 C CNN
+ 1 4900 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_in_and X3
+U 1 1 68775A17
+P 4900 3750
+F 0 "X3" H 4900 3750 60 0000 C CNN
+F 1 "3_in_and" H 4900 3450 60 0000 C CNN
+F 2 "" H 4900 3750 60 0001 C CNN
+F 3 "" H 4900 3750 60 0001 C CNN
+ 1 4900 3750
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.cir b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.cir
new file mode 100644
index 000000000..e213b6679
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.cir
@@ -0,0 +1,33 @@
+* H:\esim\eSim\library\SubcircuitLibrary\SN74ALS1011A\SN74ALS1011A.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/25 19:42:49
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC6 Net-_SC1-Pad1_ Net-_SC5-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC3 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC3-Pad3_ Net-_SC2-Pad2_ Net-_SC4-Pad3_ Net-_SC4-Pad3_ sky130_fd_pr__nfet_01v8
+SC5 Net-_SC4-Pad3_ Net-_SC5-Pad2_ Net-_SC11-Pad3_ Net-_SC11-Pad3_ sky130_fd_pr__nfet_01v8
+SC7 Net-_SC12-Pad1_ Net-_SC7-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC8 Net-_SC12-Pad1_ Net-_SC10-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC12 Net-_SC12-Pad1_ Net-_SC11-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC9 Net-_SC12-Pad1_ Net-_SC7-Pad2_ Net-_SC10-Pad1_ Net-_SC10-Pad1_ sky130_fd_pr__nfet_01v8
+SC10 Net-_SC10-Pad1_ Net-_SC10-Pad2_ Net-_SC10-Pad3_ Net-_SC10-Pad3_ sky130_fd_pr__nfet_01v8
+SC11 Net-_SC10-Pad3_ Net-_SC11-Pad2_ Net-_SC11-Pad3_ Net-_SC11-Pad3_ sky130_fd_pr__nfet_01v8
+SC13 Net-_SC13-Pad1_ Net-_SC13-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC14 Net-_SC13-Pad1_ Net-_SC14-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC18 Net-_SC13-Pad1_ Net-_SC17-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC15 Net-_SC13-Pad1_ Net-_SC13-Pad2_ Net-_SC15-Pad3_ Net-_SC15-Pad3_ sky130_fd_pr__nfet_01v8
+SC16 Net-_SC15-Pad3_ Net-_SC14-Pad2_ Net-_SC16-Pad3_ Net-_SC16-Pad3_ sky130_fd_pr__nfet_01v8
+SC17 Net-_SC16-Pad3_ Net-_SC17-Pad2_ Net-_SC11-Pad3_ Net-_SC11-Pad3_ sky130_fd_pr__nfet_01v8
+X1 Net-_SC1-Pad1_ Net-_SC1-Pad3_ Net-_SC11-Pad3_ Net-_U1-Pad6_ CMOS_INVTR
+X2 Net-_SC12-Pad1_ Net-_SC1-Pad3_ Net-_SC11-Pad3_ Net-_U1-Pad10_ CMOS_INVTR
+X3 Net-_SC13-Pad1_ Net-_SC1-Pad3_ Net-_SC11-Pad3_ Net-_U1-Pad14_ CMOS_INVTR
+U1 Net-_SC2-Pad2_ Net-_SC1-Pad2_ Net-_SC5-Pad2_ Net-_SC11-Pad3_ Net-_SC1-Pad3_ Net-_U1-Pad6_ Net-_SC10-Pad2_ Net-_SC7-Pad2_ Net-_SC11-Pad2_ Net-_U1-Pad10_ Net-_SC14-Pad2_ Net-_SC13-Pad2_ Net-_SC17-Pad2_ Net-_U1-Pad14_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.cir.out b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.cir.out
new file mode 100644
index 000000000..4473a3274
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.cir.out
@@ -0,0 +1,42 @@
+* h:\esim\esim\library\subcircuitlibrary\sn74als1011a\sn74als1011a.cir
+
+.include CMOS_INVTR.sub
+.lib "H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spice" tt
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__r+c.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__pnp.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__linear.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__inductors.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc6 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc2-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc5-pad2_ net-_sc11-pad3_ net-_sc11-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc12-pad1_ net-_sc7-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc12-pad1_ net-_sc10-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc12 net-_sc12-pad1_ net-_sc11-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc9 net-_sc12-pad1_ net-_sc7-pad2_ net-_sc10-pad1_ net-_sc10-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc10 net-_sc10-pad1_ net-_sc10-pad2_ net-_sc10-pad3_ net-_sc10-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc11 net-_sc10-pad3_ net-_sc11-pad2_ net-_sc11-pad3_ net-_sc11-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc13 net-_sc13-pad1_ net-_sc13-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc14 net-_sc13-pad1_ net-_sc14-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc18 net-_sc13-pad1_ net-_sc17-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc15 net-_sc13-pad1_ net-_sc13-pad2_ net-_sc15-pad3_ net-_sc15-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc16 net-_sc15-pad3_ net-_sc14-pad2_ net-_sc16-pad3_ net-_sc16-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc17 net-_sc16-pad3_ net-_sc17-pad2_ net-_sc11-pad3_ net-_sc11-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+x1 net-_sc1-pad1_ net-_sc1-pad3_ net-_sc11-pad3_ net-_u1-pad6_ CMOS_INVTR
+x2 net-_sc12-pad1_ net-_sc1-pad3_ net-_sc11-pad3_ net-_u1-pad10_ CMOS_INVTR
+x3 net-_sc13-pad1_ net-_sc1-pad3_ net-_sc11-pad3_ net-_u1-pad14_ CMOS_INVTR
+* u1 net-_sc2-pad2_ net-_sc1-pad2_ net-_sc5-pad2_ net-_sc11-pad3_ net-_sc1-pad3_ net-_u1-pad6_ net-_sc10-pad2_ net-_sc7-pad2_ net-_sc11-pad2_ net-_u1-pad10_ net-_sc14-pad2_ net-_sc13-pad2_ net-_sc17-pad2_ net-_u1-pad14_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.pro b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.pro
new file mode 100644
index 000000000..bc66536a1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.pro
@@ -0,0 +1,74 @@
+update=07/16/25 13:11:19
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=SN74ALS1011A-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.sch b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.sch
new file mode 100644
index 000000000..e25e66845
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.sch
@@ -0,0 +1,739 @@
+EESchema Schematic File Version 2
+LIBS:SN74ALS1011A-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74ALS1011A-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 687F9C79
+P 1950 1450
+F 0 "SC1" H 2000 1750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 2250 1537 50 0000 R CNN
+F 2 "" H 1950 -50 50 0001 C CNN
+F 3 "" H 1950 1450 50 0001 C CNN
+ 1 1950 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 687F9CAD
+P 2700 1450
+F 0 "SC2" H 2750 1750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 3000 1537 50 0000 R CNN
+F 2 "" H 2700 -50 50 0001 C CNN
+F 3 "" H 2700 1450 50 0001 C CNN
+ 1 2700 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC6
+U 1 1 687F9D00
+P 3450 1450
+F 0 "SC6" H 3500 1750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 3750 1537 50 0000 R CNN
+F 2 "" H 3450 -50 50 0001 C CNN
+F 3 "" H 3450 1450 50 0001 C CNN
+ 1 3450 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 687F9DBF
+P 2700 2250
+F 0 "SC3" H 2750 2550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3000 2337 50 0000 R CNN
+F 2 "" H 2700 750 50 0001 C CNN
+F 3 "" H 2700 2250 50 0001 C CNN
+ 1 2700 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 687F9DEA
+P 2700 2950
+F 0 "SC4" H 2750 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3000 3037 50 0000 R CNN
+F 2 "" H 2700 1450 50 0001 C CNN
+F 3 "" H 2700 2950 50 0001 C CNN
+ 1 2700 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 687F9E8F
+P 3100 3650
+F 0 "SC5" H 3150 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 3400 3737 50 0000 R CNN
+F 2 "" H 3100 2150 50 0001 C CNN
+F 3 "" H 3100 3650 50 0001 C CNN
+ 1 3100 3650
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC7
+U 1 1 687FA621
+P 4850 1450
+F 0 "SC7" H 4900 1750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5150 1537 50 0000 R CNN
+F 2 "" H 4850 -50 50 0001 C CNN
+F 3 "" H 4850 1450 50 0001 C CNN
+ 1 4850 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC8
+U 1 1 687FA628
+P 5600 1450
+F 0 "SC8" H 5650 1750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5900 1537 50 0000 R CNN
+F 2 "" H 5600 -50 50 0001 C CNN
+F 3 "" H 5600 1450 50 0001 C CNN
+ 1 5600 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC12
+U 1 1 687FA62F
+P 6350 1450
+F 0 "SC12" H 6400 1750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6650 1537 50 0000 R CNN
+F 2 "" H 6350 -50 50 0001 C CNN
+F 3 "" H 6350 1450 50 0001 C CNN
+ 1 6350 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC9
+U 1 1 687FA636
+P 5600 2250
+F 0 "SC9" H 5650 2550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5900 2337 50 0000 R CNN
+F 2 "" H 5600 750 50 0001 C CNN
+F 3 "" H 5600 2250 50 0001 C CNN
+ 1 5600 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC10
+U 1 1 687FA63D
+P 5600 2950
+F 0 "SC10" H 5650 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5900 3037 50 0000 R CNN
+F 2 "" H 5600 1450 50 0001 C CNN
+F 3 "" H 5600 2950 50 0001 C CNN
+ 1 5600 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC11
+U 1 1 687FA644
+P 6000 3650
+F 0 "SC11" H 6050 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6300 3737 50 0000 R CNN
+F 2 "" H 6000 2150 50 0001 C CNN
+F 3 "" H 6000 3650 50 0001 C CNN
+ 1 6000 3650
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC13
+U 1 1 687FA842
+P 7700 1450
+F 0 "SC13" H 7750 1750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 8000 1537 50 0000 R CNN
+F 2 "" H 7700 -50 50 0001 C CNN
+F 3 "" H 7700 1450 50 0001 C CNN
+ 1 7700 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC14
+U 1 1 687FA849
+P 8450 1450
+F 0 "SC14" H 8500 1750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 8750 1537 50 0000 R CNN
+F 2 "" H 8450 -50 50 0001 C CNN
+F 3 "" H 8450 1450 50 0001 C CNN
+ 1 8450 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC18
+U 1 1 687FA850
+P 9200 1450
+F 0 "SC18" H 9250 1750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 9500 1537 50 0000 R CNN
+F 2 "" H 9200 -50 50 0001 C CNN
+F 3 "" H 9200 1450 50 0001 C CNN
+ 1 9200 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC15
+U 1 1 687FA857
+P 8450 2250
+F 0 "SC15" H 8500 2550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 8750 2337 50 0000 R CNN
+F 2 "" H 8450 750 50 0001 C CNN
+F 3 "" H 8450 2250 50 0001 C CNN
+ 1 8450 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC16
+U 1 1 687FA85E
+P 8450 2950
+F 0 "SC16" H 8500 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 8750 3037 50 0000 R CNN
+F 2 "" H 8450 1450 50 0001 C CNN
+F 3 "" H 8450 2950 50 0001 C CNN
+ 1 8450 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC17
+U 1 1 687FA865
+P 8850 3650
+F 0 "SC17" H 8900 3950 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 9150 3737 50 0000 R CNN
+F 2 "" H 8850 2150 50 0001 C CNN
+F 3 "" H 8850 3650 50 0001 C CNN
+ 1 8850 3650
+ -1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 687FA8D3
+P 3800 2400
+F 0 "X1" H 3800 2400 60 0000 C CNN
+F 1 "CMOS_INVTR" H 3750 2200 60 0000 C CNN
+F 2 "" H 3800 2400 60 0001 C CNN
+F 3 "" H 3800 2400 60 0001 C CNN
+ 1 3800 2400
+ 0 1 1 0
+$EndComp
+$Comp
+L CMOS_INVTR X2
+U 1 1 687FA92F
+P 6700 2400
+F 0 "X2" H 6700 2400 60 0000 C CNN
+F 1 "CMOS_INVTR" H 6650 2200 60 0000 C CNN
+F 2 "" H 6700 2400 60 0001 C CNN
+F 3 "" H 6700 2400 60 0001 C CNN
+ 1 6700 2400
+ 0 1 1 0
+$EndComp
+$Comp
+L CMOS_INVTR X3
+U 1 1 687FAA07
+P 9550 2450
+F 0 "X3" H 9550 2450 60 0000 C CNN
+F 1 "CMOS_INVTR" H 9500 2250 60 0000 C CNN
+F 2 "" H 9550 2450 60 0001 C CNN
+F 3 "" H 9550 2450 60 0001 C CNN
+ 1 9550 2450
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 1650 1450 1650 2250
+Wire Wire Line
+ 1650 2250 2400 2250
+Wire Wire Line
+ 2400 1450 2300 1450
+Wire Wire Line
+ 2300 1450 2300 2950
+Wire Wire Line
+ 2300 2950 2400 2950
+Wire Wire Line
+ 3150 1450 3150 3500
+Wire Wire Line
+ 3150 3500 3400 3500
+Wire Wire Line
+ 3400 3500 3400 3650
+Wire Wire Line
+ 2150 1150 2150 1100
+Wire Wire Line
+ 2150 1100 9650 1100
+Wire Wire Line
+ 3650 1100 3650 1150
+Wire Wire Line
+ 2050 1450 2200 1450
+Wire Wire Line
+ 2200 1450 2200 1100
+Connection ~ 2200 1100
+Wire Wire Line
+ 2800 1450 2950 1450
+Wire Wire Line
+ 2950 1450 2950 1100
+Connection ~ 2950 1100
+Wire Wire Line
+ 2900 1150 2900 1100
+Connection ~ 2900 1100
+Wire Wire Line
+ 3550 1450 3700 1450
+Wire Wire Line
+ 3700 1450 3700 1100
+Connection ~ 3650 1100
+Wire Wire Line
+ 2150 1750 2150 1800
+Wire Wire Line
+ 2150 1800 3800 1800
+Wire Wire Line
+ 3650 1800 3650 1750
+Wire Wire Line
+ 2900 1750 2900 1950
+Connection ~ 2900 1800
+Connection ~ 3650 1800
+Wire Wire Line
+ 3150 2000 3250 2000
+Connection ~ 3150 2000
+Wire Wire Line
+ 2300 2400 2150 2400
+Connection ~ 2300 2400
+Wire Wire Line
+ 1650 1900 1700 1900
+Connection ~ 1650 1900
+Wire Wire Line
+ 3000 3650 2850 3650
+Wire Wire Line
+ 2850 3650 2850 4000
+Wire Wire Line
+ 2850 3950 2900 3950
+Wire Wire Line
+ 2800 2950 2950 2950
+Wire Wire Line
+ 2950 2950 2950 3300
+Wire Wire Line
+ 2950 3300 2900 3300
+Wire Wire Line
+ 2900 3250 2900 3350
+Connection ~ 2900 3300
+Wire Wire Line
+ 2800 2250 2950 2250
+Wire Wire Line
+ 2950 2250 2950 2600
+Wire Wire Line
+ 2950 2600 2900 2600
+Wire Wire Line
+ 2900 2550 2900 2650
+Connection ~ 2900 2600
+Wire Wire Line
+ 4550 1450 4550 2250
+Wire Wire Line
+ 4550 2250 5300 2250
+Wire Wire Line
+ 5300 1450 5200 1450
+Wire Wire Line
+ 5200 1450 5200 2950
+Wire Wire Line
+ 5200 2950 5300 2950
+Wire Wire Line
+ 6050 1450 6050 3500
+Wire Wire Line
+ 6050 3500 6300 3500
+Wire Wire Line
+ 6300 3500 6300 3650
+Wire Wire Line
+ 5050 1100 5050 1150
+Wire Wire Line
+ 6550 1100 6550 1150
+Wire Wire Line
+ 4950 1450 5100 1450
+Wire Wire Line
+ 5100 1450 5100 1100
+Connection ~ 5100 1100
+Wire Wire Line
+ 5700 1450 5850 1450
+Wire Wire Line
+ 5850 1450 5850 1100
+Connection ~ 5850 1100
+Wire Wire Line
+ 5800 1150 5800 1100
+Connection ~ 5800 1100
+Wire Wire Line
+ 6450 1450 6600 1450
+Wire Wire Line
+ 6600 1450 6600 1100
+Connection ~ 6550 1100
+Wire Wire Line
+ 5050 1750 5050 1800
+Wire Wire Line
+ 5050 1800 6700 1800
+Wire Wire Line
+ 6550 1800 6550 1750
+Wire Wire Line
+ 5800 1750 5800 1950
+Connection ~ 5800 1800
+Connection ~ 6550 1800
+Wire Wire Line
+ 6050 2000 6150 2000
+Connection ~ 6050 2000
+Wire Wire Line
+ 5200 2400 5050 2400
+Connection ~ 5200 2400
+Wire Wire Line
+ 4550 1900 4600 1900
+Connection ~ 4550 1900
+Wire Wire Line
+ 5900 3650 5750 3650
+Wire Wire Line
+ 5750 3650 5750 4000
+Wire Wire Line
+ 5750 3950 5800 3950
+Wire Wire Line
+ 5700 2950 5850 2950
+Wire Wire Line
+ 5850 2950 5850 3300
+Wire Wire Line
+ 5850 3300 5800 3300
+Wire Wire Line
+ 5800 3250 5800 3350
+Connection ~ 5800 3300
+Wire Wire Line
+ 5700 2250 5850 2250
+Wire Wire Line
+ 5850 2250 5850 2600
+Wire Wire Line
+ 5850 2600 5800 2600
+Wire Wire Line
+ 5800 2550 5800 2650
+Connection ~ 5800 2600
+Wire Wire Line
+ 7400 1450 7400 2250
+Wire Wire Line
+ 7400 2250 8150 2250
+Wire Wire Line
+ 8150 1450 8050 1450
+Wire Wire Line
+ 8050 1450 8050 2950
+Wire Wire Line
+ 8050 2950 8150 2950
+Wire Wire Line
+ 8900 1450 8900 3500
+Wire Wire Line
+ 8900 3500 9150 3500
+Wire Wire Line
+ 9150 3500 9150 3650
+Wire Wire Line
+ 7900 1100 7900 1150
+Wire Wire Line
+ 9400 1100 9400 1150
+Wire Wire Line
+ 7800 1450 7950 1450
+Wire Wire Line
+ 7950 1450 7950 1100
+Connection ~ 7950 1100
+Wire Wire Line
+ 8550 1450 8700 1450
+Wire Wire Line
+ 8700 1450 8700 1100
+Connection ~ 8700 1100
+Wire Wire Line
+ 8650 1150 8650 1100
+Connection ~ 8650 1100
+Wire Wire Line
+ 9300 1450 9450 1450
+Wire Wire Line
+ 9450 1450 9450 1100
+Connection ~ 9400 1100
+Wire Wire Line
+ 7900 1750 7900 1800
+Wire Wire Line
+ 7900 1800 9550 1800
+Wire Wire Line
+ 9400 1800 9400 1750
+Wire Wire Line
+ 8650 1750 8650 1950
+Connection ~ 8650 1800
+Connection ~ 9400 1800
+Wire Wire Line
+ 8900 2000 9000 2000
+Connection ~ 8900 2000
+Wire Wire Line
+ 8050 2400 7900 2400
+Connection ~ 8050 2400
+Wire Wire Line
+ 7400 1900 7450 1900
+Connection ~ 7400 1900
+Wire Wire Line
+ 8750 3650 8600 3650
+Wire Wire Line
+ 8600 3650 8600 4000
+Wire Wire Line
+ 8600 3950 8650 3950
+Wire Wire Line
+ 8550 2950 8700 2950
+Wire Wire Line
+ 8700 2950 8700 3300
+Wire Wire Line
+ 8700 3300 8650 3300
+Wire Wire Line
+ 8650 3250 8650 3350
+Connection ~ 8650 3300
+Wire Wire Line
+ 8550 2250 8700 2250
+Wire Wire Line
+ 8700 2250 8700 2600
+Wire Wire Line
+ 8700 2600 8650 2600
+Wire Wire Line
+ 8650 2550 8650 2650
+Connection ~ 8650 2600
+Wire Wire Line
+ 9550 1800 9550 2000
+Wire Wire Line
+ 9450 2000 9400 2000
+Wire Wire Line
+ 9400 2000 9400 4000
+Wire Wire Line
+ 9400 4000 2850 4000
+Connection ~ 8600 3950
+Wire Wire Line
+ 9650 1100 9650 2000
+Connection ~ 9450 1100
+Wire Wire Line
+ 6700 1800 6700 1950
+Wire Wire Line
+ 6600 1950 6550 1950
+Wire Wire Line
+ 6550 1950 6550 4000
+Connection ~ 5750 3950
+Wire Wire Line
+ 6800 1100 6800 1950
+Connection ~ 6600 1100
+Wire Wire Line
+ 3800 1800 3800 1950
+Wire Wire Line
+ 3700 1950 3650 1950
+Wire Wire Line
+ 3650 1950 3650 4000
+Connection ~ 2850 3950
+Wire Wire Line
+ 3900 1100 3900 1950
+Connection ~ 3700 1100
+Connection ~ 5050 1100
+Connection ~ 3900 1100
+Connection ~ 7900 1100
+Connection ~ 6800 1100
+Connection ~ 8600 4000
+Connection ~ 6550 4000
+Connection ~ 5750 4000
+Connection ~ 3650 4000
+$Comp
+L PORT U1
+U 5 1 687FBF6D
+P 3900 850
+F 0 "U1" H 3950 950 30 0000 C CNN
+F 1 "PORT" H 3900 850 30 0000 C CNN
+F 2 "" H 3900 850 60 0000 C CNN
+F 3 "" H 3900 850 60 0000 C CNN
+ 5 3900 850
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 2 1 687FC210
+P 1950 1900
+F 0 "U1" H 2000 2000 30 0000 C CNN
+F 1 "PORT" H 1950 1900 30 0000 C CNN
+F 2 "" H 1950 1900 60 0000 C CNN
+F 3 "" H 1950 1900 60 0000 C CNN
+ 2 1950 1900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 687FC2CE
+P 1900 2400
+F 0 "U1" H 1950 2500 30 0000 C CNN
+F 1 "PORT" H 1900 2400 30 0000 C CNN
+F 2 "" H 1900 2400 60 0000 C CNN
+F 3 "" H 1900 2400 60 0000 C CNN
+ 1 1900 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 687FC333
+P 3250 2250
+F 0 "U1" H 3300 2350 30 0000 C CNN
+F 1 "PORT" H 3250 2250 30 0000 C CNN
+F 2 "" H 3250 2250 60 0000 C CNN
+F 3 "" H 3250 2250 60 0000 C CNN
+ 3 3250 2250
+ 0 1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 6 1 687FC39A
+P 4050 2900
+F 0 "U1" H 4100 3000 30 0000 C CNN
+F 1 "PORT" H 4050 2900 30 0000 C CNN
+F 2 "" H 4050 2900 60 0000 C CNN
+F 3 "" H 4050 2900 60 0000 C CNN
+ 6 4050 2900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 687FC537
+P 3650 4250
+F 0 "U1" H 3700 4350 30 0000 C CNN
+F 1 "PORT" H 3650 4250 30 0000 C CNN
+F 2 "" H 3650 4250 60 0000 C CNN
+F 3 "" H 3650 4250 60 0000 C CNN
+ 4 3650 4250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 8 1 687FC6F4
+P 4850 1900
+F 0 "U1" H 4900 2000 30 0000 C CNN
+F 1 "PORT" H 4850 1900 30 0000 C CNN
+F 2 "" H 4850 1900 60 0000 C CNN
+F 3 "" H 4850 1900 60 0000 C CNN
+ 8 4850 1900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 687FC787
+P 4800 2400
+F 0 "U1" H 4850 2500 30 0000 C CNN
+F 1 "PORT" H 4800 2400 30 0000 C CNN
+F 2 "" H 4800 2400 60 0000 C CNN
+F 3 "" H 4800 2400 60 0000 C CNN
+ 7 4800 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 687FC84E
+P 6150 2250
+F 0 "U1" H 6200 2350 30 0000 C CNN
+F 1 "PORT" H 6150 2250 30 0000 C CNN
+F 2 "" H 6150 2250 60 0000 C CNN
+F 3 "" H 6150 2250 60 0000 C CNN
+ 9 6150 2250
+ 0 1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 10 1 687FC8F4
+P 6950 2900
+F 0 "U1" H 7000 3000 30 0000 C CNN
+F 1 "PORT" H 6950 2900 30 0000 C CNN
+F 2 "" H 6950 2900 60 0000 C CNN
+F 3 "" H 6950 2900 60 0000 C CNN
+ 10 6950 2900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 687FCA0D
+P 7700 1900
+F 0 "U1" H 7750 2000 30 0000 C CNN
+F 1 "PORT" H 7700 1900 30 0000 C CNN
+F 2 "" H 7700 1900 60 0000 C CNN
+F 3 "" H 7700 1900 60 0000 C CNN
+ 12 7700 1900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 687FCA6A
+P 7650 2400
+F 0 "U1" H 7700 2500 30 0000 C CNN
+F 1 "PORT" H 7650 2400 30 0000 C CNN
+F 2 "" H 7650 2400 60 0000 C CNN
+F 3 "" H 7650 2400 60 0000 C CNN
+ 11 7650 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 687FCBCF
+P 9000 2250
+F 0 "U1" H 9050 2350 30 0000 C CNN
+F 1 "PORT" H 9000 2250 30 0000 C CNN
+F 2 "" H 9000 2250 60 0000 C CNN
+F 3 "" H 9000 2250 60 0000 C CNN
+ 13 9000 2250
+ 0 1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 14 1 687FCD4D
+P 9800 2950
+F 0 "U1" H 9850 3050 30 0000 C CNN
+F 1 "PORT" H 9800 2950 30 0000 C CNN
+F 2 "" H 9800 2950 60 0000 C CNN
+F 3 "" H 9800 2950 60 0000 C CNN
+ 14 9800 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 687FCE65
+P 7650 3600
+F 0 "scmode1" H 7650 3750 98 0000 C CNB
+F 1 "SKY130mode" H 7650 3500 118 0000 C CNB
+F 2 "" H 7650 3750 60 0001 C CNN
+F 3 "" H 7650 3750 60 0001 C CNN
+ 1 7650 3600
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.sub b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.sub
new file mode 100644
index 000000000..9c3996400
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A.sub
@@ -0,0 +1,36 @@
+* Subcircuit SN74ALS1011A
+.subckt SN74ALS1011A net-_sc2-pad2_ net-_sc1-pad2_ net-_sc5-pad2_ net-_sc11-pad3_ net-_sc1-pad3_ net-_u1-pad6_ net-_sc10-pad2_ net-_sc7-pad2_ net-_sc11-pad2_ net-_u1-pad10_ net-_sc14-pad2_ net-_sc13-pad2_ net-_sc17-pad2_ net-_u1-pad14_
+* h:\esim\esim\library\subcircuitlibrary\sn74als1011a\sn74als1011a.cir
+.include CMOS_INVTR.sub
+.lib "H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spice" tt
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__diode_pd2nw_11v0.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__r+c.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__pnp.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__linear.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__diode_pw2nd_11v0.model.spice"
+.include "H:\esim\eSim\library\sky130_fd_pr\models\sky130_fd_pr__model__inductors.model.spice"
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc6 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc2-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc5-pad2_ net-_sc11-pad3_ net-_sc11-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc12-pad1_ net-_sc7-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc12-pad1_ net-_sc10-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc12 net-_sc12-pad1_ net-_sc11-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc9 net-_sc12-pad1_ net-_sc7-pad2_ net-_sc10-pad1_ net-_sc10-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc10 net-_sc10-pad1_ net-_sc10-pad2_ net-_sc10-pad3_ net-_sc10-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc11 net-_sc10-pad3_ net-_sc11-pad2_ net-_sc11-pad3_ net-_sc11-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc13 net-_sc13-pad1_ net-_sc13-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc14 net-_sc13-pad1_ net-_sc14-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc18 net-_sc13-pad1_ net-_sc17-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc15 net-_sc13-pad1_ net-_sc13-pad2_ net-_sc15-pad3_ net-_sc15-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc16 net-_sc15-pad3_ net-_sc14-pad2_ net-_sc16-pad3_ net-_sc16-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc17 net-_sc16-pad3_ net-_sc17-pad2_ net-_sc11-pad3_ net-_sc11-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+x1 net-_sc1-pad1_ net-_sc1-pad3_ net-_sc11-pad3_ net-_u1-pad6_ CMOS_INVTR
+x2 net-_sc12-pad1_ net-_sc1-pad3_ net-_sc11-pad3_ net-_u1-pad10_ CMOS_INVTR
+x3 net-_sc13-pad1_ net-_sc1-pad3_ net-_sc11-pad3_ net-_u1-pad14_ CMOS_INVTR
+* s c m o d e
+* Control Statements
+
+.ends SN74ALS1011A
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A_Previous_Values.xml b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A_Previous_Values.xml
new file mode 100644
index 000000000..020905d17
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/SN74ALS1011A_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15H:\esim\eSim\library\SubcircuitLibrary\CMOS_INVTRH:\esim\eSim\library\SubcircuitLibrary\CMOS_INVTRH:\esim\eSim\library\SubcircuitLibrary\CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74ALS1011A/analysis b/library/SubcircuitLibrary/SN74ALS1011A/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74ALS1011A/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58-cache.lib b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58-cache.lib
new file mode 100644
index 000000000..c743d042c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir
new file mode 100644
index 000000000..bcc97dfc0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir
@@ -0,0 +1,17 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74AUP1G58\SN74AUP1G58.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 20:55:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7 Net-_U1-Pad3_ Net-_U4-Pad1_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
+U3 Net-_U1-Pad6_ Net-_U3-Pad2_ d_inverter
+U4 Net-_U4-Pad1_ Net-_U3-Pad2_ Net-_U4-Pad3_ d_and
+U5 Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U5-Pad3_ d_nor
+U6 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad4_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad6_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir.out b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir.out
new file mode 100644
index 000000000..9f7fa54fe
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.cir.out
@@ -0,0 +1,36 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74aup1g58\sn74aup1g58.cir
+
+* u7 net-_u1-pad3_ net-_u4-pad1_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad6_ net-_u3-pad2_ d_inverter
+* u4 net-_u4-pad1_ net-_u3-pad2_ net-_u4-pad3_ d_and
+* u5 net-_u2-pad2_ net-_u3-pad2_ net-_u5-pad3_ d_nor
+* u6 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad4_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_ port
+a1 net-_u1-pad3_ net-_u4-pad1_ u7
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad6_ net-_u3-pad2_ u3
+a4 [net-_u4-pad1_ net-_u3-pad2_ ] net-_u4-pad3_ u4
+a5 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad4_ u6
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 250e-03 10e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.pro b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sch b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sch
new file mode 100644
index 000000000..8b1d44e3f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sch
@@ -0,0 +1,199 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U7
+U 1 1 685AC144
+P 4800 3050
+F 0 "U7" H 4800 2950 60 0000 C CNN
+F 1 "d_inverter" H 4800 3200 60 0000 C CNN
+F 2 "" H 4850 3000 60 0000 C CNN
+F 3 "" H 4850 3000 60 0000 C CNN
+ 1 4800 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 685AC16D
+P 4800 3700
+F 0 "U2" H 4800 3600 60 0000 C CNN
+F 1 "d_inverter" H 4800 3850 60 0000 C CNN
+F 2 "" H 4850 3650 60 0000 C CNN
+F 3 "" H 4850 3650 60 0000 C CNN
+ 1 4800 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 685AC19E
+P 4800 4400
+F 0 "U3" H 4800 4300 60 0000 C CNN
+F 1 "d_inverter" H 4800 4550 60 0000 C CNN
+F 2 "" H 4850 4350 60 0000 C CNN
+F 3 "" H 4850 4350 60 0000 C CNN
+ 1 4800 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 685AC1E0
+P 6900 3350
+F 0 "U4" H 6900 3350 60 0000 C CNN
+F 1 "d_and" H 6950 3450 60 0000 C CNN
+F 2 "" H 6900 3350 60 0000 C CNN
+F 3 "" H 6900 3350 60 0000 C CNN
+ 1 6900 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U5
+U 1 1 685AC23D
+P 6900 4000
+F 0 "U5" H 6900 4000 60 0000 C CNN
+F 1 "d_nor" H 6950 4100 60 0000 C CNN
+F 2 "" H 6900 4000 60 0000 C CNN
+F 3 "" H 6900 4000 60 0000 C CNN
+ 1 6900 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 685AC29F
+P 8450 3650
+F 0 "U6" H 8450 3650 60 0000 C CNN
+F 1 "d_nor" H 8500 3750 60 0000 C CNN
+F 2 "" H 8450 3650 60 0000 C CNN
+F 3 "" H 8450 3650 60 0000 C CNN
+ 1 8450 3650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5100 3050 6450 3050
+Wire Wire Line
+ 6450 3050 6450 3250
+Wire Wire Line
+ 5100 4400 6000 4400
+Wire Wire Line
+ 6000 4400 6000 3350
+Wire Wire Line
+ 6000 3350 6450 3350
+Wire Wire Line
+ 5100 3700 6450 3700
+Wire Wire Line
+ 6450 3700 6450 3900
+Wire Wire Line
+ 6000 4000 6450 4000
+Connection ~ 6000 4000
+Wire Wire Line
+ 7350 3300 7350 3550
+Wire Wire Line
+ 7350 3550 8000 3550
+Wire Wire Line
+ 7350 3950 7350 3650
+Wire Wire Line
+ 7350 3650 8000 3650
+$Comp
+L PORT U1
+U 1 1 685AC4F6
+P 4000 3700
+F 0 "U1" H 4050 3800 30 0000 C CNN
+F 1 "PORT" H 4000 3700 30 0000 C CNN
+F 2 "" H 4000 3700 60 0000 C CNN
+F 3 "" H 4000 3700 60 0000 C CNN
+ 1 4000 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685AC57C
+P 4000 3050
+F 0 "U1" H 4050 3150 30 0000 C CNN
+F 1 "PORT" H 4000 3050 30 0000 C CNN
+F 2 "" H 4000 3050 60 0000 C CNN
+F 3 "" H 4000 3050 60 0000 C CNN
+ 3 4000 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685AC5C3
+P 9500 3600
+F 0 "U1" H 9550 3700 30 0000 C CNN
+F 1 "PORT" H 9500 3600 30 0000 C CNN
+F 2 "" H 9500 3600 60 0000 C CNN
+F 3 "" H 9500 3600 60 0000 C CNN
+ 4 9500 3600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685AC803
+P 4100 4400
+F 0 "U1" H 4150 4500 30 0000 C CNN
+F 1 "PORT" H 4100 4400 30 0000 C CNN
+F 2 "" H 4100 4400 60 0000 C CNN
+F 3 "" H 4100 4400 60 0000 C CNN
+ 6 4100 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4250 3050 4500 3050
+Wire Wire Line
+ 4250 3700 4500 3700
+Wire Wire Line
+ 4350 4400 4500 4400
+Wire Wire Line
+ 8900 3600 9250 3600
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sub b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sub
new file mode 100644
index 000000000..664a5de6c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58.sub
@@ -0,0 +1,30 @@
+* Subcircuit SN74AUP1G58
+.subckt SN74AUP1G58 net-_u1-pad1_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad6_
+* c:\fossee\esim\library\subcircuitlibrary\sn74aup1g58\sn74aup1g58.cir
+* u7 net-_u1-pad3_ net-_u4-pad1_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u1-pad6_ net-_u3-pad2_ d_inverter
+* u4 net-_u4-pad1_ net-_u3-pad2_ net-_u4-pad3_ d_and
+* u5 net-_u2-pad2_ net-_u3-pad2_ net-_u5-pad3_ d_nor
+* u6 net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad4_ d_nor
+a1 net-_u1-pad3_ net-_u4-pad1_ u7
+a2 net-_u1-pad1_ net-_u2-pad2_ u2
+a3 net-_u1-pad6_ net-_u3-pad2_ u3
+a4 [net-_u4-pad1_ net-_u3-pad2_ ] net-_u4-pad3_ u4
+a5 [net-_u2-pad2_ net-_u3-pad2_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad4_ u6
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74AUP1G58
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58_Previous_Values.xml b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58_Previous_Values.xml
new file mode 100644
index 000000000..a0ba30aa8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74AUP1G58/SN74AUP1G58_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_inverterd_inverterd_inverterd_andd_nord_nor
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74AUP1G58/analysis b/library/SubcircuitLibrary/SN74AUP1G58/analysis
new file mode 100644
index 000000000..0a6c83b5a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74AUP1G58/analysis
@@ -0,0 +1 @@
+.tran 250e-03 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H53/3_and-cache.lib b/library/SubcircuitLibrary/SN74H53/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H53/3_and.cir b/library/SubcircuitLibrary/SN74H53/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H53/3_and.cir.out b/library/SubcircuitLibrary/SN74H53/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H53/3_and.pro b/library/SubcircuitLibrary/SN74H53/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74H53/3_and.sch b/library/SubcircuitLibrary/SN74H53/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H53/3_and.sub b/library/SubcircuitLibrary/SN74H53/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H53/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74H53/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53-cache.lib b/library/SubcircuitLibrary/SN74H53/SN74H53-cache.lib
new file mode 100644
index 000000000..8256d8a65
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/SN74H53-cache.lib
@@ -0,0 +1,112 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.cir b/library/SubcircuitLibrary/SN74H53/SN74H53.cir
new file mode 100644
index 000000000..3d277aadc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/SN74H53.cir
@@ -0,0 +1,22 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74H53\SN74H53.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/25 08:17:09
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad13_ Net-_U2-Pad3_ d_and
+U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_and
+U4 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_and
+X1 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U7-Pad1_ 3_and
+U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_or
+U7 Net-_U7-Pad1_ Net-_U4-Pad3_ Net-_U7-Pad3_ d_or
+U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U10-Pad1_ d_or
+U9 Net-_U1-Pad11_ Net-_U5-Pad2_ Net-_U10-Pad2_ d_or
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or
+U5 Net-_U1-Pad12_ Net-_U5-Pad2_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT
+U11 Net-_U10-Pad3_ Net-_U1-Pad8_ d_inverter
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.cir.out b/library/SubcircuitLibrary/SN74H53/SN74H53.cir.out
new file mode 100644
index 000000000..ec18a34d7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/SN74H53.cir.out
@@ -0,0 +1,54 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74h53\sn74h53.cir
+
+.include 3_and.sub
+* u2 net-_u1-pad1_ net-_u1-pad13_ net-_u2-pad3_ d_and
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u7-pad1_ 3_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_or
+* u7 net-_u7-pad1_ net-_u4-pad3_ net-_u7-pad3_ d_or
+* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_or
+* u9 net-_u1-pad11_ net-_u5-pad2_ net-_u10-pad2_ d_or
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
+* u5 net-_u1-pad12_ net-_u5-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u11 net-_u10-pad3_ net-_u1-pad8_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad13_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a5 [net-_u7-pad1_ net-_u4-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8
+a7 [net-_u1-pad11_ net-_u5-pad2_ ] net-_u10-pad2_ u9
+a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a9 net-_u1-pad12_ net-_u5-pad2_ u5
+a10 net-_u10-pad3_ net-_u1-pad8_ u11
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.pro b/library/SubcircuitLibrary/SN74H53/SN74H53.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/SN74H53.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.sch b/library/SubcircuitLibrary/SN74H53/SN74H53.sch
new file mode 100644
index 000000000..78a53dd2a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/SN74H53.sch
@@ -0,0 +1,410 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74H53-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 685CA412
+P 4150 2200
+F 0 "U2" H 4150 2200 60 0000 C CNN
+F 1 "d_and" H 4200 2300 60 0000 C CNN
+F 2 "" H 4150 2200 60 0000 C CNN
+F 3 "" H 4150 2200 60 0000 C CNN
+ 1 4150 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 685CA450
+P 4150 2550
+F 0 "U3" H 4150 2550 60 0000 C CNN
+F 1 "d_and" H 4200 2650 60 0000 C CNN
+F 2 "" H 4150 2550 60 0000 C CNN
+F 3 "" H 4150 2550 60 0000 C CNN
+ 1 4150 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 685CA478
+P 4200 3750
+F 0 "U4" H 4200 3750 60 0000 C CNN
+F 1 "d_and" H 4250 3850 60 0000 C CNN
+F 2 "" H 4200 3750 60 0000 C CNN
+F 3 "" H 4200 3750 60 0000 C CNN
+ 1 4200 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 685CA4B6
+P 4100 3150
+F 0 "X1" H 4200 3100 60 0000 C CNN
+F 1 "3_and" H 4250 3300 60 0000 C CNN
+F 2 "" H 4100 3150 60 0000 C CNN
+F 3 "" H 4100 3150 60 0000 C CNN
+ 1 4100 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U6
+U 1 1 685CA4FB
+P 5350 2350
+F 0 "U6" H 5350 2350 60 0000 C CNN
+F 1 "d_or" H 5350 2450 60 0000 C CNN
+F 2 "" H 5350 2350 60 0000 C CNN
+F 3 "" H 5350 2350 60 0000 C CNN
+ 1 5350 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U7
+U 1 1 685CA535
+P 5350 3400
+F 0 "U7" H 5350 3400 60 0000 C CNN
+F 1 "d_or" H 5350 3500 60 0000 C CNN
+F 2 "" H 5350 3400 60 0000 C CNN
+F 3 "" H 5350 3400 60 0000 C CNN
+ 1 5350 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U8
+U 1 1 685CA57B
+P 6400 2800
+F 0 "U8" H 6400 2800 60 0000 C CNN
+F 1 "d_or" H 6400 2900 60 0000 C CNN
+F 2 "" H 6400 2800 60 0000 C CNN
+F 3 "" H 6400 2800 60 0000 C CNN
+ 1 6400 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U9
+U 1 1 685CA5C0
+P 6400 4250
+F 0 "U9" H 6400 4250 60 0000 C CNN
+F 1 "d_or" H 6400 4350 60 0000 C CNN
+F 2 "" H 6400 4250 60 0000 C CNN
+F 3 "" H 6400 4250 60 0000 C CNN
+ 1 6400 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U10
+U 1 1 685CA616
+P 7700 3250
+F 0 "U10" H 7700 3250 60 0000 C CNN
+F 1 "d_or" H 7700 3350 60 0000 C CNN
+F 2 "" H 7700 3250 60 0000 C CNN
+F 3 "" H 7700 3250 60 0000 C CNN
+ 1 7700 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4600 2150 4900 2150
+Wire Wire Line
+ 4900 2150 4900 2250
+Wire Wire Line
+ 4600 2500 4900 2500
+Wire Wire Line
+ 4900 2500 4900 2350
+Wire Wire Line
+ 5800 2300 5900 2300
+Wire Wire Line
+ 5900 2300 5900 2700
+Wire Wire Line
+ 5900 2700 5950 2700
+Wire Wire Line
+ 4600 3100 4900 3100
+Wire Wire Line
+ 4900 3100 4900 3300
+Wire Wire Line
+ 4650 3700 4900 3700
+Wire Wire Line
+ 4900 3700 4900 3400
+Wire Wire Line
+ 5800 3350 5800 2800
+Wire Wire Line
+ 5800 2800 5950 2800
+Wire Wire Line
+ 6850 2750 7250 2750
+Wire Wire Line
+ 7250 2750 7250 3150
+Wire Wire Line
+ 6850 4200 7250 4200
+Wire Wire Line
+ 7250 4200 7250 3250
+$Comp
+L d_inverter U5
+U 1 1 685CA710
+P 5250 4450
+F 0 "U5" H 5250 4350 60 0000 C CNN
+F 1 "d_inverter" H 5250 4600 60 0000 C CNN
+F 2 "" H 5300 4400 60 0000 C CNN
+F 3 "" H 5300 4400 60 0000 C CNN
+ 1 5250 4450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 4450 5950 4450
+Wire Wire Line
+ 5950 4450 5950 4250
+$Comp
+L PORT U1
+U 1 1 685CA792
+P 3350 2100
+F 0 "U1" H 3400 2200 30 0000 C CNN
+F 1 "PORT" H 3350 2100 30 0000 C CNN
+F 2 "" H 3350 2100 60 0000 C CNN
+F 3 "" H 3350 2100 60 0000 C CNN
+ 1 3350 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685CA801
+P 3350 2400
+F 0 "U1" H 3400 2500 30 0000 C CNN
+F 1 "PORT" H 3350 2400 30 0000 C CNN
+F 2 "" H 3350 2400 60 0000 C CNN
+F 3 "" H 3350 2400 60 0000 C CNN
+ 2 3350 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685CA83A
+P 3350 2550
+F 0 "U1" H 3400 2650 30 0000 C CNN
+F 1 "PORT" H 3350 2550 30 0000 C CNN
+F 2 "" H 3350 2550 60 0000 C CNN
+F 3 "" H 3350 2550 60 0000 C CNN
+ 3 3350 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685CA869
+P 3350 2900
+F 0 "U1" H 3400 3000 30 0000 C CNN
+F 1 "PORT" H 3350 2900 30 0000 C CNN
+F 2 "" H 3350 2900 60 0000 C CNN
+F 3 "" H 3350 2900 60 0000 C CNN
+ 4 3350 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685CA89E
+P 3350 3100
+F 0 "U1" H 3400 3200 30 0000 C CNN
+F 1 "PORT" H 3350 3100 30 0000 C CNN
+F 2 "" H 3350 3100 60 0000 C CNN
+F 3 "" H 3350 3100 60 0000 C CNN
+ 5 3350 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685CA8D1
+P 3350 3300
+F 0 "U1" H 3400 3400 30 0000 C CNN
+F 1 "PORT" H 3350 3300 30 0000 C CNN
+F 2 "" H 3350 3300 60 0000 C CNN
+F 3 "" H 3350 3300 60 0000 C CNN
+ 6 3350 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685CA910
+P 7150 2100
+F 0 "U1" H 7200 2200 30 0000 C CNN
+F 1 "PORT" H 7150 2100 30 0000 C CNN
+F 2 "" H 7150 2100 60 0000 C CNN
+F 3 "" H 7150 2100 60 0000 C CNN
+ 7 7150 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685CA985
+P 9300 3200
+F 0 "U1" H 9350 3300 30 0000 C CNN
+F 1 "PORT" H 9300 3200 30 0000 C CNN
+F 2 "" H 9300 3200 60 0000 C CNN
+F 3 "" H 9300 3200 60 0000 C CNN
+ 8 9300 3200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685CA9C0
+P 3350 3600
+F 0 "U1" H 3400 3700 30 0000 C CNN
+F 1 "PORT" H 3350 3600 30 0000 C CNN
+F 2 "" H 3350 3600 60 0000 C CNN
+F 3 "" H 3350 3600 60 0000 C CNN
+ 9 3350 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685CA9FB
+P 3350 3800
+F 0 "U1" H 3400 3900 30 0000 C CNN
+F 1 "PORT" H 3350 3800 30 0000 C CNN
+F 2 "" H 3350 3800 60 0000 C CNN
+F 3 "" H 3350 3800 60 0000 C CNN
+ 10 3350 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685CAA3C
+P 3350 4150
+F 0 "U1" H 3400 4250 30 0000 C CNN
+F 1 "PORT" H 3350 4150 30 0000 C CNN
+F 2 "" H 3350 4150 60 0000 C CNN
+F 3 "" H 3350 4150 60 0000 C CNN
+ 11 3350 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685CAA7D
+P 3350 4450
+F 0 "U1" H 3400 4550 30 0000 C CNN
+F 1 "PORT" H 3350 4450 30 0000 C CNN
+F 2 "" H 3350 4450 60 0000 C CNN
+F 3 "" H 3350 4450 60 0000 C CNN
+ 12 3350 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685CAAC4
+P 3350 2250
+F 0 "U1" H 3400 2350 30 0000 C CNN
+F 1 "PORT" H 3350 2250 30 0000 C CNN
+F 2 "" H 3350 2250 60 0000 C CNN
+F 3 "" H 3350 2250 60 0000 C CNN
+ 13 3350 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685CAB07
+P 7150 2300
+F 0 "U1" H 7200 2400 30 0000 C CNN
+F 1 "PORT" H 7150 2300 30 0000 C CNN
+F 2 "" H 7150 2300 60 0000 C CNN
+F 3 "" H 7150 2300 60 0000 C CNN
+ 14 7150 2300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3600 2100 3700 2100
+Wire Wire Line
+ 3600 2250 3700 2250
+Wire Wire Line
+ 3700 2250 3700 2200
+Wire Wire Line
+ 3600 2400 3700 2400
+Wire Wire Line
+ 3700 2400 3700 2450
+Wire Wire Line
+ 3600 2550 3700 2550
+Wire Wire Line
+ 3600 2900 3750 2900
+Wire Wire Line
+ 3750 2900 3750 3000
+Wire Wire Line
+ 3600 3100 3750 3100
+Wire Wire Line
+ 3600 3300 3750 3300
+Wire Wire Line
+ 3750 3300 3750 3200
+Wire Wire Line
+ 3600 3600 3750 3600
+Wire Wire Line
+ 3750 3600 3750 3650
+Wire Wire Line
+ 3600 3800 3750 3800
+Wire Wire Line
+ 3750 3800 3750 3750
+Wire Wire Line
+ 3600 4150 5950 4150
+Wire Wire Line
+ 3600 4450 4950 4450
+NoConn ~ 7400 2100
+NoConn ~ 7400 2300
+$Comp
+L d_inverter U11
+U 1 1 685CDB2C
+P 8550 3200
+F 0 "U11" H 8550 3100 60 0000 C CNN
+F 1 "d_inverter" H 8550 3350 60 0000 C CNN
+F 2 "" H 8600 3150 60 0000 C CNN
+F 3 "" H 8600 3150 60 0000 C CNN
+ 1 8550 3200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8850 3200 9050 3200
+Wire Wire Line
+ 8250 3200 8150 3200
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53.sub b/library/SubcircuitLibrary/SN74H53/SN74H53.sub
new file mode 100644
index 000000000..f0445f685
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/SN74H53.sub
@@ -0,0 +1,48 @@
+* Subcircuit SN74H53
+.subckt SN74H53 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ?
+* c:\fossee\esim\library\subcircuitlibrary\sn74h53\sn74h53.cir
+.include 3_and.sub
+* u2 net-_u1-pad1_ net-_u1-pad13_ net-_u2-pad3_ d_and
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_and
+x1 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u7-pad1_ 3_and
+* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_or
+* u7 net-_u7-pad1_ net-_u4-pad3_ net-_u7-pad3_ d_or
+* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_or
+* u9 net-_u1-pad11_ net-_u5-pad2_ net-_u10-pad2_ d_or
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or
+* u5 net-_u1-pad12_ net-_u5-pad2_ d_inverter
+* u11 net-_u10-pad3_ net-_u1-pad8_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad13_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a4 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6
+a5 [net-_u7-pad1_ net-_u4-pad3_ ] net-_u7-pad3_ u7
+a6 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8
+a7 [net-_u1-pad11_ net-_u5-pad2_ ] net-_u10-pad2_ u9
+a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a9 net-_u1-pad12_ net-_u5-pad2_ u5
+a10 net-_u10-pad3_ net-_u1-pad8_ u11
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74H53
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H53/SN74H53_Previous_Values.xml b/library/SubcircuitLibrary/SN74H53/SN74H53_Previous_Values.xml
new file mode 100644
index 000000000..9c440c9a6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/SN74H53_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andd_andd_ord_ord_ord_ord_ord_inverterd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H53/analysis b/library/SubcircuitLibrary/SN74H53/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H53/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H55/3_and-cache.lib b/library/SubcircuitLibrary/SN74H55/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H55/3_and.cir b/library/SubcircuitLibrary/SN74H55/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H55/3_and.cir.out b/library/SubcircuitLibrary/SN74H55/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H55/3_and.pro b/library/SubcircuitLibrary/SN74H55/3_and.pro
new file mode 100644
index 000000000..06813ca78
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/3_and.pro
@@ -0,0 +1,43 @@
+update=Wed Mar 18 19:54:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/SN74H55/3_and.sch b/library/SubcircuitLibrary/SN74H55/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H55/3_and.sub b/library/SubcircuitLibrary/SN74H55/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H55/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74H55/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H55/4_OR-cache.lib b/library/SubcircuitLibrary/SN74H55/4_OR-cache.lib
new file mode 100644
index 000000000..155f5e601
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.cir b/library/SubcircuitLibrary/SN74H55/4_OR.cir
new file mode 100644
index 000000000..b338b7b5f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.cir.out b/library/SubcircuitLibrary/SN74H55/4_OR.cir.out
new file mode 100644
index 000000000..adb6b01be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.pro b/library/SubcircuitLibrary/SN74H55/4_OR.pro
new file mode 100644
index 000000000..881563ebd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.sch b/library/SubcircuitLibrary/SN74H55/4_OR.sch
new file mode 100644
index 000000000..118968656
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H55/4_OR.sub b/library/SubcircuitLibrary/SN74H55/4_OR.sub
new file mode 100644
index 000000000..d1fd3a241
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H55/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74H55/4_OR_Previous_Values.xml
new file mode 100644
index 000000000..0683d9eb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H55/4_and-cache.lib b/library/SubcircuitLibrary/SN74H55/4_and-cache.lib
new file mode 100644
index 000000000..60f1a83d4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H55/4_and-rescue.lib b/library/SubcircuitLibrary/SN74H55/4_and-rescue.lib
new file mode 100644
index 000000000..e38330518
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H55/4_and.cir b/library/SubcircuitLibrary/SN74H55/4_and.cir
new file mode 100644
index 000000000..fdf2e1074
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H55/4_and.cir.out b/library/SubcircuitLibrary/SN74H55/4_and.cir.out
new file mode 100644
index 000000000..f40e5bc62
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H55/4_and.pro b/library/SubcircuitLibrary/SN74H55/4_and.pro
new file mode 100644
index 000000000..b13a0a825
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/SN74H55/4_and.sch b/library/SubcircuitLibrary/SN74H55/4_and.sch
new file mode 100644
index 000000000..f5e8febdc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H55/4_and.sub b/library/SubcircuitLibrary/SN74H55/4_and.sub
new file mode 100644
index 000000000..8663f37e6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H55/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74H55/4_and_Previous_Values.xml
new file mode 100644
index 000000000..f2ba0130e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55-cache.lib b/library/SubcircuitLibrary/SN74H55/SN74H55-cache.lib
new file mode 100644
index 000000000..4f81c933f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/SN74H55-cache.lib
@@ -0,0 +1,98 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.cir b/library/SubcircuitLibrary/SN74H55/SN74H55.cir
new file mode 100644
index 000000000..d96c442f8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/SN74H55.cir
@@ -0,0 +1,16 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74H55\SN74H55.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/21/25 12:33:56
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_X1-Pad5_ 4_and
+X2 Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U3-Pad12_ Net-_U3-Pad13_ Net-_X2-Pad5_ 4_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+X3 Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U1-Pad2_ Net-_U3-Pad5_ Net-_U2-Pad1_ 4_OR
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ d_inverter
+U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ ? ? Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U3-Pad12_ Net-_U3-Pad13_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.cir.out b/library/SubcircuitLibrary/SN74H55/SN74H55.cir.out
new file mode 100644
index 000000000..8f6ce3c98
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/SN74H55.cir.out
@@ -0,0 +1,25 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74h55\sn74h55.cir
+
+.include 4_and.sub
+.include 4_OR.sub
+x1 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_x1-pad5_ 4_and
+x2 net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_x2-pad5_ 4_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+x3 net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad2_ net-_u3-pad5_ net-_u2-pad1_ 4_OR
+* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ ? ? net-_u2-pad2_ net-_u1-pad1_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ ? port
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u2-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.pro b/library/SubcircuitLibrary/SN74H55/SN74H55.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/SN74H55.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.sch b/library/SubcircuitLibrary/SN74H55/SN74H55.sch
new file mode 100644
index 000000000..97032c503
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/SN74H55.sch
@@ -0,0 +1,321 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74H55-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4_and X1
+U 1 1 68562EC6
+P 3500 2150
+F 0 "X1" H 3550 2100 60 0000 C CNN
+F 1 "4_and" H 3600 2250 60 0000 C CNN
+F 2 "" H 3500 2150 60 0000 C CNN
+F 3 "" H 3500 2150 60 0000 C CNN
+ 1 3500 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X2
+U 1 1 68562F0C
+P 3500 2800
+F 0 "X2" H 3550 2750 60 0000 C CNN
+F 1 "4_and" H 3600 2900 60 0000 C CNN
+F 2 "" H 3500 2800 60 0000 C CNN
+F 3 "" H 3500 2800 60 0000 C CNN
+ 1 3500 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U1
+U 1 1 68564EC2
+P 4350 3350
+F 0 "U1" H 4350 3250 60 0000 C CNN
+F 1 "d_inverter" H 4350 3500 60 0000 C CNN
+F 2 "" H 4400 3300 60 0000 C CNN
+F 3 "" H 4400 3300 60 0000 C CNN
+ 1 4350 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X3
+U 1 1 68564F65
+P 5650 2450
+F 0 "X3" H 5800 2350 60 0000 C CNN
+F 1 "4_OR" H 5800 2550 60 0000 C CNN
+F 2 "" H 5650 2450 60 0000 C CNN
+F 3 "" H 5650 2450 60 0000 C CNN
+ 1 5650 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 68564FFE
+P 6700 2450
+F 0 "U2" H 6700 2350 60 0000 C CNN
+F 1 "d_inverter" H 6700 2600 60 0000 C CNN
+F 2 "" H 6750 2400 60 0000 C CNN
+F 3 "" H 6750 2400 60 0000 C CNN
+ 1 6700 2450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4000 2150 5300 2150
+Wire Wire Line
+ 5300 2150 5300 2300
+Wire Wire Line
+ 4000 2800 4100 2800
+Wire Wire Line
+ 4100 2800 4100 2400
+Wire Wire Line
+ 4100 2400 5300 2400
+Wire Wire Line
+ 4650 3350 4650 2500
+Wire Wire Line
+ 4650 2500 5300 2500
+Wire Wire Line
+ 6200 2450 6400 2450
+$Comp
+L PORT U3
+U 1 1 68565099
+P 2750 1900
+F 0 "U3" H 2800 2000 30 0000 C CNN
+F 1 "PORT" H 2750 1900 30 0000 C CNN
+F 2 "" H 2750 1900 60 0000 C CNN
+F 3 "" H 2750 1900 60 0000 C CNN
+ 1 2750 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 2 1 685650DA
+P 2750 2050
+F 0 "U3" H 2800 2150 30 0000 C CNN
+F 1 "PORT" H 2750 2050 30 0000 C CNN
+F 2 "" H 2750 2050 60 0000 C CNN
+F 3 "" H 2750 2050 60 0000 C CNN
+ 2 2750 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 3 1 6856510D
+P 2750 2200
+F 0 "U3" H 2800 2300 30 0000 C CNN
+F 1 "PORT" H 2750 2200 30 0000 C CNN
+F 2 "" H 2750 2200 60 0000 C CNN
+F 3 "" H 2750 2200 60 0000 C CNN
+ 3 2750 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 4 1 68565142
+P 2750 2350
+F 0 "U3" H 2800 2450 30 0000 C CNN
+F 1 "PORT" H 2750 2350 30 0000 C CNN
+F 2 "" H 2750 2350 60 0000 C CNN
+F 3 "" H 2750 2350 60 0000 C CNN
+ 4 2750 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 5 1 68565169
+P 2650 3750
+F 0 "U3" H 2700 3850 30 0000 C CNN
+F 1 "PORT" H 2650 3750 30 0000 C CNN
+F 2 "" H 2650 3750 60 0000 C CNN
+F 3 "" H 2650 3750 60 0000 C CNN
+ 5 2650 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 6 1 68565192
+P 6200 1400
+F 0 "U3" H 6250 1500 30 0000 C CNN
+F 1 "PORT" H 6200 1400 30 0000 C CNN
+F 2 "" H 6200 1400 60 0000 C CNN
+F 3 "" H 6200 1400 60 0000 C CNN
+ 6 6200 1400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 7 1 685651BD
+P 6200 1550
+F 0 "U3" H 6250 1650 30 0000 C CNN
+F 1 "PORT" H 6200 1550 30 0000 C CNN
+F 2 "" H 6200 1550 60 0000 C CNN
+F 3 "" H 6200 1550 60 0000 C CNN
+ 7 6200 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 8 1 685651EE
+P 7500 2450
+F 0 "U3" H 7550 2550 30 0000 C CNN
+F 1 "PORT" H 7500 2450 30 0000 C CNN
+F 2 "" H 7500 2450 60 0000 C CNN
+F 3 "" H 7500 2450 60 0000 C CNN
+ 8 7500 2450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U3
+U 9 1 6856521D
+P 2650 3350
+F 0 "U3" H 2700 3450 30 0000 C CNN
+F 1 "PORT" H 2650 3350 30 0000 C CNN
+F 2 "" H 2650 3350 60 0000 C CNN
+F 3 "" H 2650 3350 60 0000 C CNN
+ 9 2650 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 10 1 6856524E
+P 2750 2600
+F 0 "U3" H 2800 2700 30 0000 C CNN
+F 1 "PORT" H 2750 2600 30 0000 C CNN
+F 2 "" H 2750 2600 60 0000 C CNN
+F 3 "" H 2750 2600 60 0000 C CNN
+ 10 2750 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 11 1 68565283
+P 2750 2750
+F 0 "U3" H 2800 2850 30 0000 C CNN
+F 1 "PORT" H 2750 2750 30 0000 C CNN
+F 2 "" H 2750 2750 60 0000 C CNN
+F 3 "" H 2750 2750 60 0000 C CNN
+ 11 2750 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 12 1 685652B8
+P 2750 2900
+F 0 "U3" H 2800 3000 30 0000 C CNN
+F 1 "PORT" H 2750 2900 30 0000 C CNN
+F 2 "" H 2750 2900 60 0000 C CNN
+F 3 "" H 2750 2900 60 0000 C CNN
+ 12 2750 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 13 1 685652EF
+P 2750 3050
+F 0 "U3" H 2800 3150 30 0000 C CNN
+F 1 "PORT" H 2750 3050 30 0000 C CNN
+F 2 "" H 2750 3050 60 0000 C CNN
+F 3 "" H 2750 3050 60 0000 C CNN
+ 13 2750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 14 1 68565328
+P 6200 1750
+F 0 "U3" H 6250 1850 30 0000 C CNN
+F 1 "PORT" H 6200 1750 30 0000 C CNN
+F 2 "" H 6200 1750 60 0000 C CNN
+F 3 "" H 6200 1750 60 0000 C CNN
+ 14 6200 1750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3000 1900 3100 1900
+Wire Wire Line
+ 3100 1900 3100 2000
+Wire Wire Line
+ 3000 2050 3100 2050
+Wire Wire Line
+ 3100 2050 3100 2100
+Wire Wire Line
+ 3000 2200 3100 2200
+Wire Wire Line
+ 3000 2350 3100 2350
+Wire Wire Line
+ 3100 2350 3100 2300
+Wire Wire Line
+ 3000 2600 3100 2600
+Wire Wire Line
+ 3100 2600 3100 2650
+Wire Wire Line
+ 3000 2750 3100 2750
+Wire Wire Line
+ 3000 2900 3100 2900
+Wire Wire Line
+ 3100 2900 3100 2850
+Wire Wire Line
+ 3000 3050 3100 3050
+Wire Wire Line
+ 3100 3050 3100 2950
+Wire Wire Line
+ 2900 3350 4050 3350
+Wire Wire Line
+ 2900 3750 5300 3750
+Wire Wire Line
+ 5300 3750 5300 2600
+Wire Wire Line
+ 7000 2450 7250 2450
+NoConn ~ 6450 1400
+NoConn ~ 6450 1550
+NoConn ~ 6450 1750
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55.sub b/library/SubcircuitLibrary/SN74H55/SN74H55.sub
new file mode 100644
index 000000000..4ed992ac9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/SN74H55.sub
@@ -0,0 +1,19 @@
+* Subcircuit SN74H55
+.subckt SN74H55 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ ? ? net-_u2-pad2_ net-_u1-pad1_ net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ ?
+* c:\fossee\esim\library\subcircuitlibrary\sn74h55\sn74h55.cir
+.include 4_and.sub
+.include 4_OR.sub
+x1 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_x1-pad5_ 4_and
+x2 net-_u3-pad10_ net-_u3-pad11_ net-_u3-pad12_ net-_u3-pad13_ net-_x2-pad5_ 4_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+x3 net-_x1-pad5_ net-_x2-pad5_ net-_u1-pad2_ net-_u3-pad5_ net-_u2-pad1_ 4_OR
+* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u2-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74H55
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H55/SN74H55_Previous_Values.xml b/library/SubcircuitLibrary/SN74H55/SN74H55_Previous_Values.xml
new file mode 100644
index 000000000..413fe74ed
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/SN74H55_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H55/analysis b/library/SubcircuitLibrary/SN74H55/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H55/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H60/D.lib b/library/SubcircuitLibrary/SN74H60/D.lib
new file mode 100644
index 000000000..f53bf3e03
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/SN74H60/NPN.lib b/library/SubcircuitLibrary/SN74H60/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60-cache.lib b/library/SubcircuitLibrary/SN74H60/SN74H60-cache.lib
new file mode 100644
index 000000000..416a996bf
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/SN74H60-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.cir b/library/SubcircuitLibrary/SN74H60/SN74H60.cir
new file mode 100644
index 000000000..b30b7877f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/SN74H60.cir
@@ -0,0 +1,19 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74H60\SN74H60.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/25 15:54:11
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and
+U5 Net-_U1-Pad3_ Net-_U2-Pad3_ Net-_U5-Pad3_ d_and
+U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U3-Pad3_ d_and
+U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_and
+U6 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U6-Pad3_ d_and
+U7 Net-_U5-Pad3_ Net-_U7-Pad2_ d_inverter
+U8 Net-_U6-Pad3_ Net-_U8-Pad2_ d_inverter
+U9 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad1_ Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U4-Pad1_ ? Net-_U4-Pad2_ Net-_U8-Pad2_ Net-_U6-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad2_ Net-_U2-Pad2_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.cir.out b/library/SubcircuitLibrary/SN74H60/SN74H60.cir.out
new file mode 100644
index 000000000..fc86579c9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/SN74H60.cir.out
@@ -0,0 +1,44 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74h60\sn74h60.cir
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and
+* u5 net-_u1-pad3_ net-_u2-pad3_ net-_u5-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_and
+* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ d_and
+* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u5-pad3_ net-_u7-pad2_ d_inverter
+* u8 net-_u6-pad3_ net-_u8-pad2_ d_inverter
+* u9 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad1_ net-_u3-pad1_ net-_u3-pad2_ net-_u4-pad1_ ? net-_u4-pad2_ net-_u8-pad2_ net-_u6-pad3_ net-_u5-pad3_ net-_u7-pad2_ net-_u2-pad2_ ? port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
+a3 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u5-pad3_ u5
+a4 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+a5 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u4-pad3_ u4
+a6 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u6-pad3_ u6
+a7 net-_u5-pad3_ net-_u7-pad2_ u7
+a8 net-_u6-pad3_ net-_u8-pad2_ u8
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.pro b/library/SubcircuitLibrary/SN74H60/SN74H60.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/SN74H60.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.sch b/library/SubcircuitLibrary/SN74H60/SN74H60.sch
new file mode 100644
index 000000000..ae70d4fb5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/SN74H60.sch
@@ -0,0 +1,361 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74H60-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U1
+U 1 1 6853E4C9
+P 3700 2150
+F 0 "U1" H 3700 2150 60 0000 C CNN
+F 1 "d_and" H 3750 2250 60 0000 C CNN
+F 2 "" H 3700 2150 60 0000 C CNN
+F 3 "" H 3700 2150 60 0000 C CNN
+ 1 3700 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 6853E52B
+P 3700 2550
+F 0 "U2" H 3700 2550 60 0000 C CNN
+F 1 "d_and" H 3750 2650 60 0000 C CNN
+F 2 "" H 3700 2550 60 0000 C CNN
+F 3 "" H 3700 2550 60 0000 C CNN
+ 1 3700 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 6853E555
+P 4950 2300
+F 0 "U5" H 4950 2300 60 0000 C CNN
+F 1 "d_and" H 5000 2400 60 0000 C CNN
+F 2 "" H 4950 2300 60 0000 C CNN
+F 3 "" H 4950 2300 60 0000 C CNN
+ 1 4950 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 6853E5A0
+P 3700 3150
+F 0 "U3" H 3700 3150 60 0000 C CNN
+F 1 "d_and" H 3750 3250 60 0000 C CNN
+F 2 "" H 3700 3150 60 0000 C CNN
+F 3 "" H 3700 3150 60 0000 C CNN
+ 1 3700 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 6853E620
+P 3700 3550
+F 0 "U4" H 3700 3550 60 0000 C CNN
+F 1 "d_and" H 3750 3650 60 0000 C CNN
+F 2 "" H 3700 3550 60 0000 C CNN
+F 3 "" H 3700 3550 60 0000 C CNN
+ 1 3700 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 6853E64F
+P 4950 3350
+F 0 "U6" H 4950 3350 60 0000 C CNN
+F 1 "d_and" H 5000 3450 60 0000 C CNN
+F 2 "" H 4950 3350 60 0000 C CNN
+F 3 "" H 4950 3350 60 0000 C CNN
+ 1 4950 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 6853E855
+P 6050 2000
+F 0 "U7" H 6050 1900 60 0000 C CNN
+F 1 "d_inverter" H 6050 2150 60 0000 C CNN
+F 2 "" H 6100 1950 60 0000 C CNN
+F 3 "" H 6100 1950 60 0000 C CNN
+ 1 6050 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 6853E88B
+P 6050 3050
+F 0 "U8" H 6050 2950 60 0000 C CNN
+F 1 "d_inverter" H 6050 3200 60 0000 C CNN
+F 2 "" H 6100 3000 60 0000 C CNN
+F 3 "" H 6100 3000 60 0000 C CNN
+ 1 6050 3050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4150 2100 4500 2100
+Wire Wire Line
+ 4500 2100 4500 2200
+Wire Wire Line
+ 4150 2500 4500 2500
+Wire Wire Line
+ 4500 2500 4500 2300
+Wire Wire Line
+ 4150 3100 4500 3100
+Wire Wire Line
+ 4500 3100 4500 3250
+Wire Wire Line
+ 4150 3500 4500 3500
+Wire Wire Line
+ 4500 3500 4500 3350
+Wire Wire Line
+ 5400 2250 6800 2250
+Wire Wire Line
+ 5450 2250 5450 2000
+Wire Wire Line
+ 5450 2000 5750 2000
+$Comp
+L PORT U9
+U 1 1 6853ECEA
+P 2850 2050
+F 0 "U9" H 2900 2150 30 0000 C CNN
+F 1 "PORT" H 2850 2050 30 0000 C CNN
+F 2 "" H 2850 2050 60 0000 C CNN
+F 3 "" H 2850 2050 60 0000 C CNN
+ 1 2850 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U9
+U 2 1 6853ED35
+P 2850 2200
+F 0 "U9" H 2900 2300 30 0000 C CNN
+F 1 "PORT" H 2850 2200 30 0000 C CNN
+F 2 "" H 2850 2200 60 0000 C CNN
+F 3 "" H 2850 2200 60 0000 C CNN
+ 2 2850 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U9
+U 6 1 6853ED90
+P 2850 3400
+F 0 "U9" H 2900 3500 30 0000 C CNN
+F 1 "PORT" H 2850 3400 30 0000 C CNN
+F 2 "" H 2850 3400 60 0000 C CNN
+F 3 "" H 2850 3400 60 0000 C CNN
+ 6 2850 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U9
+U 3 1 6853EDF0
+P 2850 2450
+F 0 "U9" H 2900 2550 30 0000 C CNN
+F 1 "PORT" H 2850 2450 30 0000 C CNN
+F 2 "" H 2850 2450 60 0000 C CNN
+F 3 "" H 2850 2450 60 0000 C CNN
+ 3 2850 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U9
+U 7 1 6853EE21
+P 6800 1350
+F 0 "U9" H 6850 1450 30 0000 C CNN
+F 1 "PORT" H 6800 1350 30 0000 C CNN
+F 2 "" H 6800 1350 60 0000 C CNN
+F 3 "" H 6800 1350 60 0000 C CNN
+ 7 6800 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U9
+U 8 1 6853EE50
+P 2850 3600
+F 0 "U9" H 2900 3700 30 0000 C CNN
+F 1 "PORT" H 2850 3600 30 0000 C CNN
+F 2 "" H 2850 3600 60 0000 C CNN
+F 3 "" H 2850 3600 60 0000 C CNN
+ 8 2850 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U9
+U 9 1 6853EE81
+P 7050 3050
+F 0 "U9" H 7100 3150 30 0000 C CNN
+F 1 "PORT" H 7050 3050 30 0000 C CNN
+F 2 "" H 7050 3050 60 0000 C CNN
+F 3 "" H 7050 3050 60 0000 C CNN
+ 9 7050 3050
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U9
+U 4 1 6853EEB8
+P 2850 2950
+F 0 "U9" H 2900 3050 30 0000 C CNN
+F 1 "PORT" H 2850 2950 30 0000 C CNN
+F 2 "" H 2850 2950 60 0000 C CNN
+F 3 "" H 2850 2950 60 0000 C CNN
+ 4 2850 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U9
+U 5 1 6853EF01
+P 2850 3150
+F 0 "U9" H 2900 3250 30 0000 C CNN
+F 1 "PORT" H 2850 3150 30 0000 C CNN
+F 2 "" H 2850 3150 60 0000 C CNN
+F 3 "" H 2850 3150 60 0000 C CNN
+ 5 2850 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U9
+U 10 1 6853EF3C
+P 7050 3300
+F 0 "U9" H 7100 3400 30 0000 C CNN
+F 1 "PORT" H 7050 3300 30 0000 C CNN
+F 2 "" H 7050 3300 60 0000 C CNN
+F 3 "" H 7050 3300 60 0000 C CNN
+ 10 7050 3300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U9
+U 11 1 6853EF81
+P 7050 2250
+F 0 "U9" H 7100 2350 30 0000 C CNN
+F 1 "PORT" H 7050 2250 30 0000 C CNN
+F 2 "" H 7050 2250 60 0000 C CNN
+F 3 "" H 7050 2250 60 0000 C CNN
+ 11 7050 2250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U9
+U 12 1 6853EFBC
+P 7050 2000
+F 0 "U9" H 7100 2100 30 0000 C CNN
+F 1 "PORT" H 7050 2000 30 0000 C CNN
+F 2 "" H 7050 2000 60 0000 C CNN
+F 3 "" H 7050 2000 60 0000 C CNN
+ 12 7050 2000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U9
+U 13 1 6853EFFD
+P 2850 2600
+F 0 "U9" H 2900 2700 30 0000 C CNN
+F 1 "PORT" H 2850 2600 30 0000 C CNN
+F 2 "" H 2850 2600 60 0000 C CNN
+F 3 "" H 2850 2600 60 0000 C CNN
+ 13 2850 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U9
+U 14 1 6853F046
+P 6800 1550
+F 0 "U9" H 6850 1650 30 0000 C CNN
+F 1 "PORT" H 6800 1550 30 0000 C CNN
+F 2 "" H 6800 1550 60 0000 C CNN
+F 3 "" H 6800 1550 60 0000 C CNN
+ 14 6800 1550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6350 2000 6800 2000
+Connection ~ 5450 2250
+Wire Wire Line
+ 5400 3300 6800 3300
+Wire Wire Line
+ 6350 3050 6800 3050
+Wire Wire Line
+ 5750 3050 5450 3050
+Wire Wire Line
+ 5450 3050 5450 3300
+Connection ~ 5450 3300
+Wire Wire Line
+ 3100 2050 3250 2050
+Wire Wire Line
+ 3100 2200 3250 2200
+Wire Wire Line
+ 3250 2200 3250 2150
+Wire Wire Line
+ 3100 2450 3250 2450
+Wire Wire Line
+ 3100 2600 3250 2600
+Wire Wire Line
+ 3250 2600 3250 2550
+Wire Wire Line
+ 3100 2950 3250 2950
+Wire Wire Line
+ 3250 2950 3250 3050
+Wire Wire Line
+ 3100 3150 3250 3150
+Wire Wire Line
+ 3100 3400 3250 3400
+Wire Wire Line
+ 3250 3400 3250 3450
+Wire Wire Line
+ 3100 3600 3250 3600
+Wire Wire Line
+ 3250 3600 3250 3550
+NoConn ~ 7050 1350
+NoConn ~ 7050 1550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60.sub b/library/SubcircuitLibrary/SN74H60/SN74H60.sub
new file mode 100644
index 000000000..39700738f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/SN74H60.sub
@@ -0,0 +1,38 @@
+* Subcircuit SN74H60
+.subckt SN74H60 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad1_ net-_u3-pad1_ net-_u3-pad2_ net-_u4-pad1_ ? net-_u4-pad2_ net-_u8-pad2_ net-_u6-pad3_ net-_u5-pad3_ net-_u7-pad2_ net-_u2-pad2_ ?
+* c:\fossee\esim\library\subcircuitlibrary\sn74h60\sn74h60.cir
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and
+* u5 net-_u1-pad3_ net-_u2-pad3_ net-_u5-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u3-pad3_ d_and
+* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ d_and
+* u6 net-_u3-pad3_ net-_u4-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u5-pad3_ net-_u7-pad2_ d_inverter
+* u8 net-_u6-pad3_ net-_u8-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
+a3 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u5-pad3_ u5
+a4 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u3-pad3_ u3
+a5 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u4-pad3_ u4
+a6 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u6-pad3_ u6
+a7 net-_u5-pad3_ net-_u7-pad2_ u7
+a8 net-_u6-pad3_ net-_u8-pad2_ u8
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74H60
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H60/SN74H60_Previous_Values.xml b/library/SubcircuitLibrary/SN74H60/SN74H60_Previous_Values.xml
new file mode 100644
index 000000000..e7374d7d6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/SN74H60_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andd_andd_andd_andd_andd_inverterd_invertertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H60/analysis b/library/SubcircuitLibrary/SN74H60/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H60/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H62/3_and-cache.lib b/library/SubcircuitLibrary/SN74H62/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H62/3_and.cir b/library/SubcircuitLibrary/SN74H62/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H62/3_and.cir.out b/library/SubcircuitLibrary/SN74H62/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H62/3_and.pro b/library/SubcircuitLibrary/SN74H62/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74H62/3_and.sch b/library/SubcircuitLibrary/SN74H62/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H62/3_and.sub b/library/SubcircuitLibrary/SN74H62/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H62/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74H62/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H62/4_OR-cache.lib b/library/SubcircuitLibrary/SN74H62/4_OR-cache.lib
new file mode 100644
index 000000000..155f5e601
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.cir b/library/SubcircuitLibrary/SN74H62/4_OR.cir
new file mode 100644
index 000000000..b338b7b5f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.cir.out b/library/SubcircuitLibrary/SN74H62/4_OR.cir.out
new file mode 100644
index 000000000..adb6b01be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.pro b/library/SubcircuitLibrary/SN74H62/4_OR.pro
new file mode 100644
index 000000000..881563ebd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.sch b/library/SubcircuitLibrary/SN74H62/4_OR.sch
new file mode 100644
index 000000000..118968656
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H62/4_OR.sub b/library/SubcircuitLibrary/SN74H62/4_OR.sub
new file mode 100644
index 000000000..d1fd3a241
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H62/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74H62/4_OR_Previous_Values.xml
new file mode 100644
index 000000000..0683d9eb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62-cache.lib b/library/SubcircuitLibrary/SN74H62/SN74H62-cache.lib
new file mode 100644
index 000000000..6bcc31039
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/SN74H62-cache.lib
@@ -0,0 +1,114 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.cir b/library/SubcircuitLibrary/SN74H62/SN74H62.cir
new file mode 100644
index 000000000..40559961b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/SN74H62.cir
@@ -0,0 +1,17 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74H62\SN74H62.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/10/25 11:11:56
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and
+X1 Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_X1-Pad4_ 3_and
+X2 Net-_U3-Pad9_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_X2-Pad4_ 3_and
+U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and
+X3 Net-_U1-Pad3_ Net-_X1-Pad4_ Net-_X2-Pad4_ Net-_U2-Pad3_ Net-_U3-Pad8_ 4_OR
+U4 Net-_U3-Pad8_ Net-_U3-Pad6_ d_inverter
+U3 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_U3-Pad6_ ? Net-_U3-Pad8_ Net-_U3-Pad9_ Net-_U3-Pad10_ Net-_U3-Pad11_ Net-_U2-Pad1_ Net-_U2-Pad2_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.cir.out b/library/SubcircuitLibrary/SN74H62/SN74H62.cir.out
new file mode 100644
index 000000000..211568255
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/SN74H62.cir.out
@@ -0,0 +1,29 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74h62\sn74h62.cir
+
+.include 3_and.sub
+.include 4_OR.sub
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and
+x1 net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_x1-pad4_ 3_and
+x2 net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_x2-pad4_ 3_and
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and
+x3 net-_u1-pad3_ net-_x1-pad4_ net-_x2-pad4_ net-_u2-pad3_ net-_u3-pad8_ 4_OR
+* u4 net-_u3-pad8_ net-_u3-pad6_ d_inverter
+* u3 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ ? net-_u3-pad8_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u2-pad1_ net-_u2-pad2_ ? port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
+a3 net-_u3-pad8_ net-_u3-pad6_ u4
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.pro b/library/SubcircuitLibrary/SN74H62/SN74H62.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/SN74H62.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.sch b/library/SubcircuitLibrary/SN74H62/SN74H62.sch
new file mode 100644
index 000000000..8bf0f1f0c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/SN74H62.sch
@@ -0,0 +1,337 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U1
+U 1 1 6847C3ED
+P 4700 2750
+F 0 "U1" H 4700 2750 60 0000 C CNN
+F 1 "d_and" H 4750 2850 60 0000 C CNN
+F 2 "" H 4700 2750 60 0000 C CNN
+F 3 "" H 4700 2750 60 0000 C CNN
+ 1 4700 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 6847C42C
+P 4600 3150
+F 0 "X1" H 4700 3100 60 0000 C CNN
+F 1 "3_and" H 4750 3300 60 0000 C CNN
+F 2 "" H 4600 3150 60 0000 C CNN
+F 3 "" H 4600 3150 60 0000 C CNN
+ 1 4600 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 6847C45F
+P 4600 3550
+F 0 "X2" H 4700 3500 60 0000 C CNN
+F 1 "3_and" H 4750 3700 60 0000 C CNN
+F 2 "" H 4600 3550 60 0000 C CNN
+F 3 "" H 4600 3550 60 0000 C CNN
+ 1 4600 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 6847C490
+P 4700 3900
+F 0 "U2" H 4700 3900 60 0000 C CNN
+F 1 "d_and" H 4750 4000 60 0000 C CNN
+F 2 "" H 4700 3900 60 0000 C CNN
+F 3 "" H 4700 3900 60 0000 C CNN
+ 1 4700 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X3
+U 1 1 6847C4C2
+P 5800 3200
+F 0 "X3" H 5950 3100 60 0000 C CNN
+F 1 "4_OR" H 5950 3300 60 0000 C CNN
+F 2 "" H 5800 3200 60 0000 C CNN
+F 3 "" H 5800 3200 60 0000 C CNN
+ 1 5800 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 6847C4F1
+P 6950 2850
+F 0 "U4" H 6950 2750 60 0000 C CNN
+F 1 "d_inverter" H 6950 3000 60 0000 C CNN
+F 2 "" H 7000 2800 60 0000 C CNN
+F 3 "" H 7000 2800 60 0000 C CNN
+ 1 6950 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 2 1 6847C51A
+P 3800 2800
+F 0 "U3" H 3850 2900 30 0000 C CNN
+F 1 "PORT" H 3800 2800 30 0000 C CNN
+F 2 "" H 3800 2800 60 0000 C CNN
+F 3 "" H 3800 2800 60 0000 C CNN
+ 2 3800 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 3 1 6847C579
+P 3800 2950
+F 0 "U3" H 3850 3050 30 0000 C CNN
+F 1 "PORT" H 3800 2950 30 0000 C CNN
+F 2 "" H 3800 2950 60 0000 C CNN
+F 3 "" H 3800 2950 60 0000 C CNN
+ 3 3800 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 1 1 6847C59E
+P 3800 2650
+F 0 "U3" H 3850 2750 30 0000 C CNN
+F 1 "PORT" H 3800 2650 30 0000 C CNN
+F 2 "" H 3800 2650 60 0000 C CNN
+F 3 "" H 3800 2650 60 0000 C CNN
+ 1 3800 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 4 1 6847C5C7
+P 3800 3100
+F 0 "U3" H 3850 3200 30 0000 C CNN
+F 1 "PORT" H 3800 3100 30 0000 C CNN
+F 2 "" H 3800 3100 60 0000 C CNN
+F 3 "" H 3800 3100 60 0000 C CNN
+ 4 3800 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 5 1 6847C5F0
+P 3800 3250
+F 0 "U3" H 3850 3350 30 0000 C CNN
+F 1 "PORT" H 3800 3250 30 0000 C CNN
+F 2 "" H 3800 3250 60 0000 C CNN
+F 3 "" H 3800 3250 60 0000 C CNN
+ 5 3800 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 6 1 6847C61B
+P 7700 2850
+F 0 "U3" H 7750 2950 30 0000 C CNN
+F 1 "PORT" H 7700 2850 30 0000 C CNN
+F 2 "" H 7700 2850 60 0000 C CNN
+F 3 "" H 7700 2850 60 0000 C CNN
+ 6 7700 2850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U3
+U 7 1 6847C648
+P 6000 2450
+F 0 "U3" H 6050 2550 30 0000 C CNN
+F 1 "PORT" H 6000 2450 30 0000 C CNN
+F 2 "" H 6000 2450 60 0000 C CNN
+F 3 "" H 6000 2450 60 0000 C CNN
+ 7 6000 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 8 1 6847C677
+P 7700 3200
+F 0 "U3" H 7750 3300 30 0000 C CNN
+F 1 "PORT" H 7700 3200 30 0000 C CNN
+F 2 "" H 7700 3200 60 0000 C CNN
+F 3 "" H 7700 3200 60 0000 C CNN
+ 8 7700 3200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U3
+U 9 1 6847C6A8
+P 3800 3400
+F 0 "U3" H 3850 3500 30 0000 C CNN
+F 1 "PORT" H 3800 3400 30 0000 C CNN
+F 2 "" H 3800 3400 60 0000 C CNN
+F 3 "" H 3800 3400 60 0000 C CNN
+ 9 3800 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 10 1 6847C6DB
+P 3800 3550
+F 0 "U3" H 3850 3650 30 0000 C CNN
+F 1 "PORT" H 3800 3550 30 0000 C CNN
+F 2 "" H 3800 3550 60 0000 C CNN
+F 3 "" H 3800 3550 60 0000 C CNN
+ 10 3800 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 11 1 6847C710
+P 3800 3700
+F 0 "U3" H 3850 3800 30 0000 C CNN
+F 1 "PORT" H 3800 3700 30 0000 C CNN
+F 2 "" H 3800 3700 60 0000 C CNN
+F 3 "" H 3800 3700 60 0000 C CNN
+ 11 3800 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 12 1 6847C747
+P 3800 3850
+F 0 "U3" H 3850 3950 30 0000 C CNN
+F 1 "PORT" H 3800 3850 30 0000 C CNN
+F 2 "" H 3800 3850 60 0000 C CNN
+F 3 "" H 3800 3850 60 0000 C CNN
+ 12 3800 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 13 1 6847C780
+P 3800 4000
+F 0 "U3" H 3850 4100 30 0000 C CNN
+F 1 "PORT" H 3800 4000 30 0000 C CNN
+F 2 "" H 3800 4000 60 0000 C CNN
+F 3 "" H 3800 4000 60 0000 C CNN
+ 13 3800 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U3
+U 14 1 6847C7BB
+P 6000 2600
+F 0 "U3" H 6050 2700 30 0000 C CNN
+F 1 "PORT" H 6000 2600 30 0000 C CNN
+F 2 "" H 6000 2600 60 0000 C CNN
+F 3 "" H 6000 2600 60 0000 C CNN
+ 14 6000 2600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5150 2700 5450 2700
+Wire Wire Line
+ 5450 2700 5450 3050
+Wire Wire Line
+ 5100 3100 5450 3100
+Wire Wire Line
+ 5450 3100 5450 3150
+Wire Wire Line
+ 5100 3500 5100 3250
+Wire Wire Line
+ 5100 3250 5450 3250
+Wire Wire Line
+ 5150 3850 5450 3850
+Wire Wire Line
+ 5450 3850 5450 3350
+Wire Wire Line
+ 4050 2650 4250 2650
+Wire Wire Line
+ 4050 2800 4250 2800
+Wire Wire Line
+ 4250 2800 4250 2750
+Wire Wire Line
+ 4050 2950 4250 2950
+Wire Wire Line
+ 4250 2950 4250 3000
+Wire Wire Line
+ 4050 3100 4250 3100
+Wire Wire Line
+ 4050 3250 4250 3250
+Wire Wire Line
+ 4250 3250 4250 3200
+Wire Wire Line
+ 4050 3400 4250 3400
+Wire Wire Line
+ 4050 3550 4250 3550
+Wire Wire Line
+ 4250 3550 4250 3500
+Wire Wire Line
+ 4050 3700 4250 3700
+Wire Wire Line
+ 4250 3700 4250 3600
+Wire Wire Line
+ 4050 3850 4050 3800
+Wire Wire Line
+ 4050 3800 4250 3800
+Wire Wire Line
+ 4050 4000 4250 4000
+Wire Wire Line
+ 4250 4000 4250 3900
+Wire Wire Line
+ 6350 3200 7450 3200
+Wire Wire Line
+ 6650 2850 6550 2850
+Wire Wire Line
+ 6550 2850 6550 3200
+Connection ~ 6550 3200
+NoConn ~ 6250 2450
+NoConn ~ 6250 2600
+Wire Wire Line
+ 7250 2850 7450 2850
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62.sub b/library/SubcircuitLibrary/SN74H62/SN74H62.sub
new file mode 100644
index 000000000..949abe968
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/SN74H62.sub
@@ -0,0 +1,23 @@
+* Subcircuit SN74H62
+.subckt SN74H62 net-_u1-pad1_ net-_u1-pad2_ net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ ? net-_u3-pad8_ net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_u2-pad1_ net-_u2-pad2_ ?
+* c:\fossee\esim\library\subcircuitlibrary\sn74h62\sn74h62.cir
+.include 3_and.sub
+.include 4_OR.sub
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and
+x1 net-_u3-pad3_ net-_u3-pad4_ net-_u3-pad5_ net-_x1-pad4_ 3_and
+x2 net-_u3-pad9_ net-_u3-pad10_ net-_u3-pad11_ net-_x2-pad4_ 3_and
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and
+x3 net-_u1-pad3_ net-_x1-pad4_ net-_x2-pad4_ net-_u2-pad3_ net-_u3-pad8_ 4_OR
+* u4 net-_u3-pad8_ net-_u3-pad6_ d_inverter
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2
+a3 net-_u3-pad8_ net-_u3-pad6_ u4
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74H62
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H62/SN74H62_Previous_Values.xml b/library/SubcircuitLibrary/SN74H62/SN74H62_Previous_Values.xml
new file mode 100644
index 000000000..dda622bc6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/SN74H62_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andd_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74H62/analysis b/library/SubcircuitLibrary/SN74H62/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74H62/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR-cache.lib b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.cir b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.cir
new file mode 100644
index 000000000..d2199ddbb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.cir
@@ -0,0 +1,14 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/CMOS_INVTR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 13 08:49:20 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.cir.out b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.cir.out
new file mode 100644
index 000000000..dec1c5fa5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.pro b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.sch b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.sch
new file mode 100644
index 000000000..aa7a7ee81
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.sch
@@ -0,0 +1,161 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 684B982F
+P 5350 2950
+F 0 "SC1" H 5400 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 3037 50 0000 R CNN
+F 2 "" H 5350 1450 50 0001 C CNN
+F 3 "" H 5350 2950 50 0001 C CNN
+ 1 5350 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684B9856
+P 5350 3800
+F 0 "SC2" H 5400 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5650 3887 50 0000 R CNN
+F 2 "" H 5350 2300 50 0001 C CNN
+F 3 "" H 5350 3800 50 0001 C CNN
+ 1 5350 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B98AD
+P 4550 3300
+F 0 "U1" H 4600 3400 30 0000 C CNN
+F 1 "PORT" H 4550 3300 30 0000 C CNN
+F 2 "" H 4550 3300 60 0000 C CNN
+F 3 "" H 4550 3300 60 0000 C CNN
+ 1 4550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B98D8
+P 6300 3350
+F 0 "U1" H 6350 3450 30 0000 C CNN
+F 1 "PORT" H 6300 3350 30 0000 C CNN
+F 2 "" H 6300 3350 60 0000 C CNN
+F 3 "" H 6300 3350 60 0000 C CNN
+ 4 6300 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B9935
+P 5300 4350
+F 0 "U1" H 5350 4450 30 0000 C CNN
+F 1 "PORT" H 5300 4350 30 0000 C CNN
+F 2 "" H 5300 4350 60 0000 C CNN
+F 3 "" H 5300 4350 60 0000 C CNN
+ 3 5300 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B999A
+P 5300 2350
+F 0 "U1" H 5350 2450 30 0000 C CNN
+F 1 "PORT" H 5300 2350 30 0000 C CNN
+F 2 "" H 5300 2350 60 0000 C CNN
+F 3 "" H 5300 2350 60 0000 C CNN
+ 2 5300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B99CD
+P 7950 3000
+F 0 "scmode1" H 7950 3150 98 0000 C CNB
+F 1 "SKY130mode" H 7950 2900 118 0000 C CNB
+F 2 "" H 7950 3150 60 0001 C CNN
+F 3 "" H 7950 3150 60 0001 C CNN
+ 1 7950 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 2650 5550 2350
+Wire Wire Line
+ 5450 2950 5600 2950
+Wire Wire Line
+ 5600 2950 5600 2550
+Wire Wire Line
+ 5600 2550 5550 2550
+Connection ~ 5550 2550
+Wire Wire Line
+ 5550 3250 5550 3500
+Wire Wire Line
+ 6050 3350 5550 3350
+Connection ~ 5550 3350
+Wire Wire Line
+ 5050 2950 5050 3800
+Wire Wire Line
+ 4800 3300 5050 3300
+Connection ~ 5050 3300
+Wire Wire Line
+ 5450 3800 5600 3800
+Wire Wire Line
+ 5600 3800 5600 4150
+Wire Wire Line
+ 5600 4150 5550 4150
+Wire Wire Line
+ 5550 4100 5550 4350
+Connection ~ 5550 4150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.sub b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.sub
new file mode 100644
index 000000000..8283bca86
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR.sub
@@ -0,0 +1,11 @@
+* Subcircuit CMOS_INVTR
+.subckt CMOS_INVTR net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/cmos_invtr/cmos_invtr.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends CMOS_INVTR
diff --git a/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR_Previous_Values.xml
new file mode 100644
index 000000000..d17c4f93e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/CMOS_INVTR_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3, l=0.15w=1, l=0.15
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC259/D_latch-cache.lib b/library/SubcircuitLibrary/SN74HC259/D_latch-cache.lib
new file mode 100644
index 000000000..00b011e78
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/D_latch-cache.lib
@@ -0,0 +1,98 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# NAND_2
+#
+DEF NAND_2 X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "NAND_2" 400 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 400 0 255 787 -787 0 1 0 N 450 250 450 -250
+C 700 0 0 0 1 0 N
+C 700 0 50 0 1 0 N
+P 2 0 1 0 -300 250 450 250 N
+P 3 0 1 0 -300 250 -300 -250 450 -250 N
+X inA 1 -500 100 200 R 50 50 1 1 I
+X Gnd 2 0 -450 200 U 50 50 1 1 I
+X Vdd 3 0 450 200 D 50 50 1 1 I
+X Out 4 950 0 200 L 50 50 1 1 O
+X inB 5 -500 -100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# NAND_3
+#
+DEF NAND_3 X 0 40 Y Y 1 F N
+F0 "X" 150 0 60 H V C CNN
+F1 "NAND_3" 450 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 500 0 255 787 -787 0 1 0 N 550 250 550 -250
+C 800 0 50 0 1 0 N
+P 2 0 1 0 -250 250 550 250 N
+P 3 0 1 0 -250 250 -250 -250 550 -250 N
+X inA 1 -450 150 200 R 50 50 1 1 I
+X inB 2 -450 0 200 R 50 50 1 1 I
+X Gnd 3 0 -450 200 U 50 50 1 1 I
+X Vdd 4 0 450 200 D 50 50 1 1 I
+X Out 5 1050 0 200 L 50 50 1 1 O
+X inC 6 -450 -150 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/D_latch-rescue.lib b/library/SubcircuitLibrary/SN74HC259/D_latch-rescue.lib
new file mode 100644
index 000000000..7569c1e39
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/D_latch-rescue.lib
@@ -0,0 +1,46 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# NAND_2-RESCUE-D_latch
+#
+DEF NAND_2-RESCUE-D_latch X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "NAND_2-RESCUE-D_latch" 400 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 400 0 255 787 -787 0 1 0 N 450 250 450 -250
+C 700 0 0 0 1 0 N
+C 700 0 50 0 1 0 N
+P 2 0 1 0 -300 250 450 250 N
+P 3 0 1 0 -300 250 -300 -250 450 -250 N
+X inA 1 -500 100 200 R 50 50 1 1 I
+X Gnd 2 0 -450 200 U 50 50 1 1 I
+X Vdd 3 0 450 200 D 50 50 1 1 I
+X inB 4 -500 -100 200 R 50 50 1 1 I
+X Out 5 950 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NAND_3-RESCUE-D_latch
+#
+DEF NAND_3-RESCUE-D_latch X 0 40 Y Y 1 F N
+F0 "X" 150 0 60 H V C CNN
+F1 "NAND_3-RESCUE-D_latch" 450 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 500 0 255 787 -787 0 1 0 N 550 250 550 -250
+C 800 0 50 0 1 0 N
+P 2 0 1 0 -250 250 550 250 N
+P 3 0 1 0 -250 250 -250 -250 550 -250 N
+X inA 1 -450 150 200 R 50 50 1 1 I
+X inB 2 -450 0 200 R 50 50 1 1 I
+X Gnd 3 0 -450 200 U 50 50 1 1 I
+X Vdd 4 0 450 200 D 50 50 1 1 I
+X inC 5 -450 -150 200 R 50 50 1 1 I
+X Out 6 1050 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/D_latch.bak b/library/SubcircuitLibrary/SN74HC259/D_latch.bak
new file mode 100644
index 000000000..1330c40b2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/D_latch.bak
@@ -0,0 +1,362 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L NAND_2 X4
+U 1 1 684AF5ED
+P 3900 1800
+F 0 "X4" H 4000 1800 60 0000 C CNN
+F 1 "NAND_2" H 4300 1800 60 0000 C CNN
+F 2 "" H 3900 1800 60 0001 C CNN
+F 3 "" H 3900 1800 60 0001 C CNN
+ 1 3900 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X6
+U 1 1 684AF614
+P 8000 2950
+F 0 "X6" H 8100 2950 60 0000 C CNN
+F 1 "NAND_2" H 8400 2950 60 0000 C CNN
+F 2 "" H 8000 2950 60 0001 C CNN
+F 3 "" H 8000 2950 60 0001 C CNN
+ 1 8000 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X1
+U 1 1 684AF795
+P 3850 3100
+F 0 "X1" H 4000 3100 60 0000 C CNN
+F 1 "NAND_3" H 4300 3100 60 0000 C CNN
+F 2 "" H 3850 3100 60 0001 C CNN
+F 3 "" H 3850 3100 60 0001 C CNN
+ 1 3850 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X2
+U 1 1 684AF829
+P 3850 4350
+F 0 "X2" H 4000 4350 60 0000 C CNN
+F 1 "NAND_3" H 4300 4350 60 0000 C CNN
+F 2 "" H 3850 4350 60 0001 C CNN
+F 3 "" H 3850 4350 60 0001 C CNN
+ 1 3850 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X3
+U 1 1 684AF8A8
+P 3850 5600
+F 0 "X3" H 4000 5600 60 0000 C CNN
+F 1 "NAND_3" H 4300 5600 60 0000 C CNN
+F 2 "" H 3850 5600 60 0001 C CNN
+F 3 "" H 3850 5600 60 0001 C CNN
+ 1 3850 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X5
+U 1 1 684AF935
+P 7950 4400
+F 0 "X5" H 8100 4400 60 0000 C CNN
+F 1 "NAND_3" H 8400 4400 60 0000 C CNN
+F 2 "" H 7950 4400 60 0001 C CNN
+F 3 "" H 7950 4400 60 0001 C CNN
+ 1 7950 4400
+ 1 0 0 -1
+$EndComp
+Text Label 3050 3700 0 60 ~ 0
+LE
+Wire Wire Line
+ 3400 3100 3050 3100
+Wire Wire Line
+ 3050 3100 3050 4350
+Wire Wire Line
+ 3050 4350 3400 4350
+Wire Wire Line
+ 3050 3700 2400 3700
+Connection ~ 3050 3700
+Wire Wire Line
+ 3400 2950 3400 2550
+Wire Wire Line
+ 3400 2550 4900 2550
+Wire Wire Line
+ 4900 2550 4900 1800
+Wire Wire Line
+ 4900 1800 4850 1800
+Wire Wire Line
+ 3400 1900 3400 2500
+Wire Wire Line
+ 3400 2500 4950 2500
+Wire Wire Line
+ 4950 2500 4950 3750
+Wire Wire Line
+ 4900 3100 6950 3100
+Wire Wire Line
+ 4900 5600 5000 5600
+Wire Wire Line
+ 5000 4950 5000 6500
+Wire Wire Line
+ 5000 6500 2700 6500
+Wire Wire Line
+ 2700 6500 2700 1700
+Wire Wire Line
+ 2700 1700 3400 1700
+Wire Wire Line
+ 3400 4500 3300 4500
+Wire Wire Line
+ 3300 4500 3300 4950
+Wire Wire Line
+ 3300 4950 5000 4950
+Connection ~ 5000 5600
+Wire Wire Line
+ 4900 4350 7350 4350
+Wire Wire Line
+ 4950 4350 4950 5000
+Wire Wire Line
+ 4950 5000 3300 5000
+Wire Wire Line
+ 3300 5000 3300 5450
+Wire Wire Line
+ 3300 5450 3400 5450
+Wire Wire Line
+ 3400 5600 2400 5600
+Wire Wire Line
+ 3400 3250 2850 3250
+Wire Wire Line
+ 2850 3250 2850 6350
+Wire Wire Line
+ 2850 6350 5650 6350
+Wire Wire Line
+ 2400 5750 3400 5750
+Connection ~ 2850 5750
+Text Label 2850 5750 0 60 ~ 0
+RE
+Text Label 2500 5600 0 60 ~ 0
+D
+Wire Wire Line
+ 3400 4200 3300 4200
+Wire Wire Line
+ 3300 4200 3300 3750
+Wire Wire Line
+ 3300 3750 4950 3750
+Connection ~ 4950 3100
+Wire Wire Line
+ 8950 2950 9600 2950
+Wire Wire Line
+ 9000 2950 9000 3600
+Wire Wire Line
+ 9000 3600 7500 3600
+Wire Wire Line
+ 7500 3600 7500 4250
+Wire Wire Line
+ 7500 3050 7400 3050
+Wire Wire Line
+ 7400 3050 7400 3750
+Wire Wire Line
+ 7400 3750 9100 3750
+Wire Wire Line
+ 9100 3750 9100 4400
+Wire Wire Line
+ 9000 4400 9750 4400
+Wire Wire Line
+ 6950 3100 6950 2850
+Wire Wire Line
+ 6950 2850 7500 2850
+Wire Wire Line
+ 7350 4350 7350 4400
+Wire Wire Line
+ 7350 4400 7500 4400
+Connection ~ 4950 4350
+Wire Wire Line
+ 7500 4550 5650 4550
+Wire Wire Line
+ 5650 4550 5650 6350
+Connection ~ 9000 2950
+Connection ~ 9100 4400
+$Comp
+L PORT U1
+U 2 1 684B0C88
+P 2150 5600
+F 0 "U1" H 2200 5700 30 0000 C CNN
+F 1 "PORT" H 2150 5600 30 0000 C CNN
+F 2 "" H 2150 5600 60 0000 C CNN
+F 3 "" H 2150 5600 60 0000 C CNN
+ 2 2150 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B0F85
+P 2150 3700
+F 0 "U1" H 2200 3800 30 0000 C CNN
+F 1 "PORT" H 2150 3700 30 0000 C CNN
+F 2 "" H 2150 3700 60 0000 C CNN
+F 3 "" H 2150 3700 60 0000 C CNN
+ 1 2150 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B1102
+P 2150 5750
+F 0 "U1" H 2200 5850 30 0000 C CNN
+F 1 "PORT" H 2150 5750 30 0000 C CNN
+F 2 "" H 2150 5750 60 0000 C CNN
+F 3 "" H 2150 5750 60 0000 C CNN
+ 3 2150 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684B120F
+P 9850 2950
+F 0 "U1" H 9900 3050 30 0000 C CNN
+F 1 "PORT" H 9850 2950 30 0000 C CNN
+F 2 "" H 9850 2950 60 0000 C CNN
+F 3 "" H 9850 2950 60 0000 C CNN
+ 6 9850 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684B1432
+P 10000 4400
+F 0 "U1" H 10050 4500 30 0000 C CNN
+F 1 "PORT" H 10000 4400 30 0000 C CNN
+F 2 "" H 10000 4400 60 0000 C CNN
+F 3 "" H 10000 4400 60 0000 C CNN
+ 7 10000 4400
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 3900 1350 8000 1350
+Wire Wire Line
+ 8000 1350 8000 2500
+Wire Wire Line
+ 3850 2650 5300 2650
+Wire Wire Line
+ 5300 1350 5300 5150
+Connection ~ 5300 1350
+Wire Wire Line
+ 5300 3900 3850 3900
+Connection ~ 5300 2650
+Wire Wire Line
+ 5300 5150 3850 5150
+Connection ~ 5300 3900
+Wire Wire Line
+ 7950 3950 5300 3950
+Wire Wire Line
+ 5300 3950 5300 3900
+Wire Wire Line
+ 3900 2250 4200 2250
+Wire Wire Line
+ 4200 2250 4200 6050
+Wire Wire Line
+ 4200 6050 3850 6050
+Wire Wire Line
+ 3850 4800 4200 4800
+Connection ~ 4200 4800
+Wire Wire Line
+ 3850 3550 4200 3550
+Connection ~ 4200 3550
+Wire Wire Line
+ 8000 3400 4200 3400
+Connection ~ 4200 3400
+Wire Wire Line
+ 7950 4850 4200 4850
+Connection ~ 4200 4850
+$Comp
+L PORT U1
+U 5 1 684B1B45
+P 4800 1550
+F 0 "U1" H 4850 1650 30 0000 C CNN
+F 1 "PORT" H 4800 1550 30 0000 C CNN
+F 2 "" H 4800 1550 60 0000 C CNN
+F 3 "" H 4800 1550 60 0000 C CNN
+ 5 4800 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B1E48
+P 3750 2400
+F 0 "U1" H 3800 2500 30 0000 C CNN
+F 1 "PORT" H 3750 2400 30 0000 C CNN
+F 2 "" H 3750 2400 60 0000 C CNN
+F 3 "" H 3750 2400 60 0000 C CNN
+ 4 3750 2400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4000 2400 4000 2250
+Connection ~ 4000 2250
+Wire Wire Line
+ 5050 1550 5050 1350
+Connection ~ 5050 1350
+$Comp
+L SKY130mode scmode1
+U 1 1 684B2043
+P 10100 1700
+F 0 "scmode1" H 10100 1850 98 0000 C CNB
+F 1 "SKY130mode" H 10100 1600 118 0000 C CNB
+F 2 "" H 10100 1850 60 0001 C CNN
+F 3 "" H 10100 1850 60 0001 C CNN
+ 1 10100 1700
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/D_latch.cir b/library/SubcircuitLibrary/SN74HC259/D_latch.cir
new file mode 100644
index 000000000..e0414df84
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/D_latch.cir
@@ -0,0 +1,18 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_latch/D_latch.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 09:45:19 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 /LE /D /RE Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+scmode1 SKY130mode
+X4 Net-_X2-Pad6_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X1-Pad1_ Net-_X1-Pad5_ NAND_2
+X1 Net-_X1-Pad1_ /LE Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X1-Pad5_ /RE NAND_3
+X2 Net-_X1-Pad5_ /LE Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X2-Pad5_ Net-_X2-Pad6_ NAND_3
+X3 Net-_X2-Pad5_ /D Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X2-Pad6_ /RE NAND_3
+X6 Net-_X1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ NAND_2
+X5 Net-_U1-Pad6_ Net-_X2-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad7_ /RE NAND_3
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/D_latch.cir.out b/library/SubcircuitLibrary/SN74HC259/D_latch.cir.out
new file mode 100644
index 000000000..cc8164a26
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/D_latch.cir.out
@@ -0,0 +1,23 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/d_latch/d_latch.cir
+
+.include NAND_2.sub
+.include NAND_3.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* u1 /le /d /re net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+* s c m o d e
+x4 net-_x2-pad6_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad1_ net-_x1-pad5_ NAND_2
+x1 net-_x1-pad1_ /le net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad5_ /re NAND_3
+x2 net-_x1-pad5_ /le net-_u1-pad4_ net-_u1-pad5_ net-_x2-pad5_ net-_x2-pad6_ NAND_3
+x3 net-_x2-pad5_ /d net-_u1-pad4_ net-_u1-pad5_ net-_x2-pad6_ /re NAND_3
+x6 net-_x1-pad5_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ NAND_2
+x5 net-_u1-pad6_ net-_x2-pad5_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ /re NAND_3
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/D_latch.pro b/library/SubcircuitLibrary/SN74HC259/D_latch.pro
new file mode 100644
index 000000000..973266fee
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/D_latch.pro
@@ -0,0 +1,74 @@
+update=Sat Jun 14 09:43:16 2025
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=D_latch-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74HC259/D_latch.sch b/library/SubcircuitLibrary/SN74HC259/D_latch.sch
new file mode 100644
index 000000000..98739abf0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/D_latch.sch
@@ -0,0 +1,364 @@
+EESchema Schematic File Version 2
+LIBS:D_latch-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:D_latch-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Text Label 3050 3700 0 60 ~ 0
+LE
+Wire Wire Line
+ 3400 3100 3050 3100
+Wire Wire Line
+ 3050 3100 3050 4350
+Wire Wire Line
+ 3050 4350 3400 4350
+Wire Wire Line
+ 3050 3700 2400 3700
+Connection ~ 3050 3700
+Wire Wire Line
+ 3400 2950 3400 2550
+Wire Wire Line
+ 3400 2550 4900 2550
+Wire Wire Line
+ 4900 2550 4900 1800
+Wire Wire Line
+ 4900 1800 4850 1800
+Wire Wire Line
+ 3400 1900 3400 2500
+Wire Wire Line
+ 3400 2500 4950 2500
+Wire Wire Line
+ 4950 2500 4950 3750
+Wire Wire Line
+ 4900 3100 6950 3100
+Wire Wire Line
+ 4900 5600 5000 5600
+Wire Wire Line
+ 5000 4950 5000 6500
+Wire Wire Line
+ 5000 6500 2700 6500
+Wire Wire Line
+ 2700 6500 2700 1700
+Wire Wire Line
+ 2700 1700 3400 1700
+Wire Wire Line
+ 3400 4500 3300 4500
+Wire Wire Line
+ 3300 4500 3300 4950
+Wire Wire Line
+ 3300 4950 5000 4950
+Connection ~ 5000 5600
+Wire Wire Line
+ 4900 4350 7350 4350
+Wire Wire Line
+ 4950 4350 4950 5000
+Wire Wire Line
+ 4950 5000 3300 5000
+Wire Wire Line
+ 3300 5000 3300 5450
+Wire Wire Line
+ 3300 5450 3400 5450
+Wire Wire Line
+ 3400 5600 2400 5600
+Wire Wire Line
+ 3400 3250 2850 3250
+Wire Wire Line
+ 2850 3250 2850 6350
+Wire Wire Line
+ 2850 6350 5650 6350
+Wire Wire Line
+ 2400 5750 3400 5750
+Connection ~ 2850 5750
+Text Label 2850 5750 0 60 ~ 0
+RE
+Text Label 2500 5600 0 60 ~ 0
+D
+Wire Wire Line
+ 3400 4200 3300 4200
+Wire Wire Line
+ 3300 4200 3300 3750
+Wire Wire Line
+ 3300 3750 4950 3750
+Connection ~ 4950 3100
+Wire Wire Line
+ 8950 2950 9600 2950
+Wire Wire Line
+ 9000 2950 9000 3600
+Wire Wire Line
+ 9000 3600 7500 3600
+Wire Wire Line
+ 7500 3600 7500 4250
+Wire Wire Line
+ 7500 3050 7400 3050
+Wire Wire Line
+ 7400 3050 7400 3750
+Wire Wire Line
+ 7400 3750 9100 3750
+Wire Wire Line
+ 9100 3750 9100 4400
+Wire Wire Line
+ 9000 4400 9750 4400
+Wire Wire Line
+ 6950 3100 6950 2850
+Wire Wire Line
+ 6950 2850 7500 2850
+Wire Wire Line
+ 7350 4350 7350 4400
+Wire Wire Line
+ 7350 4400 7500 4400
+Connection ~ 4950 4350
+Wire Wire Line
+ 7500 4550 5650 4550
+Wire Wire Line
+ 5650 4550 5650 6350
+Connection ~ 9000 2950
+Connection ~ 9100 4400
+$Comp
+L PORT U1
+U 2 1 684B0C88
+P 2150 5600
+F 0 "U1" H 2200 5700 30 0000 C CNN
+F 1 "PORT" H 2150 5600 30 0000 C CNN
+F 2 "" H 2150 5600 60 0000 C CNN
+F 3 "" H 2150 5600 60 0000 C CNN
+ 2 2150 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B0F85
+P 2150 3700
+F 0 "U1" H 2200 3800 30 0000 C CNN
+F 1 "PORT" H 2150 3700 30 0000 C CNN
+F 2 "" H 2150 3700 60 0000 C CNN
+F 3 "" H 2150 3700 60 0000 C CNN
+ 1 2150 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B1102
+P 2150 5750
+F 0 "U1" H 2200 5850 30 0000 C CNN
+F 1 "PORT" H 2150 5750 30 0000 C CNN
+F 2 "" H 2150 5750 60 0000 C CNN
+F 3 "" H 2150 5750 60 0000 C CNN
+ 3 2150 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684B120F
+P 9850 2950
+F 0 "U1" H 9900 3050 30 0000 C CNN
+F 1 "PORT" H 9850 2950 30 0000 C CNN
+F 2 "" H 9850 2950 60 0000 C CNN
+F 3 "" H 9850 2950 60 0000 C CNN
+ 6 9850 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684B1432
+P 10000 4400
+F 0 "U1" H 10050 4500 30 0000 C CNN
+F 1 "PORT" H 10000 4400 30 0000 C CNN
+F 2 "" H 10000 4400 60 0000 C CNN
+F 3 "" H 10000 4400 60 0000 C CNN
+ 7 10000 4400
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 3900 1350 8000 1350
+Wire Wire Line
+ 8000 1350 8000 2500
+Wire Wire Line
+ 3850 2650 5300 2650
+Wire Wire Line
+ 5300 1350 5300 5150
+Connection ~ 5300 1350
+Wire Wire Line
+ 5300 3900 3850 3900
+Connection ~ 5300 2650
+Wire Wire Line
+ 5300 5150 3850 5150
+Connection ~ 5300 3900
+Wire Wire Line
+ 7950 3950 5300 3950
+Wire Wire Line
+ 5300 3950 5300 3900
+Wire Wire Line
+ 3900 2250 4200 2250
+Wire Wire Line
+ 4200 2250 4200 6050
+Wire Wire Line
+ 4200 6050 3850 6050
+Wire Wire Line
+ 3850 4800 4200 4800
+Connection ~ 4200 4800
+Wire Wire Line
+ 3850 3550 4200 3550
+Connection ~ 4200 3550
+Wire Wire Line
+ 8000 3400 4200 3400
+Connection ~ 4200 3400
+Wire Wire Line
+ 7950 4850 4200 4850
+Connection ~ 4200 4850
+$Comp
+L PORT U1
+U 5 1 684B1B45
+P 4800 1550
+F 0 "U1" H 4850 1650 30 0000 C CNN
+F 1 "PORT" H 4800 1550 30 0000 C CNN
+F 2 "" H 4800 1550 60 0000 C CNN
+F 3 "" H 4800 1550 60 0000 C CNN
+ 5 4800 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B1E48
+P 3750 2400
+F 0 "U1" H 3800 2500 30 0000 C CNN
+F 1 "PORT" H 3750 2400 30 0000 C CNN
+F 2 "" H 3750 2400 60 0000 C CNN
+F 3 "" H 3750 2400 60 0000 C CNN
+ 4 3750 2400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4000 2400 4000 2250
+Connection ~ 4000 2250
+Wire Wire Line
+ 5050 1550 5050 1350
+Connection ~ 5050 1350
+$Comp
+L SKY130mode scmode1
+U 1 1 684B2043
+P 10100 1700
+F 0 "scmode1" H 10100 1850 98 0000 C CNB
+F 1 "SKY130mode" H 10100 1600 118 0000 C CNB
+F 2 "" H 10100 1850 60 0001 C CNN
+F 3 "" H 10100 1850 60 0001 C CNN
+ 1 10100 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X4
+U 1 1 684CF80D
+P 3900 1800
+F 0 "X4" H 4000 1800 60 0000 C CNN
+F 1 "NAND_2" H 4300 1800 60 0000 C CNN
+F 2 "" H 3900 1800 60 0001 C CNN
+F 3 "" H 3900 1800 60 0001 C CNN
+ 1 3900 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X1
+U 1 1 684CF882
+P 3850 3100
+F 0 "X1" H 4000 3100 60 0000 C CNN
+F 1 "NAND_3" H 4300 3100 60 0000 C CNN
+F 2 "" H 3850 3100 60 0001 C CNN
+F 3 "" H 3850 3100 60 0001 C CNN
+ 1 3850 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X2
+U 1 1 684CF905
+P 3850 4350
+F 0 "X2" H 4000 4350 60 0000 C CNN
+F 1 "NAND_3" H 4300 4350 60 0000 C CNN
+F 2 "" H 3850 4350 60 0001 C CNN
+F 3 "" H 3850 4350 60 0001 C CNN
+ 1 3850 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X3
+U 1 1 684CF986
+P 3850 5600
+F 0 "X3" H 4000 5600 60 0000 C CNN
+F 1 "NAND_3" H 4300 5600 60 0000 C CNN
+F 2 "" H 3850 5600 60 0001 C CNN
+F 3 "" H 3850 5600 60 0001 C CNN
+ 1 3850 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X6
+U 1 1 684CFB07
+P 8000 2950
+F 0 "X6" H 8100 2950 60 0000 C CNN
+F 1 "NAND_2" H 8400 2950 60 0000 C CNN
+F 2 "" H 8000 2950 60 0001 C CNN
+F 3 "" H 8000 2950 60 0001 C CNN
+ 1 8000 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X5
+U 1 1 684CFBB2
+P 7950 4400
+F 0 "X5" H 8100 4400 60 0000 C CNN
+F 1 "NAND_3" H 8400 4400 60 0000 C CNN
+F 2 "" H 7950 4400 60 0001 C CNN
+F 3 "" H 7950 4400 60 0001 C CNN
+ 1 7950 4400
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/D_latch.sub b/library/SubcircuitLibrary/SN74HC259/D_latch.sub
new file mode 100644
index 000000000..be42d30cc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/D_latch.sub
@@ -0,0 +1,17 @@
+* Subcircuit D_latch
+.subckt D_latch /le /d /re net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/d_latch/d_latch.cir
+.include NAND_2.sub
+.include NAND_3.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* s c m o d e
+x4 net-_x2-pad6_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad1_ net-_x1-pad5_ NAND_2
+x1 net-_x1-pad1_ /le net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad5_ /re NAND_3
+x2 net-_x1-pad5_ /le net-_u1-pad4_ net-_u1-pad5_ net-_x2-pad5_ net-_x2-pad6_ NAND_3
+x3 net-_x2-pad5_ /d net-_u1-pad4_ net-_u1-pad5_ net-_x2-pad6_ /re NAND_3
+x6 net-_x1-pad5_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ NAND_2
+x5 net-_u1-pad6_ net-_x2-pad5_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad7_ /re NAND_3
+* Control Statements
+
+.ends D_latch
diff --git a/library/SubcircuitLibrary/SN74HC259/D_latch_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC259/D_latch_Previous_Values.xml
new file mode 100644
index 000000000..d8d7bbcf4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/D_latch_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38-cache.lib b/library/SubcircuitLibrary/SN74HC259/Decoder_38-cache.lib
new file mode 100644
index 000000000..00b011e78
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38-cache.lib
@@ -0,0 +1,98 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# NAND_2
+#
+DEF NAND_2 X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "NAND_2" 400 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 400 0 255 787 -787 0 1 0 N 450 250 450 -250
+C 700 0 0 0 1 0 N
+C 700 0 50 0 1 0 N
+P 2 0 1 0 -300 250 450 250 N
+P 3 0 1 0 -300 250 -300 -250 450 -250 N
+X inA 1 -500 100 200 R 50 50 1 1 I
+X Gnd 2 0 -450 200 U 50 50 1 1 I
+X Vdd 3 0 450 200 D 50 50 1 1 I
+X Out 4 950 0 200 L 50 50 1 1 O
+X inB 5 -500 -100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# NAND_3
+#
+DEF NAND_3 X 0 40 Y Y 1 F N
+F0 "X" 150 0 60 H V C CNN
+F1 "NAND_3" 450 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 500 0 255 787 -787 0 1 0 N 550 250 550 -250
+C 800 0 50 0 1 0 N
+P 2 0 1 0 -250 250 550 250 N
+P 3 0 1 0 -250 250 -250 -250 550 -250 N
+X inA 1 -450 150 200 R 50 50 1 1 I
+X inB 2 -450 0 200 R 50 50 1 1 I
+X Gnd 3 0 -450 200 U 50 50 1 1 I
+X Vdd 4 0 450 200 D 50 50 1 1 I
+X Out 5 1050 0 200 L 50 50 1 1 O
+X inC 6 -450 -150 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38-rescue.lib b/library/SubcircuitLibrary/SN74HC259/Decoder_38-rescue.lib
new file mode 100644
index 000000000..e66f87023
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38-rescue.lib
@@ -0,0 +1,46 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# NAND_2-RESCUE-Decoder_38
+#
+DEF NAND_2-RESCUE-Decoder_38 X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "NAND_2-RESCUE-Decoder_38" 400 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 400 0 255 787 -787 0 1 0 N 450 250 450 -250
+C 700 0 0 0 1 0 N
+C 700 0 50 0 1 0 N
+P 2 0 1 0 -300 250 450 250 N
+P 3 0 1 0 -300 250 -300 -250 450 -250 N
+X inA 1 -500 100 200 R 50 50 1 1 I
+X Gnd 2 0 -450 200 U 50 50 1 1 I
+X Vdd 3 0 450 200 D 50 50 1 1 I
+X inB 4 -500 -100 200 R 50 50 1 1 I
+X Out 5 950 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# NAND_3-RESCUE-Decoder_38
+#
+DEF NAND_3-RESCUE-Decoder_38 X 0 40 Y Y 1 F N
+F0 "X" 150 0 60 H V C CNN
+F1 "NAND_3-RESCUE-Decoder_38" 450 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 500 0 255 787 -787 0 1 0 N 550 250 550 -250
+C 800 0 50 0 1 0 N
+P 2 0 1 0 -250 250 550 250 N
+P 3 0 1 0 -250 250 -250 -250 550 -250 N
+X inA 1 -450 150 200 R 50 50 1 1 I
+X inB 2 -450 0 200 R 50 50 1 1 I
+X Gnd 3 0 -450 200 U 50 50 1 1 I
+X Vdd 4 0 450 200 D 50 50 1 1 I
+X inC 5 -450 -150 200 R 50 50 1 1 I
+X Out 6 1050 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38.bak b/library/SubcircuitLibrary/SN74HC259/Decoder_38.bak
new file mode 100644
index 000000000..12de0aaf8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38.bak
@@ -0,0 +1,745 @@
+EESchema Schematic File Version 2
+LIBS:Decoder_38-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:Decoder_38-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 1150 2900
+Connection ~ 1150 3050
+Connection ~ 1150 3200
+Connection ~ 1150 3500
+Connection ~ 1150 3650
+Connection ~ 1150 3800
+Wire Wire Line
+ 3050 800 1350 800
+Wire Wire Line
+ 1350 800 1350 2900
+Wire Wire Line
+ 1350 2900 1150 2900
+Wire Wire Line
+ 3050 950 1400 950
+Wire Wire Line
+ 1400 950 1400 3050
+Wire Wire Line
+ 1150 3050 1750 3050
+Wire Wire Line
+ 3050 1100 1450 1100
+Wire Wire Line
+ 1450 1100 1450 3200
+Wire Wire Line
+ 1150 3200 1850 3200
+Wire Wire Line
+ 1150 3800 1500 3800
+Wire Wire Line
+ 1350 3800 1350 8200
+Wire Wire Line
+ 1150 3650 1550 3650
+Wire Wire Line
+ 1400 3650 1400 8050
+Wire Wire Line
+ 1150 3500 1450 3500
+Wire Wire Line
+ 1450 3500 1450 7900
+Wire Wire Line
+ 3100 1800 1350 1800
+Connection ~ 1350 1800
+Wire Wire Line
+ 3100 1950 1400 1950
+Connection ~ 1400 1950
+Wire Wire Line
+ 3100 2100 1500 2100
+Wire Wire Line
+ 1500 2100 1500 3800
+Connection ~ 1350 3800
+Wire Wire Line
+ 3000 2800 1350 2800
+Connection ~ 1350 2800
+Wire Wire Line
+ 3000 2950 1550 2950
+Wire Wire Line
+ 1550 2950 1550 3650
+Connection ~ 1400 3650
+Wire Wire Line
+ 3000 3100 1450 3100
+Connection ~ 1450 3100
+Wire Wire Line
+ 3100 3800 1600 3800
+Wire Wire Line
+ 1600 3800 1600 2800
+Connection ~ 1600 2800
+Wire Wire Line
+ 3100 3950 1400 3950
+Connection ~ 1400 3950
+Wire Wire Line
+ 3100 4100 1350 4100
+Connection ~ 1350 4100
+Wire Wire Line
+ 3000 4800 1450 4800
+Connection ~ 1450 4800
+Wire Wire Line
+ 3000 4950 1650 4950
+Wire Wire Line
+ 1650 4950 1650 3050
+Connection ~ 1400 3050
+Wire Wire Line
+ 3000 5100 1700 5100
+Wire Wire Line
+ 1700 5100 1700 3200
+Connection ~ 1450 3200
+Wire Wire Line
+ 1450 7900 3150 7900
+Wire Wire Line
+ 1400 8050 3150 8050
+Wire Wire Line
+ 1350 8200 3150 8200
+Wire Wire Line
+ 3100 5800 1450 5800
+Connection ~ 1450 5800
+Wire Wire Line
+ 3100 6100 1350 6100
+Connection ~ 1350 6100
+Wire Wire Line
+ 3100 5950 1750 5950
+Wire Wire Line
+ 1750 5950 1750 3050
+Connection ~ 1650 3050
+Wire Wire Line
+ 3000 6800 1450 6800
+Connection ~ 1450 6800
+Wire Wire Line
+ 3000 6950 1400 6950
+Connection ~ 1400 6950
+Wire Wire Line
+ 3000 7100 1850 7100
+Wire Wire Line
+ 1850 7100 1850 3200
+Connection ~ 1700 3200
+Wire Wire Line
+ 3500 500 5600 500
+Wire Wire Line
+ 3950 500 3950 7650
+Wire Wire Line
+ 3950 7600 3600 7600
+Wire Wire Line
+ 3600 8500 3800 8500
+Wire Wire Line
+ 3800 1400 3800 8550
+Wire Wire Line
+ 3500 1400 5600 1400
+Wire Wire Line
+ 3550 1500 5400 1500
+Connection ~ 3950 1500
+Wire Wire Line
+ 3550 2400 5400 2400
+Connection ~ 3800 2400
+Wire Wire Line
+ 3450 2500 5600 2500
+Connection ~ 3950 2500
+Wire Wire Line
+ 3450 3400 5600 3400
+Connection ~ 3800 3400
+Wire Wire Line
+ 3550 3500 5400 3500
+Connection ~ 3950 3500
+Wire Wire Line
+ 3550 4400 5300 4400
+Connection ~ 3800 4400
+Wire Wire Line
+ 3450 4500 5600 4500
+Connection ~ 3950 4500
+Wire Wire Line
+ 3450 5400 5500 5400
+Connection ~ 3800 5400
+Wire Wire Line
+ 3550 5500 5450 5500
+Connection ~ 3950 5500
+Wire Wire Line
+ 3550 6400 5350 6400
+Connection ~ 3800 6400
+Wire Wire Line
+ 3450 6500 5550 6500
+Connection ~ 3950 6500
+Wire Wire Line
+ 3450 7400 5400 7400
+Connection ~ 3800 7400
+Wire Wire Line
+ 4550 950 4800 950
+Wire Wire Line
+ 4800 950 4800 850
+Wire Wire Line
+ 4800 850 5100 850
+Wire Wire Line
+ 4600 1950 4600 1850
+Wire Wire Line
+ 4600 1850 4900 1850
+Wire Wire Line
+ 4500 2950 4700 2950
+Wire Wire Line
+ 4700 2950 4700 2850
+Wire Wire Line
+ 4700 2850 5100 2850
+Wire Wire Line
+ 4600 3950 4600 3900
+Wire Wire Line
+ 4600 3900 4900 3900
+Wire Wire Line
+ 4500 4950 4850 4950
+Wire Wire Line
+ 4850 4950 4850 4900
+Wire Wire Line
+ 4850 4900 5100 4900
+Wire Wire Line
+ 4600 5950 4650 5950
+Wire Wire Line
+ 4650 5950 4650 5900
+Wire Wire Line
+ 4650 5900 4950 5900
+Wire Wire Line
+ 4500 6950 5050 6950
+Wire Wire Line
+ 4650 8050 4650 8000
+Wire Wire Line
+ 4650 8000 4900 8000
+Connection ~ 3950 500
+Connection ~ 3800 1400
+Wire Wire Line
+ 5400 3500 5400 3550
+Wire Wire Line
+ 5300 4400 5300 4450
+Wire Wire Line
+ 5300 4450 5400 4450
+Wire Wire Line
+ 5600 4500 5600 4550
+Wire Wire Line
+ 5500 5400 5500 5450
+Wire Wire Line
+ 5500 5450 5600 5450
+Wire Wire Line
+ 5450 5500 5450 5550
+Wire Wire Line
+ 5350 6400 5350 6450
+Wire Wire Line
+ 5350 6450 5450 6450
+Wire Wire Line
+ 5550 6500 5550 6600
+Wire Wire Line
+ 5400 7400 5400 7500
+Wire Wire Line
+ 5400 7500 5550 7500
+Wire Wire Line
+ 3950 7650 5400 7650
+Connection ~ 3950 7600
+Wire Wire Line
+ 3800 8550 5400 8550
+Connection ~ 3800 8500
+Wire Wire Line
+ 5100 1050 4750 1050
+Wire Wire Line
+ 4750 1050 4750 8800
+Wire Wire Line
+ 4750 8800 1200 8800
+Wire Wire Line
+ 4900 2050 4750 2050
+Connection ~ 4750 2050
+Wire Wire Line
+ 5100 3050 4750 3050
+Connection ~ 4750 3050
+Wire Wire Line
+ 4900 4100 4750 4100
+Connection ~ 4750 4100
+Wire Wire Line
+ 5100 5100 4750 5100
+Connection ~ 4750 5100
+Wire Wire Line
+ 5050 7150 4750 7150
+Connection ~ 4750 7150
+Wire Wire Line
+ 4750 8200 4900 8200
+Connection ~ 4750 8200
+$Comp
+L PORT U1
+U 1 1 684B4EE5
+P 900 2900
+F 0 "U1" H 950 3000 30 0000 C CNN
+F 1 "PORT" H 900 2900 30 0000 C CNN
+F 2 "" H 900 2900 60 0000 C CNN
+F 3 "" H 900 2900 60 0000 C CNN
+ 1 900 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B5027
+P 900 3050
+F 0 "U1" H 950 3150 30 0000 C CNN
+F 1 "PORT" H 900 3050 30 0000 C CNN
+F 2 "" H 900 3050 60 0000 C CNN
+F 3 "" H 900 3050 60 0000 C CNN
+ 2 900 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B5070
+P 900 3200
+F 0 "U1" H 950 3300 30 0000 C CNN
+F 1 "PORT" H 900 3200 30 0000 C CNN
+F 2 "" H 900 3200 60 0000 C CNN
+F 3 "" H 900 3200 60 0000 C CNN
+ 3 900 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B50ED
+P 900 3500
+F 0 "U1" H 950 3600 30 0000 C CNN
+F 1 "PORT" H 900 3500 30 0000 C CNN
+F 2 "" H 900 3500 60 0000 C CNN
+F 3 "" H 900 3500 60 0000 C CNN
+ 4 900 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684B5144
+P 900 3650
+F 0 "U1" H 950 3750 30 0000 C CNN
+F 1 "PORT" H 900 3650 30 0000 C CNN
+F 2 "" H 900 3650 60 0000 C CNN
+F 3 "" H 900 3650 60 0000 C CNN
+ 5 900 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684B51C5
+P 900 3800
+F 0 "U1" H 950 3900 30 0000 C CNN
+F 1 "PORT" H 900 3800 30 0000 C CNN
+F 2 "" H 900 3800 60 0000 C CNN
+F 3 "" H 900 3800 60 0000 C CNN
+ 6 900 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684B53AC
+P 950 8800
+F 0 "U1" H 1000 8900 30 0000 C CNN
+F 1 "PORT" H 950 8800 30 0000 C CNN
+F 2 "" H 950 8800 60 0000 C CNN
+F 3 "" H 950 8800 60 0000 C CNN
+ 7 950 8800
+ 1 0 0 -1
+$EndComp
+Text Label 1500 8800 0 60 ~ 0
+G_Bar
+Text Label 1150 2900 0 60 ~ 0
+S0_Bar
+Text Label 1150 3050 0 60 ~ 0
+S1_Bar
+Text Label 1150 3200 0 60 ~ 0
+S2_Bar
+Text Label 1150 3500 0 60 ~ 0
+S0
+Text Label 1150 3650 0 60 ~ 0
+S1
+Text Label 1150 3800 0 60 ~ 0
+S2
+$Comp
+L PORT U1
+U 8 1 684B5AAA
+P 4300 600
+F 0 "U1" H 4350 700 30 0000 C CNN
+F 1 "PORT" H 4300 600 30 0000 C CNN
+F 2 "" H 4300 600 60 0000 C CNN
+F 3 "" H 4300 600 60 0000 C CNN
+ 8 4300 600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684B5B1B
+P 4350 1300
+F 0 "U1" H 4400 1400 30 0000 C CNN
+F 1 "PORT" H 4350 1300 30 0000 C CNN
+F 2 "" H 4350 1300 60 0000 C CNN
+F 3 "" H 4350 1300 60 0000 C CNN
+ 9 4350 1300
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4050 600 4000 600
+Wire Wire Line
+ 4000 600 4000 500
+Connection ~ 4000 500
+Wire Wire Line
+ 4100 1300 4100 1400
+Connection ~ 4100 1400
+Text Label 4000 500 0 60 ~ 0
+Vdd
+Text Label 4100 1400 0 60 ~ 0
+Gnd
+$Comp
+L PORT U1
+U 13 1 684B5F75
+P 6900 950
+F 0 "U1" H 6950 1050 30 0000 C CNN
+F 1 "PORT" H 6900 950 30 0000 C CNN
+F 2 "" H 6900 950 60 0000 C CNN
+F 3 "" H 6900 950 60 0000 C CNN
+ 13 6900 950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684B6132
+P 6750 1950
+F 0 "U1" H 6800 2050 30 0000 C CNN
+F 1 "PORT" H 6750 1950 30 0000 C CNN
+F 2 "" H 6750 1950 60 0000 C CNN
+F 3 "" H 6750 1950 60 0000 C CNN
+ 10 6750 1950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 684B6260
+P 6900 2950
+F 0 "U1" H 6950 3050 30 0000 C CNN
+F 1 "PORT" H 6900 2950 30 0000 C CNN
+F 2 "" H 6900 2950 60 0000 C CNN
+F 3 "" H 6900 2950 60 0000 C CNN
+ 14 6900 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 684B63FD
+P 6750 4000
+F 0 "U1" H 6800 4100 30 0000 C CNN
+F 1 "PORT" H 6750 4000 30 0000 C CNN
+F 2 "" H 6750 4000 60 0000 C CNN
+F 3 "" H 6750 4000 60 0000 C CNN
+ 11 6750 4000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 684B6812
+P 6950 5000
+F 0 "U1" H 7000 5100 30 0000 C CNN
+F 1 "PORT" H 6950 5000 30 0000 C CNN
+F 2 "" H 6950 5000 60 0000 C CNN
+F 3 "" H 6950 5000 60 0000 C CNN
+ 17 6950 5000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 684B6911
+P 6900 6000
+F 0 "U1" H 6950 6100 30 0000 C CNN
+F 1 "PORT" H 6900 6000 30 0000 C CNN
+F 2 "" H 6900 6000 60 0000 C CNN
+F 3 "" H 6900 6000 60 0000 C CNN
+ 15 6900 6000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 684B6A00
+P 6900 7050
+F 0 "U1" H 6950 7150 30 0000 C CNN
+F 1 "PORT" H 6900 7050 30 0000 C CNN
+F 2 "" H 6900 7050 60 0000 C CNN
+F 3 "" H 6900 7050 60 0000 C CNN
+ 16 6900 7050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 684B6ADF
+P 6800 8100
+F 0 "U1" H 6850 8200 30 0000 C CNN
+F 1 "PORT" H 6800 8100 30 0000 C CNN
+F 2 "" H 6800 8100 60 0000 C CNN
+F 3 "" H 6800 8100 60 0000 C CNN
+ 12 6800 8100
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6550 950 6650 950
+Text Label 6550 950 0 60 ~ 0
+d7
+Wire Wire Line
+ 6350 1950 6500 1950
+Wire Wire Line
+ 6550 2950 6650 2950
+Wire Wire Line
+ 6550 5000 6700 5000
+Wire Wire Line
+ 6350 4000 6500 4000
+Wire Wire Line
+ 6400 6000 6650 6000
+Wire Wire Line
+ 6500 7050 6650 7050
+Wire Wire Line
+ 6350 8100 6550 8100
+Text Label 6400 1950 0 60 ~ 0
+d6
+Text Label 6550 2950 0 60 ~ 0
+d5
+Text Label 6400 4000 0 60 ~ 0
+d4
+Text Label 6600 5000 0 60 ~ 0
+d3
+Text Label 6450 6000 0 60 ~ 0
+d2
+Text Label 6550 7050 0 60 ~ 0
+d1
+Text Label 6400 8100 0 60 ~ 0
+d0
+$Comp
+L SKY130mode scmode1
+U 1 1 684B80A5
+P 9300 2750
+F 0 "scmode1" H 9300 2900 98 0000 C CNB
+F 1 "SKY130mode" H 9300 2650 118 0000 C CNB
+F 2 "" H 9300 2900 60 0001 C CNN
+F 3 "" H 9300 2900 60 0001 C CNN
+ 1 9300 2750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 6100 4750 6100
+Connection ~ 4750 6100
+$Comp
+L NAND_3 X?
+U 1 1 684CF822
+P 3500 950
+F 0 "X?" H 3650 950 60 0000 C CNN
+F 1 "NAND_3" H 3950 950 60 0000 C CNN
+F 2 "" H 3500 950 60 0001 C CNN
+F 3 "" H 3500 950 60 0001 C CNN
+ 1 3500 950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X?
+U 1 1 684CF965
+P 3550 1950
+F 0 "X?" H 3700 1950 60 0000 C CNN
+F 1 "NAND_3" H 4000 1950 60 0000 C CNN
+F 2 "" H 3550 1950 60 0001 C CNN
+F 3 "" H 3550 1950 60 0001 C CNN
+ 1 3550 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X?
+U 1 1 684CFC72
+P 3450 2950
+F 0 "X?" H 3600 2950 60 0000 C CNN
+F 1 "NAND_3" H 3900 2950 60 0000 C CNN
+F 2 "" H 3450 2950 60 0001 C CNN
+F 3 "" H 3450 2950 60 0001 C CNN
+ 1 3450 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X?
+U 1 1 684CFD5F
+P 3550 3950
+F 0 "X?" H 3700 3950 60 0000 C CNN
+F 1 "NAND_3" H 4000 3950 60 0000 C CNN
+F 2 "" H 3550 3950 60 0001 C CNN
+F 3 "" H 3550 3950 60 0001 C CNN
+ 1 3550 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X?
+U 1 1 684CFEB8
+P 3450 4950
+F 0 "X?" H 3600 4950 60 0000 C CNN
+F 1 "NAND_3" H 3900 4950 60 0000 C CNN
+F 2 "" H 3450 4950 60 0001 C CNN
+F 3 "" H 3450 4950 60 0001 C CNN
+ 1 3450 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X?
+U 1 1 684CFFA3
+P 3550 5950
+F 0 "X?" H 3700 5950 60 0000 C CNN
+F 1 "NAND_3" H 4000 5950 60 0000 C CNN
+F 2 "" H 3550 5950 60 0001 C CNN
+F 3 "" H 3550 5950 60 0001 C CNN
+ 1 3550 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X?
+U 1 1 684D025A
+P 3450 6950
+F 0 "X?" H 3600 6950 60 0000 C CNN
+F 1 "NAND_3" H 3900 6950 60 0000 C CNN
+F 2 "" H 3450 6950 60 0001 C CNN
+F 3 "" H 3450 6950 60 0001 C CNN
+ 1 3450 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X?
+U 1 1 684D0467
+P 3600 8050
+F 0 "X?" H 3750 8050 60 0000 C CNN
+F 1 "NAND_3" H 4050 8050 60 0000 C CNN
+F 2 "" H 3600 8050 60 0001 C CNN
+F 3 "" H 3600 8050 60 0001 C CNN
+ 1 3600 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X?
+U 1 1 684D06B2
+P 5400 8100
+F 0 "X?" H 5500 8100 60 0000 C CNN
+F 1 "NAND_2" H 5800 8100 60 0000 C CNN
+F 2 "" H 5400 8100 60 0001 C CNN
+F 3 "" H 5400 8100 60 0001 C CNN
+ 1 5400 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X?
+U 1 1 684D0797
+P 5550 7050
+F 0 "X?" H 5650 7050 60 0000 C CNN
+F 1 "NAND_2" H 5950 7050 60 0000 C CNN
+F 2 "" H 5550 7050 60 0001 C CNN
+F 3 "" H 5550 7050 60 0001 C CNN
+ 1 5550 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X?
+U 1 1 684D08E8
+P 5450 6000
+F 0 "X?" H 5550 6000 60 0000 C CNN
+F 1 "NAND_2" H 5850 6000 60 0000 C CNN
+F 2 "" H 5450 6000 60 0001 C CNN
+F 3 "" H 5450 6000 60 0001 C CNN
+ 1 5450 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X?
+U 1 1 684D0B9F
+P 5600 5000
+F 0 "X?" H 5700 5000 60 0000 C CNN
+F 1 "NAND_2" H 6000 5000 60 0000 C CNN
+F 2 "" H 5600 5000 60 0001 C CNN
+F 3 "" H 5600 5000 60 0001 C CNN
+ 1 5600 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X?
+U 1 1 684D0CA6
+P 5400 4000
+F 0 "X?" H 5500 4000 60 0000 C CNN
+F 1 "NAND_2" H 5800 4000 60 0000 C CNN
+F 2 "" H 5400 4000 60 0001 C CNN
+F 3 "" H 5400 4000 60 0001 C CNN
+ 1 5400 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X?
+U 1 1 684D0DA7
+P 5600 2950
+F 0 "X?" H 5700 2950 60 0000 C CNN
+F 1 "NAND_2" H 6000 2950 60 0000 C CNN
+F 2 "" H 5600 2950 60 0001 C CNN
+F 3 "" H 5600 2950 60 0001 C CNN
+ 1 5600 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X?
+U 1 1 684D0F38
+P 5400 1950
+F 0 "X?" H 5500 1950 60 0000 C CNN
+F 1 "NAND_2" H 5800 1950 60 0000 C CNN
+F 2 "" H 5400 1950 60 0001 C CNN
+F 3 "" H 5400 1950 60 0001 C CNN
+ 1 5400 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X?
+U 1 1 684D10A7
+P 5600 950
+F 0 "X?" H 5700 950 60 0000 C CNN
+F 1 "NAND_2" H 6000 950 60 0000 C CNN
+F 2 "" H 5600 950 60 0001 C CNN
+F 3 "" H 5600 950 60 0001 C CNN
+ 1 5600 950
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38.cir b/library/SubcircuitLibrary/SN74HC259/Decoder_38.cir
new file mode 100644
index 000000000..4a6e20d08
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38.cir
@@ -0,0 +1,28 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Decoder_38/Decoder_38.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 09:39:18 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 /S0_Bar /S1_Bar /S2_Bar /S0 /S1 /S2 /G_Bar /Vdd /Gnd /d6 /d4 /d0 /d7 /d5 /d2 /d1 /d3 PORT
+scmode1 SKY130mode
+X4 /S0_Bar /S1_Bar /Gnd /Vdd Net-_X14-Pad1_ /S2_Bar NAND_3
+X5 /S0_Bar /S1_Bar /Gnd /Vdd Net-_X5-Pad5_ /S2 NAND_3
+X1 /S0_Bar /S1 /Gnd /Vdd Net-_X1-Pad5_ /S2_Bar NAND_3
+X6 /S0_Bar /S1 /Gnd /Vdd Net-_X10-Pad1_ /S2 NAND_3
+X2 /S0 /S1_Bar /Gnd /Vdd Net-_X16-Pad1_ /S2_Bar NAND_3
+X7 /S0 /S1_Bar /Gnd /Vdd Net-_X12-Pad1_ /S2 NAND_3
+X3 /S0 /S1 /Gnd /Vdd Net-_X13-Pad1_ /S2_Bar NAND_3
+X8 /S0 /S1 /Gnd /Vdd Net-_X11-Pad1_ /S2 NAND_3
+X11 Net-_X11-Pad1_ /Gnd /Vdd /d0 /G_Bar NAND_2
+X13 Net-_X13-Pad1_ /Gnd /Vdd /d1 /G_Bar NAND_2
+X12 Net-_X12-Pad1_ /Gnd /Vdd /d2 /G_Bar NAND_2
+X16 Net-_X16-Pad1_ /Gnd /Vdd /d3 /G_Bar NAND_2
+X10 Net-_X10-Pad1_ /Gnd /Vdd /d4 /G_Bar NAND_2
+X15 Net-_X1-Pad5_ /Gnd /Vdd /d5 /G_Bar NAND_2
+X9 Net-_X5-Pad5_ /Gnd /Vdd /d6 /G_Bar NAND_2
+X14 Net-_X14-Pad1_ /Gnd /Vdd /d7 /G_Bar NAND_2
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38.cir.out b/library/SubcircuitLibrary/SN74HC259/Decoder_38.cir.out
new file mode 100644
index 000000000..66b8007cd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38.cir.out
@@ -0,0 +1,33 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/decoder_38/decoder_38.cir
+
+.include NAND_2.sub
+.include NAND_3.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* u1 /s0_bar /s1_bar /s2_bar /s0 /s1 /s2 /g_bar /vdd /gnd /d6 /d4 /d0 /d7 /d5 /d2 /d1 /d3 port
+* s c m o d e
+x4 /s0_bar /s1_bar /gnd /vdd net-_x14-pad1_ /s2_bar NAND_3
+x5 /s0_bar /s1_bar /gnd /vdd net-_x5-pad5_ /s2 NAND_3
+x1 /s0_bar /s1 /gnd /vdd net-_x1-pad5_ /s2_bar NAND_3
+x6 /s0_bar /s1 /gnd /vdd net-_x10-pad1_ /s2 NAND_3
+x2 /s0 /s1_bar /gnd /vdd net-_x16-pad1_ /s2_bar NAND_3
+x7 /s0 /s1_bar /gnd /vdd net-_x12-pad1_ /s2 NAND_3
+x3 /s0 /s1 /gnd /vdd net-_x13-pad1_ /s2_bar NAND_3
+x8 /s0 /s1 /gnd /vdd net-_x11-pad1_ /s2 NAND_3
+x11 net-_x11-pad1_ /gnd /vdd /d0 /g_bar NAND_2
+x13 net-_x13-pad1_ /gnd /vdd /d1 /g_bar NAND_2
+x12 net-_x12-pad1_ /gnd /vdd /d2 /g_bar NAND_2
+x16 net-_x16-pad1_ /gnd /vdd /d3 /g_bar NAND_2
+x10 net-_x10-pad1_ /gnd /vdd /d4 /g_bar NAND_2
+x15 net-_x1-pad5_ /gnd /vdd /d5 /g_bar NAND_2
+x9 net-_x5-pad5_ /gnd /vdd /d6 /g_bar NAND_2
+x14 net-_x14-pad1_ /gnd /vdd /d7 /g_bar NAND_2
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38.pro b/library/SubcircuitLibrary/SN74HC259/Decoder_38.pro
new file mode 100644
index 000000000..3b4e7cf7a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38.pro
@@ -0,0 +1,74 @@
+update=Sat Jun 14 09:34:32 2025
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=Decoder_38-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38.sch b/library/SubcircuitLibrary/SN74HC259/Decoder_38.sch
new file mode 100644
index 000000000..935b86cf1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38.sch
@@ -0,0 +1,745 @@
+EESchema Schematic File Version 2
+LIBS:Decoder_38-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:Decoder_38-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Connection ~ 1150 2900
+Connection ~ 1150 3050
+Connection ~ 1150 3200
+Connection ~ 1150 3500
+Connection ~ 1150 3650
+Connection ~ 1150 3800
+Wire Wire Line
+ 3050 800 1350 800
+Wire Wire Line
+ 1350 800 1350 2900
+Wire Wire Line
+ 1350 2900 1150 2900
+Wire Wire Line
+ 3050 950 1400 950
+Wire Wire Line
+ 1400 950 1400 3050
+Wire Wire Line
+ 1150 3050 1750 3050
+Wire Wire Line
+ 3050 1100 1450 1100
+Wire Wire Line
+ 1450 1100 1450 3200
+Wire Wire Line
+ 1150 3200 1850 3200
+Wire Wire Line
+ 1150 3800 1500 3800
+Wire Wire Line
+ 1350 3800 1350 8200
+Wire Wire Line
+ 1150 3650 1550 3650
+Wire Wire Line
+ 1400 3650 1400 8050
+Wire Wire Line
+ 1150 3500 1450 3500
+Wire Wire Line
+ 1450 3500 1450 7900
+Wire Wire Line
+ 3100 1800 1350 1800
+Connection ~ 1350 1800
+Wire Wire Line
+ 3100 1950 1400 1950
+Connection ~ 1400 1950
+Wire Wire Line
+ 3100 2100 1500 2100
+Wire Wire Line
+ 1500 2100 1500 3800
+Connection ~ 1350 3800
+Wire Wire Line
+ 3000 2800 1350 2800
+Connection ~ 1350 2800
+Wire Wire Line
+ 3000 2950 1550 2950
+Wire Wire Line
+ 1550 2950 1550 3650
+Connection ~ 1400 3650
+Wire Wire Line
+ 3000 3100 1450 3100
+Connection ~ 1450 3100
+Wire Wire Line
+ 3100 3800 1600 3800
+Wire Wire Line
+ 1600 3800 1600 2800
+Connection ~ 1600 2800
+Wire Wire Line
+ 3100 3950 1400 3950
+Connection ~ 1400 3950
+Wire Wire Line
+ 3100 4100 1350 4100
+Connection ~ 1350 4100
+Wire Wire Line
+ 3000 4800 1450 4800
+Connection ~ 1450 4800
+Wire Wire Line
+ 3000 4950 1650 4950
+Wire Wire Line
+ 1650 4950 1650 3050
+Connection ~ 1400 3050
+Wire Wire Line
+ 3000 5100 1700 5100
+Wire Wire Line
+ 1700 5100 1700 3200
+Connection ~ 1450 3200
+Wire Wire Line
+ 1450 7900 3150 7900
+Wire Wire Line
+ 1400 8050 3150 8050
+Wire Wire Line
+ 1350 8200 3150 8200
+Wire Wire Line
+ 3100 5800 1450 5800
+Connection ~ 1450 5800
+Wire Wire Line
+ 3100 6100 1350 6100
+Connection ~ 1350 6100
+Wire Wire Line
+ 3100 5950 1750 5950
+Wire Wire Line
+ 1750 5950 1750 3050
+Connection ~ 1650 3050
+Wire Wire Line
+ 3000 6800 1450 6800
+Connection ~ 1450 6800
+Wire Wire Line
+ 3000 6950 1400 6950
+Connection ~ 1400 6950
+Wire Wire Line
+ 3000 7100 1850 7100
+Wire Wire Line
+ 1850 7100 1850 3200
+Connection ~ 1700 3200
+Wire Wire Line
+ 3500 500 5600 500
+Wire Wire Line
+ 3950 500 3950 7650
+Wire Wire Line
+ 3950 7600 3600 7600
+Wire Wire Line
+ 3600 8500 3800 8500
+Wire Wire Line
+ 3800 1400 3800 8550
+Wire Wire Line
+ 3500 1400 5600 1400
+Wire Wire Line
+ 3550 1500 5400 1500
+Connection ~ 3950 1500
+Wire Wire Line
+ 3550 2400 5400 2400
+Connection ~ 3800 2400
+Wire Wire Line
+ 3450 2500 5600 2500
+Connection ~ 3950 2500
+Wire Wire Line
+ 3450 3400 5600 3400
+Connection ~ 3800 3400
+Wire Wire Line
+ 3550 3500 5400 3500
+Connection ~ 3950 3500
+Wire Wire Line
+ 3550 4400 5300 4400
+Connection ~ 3800 4400
+Wire Wire Line
+ 3450 4500 5600 4500
+Connection ~ 3950 4500
+Wire Wire Line
+ 3450 5400 5500 5400
+Connection ~ 3800 5400
+Wire Wire Line
+ 3550 5500 5450 5500
+Connection ~ 3950 5500
+Wire Wire Line
+ 3550 6400 5350 6400
+Connection ~ 3800 6400
+Wire Wire Line
+ 3450 6500 5550 6500
+Connection ~ 3950 6500
+Wire Wire Line
+ 3450 7400 5400 7400
+Connection ~ 3800 7400
+Wire Wire Line
+ 4550 950 4800 950
+Wire Wire Line
+ 4800 950 4800 850
+Wire Wire Line
+ 4800 850 5100 850
+Wire Wire Line
+ 4600 1950 4600 1850
+Wire Wire Line
+ 4600 1850 4900 1850
+Wire Wire Line
+ 4500 2950 4700 2950
+Wire Wire Line
+ 4700 2950 4700 2850
+Wire Wire Line
+ 4700 2850 5100 2850
+Wire Wire Line
+ 4600 3950 4600 3900
+Wire Wire Line
+ 4600 3900 4900 3900
+Wire Wire Line
+ 4500 4950 4850 4950
+Wire Wire Line
+ 4850 4950 4850 4900
+Wire Wire Line
+ 4850 4900 5100 4900
+Wire Wire Line
+ 4600 5950 4650 5950
+Wire Wire Line
+ 4650 5950 4650 5900
+Wire Wire Line
+ 4650 5900 4950 5900
+Wire Wire Line
+ 4500 6950 5050 6950
+Wire Wire Line
+ 4650 8050 4650 8000
+Wire Wire Line
+ 4650 8000 4900 8000
+Connection ~ 3950 500
+Connection ~ 3800 1400
+Wire Wire Line
+ 5400 3500 5400 3550
+Wire Wire Line
+ 5300 4400 5300 4450
+Wire Wire Line
+ 5300 4450 5400 4450
+Wire Wire Line
+ 5600 4500 5600 4550
+Wire Wire Line
+ 5500 5400 5500 5450
+Wire Wire Line
+ 5500 5450 5600 5450
+Wire Wire Line
+ 5450 5500 5450 5550
+Wire Wire Line
+ 5350 6400 5350 6450
+Wire Wire Line
+ 5350 6450 5450 6450
+Wire Wire Line
+ 5550 6500 5550 6600
+Wire Wire Line
+ 5400 7400 5400 7500
+Wire Wire Line
+ 5400 7500 5550 7500
+Wire Wire Line
+ 3950 7650 5400 7650
+Connection ~ 3950 7600
+Wire Wire Line
+ 3800 8550 5400 8550
+Connection ~ 3800 8500
+Wire Wire Line
+ 5100 1050 4750 1050
+Wire Wire Line
+ 4750 1050 4750 8800
+Wire Wire Line
+ 4750 8800 1200 8800
+Wire Wire Line
+ 4900 2050 4750 2050
+Connection ~ 4750 2050
+Wire Wire Line
+ 5100 3050 4750 3050
+Connection ~ 4750 3050
+Wire Wire Line
+ 4900 4100 4750 4100
+Connection ~ 4750 4100
+Wire Wire Line
+ 5100 5100 4750 5100
+Connection ~ 4750 5100
+Wire Wire Line
+ 5050 7150 4750 7150
+Connection ~ 4750 7150
+Wire Wire Line
+ 4750 8200 4900 8200
+Connection ~ 4750 8200
+$Comp
+L PORT U1
+U 1 1 684B4EE5
+P 900 2900
+F 0 "U1" H 950 3000 30 0000 C CNN
+F 1 "PORT" H 900 2900 30 0000 C CNN
+F 2 "" H 900 2900 60 0000 C CNN
+F 3 "" H 900 2900 60 0000 C CNN
+ 1 900 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B5027
+P 900 3050
+F 0 "U1" H 950 3150 30 0000 C CNN
+F 1 "PORT" H 900 3050 30 0000 C CNN
+F 2 "" H 900 3050 60 0000 C CNN
+F 3 "" H 900 3050 60 0000 C CNN
+ 2 900 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B5070
+P 900 3200
+F 0 "U1" H 950 3300 30 0000 C CNN
+F 1 "PORT" H 900 3200 30 0000 C CNN
+F 2 "" H 900 3200 60 0000 C CNN
+F 3 "" H 900 3200 60 0000 C CNN
+ 3 900 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B50ED
+P 900 3500
+F 0 "U1" H 950 3600 30 0000 C CNN
+F 1 "PORT" H 900 3500 30 0000 C CNN
+F 2 "" H 900 3500 60 0000 C CNN
+F 3 "" H 900 3500 60 0000 C CNN
+ 4 900 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684B5144
+P 900 3650
+F 0 "U1" H 950 3750 30 0000 C CNN
+F 1 "PORT" H 900 3650 30 0000 C CNN
+F 2 "" H 900 3650 60 0000 C CNN
+F 3 "" H 900 3650 60 0000 C CNN
+ 5 900 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684B51C5
+P 900 3800
+F 0 "U1" H 950 3900 30 0000 C CNN
+F 1 "PORT" H 900 3800 30 0000 C CNN
+F 2 "" H 900 3800 60 0000 C CNN
+F 3 "" H 900 3800 60 0000 C CNN
+ 6 900 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684B53AC
+P 950 8800
+F 0 "U1" H 1000 8900 30 0000 C CNN
+F 1 "PORT" H 950 8800 30 0000 C CNN
+F 2 "" H 950 8800 60 0000 C CNN
+F 3 "" H 950 8800 60 0000 C CNN
+ 7 950 8800
+ 1 0 0 -1
+$EndComp
+Text Label 1500 8800 0 60 ~ 0
+G_Bar
+Text Label 1150 2900 0 60 ~ 0
+S0_Bar
+Text Label 1150 3050 0 60 ~ 0
+S1_Bar
+Text Label 1150 3200 0 60 ~ 0
+S2_Bar
+Text Label 1150 3500 0 60 ~ 0
+S0
+Text Label 1150 3650 0 60 ~ 0
+S1
+Text Label 1150 3800 0 60 ~ 0
+S2
+$Comp
+L PORT U1
+U 8 1 684B5AAA
+P 4300 600
+F 0 "U1" H 4350 700 30 0000 C CNN
+F 1 "PORT" H 4300 600 30 0000 C CNN
+F 2 "" H 4300 600 60 0000 C CNN
+F 3 "" H 4300 600 60 0000 C CNN
+ 8 4300 600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684B5B1B
+P 4350 1300
+F 0 "U1" H 4400 1400 30 0000 C CNN
+F 1 "PORT" H 4350 1300 30 0000 C CNN
+F 2 "" H 4350 1300 60 0000 C CNN
+F 3 "" H 4350 1300 60 0000 C CNN
+ 9 4350 1300
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4050 600 4000 600
+Wire Wire Line
+ 4000 600 4000 500
+Connection ~ 4000 500
+Wire Wire Line
+ 4100 1300 4100 1400
+Connection ~ 4100 1400
+Text Label 4000 500 0 60 ~ 0
+Vdd
+Text Label 4100 1400 0 60 ~ 0
+Gnd
+$Comp
+L PORT U1
+U 13 1 684B5F75
+P 6900 950
+F 0 "U1" H 6950 1050 30 0000 C CNN
+F 1 "PORT" H 6900 950 30 0000 C CNN
+F 2 "" H 6900 950 60 0000 C CNN
+F 3 "" H 6900 950 60 0000 C CNN
+ 13 6900 950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684B6132
+P 6750 1950
+F 0 "U1" H 6800 2050 30 0000 C CNN
+F 1 "PORT" H 6750 1950 30 0000 C CNN
+F 2 "" H 6750 1950 60 0000 C CNN
+F 3 "" H 6750 1950 60 0000 C CNN
+ 10 6750 1950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 684B6260
+P 6900 2950
+F 0 "U1" H 6950 3050 30 0000 C CNN
+F 1 "PORT" H 6900 2950 30 0000 C CNN
+F 2 "" H 6900 2950 60 0000 C CNN
+F 3 "" H 6900 2950 60 0000 C CNN
+ 14 6900 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 684B63FD
+P 6750 4000
+F 0 "U1" H 6800 4100 30 0000 C CNN
+F 1 "PORT" H 6750 4000 30 0000 C CNN
+F 2 "" H 6750 4000 60 0000 C CNN
+F 3 "" H 6750 4000 60 0000 C CNN
+ 11 6750 4000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 684B6812
+P 6950 5000
+F 0 "U1" H 7000 5100 30 0000 C CNN
+F 1 "PORT" H 6950 5000 30 0000 C CNN
+F 2 "" H 6950 5000 60 0000 C CNN
+F 3 "" H 6950 5000 60 0000 C CNN
+ 17 6950 5000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 684B6911
+P 6900 6000
+F 0 "U1" H 6950 6100 30 0000 C CNN
+F 1 "PORT" H 6900 6000 30 0000 C CNN
+F 2 "" H 6900 6000 60 0000 C CNN
+F 3 "" H 6900 6000 60 0000 C CNN
+ 15 6900 6000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 684B6A00
+P 6900 7050
+F 0 "U1" H 6950 7150 30 0000 C CNN
+F 1 "PORT" H 6900 7050 30 0000 C CNN
+F 2 "" H 6900 7050 60 0000 C CNN
+F 3 "" H 6900 7050 60 0000 C CNN
+ 16 6900 7050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 684B6ADF
+P 6800 8100
+F 0 "U1" H 6850 8200 30 0000 C CNN
+F 1 "PORT" H 6800 8100 30 0000 C CNN
+F 2 "" H 6800 8100 60 0000 C CNN
+F 3 "" H 6800 8100 60 0000 C CNN
+ 12 6800 8100
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6550 950 6650 950
+Text Label 6550 950 0 60 ~ 0
+d7
+Wire Wire Line
+ 6350 1950 6500 1950
+Wire Wire Line
+ 6550 2950 6650 2950
+Wire Wire Line
+ 6550 5000 6700 5000
+Wire Wire Line
+ 6350 4000 6500 4000
+Wire Wire Line
+ 6400 6000 6650 6000
+Wire Wire Line
+ 6500 7050 6650 7050
+Wire Wire Line
+ 6350 8100 6550 8100
+Text Label 6400 1950 0 60 ~ 0
+d6
+Text Label 6550 2950 0 60 ~ 0
+d5
+Text Label 6400 4000 0 60 ~ 0
+d4
+Text Label 6600 5000 0 60 ~ 0
+d3
+Text Label 6450 6000 0 60 ~ 0
+d2
+Text Label 6550 7050 0 60 ~ 0
+d1
+Text Label 6400 8100 0 60 ~ 0
+d0
+$Comp
+L SKY130mode scmode1
+U 1 1 684B80A5
+P 9300 2750
+F 0 "scmode1" H 9300 2900 98 0000 C CNB
+F 1 "SKY130mode" H 9300 2650 118 0000 C CNB
+F 2 "" H 9300 2900 60 0001 C CNN
+F 3 "" H 9300 2900 60 0001 C CNN
+ 1 9300 2750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 6100 4750 6100
+Connection ~ 4750 6100
+$Comp
+L NAND_3 X4
+U 1 1 684CF822
+P 3500 950
+F 0 "X4" H 3650 950 60 0000 C CNN
+F 1 "NAND_3" H 3950 950 60 0000 C CNN
+F 2 "" H 3500 950 60 0001 C CNN
+F 3 "" H 3500 950 60 0001 C CNN
+ 1 3500 950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X5
+U 1 1 684CF965
+P 3550 1950
+F 0 "X5" H 3700 1950 60 0000 C CNN
+F 1 "NAND_3" H 4000 1950 60 0000 C CNN
+F 2 "" H 3550 1950 60 0001 C CNN
+F 3 "" H 3550 1950 60 0001 C CNN
+ 1 3550 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X1
+U 1 1 684CFC72
+P 3450 2950
+F 0 "X1" H 3600 2950 60 0000 C CNN
+F 1 "NAND_3" H 3900 2950 60 0000 C CNN
+F 2 "" H 3450 2950 60 0001 C CNN
+F 3 "" H 3450 2950 60 0001 C CNN
+ 1 3450 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X6
+U 1 1 684CFD5F
+P 3550 3950
+F 0 "X6" H 3700 3950 60 0000 C CNN
+F 1 "NAND_3" H 4000 3950 60 0000 C CNN
+F 2 "" H 3550 3950 60 0001 C CNN
+F 3 "" H 3550 3950 60 0001 C CNN
+ 1 3550 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X2
+U 1 1 684CFEB8
+P 3450 4950
+F 0 "X2" H 3600 4950 60 0000 C CNN
+F 1 "NAND_3" H 3900 4950 60 0000 C CNN
+F 2 "" H 3450 4950 60 0001 C CNN
+F 3 "" H 3450 4950 60 0001 C CNN
+ 1 3450 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X7
+U 1 1 684CFFA3
+P 3550 5950
+F 0 "X7" H 3700 5950 60 0000 C CNN
+F 1 "NAND_3" H 4000 5950 60 0000 C CNN
+F 2 "" H 3550 5950 60 0001 C CNN
+F 3 "" H 3550 5950 60 0001 C CNN
+ 1 3550 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X3
+U 1 1 684D025A
+P 3450 6950
+F 0 "X3" H 3600 6950 60 0000 C CNN
+F 1 "NAND_3" H 3900 6950 60 0000 C CNN
+F 2 "" H 3450 6950 60 0001 C CNN
+F 3 "" H 3450 6950 60 0001 C CNN
+ 1 3450 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_3 X8
+U 1 1 684D0467
+P 3600 8050
+F 0 "X8" H 3750 8050 60 0000 C CNN
+F 1 "NAND_3" H 4050 8050 60 0000 C CNN
+F 2 "" H 3600 8050 60 0001 C CNN
+F 3 "" H 3600 8050 60 0001 C CNN
+ 1 3600 8050
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X11
+U 1 1 684D06B2
+P 5400 8100
+F 0 "X11" H 5500 8100 60 0000 C CNN
+F 1 "NAND_2" H 5800 8100 60 0000 C CNN
+F 2 "" H 5400 8100 60 0001 C CNN
+F 3 "" H 5400 8100 60 0001 C CNN
+ 1 5400 8100
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X13
+U 1 1 684D0797
+P 5550 7050
+F 0 "X13" H 5650 7050 60 0000 C CNN
+F 1 "NAND_2" H 5950 7050 60 0000 C CNN
+F 2 "" H 5550 7050 60 0001 C CNN
+F 3 "" H 5550 7050 60 0001 C CNN
+ 1 5550 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X12
+U 1 1 684D08E8
+P 5450 6000
+F 0 "X12" H 5550 6000 60 0000 C CNN
+F 1 "NAND_2" H 5850 6000 60 0000 C CNN
+F 2 "" H 5450 6000 60 0001 C CNN
+F 3 "" H 5450 6000 60 0001 C CNN
+ 1 5450 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X16
+U 1 1 684D0B9F
+P 5600 5000
+F 0 "X16" H 5700 5000 60 0000 C CNN
+F 1 "NAND_2" H 6000 5000 60 0000 C CNN
+F 2 "" H 5600 5000 60 0001 C CNN
+F 3 "" H 5600 5000 60 0001 C CNN
+ 1 5600 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X10
+U 1 1 684D0CA6
+P 5400 4000
+F 0 "X10" H 5500 4000 60 0000 C CNN
+F 1 "NAND_2" H 5800 4000 60 0000 C CNN
+F 2 "" H 5400 4000 60 0001 C CNN
+F 3 "" H 5400 4000 60 0001 C CNN
+ 1 5400 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X15
+U 1 1 684D0DA7
+P 5600 2950
+F 0 "X15" H 5700 2950 60 0000 C CNN
+F 1 "NAND_2" H 6000 2950 60 0000 C CNN
+F 2 "" H 5600 2950 60 0001 C CNN
+F 3 "" H 5600 2950 60 0001 C CNN
+ 1 5600 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X9
+U 1 1 684D0F38
+P 5400 1950
+F 0 "X9" H 5500 1950 60 0000 C CNN
+F 1 "NAND_2" H 5800 1950 60 0000 C CNN
+F 2 "" H 5400 1950 60 0001 C CNN
+F 3 "" H 5400 1950 60 0001 C CNN
+ 1 5400 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L NAND_2 X14
+U 1 1 684D10A7
+P 5600 950
+F 0 "X14" H 5700 950 60 0000 C CNN
+F 1 "NAND_2" H 6000 950 60 0000 C CNN
+F 2 "" H 5600 950 60 0001 C CNN
+F 3 "" H 5600 950 60 0001 C CNN
+ 1 5600 950
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38.sub b/library/SubcircuitLibrary/SN74HC259/Decoder_38.sub
new file mode 100644
index 000000000..67271ac43
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38.sub
@@ -0,0 +1,27 @@
+* Subcircuit Decoder_38
+.subckt Decoder_38 /s0_bar /s1_bar /s2_bar /s0 /s1 /s2 /g_bar /vdd /gnd /d6 /d4 /d0 /d7 /d5 /d2 /d1 /d3
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/decoder_38/decoder_38.cir
+.include NAND_2.sub
+.include NAND_3.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* s c m o d e
+x4 /s0_bar /s1_bar /gnd /vdd net-_x14-pad1_ /s2_bar NAND_3
+x5 /s0_bar /s1_bar /gnd /vdd net-_x5-pad5_ /s2 NAND_3
+x1 /s0_bar /s1 /gnd /vdd net-_x1-pad5_ /s2_bar NAND_3
+x6 /s0_bar /s1 /gnd /vdd net-_x10-pad1_ /s2 NAND_3
+x2 /s0 /s1_bar /gnd /vdd net-_x16-pad1_ /s2_bar NAND_3
+x7 /s0 /s1_bar /gnd /vdd net-_x12-pad1_ /s2 NAND_3
+x3 /s0 /s1 /gnd /vdd net-_x13-pad1_ /s2_bar NAND_3
+x8 /s0 /s1 /gnd /vdd net-_x11-pad1_ /s2 NAND_3
+x11 net-_x11-pad1_ /gnd /vdd /d0 /g_bar NAND_2
+x13 net-_x13-pad1_ /gnd /vdd /d1 /g_bar NAND_2
+x12 net-_x12-pad1_ /gnd /vdd /d2 /g_bar NAND_2
+x16 net-_x16-pad1_ /gnd /vdd /d3 /g_bar NAND_2
+x10 net-_x10-pad1_ /gnd /vdd /d4 /g_bar NAND_2
+x15 net-_x1-pad5_ /gnd /vdd /d5 /g_bar NAND_2
+x9 net-_x5-pad5_ /gnd /vdd /d6 /g_bar NAND_2
+x14 net-_x14-pad1_ /gnd /vdd /d7 /g_bar NAND_2
+* Control Statements
+
+.ends Decoder_38
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage-cache.lib b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage-cache.lib
new file mode 100644
index 000000000..5d471583c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage-cache.lib
@@ -0,0 +1,104 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# D_Latch
+#
+DEF D_Latch X 0 40 Y Y 1 F N
+F0 "X" 100 -100 60 H V C CNN
+F1 "D_Latch" 100 50 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -500 500 650 -450 0 1 0 N
+X D 1 -700 300 200 R 50 50 1 1 I
+X LE 2 -700 0 200 R 50 50 1 1 I
+X RE 3 -700 -300 200 R 50 50 1 1 I
+X Gnd 4 0 -650 200 U 50 50 1 1 I
+X Vdd 5 0 700 200 D 50 50 1 1 I
+X Q 6 850 200 200 L 50 50 1 1 O
+X Q_Bar 7 850 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Decoder_38
+#
+DEF Decoder_38 X 0 40 Y Y 1 F N
+F0 "X" 0 -200 60 H V C CNN
+F1 "Decoder_38" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -700 1200 700 -1200 0 1 0 N
+X S0_Bar 1 -900 850 200 R 50 50 1 1 I
+X S1_Bar 2 -900 550 200 R 50 50 1 1 I
+X S2_Bar 3 -900 250 200 R 50 50 1 1 I
+X S0 4 -900 -300 200 R 50 50 1 1 I
+X S1 5 -900 -600 200 R 50 50 1 1 I
+X S2 6 -900 -900 200 R 50 50 1 1 I
+X G_Bar 7 -900 0 200 R 50 50 1 1 I
+X Vdd 8 0 1400 200 D 50 50 1 1 I
+X Gnd 9 0 -1400 200 U 50 50 1 1 I
+X d6 10 900 -650 200 L 50 50 1 1 O
+X d4 11 900 -150 200 L 50 50 1 1 O
+X d0 12 900 900 200 L 50 50 1 1 O
+X d7 13 900 -900 200 L 50 50 1 1 O
+X d5 14 900 -400 200 L 50 50 1 1 O
+X d2 15 900 400 200 L 50 50 1 1 O
+X d1 16 900 650 200 L 50 50 1 1 O
+X d3 17 900 150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.bak b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.bak
new file mode 100644
index 000000000..584a16a11
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.bak
@@ -0,0 +1,583 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:Decoder_38_Address_Latch_storage-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L D_Latch X2
+U 1 1 684B8D5D
+P 2100 1700
+F 0 "X2" H 2200 1600 60 0000 C CNN
+F 1 "D_Latch" H 2200 1750 60 0000 C CNN
+F 2 "" H 2100 1700 60 0001 C CNN
+F 3 "" H 2100 1700 60 0001 C CNN
+ 1 2100 1700
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X1
+U 1 1 684B8DE8
+P 1950 3300
+F 0 "X1" H 2050 3200 60 0000 C CNN
+F 1 "D_Latch" H 2050 3350 60 0000 C CNN
+F 2 "" H 1950 3300 60 0001 C CNN
+F 3 "" H 1950 3300 60 0001 C CNN
+ 1 1950 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X3
+U 1 1 684B8EF1
+P 2100 4750
+F 0 "X3" H 2200 4650 60 0000 C CNN
+F 1 "D_Latch" H 2200 4800 60 0000 C CNN
+F 2 "" H 2100 4750 60 0001 C CNN
+F 3 "" H 2100 4750 60 0001 C CNN
+ 1 2100 4750
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X4
+U 1 1 684B8FAC
+P 2200 6350
+F 0 "X4" H 2300 6250 60 0000 C CNN
+F 1 "D_Latch" H 2300 6400 60 0000 C CNN
+F 2 "" H 2200 6350 60 0001 C CNN
+F 3 "" H 2200 6350 60 0001 C CNN
+ 1 2200 6350
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X5
+U 1 1 684B9053
+P 4650 1700
+F 0 "X5" H 4750 1600 60 0000 C CNN
+F 1 "D_Latch" H 4750 1750 60 0000 C CNN
+F 2 "" H 4650 1700 60 0001 C CNN
+F 3 "" H 4650 1700 60 0001 C CNN
+ 1 4650 1700
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X6
+U 1 1 684B90D4
+P 4750 3300
+F 0 "X6" H 4850 3200 60 0000 C CNN
+F 1 "D_Latch" H 4850 3350 60 0000 C CNN
+F 2 "" H 4750 3300 60 0001 C CNN
+F 3 "" H 4750 3300 60 0001 C CNN
+ 1 4750 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X7
+U 1 1 684B9169
+P 4950 4750
+F 0 "X7" H 5050 4650 60 0000 C CNN
+F 1 "D_Latch" H 5050 4800 60 0000 C CNN
+F 2 "" H 4950 4750 60 0001 C CNN
+F 3 "" H 4950 4750 60 0001 C CNN
+ 1 4950 4750
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X8
+U 1 1 684B91E8
+P 5150 6350
+F 0 "X8" H 5250 6250 60 0000 C CNN
+F 1 "D_Latch" H 5250 6400 60 0000 C CNN
+F 2 "" H 5150 6350 60 0001 C CNN
+F 3 "" H 5150 6350 60 0001 C CNN
+ 1 5150 6350
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2100 1000 4650 1000
+Wire Wire Line
+ 2200 5650 5150 5650
+Wire Wire Line
+ 3450 800 3450 5650
+Connection ~ 3450 5650
+Connection ~ 3450 1000
+Wire Wire Line
+ 2200 7000 5150 7000
+Wire Wire Line
+ 2100 2350 4650 2350
+Wire Wire Line
+ 3300 2200 3300 7000
+Connection ~ 3300 7000
+Connection ~ 3300 2350
+Wire Wire Line
+ 2100 4050 4950 4050
+Connection ~ 3450 4050
+Wire Wire Line
+ 1950 2600 4750 2600
+Connection ~ 3450 2600
+Wire Wire Line
+ 1950 3950 4750 3950
+Connection ~ 3300 3950
+Wire Wire Line
+ 2100 5400 4950 5400
+Connection ~ 3300 5400
+Wire Wire Line
+ 2800 1400 3050 1400
+Wire Wire Line
+ 3050 1400 3050 6050
+Wire Wire Line
+ 3050 6050 2900 6050
+Wire Wire Line
+ 5850 6050 6200 6050
+Wire Wire Line
+ 6200 6050 6200 1400
+Wire Wire Line
+ 5350 1400 6400 1400
+Wire Wire Line
+ 2650 3000 3050 3000
+Connection ~ 3050 3000
+Wire Wire Line
+ 5450 3000 6200 3000
+Connection ~ 6200 3000
+Wire Wire Line
+ 2800 4450 3050 4450
+Connection ~ 3050 4450
+Wire Wire Line
+ 5650 4450 6200 4450
+Connection ~ 6200 4450
+Wire Wire Line
+ 3050 5850 6200 5850
+Connection ~ 6200 5850
+Connection ~ 3050 5850
+Text Label 6200 1400 0 60 ~ 0
+D
+Text Label 3450 1000 0 60 ~ 0
+Vdd
+Text Label 3300 2350 0 60 ~ 0
+Gnd
+Wire Wire Line
+ 2800 2000 3200 2000
+Wire Wire Line
+ 3200 2000 3200 6650
+Wire Wire Line
+ 3200 6650 2900 6650
+Wire Wire Line
+ 2800 5050 3200 5050
+Connection ~ 3200 5050
+Wire Wire Line
+ 2650 3600 3200 3600
+Connection ~ 3200 3600
+Wire Wire Line
+ 5350 2000 6000 2000
+Wire Wire Line
+ 6000 2000 6000 6650
+Wire Wire Line
+ 6000 6650 5850 6650
+Wire Wire Line
+ 5650 5050 6000 5050
+Connection ~ 6000 5050
+Wire Wire Line
+ 5450 3600 6000 3600
+Connection ~ 6000 3600
+Wire Wire Line
+ 3200 2500 6000 2500
+Connection ~ 6000 2500
+Connection ~ 3200 2500
+$Comp
+L PORT U1
+U 12 1 684BA095
+P 6650 1400
+F 0 "U1" H 6700 1500 30 0000 C CNN
+F 1 "PORT" H 6650 1400 30 0000 C CNN
+F 2 "" H 6650 1400 60 0000 C CNN
+F 3 "" H 6650 1400 60 0000 C CNN
+ 12 6650 1400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 684BA0F0
+P 5650 2200
+F 0 "U1" H 5700 2300 30 0000 C CNN
+F 1 "PORT" H 5650 2200 30 0000 C CNN
+F 2 "" H 5650 2200 60 0000 C CNN
+F 3 "" H 5650 2200 60 0000 C CNN
+ 11 5650 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684BA2EB
+P 3200 800
+F 0 "U1" H 3250 900 30 0000 C CNN
+F 1 "PORT" H 3200 800 30 0000 C CNN
+F 2 "" H 3200 800 60 0000 C CNN
+F 3 "" H 3200 800 60 0000 C CNN
+ 5 3200 800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684BA392
+P 3300 1950
+F 0 "U1" H 3350 2050 30 0000 C CNN
+F 1 "PORT" H 3300 1950 30 0000 C CNN
+F 2 "" H 3300 1950 60 0000 C CNN
+F 3 "" H 3300 1950 60 0000 C CNN
+ 6 3300 1950
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684BA46C
+P 850 1500
+F 0 "U1" H 900 1600 30 0000 C CNN
+F 1 "PORT" H 850 1500 30 0000 C CNN
+F 2 "" H 850 1500 60 0000 C CNN
+F 3 "" H 850 1500 60 0000 C CNN
+ 3 850 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684BA757
+P 750 3100
+F 0 "U1" H 800 3200 30 0000 C CNN
+F 1 "PORT" H 750 3100 30 0000 C CNN
+F 2 "" H 750 3100 60 0000 C CNN
+F 3 "" H 750 3100 60 0000 C CNN
+ 1 750 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684BA82C
+P 800 4550
+F 0 "U1" H 850 4650 30 0000 C CNN
+F 1 "PORT" H 800 4550 30 0000 C CNN
+F 2 "" H 800 4550 60 0000 C CNN
+F 3 "" H 800 4550 60 0000 C CNN
+ 2 800 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684BA923
+P 900 6150
+F 0 "U1" H 950 6250 30 0000 C CNN
+F 1 "PORT" H 900 6150 30 0000 C CNN
+F 2 "" H 900 6150 60 0000 C CNN
+F 3 "" H 900 6150 60 0000 C CNN
+ 4 900 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684BA9CD
+P 3950 6150
+F 0 "U1" H 4000 6250 30 0000 C CNN
+F 1 "PORT" H 3950 6150 30 0000 C CNN
+F 2 "" H 3950 6150 60 0000 C CNN
+F 3 "" H 3950 6150 60 0000 C CNN
+ 10 3950 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684BAAB0
+P 3750 4550
+F 0 "U1" H 3800 4650 30 0000 C CNN
+F 1 "PORT" H 3750 4550 30 0000 C CNN
+F 2 "" H 3750 4550 60 0000 C CNN
+F 3 "" H 3750 4550 60 0000 C CNN
+ 9 3750 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 684BAB6F
+P 3600 3100
+F 0 "U1" H 3650 3200 30 0000 C CNN
+F 1 "PORT" H 3600 3100 30 0000 C CNN
+F 2 "" H 3600 3100 60 0000 C CNN
+F 3 "" H 3600 3100 60 0000 C CNN
+ 8 3600 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684BAC3A
+P 3500 1500
+F 0 "U1" H 3550 1600 30 0000 C CNN
+F 1 "PORT" H 3500 1500 30 0000 C CNN
+F 2 "" H 3500 1500 60 0000 C CNN
+F 3 "" H 3500 1500 60 0000 C CNN
+ 7 3500 1500
+ 1 0 0 -1
+$EndComp
+Connection ~ 6200 1400
+Wire Wire Line
+ 5900 2200 6000 2200
+Connection ~ 6000 2200
+Wire Wire Line
+ 3750 1500 3800 1500
+Wire Wire Line
+ 3850 3100 3900 3100
+Wire Wire Line
+ 4000 4550 4100 4550
+Wire Wire Line
+ 4200 6150 4300 6150
+Wire Wire Line
+ 1150 6150 1350 6150
+Wire Wire Line
+ 1050 4550 1250 4550
+Wire Wire Line
+ 1000 3100 1100 3100
+Wire Wire Line
+ 1100 1500 1250 1500
+Wire Wire Line
+ 7550 2500 6400 2500
+Wire Wire Line
+ 6400 2500 6400 2900
+Wire Wire Line
+ 6400 2900 2800 2900
+Wire Wire Line
+ 2800 2900 2800 3300
+Wire Wire Line
+ 2800 3300 2650 3300
+Wire Wire Line
+ 7550 2750 4850 2750
+Wire Wire Line
+ 4850 2750 4850 2400
+Wire Wire Line
+ 4850 2400 2900 2400
+Wire Wire Line
+ 2900 2400 2900 1700
+Wire Wire Line
+ 2900 1700 2800 1700
+Wire Wire Line
+ 2800 4750 3550 4750
+Wire Wire Line
+ 3550 4750 3550 3650
+Wire Wire Line
+ 3550 3650 6550 3650
+Wire Wire Line
+ 6550 3650 6550 3000
+Wire Wire Line
+ 6550 3000 7550 3000
+Wire Wire Line
+ 2900 6350 3600 6350
+Wire Wire Line
+ 3600 6350 3600 3700
+Wire Wire Line
+ 3600 3700 6650 3700
+Wire Wire Line
+ 6650 3700 6650 3250
+Wire Wire Line
+ 6650 3250 7550 3250
+Wire Wire Line
+ 7550 3550 6700 3550
+Wire Wire Line
+ 6700 3550 6700 1700
+Wire Wire Line
+ 6700 1700 5350 1700
+Wire Wire Line
+ 7550 3800 6850 3800
+Wire Wire Line
+ 6850 3800 6850 3300
+Wire Wire Line
+ 6850 3300 5450 3300
+Wire Wire Line
+ 5650 4750 6450 4750
+Wire Wire Line
+ 6450 4750 6450 4050
+Wire Wire Line
+ 6450 4050 7550 4050
+Wire Wire Line
+ 5850 6350 6650 6350
+Wire Wire Line
+ 6650 6350 6650 4300
+Wire Wire Line
+ 6650 4300 7550 4300
+Wire Wire Line
+ 8450 4800 8450 5500
+Wire Wire Line
+ 8450 5500 3450 5500
+Connection ~ 3450 5500
+Wire Wire Line
+ 3450 900 8450 900
+Wire Wire Line
+ 8450 900 8450 2000
+Connection ~ 3450 900
+$Comp
+L Decoder_38 X9
+U 1 1 684B931F
+P 8450 3400
+F 0 "X9" H 8450 3200 60 0000 C CNN
+F 1 "Decoder_38" H 8450 3400 60 0000 C CNN
+F 2 "" H 8450 3400 60 0001 C CNN
+F 3 "" H 8450 3400 60 0001 C CNN
+ 1 8450 3400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 684B9841
+P 9900 2550
+F 0 "U1" H 9950 2650 30 0000 C CNN
+F 1 "PORT" H 9900 2550 30 0000 C CNN
+F 2 "" H 9900 2550 60 0000 C CNN
+F 3 "" H 9900 2550 60 0000 C CNN
+ 13 9900 2550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 684B989E
+P 9900 2850
+F 0 "U1" H 9950 2950 30 0000 C CNN
+F 1 "PORT" H 9900 2850 30 0000 C CNN
+F 2 "" H 9900 2850 60 0000 C CNN
+F 3 "" H 9900 2850 60 0000 C CNN
+ 14 9900 2850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 684B9931
+P 9900 3150
+F 0 "U1" H 9950 3250 30 0000 C CNN
+F 1 "PORT" H 9900 3150 30 0000 C CNN
+F 2 "" H 9900 3150 60 0000 C CNN
+F 3 "" H 9900 3150 60 0000 C CNN
+ 15 9900 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 684B99A6
+P 9900 3400
+F 0 "U1" H 9950 3500 30 0000 C CNN
+F 1 "PORT" H 9900 3400 30 0000 C CNN
+F 2 "" H 9900 3400 60 0000 C CNN
+F 3 "" H 9900 3400 60 0000 C CNN
+ 16 9900 3400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 684B9A1F
+P 9900 3700
+F 0 "U1" H 9950 3800 30 0000 C CNN
+F 1 "PORT" H 9900 3700 30 0000 C CNN
+F 2 "" H 9900 3700 60 0000 C CNN
+F 3 "" H 9900 3700 60 0000 C CNN
+ 17 9900 3700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 684B9B14
+P 9900 4000
+F 0 "U1" H 9950 4100 30 0000 C CNN
+F 1 "PORT" H 9900 4000 30 0000 C CNN
+F 2 "" H 9900 4000 60 0000 C CNN
+F 3 "" H 9900 4000 60 0000 C CNN
+ 18 9900 4000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 19 1 684B9B8D
+P 9900 4300
+F 0 "U1" H 9950 4400 30 0000 C CNN
+F 1 "PORT" H 9900 4300 30 0000 C CNN
+F 2 "" H 9900 4300 60 0000 C CNN
+F 3 "" H 9900 4300 60 0000 C CNN
+ 19 9900 4300
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9350 2550 9650 2550
+Wire Wire Line
+ 9350 2850 9650 2850
+Wire Wire Line
+ 9350 3150 9650 3150
+Wire Wire Line
+ 9350 3400 9650 3400
+Wire Wire Line
+ 9350 3700 9650 3700
+Wire Wire Line
+ 9350 4000 9650 4000
+Wire Wire Line
+ 9350 4300 9650 4300
+$Comp
+L SKY130mode scmode1
+U 1 1 684BA49C
+P 10150 1300
+F 0 "scmode1" H 10150 1450 98 0000 C CNB
+F 1 "SKY130mode" H 10150 1200 118 0000 C CNB
+F 2 "" H 10150 1450 60 0001 C CNN
+F 3 "" H 10150 1450 60 0001 C CNN
+ 1 10150 1300
+ 1 0 0 -1
+$EndComp
+NoConn ~ 1250 1850
+NoConn ~ 3800 1850
+NoConn ~ 1100 3450
+NoConn ~ 3900 3450
+NoConn ~ 1250 4900
+NoConn ~ 4100 4900
+NoConn ~ 1350 6500
+NoConn ~ 4300 6500
+NoConn ~ 17800 2250
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.cir b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.cir
new file mode 100644
index 000000000..af8ba3eaa
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.cir
@@ -0,0 +1,21 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Decoder_38_Address_Latch_storage/Decoder_38_Address_Latch_storage.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 09:52:10 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ /Vdd /Gnd Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ /D Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ PORT
+scmode1 SKY130mode
+X2 /D Net-_X2-Pad2_ Net-_U1-Pad11_ /Gnd /Vdd Net-_U1-Pad3_ ? D_Latch
+X1 /D Net-_X1-Pad2_ Net-_U1-Pad11_ /Gnd /Vdd Net-_U1-Pad1_ ? D_Latch
+X3 /D Net-_X3-Pad2_ Net-_U1-Pad11_ /Gnd /Vdd Net-_U1-Pad2_ ? D_Latch
+X4 /D Net-_X4-Pad2_ Net-_U1-Pad11_ /Gnd /Vdd Net-_U1-Pad4_ ? D_Latch
+X8 /D Net-_X8-Pad2_ Net-_U1-Pad11_ /Gnd /Vdd Net-_U1-Pad10_ ? D_Latch
+X7 /D Net-_X7-Pad2_ Net-_U1-Pad11_ /Gnd /Vdd Net-_U1-Pad9_ ? D_Latch
+X6 /D Net-_X6-Pad2_ Net-_U1-Pad11_ /Gnd /Vdd Net-_U1-Pad8_ ? D_Latch
+X5 /D Net-_X5-Pad2_ Net-_U1-Pad11_ /Gnd /Vdd Net-_U1-Pad7_ ? D_Latch
+X9 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad16_ /Vdd /Vdd Net-_X7-Pad2_ Net-_X5-Pad2_ Net-_X1-Pad2_ Net-_X8-Pad2_ Net-_X6-Pad2_ Net-_X3-Pad2_ Net-_X2-Pad2_ Net-_X4-Pad2_ Decoder_38
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.cir.out b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.cir.out
new file mode 100644
index 000000000..44855644c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.cir.out
@@ -0,0 +1,26 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/decoder_38_address_latch_storage/decoder_38_address_latch_storage.cir
+
+.include D_latch.sub
+.include Decoder_38.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ /vdd /gnd net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ /d net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ port
+* s c m o d e
+x2 /d net-_x2-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad3_ ? D_latch
+x1 /d net-_x1-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad1_ ? D_latch
+x3 /d net-_x3-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad2_ ? D_latch
+x4 /d net-_x4-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad4_ ? D_latch
+x8 /d net-_x8-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad10_ ? D_latch
+x7 /d net-_x7-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad9_ ? D_latch
+x6 /d net-_x6-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad8_ ? D_latch
+x5 /d net-_x5-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad7_ ? D_latch
+x9 net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad16_ /vdd /vdd net-_x7-pad2_ net-_x5-pad2_ net-_x1-pad2_ net-_x8-pad2_ net-_x6-pad2_ net-_x3-pad2_ net-_x2-pad2_ net-_x4-pad2_ Decoder_38
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.pro b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.sch b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.sch
new file mode 100644
index 000000000..d9508a2dc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.sch
@@ -0,0 +1,583 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:Decoder_38_Address_Latch_storage-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 2100 1000 4650 1000
+Wire Wire Line
+ 2200 5650 5150 5650
+Wire Wire Line
+ 3450 800 3450 5650
+Connection ~ 3450 5650
+Connection ~ 3450 1000
+Wire Wire Line
+ 2200 7000 5150 7000
+Wire Wire Line
+ 2100 2350 4650 2350
+Wire Wire Line
+ 3300 2200 3300 7000
+Connection ~ 3300 7000
+Connection ~ 3300 2350
+Wire Wire Line
+ 2100 4050 4950 4050
+Connection ~ 3450 4050
+Wire Wire Line
+ 1950 2600 4750 2600
+Connection ~ 3450 2600
+Wire Wire Line
+ 1950 3950 4750 3950
+Connection ~ 3300 3950
+Wire Wire Line
+ 2100 5400 4950 5400
+Connection ~ 3300 5400
+Wire Wire Line
+ 2800 1400 3050 1400
+Wire Wire Line
+ 3050 1400 3050 6050
+Wire Wire Line
+ 3050 6050 2900 6050
+Wire Wire Line
+ 5850 6050 6200 6050
+Wire Wire Line
+ 6200 6050 6200 1400
+Wire Wire Line
+ 5350 1400 6400 1400
+Wire Wire Line
+ 2650 3000 3050 3000
+Connection ~ 3050 3000
+Wire Wire Line
+ 5450 3000 6200 3000
+Connection ~ 6200 3000
+Wire Wire Line
+ 2800 4450 3050 4450
+Connection ~ 3050 4450
+Wire Wire Line
+ 5650 4450 6200 4450
+Connection ~ 6200 4450
+Wire Wire Line
+ 3050 5850 6200 5850
+Connection ~ 6200 5850
+Connection ~ 3050 5850
+Text Label 6200 1400 0 60 ~ 0
+D
+Text Label 3450 1000 0 60 ~ 0
+Vdd
+Text Label 3300 2350 0 60 ~ 0
+Gnd
+Wire Wire Line
+ 2800 2000 3200 2000
+Wire Wire Line
+ 3200 2000 3200 6650
+Wire Wire Line
+ 3200 6650 2900 6650
+Wire Wire Line
+ 2800 5050 3200 5050
+Connection ~ 3200 5050
+Wire Wire Line
+ 2650 3600 3200 3600
+Connection ~ 3200 3600
+Wire Wire Line
+ 5350 2000 6000 2000
+Wire Wire Line
+ 6000 2000 6000 6650
+Wire Wire Line
+ 6000 6650 5850 6650
+Wire Wire Line
+ 5650 5050 6000 5050
+Connection ~ 6000 5050
+Wire Wire Line
+ 5450 3600 6000 3600
+Connection ~ 6000 3600
+Wire Wire Line
+ 3200 2500 6000 2500
+Connection ~ 6000 2500
+Connection ~ 3200 2500
+$Comp
+L PORT U1
+U 12 1 684BA095
+P 6650 1400
+F 0 "U1" H 6700 1500 30 0000 C CNN
+F 1 "PORT" H 6650 1400 30 0000 C CNN
+F 2 "" H 6650 1400 60 0000 C CNN
+F 3 "" H 6650 1400 60 0000 C CNN
+ 12 6650 1400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 684BA0F0
+P 5650 2200
+F 0 "U1" H 5700 2300 30 0000 C CNN
+F 1 "PORT" H 5650 2200 30 0000 C CNN
+F 2 "" H 5650 2200 60 0000 C CNN
+F 3 "" H 5650 2200 60 0000 C CNN
+ 11 5650 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684BA2EB
+P 3200 800
+F 0 "U1" H 3250 900 30 0000 C CNN
+F 1 "PORT" H 3200 800 30 0000 C CNN
+F 2 "" H 3200 800 60 0000 C CNN
+F 3 "" H 3200 800 60 0000 C CNN
+ 5 3200 800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684BA392
+P 3300 1950
+F 0 "U1" H 3350 2050 30 0000 C CNN
+F 1 "PORT" H 3300 1950 30 0000 C CNN
+F 2 "" H 3300 1950 60 0000 C CNN
+F 3 "" H 3300 1950 60 0000 C CNN
+ 6 3300 1950
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684BA46C
+P 850 1500
+F 0 "U1" H 900 1600 30 0000 C CNN
+F 1 "PORT" H 850 1500 30 0000 C CNN
+F 2 "" H 850 1500 60 0000 C CNN
+F 3 "" H 850 1500 60 0000 C CNN
+ 3 850 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684BA757
+P 750 3100
+F 0 "U1" H 800 3200 30 0000 C CNN
+F 1 "PORT" H 750 3100 30 0000 C CNN
+F 2 "" H 750 3100 60 0000 C CNN
+F 3 "" H 750 3100 60 0000 C CNN
+ 1 750 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684BA82C
+P 800 4550
+F 0 "U1" H 850 4650 30 0000 C CNN
+F 1 "PORT" H 800 4550 30 0000 C CNN
+F 2 "" H 800 4550 60 0000 C CNN
+F 3 "" H 800 4550 60 0000 C CNN
+ 2 800 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684BA923
+P 900 6150
+F 0 "U1" H 950 6250 30 0000 C CNN
+F 1 "PORT" H 900 6150 30 0000 C CNN
+F 2 "" H 900 6150 60 0000 C CNN
+F 3 "" H 900 6150 60 0000 C CNN
+ 4 900 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684BA9CD
+P 3950 6150
+F 0 "U1" H 4000 6250 30 0000 C CNN
+F 1 "PORT" H 3950 6150 30 0000 C CNN
+F 2 "" H 3950 6150 60 0000 C CNN
+F 3 "" H 3950 6150 60 0000 C CNN
+ 10 3950 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684BAAB0
+P 3750 4550
+F 0 "U1" H 3800 4650 30 0000 C CNN
+F 1 "PORT" H 3750 4550 30 0000 C CNN
+F 2 "" H 3750 4550 60 0000 C CNN
+F 3 "" H 3750 4550 60 0000 C CNN
+ 9 3750 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 684BAB6F
+P 3600 3100
+F 0 "U1" H 3650 3200 30 0000 C CNN
+F 1 "PORT" H 3600 3100 30 0000 C CNN
+F 2 "" H 3600 3100 60 0000 C CNN
+F 3 "" H 3600 3100 60 0000 C CNN
+ 8 3600 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684BAC3A
+P 3500 1500
+F 0 "U1" H 3550 1600 30 0000 C CNN
+F 1 "PORT" H 3500 1500 30 0000 C CNN
+F 2 "" H 3500 1500 60 0000 C CNN
+F 3 "" H 3500 1500 60 0000 C CNN
+ 7 3500 1500
+ 1 0 0 -1
+$EndComp
+Connection ~ 6200 1400
+Wire Wire Line
+ 5900 2200 6000 2200
+Connection ~ 6000 2200
+Wire Wire Line
+ 3750 1500 3800 1500
+Wire Wire Line
+ 3850 3100 3900 3100
+Wire Wire Line
+ 4000 4550 4100 4550
+Wire Wire Line
+ 4200 6150 4300 6150
+Wire Wire Line
+ 1150 6150 1350 6150
+Wire Wire Line
+ 1050 4550 1250 4550
+Wire Wire Line
+ 1000 3100 1100 3100
+Wire Wire Line
+ 1100 1500 1250 1500
+Wire Wire Line
+ 7550 2500 6400 2500
+Wire Wire Line
+ 6400 2500 6400 2900
+Wire Wire Line
+ 6400 2900 2800 2900
+Wire Wire Line
+ 2800 2900 2800 3300
+Wire Wire Line
+ 2800 3300 2650 3300
+Wire Wire Line
+ 7550 2750 4850 2750
+Wire Wire Line
+ 4850 2750 4850 2400
+Wire Wire Line
+ 4850 2400 2900 2400
+Wire Wire Line
+ 2900 2400 2900 1700
+Wire Wire Line
+ 2900 1700 2800 1700
+Wire Wire Line
+ 2800 4750 3550 4750
+Wire Wire Line
+ 3550 4750 3550 3650
+Wire Wire Line
+ 3550 3650 6550 3650
+Wire Wire Line
+ 6550 3650 6550 3000
+Wire Wire Line
+ 6550 3000 7550 3000
+Wire Wire Line
+ 2900 6350 3600 6350
+Wire Wire Line
+ 3600 6350 3600 3700
+Wire Wire Line
+ 3600 3700 6650 3700
+Wire Wire Line
+ 6650 3700 6650 3250
+Wire Wire Line
+ 6650 3250 7550 3250
+Wire Wire Line
+ 7550 3550 6700 3550
+Wire Wire Line
+ 6700 3550 6700 1700
+Wire Wire Line
+ 6700 1700 5350 1700
+Wire Wire Line
+ 7550 3800 6850 3800
+Wire Wire Line
+ 6850 3800 6850 3300
+Wire Wire Line
+ 6850 3300 5450 3300
+Wire Wire Line
+ 5650 4750 6450 4750
+Wire Wire Line
+ 6450 4750 6450 4050
+Wire Wire Line
+ 6450 4050 7550 4050
+Wire Wire Line
+ 5850 6350 6650 6350
+Wire Wire Line
+ 6650 6350 6650 4300
+Wire Wire Line
+ 6650 4300 7550 4300
+Wire Wire Line
+ 8450 4800 8450 5500
+Wire Wire Line
+ 8450 5500 3450 5500
+Connection ~ 3450 5500
+Wire Wire Line
+ 3450 900 8450 900
+Wire Wire Line
+ 8450 900 8450 2000
+Connection ~ 3450 900
+$Comp
+L PORT U1
+U 13 1 684B9841
+P 9900 2550
+F 0 "U1" H 9950 2650 30 0000 C CNN
+F 1 "PORT" H 9900 2550 30 0000 C CNN
+F 2 "" H 9900 2550 60 0000 C CNN
+F 3 "" H 9900 2550 60 0000 C CNN
+ 13 9900 2550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 684B989E
+P 9900 2850
+F 0 "U1" H 9950 2950 30 0000 C CNN
+F 1 "PORT" H 9900 2850 30 0000 C CNN
+F 2 "" H 9900 2850 60 0000 C CNN
+F 3 "" H 9900 2850 60 0000 C CNN
+ 14 9900 2850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 684B9931
+P 9900 3150
+F 0 "U1" H 9950 3250 30 0000 C CNN
+F 1 "PORT" H 9900 3150 30 0000 C CNN
+F 2 "" H 9900 3150 60 0000 C CNN
+F 3 "" H 9900 3150 60 0000 C CNN
+ 15 9900 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 684B99A6
+P 9900 3400
+F 0 "U1" H 9950 3500 30 0000 C CNN
+F 1 "PORT" H 9900 3400 30 0000 C CNN
+F 2 "" H 9900 3400 60 0000 C CNN
+F 3 "" H 9900 3400 60 0000 C CNN
+ 16 9900 3400
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 684B9A1F
+P 9900 3700
+F 0 "U1" H 9950 3800 30 0000 C CNN
+F 1 "PORT" H 9900 3700 30 0000 C CNN
+F 2 "" H 9900 3700 60 0000 C CNN
+F 3 "" H 9900 3700 60 0000 C CNN
+ 17 9900 3700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 684B9B14
+P 9900 4000
+F 0 "U1" H 9950 4100 30 0000 C CNN
+F 1 "PORT" H 9900 4000 30 0000 C CNN
+F 2 "" H 9900 4000 60 0000 C CNN
+F 3 "" H 9900 4000 60 0000 C CNN
+ 18 9900 4000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 19 1 684B9B8D
+P 9900 4300
+F 0 "U1" H 9950 4400 30 0000 C CNN
+F 1 "PORT" H 9900 4300 30 0000 C CNN
+F 2 "" H 9900 4300 60 0000 C CNN
+F 3 "" H 9900 4300 60 0000 C CNN
+ 19 9900 4300
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9350 2550 9650 2550
+Wire Wire Line
+ 9350 2850 9650 2850
+Wire Wire Line
+ 9350 3150 9650 3150
+Wire Wire Line
+ 9350 3400 9650 3400
+Wire Wire Line
+ 9350 3700 9650 3700
+Wire Wire Line
+ 9350 4000 9650 4000
+Wire Wire Line
+ 9350 4300 9650 4300
+$Comp
+L SKY130mode scmode1
+U 1 1 684BA49C
+P 10150 1300
+F 0 "scmode1" H 10150 1450 98 0000 C CNB
+F 1 "SKY130mode" H 10150 1200 118 0000 C CNB
+F 2 "" H 10150 1450 60 0001 C CNN
+F 3 "" H 10150 1450 60 0001 C CNN
+ 1 10150 1300
+ 1 0 0 -1
+$EndComp
+NoConn ~ 1250 1850
+NoConn ~ 3800 1850
+NoConn ~ 1100 3450
+NoConn ~ 3900 3450
+NoConn ~ 1250 4900
+NoConn ~ 4100 4900
+NoConn ~ 1350 6500
+NoConn ~ 4300 6500
+NoConn ~ 17800 2250
+$Comp
+L D_Latch X2
+U 1 1 684CF9C0
+P 2100 1700
+F 0 "X2" H 2200 1600 60 0000 C CNN
+F 1 "D_Latch" H 2200 1750 60 0000 C CNN
+F 2 "" H 2100 1700 60 0001 C CNN
+F 3 "" H 2100 1700 60 0001 C CNN
+ 1 2100 1700
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X1
+U 1 1 684CFAF2
+P 1950 3300
+F 0 "X1" H 2050 3200 60 0000 C CNN
+F 1 "D_Latch" H 2050 3350 60 0000 C CNN
+F 2 "" H 1950 3300 60 0001 C CNN
+F 3 "" H 1950 3300 60 0001 C CNN
+ 1 1950 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X3
+U 1 1 684D09F6
+P 2100 4750
+F 0 "X3" H 2200 4650 60 0000 C CNN
+F 1 "D_Latch" H 2200 4800 60 0000 C CNN
+F 2 "" H 2100 4750 60 0001 C CNN
+F 3 "" H 2100 4750 60 0001 C CNN
+ 1 2100 4750
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X4
+U 1 1 684D0B3B
+P 2200 6350
+F 0 "X4" H 2300 6250 60 0000 C CNN
+F 1 "D_Latch" H 2300 6400 60 0000 C CNN
+F 2 "" H 2200 6350 60 0001 C CNN
+F 3 "" H 2200 6350 60 0001 C CNN
+ 1 2200 6350
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X8
+U 1 1 684D0C60
+P 5150 6350
+F 0 "X8" H 5250 6250 60 0000 C CNN
+F 1 "D_Latch" H 5250 6400 60 0000 C CNN
+F 2 "" H 5150 6350 60 0001 C CNN
+F 3 "" H 5150 6350 60 0001 C CNN
+ 1 5150 6350
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X7
+U 1 1 684D0D81
+P 4950 4750
+F 0 "X7" H 5050 4650 60 0000 C CNN
+F 1 "D_Latch" H 5050 4800 60 0000 C CNN
+F 2 "" H 4950 4750 60 0001 C CNN
+F 3 "" H 4950 4750 60 0001 C CNN
+ 1 4950 4750
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X6
+U 1 1 684D0EF8
+P 4750 3300
+F 0 "X6" H 4850 3200 60 0000 C CNN
+F 1 "D_Latch" H 4850 3350 60 0000 C CNN
+F 2 "" H 4750 3300 60 0001 C CNN
+F 3 "" H 4750 3300 60 0001 C CNN
+ 1 4750 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_Latch X5
+U 1 1 684D103D
+P 4650 1700
+F 0 "X5" H 4750 1600 60 0000 C CNN
+F 1 "D_Latch" H 4750 1750 60 0000 C CNN
+F 2 "" H 4650 1700 60 0001 C CNN
+F 3 "" H 4650 1700 60 0001 C CNN
+ 1 4650 1700
+ -1 0 0 -1
+$EndComp
+$Comp
+L Decoder_38 X9
+U 1 1 684D1335
+P 8450 3400
+F 0 "X9" H 8450 3200 60 0000 C CNN
+F 1 "Decoder_38" H 8450 3400 60 0000 C CNN
+F 2 "" H 8450 3400 60 0001 C CNN
+F 3 "" H 8450 3400 60 0001 C CNN
+ 1 8450 3400
+ -1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.sub b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.sub
new file mode 100644
index 000000000..8175b2236
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage.sub
@@ -0,0 +1,20 @@
+* Subcircuit Decoder_38_Address_Latch_storage
+.subckt Decoder_38_Address_Latch_storage net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ /vdd /gnd net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ /d net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/decoder_38_address_latch_storage/decoder_38_address_latch_storage.cir
+.include D_latch.sub
+.include Decoder_38.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+* s c m o d e
+x2 /d net-_x2-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad3_ ? D_latch
+x1 /d net-_x1-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad1_ ? D_latch
+x3 /d net-_x3-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad2_ ? D_latch
+x4 /d net-_x4-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad4_ ? D_latch
+x8 /d net-_x8-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad10_ ? D_latch
+x7 /d net-_x7-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad9_ ? D_latch
+x6 /d net-_x6-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad8_ ? D_latch
+x5 /d net-_x5-pad2_ net-_u1-pad11_ /gnd /vdd net-_u1-pad7_ ? D_latch
+x9 net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad16_ /vdd /vdd net-_x7-pad2_ net-_x5-pad2_ net-_x1-pad2_ net-_x8-pad2_ net-_x6-pad2_ net-_x3-pad2_ net-_x2-pad2_ net-_x4-pad2_ Decoder_38
+* Control Statements
+
+.ends Decoder_38_Address_Latch_storage
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage_Previous_Values.xml
new file mode 100644
index 000000000..f954fbc7b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Address_Latch_storage_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_latch/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_latch/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_latch/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_latch/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_latch/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_latch/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_latch/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/D_latch/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Decoder_38truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC259/Decoder_38_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Previous_Values.xml
new file mode 100644
index 000000000..b91e445ab
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Decoder_38_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_2-cache.lib b/library/SubcircuitLibrary/SN74HC259/NAND_2-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_2-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_2.bak b/library/SubcircuitLibrary/SN74HC259/NAND_2.bak
new file mode 100644
index 000000000..ad9819396
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_2.bak
@@ -0,0 +1,221 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684AF0E9
+P 4750 2050
+F 0 "SC2" H 4800 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5050 2137 50 0000 R CNN
+F 2 "" H 4750 550 50 0001 C CNN
+F 3 "" H 4750 2050 50 0001 C CNN
+ 1 4750 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF14C
+P 5150 2750
+F 0 "SC3" H 5200 3050 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 2837 50 0000 R CNN
+F 2 "" H 5150 1250 50 0001 C CNN
+F 3 "" H 5150 2750 50 0001 C CNN
+ 1 5150 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF1CF
+P 4200 3600
+F 0 "SC1" H 4250 3900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4500 3687 50 0000 R CNN
+F 2 "" H 4200 2100 50 0001 C CNN
+F 3 "" H 4200 3600 50 0001 C CNN
+ 1 4200 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684AF20C
+P 5550 3600
+F 0 "SC4" H 5600 3900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5850 3687 50 0000 R CNN
+F 2 "" H 5550 2100 50 0001 C CNN
+F 3 "" H 5550 3600 50 0001 C CNN
+ 1 5550 3600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF271
+P 4650 1550
+F 0 "U1" H 4700 1650 30 0000 C CNN
+F 1 "PORT" H 4650 1550 30 0000 C CNN
+F 2 "" H 4650 1550 60 0000 C CNN
+F 3 "" H 4650 1550 60 0000 C CNN
+ 3 4650 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF336
+P 3550 2650
+F 0 "U1" H 3600 2750 30 0000 C CNN
+F 1 "PORT" H 3550 2650 30 0000 C CNN
+F 2 "" H 3550 2650 60 0000 C CNN
+F 3 "" H 3550 2650 60 0000 C CNN
+ 1 3550 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AF413
+P 6200 2750
+F 0 "U1" H 6250 2850 30 0000 C CNN
+F 1 "PORT" H 6200 2750 30 0000 C CNN
+F 2 "" H 6200 2750 60 0000 C CNN
+F 3 "" H 6200 2750 60 0000 C CNN
+ 4 6200 2750
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF82C
+P 6200 3150
+F 0 "U1" H 6250 3250 30 0000 C CNN
+F 1 "PORT" H 6200 3150 30 0000 C CNN
+F 2 "" H 6200 3150 60 0000 C CNN
+F 3 "" H 6200 3150 60 0000 C CNN
+ 5 6200 3150
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF895
+P 4550 4050
+F 0 "U1" H 4600 4150 30 0000 C CNN
+F 1 "PORT" H 4550 4050 30 0000 C CNN
+F 2 "" H 4550 4050 60 0000 C CNN
+F 3 "" H 4550 4050 60 0000 C CNN
+ 2 4550 4050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 3900 5350 3900
+Wire Wire Line
+ 4800 4050 4800 3900
+Connection ~ 4800 3900
+Wire Wire Line
+ 4300 3600 4450 3600
+Wire Wire Line
+ 4450 3600 4450 3900
+Connection ~ 4450 3900
+Wire Wire Line
+ 5450 3600 5300 3600
+Wire Wire Line
+ 5300 3600 5300 3900
+Connection ~ 5300 3900
+Wire Wire Line
+ 4400 3300 5350 3300
+Wire Wire Line
+ 4950 3050 4950 3300
+Connection ~ 4950 3300
+Wire Wire Line
+ 5950 3150 4950 3150
+Connection ~ 4950 3150
+Wire Wire Line
+ 5450 2750 5950 2750
+Wire Wire Line
+ 5850 2750 5850 3600
+Wire Wire Line
+ 5050 2750 4900 2750
+Wire Wire Line
+ 4900 2750 4900 2400
+Wire Wire Line
+ 4900 2400 4950 2400
+Wire Wire Line
+ 4950 2350 4950 2450
+Connection ~ 4950 2400
+Wire Wire Line
+ 4450 2050 3900 2050
+Wire Wire Line
+ 3900 2050 3900 3600
+Wire Wire Line
+ 3800 2650 3900 2650
+Connection ~ 3900 2650
+Connection ~ 5850 2750
+Wire Wire Line
+ 4850 2050 5000 2050
+Wire Wire Line
+ 5000 2050 5000 1650
+Wire Wire Line
+ 5000 1650 4950 1650
+Wire Wire Line
+ 4950 1550 4950 1750
+Wire Wire Line
+ 4900 1550 4950 1550
+Connection ~ 4950 1650
+$Comp
+L SKY130mode scmode1
+U 1 1 684AFD6B
+P 7350 2150
+F 0 "scmode1" H 7350 2300 98 0000 C CNB
+F 1 "SKY130mode" H 7350 2050 118 0000 C CNB
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2150
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_2.cir b/library/SubcircuitLibrary/SN74HC259/NAND_2.cir
new file mode 100644
index 000000000..1fa1e05e8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_2.cir
@@ -0,0 +1,16 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_2/NAND_2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 09:19:59 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC1-Pad3_ Net-_SC3-Pad2_ Net-_SC4-Pad3_ Net-_SC4-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC4-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ Net-_SC3-Pad2_ PORT
+scmode1 SKY130mode
+SC3 Net-_SC1-Pad1_ Net-_SC3-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__pfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_2.cir.out b/library/SubcircuitLibrary/SN74HC259/NAND_2.cir.out
new file mode 100644
index 000000000..079b2d2c2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_2.cir.out
@@ -0,0 +1,19 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_2/nand_2.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad3_ net-_sc3-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc4-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ net-_sc3-pad2_ port
+* s c m o d e
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_2.pro b/library/SubcircuitLibrary/SN74HC259/NAND_2.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_2.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_2.sch b/library/SubcircuitLibrary/SN74HC259/NAND_2.sch
new file mode 100644
index 000000000..ebef1d4c6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_2.sch
@@ -0,0 +1,222 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:NAND_2-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 684AF0E9
+P 4200 2050
+F 0 "SC2" H 4250 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4500 2137 50 0000 R CNN
+F 2 "" H 4200 550 50 0001 C CNN
+F 3 "" H 4200 2050 50 0001 C CNN
+ 1 4200 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF1CF
+P 4450 2850
+F 0 "SC1" H 4500 3150 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4750 2937 50 0000 R CNN
+F 2 "" H 4450 1350 50 0001 C CNN
+F 3 "" H 4450 2850 50 0001 C CNN
+ 1 4450 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 684AF20C
+P 4850 3550
+F 0 "SC4" H 4900 3850 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5150 3637 50 0000 R CNN
+F 2 "" H 4850 2050 50 0001 C CNN
+F 3 "" H 4850 3550 50 0001 C CNN
+ 1 4850 3550
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF271
+P 4350 1550
+F 0 "U1" H 4400 1650 30 0000 C CNN
+F 1 "PORT" H 4350 1550 30 0000 C CNN
+F 2 "" H 4350 1550 60 0000 C CNN
+F 3 "" H 4350 1550 60 0000 C CNN
+ 3 4350 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF336
+P 3550 2650
+F 0 "U1" H 3600 2750 30 0000 C CNN
+F 1 "PORT" H 3550 2650 30 0000 C CNN
+F 2 "" H 3550 2650 60 0000 C CNN
+F 3 "" H 3550 2650 60 0000 C CNN
+ 1 3550 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AF413
+P 5750 2450
+F 0 "U1" H 5800 2550 30 0000 C CNN
+F 1 "PORT" H 5750 2450 30 0000 C CNN
+F 2 "" H 5750 2450 60 0000 C CNN
+F 3 "" H 5750 2450 60 0000 C CNN
+ 4 5750 2450
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF82C
+P 5750 3300
+F 0 "U1" H 5800 3400 30 0000 C CNN
+F 1 "PORT" H 5750 3300 30 0000 C CNN
+F 2 "" H 5750 3300 60 0000 C CNN
+F 3 "" H 5750 3300 60 0000 C CNN
+ 5 5750 3300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF895
+P 4400 4000
+F 0 "U1" H 4450 4100 30 0000 C CNN
+F 1 "PORT" H 4400 4000 30 0000 C CNN
+F 2 "" H 4400 4000 60 0000 C CNN
+F 3 "" H 4400 4000 60 0000 C CNN
+ 2 4400 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684AFD6B
+P 7350 2150
+F 0 "scmode1" H 7350 2300 98 0000 C CNB
+F 1 "SKY130mode" H 7350 2050 118 0000 C CNB
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684CF41D
+P 5000 2050
+F 0 "SC3" H 5050 2350 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5300 2137 50 0000 R CNN
+F 2 "" H 5000 550 50 0001 C CNN
+F 3 "" H 5000 2050 50 0001 C CNN
+ 1 5000 2050
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 1750 4800 1750
+Wire Wire Line
+ 4600 1550 4600 1750
+Connection ~ 4600 1750
+Wire Wire Line
+ 4300 2050 4450 2050
+Wire Wire Line
+ 4450 2050 4450 1750
+Connection ~ 4450 1750
+Wire Wire Line
+ 4900 2050 4750 2050
+Wire Wire Line
+ 4750 2050 4750 1750
+Connection ~ 4750 1750
+Wire Wire Line
+ 4400 2350 4800 2350
+Wire Wire Line
+ 4650 2550 4650 2350
+Connection ~ 4650 2350
+Wire Wire Line
+ 5500 2450 4650 2450
+Connection ~ 4650 2450
+Wire Wire Line
+ 3900 2050 3900 2850
+Wire Wire Line
+ 3900 2850 4150 2850
+Wire Wire Line
+ 3800 2650 3900 2650
+Connection ~ 3900 2650
+Wire Wire Line
+ 5300 2050 5300 3550
+Wire Wire Line
+ 5300 3550 5150 3550
+Wire Wire Line
+ 5500 3300 5300 3300
+Connection ~ 5300 3300
+Wire Wire Line
+ 4550 2850 4700 2850
+Wire Wire Line
+ 4700 2850 4700 3200
+Wire Wire Line
+ 4700 3200 4650 3200
+Wire Wire Line
+ 4650 3150 4650 3250
+Connection ~ 4650 3200
+Wire Wire Line
+ 4650 3850 4650 4000
+Wire Wire Line
+ 4750 3550 4600 3550
+Wire Wire Line
+ 4600 3550 4600 3900
+Wire Wire Line
+ 4600 3900 4650 3900
+Connection ~ 4650 3900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_2.sub b/library/SubcircuitLibrary/SN74HC259/NAND_2.sub
new file mode 100644
index 000000000..47d0bd150
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_2.sub
@@ -0,0 +1,13 @@
+* Subcircuit NAND_2
+.subckt NAND_2 net-_sc1-pad2_ net-_sc4-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ net-_sc3-pad2_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_2/nand_2.cir
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc1-pad3_ net-_sc3-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+xsc3 net-_sc1-pad1_ net-_sc3-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+* Control Statements
+
+.ends NAND_2
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_2_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC259/NAND_2_Previous_Values.xml
new file mode 100644
index 000000000..066d43a60
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_2_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_3-cache.lib b/library/SubcircuitLibrary/SN74HC259/NAND_3-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_3-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_3.bak b/library/SubcircuitLibrary/SN74HC259/NAND_3.bak
new file mode 100644
index 000000000..d9890c5d1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_3.bak
@@ -0,0 +1,287 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF360
+P 5550 2300
+F 0 "SC3" H 5600 2600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5850 2387 50 0000 R CNN
+F 2 "" H 5550 800 50 0001 C CNN
+F 3 "" H 5550 2300 50 0001 C CNN
+ 1 5550 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 684AF39D
+P 5550 3100
+F 0 "SC4" H 5600 3400 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5850 3187 50 0000 R CNN
+F 2 "" H 5550 1600 50 0001 C CNN
+F 3 "" H 5550 3100 50 0001 C CNN
+ 1 5550 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC5
+U 1 1 684AF420
+P 5950 3800
+F 0 "SC5" H 6000 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6250 3887 50 0000 R CNN
+F 2 "" H 5950 2300 50 0001 C CNN
+F 3 "" H 5950 3800 50 0001 C CNN
+ 1 5950 3800
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF50C
+P 4450 4700
+F 0 "SC1" H 4500 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4750 4787 50 0000 R CNN
+F 2 "" H 4450 3200 50 0001 C CNN
+F 3 "" H 4450 4700 50 0001 C CNN
+ 1 4450 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684AF577
+P 5500 4700
+F 0 "SC2" H 5550 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5800 4787 50 0000 R CNN
+F 2 "" H 5500 3200 50 0001 C CNN
+F 3 "" H 5500 4700 50 0001 C CNN
+ 1 5500 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 684AF5EC
+P 6450 4700
+F 0 "SC6" H 6500 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6750 4787 50 0000 R CNN
+F 2 "" H 6450 3200 50 0001 C CNN
+F 3 "" H 6450 4700 50 0001 C CNN
+ 1 6450 4700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF63F
+P 3700 4000
+F 0 "U1" H 3750 4100 30 0000 C CNN
+F 1 "PORT" H 3700 4000 30 0000 C CNN
+F 2 "" H 3700 4000 60 0000 C CNN
+F 3 "" H 3700 4000 60 0000 C CNN
+ 1 3700 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF6CC
+P 4850 3850
+F 0 "U1" H 4900 3950 30 0000 C CNN
+F 1 "PORT" H 4850 3850 30 0000 C CNN
+F 2 "" H 4850 3850 60 0000 C CNN
+F 3 "" H 4850 3850 60 0000 C CNN
+ 2 4850 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF829
+P 7050 3800
+F 0 "U1" H 7100 3900 30 0000 C CNN
+F 1 "PORT" H 7050 3800 30 0000 C CNN
+F 2 "" H 7050 3800 60 0000 C CNN
+F 3 "" H 7050 3800 60 0000 C CNN
+ 5 7050 3800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684AF94D
+P 7150 4200
+F 0 "U1" H 7200 4300 30 0000 C CNN
+F 1 "PORT" H 7150 4200 30 0000 C CNN
+F 2 "" H 7150 4200 60 0000 C CNN
+F 3 "" H 7150 4200 60 0000 C CNN
+ 6 7150 4200
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF9FE
+P 5100 5200
+F 0 "U1" H 5150 5300 30 0000 C CNN
+F 1 "PORT" H 5100 5200 30 0000 C CNN
+F 2 "" H 5100 5200 60 0000 C CNN
+F 3 "" H 5100 5200 60 0000 C CNN
+ 3 5100 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AFAE6
+P 5500 1750
+F 0 "U1" H 5550 1850 30 0000 C CNN
+F 1 "PORT" H 5500 1750 30 0000 C CNN
+F 2 "" H 5500 1750 60 0000 C CNN
+F 3 "" H 5500 1750 60 0000 C CNN
+ 4 5500 1750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5650 2300 5800 2300
+Wire Wire Line
+ 5800 2300 5800 1950
+Wire Wire Line
+ 5800 1950 5750 1950
+Wire Wire Line
+ 5750 1750 5750 2000
+Connection ~ 5750 1950
+Wire Wire Line
+ 5750 2600 5750 2800
+Wire Wire Line
+ 5650 3100 5800 3100
+Wire Wire Line
+ 5800 3100 5800 2750
+Wire Wire Line
+ 5800 2750 5750 2750
+Connection ~ 5750 2750
+Wire Wire Line
+ 5750 3500 5750 3400
+Wire Wire Line
+ 5850 3800 5700 3800
+Wire Wire Line
+ 5700 3800 5700 3450
+Wire Wire Line
+ 5700 3450 5750 3450
+Connection ~ 5750 3450
+Wire Wire Line
+ 4650 4400 4650 4300
+Wire Wire Line
+ 4650 4300 6250 4300
+Wire Wire Line
+ 6250 4300 6250 4400
+Wire Wire Line
+ 5700 4400 5700 4300
+Connection ~ 5700 4300
+Wire Wire Line
+ 5750 4100 5750 4300
+Connection ~ 5750 4300
+Wire Wire Line
+ 4650 5000 4650 5050
+Wire Wire Line
+ 4650 5050 6250 5050
+Wire Wire Line
+ 6250 5050 6250 5000
+Wire Wire Line
+ 5700 5000 5700 5050
+Connection ~ 5700 5050
+Wire Wire Line
+ 5350 5200 5350 5050
+Connection ~ 5350 5050
+Wire Wire Line
+ 4550 4700 4700 4700
+Wire Wire Line
+ 4700 4700 4700 5050
+Connection ~ 4700 5050
+Wire Wire Line
+ 5600 4700 5750 4700
+Wire Wire Line
+ 5750 4700 5750 5050
+Connection ~ 5750 5050
+Wire Wire Line
+ 6350 4700 6200 4700
+Wire Wire Line
+ 6200 4700 6200 5050
+Connection ~ 6200 5050
+Wire Wire Line
+ 4150 2300 4150 4700
+Wire Wire Line
+ 3950 4000 4150 4000
+Connection ~ 4150 4000
+Wire Wire Line
+ 5250 2300 4150 2300
+Wire Wire Line
+ 5250 3100 5200 3100
+Wire Wire Line
+ 5200 3100 5200 4700
+Wire Wire Line
+ 6250 3800 6800 3800
+Wire Wire Line
+ 6750 3800 6750 4700
+Connection ~ 6750 3800
+Wire Wire Line
+ 5100 3850 5200 3850
+Connection ~ 5200 3850
+Wire Wire Line
+ 6900 4200 5750 4200
+Connection ~ 5750 4200
+$Comp
+L SKY130mode scmode1
+U 1 1 684B00C1
+P 8250 2900
+F 0 "scmode1" H 8250 3050 98 0000 C CNB
+F 1 "SKY130mode" H 8250 2800 118 0000 C CNB
+F 2 "" H 8250 3050 60 0001 C CNN
+F 3 "" H 8250 3050 60 0001 C CNN
+ 1 8250 2900
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_3.cir b/library/SubcircuitLibrary/SN74HC259/NAND_3.cir
new file mode 100644
index 000000000..e4f46e26d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_3.cir
@@ -0,0 +1,18 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/NAND_3/NAND_3.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 09:30:02 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC3 Net-_SC2-Pad1_ Net-_SC2-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC4 Net-_SC2-Pad1_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC5 Net-_SC2-Pad1_ Net-_SC5-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__pfet_01v8
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC6 Net-_SC1-Pad3_ Net-_SC5-Pad2_ Net-_SC6-Pad3_ Net-_SC6-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC2-Pad2_ Net-_SC1-Pad2_ Net-_SC6-Pad3_ Net-_SC3-Pad3_ Net-_SC2-Pad1_ Net-_SC5-Pad2_ PORT
+scmode1 SKY130mode
+SC2 Net-_SC2-Pad1_ Net-_SC2-Pad2_ Net-_SC1-Pad1_ Net-_SC1-Pad1_ sky130_fd_pr__nfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_3.cir.out b/library/SubcircuitLibrary/SN74HC259/NAND_3.cir.out
new file mode 100644
index 000000000..b08a2163a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_3.cir.out
@@ -0,0 +1,21 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_3/nand_3.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc3 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc2-pad1_ net-_sc5-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc1-pad3_ net-_sc5-pad2_ net-_sc6-pad3_ net-_sc6-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc2-pad2_ net-_sc1-pad2_ net-_sc6-pad3_ net-_sc3-pad3_ net-_sc2-pad1_ net-_sc5-pad2_ port
+* s c m o d e
+xsc2 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_3.pro b/library/SubcircuitLibrary/SN74HC259/NAND_3.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_3.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_3.sch b/library/SubcircuitLibrary/SN74HC259/NAND_3.sch
new file mode 100644
index 000000000..eb96f8eac
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_3.sch
@@ -0,0 +1,289 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:NAND_3-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC3
+U 1 1 684AF360
+P 4200 2350
+F 0 "SC3" H 4250 2650 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4500 2437 50 0000 R CNN
+F 2 "" H 4200 850 50 0001 C CNN
+F 3 "" H 4200 2350 50 0001 C CNN
+ 1 4200 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 684AF39D
+P 5250 2350
+F 0 "SC4" H 5300 2650 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5550 2437 50 0000 R CNN
+F 2 "" H 5250 850 50 0001 C CNN
+F 3 "" H 5250 2350 50 0001 C CNN
+ 1 5250 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC5
+U 1 1 684AF420
+P 6100 2350
+F 0 "SC5" H 6150 2650 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6400 2437 50 0000 R CNN
+F 2 "" H 6100 850 50 0001 C CNN
+F 3 "" H 6100 2350 50 0001 C CNN
+ 1 6100 2350
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 684AF50C
+P 5250 4000
+F 0 "SC1" H 5300 4300 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5550 4087 50 0000 R CNN
+F 2 "" H 5250 2500 50 0001 C CNN
+F 3 "" H 5250 4000 50 0001 C CNN
+ 1 5250 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 684AF5EC
+P 5650 4700
+F 0 "SC6" H 5700 5000 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5950 4787 50 0000 R CNN
+F 2 "" H 5650 3200 50 0001 C CNN
+F 3 "" H 5650 4700 50 0001 C CNN
+ 1 5650 4700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AF63F
+P 3450 2350
+F 0 "U1" H 3500 2450 30 0000 C CNN
+F 1 "PORT" H 3450 2350 30 0000 C CNN
+F 2 "" H 3450 2350 60 0000 C CNN
+F 3 "" H 3450 2350 60 0000 C CNN
+ 1 3450 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AF6CC
+P 4500 4000
+F 0 "U1" H 4550 4100 30 0000 C CNN
+F 1 "PORT" H 4500 4000 30 0000 C CNN
+F 2 "" H 4500 4000 60 0000 C CNN
+F 3 "" H 4500 4000 60 0000 C CNN
+ 2 4500 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AF829
+P 6300 2800
+F 0 "U1" H 6350 2900 30 0000 C CNN
+F 1 "PORT" H 6300 2800 30 0000 C CNN
+F 2 "" H 6300 2800 60 0000 C CNN
+F 3 "" H 6300 2800 60 0000 C CNN
+ 5 6300 2800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684AF94D
+P 6850 2350
+F 0 "U1" H 6900 2450 30 0000 C CNN
+F 1 "PORT" H 6850 2350 30 0000 C CNN
+F 2 "" H 6850 2350 60 0000 C CNN
+F 3 "" H 6850 2350 60 0000 C CNN
+ 6 6850 2350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AF9FE
+P 5100 5200
+F 0 "U1" H 5150 5300 30 0000 C CNN
+F 1 "PORT" H 5100 5200 30 0000 C CNN
+F 2 "" H 5100 5200 60 0000 C CNN
+F 3 "" H 5100 5200 60 0000 C CNN
+ 3 5100 5200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AFAE6
+P 5500 1750
+F 0 "U1" H 5550 1850 30 0000 C CNN
+F 1 "PORT" H 5500 1750 30 0000 C CNN
+F 2 "" H 5500 1750 60 0000 C CNN
+F 3 "" H 5500 1750 60 0000 C CNN
+ 4 5500 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B00C1
+P 8250 2900
+F 0 "scmode1" H 8250 3050 98 0000 C CNB
+F 1 "SKY130mode" H 8250 2800 118 0000 C CNB
+F 2 "" H 8250 3050 60 0001 C CNN
+F 3 "" H 8250 3050 60 0001 C CNN
+ 1 8250 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684AF577
+P 5250 3250
+F 0 "SC2" H 5300 3550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5550 3337 50 0000 R CNN
+F 2 "" H 5250 1750 50 0001 C CNN
+F 3 "" H 5250 3250 50 0001 C CNN
+ 1 5250 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4400 2050 4400 2000
+Wire Wire Line
+ 4400 2000 5900 2000
+Wire Wire Line
+ 5900 2000 5900 2050
+Wire Wire Line
+ 5450 2050 5450 2000
+Connection ~ 5450 2000
+Wire Wire Line
+ 5750 1750 5750 2000
+Connection ~ 5750 2000
+Wire Wire Line
+ 4300 2350 4450 2350
+Wire Wire Line
+ 4450 2350 4450 2000
+Connection ~ 4450 2000
+Wire Wire Line
+ 5350 2350 5500 2350
+Wire Wire Line
+ 5500 2350 5500 2000
+Connection ~ 5500 2000
+Wire Wire Line
+ 6000 2350 5850 2350
+Wire Wire Line
+ 5850 2350 5850 2000
+Connection ~ 5850 2000
+Wire Wire Line
+ 4400 2650 4400 2700
+Wire Wire Line
+ 4400 2700 5900 2700
+Wire Wire Line
+ 5900 2700 5900 2650
+Wire Wire Line
+ 5450 2650 5450 2950
+Connection ~ 5450 2700
+Wire Wire Line
+ 6050 2800 5450 2800
+Connection ~ 5450 2800
+Wire Wire Line
+ 3700 2350 3900 2350
+Wire Wire Line
+ 3850 2350 3850 3250
+Wire Wire Line
+ 3850 3250 4950 3250
+Wire Wire Line
+ 4950 2350 4800 2350
+Wire Wire Line
+ 4800 2350 4800 4000
+Wire Wire Line
+ 4750 4000 4950 4000
+Wire Wire Line
+ 5350 3250 5500 3250
+Wire Wire Line
+ 5500 3250 5500 3600
+Wire Wire Line
+ 5500 3600 5450 3600
+Wire Wire Line
+ 5450 3550 5450 3700
+Connection ~ 5450 3600
+Wire Wire Line
+ 6400 2350 6600 2350
+Wire Wire Line
+ 6450 2350 6450 4700
+Wire Wire Line
+ 6450 4700 5950 4700
+Connection ~ 6450 2350
+Wire Wire Line
+ 5350 4000 5500 4000
+Wire Wire Line
+ 5500 4000 5500 4350
+Wire Wire Line
+ 5500 4350 5450 4350
+Wire Wire Line
+ 5450 4300 5450 4400
+Connection ~ 5450 4350
+Connection ~ 4800 4000
+Wire Wire Line
+ 5450 5000 5450 5200
+Wire Wire Line
+ 5450 5200 5350 5200
+Wire Wire Line
+ 5550 4700 5400 4700
+Wire Wire Line
+ 5400 4700 5400 5050
+Wire Wire Line
+ 5400 5050 5450 5050
+Connection ~ 5450 5050
+Connection ~ 3850 2350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_3.sub b/library/SubcircuitLibrary/SN74HC259/NAND_3.sub
new file mode 100644
index 000000000..3b4f4b3ff
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_3.sub
@@ -0,0 +1,15 @@
+* Subcircuit NAND_3
+.subckt NAND_3 net-_sc2-pad2_ net-_sc1-pad2_ net-_sc6-pad3_ net-_sc3-pad3_ net-_sc2-pad1_ net-_sc5-pad2_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/nand_3/nand_3.cir
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc3 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc4 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc2-pad1_ net-_sc5-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc1-pad3_ net-_sc5-pad2_ net-_sc6-pad3_ net-_sc6-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+xsc2 net-_sc2-pad1_ net-_sc2-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends NAND_3
diff --git a/library/SubcircuitLibrary/SN74HC259/NAND_3_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC259/NAND_3_Previous_Values.xml
new file mode 100644
index 000000000..c0934485a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/NAND_3_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC259/SN74HC259-cache.lib b/library/SubcircuitLibrary/SN74HC259/SN74HC259-cache.lib
new file mode 100644
index 000000000..aeffc2259
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/SN74HC259-cache.lib
@@ -0,0 +1,126 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" 100 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -450 250 500 0 N
+P 3 0 1 0 -450 250 -450 -250 500 0 N
+X IN 1 -650 0 200 R 50 50 1 1 I
+X VDD 2 -650 150 200 R 50 50 1 1 I
+X GND 3 -650 -150 200 R 50 50 1 1 I
+X OUT 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Decoder_38_Address_Latch_storage
+#
+DEF Decoder_38_Address_Latch_storage X 0 40 Y Y 1 F N
+F0 "X" 0 -150 60 H V C CNN
+F1 "Decoder_38_Address_Latch_storage" 100 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -900 1150 900 -1250 0 1 0 N
+X Q1 1 1100 1000 200 L 50 50 1 1 O
+X Q3 2 1100 500 200 L 50 50 1 1 O
+X Q2 3 1100 750 200 L 50 50 1 1 O
+X Q4 4 1100 250 200 L 50 50 1 1 O
+X VDD 5 -1100 1000 200 R 50 50 1 1 I
+X GND 6 -1150 -1000 200 R 50 50 1 1 I
+X Q5 7 1100 -200 200 L 50 50 1 1 O
+X Q6 8 1100 -400 200 L 50 50 1 1 O
+X Q7 9 1100 -650 200 L 50 50 1 1 O
+X Q8 10 1100 -950 200 L 50 50 1 1 O
+X RE 11 -1100 -450 200 R 50 50 1 1 I
+X D 12 -1100 -650 200 R 50 50 1 1 I
+X S0_BAR 13 -1100 850 200 R 50 50 1 1 I
+X S1_BAR 14 -1100 700 200 R 50 50 1 1 I
+X S2_BAR 15 -1100 550 200 R 50 50 1 1 I
+X G_BAR 16 -1150 -250 200 R 50 50 1 1 I
+X S0 17 -1100 350 200 R 50 50 1 1 I
+X S1 18 -1100 200 200 R 50 50 1 1 I
+X S2 19 -1100 50 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Schmitt_Trigger
+#
+DEF Schmitt_Trigger X 0 40 Y Y 1 F N
+F0 "X" -400 0 60 H V C CNN
+F1 "Schmitt_Trigger" 50 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+P 2 0 1 0 -650 -150 -700 -150 N
+P 2 0 1 0 -550 150 -450 150 N
+P 2 0 1 0 -450 150 -400 150 N
+P 3 0 1 0 -550 150 -600 -150 -650 -150 N
+P 3 0 1 0 -500 150 -550 -150 -600 -150 N
+P 4 0 1 0 -800 350 900 0 -800 -350 -800 350 N
+X In 1 -1000 0 200 R 50 50 1 1 I
+X Vdd 2 -300 450 200 D 50 50 1 1 I
+X Gnd 3 -300 -450 200 U 50 50 1 1 I
+X Out 4 1100 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/SN74HC259.bak b/library/SubcircuitLibrary/SN74HC259/SN74HC259.bak
new file mode 100644
index 000000000..ea9ed7bf8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/SN74HC259.bak
@@ -0,0 +1,531 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74HC259-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CMOS_INVTR X6
+U 1 1 684B99C4
+P 5350 1700
+F 0 "X6" H 5350 1700 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 1450 60 0000 C CNN
+F 2 "" H 5350 1700 60 0001 C CNN
+F 3 "" H 5350 1700 60 0001 C CNN
+ 1 5350 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X7
+U 1 1 684B9A21
+P 5350 2400
+F 0 "X7" H 5350 2400 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 2150 60 0000 C CNN
+F 2 "" H 5350 2400 60 0001 C CNN
+F 3 "" H 5350 2400 60 0001 C CNN
+ 1 5350 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X8
+U 1 1 684B9A8E
+P 5350 3250
+F 0 "X8" H 5350 3250 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 3000 60 0000 C CNN
+F 2 "" H 5350 3250 60 0001 C CNN
+F 3 "" H 5350 3250 60 0001 C CNN
+ 1 5350 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X9
+U 1 1 684B9B4B
+P 5350 4100
+F 0 "X9" H 5350 4100 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 3850 60 0000 C CNN
+F 2 "" H 5350 4100 60 0001 C CNN
+F 3 "" H 5350 4100 60 0001 C CNN
+ 1 5350 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X10
+U 1 1 684B9D35
+P 5350 4850
+F 0 "X10" H 5350 4850 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 4600 60 0000 C CNN
+F 2 "" H 5350 4850 60 0001 C CNN
+F 3 "" H 5350 4850 60 0001 C CNN
+ 1 5350 4850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6150 1700 7750 1700
+Wire Wire Line
+ 7750 1700 7750 1750
+Wire Wire Line
+ 6150 2400 6150 1900
+Wire Wire Line
+ 6150 1900 7750 1900
+Wire Wire Line
+ 6150 3250 6350 3250
+Wire Wire Line
+ 6350 3250 6350 2050
+Wire Wire Line
+ 6350 2050 7750 2050
+Wire Wire Line
+ 4000 1700 4700 1700
+Wire Wire Line
+ 4350 1700 4350 2100
+Wire Wire Line
+ 4350 2100 7750 2100
+Wire Wire Line
+ 7750 2100 7750 2250
+Connection ~ 4350 1700
+Wire Wire Line
+ 7750 2400 6400 2400
+Wire Wire Line
+ 6400 2400 6400 2700
+Wire Wire Line
+ 6400 2700 4000 2700
+Wire Wire Line
+ 4700 2400 4350 2400
+Wire Wire Line
+ 4350 2400 4350 2700
+Connection ~ 4350 2700
+Wire Wire Line
+ 7750 2550 6450 2550
+Wire Wire Line
+ 6450 2550 6450 2950
+Wire Wire Line
+ 6450 2950 4000 2950
+Wire Wire Line
+ 4700 3250 4350 3250
+Wire Wire Line
+ 4350 3250 4350 2950
+Connection ~ 4350 2950
+Wire Wire Line
+ 6150 4100 6750 4100
+Wire Wire Line
+ 6750 4100 6750 2850
+Wire Wire Line
+ 6750 2850 7700 2850
+Wire Wire Line
+ 6150 4850 6900 4850
+Wire Wire Line
+ 6900 4850 6900 3050
+Wire Wire Line
+ 6900 3050 7750 3050
+Wire Wire Line
+ 4700 1850 4550 1850
+Wire Wire Line
+ 4550 1850 4550 5450
+Wire Wire Line
+ 4550 5000 4700 5000
+Wire Wire Line
+ 4700 1550 4450 1550
+Wire Wire Line
+ 4450 1250 4450 4700
+Wire Wire Line
+ 4450 4700 4700 4700
+Wire Wire Line
+ 3950 4100 4700 4100
+Wire Wire Line
+ 4700 4850 4050 4850
+Wire Wire Line
+ 4700 4250 4550 4250
+Connection ~ 4550 4250
+Wire Wire Line
+ 4700 3950 4450 3950
+Connection ~ 4450 3950
+Wire Wire Line
+ 4700 3400 4550 3400
+Connection ~ 4550 3400
+Wire Wire Line
+ 4700 3100 4450 3100
+Connection ~ 4450 3100
+Wire Wire Line
+ 4700 2550 4550 2550
+Connection ~ 4550 2550
+Wire Wire Line
+ 2600 2250 4700 2250
+Connection ~ 4450 2250
+Wire Wire Line
+ 7700 3600 4550 3600
+Connection ~ 4550 3600
+Wire Wire Line
+ 7750 1600 4450 1600
+Connection ~ 4450 1600
+$Comp
+L Schmitt_Trigger X2
+U 1 1 684BA479
+P 2900 1700
+F 0 "X2" H 2500 1700 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 2950 1700 60 0000 C CNN
+F 2 "" H 2900 1700 60 0001 C CNN
+F 3 "" H 2900 1700 60 0001 C CNN
+ 1 2900 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L Schmitt_Trigger X3
+U 1 1 684BA5DA
+P 2900 2700
+F 0 "X3" H 2500 2700 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 2950 2700 60 0000 C CNN
+F 2 "" H 2900 2700 60 0001 C CNN
+F 3 "" H 2900 2700 60 0001 C CNN
+ 1 2900 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L Schmitt_Trigger X4
+U 1 1 684BA619
+P 2900 3750
+F 0 "X4" H 2500 3750 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 2950 3750 60 0000 C CNN
+F 2 "" H 2900 3750 60 0001 C CNN
+F 3 "" H 2900 3750 60 0001 C CNN
+ 1 2900 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L Schmitt_Trigger X1
+U 1 1 684BA672
+P 2850 5000
+F 0 "X1" H 2450 5000 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 2900 5000 60 0000 C CNN
+F 2 "" H 2850 5000 60 0001 C CNN
+F 3 "" H 2850 5000 60 0001 C CNN
+ 1 2850 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L Schmitt_Trigger X5
+U 1 1 684BA77B
+P 2950 6250
+F 0 "X5" H 2550 6250 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 3000 6250 60 0000 C CNN
+F 2 "" H 2950 6250 60 0001 C CNN
+F 3 "" H 2950 6250 60 0001 C CNN
+ 1 2950 6250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4000 2950 4000 3750
+Wire Wire Line
+ 3950 5000 3950 4100
+Wire Wire Line
+ 4050 4850 4050 6250
+Wire Wire Line
+ 2600 1250 4450 1250
+Connection ~ 4450 1550
+Wire Wire Line
+ 2600 2150 4550 2150
+Connection ~ 4550 2150
+Wire Wire Line
+ 2600 3150 4550 3150
+Connection ~ 4550 3150
+Wire Wire Line
+ 2600 3300 4450 3300
+Connection ~ 4450 3300
+Wire Wire Line
+ 2600 4200 4550 4200
+Connection ~ 4550 4200
+Wire Wire Line
+ 2550 4550 4450 4550
+Connection ~ 4450 4550
+Wire Wire Line
+ 4550 5450 2550 5450
+Connection ~ 4550 5000
+Wire Wire Line
+ 2650 5800 2650 4550
+Connection ~ 2650 4550
+Wire Wire Line
+ 2650 6700 2850 6700
+Wire Wire Line
+ 2850 6700 2850 5450
+Connection ~ 2850 5450
+$Comp
+L PORT U1
+U 1 1 684BB024
+P 1400 1700
+F 0 "U1" H 1450 1800 30 0000 C CNN
+F 1 "PORT" H 1400 1700 30 0000 C CNN
+F 2 "" H 1400 1700 60 0000 C CNN
+F 3 "" H 1400 1700 60 0000 C CNN
+ 1 1400 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684BB087
+P 1400 2700
+F 0 "U1" H 1450 2800 30 0000 C CNN
+F 1 "PORT" H 1400 2700 30 0000 C CNN
+F 2 "" H 1400 2700 60 0000 C CNN
+F 3 "" H 1400 2700 60 0000 C CNN
+ 2 1400 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684BB103
+P 1400 3750
+F 0 "U1" H 1450 3850 30 0000 C CNN
+F 1 "PORT" H 1400 3750 30 0000 C CNN
+F 2 "" H 1400 3750 60 0000 C CNN
+F 3 "" H 1400 3750 60 0000 C CNN
+ 3 1400 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684BB194
+P 1400 5000
+F 0 "U1" H 1450 5100 30 0000 C CNN
+F 1 "PORT" H 1400 5000 30 0000 C CNN
+F 2 "" H 1400 5000 60 0000 C CNN
+F 3 "" H 1400 5000 60 0000 C CNN
+ 4 1400 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684BB25E
+P 1400 6250
+F 0 "U1" H 1450 6350 30 0000 C CNN
+F 1 "PORT" H 1400 6250 30 0000 C CNN
+F 2 "" H 1400 6250 60 0000 C CNN
+F 3 "" H 1400 6250 60 0000 C CNN
+ 5 1400 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684BB3D1
+P 7350 1500
+F 0 "U1" H 7400 1600 30 0000 C CNN
+F 1 "PORT" H 7350 1500 30 0000 C CNN
+F 2 "" H 7350 1500 60 0000 C CNN
+F 3 "" H 7350 1500 60 0000 C CNN
+ 6 7350 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684BB471
+P 7350 3250
+F 0 "U1" H 7400 3350 30 0000 C CNN
+F 1 "PORT" H 7350 3250 30 0000 C CNN
+F 2 "" H 7350 3250 60 0000 C CNN
+F 3 "" H 7350 3250 60 0000 C CNN
+ 7 7350 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 684BB4EC
+P 7350 3700
+F 0 "U1" H 7400 3800 30 0000 C CNN
+F 1 "PORT" H 7350 3700 30 0000 C CNN
+F 2 "" H 7350 3700 60 0000 C CNN
+F 3 "" H 7350 3700 60 0000 C CNN
+ 8 7350 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684BB5BA
+P 10500 1600
+F 0 "U1" H 10550 1700 30 0000 C CNN
+F 1 "PORT" H 10500 1600 30 0000 C CNN
+F 2 "" H 10500 1600 60 0000 C CNN
+F 3 "" H 10500 1600 60 0000 C CNN
+ 9 10500 1600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684BB6E5
+P 10500 1850
+F 0 "U1" H 10550 1950 30 0000 C CNN
+F 1 "PORT" H 10500 1850 30 0000 C CNN
+F 2 "" H 10500 1850 60 0000 C CNN
+F 3 "" H 10500 1850 60 0000 C CNN
+ 10 10500 1850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 684BB74E
+P 10500 2100
+F 0 "U1" H 10550 2200 30 0000 C CNN
+F 1 "PORT" H 10500 2100 30 0000 C CNN
+F 2 "" H 10500 2100 60 0000 C CNN
+F 3 "" H 10500 2100 60 0000 C CNN
+ 11 10500 2100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 684BB809
+P 10500 2350
+F 0 "U1" H 10550 2450 30 0000 C CNN
+F 1 "PORT" H 10500 2350 30 0000 C CNN
+F 2 "" H 10500 2350 60 0000 C CNN
+F 3 "" H 10500 2350 60 0000 C CNN
+ 12 10500 2350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 684BB87A
+P 10500 2800
+F 0 "U1" H 10550 2900 30 0000 C CNN
+F 1 "PORT" H 10500 2800 30 0000 C CNN
+F 2 "" H 10500 2800 60 0000 C CNN
+F 3 "" H 10500 2800 60 0000 C CNN
+ 13 10500 2800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 684BB913
+P 10500 3000
+F 0 "U1" H 10550 3100 30 0000 C CNN
+F 1 "PORT" H 10500 3000 30 0000 C CNN
+F 2 "" H 10500 3000 60 0000 C CNN
+F 3 "" H 10500 3000 60 0000 C CNN
+ 14 10500 3000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 684BB98A
+P 10500 3250
+F 0 "U1" H 10550 3350 30 0000 C CNN
+F 1 "PORT" H 10500 3250 30 0000 C CNN
+F 2 "" H 10500 3250 60 0000 C CNN
+F 3 "" H 10500 3250 60 0000 C CNN
+ 15 10500 3250
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 684BB9EB
+P 10500 3550
+F 0 "U1" H 10550 3650 30 0000 C CNN
+F 1 "PORT" H 10500 3550 30 0000 C CNN
+F 2 "" H 10500 3550 60 0000 C CNN
+F 3 "" H 10500 3550 60 0000 C CNN
+ 16 10500 3550
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9950 1600 10250 1600
+Wire Wire Line
+ 9950 1850 10250 1850
+Wire Wire Line
+ 9950 2100 10250 2100
+Wire Wire Line
+ 9950 2350 10250 2350
+Wire Wire Line
+ 9950 2800 10250 2800
+Wire Wire Line
+ 9950 3000 10250 3000
+Wire Wire Line
+ 9950 3250 10250 3250
+Wire Wire Line
+ 9950 3550 10250 3550
+Wire Wire Line
+ 7600 3250 7750 3250
+Wire Wire Line
+ 7600 3700 7600 3600
+Connection ~ 7600 3600
+Wire Wire Line
+ 7600 1500 7600 1600
+Connection ~ 7600 1600
+Wire Wire Line
+ 1650 1700 1900 1700
+Wire Wire Line
+ 1650 2700 1900 2700
+Wire Wire Line
+ 1650 3750 1900 3750
+Wire Wire Line
+ 1650 5000 1850 5000
+Wire Wire Line
+ 1650 6250 1950 6250
+$Comp
+L SKY130mode scmode1
+U 1 1 684BCA2F
+P 8750 5500
+F 0 "scmode1" H 8750 5650 98 0000 C CNB
+F 1 "SKY130mode" H 8750 5400 118 0000 C CNB
+F 2 "" H 8750 5650 60 0001 C CNN
+F 3 "" H 8750 5650 60 0001 C CNN
+ 1 8750 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L Decoder_38_Address_Latch_storage X?
+U 1 1 684CFBD4
+P 8850 2600
+F 0 "X?" H 8850 2450 60 0000 C CNN
+F 1 "Decoder_38_Address_Latch_storage" H 8950 2600 60 0000 C CNN
+F 2 "" H 8850 2600 60 0001 C CNN
+F 3 "" H 8850 2600 60 0001 C CNN
+ 1 8850 2600
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/SN74HC259.cir b/library/SubcircuitLibrary/SN74HC259/SN74HC259.cir
new file mode 100644
index 000000000..37dd5be78
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/SN74HC259.cir
@@ -0,0 +1,23 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/SN74HC259/SN74HC259.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jun 14 09:55:16 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X6 Net-_X11-Pad17_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X11-Pad13_ CMOS_INVTR
+X7 Net-_X11-Pad18_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X11-Pad14_ CMOS_INVTR
+X8 Net-_X11-Pad19_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X11-Pad15_ CMOS_INVTR
+X9 Net-_X1-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X11-Pad16_ CMOS_INVTR
+X10 Net-_X10-Pad1_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X10-Pad4_ CMOS_INVTR
+X2 Net-_U1-Pad1_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X11-Pad17_ Schmitt_Trigger
+X3 Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X11-Pad18_ Schmitt_Trigger
+X4 Net-_U1-Pad3_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X11-Pad19_ Schmitt_Trigger
+X1 Net-_U1-Pad4_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X1-Pad4_ Schmitt_Trigger
+X5 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_X10-Pad1_ Schmitt_Trigger
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ PORT
+scmode1 SKY130mode
+X11 Net-_U1-Pad9_ Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U1-Pad12_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_X10-Pad4_ Net-_U1-Pad7_ Net-_X11-Pad13_ Net-_X11-Pad14_ Net-_X11-Pad15_ Net-_X11-Pad16_ Net-_X11-Pad17_ Net-_X11-Pad18_ Net-_X11-Pad19_ Decoder_38_Address_Latch_storage
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/SN74HC259.cir.out b/library/SubcircuitLibrary/SN74HC259/SN74HC259.cir.out
new file mode 100644
index 000000000..15ad3bb0a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/SN74HC259.cir.out
@@ -0,0 +1,29 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/sn74hc259/sn74hc259.cir
+
+.include CMOS_INVTR.sub
+.include Schmitt_Trigger.sub
+.include Decoder_38_Address_Latch_storage.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x6 net-_x11-pad17_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad13_ CMOS_INVTR
+x7 net-_x11-pad18_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad14_ CMOS_INVTR
+x8 net-_x11-pad19_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad15_ CMOS_INVTR
+x9 net-_x1-pad4_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad16_ CMOS_INVTR
+x10 net-_x10-pad1_ net-_u1-pad6_ net-_u1-pad8_ net-_x10-pad4_ CMOS_INVTR
+x2 net-_u1-pad1_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad17_ Schmitt_Trigger
+x3 net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad18_ Schmitt_Trigger
+x4 net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad19_ Schmitt_Trigger
+x1 net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad8_ net-_x1-pad4_ Schmitt_Trigger
+x5 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_x10-pad1_ Schmitt_Trigger
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
+* s c m o d e
+x11 net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad12_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x10-pad4_ net-_u1-pad7_ net-_x11-pad13_ net-_x11-pad14_ net-_x11-pad15_ net-_x11-pad16_ net-_x11-pad17_ net-_x11-pad18_ net-_x11-pad19_ Decoder_38_Address_Latch_storage
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/SN74HC259.pro b/library/SubcircuitLibrary/SN74HC259/SN74HC259.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/SN74HC259.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74HC259/SN74HC259.sch b/library/SubcircuitLibrary/SN74HC259/SN74HC259.sch
new file mode 100644
index 000000000..f4dbfed48
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/SN74HC259.sch
@@ -0,0 +1,531 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74HC259-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CMOS_INVTR X6
+U 1 1 684B99C4
+P 5350 1700
+F 0 "X6" H 5350 1700 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 1450 60 0000 C CNN
+F 2 "" H 5350 1700 60 0001 C CNN
+F 3 "" H 5350 1700 60 0001 C CNN
+ 1 5350 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X7
+U 1 1 684B9A21
+P 5350 2400
+F 0 "X7" H 5350 2400 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 2150 60 0000 C CNN
+F 2 "" H 5350 2400 60 0001 C CNN
+F 3 "" H 5350 2400 60 0001 C CNN
+ 1 5350 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X8
+U 1 1 684B9A8E
+P 5350 3250
+F 0 "X8" H 5350 3250 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 3000 60 0000 C CNN
+F 2 "" H 5350 3250 60 0001 C CNN
+F 3 "" H 5350 3250 60 0001 C CNN
+ 1 5350 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X9
+U 1 1 684B9B4B
+P 5350 4100
+F 0 "X9" H 5350 4100 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 3850 60 0000 C CNN
+F 2 "" H 5350 4100 60 0001 C CNN
+F 3 "" H 5350 4100 60 0001 C CNN
+ 1 5350 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X10
+U 1 1 684B9D35
+P 5350 4850
+F 0 "X10" H 5350 4850 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5450 4600 60 0000 C CNN
+F 2 "" H 5350 4850 60 0001 C CNN
+F 3 "" H 5350 4850 60 0001 C CNN
+ 1 5350 4850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6150 1700 7750 1700
+Wire Wire Line
+ 7750 1700 7750 1750
+Wire Wire Line
+ 6150 2400 6150 1900
+Wire Wire Line
+ 6150 1900 7750 1900
+Wire Wire Line
+ 6150 3250 6350 3250
+Wire Wire Line
+ 6350 3250 6350 2050
+Wire Wire Line
+ 6350 2050 7750 2050
+Wire Wire Line
+ 4000 1700 4700 1700
+Wire Wire Line
+ 4350 1700 4350 2100
+Wire Wire Line
+ 4350 2100 7750 2100
+Wire Wire Line
+ 7750 2100 7750 2250
+Connection ~ 4350 1700
+Wire Wire Line
+ 7750 2400 6400 2400
+Wire Wire Line
+ 6400 2400 6400 2700
+Wire Wire Line
+ 6400 2700 4000 2700
+Wire Wire Line
+ 4700 2400 4350 2400
+Wire Wire Line
+ 4350 2400 4350 2700
+Connection ~ 4350 2700
+Wire Wire Line
+ 7750 2550 6450 2550
+Wire Wire Line
+ 6450 2550 6450 2950
+Wire Wire Line
+ 6450 2950 4000 2950
+Wire Wire Line
+ 4700 3250 4350 3250
+Wire Wire Line
+ 4350 3250 4350 2950
+Connection ~ 4350 2950
+Wire Wire Line
+ 6150 4100 6750 4100
+Wire Wire Line
+ 6750 4100 6750 2850
+Wire Wire Line
+ 6750 2850 7700 2850
+Wire Wire Line
+ 6150 4850 6900 4850
+Wire Wire Line
+ 6900 4850 6900 3050
+Wire Wire Line
+ 6900 3050 7750 3050
+Wire Wire Line
+ 4700 1850 4550 1850
+Wire Wire Line
+ 4550 1850 4550 5450
+Wire Wire Line
+ 4550 5000 4700 5000
+Wire Wire Line
+ 4700 1550 4450 1550
+Wire Wire Line
+ 4450 1250 4450 4700
+Wire Wire Line
+ 4450 4700 4700 4700
+Wire Wire Line
+ 3950 4100 4700 4100
+Wire Wire Line
+ 4700 4850 4050 4850
+Wire Wire Line
+ 4700 4250 4550 4250
+Connection ~ 4550 4250
+Wire Wire Line
+ 4700 3950 4450 3950
+Connection ~ 4450 3950
+Wire Wire Line
+ 4700 3400 4550 3400
+Connection ~ 4550 3400
+Wire Wire Line
+ 4700 3100 4450 3100
+Connection ~ 4450 3100
+Wire Wire Line
+ 4700 2550 4550 2550
+Connection ~ 4550 2550
+Wire Wire Line
+ 2600 2250 4700 2250
+Connection ~ 4450 2250
+Wire Wire Line
+ 7700 3600 4550 3600
+Connection ~ 4550 3600
+Wire Wire Line
+ 7750 1600 4450 1600
+Connection ~ 4450 1600
+$Comp
+L Schmitt_Trigger X2
+U 1 1 684BA479
+P 2900 1700
+F 0 "X2" H 2500 1700 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 2950 1700 60 0000 C CNN
+F 2 "" H 2900 1700 60 0001 C CNN
+F 3 "" H 2900 1700 60 0001 C CNN
+ 1 2900 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L Schmitt_Trigger X3
+U 1 1 684BA5DA
+P 2900 2700
+F 0 "X3" H 2500 2700 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 2950 2700 60 0000 C CNN
+F 2 "" H 2900 2700 60 0001 C CNN
+F 3 "" H 2900 2700 60 0001 C CNN
+ 1 2900 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L Schmitt_Trigger X4
+U 1 1 684BA619
+P 2900 3750
+F 0 "X4" H 2500 3750 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 2950 3750 60 0000 C CNN
+F 2 "" H 2900 3750 60 0001 C CNN
+F 3 "" H 2900 3750 60 0001 C CNN
+ 1 2900 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L Schmitt_Trigger X1
+U 1 1 684BA672
+P 2850 5000
+F 0 "X1" H 2450 5000 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 2900 5000 60 0000 C CNN
+F 2 "" H 2850 5000 60 0001 C CNN
+F 3 "" H 2850 5000 60 0001 C CNN
+ 1 2850 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L Schmitt_Trigger X5
+U 1 1 684BA77B
+P 2950 6250
+F 0 "X5" H 2550 6250 60 0000 C CNN
+F 1 "Schmitt_Trigger" H 3000 6250 60 0000 C CNN
+F 2 "" H 2950 6250 60 0001 C CNN
+F 3 "" H 2950 6250 60 0001 C CNN
+ 1 2950 6250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4000 2950 4000 3750
+Wire Wire Line
+ 3950 5000 3950 4100
+Wire Wire Line
+ 4050 4850 4050 6250
+Wire Wire Line
+ 2600 1250 4450 1250
+Connection ~ 4450 1550
+Wire Wire Line
+ 2600 2150 4550 2150
+Connection ~ 4550 2150
+Wire Wire Line
+ 2600 3150 4550 3150
+Connection ~ 4550 3150
+Wire Wire Line
+ 2600 3300 4450 3300
+Connection ~ 4450 3300
+Wire Wire Line
+ 2600 4200 4550 4200
+Connection ~ 4550 4200
+Wire Wire Line
+ 2550 4550 4450 4550
+Connection ~ 4450 4550
+Wire Wire Line
+ 4550 5450 2550 5450
+Connection ~ 4550 5000
+Wire Wire Line
+ 2650 5800 2650 4550
+Connection ~ 2650 4550
+Wire Wire Line
+ 2650 6700 2850 6700
+Wire Wire Line
+ 2850 6700 2850 5450
+Connection ~ 2850 5450
+$Comp
+L PORT U1
+U 1 1 684BB024
+P 1400 1700
+F 0 "U1" H 1450 1800 30 0000 C CNN
+F 1 "PORT" H 1400 1700 30 0000 C CNN
+F 2 "" H 1400 1700 60 0000 C CNN
+F 3 "" H 1400 1700 60 0000 C CNN
+ 1 1400 1700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684BB087
+P 1400 2700
+F 0 "U1" H 1450 2800 30 0000 C CNN
+F 1 "PORT" H 1400 2700 30 0000 C CNN
+F 2 "" H 1400 2700 60 0000 C CNN
+F 3 "" H 1400 2700 60 0000 C CNN
+ 2 1400 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684BB103
+P 1400 3750
+F 0 "U1" H 1450 3850 30 0000 C CNN
+F 1 "PORT" H 1400 3750 30 0000 C CNN
+F 2 "" H 1400 3750 60 0000 C CNN
+F 3 "" H 1400 3750 60 0000 C CNN
+ 3 1400 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684BB194
+P 1400 5000
+F 0 "U1" H 1450 5100 30 0000 C CNN
+F 1 "PORT" H 1400 5000 30 0000 C CNN
+F 2 "" H 1400 5000 60 0000 C CNN
+F 3 "" H 1400 5000 60 0000 C CNN
+ 4 1400 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684BB25E
+P 1400 6250
+F 0 "U1" H 1450 6350 30 0000 C CNN
+F 1 "PORT" H 1400 6250 30 0000 C CNN
+F 2 "" H 1400 6250 60 0000 C CNN
+F 3 "" H 1400 6250 60 0000 C CNN
+ 5 1400 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684BB3D1
+P 7350 1500
+F 0 "U1" H 7400 1600 30 0000 C CNN
+F 1 "PORT" H 7350 1500 30 0000 C CNN
+F 2 "" H 7350 1500 60 0000 C CNN
+F 3 "" H 7350 1500 60 0000 C CNN
+ 6 7350 1500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684BB471
+P 7350 3250
+F 0 "U1" H 7400 3350 30 0000 C CNN
+F 1 "PORT" H 7350 3250 30 0000 C CNN
+F 2 "" H 7350 3250 60 0000 C CNN
+F 3 "" H 7350 3250 60 0000 C CNN
+ 7 7350 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 684BB4EC
+P 7350 3700
+F 0 "U1" H 7400 3800 30 0000 C CNN
+F 1 "PORT" H 7350 3700 30 0000 C CNN
+F 2 "" H 7350 3700 60 0000 C CNN
+F 3 "" H 7350 3700 60 0000 C CNN
+ 8 7350 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684BB5BA
+P 10500 1600
+F 0 "U1" H 10550 1700 30 0000 C CNN
+F 1 "PORT" H 10500 1600 30 0000 C CNN
+F 2 "" H 10500 1600 60 0000 C CNN
+F 3 "" H 10500 1600 60 0000 C CNN
+ 9 10500 1600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684BB6E5
+P 10500 1850
+F 0 "U1" H 10550 1950 30 0000 C CNN
+F 1 "PORT" H 10500 1850 30 0000 C CNN
+F 2 "" H 10500 1850 60 0000 C CNN
+F 3 "" H 10500 1850 60 0000 C CNN
+ 10 10500 1850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 684BB74E
+P 10500 2100
+F 0 "U1" H 10550 2200 30 0000 C CNN
+F 1 "PORT" H 10500 2100 30 0000 C CNN
+F 2 "" H 10500 2100 60 0000 C CNN
+F 3 "" H 10500 2100 60 0000 C CNN
+ 11 10500 2100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 684BB809
+P 10500 2350
+F 0 "U1" H 10550 2450 30 0000 C CNN
+F 1 "PORT" H 10500 2350 30 0000 C CNN
+F 2 "" H 10500 2350 60 0000 C CNN
+F 3 "" H 10500 2350 60 0000 C CNN
+ 12 10500 2350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 684BB87A
+P 10500 2800
+F 0 "U1" H 10550 2900 30 0000 C CNN
+F 1 "PORT" H 10500 2800 30 0000 C CNN
+F 2 "" H 10500 2800 60 0000 C CNN
+F 3 "" H 10500 2800 60 0000 C CNN
+ 13 10500 2800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 684BB913
+P 10500 3000
+F 0 "U1" H 10550 3100 30 0000 C CNN
+F 1 "PORT" H 10500 3000 30 0000 C CNN
+F 2 "" H 10500 3000 60 0000 C CNN
+F 3 "" H 10500 3000 60 0000 C CNN
+ 14 10500 3000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 684BB98A
+P 10500 3250
+F 0 "U1" H 10550 3350 30 0000 C CNN
+F 1 "PORT" H 10500 3250 30 0000 C CNN
+F 2 "" H 10500 3250 60 0000 C CNN
+F 3 "" H 10500 3250 60 0000 C CNN
+ 15 10500 3250
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 684BB9EB
+P 10500 3550
+F 0 "U1" H 10550 3650 30 0000 C CNN
+F 1 "PORT" H 10500 3550 30 0000 C CNN
+F 2 "" H 10500 3550 60 0000 C CNN
+F 3 "" H 10500 3550 60 0000 C CNN
+ 16 10500 3550
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9950 1600 10250 1600
+Wire Wire Line
+ 9950 1850 10250 1850
+Wire Wire Line
+ 9950 2100 10250 2100
+Wire Wire Line
+ 9950 2350 10250 2350
+Wire Wire Line
+ 9950 2800 10250 2800
+Wire Wire Line
+ 9950 3000 10250 3000
+Wire Wire Line
+ 9950 3250 10250 3250
+Wire Wire Line
+ 9950 3550 10250 3550
+Wire Wire Line
+ 7600 3250 7750 3250
+Wire Wire Line
+ 7600 3700 7600 3600
+Connection ~ 7600 3600
+Wire Wire Line
+ 7600 1500 7600 1600
+Connection ~ 7600 1600
+Wire Wire Line
+ 1650 1700 1900 1700
+Wire Wire Line
+ 1650 2700 1900 2700
+Wire Wire Line
+ 1650 3750 1900 3750
+Wire Wire Line
+ 1650 5000 1850 5000
+Wire Wire Line
+ 1650 6250 1950 6250
+$Comp
+L SKY130mode scmode1
+U 1 1 684BCA2F
+P 8750 5500
+F 0 "scmode1" H 8750 5650 98 0000 C CNB
+F 1 "SKY130mode" H 8750 5400 118 0000 C CNB
+F 2 "" H 8750 5650 60 0001 C CNN
+F 3 "" H 8750 5650 60 0001 C CNN
+ 1 8750 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L Decoder_38_Address_Latch_storage X11
+U 1 1 684CFBD4
+P 8850 2600
+F 0 "X11" H 8850 2450 60 0000 C CNN
+F 1 "Decoder_38_Address_Latch_storage" H 8950 2600 60 0000 C CNN
+F 2 "" H 8850 2600 60 0001 C CNN
+F 3 "" H 8850 2600 60 0001 C CNN
+ 1 8850 2600
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/SN74HC259.sub b/library/SubcircuitLibrary/SN74HC259/SN74HC259.sub
new file mode 100644
index 000000000..279089f43
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/SN74HC259.sub
@@ -0,0 +1,23 @@
+* Subcircuit SN74HC259
+.subckt SN74HC259 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/sn74hc259/sn74hc259.cir
+.include CMOS_INVTR.sub
+.include Schmitt_Trigger.sub
+.include Decoder_38_Address_Latch_storage.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x6 net-_x11-pad17_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad13_ CMOS_INVTR
+x7 net-_x11-pad18_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad14_ CMOS_INVTR
+x8 net-_x11-pad19_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad15_ CMOS_INVTR
+x9 net-_x1-pad4_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad16_ CMOS_INVTR
+x10 net-_x10-pad1_ net-_u1-pad6_ net-_u1-pad8_ net-_x10-pad4_ CMOS_INVTR
+x2 net-_u1-pad1_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad17_ Schmitt_Trigger
+x3 net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad18_ Schmitt_Trigger
+x4 net-_u1-pad3_ net-_u1-pad6_ net-_u1-pad8_ net-_x11-pad19_ Schmitt_Trigger
+x1 net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad8_ net-_x1-pad4_ Schmitt_Trigger
+x5 net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_x10-pad1_ Schmitt_Trigger
+* s c m o d e
+x11 net-_u1-pad9_ net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad12_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_x10-pad4_ net-_u1-pad7_ net-_x11-pad13_ net-_x11-pad14_ net-_x11-pad15_ net-_x11-pad16_ net-_x11-pad17_ net-_x11-pad18_ net-_x11-pad19_ Decoder_38_Address_Latch_storage
+* Control Statements
+
+.ends SN74HC259
diff --git a/library/SubcircuitLibrary/SN74HC259/SN74HC259_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC259/SN74HC259_Previous_Values.xml
new file mode 100644
index 000000000..67532ae04
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/SN74HC259_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/CMOS_INVTR/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Schmitt_Trigger/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Schmitt_Trigger/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Schmitt_Trigger/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Schmitt_Trigger/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Schmitt_Trigger/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Decoder_38_Address_Latch_storagetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger-cache.lib b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.cir b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.cir
new file mode 100644
index 000000000..36477c500
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.cir
@@ -0,0 +1,20 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Schmitt_Trigger/Schmitt_Trigger.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Mon Jun 9 08:39:40 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC2-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad1_ Net-_SC1-Pad1_ sky130_fd_pr__pfet_01v8
+SC3 Net-_SC2-Pad1_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC3-Pad3_ Net-_SC1-Pad2_ Net-_SC4-Pad3_ Net-_SC4-Pad3_ sky130_fd_pr__nfet_01v8
+SC5 Net-_SC4-Pad3_ Net-_SC2-Pad1_ Net-_SC1-Pad1_ Net-_SC1-Pad1_ sky130_fd_pr__pfet_01v8
+SC6 Net-_SC1-Pad3_ Net-_SC2-Pad1_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+SC7 Net-_SC7-Pad1_ Net-_SC2-Pad1_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC8 Net-_SC7-Pad1_ Net-_SC2-Pad1_ Net-_SC4-Pad3_ Net-_SC4-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC4-Pad3_ Net-_SC7-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.cir.out b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.cir.out
new file mode 100644
index 000000000..3935e9ff4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.cir.out
@@ -0,0 +1,24 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/schmitt_trigger/schmitt_trigger.cir
+
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc1-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc2-pad1_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc6 net-_sc1-pad3_ net-_sc2-pad1_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc7-pad1_ net-_sc2-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc7-pad1_ net-_sc2-pad1_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc4-pad3_ net-_sc7-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.pro b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.sch b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.sch
new file mode 100644
index 000000000..f8fee114a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.sch
@@ -0,0 +1,312 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 68464E7B
+P 3850 1600
+F 0 "SC1" H 3900 1900 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4150 1687 50 0000 R CNN
+F 2 "" H 3850 100 50 0001 C CNN
+F 3 "" H 3850 1600 50 0001 C CNN
+ 1 3850 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 68465252
+P 3850 2400
+F 0 "SC2" H 3900 2700 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4150 2487 50 0000 R CNN
+F 2 "" H 3850 900 50 0001 C CNN
+F 3 "" H 3850 2400 50 0001 C CNN
+ 1 3850 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 68465307
+P 3850 3400
+F 0 "SC3" H 3900 3700 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4150 3487 50 0000 R CNN
+F 2 "" H 3850 1900 50 0001 C CNN
+F 3 "" H 3850 3400 50 0001 C CNN
+ 1 3850 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 68465392
+P 3850 4200
+F 0 "SC4" H 3900 4500 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4150 4287 50 0000 R CNN
+F 2 "" H 3850 2700 50 0001 C CNN
+F 3 "" H 3850 4200 50 0001 C CNN
+ 1 3850 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC5
+U 1 1 68465403
+P 4850 2200
+F 0 "SC5" H 4900 2500 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5150 2287 50 0000 R CNN
+F 2 "" H 4850 700 50 0001 C CNN
+F 3 "" H 4850 2200 50 0001 C CNN
+ 1 4850 2200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 6846558D
+P 4850 3600
+F 0 "SC6" H 4900 3900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5150 3687 50 0000 R CNN
+F 2 "" H 4850 2100 50 0001 C CNN
+F 3 "" H 4850 3600 50 0001 C CNN
+ 1 4850 3600
+ 0 1 1 0
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC7
+U 1 1 68465896
+P 5900 1900
+F 0 "SC7" H 5950 2200 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6200 1987 50 0000 R CNN
+F 2 "" H 5900 400 50 0001 C CNN
+F 3 "" H 5900 1900 50 0001 C CNN
+ 1 5900 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC8
+U 1 1 68465B12
+P 5900 3900
+F 0 "SC8" H 5950 4200 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6200 3987 50 0000 R CNN
+F 2 "" H 5900 2400 50 0001 C CNN
+F 3 "" H 5900 3900 50 0001 C CNN
+ 1 5900 3900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6100 2200 6100 3600
+Wire Wire Line
+ 5600 1900 5600 3900
+Wire Wire Line
+ 4050 2700 4050 3100
+Wire Wire Line
+ 4050 2900 5600 2900
+Connection ~ 5600 2900
+Connection ~ 4050 2900
+Wire Wire Line
+ 4850 2500 4850 3300
+Connection ~ 4850 2900
+Wire Wire Line
+ 4050 1900 4050 2100
+Wire Wire Line
+ 4550 2000 4050 2000
+Connection ~ 4050 2000
+Wire Wire Line
+ 4050 1300 6100 1300
+Wire Wire Line
+ 6100 1300 6100 1600
+Wire Wire Line
+ 4050 4500 6100 4500
+Wire Wire Line
+ 6100 4500 6100 4200
+Wire Wire Line
+ 5150 2000 5500 2000
+Wire Wire Line
+ 5500 2000 5500 4500
+Connection ~ 5500 4500
+Wire Wire Line
+ 5150 3800 5400 3800
+Wire Wire Line
+ 5400 3800 5400 1300
+Connection ~ 5400 1300
+Wire Wire Line
+ 3550 1600 3350 1600
+Wire Wire Line
+ 3350 1600 3350 4200
+Wire Wire Line
+ 3350 4200 3550 4200
+Wire Wire Line
+ 4050 3700 4050 3900
+Wire Wire Line
+ 4550 3800 4050 3800
+Connection ~ 4050 3800
+Wire Wire Line
+ 4850 3700 4850 3900
+Wire Wire Line
+ 4850 3900 4450 3900
+Wire Wire Line
+ 4450 3900 4450 3800
+Connection ~ 4450 3800
+Wire Wire Line
+ 3950 4200 4100 4200
+Wire Wire Line
+ 4100 4200 4100 4500
+Connection ~ 4100 4500
+Wire Wire Line
+ 6000 3900 6150 3900
+Wire Wire Line
+ 6150 3900 6150 4250
+Wire Wire Line
+ 6150 4250 6100 4250
+Connection ~ 6100 4250
+Wire Wire Line
+ 3950 3400 4150 3400
+Wire Wire Line
+ 4150 3400 4150 3800
+Connection ~ 4150 3800
+Wire Wire Line
+ 3950 2400 4100 2400
+Wire Wire Line
+ 4100 2400 4100 2000
+Connection ~ 4100 2000
+Wire Wire Line
+ 4850 2100 4850 1950
+Wire Wire Line
+ 4850 1950 4500 1950
+Wire Wire Line
+ 4500 1950 4500 2000
+Connection ~ 4500 2000
+Wire Wire Line
+ 3950 1600 4100 1600
+Wire Wire Line
+ 4100 1600 4100 1300
+Connection ~ 4100 1300
+Wire Wire Line
+ 6000 1900 6150 1900
+Wire Wire Line
+ 6150 1900 6150 1500
+Wire Wire Line
+ 6150 1500 6100 1500
+Connection ~ 6100 1500
+Wire Wire Line
+ 3550 2400 3350 2400
+Connection ~ 3350 2400
+Wire Wire Line
+ 3550 3400 3350 3400
+Connection ~ 3350 3400
+$Comp
+L PORT U1
+U 1 1 68466403
+P 2850 2900
+F 0 "U1" H 2900 3000 30 0000 C CNN
+F 1 "PORT" H 2850 2900 30 0000 C CNN
+F 2 "" H 2850 2900 60 0000 C CNN
+F 3 "" H 2850 2900 60 0000 C CNN
+ 1 2850 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684664D8
+P 4500 1050
+F 0 "U1" H 4550 1150 30 0000 C CNN
+F 1 "PORT" H 4500 1050 30 0000 C CNN
+F 2 "" H 4500 1050 60 0000 C CNN
+F 3 "" H 4500 1050 60 0000 C CNN
+ 2 4500 1050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68466579
+P 6600 2950
+F 0 "U1" H 6650 3050 30 0000 C CNN
+F 1 "PORT" H 6600 2950 30 0000 C CNN
+F 2 "" H 6600 2950 60 0000 C CNN
+F 3 "" H 6600 2950 60 0000 C CNN
+ 4 6600 2950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68466640
+P 4600 4800
+F 0 "U1" H 4650 4900 30 0000 C CNN
+F 1 "PORT" H 4600 4800 30 0000 C CNN
+F 2 "" H 4600 4800 60 0000 C CNN
+F 3 "" H 4600 4800 60 0000 C CNN
+ 3 4600 4800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4850 4800 4850 4500
+Connection ~ 4850 4500
+Wire Wire Line
+ 3100 2900 3350 2900
+Connection ~ 3350 2900
+Wire Wire Line
+ 6350 2950 6100 2950
+Connection ~ 6100 2950
+Wire Wire Line
+ 4750 1050 4750 1300
+Connection ~ 4750 1300
+$Comp
+L SKY130mode scmode1
+U 1 1 6846736A
+P 8750 3650
+F 0 "scmode1" H 8750 3800 98 0000 C CNB
+F 1 "SKY130mode" H 8750 3550 118 0000 C CNB
+F 2 "" H 8750 3800 60 0001 C CNN
+F 3 "" H 8750 3800 60 0001 C CNN
+ 1 8750 3650
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.sub b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.sub
new file mode 100644
index 000000000..48e9e5d96
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger.sub
@@ -0,0 +1,18 @@
+* Subcircuit Schmitt_Trigger
+.subckt Schmitt_Trigger net-_sc1-pad2_ net-_sc1-pad3_ net-_sc4-pad3_ net-_sc7-pad1_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/schmitt_trigger/schmitt_trigger.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc2-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc1-pad2_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc2-pad1_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc6 net-_sc1-pad3_ net-_sc2-pad1_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc7 net-_sc7-pad1_ net-_sc2-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc7-pad1_ net-_sc2-pad1_ net-_sc4-pad3_ net-_sc4-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends Schmitt_Trigger
diff --git a/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger_Previous_Values.xml b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger_Previous_Values.xml
new file mode 100644
index 000000000..7d6ec6b4d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/Schmitt_Trigger_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=1 l=0.15w=3 l=0.15w=1 l=0.15
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74HC259/analysis b/library/SubcircuitLibrary/SN74HC259/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74HC259/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396-cache.lib b/library/SubcircuitLibrary/SN74LS396/SN74LS396-cache.lib
new file mode 100644
index 000000000..5ce2c6d86
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396-cache.lib
@@ -0,0 +1,109 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir b/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir
new file mode 100644
index 000000000..1d2fc1cfa
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir
@@ -0,0 +1,29 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS396\SN74LS396.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/12/25 14:56:18
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 /3 Net-_U1-Pad2_ ? ? Net-_U3-Pad5_ Net-_U11-Pad1_ d_dff
+U7 Net-_U3-Pad5_ Net-_U1-Pad2_ ? ? ? Net-_U12-Pad2_ d_dff
+U4 /6 Net-_U1-Pad2_ ? ? Net-_U4-Pad5_ Net-_U13-Pad1_ d_dff
+U8 Net-_U4-Pad5_ Net-_U1-Pad2_ ? ? ? Net-_U14-Pad2_ d_dff
+U5 /9 Net-_U1-Pad2_ ? ? Net-_U5-Pad5_ Net-_U15-Pad1_ d_dff
+U9 Net-_U5-Pad5_ Net-_U1-Pad2_ ? ? ? Net-_U16-Pad2_ d_dff
+U6 /12 Net-_U1-Pad2_ ? ? Net-_U10-Pad1_ Net-_U17-Pad1_ d_dff
+U10 Net-_U10-Pad1_ Net-_U1-Pad2_ ? ? ? Net-_U10-Pad6_ d_dff
+U13 Net-_U13-Pad1_ Net-_U11-Pad2_ /5 d_nor
+U14 Net-_U11-Pad2_ Net-_U14-Pad2_ /4 d_nor
+U15 Net-_U15-Pad1_ Net-_U11-Pad2_ /10 d_nor
+U16 Net-_U11-Pad2_ Net-_U16-Pad2_ /11 d_nor
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ /2 d_nor
+U12 Net-_U11-Pad2_ Net-_U12-Pad2_ /1 d_nor
+U17 Net-_U17-Pad1_ Net-_U11-Pad2_ /13 d_nor
+U18 Net-_U11-Pad2_ Net-_U10-Pad6_ /14 d_nor
+U2 /15 Net-_U11-Pad2_ d_buffer
+U1 /7 Net-_U1-Pad2_ d_inverter
+U19 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir.out b/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir.out
new file mode 100644
index 000000000..70c4b5306
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.cir.out
@@ -0,0 +1,84 @@
+* d:\fossee\esim\library\subcircuitlibrary\sn74ls396\sn74ls396.cir
+
+* u3 /3 net-_u1-pad2_ ? ? net-_u3-pad5_ net-_u11-pad1_ d_dff
+* u7 net-_u3-pad5_ net-_u1-pad2_ ? ? ? net-_u12-pad2_ d_dff
+* u4 /6 net-_u1-pad2_ ? ? net-_u4-pad5_ net-_u13-pad1_ d_dff
+* u8 net-_u4-pad5_ net-_u1-pad2_ ? ? ? net-_u14-pad2_ d_dff
+* u5 /9 net-_u1-pad2_ ? ? net-_u5-pad5_ net-_u15-pad1_ d_dff
+* u9 net-_u5-pad5_ net-_u1-pad2_ ? ? ? net-_u16-pad2_ d_dff
+* u6 /12 net-_u1-pad2_ ? ? net-_u10-pad1_ net-_u17-pad1_ d_dff
+* u10 net-_u10-pad1_ net-_u1-pad2_ ? ? ? net-_u10-pad6_ d_dff
+* u13 net-_u13-pad1_ net-_u11-pad2_ /5 d_nor
+* u14 net-_u11-pad2_ net-_u14-pad2_ /4 d_nor
+* u15 net-_u15-pad1_ net-_u11-pad2_ /10 d_nor
+* u16 net-_u11-pad2_ net-_u16-pad2_ /11 d_nor
+* u11 net-_u11-pad1_ net-_u11-pad2_ /2 d_nor
+* u12 net-_u11-pad2_ net-_u12-pad2_ /1 d_nor
+* u17 net-_u17-pad1_ net-_u11-pad2_ /13 d_nor
+* u18 net-_u11-pad2_ net-_u10-pad6_ /14 d_nor
+* u2 /15 net-_u11-pad2_ d_buffer
+* u1 /7 net-_u1-pad2_ d_inverter
+* u19 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? port
+a1 /3 net-_u1-pad2_ ? ? net-_u3-pad5_ net-_u11-pad1_ u3
+a2 net-_u3-pad5_ net-_u1-pad2_ ? ? ? net-_u12-pad2_ u7
+a3 /6 net-_u1-pad2_ ? ? net-_u4-pad5_ net-_u13-pad1_ u4
+a4 net-_u4-pad5_ net-_u1-pad2_ ? ? ? net-_u14-pad2_ u8
+a5 /9 net-_u1-pad2_ ? ? net-_u5-pad5_ net-_u15-pad1_ u5
+a6 net-_u5-pad5_ net-_u1-pad2_ ? ? ? net-_u16-pad2_ u9
+a7 /12 net-_u1-pad2_ ? ? net-_u10-pad1_ net-_u17-pad1_ u6
+a8 net-_u10-pad1_ net-_u1-pad2_ ? ? ? net-_u10-pad6_ u10
+a9 [net-_u13-pad1_ net-_u11-pad2_ ] /5 u13
+a10 [net-_u11-pad2_ net-_u14-pad2_ ] /4 u14
+a11 [net-_u15-pad1_ net-_u11-pad2_ ] /10 u15
+a12 [net-_u11-pad2_ net-_u16-pad2_ ] /11 u16
+a13 [net-_u11-pad1_ net-_u11-pad2_ ] /2 u11
+a14 [net-_u11-pad2_ net-_u12-pad2_ ] /1 u12
+a15 [net-_u17-pad1_ net-_u11-pad2_ ] /13 u17
+a16 [net-_u11-pad2_ net-_u10-pad6_ ] /14 u18
+a17 /15 net-_u11-pad2_ u2
+a18 /7 net-_u1-pad2_ u1
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.pro b/library/SubcircuitLibrary/SN74LS396/SN74LS396.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.sch b/library/SubcircuitLibrary/SN74LS396/SN74LS396.sch
new file mode 100644
index 000000000..e57cf239c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.sch
@@ -0,0 +1,629 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74LS396-cache
+EELAYER 25 0
+EELAYER END
+$Descr A3 16535 11693
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U3
+U 1 1 684A98AA
+P 5150 2550
+F 0 "U3" H 5150 2550 60 0000 C CNN
+F 1 "d_dff" H 5150 2700 60 0000 C CNN
+F 2 "" H 5150 2550 60 0000 C CNN
+F 3 "" H 5150 2550 60 0000 C CNN
+ 1 5150 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U7
+U 1 1 684A99B9
+P 6950 2550
+F 0 "U7" H 6950 2550 60 0000 C CNN
+F 1 "d_dff" H 6950 2700 60 0000 C CNN
+F 2 "" H 6950 2550 60 0000 C CNN
+F 3 "" H 6950 2550 60 0000 C CNN
+ 1 6950 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U4
+U 1 1 684A9B41
+P 5150 4200
+F 0 "U4" H 5150 4200 60 0000 C CNN
+F 1 "d_dff" H 5150 4350 60 0000 C CNN
+F 2 "" H 5150 4200 60 0000 C CNN
+F 3 "" H 5150 4200 60 0000 C CNN
+ 1 5150 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U8
+U 1 1 684A9B47
+P 6950 4200
+F 0 "U8" H 6950 4200 60 0000 C CNN
+F 1 "d_dff" H 6950 4350 60 0000 C CNN
+F 2 "" H 6950 4200 60 0000 C CNN
+F 3 "" H 6950 4200 60 0000 C CNN
+ 1 6950 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U5
+U 1 1 684A9BF1
+P 5150 5850
+F 0 "U5" H 5150 5850 60 0000 C CNN
+F 1 "d_dff" H 5150 6000 60 0000 C CNN
+F 2 "" H 5150 5850 60 0000 C CNN
+F 3 "" H 5150 5850 60 0000 C CNN
+ 1 5150 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U9
+U 1 1 684A9BF7
+P 6950 5850
+F 0 "U9" H 6950 5850 60 0000 C CNN
+F 1 "d_dff" H 6950 6000 60 0000 C CNN
+F 2 "" H 6950 5850 60 0000 C CNN
+F 3 "" H 6950 5850 60 0000 C CNN
+ 1 6950 5850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U6
+U 1 1 684A9BFD
+P 5150 7500
+F 0 "U6" H 5150 7500 60 0000 C CNN
+F 1 "d_dff" H 5150 7650 60 0000 C CNN
+F 2 "" H 5150 7500 60 0000 C CNN
+F 3 "" H 5150 7500 60 0000 C CNN
+ 1 5150 7500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U10
+U 1 1 684A9C03
+P 6950 7500
+F 0 "U10" H 6950 7500 60 0000 C CNN
+F 1 "d_dff" H 6950 7650 60 0000 C CNN
+F 2 "" H 6950 7500 60 0000 C CNN
+F 3 "" H 6950 7500 60 0000 C CNN
+ 1 6950 7500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U13
+U 1 1 684AAC31
+P 8750 3900
+F 0 "U13" H 8750 3900 60 0000 C CNN
+F 1 "d_nor" H 8800 4000 60 0000 C CNN
+F 2 "" H 8750 3900 60 0000 C CNN
+F 3 "" H 8750 3900 60 0000 C CNN
+ 1 8750 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U14
+U 1 1 684AACB6
+P 8750 4450
+F 0 "U14" H 8750 4450 60 0000 C CNN
+F 1 "d_nor" H 8800 4550 60 0000 C CNN
+F 2 "" H 8750 4450 60 0000 C CNN
+F 3 "" H 8750 4450 60 0000 C CNN
+ 1 8750 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U15
+U 1 1 684AAD2A
+P 8750 5600
+F 0 "U15" H 8750 5600 60 0000 C CNN
+F 1 "d_nor" H 8800 5700 60 0000 C CNN
+F 2 "" H 8750 5600 60 0000 C CNN
+F 3 "" H 8750 5600 60 0000 C CNN
+ 1 8750 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U16
+U 1 1 684AAD30
+P 8750 6150
+F 0 "U16" H 8750 6150 60 0000 C CNN
+F 1 "d_nor" H 8800 6250 60 0000 C CNN
+F 2 "" H 8750 6150 60 0000 C CNN
+F 3 "" H 8750 6150 60 0000 C CNN
+ 1 8750 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U11
+U 1 1 684AB218
+P 8700 2350
+F 0 "U11" H 8700 2350 60 0000 C CNN
+F 1 "d_nor" H 8750 2450 60 0000 C CNN
+F 2 "" H 8700 2350 60 0000 C CNN
+F 3 "" H 8700 2350 60 0000 C CNN
+ 1 8700 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U12
+U 1 1 684AB21E
+P 8700 2900
+F 0 "U12" H 8700 2900 60 0000 C CNN
+F 1 "d_nor" H 8750 3000 60 0000 C CNN
+F 2 "" H 8700 2900 60 0000 C CNN
+F 3 "" H 8700 2900 60 0000 C CNN
+ 1 8700 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U17
+U 1 1 684AC196
+P 8750 7250
+F 0 "U17" H 8750 7250 60 0000 C CNN
+F 1 "d_nor" H 8800 7350 60 0000 C CNN
+F 2 "" H 8750 7250 60 0000 C CNN
+F 3 "" H 8750 7250 60 0000 C CNN
+ 1 8750 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U18
+U 1 1 684AC19C
+P 8750 7800
+F 0 "U18" H 8750 7800 60 0000 C CNN
+F 1 "d_nor" H 8800 7900 60 0000 C CNN
+F 2 "" H 8750 7800 60 0000 C CNN
+F 3 "" H 8750 7800 60 0000 C CNN
+ 1 8750 7800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U2
+U 1 1 684AE615
+P 5050 8500
+F 0 "U2" H 5050 8450 60 0000 C CNN
+F 1 "d_buffer" H 5050 8550 60 0000 C CNN
+F 2 "" H 5050 8500 60 0000 C CNN
+F 3 "" H 5050 8500 60 0000 C CNN
+ 1 5050 8500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U1
+U 1 1 684B1ED3
+P 4000 1800
+F 0 "U1" H 4000 1700 60 0000 C CNN
+F 1 "d_inverter" H 4000 1950 60 0000 C CNN
+F 2 "" H 4050 1750 60 0000 C CNN
+F 3 "" H 4050 1750 60 0000 C CNN
+ 1 4000 1800
+ 1 0 0 -1
+$EndComp
+NoConn ~ 5150 1900
+NoConn ~ 5150 3150
+NoConn ~ 5150 3550
+NoConn ~ 5150 4800
+NoConn ~ 5150 5200
+NoConn ~ 5150 6450
+NoConn ~ 5150 6850
+NoConn ~ 5150 8100
+NoConn ~ 6950 8100
+NoConn ~ 6950 6850
+NoConn ~ 6950 6450
+NoConn ~ 6950 5200
+NoConn ~ 6950 4800
+NoConn ~ 6950 3550
+NoConn ~ 6950 1900
+NoConn ~ 6950 3150
+Text Label 3600 1800 0 60 ~ 0
+7
+Text Label 3950 2200 0 60 ~ 0
+3
+Text Label 4100 3850 0 60 ~ 0
+6
+Text Label 4150 5500 0 60 ~ 0
+9
+Text Label 4200 7150 0 60 ~ 0
+12
+Text Label 4100 8500 0 60 ~ 0
+15
+Text Label 9600 7750 0 60 ~ 0
+14
+Text Label 9550 7200 0 60 ~ 0
+13
+Text Label 9550 6100 0 60 ~ 0
+11
+Text Label 9550 5550 0 60 ~ 0
+10
+Text Label 9650 4400 0 60 ~ 0
+4
+Text Label 9600 3850 0 60 ~ 0
+5
+Text Label 9700 2850 0 60 ~ 0
+1
+Text Label 9700 2300 0 60 ~ 0
+2
+Wire Wire Line
+ 5700 3850 6400 3850
+Wire Wire Line
+ 5700 2200 6400 2200
+Wire Wire Line
+ 5700 5500 6400 5500
+Wire Wire Line
+ 5700 7150 6400 7150
+Wire Wire Line
+ 5700 2850 6050 2850
+Wire Wire Line
+ 6050 2850 6050 1750
+Wire Wire Line
+ 6050 1750 8000 1750
+Wire Wire Line
+ 8000 1750 8000 2250
+Wire Wire Line
+ 8000 2250 8250 2250
+Wire Wire Line
+ 7500 2850 7800 2850
+Wire Wire Line
+ 7800 2850 7800 2900
+Wire Wire Line
+ 7800 2900 8250 2900
+Wire Wire Line
+ 5700 4500 6000 4500
+Wire Wire Line
+ 6000 4500 6000 3400
+Wire Wire Line
+ 6000 3400 8000 3400
+Wire Wire Line
+ 8000 3400 8000 3800
+Wire Wire Line
+ 8000 3800 8300 3800
+Wire Wire Line
+ 7500 4500 8200 4500
+Wire Wire Line
+ 8200 4500 8200 4450
+Wire Wire Line
+ 8200 4450 8300 4450
+Wire Wire Line
+ 5700 6150 5950 6150
+Wire Wire Line
+ 5950 6150 5950 5000
+Wire Wire Line
+ 5950 5000 8000 5000
+Wire Wire Line
+ 8000 5000 8000 5500
+Wire Wire Line
+ 8000 5500 8300 5500
+Wire Wire Line
+ 7500 6150 8300 6150
+Wire Wire Line
+ 5700 7800 5950 7800
+Wire Wire Line
+ 5950 7800 5950 6700
+Wire Wire Line
+ 5950 6700 8050 6700
+Wire Wire Line
+ 8050 6700 8050 7150
+Wire Wire Line
+ 8050 7150 8300 7150
+Wire Wire Line
+ 7500 7800 8300 7800
+Wire Wire Line
+ 7850 8500 5700 8500
+Wire Wire Line
+ 7850 2350 7850 8500
+Wire Wire Line
+ 7850 2350 8250 2350
+Wire Wire Line
+ 8250 2800 7850 2800
+Connection ~ 7850 2800
+Wire Wire Line
+ 8300 3900 7850 3900
+Connection ~ 7850 3900
+Wire Wire Line
+ 8300 4350 7850 4350
+Connection ~ 7850 4350
+Wire Wire Line
+ 8300 5600 7850 5600
+Connection ~ 7850 5600
+Wire Wire Line
+ 8300 6050 7850 6050
+Connection ~ 7850 6050
+Wire Wire Line
+ 8300 7700 7850 7700
+Connection ~ 7850 7700
+Wire Wire Line
+ 8300 7250 7850 7250
+Connection ~ 7850 7250
+Wire Wire Line
+ 4550 8500 4100 8500
+Wire Wire Line
+ 4300 1800 6150 1800
+Wire Wire Line
+ 4350 1800 4350 7800
+Wire Wire Line
+ 4350 2850 4600 2850
+Wire Wire Line
+ 4350 4500 4600 4500
+Connection ~ 4350 2850
+Wire Wire Line
+ 4350 6150 4600 6150
+Connection ~ 4350 4500
+Wire Wire Line
+ 4350 7800 4600 7800
+Connection ~ 4350 6150
+Wire Wire Line
+ 6150 1800 6150 7800
+Wire Wire Line
+ 6150 2850 6400 2850
+Connection ~ 4350 1800
+Wire Wire Line
+ 6150 4500 6400 4500
+Connection ~ 6150 2850
+Wire Wire Line
+ 6150 6150 6400 6150
+Connection ~ 6150 4500
+Wire Wire Line
+ 6150 7800 6400 7800
+Connection ~ 6150 6150
+Wire Wire Line
+ 4600 2200 3950 2200
+Wire Wire Line
+ 4600 3850 4100 3850
+Wire Wire Line
+ 4600 5500 4150 5500
+Wire Wire Line
+ 4600 7150 4200 7150
+Wire Wire Line
+ 3700 1800 3600 1800
+Wire Wire Line
+ 9200 7750 9600 7750
+Wire Wire Line
+ 9200 7200 9550 7200
+Wire Wire Line
+ 9200 6100 9550 6100
+Wire Wire Line
+ 9200 5550 9550 5550
+Wire Wire Line
+ 9200 4400 9650 4400
+Wire Wire Line
+ 9200 3850 9600 3850
+Wire Wire Line
+ 9150 2850 9700 2850
+Wire Wire Line
+ 9150 2300 9700 2300
+$Comp
+L PORT U19
+U 2 1 684C29D5
+P 9950 2300
+F 0 "U19" H 10000 2400 30 0000 C CNN
+F 1 "PORT" H 9950 2300 30 0000 C CNN
+F 2 "" H 9950 2300 60 0000 C CNN
+F 3 "" H 9950 2300 60 0000 C CNN
+ 2 9950 2300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U19
+U 8 1 684C2A2E
+P 3650 4600
+F 0 "U19" H 3700 4700 30 0000 C CNN
+F 1 "PORT" H 3650 4600 30 0000 C CNN
+F 2 "" H 3650 4600 60 0000 C CNN
+F 3 "" H 3650 4600 60 0000 C CNN
+ 8 3650 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 15 1 684C2A6B
+P 3850 8500
+F 0 "U19" H 3900 8600 30 0000 C CNN
+F 1 "PORT" H 3850 8500 30 0000 C CNN
+F 2 "" H 3850 8500 60 0000 C CNN
+F 3 "" H 3850 8500 60 0000 C CNN
+ 15 3850 8500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 3 1 684C2ABA
+P 3700 2200
+F 0 "U19" H 3750 2300 30 0000 C CNN
+F 1 "PORT" H 3700 2200 30 0000 C CNN
+F 2 "" H 3700 2200 60 0000 C CNN
+F 3 "" H 3700 2200 60 0000 C CNN
+ 3 3700 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 9 1 684C2B03
+P 3900 5500
+F 0 "U19" H 3950 5600 30 0000 C CNN
+F 1 "PORT" H 3900 5500 30 0000 C CNN
+F 2 "" H 3900 5500 60 0000 C CNN
+F 3 "" H 3900 5500 60 0000 C CNN
+ 9 3900 5500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 13 1 684C2B46
+P 9800 7200
+F 0 "U19" H 9850 7300 30 0000 C CNN
+F 1 "PORT" H 9800 7200 30 0000 C CNN
+F 2 "" H 9800 7200 60 0000 C CNN
+F 3 "" H 9800 7200 60 0000 C CNN
+ 13 9800 7200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U19
+U 1 1 684C2B8B
+P 9950 2850
+F 0 "U19" H 10000 2950 30 0000 C CNN
+F 1 "PORT" H 9950 2850 30 0000 C CNN
+F 2 "" H 9950 2850 60 0000 C CNN
+F 3 "" H 9950 2850 60 0000 C CNN
+ 1 9950 2850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U19
+U 7 1 684C2BD2
+P 3350 1800
+F 0 "U19" H 3400 1900 30 0000 C CNN
+F 1 "PORT" H 3350 1800 30 0000 C CNN
+F 2 "" H 3350 1800 60 0000 C CNN
+F 3 "" H 3350 1800 60 0000 C CNN
+ 7 3350 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 14 1 684C2C1B
+P 9850 7750
+F 0 "U19" H 9900 7850 30 0000 C CNN
+F 1 "PORT" H 9850 7750 30 0000 C CNN
+F 2 "" H 9850 7750 60 0000 C CNN
+F 3 "" H 9850 7750 60 0000 C CNN
+ 14 9850 7750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U19
+U 5 1 684C2C66
+P 9850 3850
+F 0 "U19" H 9900 3950 30 0000 C CNN
+F 1 "PORT" H 9850 3850 30 0000 C CNN
+F 2 "" H 9850 3850 60 0000 C CNN
+F 3 "" H 9850 3850 60 0000 C CNN
+ 5 9850 3850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U19
+U 11 1 684C2CB3
+P 9800 6100
+F 0 "U19" H 9850 6200 30 0000 C CNN
+F 1 "PORT" H 9800 6100 30 0000 C CNN
+F 2 "" H 9800 6100 60 0000 C CNN
+F 3 "" H 9800 6100 60 0000 C CNN
+ 11 9800 6100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U19
+U 16 1 684C2D1A
+P 3650 4850
+F 0 "U19" H 3700 4950 30 0000 C CNN
+F 1 "PORT" H 3650 4850 30 0000 C CNN
+F 2 "" H 3650 4850 60 0000 C CNN
+F 3 "" H 3650 4850 60 0000 C CNN
+ 16 3650 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 4 1 684C2D6D
+P 9900 4400
+F 0 "U19" H 9950 4500 30 0000 C CNN
+F 1 "PORT" H 9900 4400 30 0000 C CNN
+F 2 "" H 9900 4400 60 0000 C CNN
+F 3 "" H 9900 4400 60 0000 C CNN
+ 4 9900 4400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U19
+U 10 1 684C2DC0
+P 9800 5550
+F 0 "U19" H 9850 5650 30 0000 C CNN
+F 1 "PORT" H 9800 5550 30 0000 C CNN
+F 2 "" H 9800 5550 60 0000 C CNN
+F 3 "" H 9800 5550 60 0000 C CNN
+ 10 9800 5550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U19
+U 12 1 684C2E15
+P 3950 7150
+F 0 "U19" H 4000 7250 30 0000 C CNN
+F 1 "PORT" H 3950 7150 30 0000 C CNN
+F 2 "" H 3950 7150 60 0000 C CNN
+F 3 "" H 3950 7150 60 0000 C CNN
+ 12 3950 7150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U19
+U 6 1 684C2E6C
+P 3850 3850
+F 0 "U19" H 3900 3950 30 0000 C CNN
+F 1 "PORT" H 3850 3850 30 0000 C CNN
+F 2 "" H 3850 3850 60 0000 C CNN
+F 3 "" H 3850 3850 60 0000 C CNN
+ 6 3850 3850
+ 1 0 0 -1
+$EndComp
+NoConn ~ 3900 4850
+NoConn ~ 3900 4600
+NoConn ~ 7500 5500
+NoConn ~ 7500 7150
+NoConn ~ 7500 3850
+NoConn ~ 7500 2200
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396.sub b/library/SubcircuitLibrary/SN74LS396/SN74LS396.sub
new file mode 100644
index 000000000..e779a1b26
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396.sub
@@ -0,0 +1,78 @@
+* Subcircuit SN74LS396
+.subckt SN74LS396 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ?
+* d:\fossee\esim\library\subcircuitlibrary\sn74ls396\sn74ls396.cir
+* u3 /3 net-_u1-pad2_ ? ? net-_u3-pad5_ net-_u11-pad1_ d_dff
+* u7 net-_u3-pad5_ net-_u1-pad2_ ? ? ? net-_u12-pad2_ d_dff
+* u4 /6 net-_u1-pad2_ ? ? net-_u4-pad5_ net-_u13-pad1_ d_dff
+* u8 net-_u4-pad5_ net-_u1-pad2_ ? ? ? net-_u14-pad2_ d_dff
+* u5 /9 net-_u1-pad2_ ? ? net-_u5-pad5_ net-_u15-pad1_ d_dff
+* u9 net-_u5-pad5_ net-_u1-pad2_ ? ? ? net-_u16-pad2_ d_dff
+* u6 /12 net-_u1-pad2_ ? ? net-_u10-pad1_ net-_u17-pad1_ d_dff
+* u10 net-_u10-pad1_ net-_u1-pad2_ ? ? ? net-_u10-pad6_ d_dff
+* u13 net-_u13-pad1_ net-_u11-pad2_ /5 d_nor
+* u14 net-_u11-pad2_ net-_u14-pad2_ /4 d_nor
+* u15 net-_u15-pad1_ net-_u11-pad2_ /10 d_nor
+* u16 net-_u11-pad2_ net-_u16-pad2_ /11 d_nor
+* u11 net-_u11-pad1_ net-_u11-pad2_ /2 d_nor
+* u12 net-_u11-pad2_ net-_u12-pad2_ /1 d_nor
+* u17 net-_u17-pad1_ net-_u11-pad2_ /13 d_nor
+* u18 net-_u11-pad2_ net-_u10-pad6_ /14 d_nor
+* u2 /15 net-_u11-pad2_ d_buffer
+* u1 /7 net-_u1-pad2_ d_inverter
+a1 /3 net-_u1-pad2_ ? ? net-_u3-pad5_ net-_u11-pad1_ u3
+a2 net-_u3-pad5_ net-_u1-pad2_ ? ? ? net-_u12-pad2_ u7
+a3 /6 net-_u1-pad2_ ? ? net-_u4-pad5_ net-_u13-pad1_ u4
+a4 net-_u4-pad5_ net-_u1-pad2_ ? ? ? net-_u14-pad2_ u8
+a5 /9 net-_u1-pad2_ ? ? net-_u5-pad5_ net-_u15-pad1_ u5
+a6 net-_u5-pad5_ net-_u1-pad2_ ? ? ? net-_u16-pad2_ u9
+a7 /12 net-_u1-pad2_ ? ? net-_u10-pad1_ net-_u17-pad1_ u6
+a8 net-_u10-pad1_ net-_u1-pad2_ ? ? ? net-_u10-pad6_ u10
+a9 [net-_u13-pad1_ net-_u11-pad2_ ] /5 u13
+a10 [net-_u11-pad2_ net-_u14-pad2_ ] /4 u14
+a11 [net-_u15-pad1_ net-_u11-pad2_ ] /10 u15
+a12 [net-_u11-pad2_ net-_u16-pad2_ ] /11 u16
+a13 [net-_u11-pad1_ net-_u11-pad2_ ] /2 u11
+a14 [net-_u11-pad2_ net-_u12-pad2_ ] /1 u12
+a15 [net-_u17-pad1_ net-_u11-pad2_ ] /13 u17
+a16 [net-_u11-pad2_ net-_u10-pad6_ ] /14 u18
+a17 /15 net-_u11-pad2_ u2
+a18 /7 net-_u1-pad2_ u1
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u9 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u6 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u10 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u2 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74LS396
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS396/SN74LS396_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS396/SN74LS396_Previous_Values.xml
new file mode 100644
index 000000000..15ef74423
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS396/SN74LS396_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_dffd_nord_nord_nord_nord_nord_nord_nord_nord_bufferd_inverter
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS396/analysis b/library/SubcircuitLibrary/SN74LS396/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS396/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR-cache.lib b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.cir b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.cir
new file mode 100644
index 000000000..798338152
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.cir
@@ -0,0 +1,14 @@
+* H:\esim\eSim\library\SubcircuitLibrary\CMOS_INVTR\CMOS_INVTR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/12/25 16:02:08
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.cir.out b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.cir.out
new file mode 100644
index 000000000..268de8701
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.cir.out
@@ -0,0 +1,16 @@
+* h:\esim\esim\library\subcircuitlibrary\cmos_invtr\cmos_invtr.cir
+
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.pro b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.sch b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.sch
new file mode 100644
index 000000000..aa7a7ee81
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.sch
@@ -0,0 +1,161 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 684B982F
+P 5350 2950
+F 0 "SC1" H 5400 3250 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5650 3037 50 0000 R CNN
+F 2 "" H 5350 1450 50 0001 C CNN
+F 3 "" H 5350 2950 50 0001 C CNN
+ 1 5350 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 684B9856
+P 5350 3800
+F 0 "SC2" H 5400 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5650 3887 50 0000 R CNN
+F 2 "" H 5350 2300 50 0001 C CNN
+F 3 "" H 5350 3800 50 0001 C CNN
+ 1 5350 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684B98AD
+P 4550 3300
+F 0 "U1" H 4600 3400 30 0000 C CNN
+F 1 "PORT" H 4550 3300 30 0000 C CNN
+F 2 "" H 4550 3300 60 0000 C CNN
+F 3 "" H 4550 3300 60 0000 C CNN
+ 1 4550 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684B98D8
+P 6300 3350
+F 0 "U1" H 6350 3450 30 0000 C CNN
+F 1 "PORT" H 6300 3350 30 0000 C CNN
+F 2 "" H 6300 3350 60 0000 C CNN
+F 3 "" H 6300 3350 60 0000 C CNN
+ 4 6300 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684B9935
+P 5300 4350
+F 0 "U1" H 5350 4450 30 0000 C CNN
+F 1 "PORT" H 5300 4350 30 0000 C CNN
+F 2 "" H 5300 4350 60 0000 C CNN
+F 3 "" H 5300 4350 60 0000 C CNN
+ 3 5300 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684B999A
+P 5300 2350
+F 0 "U1" H 5350 2450 30 0000 C CNN
+F 1 "PORT" H 5300 2350 30 0000 C CNN
+F 2 "" H 5300 2350 60 0000 C CNN
+F 3 "" H 5300 2350 60 0000 C CNN
+ 2 5300 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 684B99CD
+P 7950 3000
+F 0 "scmode1" H 7950 3150 98 0000 C CNB
+F 1 "SKY130mode" H 7950 2900 118 0000 C CNB
+F 2 "" H 7950 3150 60 0001 C CNN
+F 3 "" H 7950 3150 60 0001 C CNN
+ 1 7950 3000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5550 2650 5550 2350
+Wire Wire Line
+ 5450 2950 5600 2950
+Wire Wire Line
+ 5600 2950 5600 2550
+Wire Wire Line
+ 5600 2550 5550 2550
+Connection ~ 5550 2550
+Wire Wire Line
+ 5550 3250 5550 3500
+Wire Wire Line
+ 6050 3350 5550 3350
+Connection ~ 5550 3350
+Wire Wire Line
+ 5050 2950 5050 3800
+Wire Wire Line
+ 4800 3300 5050 3300
+Connection ~ 5050 3300
+Wire Wire Line
+ 5450 3800 5600 3800
+Wire Wire Line
+ 5600 3800 5600 4150
+Wire Wire Line
+ 5600 4150 5550 4150
+Wire Wire Line
+ 5550 4100 5550 4350
+Connection ~ 5550 4150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.sub b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.sub
new file mode 100644
index 000000000..dfe6de3e5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR.sub
@@ -0,0 +1,10 @@
+* Subcircuit CMOS_INVTR
+.subckt CMOS_INVTR net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc1-pad1_
+* h:\esim\esim\library\subcircuitlibrary\cmos_invtr\cmos_invtr.cir
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends CMOS_INVTR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR_Previous_Values.xml
new file mode 100644
index 000000000..af4904616
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/CMOS_INVTR_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettw=3 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/DFF_CE-cache.lib b/library/SubcircuitLibrary/SN74LS548/DFF_CE-cache.lib
new file mode 100644
index 000000000..8f800f53f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/DFF_CE-cache.lib
@@ -0,0 +1,103 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# D_FF
+#
+DEF D_FF X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "D_FF" 50 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -250 200 300 -200 0 1 0 N
+X D 1 -450 50 200 R 50 50 1 1 I
+X CLK 2 -450 -50 200 R 50 50 1 1 I
+X VDD 3 -450 150 200 R 50 50 1 1 I
+X GND 4 -450 -150 200 R 50 50 1 1 I
+X OUT 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/DFF_CE-rescue.lib b/library/SubcircuitLibrary/SN74LS548/DFF_CE-rescue.lib
new file mode 100644
index 000000000..970123cab
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/DFF_CE-rescue.lib
@@ -0,0 +1,21 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# D_FF-RESCUE-DFF_CE
+#
+DEF D_FF-RESCUE-DFF_CE X 0 40 Y Y 1 F N
+F0 "X" 100 100 60 H V C CNN
+F1 "D_FF-RESCUE-DFF_CE" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -200 200 200 -150 0 1 0 N
+X D 1 -400 50 200 R 50 50 1 1 I
+X Clk 2 -400 -50 200 R 50 50 1 1 I
+X Vdd 3 0 400 200 D 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X Q 5 400 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/DFF_CE.bak b/library/SubcircuitLibrary/SN74LS548/DFF_CE.bak
new file mode 100644
index 000000000..749dc6a77
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/DFF_CE.bak
@@ -0,0 +1,172 @@
+EESchema Schematic File Version 2
+LIBS:DFF_CE-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DFF_CE-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 68712618
+P 4750 2800
+F 0 "SC1" H 4800 3100 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5050 2887 50 0000 R CNN
+F 2 "" H 4750 1300 50 0001 C CNN
+F 3 "" H 4750 2800 50 0001 C CNN
+ 1 4750 2800
+ 0 -1 1 0
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 6871269E
+P 9750 3750
+F 0 "scmode1" H 9750 3900 98 0000 C CNB
+F 1 "SKY130mode" H 9750 3650 118 0000 C CNB
+F 2 "" H 9750 3900 60 0001 C CNN
+F 3 "" H 9750 3900 60 0001 C CNN
+ 1 9750 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 687126DC
+P 4200 3050
+F 0 "U1" H 4250 3150 30 0000 C CNN
+F 1 "PORT" H 4200 3050 30 0000 C CNN
+F 2 "" H 4200 3050 60 0000 C CNN
+F 3 "" H 4200 3050 60 0000 C CNN
+ 1 4200 3050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4750 2900 4750 3050
+Wire Wire Line
+ 4750 3050 4450 3050
+Wire Wire Line
+ 4450 3050 4450 3000
+Connection ~ 4450 3050
+$Comp
+L PORT U1
+U 3 1 687127CB
+P 5000 2300
+F 0 "U1" H 5050 2400 30 0000 C CNN
+F 1 "PORT" H 5000 2300 30 0000 C CNN
+F 2 "" H 5000 2300 60 0000 C CNN
+F 3 "" H 5000 2300 60 0000 C CNN
+ 3 5000 2300
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68712813
+P 4500 2500
+F 0 "U1" H 4550 2600 30 0000 C CNN
+F 1 "PORT" H 4500 2500 30 0000 C CNN
+F 2 "" H 4500 2500 60 0000 C CNN
+F 3 "" H 4500 2500 60 0000 C CNN
+ 2 4500 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6871285A
+P 5300 2650
+F 0 "U1" H 5350 2750 30 0000 C CNN
+F 1 "PORT" H 5300 2650 30 0000 C CNN
+F 2 "" H 5300 2650 60 0000 C CNN
+F 3 "" H 5300 2650 60 0000 C CNN
+ 4 5300 2650
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 687128A1
+P 5300 3250
+F 0 "U1" H 5350 3350 30 0000 C CNN
+F 1 "PORT" H 5300 3250 30 0000 C CNN
+F 2 "" H 5300 3250 60 0000 C CNN
+F 3 "" H 5300 3250 60 0000 C CNN
+ 5 5300 3250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 687128DA
+P 6250 2950
+F 0 "U1" H 6300 3050 30 0000 C CNN
+F 1 "PORT" H 6250 2950 30 0000 C CNN
+F 2 "" H 6250 2950 60 0000 C CNN
+F 3 "" H 6250 2950 60 0000 C CNN
+ 6 6250 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_FF X1
+U 1 1 6877C57A
+P 5500 2950
+F 0 "X1" H 5500 2950 60 0000 C CNN
+F 1 "D_FF" H 5550 2700 60 0000 C CNN
+F 2 "" H 5500 2950 60 0001 C CNN
+F 3 "" H 5500 2950 60 0001 C CNN
+ 1 5500 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5050 2650 5050 2800
+Wire Wire Line
+ 5000 2550 5000 2900
+Wire Wire Line
+ 5000 2900 5050 2900
+Wire Wire Line
+ 5050 3250 5050 3100
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/DFF_CE.cir b/library/SubcircuitLibrary/SN74LS548/DFF_CE.cir
new file mode 100644
index 000000000..bdc89679c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/DFF_CE.cir
@@ -0,0 +1,14 @@
+* H:\esim\eSim\library\SubcircuitLibrary\DFF_CE\DFF_CE.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/16/25 20:58:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+scmode1 SKY130mode
+U1 Net-_SC1-Pad3_ Net-_SC1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT
+X1 Net-_U1-Pad3_ Net-_SC1-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ D_FF
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/DFF_CE.cir.out b/library/SubcircuitLibrary/SN74LS548/DFF_CE.cir.out
new file mode 100644
index 000000000..227f8666c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/DFF_CE.cir.out
@@ -0,0 +1,17 @@
+* h:\esim\esim\library\subcircuitlibrary\dff_ce\dff_ce.cir
+
+.include D_FF.sub
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+* s c m o d e
+* u1 net-_sc1-pad3_ net-_sc1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port
+x1 net-_u1-pad3_ net-_sc1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ D_FF
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/DFF_CE.pro b/library/SubcircuitLibrary/SN74LS548/DFF_CE.pro
new file mode 100644
index 000000000..0cac01afd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/DFF_CE.pro
@@ -0,0 +1,74 @@
+update=07/16/25 20:56:16
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=DFF_CE-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS548/DFF_CE.sch b/library/SubcircuitLibrary/SN74LS548/DFF_CE.sch
new file mode 100644
index 000000000..749dc6a77
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/DFF_CE.sch
@@ -0,0 +1,172 @@
+EESchema Schematic File Version 2
+LIBS:DFF_CE-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DFF_CE-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 68712618
+P 4750 2800
+F 0 "SC1" H 4800 3100 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5050 2887 50 0000 R CNN
+F 2 "" H 4750 1300 50 0001 C CNN
+F 3 "" H 4750 2800 50 0001 C CNN
+ 1 4750 2800
+ 0 -1 1 0
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 6871269E
+P 9750 3750
+F 0 "scmode1" H 9750 3900 98 0000 C CNB
+F 1 "SKY130mode" H 9750 3650 118 0000 C CNB
+F 2 "" H 9750 3900 60 0001 C CNN
+F 3 "" H 9750 3900 60 0001 C CNN
+ 1 9750 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 687126DC
+P 4200 3050
+F 0 "U1" H 4250 3150 30 0000 C CNN
+F 1 "PORT" H 4200 3050 30 0000 C CNN
+F 2 "" H 4200 3050 60 0000 C CNN
+F 3 "" H 4200 3050 60 0000 C CNN
+ 1 4200 3050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4750 2900 4750 3050
+Wire Wire Line
+ 4750 3050 4450 3050
+Wire Wire Line
+ 4450 3050 4450 3000
+Connection ~ 4450 3050
+$Comp
+L PORT U1
+U 3 1 687127CB
+P 5000 2300
+F 0 "U1" H 5050 2400 30 0000 C CNN
+F 1 "PORT" H 5000 2300 30 0000 C CNN
+F 2 "" H 5000 2300 60 0000 C CNN
+F 3 "" H 5000 2300 60 0000 C CNN
+ 3 5000 2300
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68712813
+P 4500 2500
+F 0 "U1" H 4550 2600 30 0000 C CNN
+F 1 "PORT" H 4500 2500 30 0000 C CNN
+F 2 "" H 4500 2500 60 0000 C CNN
+F 3 "" H 4500 2500 60 0000 C CNN
+ 2 4500 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6871285A
+P 5300 2650
+F 0 "U1" H 5350 2750 30 0000 C CNN
+F 1 "PORT" H 5300 2650 30 0000 C CNN
+F 2 "" H 5300 2650 60 0000 C CNN
+F 3 "" H 5300 2650 60 0000 C CNN
+ 4 5300 2650
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 687128A1
+P 5300 3250
+F 0 "U1" H 5350 3350 30 0000 C CNN
+F 1 "PORT" H 5300 3250 30 0000 C CNN
+F 2 "" H 5300 3250 60 0000 C CNN
+F 3 "" H 5300 3250 60 0000 C CNN
+ 5 5300 3250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 687128DA
+P 6250 2950
+F 0 "U1" H 6300 3050 30 0000 C CNN
+F 1 "PORT" H 6250 2950 30 0000 C CNN
+F 2 "" H 6250 2950 60 0000 C CNN
+F 3 "" H 6250 2950 60 0000 C CNN
+ 6 6250 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L D_FF X1
+U 1 1 6877C57A
+P 5500 2950
+F 0 "X1" H 5500 2950 60 0000 C CNN
+F 1 "D_FF" H 5550 2700 60 0000 C CNN
+F 2 "" H 5500 2950 60 0001 C CNN
+F 3 "" H 5500 2950 60 0001 C CNN
+ 1 5500 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5050 2650 5050 2800
+Wire Wire Line
+ 5000 2550 5000 2900
+Wire Wire Line
+ 5000 2900 5050 2900
+Wire Wire Line
+ 5050 3250 5050 3100
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/DFF_CE.sub b/library/SubcircuitLibrary/SN74LS548/DFF_CE.sub
new file mode 100644
index 000000000..4bb98577f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/DFF_CE.sub
@@ -0,0 +1,10 @@
+* Subcircuit DFF_CE
+.subckt DFF_CE net-_sc1-pad3_ net-_sc1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_
+* h:\esim\esim\library\subcircuitlibrary\dff_ce\dff_ce.cir
+.include D_FF.sub
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+* s c m o d e
+x1 net-_u1-pad3_ net-_sc1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ D_FF
+* Control Statements
+
+.ends DFF_CE
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/DFF_CE_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS548/DFF_CE_Previous_Values.xml
new file mode 100644
index 000000000..21a8422bd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/DFF_CE_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettw=3 l=0.15H:\esim\eSim\library\SubcircuitLibrary\D_FFtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/D_FF-cache.lib b/library/SubcircuitLibrary/SN74LS548/D_FF-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/D_FF-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/D_FF.bak b/library/SubcircuitLibrary/SN74LS548/D_FF.bak
new file mode 100644
index 000000000..61b02ff48
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/D_FF.bak
@@ -0,0 +1,246 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode?
+U 1 1 685A3E76
+P 9400 3200
+F 0 "scmode?" H 9400 3350 98 0000 C CNB
+F 1 "SKY130mode" H 9400 3100 118 0000 C CNB
+F 2 "" H 9400 3350 60 0001 C CNN
+F 3 "" H 9400 3350 60 0001 C CNN
+ 1 9400 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC?
+U 1 1 685A3EBD
+P 4000 3300
+F 0 "SC?" H 4050 3600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 3387 50 0000 R CNN
+F 2 "" H 4000 1800 50 0001 C CNN
+F 3 "" H 4000 3300 50 0001 C CNN
+ 1 4000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3EFC
+P 4000 4100
+F 0 "SC?" H 4050 4400 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4187 50 0000 R CNN
+F 2 "" H 4000 2600 50 0001 C CNN
+F 3 "" H 4000 4100 50 0001 C CNN
+ 1 4000 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3F47
+P 4000 4900
+F 0 "SC?" H 4050 5200 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4987 50 0000 R CNN
+F 2 "" H 4000 3400 50 0001 C CNN
+F 3 "" H 4000 4900 50 0001 C CNN
+ 1 4000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC?
+U 1 1 685A3F7A
+P 4950 3700
+F 0 "SC?" H 5000 4000 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5250 3787 50 0000 R CNN
+F 2 "" H 4950 2200 50 0001 C CNN
+F 3 "" H 4950 3700 50 0001 C CNN
+ 1 4950 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC?
+U 1 1 685A3FCF
+P 4950 4500
+F 0 "SC?" H 5000 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5250 4587 50 0000 R CNN
+F 2 "" H 4950 3000 50 0001 C CNN
+F 3 "" H 4950 4500 50 0001 C CNN
+ 1 4950 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 1 1 685A401A
+P 3250 3550
+F 0 "U?" H 3300 3650 30 0000 C CNN
+F 1 "PORT" H 3250 3550 30 0000 C CNN
+F 2 "" H 3250 3550 60 0000 C CNN
+F 3 "" H 3250 3550 60 0000 C CNN
+ 1 3250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 2 1 685A40FF
+P 3250 4100
+F 0 "U?" H 3300 4200 30 0000 C CNN
+F 1 "PORT" H 3250 4100 30 0000 C CNN
+F 2 "" H 3250 4100 60 0000 C CNN
+F 3 "" H 3250 4100 60 0000 C CNN
+ 2 3250 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 3 1 685A4132
+P 3950 2750
+F 0 "U?" H 4000 2850 30 0000 C CNN
+F 1 "PORT" H 3950 2750 30 0000 C CNN
+F 2 "" H 3950 2750 60 0000 C CNN
+F 3 "" H 3950 2750 60 0000 C CNN
+ 3 3950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 4 1 685A41B1
+P 3950 5350
+F 0 "U?" H 4000 5450 30 0000 C CNN
+F 1 "PORT" H 3950 5350 30 0000 C CNN
+F 2 "" H 3950 5350 60 0000 C CNN
+F 3 "" H 3950 5350 60 0000 C CNN
+ 4 3950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 5 1 685A4206
+P 5700 4100
+F 0 "U?" H 5750 4200 30 0000 C CNN
+F 1 "PORT" H 5700 4100 30 0000 C CNN
+F 2 "" H 5700 4100 60 0000 C CNN
+F 3 "" H 5700 4100 60 0000 C CNN
+ 5 5700 4100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4200 3600 4200 3800
+Wire Wire Line
+ 3700 3300 3600 3300
+Wire Wire Line
+ 3600 3300 3600 4900
+Wire Wire Line
+ 3600 4900 3700 4900
+Wire Wire Line
+ 3500 3550 3600 3550
+Connection ~ 3600 3550
+Wire Wire Line
+ 3500 4100 3700 4100
+Wire Wire Line
+ 4200 2750 4200 3000
+Wire Wire Line
+ 4650 3700 4200 3700
+Connection ~ 4200 3700
+Wire Wire Line
+ 4200 4400 4200 4600
+Wire Wire Line
+ 4650 4500 4200 4500
+Connection ~ 4200 4500
+Wire Wire Line
+ 5150 4000 5150 4200
+Wire Wire Line
+ 5450 4100 5150 4100
+Connection ~ 5150 4100
+Wire Wire Line
+ 4200 5200 4200 5350
+Wire Wire Line
+ 4100 4900 4250 4900
+Wire Wire Line
+ 4250 4900 4250 5250
+Wire Wire Line
+ 4200 5250 5150 5250
+Connection ~ 4200 5250
+Wire Wire Line
+ 5150 5250 5150 4800
+Connection ~ 4250 5250
+Wire Wire Line
+ 5050 4500 5200 4500
+Wire Wire Line
+ 5200 4500 5200 4850
+Wire Wire Line
+ 5200 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 4100 4100 4250 4100
+Wire Wire Line
+ 4250 4100 4250 4500
+Connection ~ 4250 4500
+Wire Wire Line
+ 4100 3300 4250 3300
+Wire Wire Line
+ 4250 3300 4250 2950
+Wire Wire Line
+ 4200 2950 5150 2950
+Connection ~ 4200 2950
+Wire Wire Line
+ 5150 2950 5150 3400
+Connection ~ 4250 2950
+Wire Wire Line
+ 5050 3700 5200 3700
+Wire Wire Line
+ 5200 3700 5200 3350
+Wire Wire Line
+ 5200 3350 5150 3350
+Connection ~ 5150 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/D_FF.cir b/library/SubcircuitLibrary/SN74LS548/D_FF.cir
new file mode 100644
index 000000000..0a7e96074
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/D_FF.cir
@@ -0,0 +1,17 @@
+* H:\esim\eSim\library\SubcircuitLibrary\D_FF\D_FF.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/16/25 12:03:13
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+scmode1 SKY130mode
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+SC3 Net-_SC2-Pad3_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC4-Pad1_ Net-_SC1-Pad1_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC5 Net-_SC4-Pad1_ Net-_SC2-Pad3_ Net-_SC3-Pad3_ Net-_SC3-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC3-Pad3_ Net-_SC4-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/D_FF.cir.out b/library/SubcircuitLibrary/SN74LS548/D_FF.cir.out
new file mode 100644
index 000000000..27dfd2ff9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/D_FF.cir.out
@@ -0,0 +1,19 @@
+* h:\esim\esim\library\subcircuitlibrary\d_ff\d_ff.cir
+
+
+* s c m o d e
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc2-pad3_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc4-pad1_ net-_sc2-pad3_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc4-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/D_FF.pro b/library/SubcircuitLibrary/SN74LS548/D_FF.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/D_FF.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS548/D_FF.sch b/library/SubcircuitLibrary/SN74LS548/D_FF.sch
new file mode 100644
index 000000000..722069493
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/D_FF.sch
@@ -0,0 +1,246 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 685A3E76
+P 9400 3200
+F 0 "scmode1" H 9400 3350 98 0000 C CNB
+F 1 "SKY130mode" H 9400 3100 118 0000 C CNB
+F 2 "" H 9400 3350 60 0001 C CNN
+F 3 "" H 9400 3350 60 0001 C CNN
+ 1 9400 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 685A3EBD
+P 4000 3300
+F 0 "SC1" H 4050 3600 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4300 3387 50 0000 R CNN
+F 2 "" H 4000 1800 50 0001 C CNN
+F 3 "" H 4000 3300 50 0001 C CNN
+ 1 4000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 685A3EFC
+P 4000 4100
+F 0 "SC2" H 4050 4400 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4187 50 0000 R CNN
+F 2 "" H 4000 2600 50 0001 C CNN
+F 3 "" H 4000 4100 50 0001 C CNN
+ 1 4000 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 685A3F47
+P 4000 4900
+F 0 "SC3" H 4050 5200 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 4300 4987 50 0000 R CNN
+F 2 "" H 4000 3400 50 0001 C CNN
+F 3 "" H 4000 4900 50 0001 C CNN
+ 1 4000 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC4
+U 1 1 685A3F7A
+P 4950 3700
+F 0 "SC4" H 5000 4000 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5250 3787 50 0000 R CNN
+F 2 "" H 4950 2200 50 0001 C CNN
+F 3 "" H 4950 3700 50 0001 C CNN
+ 1 4950 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 685A3FCF
+P 4950 4500
+F 0 "SC5" H 5000 4800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5250 4587 50 0000 R CNN
+F 2 "" H 4950 3000 50 0001 C CNN
+F 3 "" H 4950 4500 50 0001 C CNN
+ 1 4950 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 685A401A
+P 3250 3550
+F 0 "U1" H 3300 3650 30 0000 C CNN
+F 1 "PORT" H 3250 3550 30 0000 C CNN
+F 2 "" H 3250 3550 60 0000 C CNN
+F 3 "" H 3250 3550 60 0000 C CNN
+ 1 3250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685A40FF
+P 3250 4100
+F 0 "U1" H 3300 4200 30 0000 C CNN
+F 1 "PORT" H 3250 4100 30 0000 C CNN
+F 2 "" H 3250 4100 60 0000 C CNN
+F 3 "" H 3250 4100 60 0000 C CNN
+ 2 3250 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685A4132
+P 3950 2750
+F 0 "U1" H 4000 2850 30 0000 C CNN
+F 1 "PORT" H 3950 2750 30 0000 C CNN
+F 2 "" H 3950 2750 60 0000 C CNN
+F 3 "" H 3950 2750 60 0000 C CNN
+ 3 3950 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A41B1
+P 3950 5350
+F 0 "U1" H 4000 5450 30 0000 C CNN
+F 1 "PORT" H 3950 5350 30 0000 C CNN
+F 2 "" H 3950 5350 60 0000 C CNN
+F 3 "" H 3950 5350 60 0000 C CNN
+ 4 3950 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685A4206
+P 5700 4100
+F 0 "U1" H 5750 4200 30 0000 C CNN
+F 1 "PORT" H 5700 4100 30 0000 C CNN
+F 2 "" H 5700 4100 60 0000 C CNN
+F 3 "" H 5700 4100 60 0000 C CNN
+ 5 5700 4100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4200 3600 4200 3800
+Wire Wire Line
+ 3700 3300 3600 3300
+Wire Wire Line
+ 3600 3300 3600 4900
+Wire Wire Line
+ 3600 4900 3700 4900
+Wire Wire Line
+ 3500 3550 3600 3550
+Connection ~ 3600 3550
+Wire Wire Line
+ 3500 4100 3700 4100
+Wire Wire Line
+ 4200 2750 4200 3000
+Wire Wire Line
+ 4650 3700 4200 3700
+Connection ~ 4200 3700
+Wire Wire Line
+ 4200 4400 4200 4600
+Wire Wire Line
+ 4650 4500 4200 4500
+Connection ~ 4200 4500
+Wire Wire Line
+ 5150 4000 5150 4200
+Wire Wire Line
+ 5450 4100 5150 4100
+Connection ~ 5150 4100
+Wire Wire Line
+ 4200 5200 4200 5350
+Wire Wire Line
+ 4100 4900 4250 4900
+Wire Wire Line
+ 4250 4900 4250 5250
+Wire Wire Line
+ 4200 5250 5150 5250
+Connection ~ 4200 5250
+Wire Wire Line
+ 5150 5250 5150 4800
+Connection ~ 4250 5250
+Wire Wire Line
+ 5050 4500 5200 4500
+Wire Wire Line
+ 5200 4500 5200 4850
+Wire Wire Line
+ 5200 4850 5150 4850
+Connection ~ 5150 4850
+Wire Wire Line
+ 4100 4100 4250 4100
+Wire Wire Line
+ 4250 4100 4250 4500
+Connection ~ 4250 4500
+Wire Wire Line
+ 4100 3300 4250 3300
+Wire Wire Line
+ 4250 3300 4250 2950
+Wire Wire Line
+ 4200 2950 5150 2950
+Connection ~ 4200 2950
+Wire Wire Line
+ 5150 2950 5150 3400
+Connection ~ 4250 2950
+Wire Wire Line
+ 5050 3700 5200 3700
+Wire Wire Line
+ 5200 3700 5200 3350
+Wire Wire Line
+ 5200 3350 5150 3350
+Connection ~ 5150 3350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/D_FF.sub b/library/SubcircuitLibrary/SN74LS548/D_FF.sub
new file mode 100644
index 000000000..194596578
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/D_FF.sub
@@ -0,0 +1,13 @@
+* Subcircuit D_FF
+.subckt D_FF net-_sc1-pad2_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc3-pad3_ net-_sc4-pad1_
+* h:\esim\esim\library\subcircuitlibrary\d_ff\d_ff.cir
+
+* s c m o d e
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc3 net-_sc2-pad3_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc4-pad1_ net-_sc1-pad1_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc5 net-_sc4-pad1_ net-_sc2-pad3_ net-_sc3-pad3_ net-_sc3-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends D_FF
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/D_FF_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS548/D_FF_Previous_Values.xml
new file mode 100644
index 000000000..cdc78294b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/D_FF_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15w=3 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/MUX_21-cache.lib b/library/SubcircuitLibrary/SN74LS548/MUX_21-cache.lib
new file mode 100644
index 000000000..cd968f1fb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/MUX_21-cache.lib
@@ -0,0 +1,98 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 250 0 50 0 1 0 N
+P 2 0 1 0 -250 150 200 0 N
+P 3 0 1 0 -250 150 -250 -150 200 0 N
+X IN 1 -450 0 200 R 50 50 1 1 I
+X VDD 2 -450 100 200 R 50 50 1 1 I
+X GND 3 -450 -100 200 R 50 50 1 1 I
+X OUT 4 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/MUX_21-rescue.lib b/library/SubcircuitLibrary/SN74LS548/MUX_21-rescue.lib
new file mode 100644
index 000000000..d9053d1b6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/MUX_21-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# CMOS_INVTR-RESCUE-MUX_21
+#
+DEF CMOS_INVTR-RESCUE-MUX_21 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR-RESCUE-MUX_21" 50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 300 0 50 0 1 0 N
+P 2 0 1 0 -200 150 250 0 N
+P 3 0 1 0 -200 150 -200 -150 250 0 N
+X in 1 -400 0 200 R 50 50 1 1 I
+X Vdd 2 -400 100 200 R 50 50 1 1 I
+X Gnd 3 -400 -100 200 R 50 50 1 1 I
+X Out 4 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/MUX_21.bak b/library/SubcircuitLibrary/SN74LS548/MUX_21.bak
new file mode 100644
index 000000000..fea7fc6c8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/MUX_21.bak
@@ -0,0 +1,196 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L CMOS_INVTR X1
+U 1 1 68711FA9
+P 5650 1650
+F 0 "X1" H 5650 1650 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5700 1450 60 0000 C CNN
+F 2 "" H 5650 1650 60 0001 C CNN
+F 3 "" H 5650 1650 60 0001 C CNN
+ 1 5650 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 68711FE2
+P 4700 2000
+F 0 "SC1" H 4750 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5000 2087 50 0000 R CNN
+F 2 "" H 4700 500 50 0001 C CNN
+F 3 "" H 4700 2000 50 0001 C CNN
+ 1 4700 2000
+ 0 1 1 0
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 68712114
+P 6200 2300
+F 0 "SC2" H 6250 2600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6500 2387 50 0000 R CNN
+F 2 "" H 6200 800 50 0001 C CNN
+F 3 "" H 6200 2300 50 0001 C CNN
+ 1 6200 2300
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 4250 1650 5250 1650
+Wire Wire Line
+ 4700 1700 4700 1650
+Connection ~ 4700 1650
+Wire Wire Line
+ 4400 2200 4250 2200
+Wire Wire Line
+ 4700 2100 4700 2250
+Wire Wire Line
+ 4700 2250 4350 2250
+Wire Wire Line
+ 4350 2250 4350 2200
+Connection ~ 4350 2200
+Wire Wire Line
+ 6200 1650 6200 2000
+Wire Wire Line
+ 5900 2500 4250 2500
+Wire Wire Line
+ 6200 2400 6200 2550
+Wire Wire Line
+ 6200 2550 5800 2550
+Wire Wire Line
+ 5800 2550 5800 2500
+Connection ~ 5800 2500
+Wire Wire Line
+ 5000 2200 6850 2200
+Wire Wire Line
+ 6500 2200 6500 2500
+Connection ~ 6500 2200
+$Comp
+L PORT U1
+U 1 1 687121FA
+P 4000 1650
+F 0 "U1" H 4050 1750 30 0000 C CNN
+F 1 "PORT" H 4000 1650 30 0000 C CNN
+F 2 "" H 4000 1650 60 0000 C CNN
+F 3 "" H 4000 1650 60 0000 C CNN
+ 1 4000 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68712241
+P 4000 2200
+F 0 "U1" H 4050 2300 30 0000 C CNN
+F 1 "PORT" H 4000 2200 30 0000 C CNN
+F 2 "" H 4000 2200 60 0000 C CNN
+F 3 "" H 4000 2200 60 0000 C CNN
+ 2 4000 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6871226C
+P 4000 2500
+F 0 "U1" H 4050 2600 30 0000 C CNN
+F 1 "PORT" H 4000 2500 30 0000 C CNN
+F 2 "" H 4000 2500 60 0000 C CNN
+F 3 "" H 4000 2500 60 0000 C CNN
+ 3 4000 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68712295
+P 5000 1550
+F 0 "U1" H 5050 1650 30 0000 C CNN
+F 1 "PORT" H 5000 1550 30 0000 C CNN
+F 2 "" H 5000 1550 60 0000 C CNN
+F 3 "" H 5000 1550 60 0000 C CNN
+ 4 5000 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 687122E8
+P 5000 1750
+F 0 "U1" H 5050 1850 30 0000 C CNN
+F 1 "PORT" H 5000 1750 30 0000 C CNN
+F 2 "" H 5000 1750 60 0000 C CNN
+F 3 "" H 5000 1750 60 0000 C CNN
+ 5 5000 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68712317
+P 7100 2200
+F 0 "U1" H 7150 2300 30 0000 C CNN
+F 1 "PORT" H 7100 2200 30 0000 C CNN
+F 2 "" H 7100 2200 60 0000 C CNN
+F 3 "" H 7100 2200 60 0000 C CNN
+ 6 7100 2200
+ -1 0 0 1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68712384
+P 8900 2800
+F 0 "scmode1" H 8900 2950 98 0000 C CNB
+F 1 "SKY130mode" H 8900 2700 118 0000 C CNB
+F 2 "" H 8900 2950 60 0001 C CNN
+F 3 "" H 8900 2950 60 0001 C CNN
+ 1 8900 2800
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/MUX_21.cir b/library/SubcircuitLibrary/SN74LS548/MUX_21.cir
new file mode 100644
index 000000000..7c308d4a4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/MUX_21.cir
@@ -0,0 +1,15 @@
+* H:\esim\eSim\library\SubcircuitLibrary\MUX_21\MUX_21.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/16/25 20:44:44
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__nfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_SC1-Pad1_ PORT
+scmode1 SKY130mode
+X1 Net-_SC1-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_SC2-Pad2_ CMOS_INVTR
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/MUX_21.cir.out b/library/SubcircuitLibrary/SN74LS548/MUX_21.cir.out
new file mode 100644
index 000000000..7eff53e07
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/MUX_21.cir.out
@@ -0,0 +1,18 @@
+* h:\esim\esim\library\subcircuitlibrary\mux_21\mux_21.cir
+
+.include CMOS_INVTR.sub
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_sc1-pad1_ port
+* s c m o d e
+x1 net-_sc1-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_sc2-pad2_ CMOS_INVTR
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/MUX_21.pro b/library/SubcircuitLibrary/SN74LS548/MUX_21.pro
new file mode 100644
index 000000000..95be4d314
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/MUX_21.pro
@@ -0,0 +1,74 @@
+update=07/16/25 20:43:20
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=MUX_21-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS548/MUX_21.sch b/library/SubcircuitLibrary/SN74LS548/MUX_21.sch
new file mode 100644
index 000000000..31974c758
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/MUX_21.sch
@@ -0,0 +1,198 @@
+EESchema Schematic File Version 2
+LIBS:MUX_21-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MUX_21-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__nfet_01v8 SC1
+U 1 1 68711FE2
+P 4700 2000
+F 0 "SC1" H 4750 2300 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5000 2087 50 0000 R CNN
+F 2 "" H 4700 500 50 0001 C CNN
+F 3 "" H 4700 2000 50 0001 C CNN
+ 1 4700 2000
+ 0 1 1 0
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 68712114
+P 6200 2300
+F 0 "SC2" H 6250 2600 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6500 2387 50 0000 R CNN
+F 2 "" H 6200 800 50 0001 C CNN
+F 3 "" H 6200 2300 50 0001 C CNN
+ 1 6200 2300
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 4250 1650 5250 1650
+Wire Wire Line
+ 4700 1700 4700 1650
+Connection ~ 4700 1650
+Wire Wire Line
+ 4400 2200 4250 2200
+Wire Wire Line
+ 4700 2100 4700 2250
+Wire Wire Line
+ 4700 2250 4350 2250
+Wire Wire Line
+ 4350 2250 4350 2200
+Connection ~ 4350 2200
+Wire Wire Line
+ 6200 1650 6200 2000
+Wire Wire Line
+ 5900 2500 4250 2500
+Wire Wire Line
+ 6200 2400 6200 2550
+Wire Wire Line
+ 6200 2550 5800 2550
+Wire Wire Line
+ 5800 2550 5800 2500
+Connection ~ 5800 2500
+Wire Wire Line
+ 5000 2200 6850 2200
+Wire Wire Line
+ 6500 2200 6500 2500
+Connection ~ 6500 2200
+$Comp
+L PORT U1
+U 1 1 687121FA
+P 4000 1650
+F 0 "U1" H 4050 1750 30 0000 C CNN
+F 1 "PORT" H 4000 1650 30 0000 C CNN
+F 2 "" H 4000 1650 60 0000 C CNN
+F 3 "" H 4000 1650 60 0000 C CNN
+ 1 4000 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68712241
+P 4000 2200
+F 0 "U1" H 4050 2300 30 0000 C CNN
+F 1 "PORT" H 4000 2200 30 0000 C CNN
+F 2 "" H 4000 2200 60 0000 C CNN
+F 3 "" H 4000 2200 60 0000 C CNN
+ 2 4000 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6871226C
+P 4000 2500
+F 0 "U1" H 4050 2600 30 0000 C CNN
+F 1 "PORT" H 4000 2500 30 0000 C CNN
+F 2 "" H 4000 2500 60 0000 C CNN
+F 3 "" H 4000 2500 60 0000 C CNN
+ 3 4000 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68712295
+P 5000 1550
+F 0 "U1" H 5050 1650 30 0000 C CNN
+F 1 "PORT" H 5000 1550 30 0000 C CNN
+F 2 "" H 5000 1550 60 0000 C CNN
+F 3 "" H 5000 1550 60 0000 C CNN
+ 4 5000 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 687122E8
+P 5000 1750
+F 0 "U1" H 5050 1850 30 0000 C CNN
+F 1 "PORT" H 5000 1750 30 0000 C CNN
+F 2 "" H 5000 1750 60 0000 C CNN
+F 3 "" H 5000 1750 60 0000 C CNN
+ 5 5000 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68712317
+P 7100 2200
+F 0 "U1" H 7150 2300 30 0000 C CNN
+F 1 "PORT" H 7100 2200 30 0000 C CNN
+F 2 "" H 7100 2200 60 0000 C CNN
+F 3 "" H 7100 2200 60 0000 C CNN
+ 6 7100 2200
+ -1 0 0 1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68712384
+P 8900 2800
+F 0 "scmode1" H 8900 2950 98 0000 C CNB
+F 1 "SKY130mode" H 8900 2700 118 0000 C CNB
+F 2 "" H 8900 2950 60 0001 C CNN
+F 3 "" H 8900 2950 60 0001 C CNN
+ 1 8900 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L CMOS_INVTR X1
+U 1 1 6877C242
+P 5700 1650
+F 0 "X1" H 5700 1650 60 0000 C CNN
+F 1 "CMOS_INVTR" H 5650 1450 60 0000 C CNN
+F 2 "" H 5700 1650 60 0001 C CNN
+F 3 "" H 5700 1650 60 0001 C CNN
+ 1 5700 1650
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/MUX_21.sub b/library/SubcircuitLibrary/SN74LS548/MUX_21.sub
new file mode 100644
index 000000000..bba590027
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/MUX_21.sub
@@ -0,0 +1,12 @@
+* Subcircuit MUX_21
+.subckt MUX_21 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_sc1-pad1_
+* h:\esim\esim\library\subcircuitlibrary\mux_21\mux_21.cir
+.include CMOS_INVTR.sub
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+x1 net-_sc1-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_sc2-pad2_ CMOS_INVTR
+* Control Statements
+
+.ends MUX_21
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/MUX_21_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS548/MUX_21_Previous_Values.xml
new file mode 100644
index 000000000..1f3ca4497
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/MUX_21_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettw=1 l=0.15w=1 l=0.15H:\esim\eSim\library\SubcircuitLibrary\CMOS_INVTRtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/Rnk_Blk-cache.lib b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk-cache.lib
new file mode 100644
index 000000000..a31ec5ac2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk-cache.lib
@@ -0,0 +1,109 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DFF_CE
+#
+DEF DFF_CE X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "DFF_CE" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -400 150 300 -150 0 1 0 N
+X CLK 1 -600 -100 200 R 50 50 1 1 I
+X CLK_EN 2 -600 0 200 R 50 50 1 1 I
+X D 3 -600 100 200 R 50 50 1 1 I
+X VDD 4 500 100 200 L 50 50 1 1 I
+X GND 5 500 -100 200 L 50 50 1 1 I
+X OUT 6 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# MUX_21
+#
+DEF MUX_21 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "MUX_21" 200 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+P 5 0 1 0 -250 200 -250 -200 200 -100 200 100 -250 200 N
+X S 1 0 -350 200 U 50 50 1 1 O
+X B 2 -450 -50 200 R 50 50 1 1 I
+X A 3 -450 50 200 R 50 50 1 1 I
+X VDD 4 -450 150 200 R 50 50 1 1 I
+X GND 5 -450 -150 200 R 50 50 1 1 I
+X Y 6 400 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# tri_state
+#
+DEF tri_state X 0 40 Y Y 1 F N
+F0 "X" 100 0 60 H V C CNN
+F1 "tri_state" 150 -150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+P 4 0 1 0 -250 150 350 0 -250 -150 -250 150 N
+X IN 1 -450 0 200 R 50 50 1 1 I
+X VDD 2 -450 100 200 R 50 50 1 1 I
+X GND 3 -450 -100 200 R 50 50 1 1 I
+X EN 4 0 300 200 D 50 50 1 1 I I
+X OUT 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/Rnk_Blk-rescue.lib b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk-rescue.lib
new file mode 100644
index 000000000..4fbf03adc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk-rescue.lib
@@ -0,0 +1,23 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# tri_state-RESCUE-Rnk_Blk
+#
+DEF tri_state-RESCUE-Rnk_Blk X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "tri_state-RESCUE-Rnk_Blk" 50 -200 60 H V C CNN
+F2 "" 1450 -500 60 H I C CNN
+F3 "" 1450 -500 60 H I C CNN
+DRAW
+C -50 150 50 0 1 0 N
+P 2 0 1 0 -250 150 250 0 N
+P 3 0 1 0 -250 150 -250 -150 250 0 N
+X in 1 -450 0 200 R 50 50 1 1 I
+X Vdd 2 -450 100 200 R 50 50 1 1 I
+X Gnd 3 -450 -100 200 R 50 50 1 1 I
+X En 4 -50 400 200 D 50 50 1 1 I
+X out 5 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.bak b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.bak
new file mode 100644
index 000000000..ba355107f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.bak
@@ -0,0 +1,319 @@
+EESchema Schematic File Version 2
+LIBS:Rnk_Blk-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:Rnk_Blk-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 4250 2350 4500 2350
+Wire Wire Line
+ 3200 2050 4400 2050
+Wire Wire Line
+ 4400 2050 4400 2250
+Wire Wire Line
+ 4400 2250 4500 2250
+Wire Wire Line
+ 5350 2300 5450 2300
+Wire Wire Line
+ 5450 2300 5450 2250
+Wire Wire Line
+ 5450 2250 5600 2250
+Wire Wire Line
+ 6900 2250 6800 2250
+Wire Wire Line
+ 6800 2250 6800 2000
+Wire Wire Line
+ 6800 2000 4350 2000
+Wire Wire Line
+ 4350 2000 4350 2350
+Connection ~ 4350 2350
+Wire Wire Line
+ 4250 2450 4250 2550
+Wire Wire Line
+ 4250 2550 7750 2550
+Wire Wire Line
+ 7750 2550 7750 2400
+Wire Wire Line
+ 6900 2450 6900 2550
+Connection ~ 6900 2550
+Connection ~ 6650 2550
+Wire Wire Line
+ 4500 2450 4500 2550
+Connection ~ 4500 2550
+Wire Wire Line
+ 5600 2450 5600 2600
+Wire Wire Line
+ 5600 2600 3200 2600
+Wire Wire Line
+ 4250 2250 4250 1950
+Wire Wire Line
+ 4250 1950 7750 1950
+Wire Wire Line
+ 7750 1950 7750 2200
+Wire Wire Line
+ 6900 2150 6900 1950
+Connection ~ 6900 1950
+Connection ~ 6650 1950
+Wire Wire Line
+ 4500 2150 4500 1950
+Connection ~ 4500 1950
+$Comp
+L PORT U1
+U 1 1 68712BF8
+P 2950 2050
+F 0 "U1" H 3000 2150 30 0000 C CNN
+F 1 "PORT" H 2950 2050 30 0000 C CNN
+F 2 "" H 2950 2050 60 0000 C CNN
+F 3 "" H 2950 2050 60 0000 C CNN
+ 1 2950 2050
+ 1 0 0 -1
+$EndComp
+Connection ~ 3200 2050
+Connection ~ 3200 2600
+$Comp
+L PORT U1
+U 2 1 68712D01
+P 2900 2350
+F 0 "U1" H 2950 2450 30 0000 C CNN
+F 1 "PORT" H 2900 2350 30 0000 C CNN
+F 2 "" H 2900 2350 60 0000 C CNN
+F 3 "" H 2900 2350 60 0000 C CNN
+ 2 2900 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68712D4B
+P 2950 2600
+F 0 "U1" H 3000 2700 30 0000 C CNN
+F 1 "PORT" H 2950 2600 30 0000 C CNN
+F 2 "" H 2950 2600 60 0000 C CNN
+F 3 "" H 2950 2600 60 0000 C CNN
+ 3 2950 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68712D90
+P 4500 1700
+F 0 "U1" H 4550 1800 30 0000 C CNN
+F 1 "PORT" H 4500 1700 30 0000 C CNN
+F 2 "" H 4500 1700 60 0000 C CNN
+F 3 "" H 4500 1700 60 0000 C CNN
+ 4 4500 1700
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68712DD7
+P 4500 2800
+F 0 "U1" H 4550 2900 30 0000 C CNN
+F 1 "PORT" H 4500 2800 30 0000 C CNN
+F 2 "" H 4500 2800 60 0000 C CNN
+F 3 "" H 4500 2800 60 0000 C CNN
+ 5 4500 2800
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68712F5A
+P 4950 2900
+F 0 "U1" H 5000 3000 30 0000 C CNN
+F 1 "PORT" H 4950 2900 30 0000 C CNN
+F 2 "" H 4950 2900 60 0000 C CNN
+F 3 "" H 4950 2900 60 0000 C CNN
+ 6 4950 2900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68713016
+P 5350 2350
+F 0 "U1" H 5400 2450 30 0000 C CNN
+F 1 "PORT" H 5350 2350 30 0000 C CNN
+F 2 "" H 5350 2350 60 0000 C CNN
+F 3 "" H 5350 2350 60 0000 C CNN
+ 7 5350 2350
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 687130AE
+P 7100 2650
+F 0 "U1" H 7150 2750 30 0000 C CNN
+F 1 "PORT" H 7100 2650 30 0000 C CNN
+F 2 "" H 7100 2650 60 0000 C CNN
+F 3 "" H 7100 2650 60 0000 C CNN
+ 8 7100 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68713163
+P 8400 1900
+F 0 "U1" H 8450 2000 30 0000 C CNN
+F 1 "PORT" H 8400 1900 30 0000 C CNN
+F 2 "" H 8400 1900 60 0000 C CNN
+F 3 "" H 8400 1900 60 0000 C CNN
+ 9 8400 1900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6871323C
+P 9000 2300
+F 0 "U1" H 9050 2400 30 0000 C CNN
+F 1 "PORT" H 9000 2300 30 0000 C CNN
+F 2 "" H 9000 2300 60 0000 C CNN
+F 3 "" H 9000 2300 60 0000 C CNN
+ 10 9000 2300
+ -1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 6871331A
+P 9150 3800
+F 0 "scmode1" H 9150 3950 98 0000 C CNB
+F 1 "SKY130mode" H 9150 3700 118 0000 C CNB
+F 2 "" H 9150 3950 60 0001 C CNN
+F 3 "" H 9150 3950 60 0001 C CNN
+ 1 9150 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L DFF_CE X1
+U 1 1 6877CD0C
+P 3750 2350
+F 0 "X1" H 3750 2350 60 0000 C CNN
+F 1 "DFF_CE" H 3750 2150 60 0000 C CNN
+F 2 "" H 3750 2350 60 0001 C CNN
+F 3 "" H 3750 2350 60 0001 C CNN
+ 1 3750 2350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3200 2050 3200 2150
+Wire Wire Line
+ 3200 2150 3150 2150
+Wire Wire Line
+ 3150 2150 3150 2250
+Wire Wire Line
+ 3200 2600 3200 2500
+Wire Wire Line
+ 3200 2500 3150 2500
+Wire Wire Line
+ 3150 2500 3150 2450
+$Comp
+L MUX_21 X2
+U 1 1 6877CE6E
+P 4950 2300
+F 0 "X2" H 4950 2300 60 0000 C CNN
+F 1 "MUX_21" H 5150 2100 60 0000 C CNN
+F 2 "" H 4950 2300 60 0001 C CNN
+F 3 "" H 4950 2300 60 0001 C CNN
+ 1 4950 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L DFF_CE X3
+U 1 1 6877CF81
+P 6200 2350
+F 0 "X3" H 6200 2350 60 0000 C CNN
+F 1 "DFF_CE" H 6200 2150 60 0000 C CNN
+F 2 "" H 6200 2350 60 0001 C CNN
+F 3 "" H 6200 2350 60 0001 C CNN
+ 1 6200 2350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6650 1950 6650 2150
+Wire Wire Line
+ 6650 2150 6700 2150
+Wire Wire Line
+ 6700 2150 6700 2250
+Wire Wire Line
+ 6700 2350 6900 2350
+Wire Wire Line
+ 6700 2450 6700 2500
+Wire Wire Line
+ 6700 2500 6650 2500
+Wire Wire Line
+ 6650 2500 6650 2550
+$Comp
+L MUX_21 X4
+U 1 1 6877D0DB
+P 7350 2300
+F 0 "X4" H 7350 2300 60 0000 C CNN
+F 1 "MUX_21" H 7550 2100 60 0000 C CNN
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X5
+U 1 1 6877D186
+P 8200 2300
+F 0 "X5" H 8300 2300 60 0000 C CNN
+F 1 "tri_state" H 8350 2150 60 0000 C CNN
+F 2 "" H 8200 2300 60 0001 C CNN
+F 3 "" H 8200 2300 60 0001 C CNN
+ 1 8200 2300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8150 1900 8150 2000
+Wire Wire Line
+ 8150 2000 8200 2000
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.cir b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.cir
new file mode 100644
index 000000000..2b3dc307a
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.cir
@@ -0,0 +1,17 @@
+* H:\esim\eSim\library\SubcircuitLibrary\Rnk_Blk\Rnk_Blk.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/17/25 16:26:27
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT
+scmode1 SKY130mode
+X1 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X1-Pad6_ DFF_CE
+X2 Net-_U1-Pad6_ Net-_X1-Pad6_ Net-_U1-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X2-Pad6_ MUX_21
+X3 Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_X2-Pad6_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X3-Pad6_ DFF_CE
+X4 Net-_U1-Pad8_ Net-_X3-Pad6_ Net-_X1-Pad6_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_X4-Pad6_ MUX_21
+X5 Net-_X4-Pad6_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad9_ Net-_U1-Pad10_ tri_state
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.cir.out b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.cir.out
new file mode 100644
index 000000000..34c92dedd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.cir.out
@@ -0,0 +1,22 @@
+* h:\esim\esim\library\subcircuitlibrary\rnk_blk\rnk_blk.cir
+
+.include MUX_21.sub
+.include DFF_CE.sub
+.include tri_state.sub
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port
+* s c m o d e
+x1 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad6_ DFF_CE
+x2 net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_x2-pad6_ MUX_21
+x3 net-_u1-pad3_ net-_u1-pad7_ net-_x2-pad6_ net-_u1-pad4_ net-_u1-pad5_ net-_x3-pad6_ DFF_CE
+x4 net-_u1-pad8_ net-_x3-pad6_ net-_x1-pad6_ net-_u1-pad4_ net-_u1-pad5_ net-_x4-pad6_ MUX_21
+x5 net-_x4-pad6_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u1-pad10_ tri_state
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.pro b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.pro
new file mode 100644
index 000000000..24526b126
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.pro
@@ -0,0 +1,74 @@
+update=07/16/25 21:27:45
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=Rnk_Blk-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.sch b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.sch
new file mode 100644
index 000000000..ba355107f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.sch
@@ -0,0 +1,319 @@
+EESchema Schematic File Version 2
+LIBS:Rnk_Blk-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:Rnk_Blk-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 4250 2350 4500 2350
+Wire Wire Line
+ 3200 2050 4400 2050
+Wire Wire Line
+ 4400 2050 4400 2250
+Wire Wire Line
+ 4400 2250 4500 2250
+Wire Wire Line
+ 5350 2300 5450 2300
+Wire Wire Line
+ 5450 2300 5450 2250
+Wire Wire Line
+ 5450 2250 5600 2250
+Wire Wire Line
+ 6900 2250 6800 2250
+Wire Wire Line
+ 6800 2250 6800 2000
+Wire Wire Line
+ 6800 2000 4350 2000
+Wire Wire Line
+ 4350 2000 4350 2350
+Connection ~ 4350 2350
+Wire Wire Line
+ 4250 2450 4250 2550
+Wire Wire Line
+ 4250 2550 7750 2550
+Wire Wire Line
+ 7750 2550 7750 2400
+Wire Wire Line
+ 6900 2450 6900 2550
+Connection ~ 6900 2550
+Connection ~ 6650 2550
+Wire Wire Line
+ 4500 2450 4500 2550
+Connection ~ 4500 2550
+Wire Wire Line
+ 5600 2450 5600 2600
+Wire Wire Line
+ 5600 2600 3200 2600
+Wire Wire Line
+ 4250 2250 4250 1950
+Wire Wire Line
+ 4250 1950 7750 1950
+Wire Wire Line
+ 7750 1950 7750 2200
+Wire Wire Line
+ 6900 2150 6900 1950
+Connection ~ 6900 1950
+Connection ~ 6650 1950
+Wire Wire Line
+ 4500 2150 4500 1950
+Connection ~ 4500 1950
+$Comp
+L PORT U1
+U 1 1 68712BF8
+P 2950 2050
+F 0 "U1" H 3000 2150 30 0000 C CNN
+F 1 "PORT" H 2950 2050 30 0000 C CNN
+F 2 "" H 2950 2050 60 0000 C CNN
+F 3 "" H 2950 2050 60 0000 C CNN
+ 1 2950 2050
+ 1 0 0 -1
+$EndComp
+Connection ~ 3200 2050
+Connection ~ 3200 2600
+$Comp
+L PORT U1
+U 2 1 68712D01
+P 2900 2350
+F 0 "U1" H 2950 2450 30 0000 C CNN
+F 1 "PORT" H 2900 2350 30 0000 C CNN
+F 2 "" H 2900 2350 60 0000 C CNN
+F 3 "" H 2900 2350 60 0000 C CNN
+ 2 2900 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68712D4B
+P 2950 2600
+F 0 "U1" H 3000 2700 30 0000 C CNN
+F 1 "PORT" H 2950 2600 30 0000 C CNN
+F 2 "" H 2950 2600 60 0000 C CNN
+F 3 "" H 2950 2600 60 0000 C CNN
+ 3 2950 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68712D90
+P 4500 1700
+F 0 "U1" H 4550 1800 30 0000 C CNN
+F 1 "PORT" H 4500 1700 30 0000 C CNN
+F 2 "" H 4500 1700 60 0000 C CNN
+F 3 "" H 4500 1700 60 0000 C CNN
+ 4 4500 1700
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68712DD7
+P 4500 2800
+F 0 "U1" H 4550 2900 30 0000 C CNN
+F 1 "PORT" H 4500 2800 30 0000 C CNN
+F 2 "" H 4500 2800 60 0000 C CNN
+F 3 "" H 4500 2800 60 0000 C CNN
+ 5 4500 2800
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68712F5A
+P 4950 2900
+F 0 "U1" H 5000 3000 30 0000 C CNN
+F 1 "PORT" H 4950 2900 30 0000 C CNN
+F 2 "" H 4950 2900 60 0000 C CNN
+F 3 "" H 4950 2900 60 0000 C CNN
+ 6 4950 2900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68713016
+P 5350 2350
+F 0 "U1" H 5400 2450 30 0000 C CNN
+F 1 "PORT" H 5350 2350 30 0000 C CNN
+F 2 "" H 5350 2350 60 0000 C CNN
+F 3 "" H 5350 2350 60 0000 C CNN
+ 7 5350 2350
+ 1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 687130AE
+P 7100 2650
+F 0 "U1" H 7150 2750 30 0000 C CNN
+F 1 "PORT" H 7100 2650 30 0000 C CNN
+F 2 "" H 7100 2650 60 0000 C CNN
+F 3 "" H 7100 2650 60 0000 C CNN
+ 8 7100 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68713163
+P 8400 1900
+F 0 "U1" H 8450 2000 30 0000 C CNN
+F 1 "PORT" H 8400 1900 30 0000 C CNN
+F 2 "" H 8400 1900 60 0000 C CNN
+F 3 "" H 8400 1900 60 0000 C CNN
+ 9 8400 1900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6871323C
+P 9000 2300
+F 0 "U1" H 9050 2400 30 0000 C CNN
+F 1 "PORT" H 9000 2300 30 0000 C CNN
+F 2 "" H 9000 2300 60 0000 C CNN
+F 3 "" H 9000 2300 60 0000 C CNN
+ 10 9000 2300
+ -1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 6871331A
+P 9150 3800
+F 0 "scmode1" H 9150 3950 98 0000 C CNB
+F 1 "SKY130mode" H 9150 3700 118 0000 C CNB
+F 2 "" H 9150 3950 60 0001 C CNN
+F 3 "" H 9150 3950 60 0001 C CNN
+ 1 9150 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L DFF_CE X1
+U 1 1 6877CD0C
+P 3750 2350
+F 0 "X1" H 3750 2350 60 0000 C CNN
+F 1 "DFF_CE" H 3750 2150 60 0000 C CNN
+F 2 "" H 3750 2350 60 0001 C CNN
+F 3 "" H 3750 2350 60 0001 C CNN
+ 1 3750 2350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3200 2050 3200 2150
+Wire Wire Line
+ 3200 2150 3150 2150
+Wire Wire Line
+ 3150 2150 3150 2250
+Wire Wire Line
+ 3200 2600 3200 2500
+Wire Wire Line
+ 3200 2500 3150 2500
+Wire Wire Line
+ 3150 2500 3150 2450
+$Comp
+L MUX_21 X2
+U 1 1 6877CE6E
+P 4950 2300
+F 0 "X2" H 4950 2300 60 0000 C CNN
+F 1 "MUX_21" H 5150 2100 60 0000 C CNN
+F 2 "" H 4950 2300 60 0001 C CNN
+F 3 "" H 4950 2300 60 0001 C CNN
+ 1 4950 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L DFF_CE X3
+U 1 1 6877CF81
+P 6200 2350
+F 0 "X3" H 6200 2350 60 0000 C CNN
+F 1 "DFF_CE" H 6200 2150 60 0000 C CNN
+F 2 "" H 6200 2350 60 0001 C CNN
+F 3 "" H 6200 2350 60 0001 C CNN
+ 1 6200 2350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6650 1950 6650 2150
+Wire Wire Line
+ 6650 2150 6700 2150
+Wire Wire Line
+ 6700 2150 6700 2250
+Wire Wire Line
+ 6700 2350 6900 2350
+Wire Wire Line
+ 6700 2450 6700 2500
+Wire Wire Line
+ 6700 2500 6650 2500
+Wire Wire Line
+ 6650 2500 6650 2550
+$Comp
+L MUX_21 X4
+U 1 1 6877D0DB
+P 7350 2300
+F 0 "X4" H 7350 2300 60 0000 C CNN
+F 1 "MUX_21" H 7550 2100 60 0000 C CNN
+F 2 "" H 7350 2300 60 0001 C CNN
+F 3 "" H 7350 2300 60 0001 C CNN
+ 1 7350 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L tri_state X5
+U 1 1 6877D186
+P 8200 2300
+F 0 "X5" H 8300 2300 60 0000 C CNN
+F 1 "tri_state" H 8350 2150 60 0000 C CNN
+F 2 "" H 8200 2300 60 0001 C CNN
+F 3 "" H 8200 2300 60 0001 C CNN
+ 1 8200 2300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8150 1900 8150 2000
+Wire Wire Line
+ 8150 2000 8200 2000
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.sub b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.sub
new file mode 100644
index 000000000..0ba174c5b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk.sub
@@ -0,0 +1,16 @@
+* Subcircuit Rnk_Blk
+.subckt Rnk_Blk net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_
+* h:\esim\esim\library\subcircuitlibrary\rnk_blk\rnk_blk.cir
+.include MUX_21.sub
+.include DFF_CE.sub
+.include tri_state.sub
+
+* s c m o d e
+x1 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_x1-pad6_ DFF_CE
+x2 net-_u1-pad6_ net-_x1-pad6_ net-_u1-pad1_ net-_u1-pad4_ net-_u1-pad5_ net-_x2-pad6_ MUX_21
+x3 net-_u1-pad3_ net-_u1-pad7_ net-_x2-pad6_ net-_u1-pad4_ net-_u1-pad5_ net-_x3-pad6_ DFF_CE
+x4 net-_u1-pad8_ net-_x3-pad6_ net-_x1-pad6_ net-_u1-pad4_ net-_u1-pad5_ net-_x4-pad6_ MUX_21
+x5 net-_x4-pad6_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u1-pad10_ tri_state
+* Control Statements
+
+.ends Rnk_Blk
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/Rnk_Blk_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk_Previous_Values.xml
new file mode 100644
index 000000000..b337a3d34
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/Rnk_Blk_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettH:\esim\eSim\library\SubcircuitLibrary\DFF_CEH:\esim\eSim\library\SubcircuitLibrary\MUX_21H:\esim\eSim\library\SubcircuitLibrary\DFF_CEH:\esim\eSim\library\SubcircuitLibrary\MUX_21H:\esim\eSim\library\SubcircuitLibrary\tri_statetruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/SN74LS548-cache.lib b/library/SubcircuitLibrary/SN74LS548/SN74LS548-cache.lib
new file mode 100644
index 000000000..cbbbe5d45
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/SN74LS548-cache.lib
@@ -0,0 +1,78 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# Rnk_Blk
+#
+DEF Rnk_Blk X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "Rnk_Blk" 0 -300 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 250 350 -250 0 1 0 N
+X D_In 1 -500 100 200 R 50 50 1 1 I
+X CKE1 2 -500 0 200 R 50 50 1 1 I I
+X CLK 3 -500 -100 200 R 50 50 1 1 I C
+X VDD 4 -500 200 200 R 50 50 1 1 I
+X GND 5 550 -200 200 L 50 50 1 1 I
+X INSEL 6 -500 -200 200 R 50 50 1 1 I
+X CKE2 7 550 0 200 L 50 50 1 1 I I
+X OUTSEL 8 550 100 200 L 50 50 1 1 I
+X OE 9 550 200 200 L 50 50 1 1 I I
+X OUT 10 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/SN74LS548-rescue.lib b/library/SubcircuitLibrary/SN74LS548/SN74LS548-rescue.lib
new file mode 100644
index 000000000..8bf544d48
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/SN74LS548-rescue.lib
@@ -0,0 +1,26 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# Rnk_Blk-RESCUE-SN74LS548
+#
+DEF Rnk_Blk-RESCUE-SN74LS548 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "Rnk_Blk-RESCUE-SN74LS548" 0 -300 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -400 250 400 -250 0 1 0 N
+X D_in 1 -600 100 200 R 50 50 1 1 I
+X CKE1 2 -600 0 200 R 50 50 1 1 I I
+X Clk 3 -600 -100 200 R 50 50 1 1 I C
+X Vdd 4 -600 200 200 R 50 50 1 1 I
+X Gnd 5 600 -200 200 L 50 50 1 1 I
+X INSEL 6 -600 -200 200 R 50 50 1 1 I
+X CKE2 7 600 0 200 L 50 50 1 1 I I
+X OUTSEL 8 600 100 200 L 50 50 1 1 I
+X OE 9 600 200 200 L 50 50 1 1 I I
+X Y_out 10 600 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/SN74LS548.bak b/library/SubcircuitLibrary/SN74LS548/SN74LS548.bak
new file mode 100644
index 000000000..80ed428cb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/SN74LS548.bak
@@ -0,0 +1,685 @@
+EESchema Schematic File Version 2
+LIBS:SN74LS548-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74LS548-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 68713AEF
+P 6200 7250
+F 0 "scmode1" H 6200 7400 98 0000 C CNB
+F 1 "SKY130mode" H 6200 7150 118 0000 C CNB
+F 2 "" H 6200 7400 60 0001 C CNN
+F 3 "" H 6200 7400 60 0001 C CNN
+ 1 6200 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6871413B
+P 1900 2750
+F 0 "U1" H 1950 2850 30 0000 C CNN
+F 1 "PORT" H 1900 2750 30 0000 C CNN
+F 2 "" H 1900 2750 60 0000 C CNN
+F 3 "" H 1900 2750 60 0000 C CNN
+ 1 1900 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 24 1 68714254
+P 10450 3350
+F 0 "U1" H 10500 3450 30 0000 C CNN
+F 1 "PORT" H 10450 3350 30 0000 C CNN
+F 2 "" H 10450 3350 60 0000 C CNN
+F 3 "" H 10450 3350 60 0000 C CNN
+ 24 10450 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 687142F2
+P 2550 2850
+F 0 "U1" H 2600 2950 30 0000 C CNN
+F 1 "PORT" H 2550 2850 30 0000 C CNN
+F 2 "" H 2550 2850 60 0000 C CNN
+F 3 "" H 2550 2850 60 0000 C CNN
+ 5 2550 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68714377
+P 4400 2850
+F 0 "U1" H 4450 2950 30 0000 C CNN
+F 1 "PORT" H 4400 2850 30 0000 C CNN
+F 2 "" H 4400 2850 60 0000 C CNN
+F 3 "" H 4400 2850 60 0000 C CNN
+ 9 4400 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 687143B4
+P 6250 2850
+F 0 "U1" H 6300 2950 30 0000 C CNN
+F 1 "PORT" H 6250 2850 30 0000 C CNN
+F 2 "" H 6250 2850 60 0000 C CNN
+F 3 "" H 6250 2850 60 0000 C CNN
+ 13 6250 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 68714411
+P 8000 2850
+F 0 "U1" H 8050 2950 30 0000 C CNN
+F 1 "PORT" H 8000 2850 30 0000 C CNN
+F 2 "" H 8000 2850 60 0000 C CNN
+F 3 "" H 8000 2850 60 0000 C CNN
+ 17 8000 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 687144B3
+P 8000 4600
+F 0 "U1" H 8050 4700 30 0000 C CNN
+F 1 "PORT" H 8000 4600 30 0000 C CNN
+F 2 "" H 8000 4600 60 0000 C CNN
+F 3 "" H 8000 4600 60 0000 C CNN
+ 18 8000 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6871452C
+P 6250 4600
+F 0 "U1" H 6300 4700 30 0000 C CNN
+F 1 "PORT" H 6250 4600 30 0000 C CNN
+F 2 "" H 6250 4600 60 0000 C CNN
+F 3 "" H 6250 4600 60 0000 C CNN
+ 14 6250 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6871458B
+P 4400 4600
+F 0 "U1" H 4450 4700 30 0000 C CNN
+F 1 "PORT" H 4400 4600 30 0000 C CNN
+F 2 "" H 4400 4600 60 0000 C CNN
+F 3 "" H 4400 4600 60 0000 C CNN
+ 10 4400 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 687145F8
+P 2550 4600
+F 0 "U1" H 2600 4700 30 0000 C CNN
+F 1 "PORT" H 2550 4600 30 0000 C CNN
+F 2 "" H 2550 4600 60 0000 C CNN
+F 3 "" H 2550 4600 60 0000 C CNN
+ 6 2550 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 687147CD
+P 1950 3400
+F 0 "U1" H 2000 3500 30 0000 C CNN
+F 1 "PORT" H 1950 3400 30 0000 C CNN
+F 2 "" H 1950 3400 60 0000 C CNN
+F 3 "" H 1950 3400 60 0000 C CNN
+ 2 1950 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68714C33
+P 2000 3550
+F 0 "U1" H 2050 3650 30 0000 C CNN
+F 1 "PORT" H 2000 3550 30 0000 C CNN
+F 2 "" H 2000 3550 60 0000 C CNN
+F 3 "" H 2000 3550 60 0000 C CNN
+ 3 2000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 687151F2
+P 2050 3750
+F 0 "U1" H 2100 3850 30 0000 C CNN
+F 1 "PORT" H 2050 3750 30 0000 C CNN
+F 2 "" H 2050 3750 60 0000 C CNN
+F 3 "" H 2050 3750 60 0000 C CNN
+ 4 2050 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 23 1 68715B07
+P 10400 3850
+F 0 "U1" H 10450 3950 30 0000 C CNN
+F 1 "PORT" H 10400 3850 30 0000 C CNN
+F 2 "" H 10400 3850 60 0000 C CNN
+F 3 "" H 10400 3850 60 0000 C CNN
+ 23 10400 3850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 22 1 68716166
+P 10350 4000
+F 0 "U1" H 10400 4100 30 0000 C CNN
+F 1 "PORT" H 10350 4000 30 0000 C CNN
+F 2 "" H 10350 4000 60 0000 C CNN
+F 3 "" H 10350 4000 60 0000 C CNN
+ 22 10350 4000
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2800 2750 2150 2750
+Wire Wire Line
+ 2150 2600 2150 4500
+Wire Wire Line
+ 2150 4500 2800 4500
+Wire Wire Line
+ 2150 2600 8250 2600
+Wire Wire Line
+ 8250 2600 8250 2750
+Connection ~ 2150 2750
+Wire Wire Line
+ 8250 4500 8250 4350
+Wire Wire Line
+ 8250 4350 2150 4350
+Connection ~ 2150 4350
+Wire Wire Line
+ 9300 3150 10200 3150
+Wire Wire Line
+ 10200 3150 10200 5100
+Wire Wire Line
+ 9300 4900 10200 4900
+Wire Wire Line
+ 10200 5100 4000 5100
+Wire Wire Line
+ 4000 5100 4000 4900
+Connection ~ 10200 4900
+Wire Wire Line
+ 4000 3150 4000 3350
+Wire Wire Line
+ 4000 3350 10200 3350
+Connection ~ 10200 3350
+Wire Wire Line
+ 4650 2750 4650 2600
+Connection ~ 4650 2600
+Wire Wire Line
+ 6500 2750 6500 2600
+Connection ~ 6500 2600
+Wire Wire Line
+ 5850 3150 5850 3350
+Connection ~ 5850 3350
+Wire Wire Line
+ 7700 3150 7700 3350
+Connection ~ 7700 3350
+Wire Wire Line
+ 7700 4900 7700 5100
+Connection ~ 7700 5100
+Wire Wire Line
+ 6500 4500 6500 4350
+Connection ~ 6500 4350
+Wire Wire Line
+ 5850 4900 5850 5100
+Connection ~ 5850 5100
+Wire Wire Line
+ 4650 4500 4650 4350
+Connection ~ 4650 4350
+Wire Wire Line
+ 2800 2950 2200 2950
+Wire Wire Line
+ 2200 2950 2200 4700
+Wire Wire Line
+ 2200 4700 2800 4700
+Wire Wire Line
+ 4650 2950 4300 2950
+Wire Wire Line
+ 4300 2950 4300 4700
+Wire Wire Line
+ 2200 3400 7900 3400
+Connection ~ 2200 3400
+Wire Wire Line
+ 6500 2950 6150 2950
+Wire Wire Line
+ 6150 2950 6150 4700
+Connection ~ 4300 3400
+Wire Wire Line
+ 8250 2950 7900 2950
+Wire Wire Line
+ 7900 2950 7900 4700
+Connection ~ 6150 3400
+Wire Wire Line
+ 4300 4700 4650 4700
+Wire Wire Line
+ 6150 4700 6500 4700
+Wire Wire Line
+ 7900 4700 8250 4700
+Connection ~ 7900 3400
+Wire Wire Line
+ 2800 3050 2250 3050
+Wire Wire Line
+ 2250 3050 2250 4800
+Wire Wire Line
+ 2250 4800 2800 4800
+Wire Wire Line
+ 4650 3050 4350 3050
+Wire Wire Line
+ 4350 3050 4350 4800
+Wire Wire Line
+ 2250 3550 7950 3550
+Connection ~ 2250 3550
+Wire Wire Line
+ 6500 3050 6200 3050
+Wire Wire Line
+ 6200 3050 6200 4800
+Connection ~ 4350 3550
+Wire Wire Line
+ 7950 3050 7950 4800
+Wire Wire Line
+ 7950 3050 8250 3050
+Connection ~ 6200 3550
+Wire Wire Line
+ 4350 4800 4650 4800
+Wire Wire Line
+ 6200 4800 6500 4800
+Wire Wire Line
+ 7950 4800 8250 4800
+Connection ~ 7950 3550
+Wire Wire Line
+ 2800 3150 2300 3150
+Wire Wire Line
+ 2300 3150 2300 4900
+Wire Wire Line
+ 2300 4900 2800 4900
+Wire Wire Line
+ 4650 3150 4400 3150
+Wire Wire Line
+ 4400 3150 4400 4900
+Wire Wire Line
+ 2300 3750 8000 3750
+Connection ~ 2300 3750
+Wire Wire Line
+ 6250 3150 6250 4900
+Wire Wire Line
+ 6250 3150 6500 3150
+Connection ~ 4400 3750
+Wire Wire Line
+ 8000 3150 8000 4900
+Wire Wire Line
+ 8000 3150 8250 3150
+Connection ~ 6250 3750
+Wire Wire Line
+ 4400 4900 4650 4900
+Wire Wire Line
+ 6250 4900 6500 4900
+Wire Wire Line
+ 8000 4900 8250 4900
+Connection ~ 8000 3750
+Wire Wire Line
+ 9300 2750 10150 2750
+Wire Wire Line
+ 10150 2750 10150 4500
+Wire Wire Line
+ 10150 4500 9300 4500
+Wire Wire Line
+ 7550 2750 7850 2750
+Wire Wire Line
+ 7850 2750 7850 4500
+Wire Wire Line
+ 4250 3850 10150 3850
+Connection ~ 10150 3850
+Wire Wire Line
+ 6100 4500 6100 2750
+Wire Wire Line
+ 6100 2750 5700 2750
+Connection ~ 7850 3850
+Wire Wire Line
+ 4250 4500 4250 2750
+Wire Wire Line
+ 4250 2750 3850 2750
+Connection ~ 6100 3850
+Wire Wire Line
+ 7850 4500 7550 4500
+Wire Wire Line
+ 5700 4500 6100 4500
+Wire Wire Line
+ 3850 4500 4250 4500
+Connection ~ 4250 3850
+Wire Wire Line
+ 9300 2850 10100 2850
+Wire Wire Line
+ 10100 2850 10100 4600
+Wire Wire Line
+ 10100 4600 9300 4600
+Wire Wire Line
+ 7550 2850 7800 2850
+Wire Wire Line
+ 7800 2850 7800 4600
+Wire Wire Line
+ 4200 4000 10100 4000
+Connection ~ 10100 4000
+Wire Wire Line
+ 7800 4600 7550 4600
+Connection ~ 7800 4000
+Wire Wire Line
+ 6050 4600 6050 2850
+Wire Wire Line
+ 5700 4600 6050 4600
+Wire Wire Line
+ 6050 2850 5700 2850
+Connection ~ 6050 4000
+Wire Wire Line
+ 4200 4600 4200 2850
+Wire Wire Line
+ 3850 4600 4200 4600
+Wire Wire Line
+ 4200 2850 3850 2850
+Connection ~ 4200 4000
+Wire Wire Line
+ 9300 2950 10050 2950
+Wire Wire Line
+ 10050 2950 10050 4700
+Wire Wire Line
+ 10050 4700 9300 4700
+Wire Wire Line
+ 7550 2950 7750 2950
+Wire Wire Line
+ 7750 2950 7750 4700
+Wire Wire Line
+ 4150 4100 10050 4100
+Connection ~ 10050 4100
+Wire Wire Line
+ 7750 4700 7550 4700
+Connection ~ 7750 4100
+Wire Wire Line
+ 6000 4700 6000 2950
+Wire Wire Line
+ 5700 4700 6000 4700
+Wire Wire Line
+ 6000 2950 5700 2950
+Connection ~ 6000 4100
+Wire Wire Line
+ 4150 4700 4150 2950
+Wire Wire Line
+ 3850 4700 4150 4700
+Wire Wire Line
+ 4150 2950 3850 2950
+Connection ~ 4150 4100
+$Comp
+L PORT U1
+U 21 1 68716B57
+P 10300 4100
+F 0 "U1" H 10350 4200 30 0000 C CNN
+F 1 "PORT" H 10300 4100 30 0000 C CNN
+F 2 "" H 10300 4100 60 0000 C CNN
+F 3 "" H 10300 4100 60 0000 C CNN
+ 21 10300 4100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68716CBD
+P 4250 3050
+F 0 "U1" H 4300 3150 30 0000 C CNN
+F 1 "PORT" H 4250 3050 30 0000 C CNN
+F 2 "" H 4250 3050 60 0000 C CNN
+F 3 "" H 4250 3050 60 0000 C CNN
+ 7 4250 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68716D64
+P 6100 3050
+F 0 "U1" H 6150 3150 30 0000 C CNN
+F 1 "PORT" H 6100 3050 30 0000 C CNN
+F 2 "" H 6100 3050 60 0000 C CNN
+F 3 "" H 6100 3050 60 0000 C CNN
+ 11 6100 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 68716DFD
+P 7950 3050
+F 0 "U1" H 8000 3150 30 0000 C CNN
+F 1 "PORT" H 7950 3050 30 0000 C CNN
+F 2 "" H 7950 3050 60 0000 C CNN
+F 3 "" H 7950 3050 60 0000 C CNN
+ 15 7950 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 19 1 68716E98
+P 9700 3050
+F 0 "U1" H 9750 3150 30 0000 C CNN
+F 1 "PORT" H 9700 3050 30 0000 C CNN
+F 2 "" H 9700 3050 60 0000 C CNN
+F 3 "" H 9700 3050 60 0000 C CNN
+ 19 9700 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 20 1 68716FB5
+P 9700 4800
+F 0 "U1" H 9750 4900 30 0000 C CNN
+F 1 "PORT" H 9700 4800 30 0000 C CNN
+F 2 "" H 9700 4800 60 0000 C CNN
+F 3 "" H 9700 4800 60 0000 C CNN
+ 20 9700 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 68717072
+P 7950 4800
+F 0 "U1" H 8000 4900 30 0000 C CNN
+F 1 "PORT" H 7950 4800 30 0000 C CNN
+F 2 "" H 7950 4800 60 0000 C CNN
+F 3 "" H 7950 4800 60 0000 C CNN
+ 16 7950 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 68717115
+P 6100 4800
+F 0 "U1" H 6150 4900 30 0000 C CNN
+F 1 "PORT" H 6100 4800 30 0000 C CNN
+F 2 "" H 6100 4800 60 0000 C CNN
+F 3 "" H 6100 4800 60 0000 C CNN
+ 12 6100 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 687171B4
+P 4250 4800
+F 0 "U1" H 4300 4900 30 0000 C CNN
+F 1 "PORT" H 4250 4800 30 0000 C CNN
+F 2 "" H 4250 4800 60 0000 C CNN
+F 3 "" H 4250 4800 60 0000 C CNN
+ 8 4250 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L Rnk_Blk X1
+U 1 1 6878DC64
+P 3300 2950
+F 0 "X1" H 3300 2950 60 0000 C CNN
+F 1 "Rnk_Blk" H 3300 2650 60 0000 C CNN
+F 2 "" H 3300 2950 60 0001 C CNN
+F 3 "" H 3300 2950 60 0001 C CNN
+ 1 3300 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3850 3050 4000 3050
+Wire Wire Line
+ 3850 3150 4000 3150
+$Comp
+L Rnk_Blk X3
+U 1 1 6878E1D0
+P 5150 2950
+F 0 "X3" H 5150 2950 60 0000 C CNN
+F 1 "Rnk_Blk" H 5150 2650 60 0000 C CNN
+F 2 "" H 5150 2950 60 0001 C CNN
+F 3 "" H 5150 2950 60 0001 C CNN
+ 1 5150 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5850 3050 5700 3050
+Wire Wire Line
+ 5850 3150 5700 3150
+$Comp
+L Rnk_Blk X5
+U 1 1 6878E69D
+P 7000 2950
+F 0 "X5" H 7000 2950 60 0000 C CNN
+F 1 "Rnk_Blk" H 7000 2650 60 0000 C CNN
+F 2 "" H 7000 2950 60 0001 C CNN
+F 3 "" H 7000 2950 60 0001 C CNN
+ 1 7000 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7700 3050 7550 3050
+Wire Wire Line
+ 7550 3150 7700 3150
+$Comp
+L Rnk_Blk X7
+U 1 1 6878EB72
+P 8750 2950
+F 0 "X7" H 8750 2950 60 0000 C CNN
+F 1 "Rnk_Blk" H 8750 2650 60 0000 C CNN
+F 2 "" H 8750 2950 60 0001 C CNN
+F 3 "" H 8750 2950 60 0001 C CNN
+ 1 8750 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9450 3050 9300 3050
+$Comp
+L Rnk_Blk X2
+U 1 1 6878F17E
+P 3300 4700
+F 0 "X2" H 3300 4700 60 0000 C CNN
+F 1 "Rnk_Blk" H 3300 4400 60 0000 C CNN
+F 2 "" H 3300 4700 60 0001 C CNN
+F 3 "" H 3300 4700 60 0001 C CNN
+ 1 3300 4700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4000 4800 3850 4800
+Wire Wire Line
+ 4000 4900 3850 4900
+$Comp
+L Rnk_Blk X4
+U 1 1 6878F665
+P 5150 4700
+F 0 "X4" H 5150 4700 60 0000 C CNN
+F 1 "Rnk_Blk" H 5150 4400 60 0000 C CNN
+F 2 "" H 5150 4700 60 0001 C CNN
+F 3 "" H 5150 4700 60 0001 C CNN
+ 1 5150 4700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5850 4800 5700 4800
+Wire Wire Line
+ 5850 4900 5700 4900
+$Comp
+L Rnk_Blk X6
+U 1 1 6878FB38
+P 7000 4700
+F 0 "X6" H 7000 4700 60 0000 C CNN
+F 1 "Rnk_Blk" H 7000 4400 60 0000 C CNN
+F 2 "" H 7000 4700 60 0001 C CNN
+F 3 "" H 7000 4700 60 0001 C CNN
+ 1 7000 4700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7700 4800 7550 4800
+Wire Wire Line
+ 7700 4900 7550 4900
+$Comp
+L Rnk_Blk X8
+U 1 1 6878FFD1
+P 8750 4700
+F 0 "X8" H 8750 4700 60 0000 C CNN
+F 1 "Rnk_Blk" H 8750 4400 60 0000 C CNN
+F 2 "" H 8750 4700 60 0001 C CNN
+F 3 "" H 8750 4700 60 0001 C CNN
+ 1 8750 4700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9450 4800 9300 4800
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/SN74LS548.cir b/library/SubcircuitLibrary/SN74LS548/SN74LS548.cir
new file mode 100644
index 000000000..90427dc2c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/SN74LS548.cir
@@ -0,0 +1,20 @@
+* H:\esim\eSim\library\SubcircuitLibrary\SN74LS548\SN74LS548.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/17/25 16:46:39
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad24_ PORT
+X1 Net-_U1-Pad5_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad24_ Net-_U1-Pad4_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad7_ Rnk_Blk
+X3 Net-_U1-Pad9_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad24_ Net-_U1-Pad4_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad11_ Rnk_Blk
+X5 Net-_U1-Pad13_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad24_ Net-_U1-Pad4_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad15_ Rnk_Blk
+X7 Net-_U1-Pad17_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad24_ Net-_U1-Pad4_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad19_ Rnk_Blk
+X2 Net-_U1-Pad6_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad24_ Net-_U1-Pad4_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad8_ Rnk_Blk
+X4 Net-_U1-Pad10_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad24_ Net-_U1-Pad4_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad12_ Rnk_Blk
+X6 Net-_U1-Pad14_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad24_ Net-_U1-Pad4_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad16_ Rnk_Blk
+X8 Net-_U1-Pad18_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad24_ Net-_U1-Pad4_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad20_ Rnk_Blk
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/SN74LS548.cir.out b/library/SubcircuitLibrary/SN74LS548/SN74LS548.cir.out
new file mode 100644
index 000000000..26f92dc98
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/SN74LS548.cir.out
@@ -0,0 +1,23 @@
+* h:\esim\esim\library\subcircuitlibrary\sn74ls548\sn74ls548.cir
+
+.include Rnk_Blk.sub
+
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ port
+x1 net-_u1-pad5_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad7_ Rnk_Blk
+x3 net-_u1-pad9_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad11_ Rnk_Blk
+x5 net-_u1-pad13_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad15_ Rnk_Blk
+x7 net-_u1-pad17_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad19_ Rnk_Blk
+x2 net-_u1-pad6_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad8_ Rnk_Blk
+x4 net-_u1-pad10_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad12_ Rnk_Blk
+x6 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad16_ Rnk_Blk
+x8 net-_u1-pad18_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad20_ Rnk_Blk
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/SN74LS548.pro b/library/SubcircuitLibrary/SN74LS548/SN74LS548.pro
new file mode 100644
index 000000000..c268182c0
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/SN74LS548.pro
@@ -0,0 +1,74 @@
+update=07/17/25 16:40:51
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=SN74LS548-rescue
+LibName2=adc-dac
+LibName3=memory
+LibName4=xilinx
+LibName5=microcontrollers
+LibName6=dsp
+LibName7=microchip
+LibName8=analog_switches
+LibName9=motorola
+LibName10=texas
+LibName11=intel
+LibName12=audio
+LibName13=interface
+LibName14=digital-audio
+LibName15=philips
+LibName16=display
+LibName17=cypress
+LibName18=siliconi
+LibName19=opto
+LibName20=atmel
+LibName21=contrib
+LibName22=power
+LibName23=eSim_Plot
+LibName24=transistors
+LibName25=conn
+LibName26=eSim_User
+LibName27=regul
+LibName28=74xx
+LibName29=cmos4000
+LibName30=eSim_Analog
+LibName31=eSim_Devices
+LibName32=eSim_Digital
+LibName33=eSim_Hybrid
+LibName34=eSim_Miscellaneous
+LibName35=eSim_Power
+LibName36=eSim_Sources
+LibName37=eSim_Subckt
+LibName38=eSim_Nghdl
+LibName39=eSim_Ngveri
+LibName40=eSim_SKY130
+LibName41=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS548/SN74LS548.sch b/library/SubcircuitLibrary/SN74LS548/SN74LS548.sch
new file mode 100644
index 000000000..b36e16465
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/SN74LS548.sch
@@ -0,0 +1,685 @@
+EESchema Schematic File Version 2
+LIBS:SN74LS548-rescue
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74LS548-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L SKY130mode scmode1
+U 1 1 68713AEF
+P 9000 3850
+F 0 "scmode1" H 9000 4000 98 0000 C CNB
+F 1 "SKY130mode" H 9000 3750 118 0000 C CNB
+F 2 "" H 9000 4000 60 0001 C CNN
+F 3 "" H 9000 4000 60 0001 C CNN
+ 1 9000 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6871413B
+P 1900 2750
+F 0 "U1" H 1950 2850 30 0000 C CNN
+F 1 "PORT" H 1900 2750 30 0000 C CNN
+F 2 "" H 1900 2750 60 0000 C CNN
+F 3 "" H 1900 2750 60 0000 C CNN
+ 1 1900 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 24 1 68714254
+P 10450 3350
+F 0 "U1" H 10500 3450 30 0000 C CNN
+F 1 "PORT" H 10450 3350 30 0000 C CNN
+F 2 "" H 10450 3350 60 0000 C CNN
+F 3 "" H 10450 3350 60 0000 C CNN
+ 24 10450 3350
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 687142F2
+P 2550 2850
+F 0 "U1" H 2600 2950 30 0000 C CNN
+F 1 "PORT" H 2550 2850 30 0000 C CNN
+F 2 "" H 2550 2850 60 0000 C CNN
+F 3 "" H 2550 2850 60 0000 C CNN
+ 5 2550 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68714377
+P 4400 2850
+F 0 "U1" H 4450 2950 30 0000 C CNN
+F 1 "PORT" H 4400 2850 30 0000 C CNN
+F 2 "" H 4400 2850 60 0000 C CNN
+F 3 "" H 4400 2850 60 0000 C CNN
+ 9 4400 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 687143B4
+P 6250 2850
+F 0 "U1" H 6300 2950 30 0000 C CNN
+F 1 "PORT" H 6250 2850 30 0000 C CNN
+F 2 "" H 6250 2850 60 0000 C CNN
+F 3 "" H 6250 2850 60 0000 C CNN
+ 13 6250 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 68714411
+P 8000 2850
+F 0 "U1" H 8050 2950 30 0000 C CNN
+F 1 "PORT" H 8000 2850 30 0000 C CNN
+F 2 "" H 8000 2850 60 0000 C CNN
+F 3 "" H 8000 2850 60 0000 C CNN
+ 17 8000 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 687144B3
+P 8000 4600
+F 0 "U1" H 8050 4700 30 0000 C CNN
+F 1 "PORT" H 8000 4600 30 0000 C CNN
+F 2 "" H 8000 4600 60 0000 C CNN
+F 3 "" H 8000 4600 60 0000 C CNN
+ 18 8000 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6871452C
+P 6250 4600
+F 0 "U1" H 6300 4700 30 0000 C CNN
+F 1 "PORT" H 6250 4600 30 0000 C CNN
+F 2 "" H 6250 4600 60 0000 C CNN
+F 3 "" H 6250 4600 60 0000 C CNN
+ 14 6250 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6871458B
+P 4400 4600
+F 0 "U1" H 4450 4700 30 0000 C CNN
+F 1 "PORT" H 4400 4600 30 0000 C CNN
+F 2 "" H 4400 4600 60 0000 C CNN
+F 3 "" H 4400 4600 60 0000 C CNN
+ 10 4400 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 687145F8
+P 2550 4600
+F 0 "U1" H 2600 4700 30 0000 C CNN
+F 1 "PORT" H 2550 4600 30 0000 C CNN
+F 2 "" H 2550 4600 60 0000 C CNN
+F 3 "" H 2550 4600 60 0000 C CNN
+ 6 2550 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 687147CD
+P 1950 3400
+F 0 "U1" H 2000 3500 30 0000 C CNN
+F 1 "PORT" H 1950 3400 30 0000 C CNN
+F 2 "" H 1950 3400 60 0000 C CNN
+F 3 "" H 1950 3400 60 0000 C CNN
+ 2 1950 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68714C33
+P 2000 3550
+F 0 "U1" H 2050 3650 30 0000 C CNN
+F 1 "PORT" H 2000 3550 30 0000 C CNN
+F 2 "" H 2000 3550 60 0000 C CNN
+F 3 "" H 2000 3550 60 0000 C CNN
+ 3 2000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 687151F2
+P 2050 3750
+F 0 "U1" H 2100 3850 30 0000 C CNN
+F 1 "PORT" H 2050 3750 30 0000 C CNN
+F 2 "" H 2050 3750 60 0000 C CNN
+F 3 "" H 2050 3750 60 0000 C CNN
+ 4 2050 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 23 1 68715B07
+P 10400 3850
+F 0 "U1" H 10450 3950 30 0000 C CNN
+F 1 "PORT" H 10400 3850 30 0000 C CNN
+F 2 "" H 10400 3850 60 0000 C CNN
+F 3 "" H 10400 3850 60 0000 C CNN
+ 23 10400 3850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 22 1 68716166
+P 10350 4000
+F 0 "U1" H 10400 4100 30 0000 C CNN
+F 1 "PORT" H 10350 4000 30 0000 C CNN
+F 2 "" H 10350 4000 60 0000 C CNN
+F 3 "" H 10350 4000 60 0000 C CNN
+ 22 10350 4000
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2800 2750 2150 2750
+Wire Wire Line
+ 2150 2600 2150 4500
+Wire Wire Line
+ 2150 4500 2800 4500
+Wire Wire Line
+ 2150 2600 8250 2600
+Wire Wire Line
+ 8250 2600 8250 2750
+Connection ~ 2150 2750
+Wire Wire Line
+ 8250 4500 8250 4350
+Wire Wire Line
+ 8250 4350 2150 4350
+Connection ~ 2150 4350
+Wire Wire Line
+ 9300 3150 10200 3150
+Wire Wire Line
+ 10200 3150 10200 5100
+Wire Wire Line
+ 9300 4900 10200 4900
+Wire Wire Line
+ 10200 5100 4000 5100
+Wire Wire Line
+ 4000 5100 4000 4900
+Connection ~ 10200 4900
+Wire Wire Line
+ 4000 3150 4000 3350
+Wire Wire Line
+ 4000 3350 10200 3350
+Connection ~ 10200 3350
+Wire Wire Line
+ 4650 2750 4650 2600
+Connection ~ 4650 2600
+Wire Wire Line
+ 6500 2750 6500 2600
+Connection ~ 6500 2600
+Wire Wire Line
+ 5850 3150 5850 3350
+Connection ~ 5850 3350
+Wire Wire Line
+ 7700 3150 7700 3350
+Connection ~ 7700 3350
+Wire Wire Line
+ 7700 4900 7700 5100
+Connection ~ 7700 5100
+Wire Wire Line
+ 6500 4500 6500 4350
+Connection ~ 6500 4350
+Wire Wire Line
+ 5850 4900 5850 5100
+Connection ~ 5850 5100
+Wire Wire Line
+ 4650 4500 4650 4350
+Connection ~ 4650 4350
+Wire Wire Line
+ 2800 2950 2200 2950
+Wire Wire Line
+ 2200 2950 2200 4700
+Wire Wire Line
+ 2200 4700 2800 4700
+Wire Wire Line
+ 4650 2950 4300 2950
+Wire Wire Line
+ 4300 2950 4300 4700
+Wire Wire Line
+ 2200 3400 7900 3400
+Connection ~ 2200 3400
+Wire Wire Line
+ 6500 2950 6150 2950
+Wire Wire Line
+ 6150 2950 6150 4700
+Connection ~ 4300 3400
+Wire Wire Line
+ 8250 2950 7900 2950
+Wire Wire Line
+ 7900 2950 7900 4700
+Connection ~ 6150 3400
+Wire Wire Line
+ 4300 4700 4650 4700
+Wire Wire Line
+ 6150 4700 6500 4700
+Wire Wire Line
+ 7900 4700 8250 4700
+Connection ~ 7900 3400
+Wire Wire Line
+ 2800 3050 2250 3050
+Wire Wire Line
+ 2250 3050 2250 4800
+Wire Wire Line
+ 2250 4800 2800 4800
+Wire Wire Line
+ 4650 3050 4350 3050
+Wire Wire Line
+ 4350 3050 4350 4800
+Wire Wire Line
+ 2250 3550 7950 3550
+Connection ~ 2250 3550
+Wire Wire Line
+ 6500 3050 6200 3050
+Wire Wire Line
+ 6200 3050 6200 4800
+Connection ~ 4350 3550
+Wire Wire Line
+ 7950 3050 7950 4800
+Wire Wire Line
+ 7950 3050 8250 3050
+Connection ~ 6200 3550
+Wire Wire Line
+ 4350 4800 4650 4800
+Wire Wire Line
+ 6200 4800 6500 4800
+Wire Wire Line
+ 7950 4800 8250 4800
+Connection ~ 7950 3550
+Wire Wire Line
+ 2800 3150 2300 3150
+Wire Wire Line
+ 2300 3150 2300 4900
+Wire Wire Line
+ 2300 4900 2800 4900
+Wire Wire Line
+ 4650 3150 4400 3150
+Wire Wire Line
+ 4400 3150 4400 4900
+Wire Wire Line
+ 2300 3750 8000 3750
+Connection ~ 2300 3750
+Wire Wire Line
+ 6250 3150 6250 4900
+Wire Wire Line
+ 6250 3150 6500 3150
+Connection ~ 4400 3750
+Wire Wire Line
+ 8000 3150 8000 4900
+Wire Wire Line
+ 8000 3150 8250 3150
+Connection ~ 6250 3750
+Wire Wire Line
+ 4400 4900 4650 4900
+Wire Wire Line
+ 6250 4900 6500 4900
+Wire Wire Line
+ 8000 4900 8250 4900
+Connection ~ 8000 3750
+Wire Wire Line
+ 9300 2750 10150 2750
+Wire Wire Line
+ 10150 2750 10150 4500
+Wire Wire Line
+ 10150 4500 9300 4500
+Wire Wire Line
+ 7550 2750 7850 2750
+Wire Wire Line
+ 7850 2750 7850 4500
+Wire Wire Line
+ 4250 3850 10150 3850
+Connection ~ 10150 3850
+Wire Wire Line
+ 6100 4500 6100 2750
+Wire Wire Line
+ 6100 2750 5700 2750
+Connection ~ 7850 3850
+Wire Wire Line
+ 4250 4500 4250 2750
+Wire Wire Line
+ 4250 2750 3850 2750
+Connection ~ 6100 3850
+Wire Wire Line
+ 7850 4500 7550 4500
+Wire Wire Line
+ 5700 4500 6100 4500
+Wire Wire Line
+ 3850 4500 4250 4500
+Connection ~ 4250 3850
+Wire Wire Line
+ 9300 2850 10100 2850
+Wire Wire Line
+ 10100 2850 10100 4600
+Wire Wire Line
+ 10100 4600 9300 4600
+Wire Wire Line
+ 7550 2850 7800 2850
+Wire Wire Line
+ 7800 2850 7800 4600
+Wire Wire Line
+ 4200 4000 10100 4000
+Connection ~ 10100 4000
+Wire Wire Line
+ 7800 4600 7550 4600
+Connection ~ 7800 4000
+Wire Wire Line
+ 6050 4600 6050 2850
+Wire Wire Line
+ 5700 4600 6050 4600
+Wire Wire Line
+ 6050 2850 5700 2850
+Connection ~ 6050 4000
+Wire Wire Line
+ 4200 4600 4200 2850
+Wire Wire Line
+ 3850 4600 4200 4600
+Wire Wire Line
+ 4200 2850 3850 2850
+Connection ~ 4200 4000
+Wire Wire Line
+ 9300 2950 10050 2950
+Wire Wire Line
+ 10050 2950 10050 4700
+Wire Wire Line
+ 10050 4700 9300 4700
+Wire Wire Line
+ 7550 2950 7750 2950
+Wire Wire Line
+ 7750 2950 7750 4700
+Wire Wire Line
+ 4150 4100 10050 4100
+Connection ~ 10050 4100
+Wire Wire Line
+ 7750 4700 7550 4700
+Connection ~ 7750 4100
+Wire Wire Line
+ 6000 4700 6000 2950
+Wire Wire Line
+ 5700 4700 6000 4700
+Wire Wire Line
+ 6000 2950 5700 2950
+Connection ~ 6000 4100
+Wire Wire Line
+ 4150 4700 4150 2950
+Wire Wire Line
+ 3850 4700 4150 4700
+Wire Wire Line
+ 4150 2950 3850 2950
+Connection ~ 4150 4100
+$Comp
+L PORT U1
+U 21 1 68716B57
+P 10300 4100
+F 0 "U1" H 10350 4200 30 0000 C CNN
+F 1 "PORT" H 10300 4100 30 0000 C CNN
+F 2 "" H 10300 4100 60 0000 C CNN
+F 3 "" H 10300 4100 60 0000 C CNN
+ 21 10300 4100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68716CBD
+P 4250 3050
+F 0 "U1" H 4300 3150 30 0000 C CNN
+F 1 "PORT" H 4250 3050 30 0000 C CNN
+F 2 "" H 4250 3050 60 0000 C CNN
+F 3 "" H 4250 3050 60 0000 C CNN
+ 7 4250 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68716D64
+P 6100 3050
+F 0 "U1" H 6150 3150 30 0000 C CNN
+F 1 "PORT" H 6100 3050 30 0000 C CNN
+F 2 "" H 6100 3050 60 0000 C CNN
+F 3 "" H 6100 3050 60 0000 C CNN
+ 11 6100 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 68716DFD
+P 7950 3050
+F 0 "U1" H 8000 3150 30 0000 C CNN
+F 1 "PORT" H 7950 3050 30 0000 C CNN
+F 2 "" H 7950 3050 60 0000 C CNN
+F 3 "" H 7950 3050 60 0000 C CNN
+ 15 7950 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 19 1 68716E98
+P 9700 3050
+F 0 "U1" H 9750 3150 30 0000 C CNN
+F 1 "PORT" H 9700 3050 30 0000 C CNN
+F 2 "" H 9700 3050 60 0000 C CNN
+F 3 "" H 9700 3050 60 0000 C CNN
+ 19 9700 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 20 1 68716FB5
+P 9700 4800
+F 0 "U1" H 9750 4900 30 0000 C CNN
+F 1 "PORT" H 9700 4800 30 0000 C CNN
+F 2 "" H 9700 4800 60 0000 C CNN
+F 3 "" H 9700 4800 60 0000 C CNN
+ 20 9700 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 68717072
+P 7950 4800
+F 0 "U1" H 8000 4900 30 0000 C CNN
+F 1 "PORT" H 7950 4800 30 0000 C CNN
+F 2 "" H 7950 4800 60 0000 C CNN
+F 3 "" H 7950 4800 60 0000 C CNN
+ 16 7950 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 68717115
+P 6100 4800
+F 0 "U1" H 6150 4900 30 0000 C CNN
+F 1 "PORT" H 6100 4800 30 0000 C CNN
+F 2 "" H 6100 4800 60 0000 C CNN
+F 3 "" H 6100 4800 60 0000 C CNN
+ 12 6100 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 687171B4
+P 4250 4800
+F 0 "U1" H 4300 4900 30 0000 C CNN
+F 1 "PORT" H 4250 4800 30 0000 C CNN
+F 2 "" H 4250 4800 60 0000 C CNN
+F 3 "" H 4250 4800 60 0000 C CNN
+ 8 4250 4800
+ -1 0 0 -1
+$EndComp
+$Comp
+L Rnk_Blk X1
+U 1 1 6878DC64
+P 3300 2950
+F 0 "X1" H 3300 2950 60 0000 C CNN
+F 1 "Rnk_Blk" H 3300 2650 60 0000 C CNN
+F 2 "" H 3300 2950 60 0001 C CNN
+F 3 "" H 3300 2950 60 0001 C CNN
+ 1 3300 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3850 3050 4000 3050
+Wire Wire Line
+ 3850 3150 4000 3150
+$Comp
+L Rnk_Blk X3
+U 1 1 6878E1D0
+P 5150 2950
+F 0 "X3" H 5150 2950 60 0000 C CNN
+F 1 "Rnk_Blk" H 5150 2650 60 0000 C CNN
+F 2 "" H 5150 2950 60 0001 C CNN
+F 3 "" H 5150 2950 60 0001 C CNN
+ 1 5150 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5850 3050 5700 3050
+Wire Wire Line
+ 5850 3150 5700 3150
+$Comp
+L Rnk_Blk X5
+U 1 1 6878E69D
+P 7000 2950
+F 0 "X5" H 7000 2950 60 0000 C CNN
+F 1 "Rnk_Blk" H 7000 2650 60 0000 C CNN
+F 2 "" H 7000 2950 60 0001 C CNN
+F 3 "" H 7000 2950 60 0001 C CNN
+ 1 7000 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7700 3050 7550 3050
+Wire Wire Line
+ 7550 3150 7700 3150
+$Comp
+L Rnk_Blk X7
+U 1 1 6878EB72
+P 8750 2950
+F 0 "X7" H 8750 2950 60 0000 C CNN
+F 1 "Rnk_Blk" H 8750 2650 60 0000 C CNN
+F 2 "" H 8750 2950 60 0001 C CNN
+F 3 "" H 8750 2950 60 0001 C CNN
+ 1 8750 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9450 3050 9300 3050
+$Comp
+L Rnk_Blk X2
+U 1 1 6878F17E
+P 3300 4700
+F 0 "X2" H 3300 4700 60 0000 C CNN
+F 1 "Rnk_Blk" H 3300 4400 60 0000 C CNN
+F 2 "" H 3300 4700 60 0001 C CNN
+F 3 "" H 3300 4700 60 0001 C CNN
+ 1 3300 4700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4000 4800 3850 4800
+Wire Wire Line
+ 4000 4900 3850 4900
+$Comp
+L Rnk_Blk X4
+U 1 1 6878F665
+P 5150 4700
+F 0 "X4" H 5150 4700 60 0000 C CNN
+F 1 "Rnk_Blk" H 5150 4400 60 0000 C CNN
+F 2 "" H 5150 4700 60 0001 C CNN
+F 3 "" H 5150 4700 60 0001 C CNN
+ 1 5150 4700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5850 4800 5700 4800
+Wire Wire Line
+ 5850 4900 5700 4900
+$Comp
+L Rnk_Blk X6
+U 1 1 6878FB38
+P 7000 4700
+F 0 "X6" H 7000 4700 60 0000 C CNN
+F 1 "Rnk_Blk" H 7000 4400 60 0000 C CNN
+F 2 "" H 7000 4700 60 0001 C CNN
+F 3 "" H 7000 4700 60 0001 C CNN
+ 1 7000 4700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7700 4800 7550 4800
+Wire Wire Line
+ 7700 4900 7550 4900
+$Comp
+L Rnk_Blk X8
+U 1 1 6878FFD1
+P 8750 4700
+F 0 "X8" H 8750 4700 60 0000 C CNN
+F 1 "Rnk_Blk" H 8750 4400 60 0000 C CNN
+F 2 "" H 8750 4700 60 0001 C CNN
+F 3 "" H 8750 4700 60 0001 C CNN
+ 1 8750 4700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9450 4800 9300 4800
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/SN74LS548.sub b/library/SubcircuitLibrary/SN74LS548/SN74LS548.sub
new file mode 100644
index 000000000..910a910bd
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/SN74LS548.sub
@@ -0,0 +1,17 @@
+* Subcircuit SN74LS548
+.subckt SN74LS548 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_
+* h:\esim\esim\library\subcircuitlibrary\sn74ls548\sn74ls548.cir
+.include Rnk_Blk.sub
+
+* s c m o d e
+x1 net-_u1-pad5_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad7_ Rnk_Blk
+x3 net-_u1-pad9_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad11_ Rnk_Blk
+x5 net-_u1-pad13_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad15_ Rnk_Blk
+x7 net-_u1-pad17_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad19_ Rnk_Blk
+x2 net-_u1-pad6_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad8_ Rnk_Blk
+x4 net-_u1-pad10_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad12_ Rnk_Blk
+x6 net-_u1-pad14_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad16_ Rnk_Blk
+x8 net-_u1-pad18_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad24_ net-_u1-pad4_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad20_ Rnk_Blk
+* Control Statements
+
+.ends SN74LS548
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/SN74LS548_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS548/SN74LS548_Previous_Values.xml
new file mode 100644
index 000000000..d52c3ae76
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/SN74LS548_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettH:\esim\eSim\library\SubcircuitLibrary\Rnk_BlkH:\esim\eSim\library\SubcircuitLibrary\Rnk_BlkH:\esim\eSim\library\SubcircuitLibrary\Rnk_BlkH:\esim\eSim\library\SubcircuitLibrary\Rnk_BlkH:\esim\eSim\library\SubcircuitLibrary\Rnk_BlkH:\esim\eSim\library\SubcircuitLibrary\Rnk_BlkH:\esim\eSim\library\SubcircuitLibrary\Rnk_BlkH:\esim\eSim\library\SubcircuitLibrary\Rnk_BlktruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/analysis b/library/SubcircuitLibrary/SN74LS548/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/tri_state-cache.lib b/library/SubcircuitLibrary/SN74LS548/tri_state-cache.lib
new file mode 100644
index 000000000..e99b45ce5
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/tri_state-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS548/tri_state.bak b/library/SubcircuitLibrary/SN74LS548/tri_state.bak
new file mode 100644
index 000000000..42f6325e1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/tri_state.bak
@@ -0,0 +1,195 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:tri_state-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 686E04ED
+P 5150 2450
+F 0 "SC1" H 5200 2750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 2537 50 0000 R CNN
+F 2 "" H 5150 950 50 0001 C CNN
+F 3 "" H 5150 2450 50 0001 C CNN
+ 1 5150 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 686E0554
+P 5150 3250
+F 0 "SC2" H 5200 3550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5450 3337 50 0000 R CNN
+F 2 "" H 5150 1750 50 0001 C CNN
+F 3 "" H 5150 3250 50 0001 C CNN
+ 1 5150 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686E05B6
+P 9300 2250
+F 0 "scmode1" H 9300 2400 98 0000 C CNB
+F 1 "SKY130mode" H 9300 2150 118 0000 C CNB
+F 2 "" H 9300 2400 60 0001 C CNN
+F 3 "" H 9300 2400 60 0001 C CNN
+ 1 9300 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E061D
+P 4200 2800
+F 0 "U1" H 4250 2900 30 0000 C CNN
+F 1 "PORT" H 4200 2800 30 0000 C CNN
+F 2 "" H 4200 2800 60 0000 C CNN
+F 3 "" H 4200 2800 60 0000 C CNN
+ 1 4200 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E069C
+P 5050 1900
+F 0 "U1" H 5100 2000 30 0000 C CNN
+F 1 "PORT" H 5050 1900 30 0000 C CNN
+F 2 "" H 5050 1900 60 0000 C CNN
+F 3 "" H 5050 1900 60 0000 C CNN
+ 2 5050 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E0725
+P 5100 3750
+F 0 "U1" H 5150 3850 30 0000 C CNN
+F 1 "PORT" H 5100 3750 30 0000 C CNN
+F 2 "" H 5100 3750 60 0000 C CNN
+F 3 "" H 5100 3750 60 0000 C CNN
+ 3 5100 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E0750
+P 6800 2800
+F 0 "U1" H 6850 2900 30 0000 C CNN
+F 1 "PORT" H 6800 2800 30 0000 C CNN
+F 2 "" H 6800 2800 60 0000 C CNN
+F 3 "" H 6800 2800 60 0000 C CNN
+ 5 6800 2800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E0793
+P 6200 2150
+F 0 "U1" H 6250 2250 30 0000 C CNN
+F 1 "PORT" H 6200 2150 30 0000 C CNN
+F 2 "" H 6200 2150 60 0000 C CNN
+F 3 "" H 6200 2150 60 0000 C CNN
+ 4 6200 2150
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4850 2450 4850 3250
+Wire Wire Line
+ 4450 2800 4850 2800
+Connection ~ 4850 2800
+Wire Wire Line
+ 5350 2750 5350 2950
+Wire Wire Line
+ 5400 2450 5250 2450
+Wire Wire Line
+ 5400 1900 5400 2450
+Wire Wire Line
+ 5400 2150 5350 2150
+Wire Wire Line
+ 5300 1900 5400 1900
+Connection ~ 5400 2150
+Wire Wire Line
+ 5250 3250 5400 3250
+Wire Wire Line
+ 5400 3250 5400 3750
+Wire Wire Line
+ 5400 3550 5350 3550
+Wire Wire Line
+ 5400 3750 5350 3750
+Connection ~ 5400 3550
+Wire Wire Line
+ 5650 2800 5350 2800
+Connection ~ 5350 2800
+Wire Wire Line
+ 5950 2850 5950 2700
+Wire Wire Line
+ 5550 2850 5950 2850
+Wire Wire Line
+ 5550 2850 5550 2800
+Connection ~ 5550 2800
+Wire Wire Line
+ 6250 2800 6550 2800
+Wire Wire Line
+ 5950 2300 5950 2150
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 686E7F5A
+P 5950 2600
+F 0 "SC3" H 6000 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6250 2687 50 0000 R CNN
+F 2 "" H 5950 1100 50 0001 C CNN
+F 3 "" H 5950 2600 50 0001 C CNN
+ 1 5950 2600
+ 0 1 1 0
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/tri_state.cir b/library/SubcircuitLibrary/SN74LS548/tri_state.cir
new file mode 100644
index 000000000..344a32960
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/tri_state.cir
@@ -0,0 +1,15 @@
+* H:\esim\eSim\library\SubcircuitLibrary\tri_state\tri_state.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/16/25 21:17:02
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC2-Pad3_ Net-_SC2-Pad3_ sky130_fd_pr__nfet_01v8
+scmode1 SKY130mode
+U1 Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC2-Pad3_ Net-_SC3-Pad2_ Net-_SC3-Pad1_ PORT
+SC3 Net-_SC3-Pad1_ Net-_SC3-Pad2_ Net-_SC1-Pad1_ Net-_SC1-Pad1_ sky130_fd_pr__nfet_01v8
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/tri_state.cir.out b/library/SubcircuitLibrary/SN74LS548/tri_state.cir.out
new file mode 100644
index 000000000..b8ee10126
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/tri_state.cir.out
@@ -0,0 +1,17 @@
+* h:\esim\esim\library\subcircuitlibrary\tri_state\tri_state.cir
+
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* u1 net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc3-pad1_ port
+xsc3 net-_sc3-pad1_ net-_sc3-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS548/tri_state.pro b/library/SubcircuitLibrary/SN74LS548/tri_state.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/tri_state.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LS548/tri_state.sch b/library/SubcircuitLibrary/SN74LS548/tri_state.sch
new file mode 100644
index 000000000..42f6325e1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/tri_state.sch
@@ -0,0 +1,195 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:tri_state-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 686E04ED
+P 5150 2450
+F 0 "SC1" H 5200 2750 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5450 2537 50 0000 R CNN
+F 2 "" H 5150 950 50 0001 C CNN
+F 3 "" H 5150 2450 50 0001 C CNN
+ 1 5150 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC2
+U 1 1 686E0554
+P 5150 3250
+F 0 "SC2" H 5200 3550 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5450 3337 50 0000 R CNN
+F 2 "" H 5150 1750 50 0001 C CNN
+F 3 "" H 5150 3250 50 0001 C CNN
+ 1 5150 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 686E05B6
+P 9300 2250
+F 0 "scmode1" H 9300 2400 98 0000 C CNB
+F 1 "SKY130mode" H 9300 2150 118 0000 C CNB
+F 2 "" H 9300 2400 60 0001 C CNN
+F 3 "" H 9300 2400 60 0001 C CNN
+ 1 9300 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686E061D
+P 4200 2800
+F 0 "U1" H 4250 2900 30 0000 C CNN
+F 1 "PORT" H 4200 2800 30 0000 C CNN
+F 2 "" H 4200 2800 60 0000 C CNN
+F 3 "" H 4200 2800 60 0000 C CNN
+ 1 4200 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686E069C
+P 5050 1900
+F 0 "U1" H 5100 2000 30 0000 C CNN
+F 1 "PORT" H 5050 1900 30 0000 C CNN
+F 2 "" H 5050 1900 60 0000 C CNN
+F 3 "" H 5050 1900 60 0000 C CNN
+ 2 5050 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686E0725
+P 5100 3750
+F 0 "U1" H 5150 3850 30 0000 C CNN
+F 1 "PORT" H 5100 3750 30 0000 C CNN
+F 2 "" H 5100 3750 60 0000 C CNN
+F 3 "" H 5100 3750 60 0000 C CNN
+ 3 5100 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686E0750
+P 6800 2800
+F 0 "U1" H 6850 2900 30 0000 C CNN
+F 1 "PORT" H 6800 2800 30 0000 C CNN
+F 2 "" H 6800 2800 60 0000 C CNN
+F 3 "" H 6800 2800 60 0000 C CNN
+ 5 6800 2800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686E0793
+P 6200 2150
+F 0 "U1" H 6250 2250 30 0000 C CNN
+F 1 "PORT" H 6200 2150 30 0000 C CNN
+F 2 "" H 6200 2150 60 0000 C CNN
+F 3 "" H 6200 2150 60 0000 C CNN
+ 4 6200 2150
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4850 2450 4850 3250
+Wire Wire Line
+ 4450 2800 4850 2800
+Connection ~ 4850 2800
+Wire Wire Line
+ 5350 2750 5350 2950
+Wire Wire Line
+ 5400 2450 5250 2450
+Wire Wire Line
+ 5400 1900 5400 2450
+Wire Wire Line
+ 5400 2150 5350 2150
+Wire Wire Line
+ 5300 1900 5400 1900
+Connection ~ 5400 2150
+Wire Wire Line
+ 5250 3250 5400 3250
+Wire Wire Line
+ 5400 3250 5400 3750
+Wire Wire Line
+ 5400 3550 5350 3550
+Wire Wire Line
+ 5400 3750 5350 3750
+Connection ~ 5400 3550
+Wire Wire Line
+ 5650 2800 5350 2800
+Connection ~ 5350 2800
+Wire Wire Line
+ 5950 2850 5950 2700
+Wire Wire Line
+ 5550 2850 5950 2850
+Wire Wire Line
+ 5550 2850 5550 2800
+Connection ~ 5550 2800
+Wire Wire Line
+ 6250 2800 6550 2800
+Wire Wire Line
+ 5950 2300 5950 2150
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 686E7F5A
+P 5950 2600
+F 0 "SC3" H 6000 2900 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 6250 2687 50 0000 R CNN
+F 2 "" H 5950 1100 50 0001 C CNN
+F 3 "" H 5950 2600 50 0001 C CNN
+ 1 5950 2600
+ 0 1 1 0
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS548/tri_state.sub b/library/SubcircuitLibrary/SN74LS548/tri_state.sub
new file mode 100644
index 000000000..603f6daee
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/tri_state.sub
@@ -0,0 +1,11 @@
+* Subcircuit tri_state
+.subckt tri_state net-_sc1-pad2_ net-_sc1-pad3_ net-_sc2-pad3_ net-_sc3-pad2_ net-_sc3-pad1_
+* h:\esim\esim\library\subcircuitlibrary\tri_state\tri_state.cir
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc2-pad3_ net-_sc2-pad3_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+xsc3 net-_sc3-pad1_ net-_sc3-pad2_ net-_sc1-pad1_ net-_sc1-pad1_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* Control Statements
+
+.ends tri_state
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LS548/tri_state_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS548/tri_state_Previous_Values.xml
new file mode 100644
index 000000000..3490db45b
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LS548/tri_state_Previous_Values.xml
@@ -0,0 +1 @@
+H:\esim\eSim\library\sky130_fd_pr\models\sky130.lib.spicettw=3 l=0.15w=1 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/NMOS-5um.lib b/library/SubcircuitLibrary/SN74LVC1G3157/NMOS-5um.lib
new file mode 100644
index 000000000..a237e1fe3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/NMOS-5um.lib
@@ -0,0 +1,5 @@
+* 5um technology
+
+.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7
++ Level=1
++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/PMOS-5um.lib b/library/SubcircuitLibrary/SN74LVC1G3157/PMOS-5um.lib
new file mode 100644
index 000000000..9c3ed9760
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/PMOS-5um.lib
@@ -0,0 +1,5 @@
+*5um technology
+
+.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65
++ Level=1
++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n )
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157-cache.lib b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157-cache.lib
new file mode 100644
index 000000000..3b7d214a1
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir
new file mode 100644
index 000000000..85fc047cf
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir
@@ -0,0 +1,20 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LVC1G3157\SN74LVC1G3157.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/25 13:13:46
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U1-Pad2_ Net-_U2-Pad2_ d_inverter
+U5 Net-_U2-Pad2_ Net-_M2-Pad2_ dac_bridge_1
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad4_ eSim_MOS_P
+M3 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M3-Pad4_ eSim_MOS_N
+M2 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad3_ Net-_M1-Pad4_ eSim_MOS_P
+M4 Net-_M1-Pad1_ Net-_M4-Pad2_ Net-_M2-Pad3_ Net-_M3-Pad4_ eSim_MOS_N
+U4 Net-_U1-Pad2_ Net-_M4-Pad2_ dac_bridge_1
+U3 Net-_U1-Pad2_ Net-_M1-Pad2_ dac_bridge_1
+U6 Net-_M1-Pad3_ Net-_M3-Pad4_ Net-_M2-Pad3_ Net-_M1-Pad1_ Net-_M1-Pad4_ Net-_U1-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir.out b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir.out
new file mode 100644
index 000000000..f29415042
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.cir.out
@@ -0,0 +1,38 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74lvc1g3157\sn74lvc1g3157.cir
+
+.include NMOS-5um.lib
+.include PMOS-5um.lib
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u5 net-_u2-pad2_ net-_m2-pad2_ dac_bridge_1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m3 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m3-pad4_ mos_n W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m4 net-_m1-pad1_ net-_m4-pad2_ net-_m2-pad3_ net-_m3-pad4_ mos_n W=100u L=100u M=1
+* u4 net-_u1-pad2_ net-_m4-pad2_ dac_bridge_1
+* u3 net-_u1-pad2_ net-_m1-pad2_ dac_bridge_1
+* u6 net-_m1-pad3_ net-_m3-pad4_ net-_m2-pad3_ net-_m1-pad1_ net-_m1-pad4_ net-_u1-pad1_ port
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m2-pad2_ ] u5
+a4 [net-_u1-pad2_ ] [net-_m4-pad2_ ] u4
+a5 [net-_u1-pad2_ ] [net-_m1-pad2_ ] u3
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.pro b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.proj b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.proj
new file mode 100644
index 000000000..14734c208
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.proj
@@ -0,0 +1 @@
+schematicFile SN74LVC1G3157.sch
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sch b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sch
new file mode 100644
index 000000000..40a02c9fc
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sch
@@ -0,0 +1,318 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74LVC1G3157-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_inverter U1
+U 1 1 683FDC62
+P 3850 4350
+F 0 "U1" H 3850 4250 60 0000 C CNN
+F 1 "d_inverter" H 3850 4500 60 0000 C CNN
+F 2 "" H 3900 4300 60 0000 C CNN
+F 3 "" H 3900 4300 60 0000 C CNN
+ 1 3850 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 683FDCF4
+P 4750 4350
+F 0 "U2" H 4750 4250 60 0000 C CNN
+F 1 "d_inverter" H 4750 4500 60 0000 C CNN
+F 2 "" H 4800 4300 60 0000 C CNN
+F 3 "" H 4800 4300 60 0000 C CNN
+ 1 4750 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4150 4350 4300 4350
+Wire Wire Line
+ 4300 4350 4350 4350
+Wire Wire Line
+ 4350 4350 4450 4350
+$Comp
+L dac_bridge_1 U5
+U 1 1 683FDDA0
+P 5850 4400
+F 0 "U5" H 5850 4400 60 0000 C CNN
+F 1 "dac_bridge_1" H 5850 4550 60 0000 C CNN
+F 2 "" H 5850 4400 60 0000 C CNN
+F 3 "" H 5850 4400 60 0000 C CNN
+ 1 5850 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5050 4350 5250 4350
+$Comp
+L eSim_MOS_P M1
+U 1 1 683FDDD1
+P 7000 3400
+F 0 "M1" H 6950 3450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 7050 3550 50 0000 R CNN
+F 2 "" H 7250 3500 29 0000 C CNN
+F 3 "" H 7050 3400 60 0000 C CNN
+ 1 7000 3400
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_MOS_N M3
+U 1 1 683FDE2F
+P 7200 4100
+F 0 "M3" H 7200 3950 50 0000 R CNN
+F 1 "eSim_MOS_N" H 7300 4050 50 0000 R CNN
+F 2 "" H 7500 3800 29 0000 C CNN
+F 3 "" H 7300 3900 60 0000 C CNN
+ 1 7200 4100
+ 0 1 -1 0
+$EndComp
+Wire Wire Line
+ 6800 3550 6800 3750
+Wire Wire Line
+ 6800 3750 6800 3900
+Wire Wire Line
+ 7200 3550 7200 3700
+Wire Wire Line
+ 7200 3700 7200 3900
+$Comp
+L eSim_MOS_P M2
+U 1 1 683FDF1C
+P 7000 4700
+F 0 "M2" H 6950 4750 50 0000 R CNN
+F 1 "eSim_MOS_P" H 7050 4850 50 0000 R CNN
+F 2 "" H 7250 4800 29 0000 C CNN
+F 3 "" H 7050 4700 60 0000 C CNN
+ 1 7000 4700
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_MOS_N M4
+U 1 1 683FDF22
+P 7200 5400
+F 0 "M4" H 7200 5250 50 0000 R CNN
+F 1 "eSim_MOS_N" H 7300 5350 50 0000 R CNN
+F 2 "" H 7500 5100 29 0000 C CNN
+F 3 "" H 7300 5200 60 0000 C CNN
+ 1 7200 5400
+ 0 1 -1 0
+$EndComp
+Wire Wire Line
+ 6800 4850 6800 5050
+Wire Wire Line
+ 6800 5050 6800 5200
+Wire Wire Line
+ 7200 4850 7200 5000
+Wire Wire Line
+ 7200 5000 7200 5200
+Wire Wire Line
+ 7000 4200 7000 4350
+Wire Wire Line
+ 7000 4350 7000 4550
+Wire Wire Line
+ 6400 4350 7000 4350
+Connection ~ 7000 4350
+$Comp
+L dac_bridge_1 U4
+U 1 1 683FE0BF
+P 5500 5350
+F 0 "U4" H 5500 5350 60 0000 C CNN
+F 1 "dac_bridge_1" H 5500 5500 60 0000 C CNN
+F 2 "" H 5500 5350 60 0000 C CNN
+F 3 "" H 5500 5350 60 0000 C CNN
+ 1 5500 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_1 U3
+U 1 1 683FE0F7
+P 5500 3400
+F 0 "U3" H 5500 3400 60 0000 C CNN
+F 1 "dac_bridge_1" H 5500 3550 60 0000 C CNN
+F 2 "" H 5500 3400 60 0000 C CNN
+F 3 "" H 5500 3400 60 0000 C CNN
+ 1 5500 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4300 4350 4300 3350
+Wire Wire Line
+ 4300 3350 4900 3350
+Connection ~ 4300 4350
+Wire Wire Line
+ 6050 3350 6900 3350
+Wire Wire Line
+ 6900 3350 6900 3250
+Wire Wire Line
+ 6900 3250 7000 3250
+Wire Wire Line
+ 4350 4350 4350 5300
+Wire Wire Line
+ 4350 5300 4900 5300
+Connection ~ 4350 4350
+Wire Wire Line
+ 6050 5300 6500 5300
+Wire Wire Line
+ 6500 5300 6500 5500
+Wire Wire Line
+ 6500 5500 7000 5500
+Wire Wire Line
+ 7200 3700 7650 3700
+Wire Wire Line
+ 7650 3700 7650 4300
+Wire Wire Line
+ 7650 4300 7650 4550
+Wire Wire Line
+ 7650 4550 7650 5000
+Wire Wire Line
+ 7650 5000 7200 5000
+Connection ~ 7200 5000
+Connection ~ 7200 3700
+$Comp
+L PORT U6
+U 4 1 683FE1B2
+P 8000 4300
+F 0 "U6" H 8050 4400 30 0000 C CNN
+F 1 "PORT" H 8000 4300 30 0000 C CNN
+F 2 "" H 8000 4300 60 0000 C CNN
+F 3 "" H 8000 4300 60 0000 C CNN
+ 4 8000 4300
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U6
+U 2 1 683FE61F
+P 7850 5100
+F 0 "U6" H 7900 5200 30 0000 C CNN
+F 1 "PORT" H 7850 5100 30 0000 C CNN
+F 2 "" H 7850 5100 60 0000 C CNN
+F 3 "" H 7850 5100 60 0000 C CNN
+ 2 7850 5100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U6
+U 3 1 683FE668
+P 6400 5050
+F 0 "U6" H 6450 5150 30 0000 C CNN
+F 1 "PORT" H 6400 5050 30 0000 C CNN
+F 2 "" H 6400 5050 60 0000 C CNN
+F 3 "" H 6400 5050 60 0000 C CNN
+ 3 6400 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U6
+U 1 1 683FE6AD
+P 6250 3750
+F 0 "U6" H 6300 3850 30 0000 C CNN
+F 1 "PORT" H 6250 3750 30 0000 C CNN
+F 2 "" H 6250 3750 60 0000 C CNN
+F 3 "" H 6250 3750 60 0000 C CNN
+ 1 6250 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U6
+U 5 1 683FE6F2
+P 6250 4650
+F 0 "U6" H 6300 4750 30 0000 C CNN
+F 1 "PORT" H 6250 4650 30 0000 C CNN
+F 2 "" H 6250 4650 60 0000 C CNN
+F 3 "" H 6250 4650 60 0000 C CNN
+ 5 6250 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U6
+U 6 1 683FE73B
+P 3050 4350
+F 0 "U6" H 3100 4450 30 0000 C CNN
+F 1 "PORT" H 3050 4350 30 0000 C CNN
+F 2 "" H 3050 4350 60 0000 C CNN
+F 3 "" H 3050 4350 60 0000 C CNN
+ 6 3050 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6850 3650 6650 3650
+Wire Wire Line
+ 6650 3650 6650 4650
+Wire Wire Line
+ 6650 4650 6650 4950
+Wire Wire Line
+ 6650 4950 6850 4950
+Wire Wire Line
+ 6500 4650 6650 4650
+Connection ~ 6650 4650
+Wire Wire Line
+ 6850 3800 7500 3800
+Wire Wire Line
+ 7500 3800 7500 5100
+Wire Wire Line
+ 6850 5100 7500 5100
+Wire Wire Line
+ 7500 5100 7600 5100
+Connection ~ 7500 5100
+Wire Wire Line
+ 7750 4300 7650 4300
+Connection ~ 7650 4300
+Wire Wire Line
+ 6500 3750 6800 3750
+Connection ~ 6800 3750
+Wire Wire Line
+ 6650 5050 6800 5050
+Connection ~ 6800 5050
+Wire Wire Line
+ 3300 4350 3550 4350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sub b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sub
new file mode 100644
index 000000000..58166855c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157.sub
@@ -0,0 +1,32 @@
+* Subcircuit SN74LVC1G3157
+.subckt SN74LVC1G3157 net-_m1-pad3_ net-_m3-pad4_ net-_m2-pad3_ net-_m1-pad1_ net-_m1-pad4_ net-_u1-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\sn74lvc1g3157\sn74lvc1g3157.cir
+.include NMOS-5um.lib
+.include PMOS-5um.lib
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad2_ net-_u2-pad2_ d_inverter
+* u5 net-_u2-pad2_ net-_m2-pad2_ dac_bridge_1
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m3 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m3-pad4_ mos_n W=100u L=100u M=1
+m2 net-_m1-pad1_ net-_m2-pad2_ net-_m2-pad3_ net-_m1-pad4_ mos_p W=100u L=100u M=1
+m4 net-_m1-pad1_ net-_m4-pad2_ net-_m2-pad3_ net-_m3-pad4_ mos_n W=100u L=100u M=1
+* u4 net-_u1-pad2_ net-_m4-pad2_ dac_bridge_1
+* u3 net-_u1-pad2_ net-_m1-pad2_ dac_bridge_1
+a1 net-_u1-pad1_ net-_u1-pad2_ u1
+a2 net-_u1-pad2_ net-_u2-pad2_ u2
+a3 [net-_u2-pad2_ ] [net-_m2-pad2_ ] u5
+a4 [net-_u1-pad2_ ] [net-_m4-pad2_ ] u4
+a5 [net-_u1-pad2_ ] [net-_m1-pad2_ ] u3
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u3 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Control Statements
+
+.ends SN74LVC1G3157
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157_Previous_Values.xml b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157_Previous_Values.xml
new file mode 100644
index 000000000..46288713c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74LVC1G3157_Previous_Values.xml
@@ -0,0 +1 @@
+d_inverterd_inverterdac_bridgedac_bridgedac_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-5um.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-5um.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test-cache.lib b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test-cache.lib
new file mode 100644
index 000000000..c99ca626e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test-cache.lib
@@ -0,0 +1,117 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 w
+X - 2 0 -450 300 U 50 50 1 1 w
+ENDDRAW
+ENDDEF
+#
+# SN74LVC1G3157
+#
+DEF SN74LVC1G3157 X 0 40 Y Y 1 F N
+F0 "X" 0 -600 60 H V C CNN
+F1 "SN74LVC1G3157" 50 650 60 H V C CNN
+F2 "" 0 -600 60 H I C CNN
+F3 "" 0 -600 60 H I C CNN
+DRAW
+S -400 500 400 -450 0 1 0 N
+S 400 -350 400 -350 0 1 0 N
+X B2 1 -600 300 200 R 50 50 1 1 I
+X Gnd 2 -600 0 200 R 50 50 1 1 I
+X B1 3 -600 -250 200 R 50 50 1 1 I
+X A 4 600 -300 200 L 50 50 1 1 O
+X Vcc 5 600 0 200 L 50 50 1 1 I
+X S 6 600 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_VCC
+#
+DEF eSim_VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "eSim_VCC" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir
new file mode 100644
index 000000000..35ab3cbc8
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir
@@ -0,0 +1,17 @@
+* C:\Users\pavithra\eSim-Workspace\SN74VC1G3157_test\SN74VC1G3157_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/04/25 13:14:27
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v1 Net-_X1-Pad3_ GND DC
+v2 Net-_X1-Pad1_ GND DC
+U2 S Net-_U2-Pad2_ adc_bridge_1
+v3 S GND pulse
+U3 Out plot_v1
+U1 S plot_v1
+X1 Net-_X1-Pad1_ GND Net-_X1-Pad3_ Out VCC Net-_U2-Pad2_ SN74LVC1G3157
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir.out b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir.out
new file mode 100644
index 000000000..d025cccff
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.cir.out
@@ -0,0 +1,24 @@
+* c:\users\pavithra\esim-workspace\sn74vc1g3157_test\sn74vc1g3157_test.cir
+
+.include SN74LVC1G3157.sub
+v1 net-_x1-pad3_ gnd dc 1
+v2 net-_x1-pad1_ gnd dc 3
+* u2 s net-_u2-pad2_ adc_bridge_1
+v3 s gnd pulse(5 0 0 0.5n 0.5n 1m 2m)
+* u3 out plot_v1
+* u1 s plot_v1
+x1 net-_x1-pad1_ gnd net-_x1-pad3_ out vcc net-_u2-pad2_ SN74LVC1G3157
+a1 [s ] [net-_u2-pad2_ ] u2
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 10e-06 10e-03 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+
+plot v(s) + 6 v(out)
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.pro b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.proj b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.proj
new file mode 100644
index 000000000..1d4fe58e3
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.proj
@@ -0,0 +1 @@
+schematicFile SN74VC1G3157_test.sch
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.sch b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.sch
new file mode 100644
index 000000000..ad5a8b942
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test.sch
@@ -0,0 +1,230 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74VC1G3157_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_GND #PWR01
+U 1 1 683FE1D3
+P 4950 3550
+F 0 "#PWR01" H 4950 3300 50 0001 C CNN
+F 1 "eSim_GND" H 4950 3400 50 0000 C CNN
+F 2 "" H 4950 3550 50 0001 C CNN
+F 3 "" H 4950 3550 50 0001 C CNN
+ 1 4950 3550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4950 3550 5100 3550
+$Comp
+L eSim_VCC #PWR02
+U 1 1 683FE1EC
+P 6450 3500
+F 0 "#PWR02" H 6450 3350 50 0001 C CNN
+F 1 "eSim_VCC" H 6450 3650 50 0000 C CNN
+F 2 "" H 6450 3500 50 0001 C CNN
+F 3 "" H 6450 3500 50 0001 C CNN
+ 1 6450 3500
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6450 3500 6450 3550
+Wire Wire Line
+ 6450 3550 6300 3550
+$Comp
+L DC v1
+U 1 1 683FE208
+P 5000 4300
+F 0 "v1" H 4800 4400 60 0000 C CNN
+F 1 "DC" H 4800 4250 60 0000 C CNN
+F 2 "R1" H 4700 4300 60 0000 C CNN
+F 3 "" H 5000 4300 60 0000 C CNN
+ 1 5000 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4550 3250 5100 3250
+$Comp
+L eSim_GND #PWR03
+U 1 1 683FE254
+P 4550 4250
+F 0 "#PWR03" H 4550 4000 50 0001 C CNN
+F 1 "eSim_GND" H 4550 4100 50 0000 C CNN
+F 2 "" H 4550 4250 50 0001 C CNN
+F 3 "" H 4550 4250 50 0001 C CNN
+ 1 4550 4250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4550 4150 4550 4250
+$Comp
+L DC v2
+U 1 1 683FE26D
+P 4550 3700
+F 0 "v2" H 4350 3800 60 0000 C CNN
+F 1 "DC" H 4350 3650 60 0000 C CNN
+F 2 "R1" H 4250 3700 60 0000 C CNN
+F 3 "" H 4550 3700 60 0000 C CNN
+ 1 4550 3700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3850 5000 3800
+Wire Wire Line
+ 5000 3800 5100 3800
+$Comp
+L eSim_GND #PWR04
+U 1 1 683FE32A
+P 5000 4900
+F 0 "#PWR04" H 5000 4650 50 0001 C CNN
+F 1 "eSim_GND" H 5000 4750 50 0000 C CNN
+F 2 "" H 5000 4900 50 0001 C CNN
+F 3 "" H 5000 4900 50 0001 C CNN
+ 1 5000 4900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 4750 5000 4900
+$Comp
+L adc_bridge_1 U2
+U 1 1 683FE349
+P 7300 3300
+F 0 "U2" H 7300 3300 60 0000 C CNN
+F 1 "adc_bridge_1" H 7300 3450 60 0000 C CNN
+F 2 "" H 7300 3300 60 0000 C CNN
+F 3 "" H 7300 3300 60 0000 C CNN
+ 1 7300 3300
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6750 3250 6300 3250
+$Comp
+L pulse v3
+U 1 1 683FE3A5
+P 8150 3700
+F 0 "v3" H 7950 3800 60 0000 C CNN
+F 1 "pulse" H 7950 3650 60 0000 C CNN
+F 2 "R1" H 7850 3700 60 0000 C CNN
+F 3 "" H 8150 3700 60 0000 C CNN
+ 1 8150 3700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7900 3250 8150 3250
+$Comp
+L eSim_GND #PWR05
+U 1 1 683FE58E
+P 8150 4300
+F 0 "#PWR05" H 8150 4050 50 0001 C CNN
+F 1 "eSim_GND" H 8150 4150 50 0000 C CNN
+F 2 "" H 8150 4300 50 0001 C CNN
+F 3 "" H 8150 4300 50 0001 C CNN
+ 1 8150 4300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8150 4150 8150 4300
+$Comp
+L plot_v1 U3
+U 1 1 683FE5B6
+P 6700 4000
+F 0 "U3" H 6700 4500 60 0000 C CNN
+F 1 "plot_v1" H 6900 4350 60 0000 C CNN
+F 2 "" H 6700 4000 60 0000 C CNN
+F 3 "" H 6700 4000 60 0000 C CNN
+ 1 6700 4000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6300 3850 6700 3850
+Text GLabel 6600 4000 2 60 Input ~ 0
+Out
+Wire Wire Line
+ 6700 3850 6700 3800
+Wire Wire Line
+ 6600 4000 6500 4000
+Wire Wire Line
+ 6500 4000 6500 3850
+Connection ~ 6500 3850
+$Comp
+L plot_v1 U1
+U 1 1 683FE9E3
+P 8000 3300
+F 0 "U1" H 8000 3800 60 0000 C CNN
+F 1 "plot_v1" H 8200 3650 60 0000 C CNN
+F 2 "" H 8000 3300 60 0000 C CNN
+F 3 "" H 8000 3300 60 0000 C CNN
+ 1 8000 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8000 3100 8000 3250
+Connection ~ 8000 3250
+Text GLabel 8150 3150 2 60 Input ~ 0
+S
+Wire Wire Line
+ 8150 3150 8000 3150
+Connection ~ 8000 3150
+$Comp
+L SN74LVC1G3157 X1
+U 1 1 683FFB48
+P 5700 3550
+F 0 "X1" H 5700 2950 60 0000 C CNN
+F 1 "SN74LVC1G3157" H 5750 4200 60 0000 C CNN
+F 2 "" H 5700 2950 60 0001 C CNN
+F 3 "" H 5700 2950 60 0001 C CNN
+ 1 5700 3550
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test_Previous_Values.xml b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test_Previous_Values.xml
new file mode 100644
index 000000000..a07854b8e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/SN74VC1G3157_test_Previous_Values.xml
@@ -0,0 +1 @@
+dc1dc3pulse5000.5n0.5n1m2madc_bridgedac_bridgeC:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LVC1G3157truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes01010secusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74LVC1G3157/analysis b/library/SubcircuitLibrary/SN74LVC1G3157/analysis
new file mode 100644
index 000000000..f4bb3b56f
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74LVC1G3157/analysis
@@ -0,0 +1 @@
+.tran 10e-06 10e-03 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S163/3_and-cache.lib b/library/SubcircuitLibrary/SN74S163/3_and-cache.lib
new file mode 100644
index 000000000..0a3ccf7f9
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74S163/3_and.cir b/library/SubcircuitLibrary/SN74S163/3_and.cir
new file mode 100644
index 000000000..15f8954df
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74S163/3_and.cir.out b/library/SubcircuitLibrary/SN74S163/3_and.cir.out
new file mode 100644
index 000000000..e3c966454
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74S163/3_and.pro b/library/SubcircuitLibrary/SN74S163/3_and.pro
new file mode 100644
index 000000000..a4cdec482
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74S163/3_and.sch b/library/SubcircuitLibrary/SN74S163/3_and.sch
new file mode 100644
index 000000000..c853bf49d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74S163/3_and.sub b/library/SubcircuitLibrary/SN74S163/3_and.sub
new file mode 100644
index 000000000..b949ae4fb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S163/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74S163/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S163/4_OR-cache.lib b/library/SubcircuitLibrary/SN74S163/4_OR-cache.lib
new file mode 100644
index 000000000..a3c1c9728
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/4_OR-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.cir b/library/SubcircuitLibrary/SN74S163/4_OR.cir
new file mode 100644
index 000000000..7adbf177d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/4_OR.cir
@@ -0,0 +1,14 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.cir.out b/library/SubcircuitLibrary/SN74S163/4_OR.cir.out
new file mode 100644
index 000000000..4388b9757
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/4_OR.cir.out
@@ -0,0 +1,24 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.pro b/library/SubcircuitLibrary/SN74S163/4_OR.pro
new file mode 100644
index 000000000..a19bf4252
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/4_OR.pro
@@ -0,0 +1,44 @@
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.sch b/library/SubcircuitLibrary/SN74S163/4_OR.sch
new file mode 100644
index 000000000..2f28896cb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/4_OR.sch
@@ -0,0 +1,150 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74S163/4_OR.sub b/library/SubcircuitLibrary/SN74S163/4_OR.sub
new file mode 100644
index 000000000..53fc8b332
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/4_OR.sub
@@ -0,0 +1,18 @@
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S163/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN74S163/4_OR_Previous_Values.xml
new file mode 100644
index 000000000..0683d9eb6
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/4_OR_Previous_Values.xml
@@ -0,0 +1 @@
+d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163-cache.lib b/library/SubcircuitLibrary/SN74S163/SN74S163-cache.lib
new file mode 100644
index 000000000..49ab4eb99
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/SN74S163-cache.lib
@@ -0,0 +1,186 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_dff
+#
+DEF d_dff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_dff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X Din 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Dout 5 550 350 200 L 50 50 1 1 O
+X Ndout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xnor
+#
+DEF d_xnor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xnor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 43 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.bak b/library/SubcircuitLibrary/SN74S163/SN74S163.bak
new file mode 100644
index 000000000..26bc695e7
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/SN74S163.bak
@@ -0,0 +1,1054 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74S163-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U40
+U 1 1 686BBBA3
+P 22500 9800
+F 0 "U40" H 22500 9800 60 0000 C CNN
+F 1 "d_dff" H 22500 9950 60 0000 C CNN
+F 2 "" H 22500 9800 60 0000 C CNN
+F 3 "" H 22500 9800 60 0000 C CNN
+ 1 22500 9800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U43
+U 1 1 686BBBDB
+P 22750 12300
+F 0 "U43" H 22750 12300 60 0000 C CNN
+F 1 "d_dff" H 22750 12450 60 0000 C CNN
+F 2 "" H 22750 12300 60 0000 C CNN
+F 3 "" H 22750 12300 60 0000 C CNN
+ 1 22750 12300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U41
+U 1 1 686BBDFE
+P 22500 14950
+F 0 "U41" H 22500 14950 60 0000 C CNN
+F 1 "d_dff" H 22500 15100 60 0000 C CNN
+F 2 "" H 22500 14950 60 0000 C CNN
+F 3 "" H 22500 14950 60 0000 C CNN
+ 1 22500 14950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U42
+U 1 1 686BBE5B
+P 22700 17400
+F 0 "U42" H 22700 17400 60 0000 C CNN
+F 1 "d_dff" H 22700 17550 60 0000 C CNN
+F 2 "" H 22700 17400 60 0000 C CNN
+F 3 "" H 22700 17400 60 0000 C CNN
+ 1 22700 17400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U11
+U 1 1 686BBEDA
+P 8450 3500
+F 0 "U11" H 8450 3450 60 0000 C CNN
+F 1 "d_buffer" H 8450 3550 60 0000 C CNN
+F 2 "" H 8450 3500 60 0000 C CNN
+F 3 "" H 8450 3500 60 0000 C CNN
+ 1 8450 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U15
+U 1 1 686BBF3F
+P 11000 3500
+F 0 "U15" H 11000 3400 60 0000 C CNN
+F 1 "d_inverter" H 11000 3650 60 0000 C CNN
+F 2 "" H 11050 3450 60 0000 C CNN
+F 3 "" H 11050 3450 60 0000 C CNN
+ 1 11000 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U36
+U 1 1 686BC0CC
+P 21450 10100
+F 0 "U36" H 21450 10000 60 0000 C CNN
+F 1 "d_inverter" H 21450 10250 60 0000 C CNN
+F 2 "" H 21500 10050 60 0000 C CNN
+F 3 "" H 21500 10050 60 0000 C CNN
+ 1 21450 10100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U39
+U 1 1 686BC107
+P 21800 12600
+F 0 "U39" H 21800 12500 60 0000 C CNN
+F 1 "d_inverter" H 21800 12750 60 0000 C CNN
+F 2 "" H 21850 12550 60 0000 C CNN
+F 3 "" H 21850 12550 60 0000 C CNN
+ 1 21800 12600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U37
+U 1 1 686BC174
+P 21550 15250
+F 0 "U37" H 21550 15150 60 0000 C CNN
+F 1 "d_inverter" H 21550 15400 60 0000 C CNN
+F 2 "" H 21600 15200 60 0000 C CNN
+F 3 "" H 21600 15200 60 0000 C CNN
+ 1 21550 15250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U38
+U 1 1 686BC277
+P 21750 17700
+F 0 "U38" H 21750 17600 60 0000 C CNN
+F 1 "d_inverter" H 21750 17850 60 0000 C CNN
+F 2 "" H 21800 17650 60 0000 C CNN
+F 3 "" H 21800 17650 60 0000 C CNN
+ 1 21750 17700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U16
+U 1 1 686BC368
+P 12900 7000
+F 0 "U16" H 12900 7000 60 0000 C CNN
+F 1 "d_nor" H 12950 7100 60 0000 C CNN
+F 2 "" H 12900 7000 60 0000 C CNN
+F 3 "" H 12900 7000 60 0000 C CNN
+ 1 12900 7000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U17
+U 1 1 686BC49C
+P 12950 8550
+F 0 "U17" H 12950 8550 60 0000 C CNN
+F 1 "d_nor" H 13000 8650 60 0000 C CNN
+F 2 "" H 12950 8550 60 0000 C CNN
+F 3 "" H 12950 8550 60 0000 C CNN
+ 1 12950 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 686BC5A5
+P 6750 8650
+F 0 "U6" H 6750 8550 60 0000 C CNN
+F 1 "d_inverter" H 6750 8800 60 0000 C CNN
+F 2 "" H 6800 8600 60 0000 C CNN
+F 3 "" H 6800 8600 60 0000 C CNN
+ 1 6750 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U10
+U 1 1 686BC701
+P 8100 8650
+F 0 "U10" H 8100 8600 60 0000 C CNN
+F 1 "d_buffer" H 8100 8700 60 0000 C CNN
+F 2 "" H 8100 8650 60 0000 C CNN
+F 3 "" H 8100 8650 60 0000 C CNN
+ 1 8100 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U30
+U 1 1 686BCD99
+P 17300 16900
+F 0 "U30" H 17300 16900 60 0000 C CNN
+F 1 "d_and" H 17350 17000 60 0000 C CNN
+F 2 "" H 17300 16900 60 0000 C CNN
+F 3 "" H 17300 16900 60 0000 C CNN
+ 1 17300 16900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U31
+U 1 1 686BCF08
+P 17300 17850
+F 0 "U31" H 17300 17850 60 0000 C CNN
+F 1 "d_and" H 17350 17950 60 0000 C CNN
+F 2 "" H 17300 17850 60 0000 C CNN
+F 3 "" H 17300 17850 60 0000 C CNN
+ 1 17300 17850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U35
+U 1 1 686BCF79
+P 19100 17250
+F 0 "U35" H 19100 17250 60 0000 C CNN
+F 1 "d_or" H 19100 17350 60 0000 C CNN
+F 2 "" H 19100 17250 60 0000 C CNN
+F 3 "" H 19100 17250 60 0000 C CNN
+ 1 19100 17250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U28
+U 1 1 686BD429
+P 17250 14400
+F 0 "U28" H 17250 14400 60 0000 C CNN
+F 1 "d_and" H 17300 14500 60 0000 C CNN
+F 2 "" H 17250 14400 60 0000 C CNN
+F 3 "" H 17250 14400 60 0000 C CNN
+ 1 17250 14400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U29
+U 1 1 686BD42F
+P 17250 15350
+F 0 "U29" H 17250 15350 60 0000 C CNN
+F 1 "d_and" H 17300 15450 60 0000 C CNN
+F 2 "" H 17250 15350 60 0000 C CNN
+F 3 "" H 17250 15350 60 0000 C CNN
+ 1 17250 15350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U34
+U 1 1 686BD435
+P 19050 14750
+F 0 "U34" H 19050 14750 60 0000 C CNN
+F 1 "d_or" H 19050 14850 60 0000 C CNN
+F 2 "" H 19050 14750 60 0000 C CNN
+F 3 "" H 19050 14750 60 0000 C CNN
+ 1 19050 14750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U26
+U 1 1 686BD748
+P 17200 11650
+F 0 "U26" H 17200 11650 60 0000 C CNN
+F 1 "d_and" H 17250 11750 60 0000 C CNN
+F 2 "" H 17200 11650 60 0000 C CNN
+F 3 "" H 17200 11650 60 0000 C CNN
+ 1 17200 11650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U27
+U 1 1 686BD74E
+P 17200 12600
+F 0 "U27" H 17200 12600 60 0000 C CNN
+F 1 "d_and" H 17250 12700 60 0000 C CNN
+F 2 "" H 17200 12600 60 0000 C CNN
+F 3 "" H 17200 12600 60 0000 C CNN
+ 1 17200 12600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U33
+U 1 1 686BD754
+P 19000 12000
+F 0 "U33" H 19000 12000 60 0000 C CNN
+F 1 "d_or" H 19000 12100 60 0000 C CNN
+F 2 "" H 19000 12000 60 0000 C CNN
+F 3 "" H 19000 12000 60 0000 C CNN
+ 1 19000 12000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U24
+U 1 1 686BD75E
+P 17150 9150
+F 0 "U24" H 17150 9150 60 0000 C CNN
+F 1 "d_and" H 17200 9250 60 0000 C CNN
+F 2 "" H 17150 9150 60 0000 C CNN
+F 3 "" H 17150 9150 60 0000 C CNN
+ 1 17150 9150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U25
+U 1 1 686BD764
+P 17150 10100
+F 0 "U25" H 17150 10100 60 0000 C CNN
+F 1 "d_and" H 17200 10200 60 0000 C CNN
+F 2 "" H 17150 10100 60 0000 C CNN
+F 3 "" H 17150 10100 60 0000 C CNN
+ 1 17150 10100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U32
+U 1 1 686BD76A
+P 18950 9500
+F 0 "U32" H 18950 9500 60 0000 C CNN
+F 1 "d_or" H 18950 9600 60 0000 C CNN
+F 2 "" H 18950 9500 60 0000 C CNN
+F 3 "" H 18950 9500 60 0000 C CNN
+ 1 18950 9500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U18
+U 1 1 686BFEFC
+P 13150 9900
+F 0 "U18" H 13150 9900 60 0000 C CNN
+F 1 "d_xnor" H 13200 10000 47 0000 C CNN
+F 2 "" H 13150 9900 60 0000 C CNN
+F 3 "" H 13150 9900 60 0000 C CNN
+ 1 13150 9900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U19
+U 1 1 686C1D19
+P 13250 12700
+F 0 "U19" H 13250 12700 60 0000 C CNN
+F 1 "d_xnor" H 13300 12800 47 0000 C CNN
+F 2 "" H 13250 12700 60 0000 C CNN
+F 3 "" H 13250 12700 60 0000 C CNN
+ 1 13250 12700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U20
+U 1 1 686C1DAA
+P 13500 15300
+F 0 "U20" H 13500 15300 60 0000 C CNN
+F 1 "d_xnor" H 13550 15400 47 0000 C CNN
+F 2 "" H 13500 15300 60 0000 C CNN
+F 3 "" H 13500 15300 60 0000 C CNN
+ 1 13500 15300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U21
+U 1 1 686C1E55
+P 13600 17850
+F 0 "U21" H 13600 17850 60 0000 C CNN
+F 1 "d_xnor" H 13650 17950 47 0000 C CNN
+F 2 "" H 13600 17850 60 0000 C CNN
+F 3 "" H 13600 17850 60 0000 C CNN
+ 1 13600 17850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 686C2D8E
+P 3400 18300
+F 0 "U2" H 3400 18300 60 0000 C CNN
+F 1 "d_and" H 3450 18400 60 0000 C CNN
+F 2 "" H 3400 18300 60 0000 C CNN
+F 3 "" H 3400 18300 60 0000 C CNN
+ 1 3400 18300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U3
+U 1 1 686C3766
+P 5950 12150
+F 0 "U3" H 5950 12100 60 0000 C CNN
+F 1 "d_buffer" H 5950 12200 60 0000 C CNN
+F 2 "" H 5950 12150 60 0000 C CNN
+F 3 "" H 5950 12150 60 0000 C CNN
+ 1 5950 12150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 686C38DD
+P 7350 12150
+F 0 "U7" H 7350 12050 60 0000 C CNN
+F 1 "d_inverter" H 7350 12300 60 0000 C CNN
+F 2 "" H 7400 12100 60 0000 C CNN
+F 3 "" H 7400 12100 60 0000 C CNN
+ 1 7350 12150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 686C3B21
+P 9900 12350
+F 0 "U12" H 9900 12350 60 0000 C CNN
+F 1 "d_and" H 9950 12450 60 0000 C CNN
+F 2 "" H 9900 12350 60 0000 C CNN
+F 3 "" H 9900 12350 60 0000 C CNN
+ 1 9900 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X2
+U 1 1 686C4942
+P 13300 19300
+F 0 "X2" H 13450 19200 60 0000 C CNN
+F 1 "4_OR" H 13450 19400 60 0000 C CNN
+F 2 "" H 13300 19300 60 0000 C CNN
+F 3 "" H 13300 19300 60 0000 C CNN
+ 1 13300 19300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U23
+U 1 1 686C49FD
+P 16050 19300
+F 0 "U23" H 16050 19200 60 0000 C CNN
+F 1 "d_inverter" H 16050 19450 60 0000 C CNN
+F 2 "" H 16100 19250 60 0000 C CNN
+F 3 "" H 16100 19250 60 0000 C CNN
+ 1 16050 19300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U22
+U 1 1 686BEC3A
+P 15000 19400
+F 0 "U22" H 15000 19400 60 0000 C CNN
+F 1 "d_or" H 15000 19500 60 0000 C CNN
+F 2 "" H 15000 19400 60 0000 C CNN
+F 3 "" H 15000 19400 60 0000 C CNN
+ 1 15000 19400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U4
+U 1 1 686BFAE8
+P 5950 20550
+F 0 "U4" H 5950 20500 60 0000 C CNN
+F 1 "d_buffer" H 5950 20600 60 0000 C CNN
+F 2 "" H 5950 20550 60 0000 C CNN
+F 3 "" H 5950 20550 60 0000 C CNN
+ 1 5950 20550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 686BFDA1
+P 7950 20550
+F 0 "U9" H 7950 20450 60 0000 C CNN
+F 1 "d_inverter" H 7950 20700 60 0000 C CNN
+F 2 "" H 8000 20500 60 0000 C CNN
+F 3 "" H 8000 20500 60 0000 C CNN
+ 1 7950 20550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 686C0E5E
+P 10000 15100
+F 0 "U13" H 10000 15100 60 0000 C CNN
+F 1 "d_and" H 10050 15200 60 0000 C CNN
+F 2 "" H 10000 15100 60 0000 C CNN
+F 3 "" H 10000 15100 60 0000 C CNN
+ 1 10000 15100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 686C0F0D
+P 10100 17650
+F 0 "U14" H 10100 17650 60 0000 C CNN
+F 1 "d_and" H 10150 17750 60 0000 C CNN
+F 2 "" H 10100 17650 60 0000 C CNN
+F 3 "" H 10100 17650 60 0000 C CNN
+ 1 10100 17650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U5
+U 1 1 686C0FB8
+P 6550 15050
+F 0 "U5" H 6550 15050 60 0000 C CNN
+F 1 "d_nor" H 6600 15150 60 0000 C CNN
+F 2 "" H 6550 15050 60 0000 C CNN
+F 3 "" H 6550 15050 60 0000 C CNN
+ 1 6550 15050
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 686C108B
+P 6450 17400
+F 0 "X1" H 6550 17350 60 0000 C CNN
+F 1 "3_and" H 6600 17550 60 0000 C CNN
+F 2 "" H 6450 17400 60 0000 C CNN
+F 3 "" H 6450 17400 60 0000 C CNN
+ 1 6450 17400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 686C1138
+P 7650 17350
+F 0 "U8" H 7650 17250 60 0000 C CNN
+F 1 "d_inverter" H 7650 17500 60 0000 C CNN
+F 2 "" H 7700 17300 60 0000 C CNN
+F 3 "" H 7700 17300 60 0000 C CNN
+ 1 7650 17350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8750 8650 12500 8650
+Wire Wire Line
+ 12500 8650 12500 8550
+Wire Wire Line
+ 7600 8650 7050 8650
+Wire Wire Line
+ 12450 7000 10450 7000
+Wire Wire Line
+ 10450 7000 10450 8650
+Connection ~ 10450 8650
+Wire Wire Line
+ 12450 6900 5500 6900
+Wire Wire Line
+ 5500 6900 5500 6800
+Wire Wire Line
+ 12500 8450 12500 7550
+Wire Wire Line
+ 12500 7550 13850 7550
+Wire Wire Line
+ 13850 7550 13850 6950
+Wire Wire Line
+ 13350 6950 16350 6950
+Wire Wire Line
+ 22150 17050 20300 17050
+Wire Wire Line
+ 20300 17050 20300 17200
+Wire Wire Line
+ 20300 17200 19550 17200
+Wire Wire Line
+ 18650 17150 18650 16850
+Wire Wire Line
+ 18650 16850 17750 16850
+Wire Wire Line
+ 18650 17250 18650 17800
+Wire Wire Line
+ 18650 17800 17750 17800
+Wire Wire Line
+ 18600 14650 18600 14350
+Wire Wire Line
+ 18600 14350 17700 14350
+Wire Wire Line
+ 18600 14750 18600 15300
+Wire Wire Line
+ 18600 15300 17700 15300
+Wire Wire Line
+ 18550 11900 18550 11600
+Wire Wire Line
+ 18550 11600 17650 11600
+Wire Wire Line
+ 18550 12000 18550 12550
+Wire Wire Line
+ 18550 12550 17650 12550
+Wire Wire Line
+ 18500 9400 18500 9100
+Wire Wire Line
+ 18500 9100 17600 9100
+Wire Wire Line
+ 18500 9500 18500 10050
+Wire Wire Line
+ 18500 10050 17600 10050
+Wire Wire Line
+ 13400 8500 15800 8500
+Wire Wire Line
+ 15800 8500 15800 17750
+Wire Wire Line
+ 15800 17750 16850 17750
+Wire Wire Line
+ 16350 6950 16350 16800
+Wire Wire Line
+ 16350 16800 16850 16800
+Connection ~ 13850 6950
+Wire Wire Line
+ 16700 10100 15800 10100
+Connection ~ 15800 10100
+Wire Wire Line
+ 16750 11650 16350 11650
+Connection ~ 16350 11650
+Wire Wire Line
+ 16750 12500 15800 12500
+Connection ~ 15800 12500
+Wire Wire Line
+ 16800 14400 16350 14400
+Connection ~ 16350 14400
+Wire Wire Line
+ 16800 15250 15800 15250
+Connection ~ 15800 15250
+Wire Wire Line
+ 16800 14300 2350 14300
+Wire Wire Line
+ 2350 14300 2350 14250
+Wire Wire Line
+ 16850 16900 2250 16900
+Wire Wire Line
+ 2250 16900 2250 16950
+Wire Wire Line
+ 16750 11550 2950 11550
+Wire Wire Line
+ 16700 9150 16350 9150
+Connection ~ 16350 9150
+Wire Wire Line
+ 16700 9050 2700 9050
+Wire Wire Line
+ 2700 9050 2700 9200
+Wire Wire Line
+ 16700 10000 13600 10000
+Wire Wire Line
+ 13600 10000 13600 9850
+Wire Wire Line
+ 21750 10100 21950 10100
+Wire Wire Line
+ 22200 12600 22100 12600
+Wire Wire Line
+ 21950 15250 21850 15250
+Wire Wire Line
+ 22050 17700 22150 17700
+Wire Wire Line
+ 21150 10100 20400 10100
+Wire Wire Line
+ 20400 3500 20400 17700
+Wire Wire Line
+ 20400 3500 11300 3500
+Wire Wire Line
+ 10700 3500 9100 3500
+Wire Wire Line
+ 7950 3500 5500 3500
+Wire Wire Line
+ 5500 3500 5500 3550
+Wire Wire Line
+ 20400 12600 21500 12600
+Connection ~ 20400 10100
+Wire Wire Line
+ 20400 15250 21250 15250
+Connection ~ 20400 12600
+Wire Wire Line
+ 20400 17700 21450 17700
+Connection ~ 20400 15250
+Wire Wire Line
+ 16750 12600 13700 12600
+Wire Wire Line
+ 13700 12600 13700 12650
+Wire Wire Line
+ 16800 15350 13950 15350
+Wire Wire Line
+ 13950 15350 13950 15250
+Wire Wire Line
+ 16850 17850 14050 17850
+Wire Wire Line
+ 14050 17850 14050 17800
+Wire Wire Line
+ 23050 10100 23350 10100
+Wire Wire Line
+ 23350 10100 23350 10800
+Wire Wire Line
+ 23350 10800 4100 10800
+Wire Wire Line
+ 12700 9900 12700 10800
+Connection ~ 12700 10800
+Wire Wire Line
+ 3850 18250 8800 18250
+Wire Wire Line
+ 8800 18250 8800 9800
+Wire Wire Line
+ 8800 9800 12700 9800
+Wire Wire Line
+ 9450 12350 8800 12350
+Connection ~ 8800 12350
+Wire Wire Line
+ 9450 12250 7650 12250
+Wire Wire Line
+ 7650 12250 7650 12150
+Wire Wire Line
+ 7050 12150 6600 12150
+Wire Wire Line
+ 10350 12300 12800 12300
+Wire Wire Line
+ 12800 12300 12800 12600
+Wire Wire Line
+ 13850 19300 14550 19300
+Wire Wire Line
+ 23250 17700 23550 17700
+Wire Wire Line
+ 23550 17700 23550 18600
+Wire Wire Line
+ 23550 18600 12600 18600
+Wire Wire Line
+ 12600 17850 12600 19150
+Wire Wire Line
+ 12600 17850 13150 17850
+Wire Wire Line
+ 12600 19150 12950 19150
+Connection ~ 12600 18600
+Wire Wire Line
+ 4100 10800 4100 19450
+Wire Wire Line
+ 5450 12150 4100 12150
+Connection ~ 4100 12150
+Wire Wire Line
+ 4100 19450 12950 19450
+Wire Wire Line
+ 23300 12600 23700 12600
+Wire Wire Line
+ 23700 12600 23700 13500
+Wire Wire Line
+ 23700 13500 4400 13500
+Wire Wire Line
+ 4400 13500 4400 19350
+Wire Wire Line
+ 4400 19350 12950 19350
+Wire Wire Line
+ 23050 15250 23550 15250
+Wire Wire Line
+ 23550 15250 23550 16100
+Wire Wire Line
+ 23550 16100 4500 16100
+Wire Wire Line
+ 4500 16100 4500 19250
+Wire Wire Line
+ 4500 19250 12950 19250
+Wire Wire Line
+ 15450 19350 15750 19350
+Wire Wire Line
+ 15750 19350 15750 19300
+Wire Wire Line
+ 14550 19400 14100 19400
+Wire Wire Line
+ 14100 19400 14100 20550
+Wire Wire Line
+ 14100 20550 8250 20550
+Wire Wire Line
+ 7650 20550 6600 20550
+Wire Wire Line
+ 5450 20550 2050 20550
+Wire Wire Line
+ 2050 20550 2050 18300
+Wire Wire Line
+ 950 18300 2950 18300
+Connection ~ 2050 18300
+Wire Wire Line
+ 2950 18200 950 18200
+Wire Wire Line
+ 12800 12700 12600 12700
+Wire Wire Line
+ 12600 12700 12600 13500
+Connection ~ 12600 13500
+Wire Wire Line
+ 13050 15300 12650 15300
+Wire Wire Line
+ 12650 15300 12650 16100
+Connection ~ 12650 16100
+Wire Wire Line
+ 7350 17350 6950 17350
+Wire Wire Line
+ 7950 17350 9650 17350
+Wire Wire Line
+ 9650 17350 9650 17550
+Wire Wire Line
+ 9650 17650 8800 17650
+Connection ~ 8800 17650
+Wire Wire Line
+ 6100 17250 4500 17250
+Connection ~ 4500 17250
+Wire Wire Line
+ 6100 17350 4400 17350
+Connection ~ 4400 17350
+Wire Wire Line
+ 6100 17450 4100 17450
+Connection ~ 4100 17450
+Wire Wire Line
+ 6100 14950 4100 14950
+Connection ~ 4100 14950
+Wire Wire Line
+ 6100 15050 4400 15050
+Connection ~ 4400 15050
+Wire Wire Line
+ 7000 15000 9550 15000
+Wire Wire Line
+ 9550 15100 9550 15150
+Wire Wire Line
+ 9550 15150 8800 15150
+Connection ~ 8800 15150
+Wire Wire Line
+ 10450 15050 13050 15050
+Wire Wire Line
+ 13050 15050 13050 15200
+Wire Wire Line
+ 10550 17600 13150 17600
+Wire Wire Line
+ 13150 17600 13150 17750
+Wire Wire Line
+ 16350 19300 27350 19300
+Wire Wire Line
+ 27350 19300 27350 19200
+Wire Wire Line
+ 19500 14700 21950 14700
+Wire Wire Line
+ 21950 14700 21950 14600
+Wire Wire Line
+ 22200 11950 19450 11950
+Wire Wire Line
+ 21950 9450 19400 9450
+Wire Wire Line
+ 23050 9450 25650 9450
+Wire Wire Line
+ 23300 11950 25800 11950
+Wire Wire Line
+ 25800 11950 25800 12000
+Wire Wire Line
+ 23050 14600 26050 14600
+Wire Wire Line
+ 26050 14600 26050 14700
+Wire Wire Line
+ 23250 17050 26650 17050
+Wire Wire Line
+ 26650 17050 26650 17000
+Wire Wire Line
+ 6450 8650 2550 8650
+Wire Wire Line
+ 2550 8650 2550 8000
+$Comp
+L PORT U1
+U 2 1 686C751C
+P 5250 3550
+F 0 "U1" H 5300 3650 30 0000 C CNN
+F 1 "PORT" H 5250 3550 30 0000 C CNN
+F 2 "" H 5250 3550 60 0000 C CNN
+F 3 "" H 5250 3550 60 0000 C CNN
+ 2 5250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686C77B9
+P 5250 6800
+F 0 "U1" H 5300 6900 30 0000 C CNN
+F 1 "PORT" H 5250 6800 30 0000 C CNN
+F 2 "" H 5250 6800 60 0000 C CNN
+F 3 "" H 5250 6800 60 0000 C CNN
+ 9 5250 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686C7AE2
+P 2300 8000
+F 0 "U1" H 2350 8100 30 0000 C CNN
+F 1 "PORT" H 2300 8000 30 0000 C CNN
+F 2 "" H 2300 8000 60 0000 C CNN
+F 3 "" H 2300 8000 60 0000 C CNN
+ 1 2300 8000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686C7C5F
+P 2450 9200
+F 0 "U1" H 2500 9300 30 0000 C CNN
+F 1 "PORT" H 2450 9200 30 0000 C CNN
+F 2 "" H 2450 9200 60 0000 C CNN
+F 3 "" H 2450 9200 60 0000 C CNN
+ 3 2450 9200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686C80EA
+P 2700 11550
+F 0 "U1" H 2750 11650 30 0000 C CNN
+F 1 "PORT" H 2700 11550 30 0000 C CNN
+F 2 "" H 2700 11550 60 0000 C CNN
+F 3 "" H 2700 11550 60 0000 C CNN
+ 4 2700 11550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686C836C
+P 2100 14250
+F 0 "U1" H 2150 14350 30 0000 C CNN
+F 1 "PORT" H 2100 14250 30 0000 C CNN
+F 2 "" H 2100 14250 60 0000 C CNN
+F 3 "" H 2100 14250 60 0000 C CNN
+ 5 2100 14250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686C8561
+P 2000 16950
+F 0 "U1" H 2050 17050 30 0000 C CNN
+F 1 "PORT" H 2000 16950 30 0000 C CNN
+F 2 "" H 2000 16950 60 0000 C CNN
+F 3 "" H 2000 16950 60 0000 C CNN
+ 6 2000 16950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686C88BB
+P 700 18200
+F 0 "U1" H 750 18300 30 0000 C CNN
+F 1 "PORT" H 700 18200 30 0000 C CNN
+F 2 "" H 700 18200 60 0000 C CNN
+F 3 "" H 700 18200 60 0000 C CNN
+ 7 700 18200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686C8B9A
+P 650 18450
+F 0 "U1" H 700 18550 30 0000 C CNN
+F 1 "PORT" H 650 18450 30 0000 C CNN
+F 2 "" H 650 18450 60 0000 C CNN
+F 3 "" H 650 18450 60 0000 C CNN
+ 10 650 18450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 950 18300 950 18450
+Wire Wire Line
+ 950 18450 900 18450
+$Comp
+L PORT U1
+U 14 1 686C9983
+P 25900 9450
+F 0 "U1" H 25950 9550 30 0000 C CNN
+F 1 "PORT" H 25900 9450 30 0000 C CNN
+F 2 "" H 25900 9450 60 0000 C CNN
+F 3 "" H 25900 9450 60 0000 C CNN
+ 14 25900 9450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686C9BA4
+P 26050 12000
+F 0 "U1" H 26100 12100 30 0000 C CNN
+F 1 "PORT" H 26050 12000 30 0000 C CNN
+F 2 "" H 26050 12000 60 0000 C CNN
+F 3 "" H 26050 12000 60 0000 C CNN
+ 13 26050 12000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686C9EBC
+P 26300 14700
+F 0 "U1" H 26350 14800 30 0000 C CNN
+F 1 "PORT" H 26300 14700 30 0000 C CNN
+F 2 "" H 26300 14700 60 0000 C CNN
+F 3 "" H 26300 14700 60 0000 C CNN
+ 12 26300 14700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686CA19D
+P 26900 17000
+F 0 "U1" H 26950 17100 30 0000 C CNN
+F 1 "PORT" H 26900 17000 30 0000 C CNN
+F 2 "" H 26900 17000 60 0000 C CNN
+F 3 "" H 26900 17000 60 0000 C CNN
+ 11 26900 17000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 686CA4A2
+P 27600 19200
+F 0 "U1" H 27650 19300 30 0000 C CNN
+F 1 "PORT" H 27600 19200 30 0000 C CNN
+F 2 "" H 27600 19200 60 0000 C CNN
+F 3 "" H 27600 19200 60 0000 C CNN
+ 15 27600 19200
+ -1 0 0 1
+$EndComp
+NoConn ~ 22500 10400
+NoConn ~ 22500 9150
+NoConn ~ 22750 11650
+NoConn ~ 22750 12900
+NoConn ~ 22500 14300
+NoConn ~ 22500 15550
+NoConn ~ 22700 16750
+NoConn ~ 22700 18000
+Text Label 5650 3500 0 60 ~ 0
+CLK
+Text Label 5700 6900 0 60 ~ 0
+LOAD_BAR
+Text Label 2700 8650 0 60 ~ 0
+CLR_BAR
+Text Label 2900 9050 0 60 ~ 0
+DATA_A
+Text Label 3150 11550 0 60 ~ 0
+DATA_B
+Text Label 2750 14300 0 60 ~ 0
+DATA_C
+Text Label 2550 16900 0 60 ~ 0
+DATA_D
+Text Label 1100 18200 0 60 ~ 0
+ENP
+Text Label 1100 18300 0 60 ~ 0
+ENT
+Text Label 26550 19300 0 60 ~ 0
+RCO
+Text Label 26250 17050 0 60 ~ 0
+QD
+Text Label 25650 14600 0 60 ~ 0
+QC
+Text Label 25250 11950 0 60 ~ 0
+QB
+Text Label 25450 9450 0 60 ~ 0
+QA
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.cir b/library/SubcircuitLibrary/SN74S163/SN74S163.cir
new file mode 100644
index 000000000..79445b0f4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/SN74S163.cir
@@ -0,0 +1,56 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74S163\SN74S163.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/08/25 18:43:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U40 Net-_U32-Pad3_ Net-_U36-Pad2_ ? ? /QA Net-_U18-Pad2_ d_dff
+U43 Net-_U33-Pad3_ Net-_U39-Pad2_ ? ? /QB Net-_U19-Pad2_ d_dff
+U41 Net-_U34-Pad3_ Net-_U37-Pad2_ ? ? /QC Net-_U20-Pad2_ d_dff
+U42 Net-_U35-Pad3_ Net-_U38-Pad2_ ? ? /QD Net-_U21-Pad2_ d_dff
+U11 /CLK Net-_U11-Pad2_ d_buffer
+U15 Net-_U11-Pad2_ Net-_U15-Pad2_ d_inverter
+U36 Net-_U15-Pad2_ Net-_U36-Pad2_ d_inverter
+U39 Net-_U15-Pad2_ Net-_U39-Pad2_ d_inverter
+U37 Net-_U15-Pad2_ Net-_U37-Pad2_ d_inverter
+U38 Net-_U15-Pad2_ Net-_U38-Pad2_ d_inverter
+U16 /LOAD_BAR Net-_U10-Pad2_ Net-_U16-Pad3_ d_nor
+U17 Net-_U16-Pad3_ Net-_U10-Pad2_ Net-_U17-Pad3_ d_nor
+U6 /CLR_BAR Net-_U10-Pad1_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_buffer
+U30 Net-_U16-Pad3_ /DATA_D Net-_U30-Pad3_ d_and
+U31 Net-_U17-Pad3_ Net-_U21-Pad3_ Net-_U31-Pad3_ d_and
+U35 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U35-Pad3_ d_or
+U28 /DATA_C Net-_U16-Pad3_ Net-_U28-Pad3_ d_and
+U29 Net-_U17-Pad3_ Net-_U20-Pad3_ Net-_U29-Pad3_ d_and
+U34 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U34-Pad3_ d_or
+U26 /DATA_B Net-_U16-Pad3_ Net-_U26-Pad3_ d_and
+U27 Net-_U17-Pad3_ Net-_U19-Pad3_ Net-_U27-Pad3_ d_and
+U33 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_or
+U24 /DATA_A Net-_U16-Pad3_ Net-_U24-Pad3_ d_and
+U25 Net-_U18-Pad3_ Net-_U17-Pad3_ Net-_U25-Pad3_ d_and
+U32 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U32-Pad3_ d_or
+U18 Net-_U12-Pad2_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_xnor
+U19 Net-_U12-Pad3_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_xnor
+U20 Net-_U13-Pad3_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_xnor
+U21 Net-_U14-Pad3_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_xnor
+U2 /ENP /ENT Net-_U12-Pad2_ d_and
+U3 Net-_U18-Pad2_ Net-_U3-Pad2_ d_buffer
+U7 Net-_U3-Pad2_ Net-_U12-Pad1_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and
+X2 Net-_U21-Pad2_ Net-_U20-Pad2_ Net-_U19-Pad2_ Net-_U18-Pad2_ Net-_U22-Pad1_ 4_OR
+U23 Net-_U22-Pad3_ /RCO d_inverter
+U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_or
+U4 /ENT Net-_U4-Pad2_ d_buffer
+U9 Net-_U4-Pad2_ Net-_U22-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U12-Pad2_ Net-_U13-Pad3_ d_and
+U14 Net-_U14-Pad1_ Net-_U12-Pad2_ Net-_U14-Pad3_ d_and
+U5 Net-_U18-Pad2_ Net-_U19-Pad2_ Net-_U13-Pad1_ d_nor
+U8 Net-_U45-Pad3_ Net-_U14-Pad1_ d_inverter
+U1 /CLR_BAR /CLK /DATA_A /DATA_B /DATA_C /DATA_D /ENP /LOAD_BAR /ENT /QD /QC /QB /QA /RCO PORT
+U44 Net-_U20-Pad2_ Net-_U19-Pad2_ Net-_U44-Pad3_ d_or
+U45 Net-_U44-Pad3_ Net-_U18-Pad2_ Net-_U45-Pad3_ d_or
+
+.end
diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.cir.out b/library/SubcircuitLibrary/SN74S163/SN74S163.cir.out
new file mode 100644
index 000000000..4f98243d4
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/SN74S163.cir.out
@@ -0,0 +1,190 @@
+* c:\fossee\esim\library\subcircuitlibrary\sn74s163\sn74s163.cir
+
+.include 4_OR.sub
+* u40 net-_u32-pad3_ net-_u36-pad2_ ? ? /qa net-_u18-pad2_ d_dff
+* u43 net-_u33-pad3_ net-_u39-pad2_ ? ? /qb net-_u19-pad2_ d_dff
+* u41 net-_u34-pad3_ net-_u37-pad2_ ? ? /qc net-_u20-pad2_ d_dff
+* u42 net-_u35-pad3_ net-_u38-pad2_ ? ? /qd net-_u21-pad2_ d_dff
+* u11 /clk net-_u11-pad2_ d_buffer
+* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter
+* u36 net-_u15-pad2_ net-_u36-pad2_ d_inverter
+* u39 net-_u15-pad2_ net-_u39-pad2_ d_inverter
+* u37 net-_u15-pad2_ net-_u37-pad2_ d_inverter
+* u38 net-_u15-pad2_ net-_u38-pad2_ d_inverter
+* u16 /load_bar net-_u10-pad2_ net-_u16-pad3_ d_nor
+* u17 net-_u16-pad3_ net-_u10-pad2_ net-_u17-pad3_ d_nor
+* u6 /clr_bar net-_u10-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_buffer
+* u30 net-_u16-pad3_ /data_d net-_u30-pad3_ d_and
+* u31 net-_u17-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_and
+* u35 net-_u30-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_or
+* u28 /data_c net-_u16-pad3_ net-_u28-pad3_ d_and
+* u29 net-_u17-pad3_ net-_u20-pad3_ net-_u29-pad3_ d_and
+* u34 net-_u28-pad3_ net-_u29-pad3_ net-_u34-pad3_ d_or
+* u26 /data_b net-_u16-pad3_ net-_u26-pad3_ d_and
+* u27 net-_u17-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_and
+* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or
+* u24 /data_a net-_u16-pad3_ net-_u24-pad3_ d_and
+* u25 net-_u18-pad3_ net-_u17-pad3_ net-_u25-pad3_ d_and
+* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or
+* u18 net-_u12-pad2_ net-_u18-pad2_ net-_u18-pad3_ d_xnor
+* u19 net-_u12-pad3_ net-_u19-pad2_ net-_u19-pad3_ d_xnor
+* u20 net-_u13-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_xnor
+* u21 net-_u14-pad3_ net-_u21-pad2_ net-_u21-pad3_ d_xnor
+* u2 /enp /ent net-_u12-pad2_ d_and
+* u3 net-_u18-pad2_ net-_u3-pad2_ d_buffer
+* u7 net-_u3-pad2_ net-_u12-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+x2 net-_u21-pad2_ net-_u20-pad2_ net-_u19-pad2_ net-_u18-pad2_ net-_u22-pad1_ 4_OR
+* u23 net-_u22-pad3_ /rco d_inverter
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_or
+* u4 /ent net-_u4-pad2_ d_buffer
+* u9 net-_u4-pad2_ net-_u22-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u12-pad2_ net-_u13-pad3_ d_and
+* u14 net-_u14-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_and
+* u5 net-_u18-pad2_ net-_u19-pad2_ net-_u13-pad1_ d_nor
+* u8 net-_u45-pad3_ net-_u14-pad1_ d_inverter
+* u1 /clr_bar /clk /data_a /data_b /data_c /data_d /enp /load_bar /ent /qd /qc /qb /qa /rco port
+* u44 net-_u20-pad2_ net-_u19-pad2_ net-_u44-pad3_ d_or
+* u45 net-_u44-pad3_ net-_u18-pad2_ net-_u45-pad3_ d_or
+a1 net-_u32-pad3_ net-_u36-pad2_ ? ? /qa net-_u18-pad2_ u40
+a2 net-_u33-pad3_ net-_u39-pad2_ ? ? /qb net-_u19-pad2_ u43
+a3 net-_u34-pad3_ net-_u37-pad2_ ? ? /qc net-_u20-pad2_ u41
+a4 net-_u35-pad3_ net-_u38-pad2_ ? ? /qd net-_u21-pad2_ u42
+a5 /clk net-_u11-pad2_ u11
+a6 net-_u11-pad2_ net-_u15-pad2_ u15
+a7 net-_u15-pad2_ net-_u36-pad2_ u36
+a8 net-_u15-pad2_ net-_u39-pad2_ u39
+a9 net-_u15-pad2_ net-_u37-pad2_ u37
+a10 net-_u15-pad2_ net-_u38-pad2_ u38
+a11 [/load_bar net-_u10-pad2_ ] net-_u16-pad3_ u16
+a12 [net-_u16-pad3_ net-_u10-pad2_ ] net-_u17-pad3_ u17
+a13 /clr_bar net-_u10-pad1_ u6
+a14 net-_u10-pad1_ net-_u10-pad2_ u10
+a15 [net-_u16-pad3_ /data_d ] net-_u30-pad3_ u30
+a16 [net-_u17-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u31
+a17 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35
+a18 [/data_c net-_u16-pad3_ ] net-_u28-pad3_ u28
+a19 [net-_u17-pad3_ net-_u20-pad3_ ] net-_u29-pad3_ u29
+a20 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u34-pad3_ u34
+a21 [/data_b net-_u16-pad3_ ] net-_u26-pad3_ u26
+a22 [net-_u17-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27
+a23 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33
+a24 [/data_a net-_u16-pad3_ ] net-_u24-pad3_ u24
+a25 [net-_u18-pad3_ net-_u17-pad3_ ] net-_u25-pad3_ u25
+a26 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32
+a27 [net-_u12-pad2_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a28 [net-_u12-pad3_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a29 [net-_u13-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a30 [net-_u14-pad3_ net-_u21-pad2_ ] net-_u21-pad3_ u21
+a31 [/enp /ent ] net-_u12-pad2_ u2
+a32 net-_u18-pad2_ net-_u3-pad2_ u3
+a33 net-_u3-pad2_ net-_u12-pad1_ u7
+a34 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a35 net-_u22-pad3_ /rco u23
+a36 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a37 /ent net-_u4-pad2_ u4
+a38 net-_u4-pad2_ net-_u22-pad2_ u9
+a39 [net-_u13-pad1_ net-_u12-pad2_ ] net-_u13-pad3_ u13
+a40 [net-_u14-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14
+a41 [net-_u18-pad2_ net-_u19-pad2_ ] net-_u13-pad1_ u5
+a42 net-_u45-pad3_ net-_u14-pad1_ u8
+a43 [net-_u20-pad2_ net-_u19-pad2_ ] net-_u44-pad3_ u44
+a44 [net-_u44-pad3_ net-_u18-pad2_ ] net-_u45-pad3_ u45
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u40 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u43 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u41 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u42 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u20 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u21 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.pro b/library/SubcircuitLibrary/SN74S163/SN74S163.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/SN74S163.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.sch b/library/SubcircuitLibrary/SN74S163/SN74S163.sch
new file mode 100644
index 000000000..033bb96eb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/SN74S163.sch
@@ -0,0 +1,1077 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN74S163-cache
+EELAYER 25 0
+EELAYER END
+$Descr A1 33110 23386
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_dff U40
+U 1 1 686BBBA3
+P 22500 9800
+F 0 "U40" H 22500 9800 60 0000 C CNN
+F 1 "d_dff" H 22500 9950 60 0000 C CNN
+F 2 "" H 22500 9800 60 0000 C CNN
+F 3 "" H 22500 9800 60 0000 C CNN
+ 1 22500 9800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U43
+U 1 1 686BBBDB
+P 22750 12300
+F 0 "U43" H 22750 12300 60 0000 C CNN
+F 1 "d_dff" H 22750 12450 60 0000 C CNN
+F 2 "" H 22750 12300 60 0000 C CNN
+F 3 "" H 22750 12300 60 0000 C CNN
+ 1 22750 12300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U41
+U 1 1 686BBDFE
+P 22500 14950
+F 0 "U41" H 22500 14950 60 0000 C CNN
+F 1 "d_dff" H 22500 15100 60 0000 C CNN
+F 2 "" H 22500 14950 60 0000 C CNN
+F 3 "" H 22500 14950 60 0000 C CNN
+ 1 22500 14950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_dff U42
+U 1 1 686BBE5B
+P 22700 17400
+F 0 "U42" H 22700 17400 60 0000 C CNN
+F 1 "d_dff" H 22700 17550 60 0000 C CNN
+F 2 "" H 22700 17400 60 0000 C CNN
+F 3 "" H 22700 17400 60 0000 C CNN
+ 1 22700 17400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U11
+U 1 1 686BBEDA
+P 8450 3500
+F 0 "U11" H 8450 3450 60 0000 C CNN
+F 1 "d_buffer" H 8450 3550 60 0000 C CNN
+F 2 "" H 8450 3500 60 0000 C CNN
+F 3 "" H 8450 3500 60 0000 C CNN
+ 1 8450 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U15
+U 1 1 686BBF3F
+P 11000 3500
+F 0 "U15" H 11000 3400 60 0000 C CNN
+F 1 "d_inverter" H 11000 3650 60 0000 C CNN
+F 2 "" H 11050 3450 60 0000 C CNN
+F 3 "" H 11050 3450 60 0000 C CNN
+ 1 11000 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U36
+U 1 1 686BC0CC
+P 21450 10100
+F 0 "U36" H 21450 10000 60 0000 C CNN
+F 1 "d_inverter" H 21450 10250 60 0000 C CNN
+F 2 "" H 21500 10050 60 0000 C CNN
+F 3 "" H 21500 10050 60 0000 C CNN
+ 1 21450 10100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U39
+U 1 1 686BC107
+P 21800 12600
+F 0 "U39" H 21800 12500 60 0000 C CNN
+F 1 "d_inverter" H 21800 12750 60 0000 C CNN
+F 2 "" H 21850 12550 60 0000 C CNN
+F 3 "" H 21850 12550 60 0000 C CNN
+ 1 21800 12600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U37
+U 1 1 686BC174
+P 21550 15250
+F 0 "U37" H 21550 15150 60 0000 C CNN
+F 1 "d_inverter" H 21550 15400 60 0000 C CNN
+F 2 "" H 21600 15200 60 0000 C CNN
+F 3 "" H 21600 15200 60 0000 C CNN
+ 1 21550 15250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U38
+U 1 1 686BC277
+P 21750 17700
+F 0 "U38" H 21750 17600 60 0000 C CNN
+F 1 "d_inverter" H 21750 17850 60 0000 C CNN
+F 2 "" H 21800 17650 60 0000 C CNN
+F 3 "" H 21800 17650 60 0000 C CNN
+ 1 21750 17700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U16
+U 1 1 686BC368
+P 12900 7000
+F 0 "U16" H 12900 7000 60 0000 C CNN
+F 1 "d_nor" H 12950 7100 60 0000 C CNN
+F 2 "" H 12900 7000 60 0000 C CNN
+F 3 "" H 12900 7000 60 0000 C CNN
+ 1 12900 7000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U17
+U 1 1 686BC49C
+P 12950 8550
+F 0 "U17" H 12950 8550 60 0000 C CNN
+F 1 "d_nor" H 13000 8650 60 0000 C CNN
+F 2 "" H 12950 8550 60 0000 C CNN
+F 3 "" H 12950 8550 60 0000 C CNN
+ 1 12950 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 686BC5A5
+P 6750 8650
+F 0 "U6" H 6750 8550 60 0000 C CNN
+F 1 "d_inverter" H 6750 8800 60 0000 C CNN
+F 2 "" H 6800 8600 60 0000 C CNN
+F 3 "" H 6800 8600 60 0000 C CNN
+ 1 6750 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U10
+U 1 1 686BC701
+P 8100 8650
+F 0 "U10" H 8100 8600 60 0000 C CNN
+F 1 "d_buffer" H 8100 8700 60 0000 C CNN
+F 2 "" H 8100 8650 60 0000 C CNN
+F 3 "" H 8100 8650 60 0000 C CNN
+ 1 8100 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U30
+U 1 1 686BCD99
+P 17300 16900
+F 0 "U30" H 17300 16900 60 0000 C CNN
+F 1 "d_and" H 17350 17000 60 0000 C CNN
+F 2 "" H 17300 16900 60 0000 C CNN
+F 3 "" H 17300 16900 60 0000 C CNN
+ 1 17300 16900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U31
+U 1 1 686BCF08
+P 17300 17850
+F 0 "U31" H 17300 17850 60 0000 C CNN
+F 1 "d_and" H 17350 17950 60 0000 C CNN
+F 2 "" H 17300 17850 60 0000 C CNN
+F 3 "" H 17300 17850 60 0000 C CNN
+ 1 17300 17850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U35
+U 1 1 686BCF79
+P 19100 17250
+F 0 "U35" H 19100 17250 60 0000 C CNN
+F 1 "d_or" H 19100 17350 60 0000 C CNN
+F 2 "" H 19100 17250 60 0000 C CNN
+F 3 "" H 19100 17250 60 0000 C CNN
+ 1 19100 17250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U28
+U 1 1 686BD429
+P 17250 14400
+F 0 "U28" H 17250 14400 60 0000 C CNN
+F 1 "d_and" H 17300 14500 60 0000 C CNN
+F 2 "" H 17250 14400 60 0000 C CNN
+F 3 "" H 17250 14400 60 0000 C CNN
+ 1 17250 14400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U29
+U 1 1 686BD42F
+P 17250 15350
+F 0 "U29" H 17250 15350 60 0000 C CNN
+F 1 "d_and" H 17300 15450 60 0000 C CNN
+F 2 "" H 17250 15350 60 0000 C CNN
+F 3 "" H 17250 15350 60 0000 C CNN
+ 1 17250 15350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U34
+U 1 1 686BD435
+P 19050 14750
+F 0 "U34" H 19050 14750 60 0000 C CNN
+F 1 "d_or" H 19050 14850 60 0000 C CNN
+F 2 "" H 19050 14750 60 0000 C CNN
+F 3 "" H 19050 14750 60 0000 C CNN
+ 1 19050 14750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U26
+U 1 1 686BD748
+P 17200 11650
+F 0 "U26" H 17200 11650 60 0000 C CNN
+F 1 "d_and" H 17250 11750 60 0000 C CNN
+F 2 "" H 17200 11650 60 0000 C CNN
+F 3 "" H 17200 11650 60 0000 C CNN
+ 1 17200 11650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U27
+U 1 1 686BD74E
+P 17200 12600
+F 0 "U27" H 17200 12600 60 0000 C CNN
+F 1 "d_and" H 17250 12700 60 0000 C CNN
+F 2 "" H 17200 12600 60 0000 C CNN
+F 3 "" H 17200 12600 60 0000 C CNN
+ 1 17200 12600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U33
+U 1 1 686BD754
+P 19000 12000
+F 0 "U33" H 19000 12000 60 0000 C CNN
+F 1 "d_or" H 19000 12100 60 0000 C CNN
+F 2 "" H 19000 12000 60 0000 C CNN
+F 3 "" H 19000 12000 60 0000 C CNN
+ 1 19000 12000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U24
+U 1 1 686BD75E
+P 17150 9150
+F 0 "U24" H 17150 9150 60 0000 C CNN
+F 1 "d_and" H 17200 9250 60 0000 C CNN
+F 2 "" H 17150 9150 60 0000 C CNN
+F 3 "" H 17150 9150 60 0000 C CNN
+ 1 17150 9150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U25
+U 1 1 686BD764
+P 17150 10100
+F 0 "U25" H 17150 10100 60 0000 C CNN
+F 1 "d_and" H 17200 10200 60 0000 C CNN
+F 2 "" H 17150 10100 60 0000 C CNN
+F 3 "" H 17150 10100 60 0000 C CNN
+ 1 17150 10100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U32
+U 1 1 686BD76A
+P 18950 9500
+F 0 "U32" H 18950 9500 60 0000 C CNN
+F 1 "d_or" H 18950 9600 60 0000 C CNN
+F 2 "" H 18950 9500 60 0000 C CNN
+F 3 "" H 18950 9500 60 0000 C CNN
+ 1 18950 9500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U18
+U 1 1 686BFEFC
+P 13150 9900
+F 0 "U18" H 13150 9900 60 0000 C CNN
+F 1 "d_xnor" H 13200 10000 47 0000 C CNN
+F 2 "" H 13150 9900 60 0000 C CNN
+F 3 "" H 13150 9900 60 0000 C CNN
+ 1 13150 9900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U19
+U 1 1 686C1D19
+P 13250 12700
+F 0 "U19" H 13250 12700 60 0000 C CNN
+F 1 "d_xnor" H 13300 12800 47 0000 C CNN
+F 2 "" H 13250 12700 60 0000 C CNN
+F 3 "" H 13250 12700 60 0000 C CNN
+ 1 13250 12700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U20
+U 1 1 686C1DAA
+P 13500 15300
+F 0 "U20" H 13500 15300 60 0000 C CNN
+F 1 "d_xnor" H 13550 15400 47 0000 C CNN
+F 2 "" H 13500 15300 60 0000 C CNN
+F 3 "" H 13500 15300 60 0000 C CNN
+ 1 13500 15300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U21
+U 1 1 686C1E55
+P 13600 17850
+F 0 "U21" H 13600 17850 60 0000 C CNN
+F 1 "d_xnor" H 13650 17950 47 0000 C CNN
+F 2 "" H 13600 17850 60 0000 C CNN
+F 3 "" H 13600 17850 60 0000 C CNN
+ 1 13600 17850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 686C2D8E
+P 3400 18300
+F 0 "U2" H 3400 18300 60 0000 C CNN
+F 1 "d_and" H 3450 18400 60 0000 C CNN
+F 2 "" H 3400 18300 60 0000 C CNN
+F 3 "" H 3400 18300 60 0000 C CNN
+ 1 3400 18300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U3
+U 1 1 686C3766
+P 5950 12150
+F 0 "U3" H 5950 12100 60 0000 C CNN
+F 1 "d_buffer" H 5950 12200 60 0000 C CNN
+F 2 "" H 5950 12150 60 0000 C CNN
+F 3 "" H 5950 12150 60 0000 C CNN
+ 1 5950 12150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 686C38DD
+P 7350 12150
+F 0 "U7" H 7350 12050 60 0000 C CNN
+F 1 "d_inverter" H 7350 12300 60 0000 C CNN
+F 2 "" H 7400 12100 60 0000 C CNN
+F 3 "" H 7400 12100 60 0000 C CNN
+ 1 7350 12150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 686C3B21
+P 9900 12350
+F 0 "U12" H 9900 12350 60 0000 C CNN
+F 1 "d_and" H 9950 12450 60 0000 C CNN
+F 2 "" H 9900 12350 60 0000 C CNN
+F 3 "" H 9900 12350 60 0000 C CNN
+ 1 9900 12350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X2
+U 1 1 686C4942
+P 13300 19300
+F 0 "X2" H 13450 19200 60 0000 C CNN
+F 1 "4_OR" H 13450 19400 60 0000 C CNN
+F 2 "" H 13300 19300 60 0000 C CNN
+F 3 "" H 13300 19300 60 0000 C CNN
+ 1 13300 19300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U23
+U 1 1 686C49FD
+P 16050 19300
+F 0 "U23" H 16050 19200 60 0000 C CNN
+F 1 "d_inverter" H 16050 19450 60 0000 C CNN
+F 2 "" H 16100 19250 60 0000 C CNN
+F 3 "" H 16100 19250 60 0000 C CNN
+ 1 16050 19300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U22
+U 1 1 686BEC3A
+P 15000 19400
+F 0 "U22" H 15000 19400 60 0000 C CNN
+F 1 "d_or" H 15000 19500 60 0000 C CNN
+F 2 "" H 15000 19400 60 0000 C CNN
+F 3 "" H 15000 19400 60 0000 C CNN
+ 1 15000 19400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U4
+U 1 1 686BFAE8
+P 5950 20550
+F 0 "U4" H 5950 20500 60 0000 C CNN
+F 1 "d_buffer" H 5950 20600 60 0000 C CNN
+F 2 "" H 5950 20550 60 0000 C CNN
+F 3 "" H 5950 20550 60 0000 C CNN
+ 1 5950 20550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 686BFDA1
+P 7950 20550
+F 0 "U9" H 7950 20450 60 0000 C CNN
+F 1 "d_inverter" H 7950 20700 60 0000 C CNN
+F 2 "" H 8000 20500 60 0000 C CNN
+F 3 "" H 8000 20500 60 0000 C CNN
+ 1 7950 20550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 686C0E5E
+P 10000 15100
+F 0 "U13" H 10000 15100 60 0000 C CNN
+F 1 "d_and" H 10050 15200 60 0000 C CNN
+F 2 "" H 10000 15100 60 0000 C CNN
+F 3 "" H 10000 15100 60 0000 C CNN
+ 1 10000 15100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 686C0F0D
+P 10100 17650
+F 0 "U14" H 10100 17650 60 0000 C CNN
+F 1 "d_and" H 10150 17750 60 0000 C CNN
+F 2 "" H 10100 17650 60 0000 C CNN
+F 3 "" H 10100 17650 60 0000 C CNN
+ 1 10100 17650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U5
+U 1 1 686C0FB8
+P 6550 15050
+F 0 "U5" H 6550 15050 60 0000 C CNN
+F 1 "d_nor" H 6600 15150 60 0000 C CNN
+F 2 "" H 6550 15050 60 0000 C CNN
+F 3 "" H 6550 15050 60 0000 C CNN
+ 1 6550 15050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 686C1138
+P 7650 17350
+F 0 "U8" H 7650 17250 60 0000 C CNN
+F 1 "d_inverter" H 7650 17500 60 0000 C CNN
+F 2 "" H 7700 17300 60 0000 C CNN
+F 3 "" H 7700 17300 60 0000 C CNN
+ 1 7650 17350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8750 8650 12500 8650
+Wire Wire Line
+ 12500 8650 12500 8550
+Wire Wire Line
+ 7600 8650 7050 8650
+Wire Wire Line
+ 12450 7000 10450 7000
+Wire Wire Line
+ 10450 7000 10450 8650
+Connection ~ 10450 8650
+Wire Wire Line
+ 12450 6900 5500 6900
+Wire Wire Line
+ 5500 6900 5500 6800
+Wire Wire Line
+ 12500 8450 12500 7550
+Wire Wire Line
+ 12500 7550 13850 7550
+Wire Wire Line
+ 13850 7550 13850 6950
+Wire Wire Line
+ 13350 6950 16350 6950
+Wire Wire Line
+ 22150 17050 20300 17050
+Wire Wire Line
+ 20300 17050 20300 17200
+Wire Wire Line
+ 20300 17200 19550 17200
+Wire Wire Line
+ 18650 17150 18650 16850
+Wire Wire Line
+ 18650 16850 17750 16850
+Wire Wire Line
+ 18650 17250 18650 17800
+Wire Wire Line
+ 18650 17800 17750 17800
+Wire Wire Line
+ 18600 14650 18600 14350
+Wire Wire Line
+ 18600 14350 17700 14350
+Wire Wire Line
+ 18600 14750 18600 15300
+Wire Wire Line
+ 18600 15300 17700 15300
+Wire Wire Line
+ 18550 11900 18550 11600
+Wire Wire Line
+ 18550 11600 17650 11600
+Wire Wire Line
+ 18550 12000 18550 12550
+Wire Wire Line
+ 18550 12550 17650 12550
+Wire Wire Line
+ 18500 9400 18500 9100
+Wire Wire Line
+ 18500 9100 17600 9100
+Wire Wire Line
+ 18500 9500 18500 10050
+Wire Wire Line
+ 18500 10050 17600 10050
+Wire Wire Line
+ 13400 8500 15800 8500
+Wire Wire Line
+ 15800 8500 15800 17750
+Wire Wire Line
+ 15800 17750 16850 17750
+Wire Wire Line
+ 16350 6950 16350 16800
+Wire Wire Line
+ 16350 16800 16850 16800
+Connection ~ 13850 6950
+Wire Wire Line
+ 16700 10100 15800 10100
+Connection ~ 15800 10100
+Wire Wire Line
+ 16750 11650 16350 11650
+Connection ~ 16350 11650
+Wire Wire Line
+ 16750 12500 15800 12500
+Connection ~ 15800 12500
+Wire Wire Line
+ 16800 14400 16350 14400
+Connection ~ 16350 14400
+Wire Wire Line
+ 16800 15250 15800 15250
+Connection ~ 15800 15250
+Wire Wire Line
+ 16800 14300 2350 14300
+Wire Wire Line
+ 2350 14300 2350 14250
+Wire Wire Line
+ 16850 16900 2250 16900
+Wire Wire Line
+ 2250 16900 2250 16950
+Wire Wire Line
+ 16750 11550 2950 11550
+Wire Wire Line
+ 16700 9150 16350 9150
+Connection ~ 16350 9150
+Wire Wire Line
+ 16700 9050 2700 9050
+Wire Wire Line
+ 2700 9050 2700 9200
+Wire Wire Line
+ 16700 10000 13600 10000
+Wire Wire Line
+ 13600 10000 13600 9850
+Wire Wire Line
+ 21750 10100 21950 10100
+Wire Wire Line
+ 22200 12600 22100 12600
+Wire Wire Line
+ 21950 15250 21850 15250
+Wire Wire Line
+ 22050 17700 22150 17700
+Wire Wire Line
+ 21150 10100 20400 10100
+Wire Wire Line
+ 20400 3500 20400 17700
+Wire Wire Line
+ 20400 3500 11300 3500
+Wire Wire Line
+ 10700 3500 9100 3500
+Wire Wire Line
+ 7950 3500 5500 3500
+Wire Wire Line
+ 5500 3500 5500 3550
+Wire Wire Line
+ 20400 12600 21500 12600
+Connection ~ 20400 10100
+Wire Wire Line
+ 20400 15250 21250 15250
+Connection ~ 20400 12600
+Wire Wire Line
+ 20400 17700 21450 17700
+Connection ~ 20400 15250
+Wire Wire Line
+ 16750 12600 13700 12600
+Wire Wire Line
+ 13700 12600 13700 12650
+Wire Wire Line
+ 16800 15350 13950 15350
+Wire Wire Line
+ 13950 15350 13950 15250
+Wire Wire Line
+ 16850 17850 14050 17850
+Wire Wire Line
+ 14050 17850 14050 17800
+Wire Wire Line
+ 23050 10100 23350 10100
+Wire Wire Line
+ 23350 10100 23350 10800
+Wire Wire Line
+ 23350 10800 4100 10800
+Wire Wire Line
+ 12700 9900 12700 10800
+Connection ~ 12700 10800
+Wire Wire Line
+ 8800 18250 3850 18250
+Wire Wire Line
+ 8800 9800 8800 18250
+Wire Wire Line
+ 8800 9800 12700 9800
+Wire Wire Line
+ 9450 12350 8800 12350
+Connection ~ 8800 12350
+Wire Wire Line
+ 9450 12250 7650 12250
+Wire Wire Line
+ 7650 12250 7650 12150
+Wire Wire Line
+ 7050 12150 6600 12150
+Wire Wire Line
+ 10350 12300 12800 12300
+Wire Wire Line
+ 12800 12300 12800 12600
+Wire Wire Line
+ 13850 19300 14550 19300
+Wire Wire Line
+ 23250 17700 23550 17700
+Wire Wire Line
+ 23550 17700 23550 18600
+Wire Wire Line
+ 12600 17850 13150 17850
+Wire Wire Line
+ 12600 19150 12950 19150
+Wire Wire Line
+ 4100 10800 4100 19450
+Wire Wire Line
+ 5450 12150 4100 12150
+Connection ~ 4100 12150
+Wire Wire Line
+ 4100 19450 12950 19450
+Wire Wire Line
+ 23300 12600 23700 12600
+Wire Wire Line
+ 23700 12600 23700 13500
+Wire Wire Line
+ 23700 13500 4400 13500
+Wire Wire Line
+ 4400 13500 4400 19350
+Wire Wire Line
+ 4400 19350 12950 19350
+Wire Wire Line
+ 23050 15250 23550 15250
+Wire Wire Line
+ 23550 15250 23550 16100
+Wire Wire Line
+ 23550 16100 4500 16100
+Wire Wire Line
+ 4500 16100 4500 19250
+Wire Wire Line
+ 4500 19250 12950 19250
+Wire Wire Line
+ 15450 19350 15750 19350
+Wire Wire Line
+ 15750 19350 15750 19300
+Wire Wire Line
+ 14550 19400 14100 19400
+Wire Wire Line
+ 14100 19400 14100 20550
+Wire Wire Line
+ 14100 20550 8250 20550
+Wire Wire Line
+ 7650 20550 6600 20550
+Wire Wire Line
+ 5450 20550 2050 20550
+Wire Wire Line
+ 2050 20550 2050 18300
+Wire Wire Line
+ 950 18300 2950 18300
+Connection ~ 2050 18300
+Wire Wire Line
+ 2950 18200 950 18200
+Wire Wire Line
+ 12800 12700 12600 12700
+Wire Wire Line
+ 12600 12700 12600 13500
+Connection ~ 12600 13500
+Wire Wire Line
+ 13050 15300 12650 15300
+Wire Wire Line
+ 12650 15300 12650 16100
+Connection ~ 12650 16100
+Wire Wire Line
+ 7350 17350 6950 17350
+Wire Wire Line
+ 7950 17350 9650 17350
+Wire Wire Line
+ 9650 17350 9650 17550
+Wire Wire Line
+ 9650 17650 8800 17650
+Connection ~ 8800 17650
+Wire Wire Line
+ 4500 17250 5300 17250
+Connection ~ 4500 17250
+Wire Wire Line
+ 4400 17350 5300 17350
+Connection ~ 4400 17350
+Wire Wire Line
+ 4100 17450 5650 17450
+Connection ~ 4100 17450
+Wire Wire Line
+ 6100 14950 4100 14950
+Connection ~ 4100 14950
+Wire Wire Line
+ 6100 15050 4400 15050
+Connection ~ 4400 15050
+Wire Wire Line
+ 7000 15000 9550 15000
+Wire Wire Line
+ 9550 15100 9550 15150
+Wire Wire Line
+ 9550 15150 8800 15150
+Connection ~ 8800 15150
+Wire Wire Line
+ 10450 15050 13050 15050
+Wire Wire Line
+ 13050 15050 13050 15200
+Wire Wire Line
+ 10550 17600 13150 17600
+Wire Wire Line
+ 13150 17600 13150 17750
+Wire Wire Line
+ 16350 19300 27350 19300
+Wire Wire Line
+ 27350 19300 27350 19200
+Wire Wire Line
+ 19500 14700 21950 14700
+Wire Wire Line
+ 21950 14700 21950 14600
+Wire Wire Line
+ 22200 11950 19450 11950
+Wire Wire Line
+ 21950 9450 19400 9450
+Wire Wire Line
+ 23050 9450 25650 9450
+Wire Wire Line
+ 23300 11950 25800 11950
+Wire Wire Line
+ 25800 11950 25800 12000
+Wire Wire Line
+ 23050 14600 26050 14600
+Wire Wire Line
+ 26050 14600 26050 14700
+Wire Wire Line
+ 23250 17050 26650 17050
+Wire Wire Line
+ 26650 17050 26650 17000
+Wire Wire Line
+ 6450 8650 2550 8650
+Wire Wire Line
+ 2550 8650 2550 8000
+$Comp
+L PORT U1
+U 2 1 686C751C
+P 5250 3550
+F 0 "U1" H 5300 3650 30 0000 C CNN
+F 1 "PORT" H 5250 3550 30 0000 C CNN
+F 2 "" H 5250 3550 60 0000 C CNN
+F 3 "" H 5250 3550 60 0000 C CNN
+ 2 5250 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686C77B9
+P 5250 6800
+F 0 "U1" H 5300 6900 30 0000 C CNN
+F 1 "PORT" H 5250 6800 30 0000 C CNN
+F 2 "" H 5250 6800 60 0000 C CNN
+F 3 "" H 5250 6800 60 0000 C CNN
+ 9 5250 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 686C7AE2
+P 2300 8000
+F 0 "U1" H 2350 8100 30 0000 C CNN
+F 1 "PORT" H 2300 8000 30 0000 C CNN
+F 2 "" H 2300 8000 60 0000 C CNN
+F 3 "" H 2300 8000 60 0000 C CNN
+ 1 2300 8000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686C7C5F
+P 2450 9200
+F 0 "U1" H 2500 9300 30 0000 C CNN
+F 1 "PORT" H 2450 9200 30 0000 C CNN
+F 2 "" H 2450 9200 60 0000 C CNN
+F 3 "" H 2450 9200 60 0000 C CNN
+ 3 2450 9200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686C80EA
+P 2700 11550
+F 0 "U1" H 2750 11650 30 0000 C CNN
+F 1 "PORT" H 2700 11550 30 0000 C CNN
+F 2 "" H 2700 11550 60 0000 C CNN
+F 3 "" H 2700 11550 60 0000 C CNN
+ 4 2700 11550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686C836C
+P 2100 14250
+F 0 "U1" H 2150 14350 30 0000 C CNN
+F 1 "PORT" H 2100 14250 30 0000 C CNN
+F 2 "" H 2100 14250 60 0000 C CNN
+F 3 "" H 2100 14250 60 0000 C CNN
+ 5 2100 14250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686C8561
+P 2000 16950
+F 0 "U1" H 2050 17050 30 0000 C CNN
+F 1 "PORT" H 2000 16950 30 0000 C CNN
+F 2 "" H 2000 16950 60 0000 C CNN
+F 3 "" H 2000 16950 60 0000 C CNN
+ 6 2000 16950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686C88BB
+P 700 18200
+F 0 "U1" H 750 18300 30 0000 C CNN
+F 1 "PORT" H 700 18200 30 0000 C CNN
+F 2 "" H 700 18200 60 0000 C CNN
+F 3 "" H 700 18200 60 0000 C CNN
+ 7 700 18200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686C8B9A
+P 650 18450
+F 0 "U1" H 700 18550 30 0000 C CNN
+F 1 "PORT" H 650 18450 30 0000 C CNN
+F 2 "" H 650 18450 60 0000 C CNN
+F 3 "" H 650 18450 60 0000 C CNN
+ 10 650 18450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 950 18300 950 18450
+Wire Wire Line
+ 950 18450 900 18450
+$Comp
+L PORT U1
+U 14 1 686C9983
+P 25900 9450
+F 0 "U1" H 25950 9550 30 0000 C CNN
+F 1 "PORT" H 25900 9450 30 0000 C CNN
+F 2 "" H 25900 9450 60 0000 C CNN
+F 3 "" H 25900 9450 60 0000 C CNN
+ 14 25900 9450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686C9BA4
+P 26050 12000
+F 0 "U1" H 26100 12100 30 0000 C CNN
+F 1 "PORT" H 26050 12000 30 0000 C CNN
+F 2 "" H 26050 12000 60 0000 C CNN
+F 3 "" H 26050 12000 60 0000 C CNN
+ 13 26050 12000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686C9EBC
+P 26300 14700
+F 0 "U1" H 26350 14800 30 0000 C CNN
+F 1 "PORT" H 26300 14700 30 0000 C CNN
+F 2 "" H 26300 14700 60 0000 C CNN
+F 3 "" H 26300 14700 60 0000 C CNN
+ 12 26300 14700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686CA19D
+P 26900 17000
+F 0 "U1" H 26950 17100 30 0000 C CNN
+F 1 "PORT" H 26900 17000 30 0000 C CNN
+F 2 "" H 26900 17000 60 0000 C CNN
+F 3 "" H 26900 17000 60 0000 C CNN
+ 11 26900 17000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 686CA4A2
+P 27600 19200
+F 0 "U1" H 27650 19300 30 0000 C CNN
+F 1 "PORT" H 27600 19200 30 0000 C CNN
+F 2 "" H 27600 19200 60 0000 C CNN
+F 3 "" H 27600 19200 60 0000 C CNN
+ 15 27600 19200
+ -1 0 0 1
+$EndComp
+NoConn ~ 22500 10400
+NoConn ~ 22500 9150
+NoConn ~ 22750 11650
+NoConn ~ 22750 12900
+NoConn ~ 22500 14300
+NoConn ~ 22500 15550
+NoConn ~ 22700 16750
+NoConn ~ 22700 18000
+Text Label 5650 3500 0 60 ~ 0
+CLK
+Text Label 5700 6900 0 60 ~ 0
+LOAD_BAR
+Text Label 2700 8650 0 60 ~ 0
+CLR_BAR
+Text Label 2900 9050 0 60 ~ 0
+DATA_A
+Text Label 3150 11550 0 60 ~ 0
+DATA_B
+Text Label 2750 14300 0 60 ~ 0
+DATA_C
+Text Label 2550 16900 0 60 ~ 0
+DATA_D
+Text Label 1100 18200 0 60 ~ 0
+ENP
+Text Label 1100 18300 0 60 ~ 0
+ENT
+Text Label 26550 19300 0 60 ~ 0
+RCO
+Text Label 26250 17050 0 60 ~ 0
+QD
+Text Label 25650 14600 0 60 ~ 0
+QC
+Text Label 25250 11950 0 60 ~ 0
+QB
+Text Label 25450 9450 0 60 ~ 0
+QA
+Wire Wire Line
+ 23550 18600 12600 18600
+Wire Wire Line
+ 12600 17850 12600 19150
+Connection ~ 12600 18600
+$Comp
+L d_or U44
+U 1 1 686DA9AB
+P 5750 17350
+F 0 "U44" H 5750 17350 60 0000 C CNN
+F 1 "d_or" H 5750 17450 60 0000 C CNN
+F 2 "" H 5750 17350 60 0000 C CNN
+F 3 "" H 5750 17350 60 0000 C CNN
+ 1 5750 17350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U45
+U 1 1 686DADD1
+P 6500 17650
+F 0 "U45" H 6500 17650 60 0000 C CNN
+F 1 "d_or" H 6500 17750 60 0000 C CNN
+F 2 "" H 6500 17650 60 0000 C CNN
+F 3 "" H 6500 17650 60 0000 C CNN
+ 1 6500 17650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6050 17550 6050 17450
+Wire Wire Line
+ 6050 17450 6200 17450
+Wire Wire Line
+ 6200 17450 6200 17300
+Wire Wire Line
+ 5650 17450 5650 17650
+Wire Wire Line
+ 5650 17650 6050 17650
+Wire Wire Line
+ 6950 17350 6950 17600
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163.sub b/library/SubcircuitLibrary/SN74S163/SN74S163.sub
new file mode 100644
index 000000000..72e71624c
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/SN74S163.sub
@@ -0,0 +1,184 @@
+* Subcircuit SN74S163
+.subckt SN74S163 /clr_bar /clk /data_a /data_b /data_c /data_d /enp /load_bar /ent /qd /qc /qb /qa /rco
+* c:\fossee\esim\library\subcircuitlibrary\sn74s163\sn74s163.cir
+.include 4_OR.sub
+* u40 net-_u32-pad3_ net-_u36-pad2_ ? ? /qa net-_u18-pad2_ d_dff
+* u43 net-_u33-pad3_ net-_u39-pad2_ ? ? /qb net-_u19-pad2_ d_dff
+* u41 net-_u34-pad3_ net-_u37-pad2_ ? ? /qc net-_u20-pad2_ d_dff
+* u42 net-_u35-pad3_ net-_u38-pad2_ ? ? /qd net-_u21-pad2_ d_dff
+* u11 /clk net-_u11-pad2_ d_buffer
+* u15 net-_u11-pad2_ net-_u15-pad2_ d_inverter
+* u36 net-_u15-pad2_ net-_u36-pad2_ d_inverter
+* u39 net-_u15-pad2_ net-_u39-pad2_ d_inverter
+* u37 net-_u15-pad2_ net-_u37-pad2_ d_inverter
+* u38 net-_u15-pad2_ net-_u38-pad2_ d_inverter
+* u16 /load_bar net-_u10-pad2_ net-_u16-pad3_ d_nor
+* u17 net-_u16-pad3_ net-_u10-pad2_ net-_u17-pad3_ d_nor
+* u6 /clr_bar net-_u10-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_buffer
+* u30 net-_u16-pad3_ /data_d net-_u30-pad3_ d_and
+* u31 net-_u17-pad3_ net-_u21-pad3_ net-_u31-pad3_ d_and
+* u35 net-_u30-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_or
+* u28 /data_c net-_u16-pad3_ net-_u28-pad3_ d_and
+* u29 net-_u17-pad3_ net-_u20-pad3_ net-_u29-pad3_ d_and
+* u34 net-_u28-pad3_ net-_u29-pad3_ net-_u34-pad3_ d_or
+* u26 /data_b net-_u16-pad3_ net-_u26-pad3_ d_and
+* u27 net-_u17-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_and
+* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or
+* u24 /data_a net-_u16-pad3_ net-_u24-pad3_ d_and
+* u25 net-_u18-pad3_ net-_u17-pad3_ net-_u25-pad3_ d_and
+* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or
+* u18 net-_u12-pad2_ net-_u18-pad2_ net-_u18-pad3_ d_xnor
+* u19 net-_u12-pad3_ net-_u19-pad2_ net-_u19-pad3_ d_xnor
+* u20 net-_u13-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_xnor
+* u21 net-_u14-pad3_ net-_u21-pad2_ net-_u21-pad3_ d_xnor
+* u2 /enp /ent net-_u12-pad2_ d_and
+* u3 net-_u18-pad2_ net-_u3-pad2_ d_buffer
+* u7 net-_u3-pad2_ net-_u12-pad1_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+x2 net-_u21-pad2_ net-_u20-pad2_ net-_u19-pad2_ net-_u18-pad2_ net-_u22-pad1_ 4_OR
+* u23 net-_u22-pad3_ /rco d_inverter
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_or
+* u4 /ent net-_u4-pad2_ d_buffer
+* u9 net-_u4-pad2_ net-_u22-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u12-pad2_ net-_u13-pad3_ d_and
+* u14 net-_u14-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_and
+* u5 net-_u18-pad2_ net-_u19-pad2_ net-_u13-pad1_ d_nor
+* u8 net-_u45-pad3_ net-_u14-pad1_ d_inverter
+* u44 net-_u20-pad2_ net-_u19-pad2_ net-_u44-pad3_ d_or
+* u45 net-_u44-pad3_ net-_u18-pad2_ net-_u45-pad3_ d_or
+a1 net-_u32-pad3_ net-_u36-pad2_ ? ? /qa net-_u18-pad2_ u40
+a2 net-_u33-pad3_ net-_u39-pad2_ ? ? /qb net-_u19-pad2_ u43
+a3 net-_u34-pad3_ net-_u37-pad2_ ? ? /qc net-_u20-pad2_ u41
+a4 net-_u35-pad3_ net-_u38-pad2_ ? ? /qd net-_u21-pad2_ u42
+a5 /clk net-_u11-pad2_ u11
+a6 net-_u11-pad2_ net-_u15-pad2_ u15
+a7 net-_u15-pad2_ net-_u36-pad2_ u36
+a8 net-_u15-pad2_ net-_u39-pad2_ u39
+a9 net-_u15-pad2_ net-_u37-pad2_ u37
+a10 net-_u15-pad2_ net-_u38-pad2_ u38
+a11 [/load_bar net-_u10-pad2_ ] net-_u16-pad3_ u16
+a12 [net-_u16-pad3_ net-_u10-pad2_ ] net-_u17-pad3_ u17
+a13 /clr_bar net-_u10-pad1_ u6
+a14 net-_u10-pad1_ net-_u10-pad2_ u10
+a15 [net-_u16-pad3_ /data_d ] net-_u30-pad3_ u30
+a16 [net-_u17-pad3_ net-_u21-pad3_ ] net-_u31-pad3_ u31
+a17 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35
+a18 [/data_c net-_u16-pad3_ ] net-_u28-pad3_ u28
+a19 [net-_u17-pad3_ net-_u20-pad3_ ] net-_u29-pad3_ u29
+a20 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u34-pad3_ u34
+a21 [/data_b net-_u16-pad3_ ] net-_u26-pad3_ u26
+a22 [net-_u17-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27
+a23 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33
+a24 [/data_a net-_u16-pad3_ ] net-_u24-pad3_ u24
+a25 [net-_u18-pad3_ net-_u17-pad3_ ] net-_u25-pad3_ u25
+a26 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32
+a27 [net-_u12-pad2_ net-_u18-pad2_ ] net-_u18-pad3_ u18
+a28 [net-_u12-pad3_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a29 [net-_u13-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a30 [net-_u14-pad3_ net-_u21-pad2_ ] net-_u21-pad3_ u21
+a31 [/enp /ent ] net-_u12-pad2_ u2
+a32 net-_u18-pad2_ net-_u3-pad2_ u3
+a33 net-_u3-pad2_ net-_u12-pad1_ u7
+a34 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a35 net-_u22-pad3_ /rco u23
+a36 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a37 /ent net-_u4-pad2_ u4
+a38 net-_u4-pad2_ net-_u22-pad2_ u9
+a39 [net-_u13-pad1_ net-_u12-pad2_ ] net-_u13-pad3_ u13
+a40 [net-_u14-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14
+a41 [net-_u18-pad2_ net-_u19-pad2_ ] net-_u13-pad1_ u5
+a42 net-_u45-pad3_ net-_u14-pad1_ u8
+a43 [net-_u20-pad2_ net-_u19-pad2_ ] net-_u44-pad3_ u44
+a44 [net-_u44-pad3_ net-_u18-pad2_ ] net-_u45-pad3_ u45
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u40 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u43 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u41 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dff, NgSpice Name: d_dff
+.model u42 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u11 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u10 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u18 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u20 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u21 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u3 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u4 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74S163
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S163/SN74S163_Previous_Values.xml b/library/SubcircuitLibrary/SN74S163/SN74S163_Previous_Values.xml
new file mode 100644
index 000000000..93a2738e2
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/SN74S163_Previous_Values.xml
@@ -0,0 +1 @@
+d_dffd_dffd_dffd_dffd_bufferd_inverterd_inverterd_inverterd_inverterd_inverterd_nord_nord_inverterd_bufferd_andd_andd_ord_andd_andd_ord_andd_andd_ord_andd_andd_ord_xnord_xnord_xnord_xnord_andd_bufferd_inverterd_andd_inverterd_ord_bufferd_inverterd_andd_andd_nord_inverterd_ord_orC:\FOSSEE\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S163/analysis b/library/SubcircuitLibrary/SN74S163/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S163/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350-cache.lib b/library/SubcircuitLibrary/SN74S350/SN74S350-cache.lib
new file mode 100644
index 000000000..9398642bb
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S350/SN74S350-cache.lib
@@ -0,0 +1,128 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_tristate
+#
+DEF d_tristate U 0 40 Y Y 1 F N
+F0 "U" -250 250 60 H V C CNN
+F1 "d_tristate" -200 450 60 H V C CNN
+F2 "" -100 350 60 H V C CNN
+F3 "" -100 350 60 H V C CNN
+DRAW
+P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N
+X IN 1 -600 350 200 R 50 50 1 1 I
+X EN 2 -50 50 193 U 50 50 1 1 I
+X OUT 3 550 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.cir b/library/SubcircuitLibrary/SN74S350/SN74S350.cir
new file mode 100644
index 000000000..91569f214
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S350/SN74S350.cir
@@ -0,0 +1,68 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74S350\SN74S350.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/06/25 16:22:32
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U45 Net-_U35-Pad3_ Net-_U36-Pad3_ Net-_U45-Pad3_ d_or
+U50 Net-_U45-Pad3_ Net-_U46-Pad3_ Net-_U50-Pad3_ d_nor
+U54 Net-_U50-Pad3_ Net-_U54-Pad2_ d_inverter
+U58 Net-_U54-Pad2_ Net-_U55-Pad2_ /11 d_tristate
+U6 /13 Net-_U55-Pad2_ d_inverter
+U3 /10 Net-_U11-Pad1_ d_inverter
+U4 Net-_U11-Pad1_ Net-_U10-Pad1_ d_inverter
+U35 Net-_U19-Pad3_ /7 Net-_U35-Pad3_ d_and
+U19 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U19-Pad3_ d_and
+U46 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U46-Pad3_ d_or
+U36 Net-_U20-Pad3_ /6 Net-_U36-Pad3_ d_and
+U20 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U20-Pad3_ d_and
+U37 Net-_U21-Pad3_ /5 Net-_U37-Pad3_ d_and
+U21 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U21-Pad3_ d_and
+U38 Net-_U22-Pad3_ /4 Net-_U38-Pad3_ d_and
+U22 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_and
+U41 Net-_U27-Pad3_ Net-_U28-Pad3_ Net-_U41-Pad3_ d_or
+U48 Net-_U41-Pad3_ Net-_U42-Pad3_ Net-_U48-Pad3_ d_nor
+U52 Net-_U48-Pad3_ Net-_U52-Pad2_ d_inverter
+U56 Net-_U52-Pad2_ Net-_U55-Pad2_ /12 d_tristate
+U27 Net-_U11-Pad3_ /6 Net-_U27-Pad3_ d_and
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and
+U42 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U42-Pad3_ d_or
+U28 Net-_U12-Pad3_ /5 Net-_U28-Pad3_ d_and
+U12 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U12-Pad3_ d_and
+U29 Net-_U13-Pad3_ /4 Net-_U29-Pad3_ d_and
+U13 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U13-Pad3_ d_and
+U30 Net-_U14-Pad3_ /3 Net-_U30-Pad3_ d_and
+U14 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_and
+U43 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U43-Pad3_ d_or
+U49 Net-_U43-Pad3_ Net-_U44-Pad3_ Net-_U49-Pad3_ d_nor
+U53 Net-_U49-Pad3_ Net-_U53-Pad2_ d_inverter
+U57 Net-_U53-Pad2_ Net-_U55-Pad2_ /14 d_tristate
+U31 Net-_U15-Pad3_ /5 Net-_U31-Pad3_ d_and
+U15 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_and
+U44 Net-_U33-Pad3_ Net-_U34-Pad3_ Net-_U44-Pad3_ d_or
+U32 Net-_U16-Pad3_ /4 Net-_U32-Pad3_ d_and
+U16 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U16-Pad3_ d_and
+U33 Net-_U17-Pad3_ /3 Net-_U33-Pad3_ d_and
+U17 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad3_ d_and
+U34 Net-_U18-Pad3_ /2 Net-_U34-Pad3_ d_and
+U18 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_and
+U39 Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U39-Pad3_ d_or
+U47 Net-_U39-Pad3_ Net-_U40-Pad3_ Net-_U47-Pad3_ d_nor
+U51 Net-_U47-Pad3_ Net-_U51-Pad2_ d_inverter
+U55 Net-_U51-Pad2_ Net-_U55-Pad2_ /15 d_tristate
+U23 Net-_U23-Pad1_ /4 Net-_U23-Pad3_ d_and
+U7 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U23-Pad1_ d_and
+U40 Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U40-Pad3_ d_or
+U24 Net-_U24-Pad1_ /3 Net-_U24-Pad3_ d_and
+U8 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U24-Pad1_ d_and
+U25 Net-_U25-Pad1_ /2 Net-_U25-Pad3_ d_and
+U9 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U25-Pad1_ d_and
+U26 Net-_U10-Pad3_ /1 Net-_U26-Pad3_ d_and
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and
+U2 /9 Net-_U11-Pad2_ d_inverter
+U5 Net-_U11-Pad2_ Net-_U10-Pad2_ d_inverter
+U1 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.cir.out b/library/SubcircuitLibrary/SN74S350/SN74S350.cir.out
new file mode 100644
index 000000000..83620a0ae
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S350/SN74S350.cir.out
@@ -0,0 +1,240 @@
+* d:\fossee\esim\library\subcircuitlibrary\sn74s350\sn74s350.cir
+
+* u45 net-_u35-pad3_ net-_u36-pad3_ net-_u45-pad3_ d_or
+* u50 net-_u45-pad3_ net-_u46-pad3_ net-_u50-pad3_ d_nor
+* u54 net-_u50-pad3_ net-_u54-pad2_ d_inverter
+* u58 net-_u54-pad2_ net-_u55-pad2_ /11 d_tristate
+* u6 /13 net-_u55-pad2_ d_inverter
+* u3 /10 net-_u11-pad1_ d_inverter
+* u4 net-_u11-pad1_ net-_u10-pad1_ d_inverter
+* u35 net-_u19-pad3_ /7 net-_u35-pad3_ d_and
+* u19 net-_u11-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_and
+* u46 net-_u37-pad3_ net-_u38-pad3_ net-_u46-pad3_ d_or
+* u36 net-_u20-pad3_ /6 net-_u36-pad3_ d_and
+* u20 net-_u10-pad1_ net-_u11-pad2_ net-_u20-pad3_ d_and
+* u37 net-_u21-pad3_ /5 net-_u37-pad3_ d_and
+* u21 net-_u11-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and
+* u38 net-_u22-pad3_ /4 net-_u38-pad3_ d_and
+* u22 net-_u10-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and
+* u41 net-_u27-pad3_ net-_u28-pad3_ net-_u41-pad3_ d_or
+* u48 net-_u41-pad3_ net-_u42-pad3_ net-_u48-pad3_ d_nor
+* u52 net-_u48-pad3_ net-_u52-pad2_ d_inverter
+* u56 net-_u52-pad2_ net-_u55-pad2_ /12 d_tristate
+* u27 net-_u11-pad3_ /6 net-_u27-pad3_ d_and
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u42 net-_u29-pad3_ net-_u30-pad3_ net-_u42-pad3_ d_or
+* u28 net-_u12-pad3_ /5 net-_u28-pad3_ d_and
+* u12 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad3_ d_and
+* u29 net-_u13-pad3_ /4 net-_u29-pad3_ d_and
+* u13 net-_u11-pad1_ net-_u10-pad2_ net-_u13-pad3_ d_and
+* u30 net-_u14-pad3_ /3 net-_u30-pad3_ d_and
+* u14 net-_u10-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_and
+* u43 net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_or
+* u49 net-_u43-pad3_ net-_u44-pad3_ net-_u49-pad3_ d_nor
+* u53 net-_u49-pad3_ net-_u53-pad2_ d_inverter
+* u57 net-_u53-pad2_ net-_u55-pad2_ /14 d_tristate
+* u31 net-_u15-pad3_ /5 net-_u31-pad3_ d_and
+* u15 net-_u11-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and
+* u44 net-_u33-pad3_ net-_u34-pad3_ net-_u44-pad3_ d_or
+* u32 net-_u16-pad3_ /4 net-_u32-pad3_ d_and
+* u16 net-_u10-pad1_ net-_u11-pad2_ net-_u16-pad3_ d_and
+* u33 net-_u17-pad3_ /3 net-_u33-pad3_ d_and
+* u17 net-_u11-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and
+* u34 net-_u18-pad3_ /2 net-_u34-pad3_ d_and
+* u18 net-_u10-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and
+* u39 net-_u23-pad3_ net-_u24-pad3_ net-_u39-pad3_ d_or
+* u47 net-_u39-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor
+* u51 net-_u47-pad3_ net-_u51-pad2_ d_inverter
+* u55 net-_u51-pad2_ net-_u55-pad2_ /15 d_tristate
+* u23 net-_u23-pad1_ /4 net-_u23-pad3_ d_and
+* u7 net-_u11-pad1_ net-_u11-pad2_ net-_u23-pad1_ d_and
+* u40 net-_u25-pad3_ net-_u26-pad3_ net-_u40-pad3_ d_or
+* u24 net-_u24-pad1_ /3 net-_u24-pad3_ d_and
+* u8 net-_u10-pad1_ net-_u11-pad2_ net-_u24-pad1_ d_and
+* u25 net-_u25-pad1_ /2 net-_u25-pad3_ d_and
+* u9 net-_u11-pad1_ net-_u10-pad2_ net-_u25-pad1_ d_and
+* u26 net-_u10-pad3_ /1 net-_u26-pad3_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u2 /9 net-_u11-pad2_ d_inverter
+* u5 net-_u11-pad2_ net-_u10-pad2_ d_inverter
+* u1 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ? port
+a1 [net-_u35-pad3_ net-_u36-pad3_ ] net-_u45-pad3_ u45
+a2 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u50-pad3_ u50
+a3 net-_u50-pad3_ net-_u54-pad2_ u54
+a4 net-_u54-pad2_ net-_u55-pad2_ /11 u58
+a5 /13 net-_u55-pad2_ u6
+a6 /10 net-_u11-pad1_ u3
+a7 net-_u11-pad1_ net-_u10-pad1_ u4
+a8 [net-_u19-pad3_ /7 ] net-_u35-pad3_ u35
+a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19
+a10 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u46-pad3_ u46
+a11 [net-_u20-pad3_ /6 ] net-_u36-pad3_ u36
+a12 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u20-pad3_ u20
+a13 [net-_u21-pad3_ /5 ] net-_u37-pad3_ u37
+a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21
+a15 [net-_u22-pad3_ /4 ] net-_u38-pad3_ u38
+a16 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22
+a17 [net-_u27-pad3_ net-_u28-pad3_ ] net-_u41-pad3_ u41
+a18 [net-_u41-pad3_ net-_u42-pad3_ ] net-_u48-pad3_ u48
+a19 net-_u48-pad3_ net-_u52-pad2_ u52
+a20 net-_u52-pad2_ net-_u55-pad2_ /12 u56
+a21 [net-_u11-pad3_ /6 ] net-_u27-pad3_ u27
+a22 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u42-pad3_ u42
+a24 [net-_u12-pad3_ /5 ] net-_u28-pad3_ u28
+a25 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u12-pad3_ u12
+a26 [net-_u13-pad3_ /4 ] net-_u29-pad3_ u29
+a27 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u13-pad3_ u13
+a28 [net-_u14-pad3_ /3 ] net-_u30-pad3_ u30
+a29 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14
+a30 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43
+a31 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u49-pad3_ u49
+a32 net-_u49-pad3_ net-_u53-pad2_ u53
+a33 net-_u53-pad2_ net-_u55-pad2_ /14 u57
+a34 [net-_u15-pad3_ /5 ] net-_u31-pad3_ u31
+a35 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15
+a36 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u44-pad3_ u44
+a37 [net-_u16-pad3_ /4 ] net-_u32-pad3_ u32
+a38 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u16-pad3_ u16
+a39 [net-_u17-pad3_ /3 ] net-_u33-pad3_ u33
+a40 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17
+a41 [net-_u18-pad3_ /2 ] net-_u34-pad3_ u34
+a42 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18
+a43 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u39-pad3_ u39
+a44 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47
+a45 net-_u47-pad3_ net-_u51-pad2_ u51
+a46 net-_u51-pad2_ net-_u55-pad2_ /15 u55
+a47 [net-_u23-pad1_ /4 ] net-_u23-pad3_ u23
+a48 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u23-pad1_ u7
+a49 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u40-pad3_ u40
+a50 [net-_u24-pad1_ /3 ] net-_u24-pad3_ u24
+a51 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u24-pad1_ u8
+a52 [net-_u25-pad1_ /2 ] net-_u25-pad3_ u25
+a53 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u25-pad1_ u9
+a54 [net-_u10-pad3_ /1 ] net-_u26-pad3_ u26
+a55 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a56 /9 net-_u11-pad2_ u2
+a57 net-_u11-pad2_ net-_u10-pad2_ u5
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u58 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u46 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u56 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u57 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u55 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.pro b/library/SubcircuitLibrary/SN74S350/SN74S350.pro
new file mode 100644
index 000000000..c6df329cf
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S350/SN74S350.pro
@@ -0,0 +1,83 @@
+update=07/06/25 15:31:31
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.sch b/library/SubcircuitLibrary/SN74S350/SN74S350.sch
new file mode 100644
index 000000000..da2d9082d
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S350/SN74S350.sch
@@ -0,0 +1,1333 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U45
+U 1 1 686A5F02
+P 10950 3850
+F 0 "U45" H 10950 3850 60 0000 C CNN
+F 1 "d_or" H 10950 3950 60 0000 C CNN
+F 2 "" H 10950 3850 60 0000 C CNN
+F 3 "" H 10950 3850 60 0000 C CNN
+ 1 10950 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U50
+U 1 1 686A5F0E
+P 12450 4300
+F 0 "U50" H 12450 4300 60 0000 C CNN
+F 1 "d_nor" H 12500 4400 60 0000 C CNN
+F 2 "" H 12450 4300 60 0000 C CNN
+F 3 "" H 12450 4300 60 0000 C CNN
+ 1 12450 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U54
+U 1 1 686A5F14
+P 13600 4250
+F 0 "U54" H 13600 4150 60 0000 C CNN
+F 1 "d_inverter" H 13600 4400 60 0000 C CNN
+F 2 "" H 13650 4200 60 0000 C CNN
+F 3 "" H 13650 4200 60 0000 C CNN
+ 1 13600 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_tristate U58
+U 1 1 686A5F1A
+P 14800 4600
+F 0 "U58" H 14550 4850 60 0000 C CNN
+F 1 "d_tristate" H 14600 5050 60 0000 C CNN
+F 2 "" H 14700 4950 60 0000 C CNN
+F 3 "" H 14700 4950 60 0000 C CNN
+ 1 14800 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 686AC3D5
+P 8300 1750
+F 0 "U6" H 8300 1650 60 0000 C CNN
+F 1 "d_inverter" H 8300 1900 60 0000 C CNN
+F 2 "" H 8350 1700 60 0000 C CNN
+F 3 "" H 8350 1700 60 0000 C CNN
+ 1 8300 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 686B27E9
+P 5900 2100
+F 0 "U3" H 5900 2000 60 0000 C CNN
+F 1 "d_inverter" H 5900 2250 60 0000 C CNN
+F 2 "" H 5950 2050 60 0000 C CNN
+F 3 "" H 5950 2050 60 0000 C CNN
+ 1 5900 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 686B2866
+P 6700 2100
+F 0 "U4" H 6700 2000 60 0000 C CNN
+F 1 "d_inverter" H 6700 2250 60 0000 C CNN
+F 2 "" H 6750 2050 60 0000 C CNN
+F 3 "" H 6750 2050 60 0000 C CNN
+ 1 6700 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U35
+U 1 1 686B5D69
+P 9650 3450
+F 0 "U35" H 9650 3450 60 0000 C CNN
+F 1 "d_and" H 9700 3550 60 0000 C CNN
+F 2 "" H 9650 3450 60 0000 C CNN
+F 3 "" H 9650 3450 60 0000 C CNN
+ 1 9650 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U19
+U 1 1 686B5ED7
+P 8500 3400
+F 0 "U19" H 8500 3400 60 0000 C CNN
+F 1 "d_and" H 8550 3500 60 0000 C CNN
+F 2 "" H 8500 3400 60 0000 C CNN
+F 3 "" H 8500 3400 60 0000 C CNN
+ 1 8500 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U46
+U 1 1 686A5F08
+P 10950 4750
+F 0 "U46" H 10950 4750 60 0000 C CNN
+F 1 "d_or" H 10950 4850 60 0000 C CNN
+F 2 "" H 10950 4750 60 0000 C CNN
+F 3 "" H 10950 4750 60 0000 C CNN
+ 1 10950 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U36
+U 1 1 686B774E
+P 9650 4100
+F 0 "U36" H 9650 4100 60 0000 C CNN
+F 1 "d_and" H 9700 4200 60 0000 C CNN
+F 2 "" H 9650 4100 60 0000 C CNN
+F 3 "" H 9650 4100 60 0000 C CNN
+ 1 9650 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U20
+U 1 1 686B7754
+P 8500 4050
+F 0 "U20" H 8500 4050 60 0000 C CNN
+F 1 "d_and" H 8550 4150 60 0000 C CNN
+F 2 "" H 8500 4050 60 0000 C CNN
+F 3 "" H 8500 4050 60 0000 C CNN
+ 1 8500 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U37
+U 1 1 686B7922
+P 9650 4500
+F 0 "U37" H 9650 4500 60 0000 C CNN
+F 1 "d_and" H 9700 4600 60 0000 C CNN
+F 2 "" H 9650 4500 60 0000 C CNN
+F 3 "" H 9650 4500 60 0000 C CNN
+ 1 9650 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U21
+U 1 1 686B7928
+P 8500 4450
+F 0 "U21" H 8500 4450 60 0000 C CNN
+F 1 "d_and" H 8550 4550 60 0000 C CNN
+F 2 "" H 8500 4450 60 0000 C CNN
+F 3 "" H 8500 4450 60 0000 C CNN
+ 1 8500 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U38
+U 1 1 686B7C4F
+P 9650 4950
+F 0 "U38" H 9650 4950 60 0000 C CNN
+F 1 "d_and" H 9700 5050 60 0000 C CNN
+F 2 "" H 9650 4950 60 0000 C CNN
+F 3 "" H 9650 4950 60 0000 C CNN
+ 1 9650 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U22
+U 1 1 686B7C55
+P 8500 4900
+F 0 "U22" H 8500 4900 60 0000 C CNN
+F 1 "d_and" H 8550 5000 60 0000 C CNN
+F 2 "" H 8500 4900 60 0000 C CNN
+F 3 "" H 8500 4900 60 0000 C CNN
+ 1 8500 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U41
+U 1 1 686B838C
+P 10900 6150
+F 0 "U41" H 10900 6150 60 0000 C CNN
+F 1 "d_or" H 10900 6250 60 0000 C CNN
+F 2 "" H 10900 6150 60 0000 C CNN
+F 3 "" H 10900 6150 60 0000 C CNN
+ 1 10900 6150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U48
+U 1 1 686B8392
+P 12400 6600
+F 0 "U48" H 12400 6600 60 0000 C CNN
+F 1 "d_nor" H 12450 6700 60 0000 C CNN
+F 2 "" H 12400 6600 60 0000 C CNN
+F 3 "" H 12400 6600 60 0000 C CNN
+ 1 12400 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U52
+U 1 1 686B8398
+P 13550 6550
+F 0 "U52" H 13550 6450 60 0000 C CNN
+F 1 "d_inverter" H 13550 6700 60 0000 C CNN
+F 2 "" H 13600 6500 60 0000 C CNN
+F 3 "" H 13600 6500 60 0000 C CNN
+ 1 13550 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_tristate U56
+U 1 1 686B839E
+P 14750 6900
+F 0 "U56" H 14500 7150 60 0000 C CNN
+F 1 "d_tristate" H 14550 7350 60 0000 C CNN
+F 2 "" H 14650 7250 60 0000 C CNN
+F 3 "" H 14650 7250 60 0000 C CNN
+ 1 14750 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U27
+U 1 1 686B83B4
+P 9600 5750
+F 0 "U27" H 9600 5750 60 0000 C CNN
+F 1 "d_and" H 9650 5850 60 0000 C CNN
+F 2 "" H 9600 5750 60 0000 C CNN
+F 3 "" H 9600 5750 60 0000 C CNN
+ 1 9600 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U11
+U 1 1 686B83BA
+P 8450 5700
+F 0 "U11" H 8450 5700 60 0000 C CNN
+F 1 "d_and" H 8500 5800 60 0000 C CNN
+F 2 "" H 8450 5700 60 0000 C CNN
+F 3 "" H 8450 5700 60 0000 C CNN
+ 1 8450 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U42
+U 1 1 686B83CC
+P 10900 7050
+F 0 "U42" H 10900 7050 60 0000 C CNN
+F 1 "d_or" H 10900 7150 60 0000 C CNN
+F 2 "" H 10900 7050 60 0000 C CNN
+F 3 "" H 10900 7050 60 0000 C CNN
+ 1 10900 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U28
+U 1 1 686B83D3
+P 9600 6400
+F 0 "U28" H 9600 6400 60 0000 C CNN
+F 1 "d_and" H 9650 6500 60 0000 C CNN
+F 2 "" H 9600 6400 60 0000 C CNN
+F 3 "" H 9600 6400 60 0000 C CNN
+ 1 9600 6400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 686B83D9
+P 8450 6350
+F 0 "U12" H 8450 6350 60 0000 C CNN
+F 1 "d_and" H 8500 6450 60 0000 C CNN
+F 2 "" H 8450 6350 60 0000 C CNN
+F 3 "" H 8450 6350 60 0000 C CNN
+ 1 8450 6350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U29
+U 1 1 686B83E5
+P 9600 6800
+F 0 "U29" H 9600 6800 60 0000 C CNN
+F 1 "d_and" H 9650 6900 60 0000 C CNN
+F 2 "" H 9600 6800 60 0000 C CNN
+F 3 "" H 9600 6800 60 0000 C CNN
+ 1 9600 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 686B83EB
+P 8450 6750
+F 0 "U13" H 8450 6750 60 0000 C CNN
+F 1 "d_and" H 8500 6850 60 0000 C CNN
+F 2 "" H 8450 6750 60 0000 C CNN
+F 3 "" H 8450 6750 60 0000 C CNN
+ 1 8450 6750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U30
+U 1 1 686B83F7
+P 9600 7250
+F 0 "U30" H 9600 7250 60 0000 C CNN
+F 1 "d_and" H 9650 7350 60 0000 C CNN
+F 2 "" H 9600 7250 60 0000 C CNN
+F 3 "" H 9600 7250 60 0000 C CNN
+ 1 9600 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 686B83FD
+P 8450 7200
+F 0 "U14" H 8450 7200 60 0000 C CNN
+F 1 "d_and" H 8500 7300 60 0000 C CNN
+F 2 "" H 8450 7200 60 0000 C CNN
+F 3 "" H 8450 7200 60 0000 C CNN
+ 1 8450 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U43
+U 1 1 686BACAA
+P 10900 8150
+F 0 "U43" H 10900 8150 60 0000 C CNN
+F 1 "d_or" H 10900 8250 60 0000 C CNN
+F 2 "" H 10900 8150 60 0000 C CNN
+F 3 "" H 10900 8150 60 0000 C CNN
+ 1 10900 8150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U49
+U 1 1 686BACB0
+P 12400 8600
+F 0 "U49" H 12400 8600 60 0000 C CNN
+F 1 "d_nor" H 12450 8700 60 0000 C CNN
+F 2 "" H 12400 8600 60 0000 C CNN
+F 3 "" H 12400 8600 60 0000 C CNN
+ 1 12400 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U53
+U 1 1 686BACB6
+P 13550 8550
+F 0 "U53" H 13550 8450 60 0000 C CNN
+F 1 "d_inverter" H 13550 8700 60 0000 C CNN
+F 2 "" H 13600 8500 60 0000 C CNN
+F 3 "" H 13600 8500 60 0000 C CNN
+ 1 13550 8550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_tristate U57
+U 1 1 686BACBC
+P 14750 8900
+F 0 "U57" H 14500 9150 60 0000 C CNN
+F 1 "d_tristate" H 14550 9350 60 0000 C CNN
+F 2 "" H 14650 9250 60 0000 C CNN
+F 3 "" H 14650 9250 60 0000 C CNN
+ 1 14750 8900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U31
+U 1 1 686BACD2
+P 9600 7750
+F 0 "U31" H 9600 7750 60 0000 C CNN
+F 1 "d_and" H 9650 7850 60 0000 C CNN
+F 2 "" H 9600 7750 60 0000 C CNN
+F 3 "" H 9600 7750 60 0000 C CNN
+ 1 9600 7750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U15
+U 1 1 686BACD8
+P 8450 7700
+F 0 "U15" H 8450 7700 60 0000 C CNN
+F 1 "d_and" H 8500 7800 60 0000 C CNN
+F 2 "" H 8450 7700 60 0000 C CNN
+F 3 "" H 8450 7700 60 0000 C CNN
+ 1 8450 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U44
+U 1 1 686BACEA
+P 10900 9050
+F 0 "U44" H 10900 9050 60 0000 C CNN
+F 1 "d_or" H 10900 9150 60 0000 C CNN
+F 2 "" H 10900 9050 60 0000 C CNN
+F 3 "" H 10900 9050 60 0000 C CNN
+ 1 10900 9050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U32
+U 1 1 686BACF1
+P 9600 8400
+F 0 "U32" H 9600 8400 60 0000 C CNN
+F 1 "d_and" H 9650 8500 60 0000 C CNN
+F 2 "" H 9600 8400 60 0000 C CNN
+F 3 "" H 9600 8400 60 0000 C CNN
+ 1 9600 8400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U16
+U 1 1 686BACF7
+P 8450 8350
+F 0 "U16" H 8450 8350 60 0000 C CNN
+F 1 "d_and" H 8500 8450 60 0000 C CNN
+F 2 "" H 8450 8350 60 0000 C CNN
+F 3 "" H 8450 8350 60 0000 C CNN
+ 1 8450 8350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U33
+U 1 1 686BAD03
+P 9600 8800
+F 0 "U33" H 9600 8800 60 0000 C CNN
+F 1 "d_and" H 9650 8900 60 0000 C CNN
+F 2 "" H 9600 8800 60 0000 C CNN
+F 3 "" H 9600 8800 60 0000 C CNN
+ 1 9600 8800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U17
+U 1 1 686BAD09
+P 8450 8750
+F 0 "U17" H 8450 8750 60 0000 C CNN
+F 1 "d_and" H 8500 8850 60 0000 C CNN
+F 2 "" H 8450 8750 60 0000 C CNN
+F 3 "" H 8450 8750 60 0000 C CNN
+ 1 8450 8750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U34
+U 1 1 686BAD15
+P 9600 9250
+F 0 "U34" H 9600 9250 60 0000 C CNN
+F 1 "d_and" H 9650 9350 60 0000 C CNN
+F 2 "" H 9600 9250 60 0000 C CNN
+F 3 "" H 9600 9250 60 0000 C CNN
+ 1 9600 9250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U18
+U 1 1 686BAD1B
+P 8450 9200
+F 0 "U18" H 8450 9200 60 0000 C CNN
+F 1 "d_and" H 8500 9300 60 0000 C CNN
+F 2 "" H 8450 9200 60 0000 C CNN
+F 3 "" H 8450 9200 60 0000 C CNN
+ 1 8450 9200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U39
+U 1 1 686BAD27
+P 10850 10450
+F 0 "U39" H 10850 10450 60 0000 C CNN
+F 1 "d_or" H 10850 10550 60 0000 C CNN
+F 2 "" H 10850 10450 60 0000 C CNN
+F 3 "" H 10850 10450 60 0000 C CNN
+ 1 10850 10450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U47
+U 1 1 686BAD2D
+P 12350 10900
+F 0 "U47" H 12350 10900 60 0000 C CNN
+F 1 "d_nor" H 12400 11000 60 0000 C CNN
+F 2 "" H 12350 10900 60 0000 C CNN
+F 3 "" H 12350 10900 60 0000 C CNN
+ 1 12350 10900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U51
+U 1 1 686BAD33
+P 13500 10850
+F 0 "U51" H 13500 10750 60 0000 C CNN
+F 1 "d_inverter" H 13500 11000 60 0000 C CNN
+F 2 "" H 13550 10800 60 0000 C CNN
+F 3 "" H 13550 10800 60 0000 C CNN
+ 1 13500 10850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_tristate U55
+U 1 1 686BAD39
+P 14700 11200
+F 0 "U55" H 14450 11450 60 0000 C CNN
+F 1 "d_tristate" H 14500 11650 60 0000 C CNN
+F 2 "" H 14600 11550 60 0000 C CNN
+F 3 "" H 14600 11550 60 0000 C CNN
+ 1 14700 11200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U23
+U 1 1 686BAD4F
+P 9550 10050
+F 0 "U23" H 9550 10050 60 0000 C CNN
+F 1 "d_and" H 9600 10150 60 0000 C CNN
+F 2 "" H 9550 10050 60 0000 C CNN
+F 3 "" H 9550 10050 60 0000 C CNN
+ 1 9550 10050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U7
+U 1 1 686BAD55
+P 8400 10000
+F 0 "U7" H 8400 10000 60 0000 C CNN
+F 1 "d_and" H 8450 10100 60 0000 C CNN
+F 2 "" H 8400 10000 60 0000 C CNN
+F 3 "" H 8400 10000 60 0000 C CNN
+ 1 8400 10000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U40
+U 1 1 686BAD67
+P 10850 11350
+F 0 "U40" H 10850 11350 60 0000 C CNN
+F 1 "d_or" H 10850 11450 60 0000 C CNN
+F 2 "" H 10850 11350 60 0000 C CNN
+F 3 "" H 10850 11350 60 0000 C CNN
+ 1 10850 11350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U24
+U 1 1 686BAD6E
+P 9550 10700
+F 0 "U24" H 9550 10700 60 0000 C CNN
+F 1 "d_and" H 9600 10800 60 0000 C CNN
+F 2 "" H 9550 10700 60 0000 C CNN
+F 3 "" H 9550 10700 60 0000 C CNN
+ 1 9550 10700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U8
+U 1 1 686BAD74
+P 8400 10650
+F 0 "U8" H 8400 10650 60 0000 C CNN
+F 1 "d_and" H 8450 10750 60 0000 C CNN
+F 2 "" H 8400 10650 60 0000 C CNN
+F 3 "" H 8400 10650 60 0000 C CNN
+ 1 8400 10650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U25
+U 1 1 686BAD80
+P 9550 11100
+F 0 "U25" H 9550 11100 60 0000 C CNN
+F 1 "d_and" H 9600 11200 60 0000 C CNN
+F 2 "" H 9550 11100 60 0000 C CNN
+F 3 "" H 9550 11100 60 0000 C CNN
+ 1 9550 11100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U9
+U 1 1 686BAD86
+P 8400 11050
+F 0 "U9" H 8400 11050 60 0000 C CNN
+F 1 "d_and" H 8450 11150 60 0000 C CNN
+F 2 "" H 8400 11050 60 0000 C CNN
+F 3 "" H 8400 11050 60 0000 C CNN
+ 1 8400 11050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U26
+U 1 1 686BAD92
+P 9550 11550
+F 0 "U26" H 9550 11550 60 0000 C CNN
+F 1 "d_and" H 9600 11650 60 0000 C CNN
+F 2 "" H 9550 11550 60 0000 C CNN
+F 3 "" H 9550 11550 60 0000 C CNN
+ 1 9550 11550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U10
+U 1 1 686BAD98
+P 8400 11500
+F 0 "U10" H 8400 11500 60 0000 C CNN
+F 1 "d_and" H 8450 11600 60 0000 C CNN
+F 2 "" H 8400 11500 60 0000 C CNN
+F 3 "" H 8400 11500 60 0000 C CNN
+ 1 8400 11500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 686D2C79
+P 5550 2550
+F 0 "U2" H 5550 2450 60 0000 C CNN
+F 1 "d_inverter" H 5550 2700 60 0000 C CNN
+F 2 "" H 5600 2500 60 0000 C CNN
+F 3 "" H 5600 2500 60 0000 C CNN
+ 1 5550 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 686D2D8F
+P 6700 2550
+F 0 "U5" H 6700 2450 60 0000 C CNN
+F 1 "d_inverter" H 6700 2700 60 0000 C CNN
+F 2 "" H 6750 2500 60 0000 C CNN
+F 3 "" H 6750 2500 60 0000 C CNN
+ 1 6700 2550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 10100 3600 10300 3600
+Wire Wire Line
+ 10300 3600 10300 3750
+Wire Wire Line
+ 10300 3750 10500 3750
+Wire Wire Line
+ 10100 4050 10300 4050
+Wire Wire Line
+ 10300 4050 10300 3850
+Wire Wire Line
+ 10300 3850 10500 3850
+Wire Wire Line
+ 11400 3800 11400 4200
+Wire Wire Line
+ 11400 4200 12000 4200
+Wire Wire Line
+ 11400 4700 11400 4300
+Wire Wire Line
+ 11400 4300 12000 4300
+Wire Wire Line
+ 12900 4250 13300 4250
+Wire Wire Line
+ 13900 4250 14200 4250
+Wire Wire Line
+ 15350 4250 16050 4250
+Wire Wire Line
+ 5150 1750 8000 1750
+Wire Wire Line
+ 8600 1750 15700 1750
+Wire Wire Line
+ 14750 4550 14750 4950
+Wire Wire Line
+ 14750 4950 15700 4950
+Wire Wire Line
+ 6200 2100 6400 2100
+Wire Wire Line
+ 5600 2100 5150 2100
+Wire Wire Line
+ 8950 3350 9200 3350
+Wire Wire Line
+ 9200 3450 9000 3450
+Wire Wire Line
+ 9000 3450 9000 3600
+Wire Wire Line
+ 9000 3600 5200 3600
+Wire Wire Line
+ 5950 3400 8050 3400
+Wire Wire Line
+ 6300 3300 8050 3300
+Wire Wire Line
+ 10300 4750 10500 4750
+Wire Wire Line
+ 10300 4900 10300 4750
+Wire Wire Line
+ 10100 4900 10300 4900
+Wire Wire Line
+ 10300 4650 10500 4650
+Wire Wire Line
+ 10300 4450 10300 4650
+Wire Wire Line
+ 10100 4450 10300 4450
+Wire Wire Line
+ 10100 3400 10100 3600
+Wire Wire Line
+ 8950 4000 9200 4000
+Wire Wire Line
+ 9200 4100 9000 4100
+Wire Wire Line
+ 9000 4100 9000 4250
+Wire Wire Line
+ 9000 4250 5250 4250
+Wire Wire Line
+ 5950 4050 8050 4050
+Wire Wire Line
+ 7150 3950 8050 3950
+Wire Wire Line
+ 8950 4400 9200 4400
+Wire Wire Line
+ 9200 4500 9000 4500
+Wire Wire Line
+ 9000 4500 9000 4650
+Wire Wire Line
+ 9000 4650 5250 4650
+Wire Wire Line
+ 6300 4350 8050 4350
+Wire Wire Line
+ 7000 4450 8050 4450
+Wire Wire Line
+ 8950 4850 9200 4850
+Wire Wire Line
+ 9200 4950 9000 4950
+Wire Wire Line
+ 9000 4950 9000 5100
+Wire Wire Line
+ 9000 5100 5250 5100
+Wire Wire Line
+ 7000 4900 8050 4900
+Wire Wire Line
+ 7150 4800 8050 4800
+Wire Wire Line
+ 10050 5900 10250 5900
+Wire Wire Line
+ 10250 5900 10250 6050
+Wire Wire Line
+ 10250 6050 10450 6050
+Wire Wire Line
+ 10050 6350 10250 6350
+Wire Wire Line
+ 10250 6350 10250 6150
+Wire Wire Line
+ 10250 6150 10450 6150
+Wire Wire Line
+ 11350 6100 11350 6500
+Wire Wire Line
+ 11350 6500 11950 6500
+Wire Wire Line
+ 11350 7000 11350 6600
+Wire Wire Line
+ 11350 6600 11950 6600
+Wire Wire Line
+ 12850 6550 13250 6550
+Wire Wire Line
+ 13850 6550 14150 6550
+Wire Wire Line
+ 15300 6550 16000 6550
+Wire Wire Line
+ 14700 6850 14700 7250
+Wire Wire Line
+ 14700 7250 15700 7250
+Wire Wire Line
+ 8900 5650 9150 5650
+Wire Wire Line
+ 9150 5750 8950 5750
+Wire Wire Line
+ 8950 5750 8950 5900
+Wire Wire Line
+ 8950 5900 5750 5900
+Wire Wire Line
+ 5950 5700 8000 5700
+Wire Wire Line
+ 6300 5600 8000 5600
+Wire Wire Line
+ 10250 7050 10450 7050
+Wire Wire Line
+ 10250 7200 10250 7050
+Wire Wire Line
+ 10050 7200 10250 7200
+Wire Wire Line
+ 10250 6950 10450 6950
+Wire Wire Line
+ 10250 6750 10250 6950
+Wire Wire Line
+ 10050 6750 10250 6750
+Wire Wire Line
+ 10050 5700 10050 5900
+Wire Wire Line
+ 8900 6300 9150 6300
+Wire Wire Line
+ 9150 6400 8950 6400
+Wire Wire Line
+ 8950 6400 8950 6550
+Wire Wire Line
+ 8950 6550 5500 6550
+Wire Wire Line
+ 5950 6350 8000 6350
+Wire Wire Line
+ 7150 6250 8000 6250
+Wire Wire Line
+ 8900 6700 9150 6700
+Wire Wire Line
+ 9150 6800 8950 6800
+Wire Wire Line
+ 8950 6800 8950 6950
+Wire Wire Line
+ 8950 6950 5400 6950
+Wire Wire Line
+ 6300 6650 8000 6650
+Wire Wire Line
+ 7000 6750 8000 6750
+Wire Wire Line
+ 8900 7150 9150 7150
+Wire Wire Line
+ 9150 7250 8950 7250
+Wire Wire Line
+ 8950 7250 8950 7400
+Wire Wire Line
+ 8950 7400 4700 7400
+Wire Wire Line
+ 7000 7200 8000 7200
+Wire Wire Line
+ 7150 7100 8000 7100
+Wire Wire Line
+ 10050 7900 10250 7900
+Wire Wire Line
+ 10250 7900 10250 8050
+Wire Wire Line
+ 10250 8050 10450 8050
+Wire Wire Line
+ 10050 8350 10250 8350
+Wire Wire Line
+ 10250 8350 10250 8150
+Wire Wire Line
+ 10250 8150 10450 8150
+Wire Wire Line
+ 11350 8100 11350 8500
+Wire Wire Line
+ 11350 8500 11950 8500
+Wire Wire Line
+ 11350 9000 11350 8600
+Wire Wire Line
+ 11350 8600 11950 8600
+Wire Wire Line
+ 12850 8550 13250 8550
+Wire Wire Line
+ 13850 8550 14150 8550
+Wire Wire Line
+ 15300 8550 16000 8550
+Wire Wire Line
+ 14700 8850 14700 9250
+Wire Wire Line
+ 14700 9250 15700 9250
+Wire Wire Line
+ 8900 7650 9150 7650
+Wire Wire Line
+ 9150 7750 8950 7750
+Wire Wire Line
+ 8950 7750 8950 7900
+Wire Wire Line
+ 8950 7900 5500 7900
+Wire Wire Line
+ 5950 7700 8000 7700
+Wire Wire Line
+ 6300 7600 8000 7600
+Wire Wire Line
+ 10250 9050 10450 9050
+Wire Wire Line
+ 10250 9200 10250 9050
+Wire Wire Line
+ 10050 9200 10250 9200
+Wire Wire Line
+ 10250 8950 10450 8950
+Wire Wire Line
+ 10250 8750 10250 8950
+Wire Wire Line
+ 10050 8750 10250 8750
+Wire Wire Line
+ 10050 7700 10050 7900
+Wire Wire Line
+ 8900 8300 9150 8300
+Wire Wire Line
+ 9150 8400 8950 8400
+Wire Wire Line
+ 8950 8400 8950 8550
+Wire Wire Line
+ 8950 8550 5400 8550
+Wire Wire Line
+ 5950 8350 8000 8350
+Wire Wire Line
+ 7150 8250 8000 8250
+Wire Wire Line
+ 8900 8700 9150 8700
+Wire Wire Line
+ 9150 8800 8950 8800
+Wire Wire Line
+ 8950 8800 8950 8950
+Wire Wire Line
+ 8950 8950 5250 8950
+Wire Wire Line
+ 6300 8650 8000 8650
+Wire Wire Line
+ 7000 8750 8000 8750
+Wire Wire Line
+ 8900 9150 9150 9150
+Wire Wire Line
+ 9150 9250 8950 9250
+Wire Wire Line
+ 8950 9250 8950 9400
+Wire Wire Line
+ 7000 9200 8000 9200
+Wire Wire Line
+ 7150 9100 8000 9100
+Wire Wire Line
+ 10000 10200 10200 10200
+Wire Wire Line
+ 10200 10200 10200 10350
+Wire Wire Line
+ 10200 10350 10400 10350
+Wire Wire Line
+ 10000 10650 10200 10650
+Wire Wire Line
+ 10200 10650 10200 10450
+Wire Wire Line
+ 10200 10450 10400 10450
+Wire Wire Line
+ 11300 10400 11300 10800
+Wire Wire Line
+ 11300 10800 11900 10800
+Wire Wire Line
+ 11300 11300 11300 10900
+Wire Wire Line
+ 11300 10900 11900 10900
+Wire Wire Line
+ 12800 10850 13200 10850
+Wire Wire Line
+ 13800 10850 14100 10850
+Wire Wire Line
+ 15250 10850 15950 10850
+Wire Wire Line
+ 14650 11150 14650 11550
+Wire Wire Line
+ 14650 11550 15700 11550
+Wire Wire Line
+ 8850 9950 9100 9950
+Wire Wire Line
+ 9100 10050 8900 10050
+Wire Wire Line
+ 8900 10050 8900 10200
+Wire Wire Line
+ 8900 10200 5400 10200
+Wire Wire Line
+ 5950 10000 7950 10000
+Wire Wire Line
+ 6300 9900 7950 9900
+Wire Wire Line
+ 10200 11350 10400 11350
+Wire Wire Line
+ 10200 11500 10200 11350
+Wire Wire Line
+ 10000 11500 10200 11500
+Wire Wire Line
+ 10200 11250 10400 11250
+Wire Wire Line
+ 10200 11050 10200 11250
+Wire Wire Line
+ 10000 11050 10200 11050
+Wire Wire Line
+ 10000 10000 10000 10200
+Wire Wire Line
+ 8850 10600 9100 10600
+Wire Wire Line
+ 9100 10700 8900 10700
+Wire Wire Line
+ 8900 10700 8900 10850
+Wire Wire Line
+ 8900 10850 5250 10850
+Wire Wire Line
+ 5950 10650 7950 10650
+Wire Wire Line
+ 7150 10550 7950 10550
+Wire Wire Line
+ 8850 11000 9100 11000
+Wire Wire Line
+ 9100 11100 8900 11100
+Wire Wire Line
+ 8900 11100 8900 11250
+Wire Wire Line
+ 8900 11250 5000 11250
+Wire Wire Line
+ 6300 10950 7950 10950
+Wire Wire Line
+ 7000 11050 7950 11050
+Wire Wire Line
+ 8850 11450 9100 11450
+Wire Wire Line
+ 9100 11550 8900 11550
+Wire Wire Line
+ 8900 11550 8900 11700
+Wire Wire Line
+ 8900 11700 4700 11700
+Wire Wire Line
+ 7000 11500 7950 11500
+Wire Wire Line
+ 7150 11400 7950 11400
+Wire Wire Line
+ 15700 11550 15700 1750
+Connection ~ 15700 7250
+Connection ~ 15700 9250
+Connection ~ 15700 4950
+Wire Wire Line
+ 7000 2100 7150 2100
+Wire Wire Line
+ 7150 2100 7150 11400
+Connection ~ 7150 10550
+Connection ~ 7150 9100
+Connection ~ 7150 8250
+Connection ~ 7150 7100
+Connection ~ 7150 6250
+Connection ~ 7150 4800
+Connection ~ 7150 3950
+Wire Wire Line
+ 6300 2100 6300 10950
+Connection ~ 6300 2100
+Connection ~ 6300 9900
+Connection ~ 6300 8650
+Connection ~ 6300 7600
+Connection ~ 6300 6650
+Connection ~ 6300 5600
+Connection ~ 6300 4350
+Connection ~ 6300 3300
+Wire Wire Line
+ 5850 2550 6400 2550
+Wire Wire Line
+ 5250 2550 4900 2550
+Wire Wire Line
+ 7000 2550 7000 11500
+Connection ~ 7000 11050
+Connection ~ 7000 8750
+Wire Wire Line
+ 8950 9400 4700 9400
+Connection ~ 7000 9200
+Connection ~ 7000 7200
+Connection ~ 7000 6750
+Connection ~ 7000 4900
+Connection ~ 7000 4450
+Wire Wire Line
+ 5950 10650 5950 2550
+Connection ~ 5950 2550
+Connection ~ 5950 10000
+Connection ~ 5950 7700
+Connection ~ 5950 8350
+Connection ~ 5950 5700
+Connection ~ 5950 6350
+Connection ~ 5950 3400
+Connection ~ 5950 4050
+Wire Wire Line
+ 5750 5900 5750 4250
+Connection ~ 5750 4250
+Wire Wire Line
+ 5500 7900 5500 4650
+Connection ~ 5500 4650
+Wire Wire Line
+ 5400 10200 5400 5100
+Connection ~ 5400 5100
+Connection ~ 5500 6550
+Connection ~ 5400 6950
+Wire Wire Line
+ 5250 10850 5250 7400
+Connection ~ 5250 7400
+Connection ~ 5250 8950
+Connection ~ 5400 8550
+Wire Wire Line
+ 5000 11250 5000 9400
+Connection ~ 5000 9400
+Text Label 5150 1750 0 60 ~ 0
+13
+Text Label 5150 2100 0 60 ~ 0
+10
+Text Label 4900 2550 0 60 ~ 0
+9
+Text Label 5200 3600 0 60 ~ 0
+7
+Text Label 5250 4250 0 60 ~ 0
+6
+Text Label 5250 4650 0 60 ~ 0
+5
+Text Label 5250 5100 0 60 ~ 0
+4
+Text Label 4700 7400 0 60 ~ 0
+3
+Text Label 4700 9400 0 60 ~ 0
+2
+Text Label 4700 11700 0 60 ~ 0
+1
+Text Label 15950 10850 0 60 ~ 0
+15
+Text Label 16000 8550 0 60 ~ 0
+14
+Text Label 16000 6550 0 60 ~ 0
+12
+Text Label 16050 4250 0 60 ~ 0
+11
+$Comp
+L PORT U1
+U 2 1 687206A9
+P 4450 9400
+F 0 "U1" H 4500 9500 30 0000 C CNN
+F 1 "PORT" H 4450 9400 30 0000 C CNN
+F 2 "" H 4450 9400 60 0000 C CNN
+F 3 "" H 4450 9400 60 0000 C CNN
+ 2 4450 9400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68720740
+P 5000 4250
+F 0 "U1" H 5050 4350 30 0000 C CNN
+F 1 "PORT" H 5000 4250 30 0000 C CNN
+F 2 "" H 5000 4250 60 0000 C CNN
+F 3 "" H 5000 4250 60 0000 C CNN
+ 6 5000 4250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 687207D5
+P 4900 2100
+F 0 "U1" H 4950 2200 30 0000 C CNN
+F 1 "PORT" H 4900 2100 30 0000 C CNN
+F 2 "" H 4900 2100 60 0000 C CNN
+F 3 "" H 4900 2100 60 0000 C CNN
+ 10 4900 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 687208C2
+P 16250 6550
+F 0 "U1" H 16300 6650 30 0000 C CNN
+F 1 "PORT" H 16250 6550 30 0000 C CNN
+F 2 "" H 16250 6550 60 0000 C CNN
+F 3 "" H 16250 6550 60 0000 C CNN
+ 12 16250 6550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 687209A1
+P 4450 11700
+F 0 "U1" H 4500 11800 30 0000 C CNN
+F 1 "PORT" H 4450 11700 30 0000 C CNN
+F 2 "" H 4450 11700 60 0000 C CNN
+F 3 "" H 4450 11700 60 0000 C CNN
+ 1 4450 11700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68720A3C
+P 5000 4650
+F 0 "U1" H 5050 4750 30 0000 C CNN
+F 1 "PORT" H 5000 4650 30 0000 C CNN
+F 2 "" H 5000 4650 60 0000 C CNN
+F 3 "" H 5000 4650 60 0000 C CNN
+ 5 5000 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68720AD5
+P 17200 8700
+F 0 "U1" H 17250 8800 30 0000 C CNN
+F 1 "PORT" H 17200 8700 30 0000 C CNN
+F 2 "" H 17200 8700 60 0000 C CNN
+F 3 "" H 17200 8700 60 0000 C CNN
+ 8 17200 8700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68720B6A
+P 4900 1750
+F 0 "U1" H 4950 1850 30 0000 C CNN
+F 1 "PORT" H 4900 1750 30 0000 C CNN
+F 2 "" H 4900 1750 60 0000 C CNN
+F 3 "" H 4900 1750 60 0000 C CNN
+ 13 4900 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68720C03
+P 4450 7400
+F 0 "U1" H 4500 7500 30 0000 C CNN
+F 1 "PORT" H 4450 7400 30 0000 C CNN
+F 2 "" H 4450 7400 60 0000 C CNN
+F 3 "" H 4450 7400 60 0000 C CNN
+ 3 4450 7400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68720CB4
+P 4950 3600
+F 0 "U1" H 5000 3700 30 0000 C CNN
+F 1 "PORT" H 4950 3600 30 0000 C CNN
+F 2 "" H 4950 3600 60 0000 C CNN
+F 3 "" H 4950 3600 60 0000 C CNN
+ 7 4950 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68720D51
+P 16300 4250
+F 0 "U1" H 16350 4350 30 0000 C CNN
+F 1 "PORT" H 16300 4250 30 0000 C CNN
+F 2 "" H 16300 4250 60 0000 C CNN
+F 3 "" H 16300 4250 60 0000 C CNN
+ 11 16300 4250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 68720DF4
+P 16200 10850
+F 0 "U1" H 16250 10950 30 0000 C CNN
+F 1 "PORT" H 16200 10850 30 0000 C CNN
+F 2 "" H 16200 10850 60 0000 C CNN
+F 3 "" H 16200 10850 60 0000 C CNN
+ 15 16200 10850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68720E95
+P 5000 5100
+F 0 "U1" H 5050 5200 30 0000 C CNN
+F 1 "PORT" H 5000 5100 30 0000 C CNN
+F 2 "" H 5000 5100 60 0000 C CNN
+F 3 "" H 5000 5100 60 0000 C CNN
+ 4 5000 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 68720F5C
+P 4650 2550
+F 0 "U1" H 4700 2650 30 0000 C CNN
+F 1 "PORT" H 4650 2550 30 0000 C CNN
+F 2 "" H 4650 2550 60 0000 C CNN
+F 3 "" H 4650 2550 60 0000 C CNN
+ 9 4650 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 68721001
+P 16250 8550
+F 0 "U1" H 16300 8650 30 0000 C CNN
+F 1 "PORT" H 16250 8550 30 0000 C CNN
+F 2 "" H 16250 8550 60 0000 C CNN
+F 3 "" H 16250 8550 60 0000 C CNN
+ 14 16250 8550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 687210AA
+P 17200 8900
+F 0 "U1" H 17250 9000 30 0000 C CNN
+F 1 "PORT" H 17200 8900 30 0000 C CNN
+F 2 "" H 17200 8900 60 0000 C CNN
+F 3 "" H 17200 8900 60 0000 C CNN
+ 16 17200 8900
+ 1 0 0 -1
+$EndComp
+NoConn ~ 17450 8700
+NoConn ~ 17450 8900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350.sub b/library/SubcircuitLibrary/SN74S350/SN74S350.sub
new file mode 100644
index 000000000..1dbde6d5e
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S350/SN74S350.sub
@@ -0,0 +1,234 @@
+* Subcircuit SN74S350
+.subckt SN74S350 /1 /2 /3 /4 /5 /6 /7 ? /9 /10 /11 /12 /13 /14 /15 ?
+* d:\fossee\esim\library\subcircuitlibrary\sn74s350\sn74s350.cir
+* u45 net-_u35-pad3_ net-_u36-pad3_ net-_u45-pad3_ d_or
+* u50 net-_u45-pad3_ net-_u46-pad3_ net-_u50-pad3_ d_nor
+* u54 net-_u50-pad3_ net-_u54-pad2_ d_inverter
+* u58 net-_u54-pad2_ net-_u55-pad2_ /11 d_tristate
+* u6 /13 net-_u55-pad2_ d_inverter
+* u3 /10 net-_u11-pad1_ d_inverter
+* u4 net-_u11-pad1_ net-_u10-pad1_ d_inverter
+* u35 net-_u19-pad3_ /7 net-_u35-pad3_ d_and
+* u19 net-_u11-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_and
+* u46 net-_u37-pad3_ net-_u38-pad3_ net-_u46-pad3_ d_or
+* u36 net-_u20-pad3_ /6 net-_u36-pad3_ d_and
+* u20 net-_u10-pad1_ net-_u11-pad2_ net-_u20-pad3_ d_and
+* u37 net-_u21-pad3_ /5 net-_u37-pad3_ d_and
+* u21 net-_u11-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and
+* u38 net-_u22-pad3_ /4 net-_u38-pad3_ d_and
+* u22 net-_u10-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and
+* u41 net-_u27-pad3_ net-_u28-pad3_ net-_u41-pad3_ d_or
+* u48 net-_u41-pad3_ net-_u42-pad3_ net-_u48-pad3_ d_nor
+* u52 net-_u48-pad3_ net-_u52-pad2_ d_inverter
+* u56 net-_u52-pad2_ net-_u55-pad2_ /12 d_tristate
+* u27 net-_u11-pad3_ /6 net-_u27-pad3_ d_and
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and
+* u42 net-_u29-pad3_ net-_u30-pad3_ net-_u42-pad3_ d_or
+* u28 net-_u12-pad3_ /5 net-_u28-pad3_ d_and
+* u12 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad3_ d_and
+* u29 net-_u13-pad3_ /4 net-_u29-pad3_ d_and
+* u13 net-_u11-pad1_ net-_u10-pad2_ net-_u13-pad3_ d_and
+* u30 net-_u14-pad3_ /3 net-_u30-pad3_ d_and
+* u14 net-_u10-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_and
+* u43 net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_or
+* u49 net-_u43-pad3_ net-_u44-pad3_ net-_u49-pad3_ d_nor
+* u53 net-_u49-pad3_ net-_u53-pad2_ d_inverter
+* u57 net-_u53-pad2_ net-_u55-pad2_ /14 d_tristate
+* u31 net-_u15-pad3_ /5 net-_u31-pad3_ d_and
+* u15 net-_u11-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and
+* u44 net-_u33-pad3_ net-_u34-pad3_ net-_u44-pad3_ d_or
+* u32 net-_u16-pad3_ /4 net-_u32-pad3_ d_and
+* u16 net-_u10-pad1_ net-_u11-pad2_ net-_u16-pad3_ d_and
+* u33 net-_u17-pad3_ /3 net-_u33-pad3_ d_and
+* u17 net-_u11-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and
+* u34 net-_u18-pad3_ /2 net-_u34-pad3_ d_and
+* u18 net-_u10-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and
+* u39 net-_u23-pad3_ net-_u24-pad3_ net-_u39-pad3_ d_or
+* u47 net-_u39-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor
+* u51 net-_u47-pad3_ net-_u51-pad2_ d_inverter
+* u55 net-_u51-pad2_ net-_u55-pad2_ /15 d_tristate
+* u23 net-_u23-pad1_ /4 net-_u23-pad3_ d_and
+* u7 net-_u11-pad1_ net-_u11-pad2_ net-_u23-pad1_ d_and
+* u40 net-_u25-pad3_ net-_u26-pad3_ net-_u40-pad3_ d_or
+* u24 net-_u24-pad1_ /3 net-_u24-pad3_ d_and
+* u8 net-_u10-pad1_ net-_u11-pad2_ net-_u24-pad1_ d_and
+* u25 net-_u25-pad1_ /2 net-_u25-pad3_ d_and
+* u9 net-_u11-pad1_ net-_u10-pad2_ net-_u25-pad1_ d_and
+* u26 net-_u10-pad3_ /1 net-_u26-pad3_ d_and
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u2 /9 net-_u11-pad2_ d_inverter
+* u5 net-_u11-pad2_ net-_u10-pad2_ d_inverter
+a1 [net-_u35-pad3_ net-_u36-pad3_ ] net-_u45-pad3_ u45
+a2 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u50-pad3_ u50
+a3 net-_u50-pad3_ net-_u54-pad2_ u54
+a4 net-_u54-pad2_ net-_u55-pad2_ /11 u58
+a5 /13 net-_u55-pad2_ u6
+a6 /10 net-_u11-pad1_ u3
+a7 net-_u11-pad1_ net-_u10-pad1_ u4
+a8 [net-_u19-pad3_ /7 ] net-_u35-pad3_ u35
+a9 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19
+a10 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u46-pad3_ u46
+a11 [net-_u20-pad3_ /6 ] net-_u36-pad3_ u36
+a12 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u20-pad3_ u20
+a13 [net-_u21-pad3_ /5 ] net-_u37-pad3_ u37
+a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21
+a15 [net-_u22-pad3_ /4 ] net-_u38-pad3_ u38
+a16 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22
+a17 [net-_u27-pad3_ net-_u28-pad3_ ] net-_u41-pad3_ u41
+a18 [net-_u41-pad3_ net-_u42-pad3_ ] net-_u48-pad3_ u48
+a19 net-_u48-pad3_ net-_u52-pad2_ u52
+a20 net-_u52-pad2_ net-_u55-pad2_ /12 u56
+a21 [net-_u11-pad3_ /6 ] net-_u27-pad3_ u27
+a22 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u42-pad3_ u42
+a24 [net-_u12-pad3_ /5 ] net-_u28-pad3_ u28
+a25 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u12-pad3_ u12
+a26 [net-_u13-pad3_ /4 ] net-_u29-pad3_ u29
+a27 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u13-pad3_ u13
+a28 [net-_u14-pad3_ /3 ] net-_u30-pad3_ u30
+a29 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14
+a30 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43
+a31 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u49-pad3_ u49
+a32 net-_u49-pad3_ net-_u53-pad2_ u53
+a33 net-_u53-pad2_ net-_u55-pad2_ /14 u57
+a34 [net-_u15-pad3_ /5 ] net-_u31-pad3_ u31
+a35 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15
+a36 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u44-pad3_ u44
+a37 [net-_u16-pad3_ /4 ] net-_u32-pad3_ u32
+a38 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u16-pad3_ u16
+a39 [net-_u17-pad3_ /3 ] net-_u33-pad3_ u33
+a40 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17
+a41 [net-_u18-pad3_ /2 ] net-_u34-pad3_ u34
+a42 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18
+a43 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u39-pad3_ u39
+a44 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47
+a45 net-_u47-pad3_ net-_u51-pad2_ u51
+a46 net-_u51-pad2_ net-_u55-pad2_ /15 u55
+a47 [net-_u23-pad1_ /4 ] net-_u23-pad3_ u23
+a48 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u23-pad1_ u7
+a49 [net-_u25-pad3_ net-_u26-pad3_ ] net-_u40-pad3_ u40
+a50 [net-_u24-pad1_ /3 ] net-_u24-pad3_ u24
+a51 [net-_u10-pad1_ net-_u11-pad2_ ] net-_u24-pad1_ u8
+a52 [net-_u25-pad1_ /2 ] net-_u25-pad3_ u25
+a53 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u25-pad1_ u9
+a54 [net-_u10-pad3_ /1 ] net-_u26-pad3_ u26
+a55 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a56 /9 net-_u11-pad2_ u2
+a57 net-_u11-pad2_ net-_u10-pad2_ u5
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u45 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u54 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u58 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u46 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u37 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u38 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u52 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u56 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u42 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u43 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u57 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u44 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u39 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u51 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_tristate, NgSpice Name: d_tristate
+.model u55 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u40 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN74S350
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S350/SN74S350_Previous_Values.xml b/library/SubcircuitLibrary/SN74S350/SN74S350_Previous_Values.xml
new file mode 100644
index 000000000..2aa4f4922
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S350/SN74S350_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_ord_nord_inverterd_tristated_inverterd_inverterd_inverterd_andd_andd_ord_andd_andd_andd_andd_andd_andd_ord_nord_inverterd_tristated_andd_andd_ord_andd_andd_andd_andd_andd_andd_ord_nord_inverterd_tristated_andd_andd_ord_andd_andd_andd_andd_andd_andd_ord_nord_inverterd_tristated_andd_andd_ord_andd_andd_andd_andd_andd_andd_inverterd_inverter
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SN74S350/analysis b/library/SubcircuitLibrary/SN74S350/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SN74S350/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1-cache.lib b/library/SubcircuitLibrary/SR_FF1/SR_FF1-cache.lib
new file mode 100644
index 000000000..ce6d8814c
--- /dev/null
+++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir b/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir
new file mode 100644
index 000000000..ba6a8f971
--- /dev/null
+++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir
@@ -0,0 +1,15 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\SR_FF\SR_FF.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/05/25 17:59:43
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_nand
+U4 Net-_U2-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_nand
+U5 Net-_U1-Pad5_ Net-_U3-Pad3_ Net-_U1-Pad4_ d_nand
+U3 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad3_ d_nand
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir.out b/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir.out
new file mode 100644
index 000000000..33d1c4912
--- /dev/null
+++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.cir.out
@@ -0,0 +1,28 @@
+* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand
+* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand
+* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4
+a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5
+a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.pro b/library/SubcircuitLibrary/SR_FF1/SR_FF1.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.sch b/library/SubcircuitLibrary/SR_FF1/SR_FF1.sch
new file mode 100644
index 000000000..58667c880
--- /dev/null
+++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.sch
@@ -0,0 +1,198 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nand U2
+U 1 1 686919A7
+P 4350 2800
+F 0 "U2" H 4350 2800 60 0000 C CNN
+F 1 "d_nand" H 4400 2900 60 0000 C CNN
+F 2 "" H 4350 2800 60 0000 C CNN
+F 3 "" H 4350 2800 60 0000 C CNN
+ 1 4350 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 686919EC
+P 5850 2800
+F 0 "U4" H 5850 2800 60 0000 C CNN
+F 1 "d_nand" H 5900 2900 60 0000 C CNN
+F 2 "" H 5850 2800 60 0000 C CNN
+F 3 "" H 5850 2800 60 0000 C CNN
+ 1 5850 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U5
+U 1 1 68691A1F
+P 5900 4000
+F 0 "U5" H 5900 4000 60 0000 C CNN
+F 1 "d_nand" H 5950 4100 60 0000 C CNN
+F 2 "" H 5900 4000 60 0000 C CNN
+F 3 "" H 5900 4000 60 0000 C CNN
+ 1 5900 4000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6300 2750 6800 2750
+Wire Wire Line
+ 6350 3950 7000 3950
+Wire Wire Line
+ 6700 2750 6700 3300
+Wire Wire Line
+ 6700 3300 5200 3300
+Wire Wire Line
+ 5200 3300 5200 3900
+Wire Wire Line
+ 5200 3900 5450 3900
+Connection ~ 6700 2750
+Wire Wire Line
+ 6550 3950 6550 3050
+Wire Wire Line
+ 6550 3050 5250 3050
+Wire Wire Line
+ 5250 3050 5250 2800
+Wire Wire Line
+ 5250 2800 5400 2800
+Connection ~ 6550 3950
+$Comp
+L d_nand U3
+U 1 1 68691A8B
+P 4350 4050
+F 0 "U3" H 4350 4050 60 0000 C CNN
+F 1 "d_nand" H 4400 4150 60 0000 C CNN
+F 2 "" H 4350 4050 60 0000 C CNN
+F 3 "" H 4350 4050 60 0000 C CNN
+ 1 4350 4050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 2750 4900 2750
+Wire Wire Line
+ 4900 2750 4900 2700
+Wire Wire Line
+ 4900 2700 5400 2700
+Wire Wire Line
+ 4800 4000 5450 4000
+Wire Wire Line
+ 3900 2800 3600 2800
+Wire Wire Line
+ 3600 2800 3600 3950
+Wire Wire Line
+ 3600 3950 3900 3950
+Wire Wire Line
+ 3900 2700 3150 2700
+Wire Wire Line
+ 3900 4050 3150 4050
+Wire Wire Line
+ 3600 3350 2400 3350
+Connection ~ 3600 3350
+$Comp
+L PORT U1
+U 4 1 68691B28
+P 7250 3950
+F 0 "U1" H 7300 4050 30 0000 C CNN
+F 1 "PORT" H 7250 3950 30 0000 C CNN
+F 2 "" H 7250 3950 60 0000 C CNN
+F 3 "" H 7250 3950 60 0000 C CNN
+ 4 7250 3950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68691BB8
+P 7050 2750
+F 0 "U1" H 7100 2850 30 0000 C CNN
+F 1 "PORT" H 7050 2750 30 0000 C CNN
+F 2 "" H 7050 2750 60 0000 C CNN
+F 3 "" H 7050 2750 60 0000 C CNN
+ 5 7050 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68691BFB
+P 2900 4050
+F 0 "U1" H 2950 4150 30 0000 C CNN
+F 1 "PORT" H 2900 4050 30 0000 C CNN
+F 2 "" H 2900 4050 60 0000 C CNN
+F 3 "" H 2900 4050 60 0000 C CNN
+ 3 2900 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68691C28
+P 2150 3350
+F 0 "U1" H 2200 3450 30 0000 C CNN
+F 1 "PORT" H 2150 3350 30 0000 C CNN
+F 2 "" H 2150 3350 60 0000 C CNN
+F 3 "" H 2150 3350 60 0000 C CNN
+ 2 2150 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68691C55
+P 2900 2700
+F 0 "U1" H 2950 2800 30 0000 C CNN
+F 1 "PORT" H 2900 2700 30 0000 C CNN
+F 2 "" H 2900 2700 60 0000 C CNN
+F 3 "" H 2900 2700 60 0000 C CNN
+ 1 2900 2700
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1.sub b/library/SubcircuitLibrary/SR_FF1/SR_FF1.sub
new file mode 100644
index 000000000..97dd47178
--- /dev/null
+++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1.sub
@@ -0,0 +1,22 @@
+* Subcircuit SR_FF
+.subckt SR_FF net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* d:\fossee\esim\library\subcircuitlibrary\sr_ff\sr_ff.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_nand
+* u4 net-_u2-pad3_ net-_u1-pad4_ net-_u1-pad5_ d_nand
+* u5 net-_u1-pad5_ net-_u3-pad3_ net-_u1-pad4_ d_nand
+* u3 net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad3_ d_nand
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad4_ ] net-_u1-pad5_ u4
+a3 [net-_u1-pad5_ net-_u3-pad3_ ] net-_u1-pad4_ u5
+a4 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SR_FF
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SR_FF1/SR_FF1_Previous_Values.xml b/library/SubcircuitLibrary/SR_FF1/SR_FF1_Previous_Values.xml
new file mode 100644
index 000000000..d73809c15
--- /dev/null
+++ b/library/SubcircuitLibrary/SR_FF1/SR_FF1_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_nandd_nand
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/SR_FF1/analysis b/library/SubcircuitLibrary/SR_FF1/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/SR_FF1/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TA7642/NPN.lib b/library/SubcircuitLibrary/TA7642/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/TA7642/TA7642-cache.lib b/library/SubcircuitLibrary/TA7642/TA7642-cache.lib
new file mode 100644
index 000000000..d94d000cf
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642-cache.lib
@@ -0,0 +1,102 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.cir b/library/SubcircuitLibrary/TA7642/TA7642.cir
new file mode 100644
index 000000000..9cec887be
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.cir
@@ -0,0 +1,40 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\TA7642\TA7642.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/03/25 11:57:32
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_C1-Pad2_ eSim_NPN
+Q2 Net-_C1-Pad2_ Net-_Q2-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 12p
+R2 Net-_C1-Pad1_ Net-_Q4-Pad2_ 3.3k
+R3 Net-_Q1-Pad1_ Net-_Q3-Pad1_ 12k
+R4 Net-_Q3-Pad1_ Net-_Q4-Pad2_ 12k
+Q3 Net-_Q3-Pad1_ Net-_Q2-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+R1 Net-_Q3-Pad1_ Net-_Q2-Pad2_ 5.6k
+R5 Net-_Q1-Pad1_ Net-_C2-Pad2_ 12k
+Q4 Net-_C2-Pad2_ Net-_Q4-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 12p
+R6 Net-_Q1-Pad1_ Net-_C3-Pad2_ 12k
+Q5 Net-_C3-Pad2_ Net-_C2-Pad1_ Net-_Q10-Pad3_ eSim_NPN
+R9 Net-_Q1-Pad1_ Net-_Q6-Pad1_ 12k
+R7 Net-_C2-Pad1_ Net-_Q6-Pad1_ 12k
+Q6 Net-_Q6-Pad1_ Net-_Q6-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+R8 Net-_Q6-Pad1_ Net-_Q6-Pad2_ 12k
+R10 Net-_Q6-Pad1_ Net-_C3-Pad1_ 12k
+C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 12p
+R11 Net-_Q1-Pad1_ Net-_C4-Pad2_ 12k
+Q7 Net-_C4-Pad2_ Net-_C3-Pad1_ Net-_Q10-Pad3_ eSim_NPN
+R13 Net-_Q1-Pad1_ Net-_Q8-Pad1_ 12k
+Q8 Net-_Q8-Pad1_ Net-_Q8-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+R12 Net-_Q8-Pad1_ Net-_Q8-Pad2_ 12k
+C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 23p
+R14 Net-_Q8-Pad1_ Net-_C4-Pad1_ 74k
+R15 Net-_Q1-Pad1_ Net-_Q10-Pad2_ 12k
+Q9 Net-_Q10-Pad2_ Net-_C4-Pad1_ Net-_Q10-Pad3_ eSim_NPN
+Q10 Net-_Q1-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+U1 Net-_Q10-Pad3_ Net-_Q1-Pad2_ Net-_Q1-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.cir.out b/library/SubcircuitLibrary/TA7642/TA7642.cir.out
new file mode 100644
index 000000000..f595bee1c
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.cir.out
@@ -0,0 +1,42 @@
+* c:\fossee\esim\library\subcircuitlibrary\ta7642\ta7642.cir
+
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_c1-pad2_ Q2N2222
+q2 net-_c1-pad2_ net-_q2-pad2_ net-_q10-pad3_ Q2N2222
+c1 net-_c1-pad1_ net-_c1-pad2_ 12p
+r2 net-_c1-pad1_ net-_q4-pad2_ 3.3k
+r3 net-_q1-pad1_ net-_q3-pad1_ 12k
+r4 net-_q3-pad1_ net-_q4-pad2_ 12k
+q3 net-_q3-pad1_ net-_q2-pad2_ net-_q10-pad3_ Q2N2222
+r1 net-_q3-pad1_ net-_q2-pad2_ 5.6k
+r5 net-_q1-pad1_ net-_c2-pad2_ 12k
+q4 net-_c2-pad2_ net-_q4-pad2_ net-_q10-pad3_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 12p
+r6 net-_q1-pad1_ net-_c3-pad2_ 12k
+q5 net-_c3-pad2_ net-_c2-pad1_ net-_q10-pad3_ Q2N2222
+r9 net-_q1-pad1_ net-_q6-pad1_ 12k
+r7 net-_c2-pad1_ net-_q6-pad1_ 12k
+q6 net-_q6-pad1_ net-_q6-pad2_ net-_q10-pad3_ Q2N2222
+r8 net-_q6-pad1_ net-_q6-pad2_ 12k
+r10 net-_q6-pad1_ net-_c3-pad1_ 12k
+c3 net-_c3-pad1_ net-_c3-pad2_ 12p
+r11 net-_q1-pad1_ net-_c4-pad2_ 12k
+q7 net-_c4-pad2_ net-_c3-pad1_ net-_q10-pad3_ Q2N2222
+r13 net-_q1-pad1_ net-_q8-pad1_ 12k
+q8 net-_q8-pad1_ net-_q8-pad2_ net-_q10-pad3_ Q2N2222
+r12 net-_q8-pad1_ net-_q8-pad2_ 12k
+c4 net-_c4-pad1_ net-_c4-pad2_ 23p
+r14 net-_q8-pad1_ net-_c4-pad1_ 74k
+r15 net-_q1-pad1_ net-_q10-pad2_ 12k
+q9 net-_q10-pad2_ net-_c4-pad1_ net-_q10-pad3_ Q2N2222
+q10 net-_q1-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+* u1 net-_q10-pad3_ net-_q1-pad2_ net-_q1-pad1_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.pro b/library/SubcircuitLibrary/TA7642/TA7642.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.proj b/library/SubcircuitLibrary/TA7642/TA7642.proj
new file mode 100644
index 000000000..ce13e5ae8
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.proj
@@ -0,0 +1 @@
+schematicFile TA7642.sch
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.sch b/library/SubcircuitLibrary/TA7642/TA7642.sch
new file mode 100644
index 000000000..5d1b25184
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.sch
@@ -0,0 +1,553 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:TA7642-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q?
+U 1 1 683E8F68
+P 1950 4400
+F 0 "Q?" H 1850 4450 50 0000 R CNN
+F 1 "eSim_NPN" H 1900 4550 50 0000 R CNN
+F 2 "" H 2150 4500 29 0000 C CNN
+F 3 "" H 1950 4400 60 0000 C CNN
+ 1 1950 4400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683E8F97
+P 2150 5600
+F 0 "Q?" H 2050 5650 50 0000 R CNN
+F 1 "eSim_NPN" H 2100 5750 50 0000 R CNN
+F 2 "" H 2350 5700 29 0000 C CNN
+F 3 "" H 2150 5600 60 0000 C CNN
+ 1 2150 5600
+ -1 0 0 -1
+$EndComp
+$Comp
+L capacitor C?
+U 1 1 683E8FD6
+P 2350 4800
+F 0 "C?" H 2375 4900 50 0000 L CNN
+F 1 "12p" H 2375 4700 50 0000 L CNN
+F 2 "" H 2388 4650 30 0000 C CNN
+F 3 "" H 2350 4800 60 0000 C CNN
+ 1 2350 4800
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E9008
+P 2800 4850
+F 0 "R?" H 2850 4980 50 0000 C CNN
+F 1 "3.3k" H 2850 4800 50 0000 C CNN
+F 2 "" H 2850 4830 30 0000 C CNN
+F 3 "" V 2850 4900 30 0000 C CNN
+ 1 2800 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E903F
+P 2950 3750
+F 0 "R?" H 3000 3880 50 0000 C CNN
+F 1 "12k" H 3000 3700 50 0000 C CNN
+F 2 "" H 3000 3730 30 0000 C CNN
+F 3 "" V 3000 3800 30 0000 C CNN
+ 1 2950 3750
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E908F
+P 2950 4250
+F 0 "R?" H 3000 4380 50 0000 C CNN
+F 1 "12k" H 3000 4200 50 0000 C CNN
+F 2 "" H 3000 4230 30 0000 C CNN
+F 3 "" V 3000 4300 30 0000 C CNN
+ 1 2950 4250
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683E92CD
+P 2600 5600
+F 0 "Q?" H 2500 5650 50 0000 R CNN
+F 1 "eSim_NPN" H 2550 5400 50 0000 R CNN
+F 2 "" H 2800 5700 29 0000 C CNN
+F 3 "" H 2600 5600 60 0000 C CNN
+ 1 2600 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E946E
+P 2350 5250
+F 0 "R?" H 2400 5380 50 0000 C CNN
+F 1 "5.6k" H 2400 5200 50 0000 C CNN
+F 2 "" H 2400 5230 30 0000 C CNN
+F 3 "" V 2400 5300 30 0000 C CNN
+ 1 2350 5250
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683E9744
+P 3300 4150
+F 0 "R?" H 3350 4280 50 0000 C CNN
+F 1 "12k" H 3350 4100 50 0000 C CNN
+F 2 "" H 3350 4130 30 0000 C CNN
+F 3 "" V 3350 4200 30 0000 C CNN
+ 1 3300 4150
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683E979C
+P 3250 4800
+F 0 "Q?" H 3150 4850 50 0000 R CNN
+F 1 "eSim_NPN" H 3200 4950 50 0000 R CNN
+F 2 "" H 3450 4900 29 0000 C CNN
+F 3 "" H 3250 4800 60 0000 C CNN
+ 1 3250 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor C?
+U 1 1 683E9F5A
+P 3750 4450
+F 0 "C?" H 3775 4550 50 0000 L CNN
+F 1 "12p" H 3775 4350 50 0000 L CNN
+F 2 "" H 3788 4300 30 0000 C CNN
+F 3 "" H 3750 4450 60 0000 C CNN
+ 1 3750 4450
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EA32D
+P 4150 4050
+F 0 "R?" H 4200 4180 50 0000 C CNN
+F 1 "12k" H 4200 4000 50 0000 C CNN
+F 2 "" H 4200 4030 30 0000 C CNN
+F 3 "" V 4200 4100 30 0000 C CNN
+ 1 4150 4050
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683EA39C
+P 4100 4850
+F 0 "Q?" H 4000 4900 50 0000 R CNN
+F 1 "eSim_NPN" H 4050 5000 50 0000 R CNN
+F 2 "" H 4300 4950 29 0000 C CNN
+F 3 "" H 4100 4850 60 0000 C CNN
+ 1 4100 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EA79E
+P 4800 4050
+F 0 "R?" H 4850 4180 50 0000 C CNN
+F 1 "12k" H 4850 4000 50 0000 C CNN
+F 2 "" H 4850 4030 30 0000 C CNN
+F 3 "" V 4850 4100 30 0000 C CNN
+ 1 4800 4050
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EA821
+P 4450 4500
+F 0 "R?" H 4500 4630 50 0000 C CNN
+F 1 "12k" H 4500 4450 50 0000 C CNN
+F 2 "" H 4500 4480 30 0000 C CNN
+F 3 "" V 4500 4550 30 0000 C CNN
+ 1 4450 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683EAA10
+P 4750 5050
+F 0 "Q?" H 4650 5100 50 0000 R CNN
+F 1 "eSim_NPN" H 4700 5200 50 0000 R CNN
+F 2 "" H 4950 5150 29 0000 C CNN
+F 3 "" H 4750 5050 60 0000 C CNN
+ 1 4750 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EABAB
+P 4500 4700
+F 0 "R?" H 4550 4830 50 0000 C CNN
+F 1 "12k" H 4550 4650 50 0000 C CNN
+F 2 "" H 4550 4680 30 0000 C CNN
+F 3 "" V 4550 4750 30 0000 C CNN
+ 1 4500 4700
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EAEC8
+P 5100 4500
+F 0 "R?" H 5150 4630 50 0000 C CNN
+F 1 "12k" H 5150 4450 50 0000 C CNN
+F 2 "" H 5150 4480 30 0000 C CNN
+F 3 "" V 5150 4550 30 0000 C CNN
+ 1 5100 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor C?
+U 1 1 683EAF58
+P 5200 4250
+F 0 "C?" H 5225 4350 50 0000 L CNN
+F 1 "12p" H 5225 4150 50 0000 L CNN
+F 2 "" H 5238 4100 30 0000 C CNN
+F 3 "" H 5200 4250 60 0000 C CNN
+ 1 5200 4250
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 2050 4600 2050 5400
+Wire Wire Line
+ 2200 4800 2050 4800
+Connection ~ 2050 4800
+Wire Wire Line
+ 2350 5600 2400 5600
+Wire Wire Line
+ 2500 4800 2700 4800
+Wire Wire Line
+ 3000 3950 3000 4150
+Wire Wire Line
+ 2050 4200 2050 3500
+Wire Wire Line
+ 2050 3500 7300 3500
+Wire Wire Line
+ 3000 3500 3000 3650
+Wire Wire Line
+ 2700 4050 2700 5400
+Wire Wire Line
+ 2700 4050 3000 4050
+Connection ~ 3000 4050
+Wire Wire Line
+ 2400 5600 2400 5450
+Wire Wire Line
+ 2400 5150 2400 5100
+Wire Wire Line
+ 2400 5100 2700 5100
+Connection ~ 2700 5100
+Wire Wire Line
+ 3000 4800 3050 4800
+Wire Wire Line
+ 3350 3500 3350 4050
+Connection ~ 3000 3500
+Wire Wire Line
+ 3350 4350 3350 4600
+Wire Wire Line
+ 2050 5800 7300 5800
+Wire Wire Line
+ 3350 5800 3350 5000
+Connection ~ 2700 5800
+Wire Wire Line
+ 3000 4450 3000 4800
+Wire Wire Line
+ 3600 4450 3350 4450
+Connection ~ 3350 4450
+Wire Wire Line
+ 4200 3500 4200 3950
+Connection ~ 3350 3500
+Wire Wire Line
+ 4200 4250 4200 4650
+Wire Wire Line
+ 3900 4850 3900 4450
+Wire Wire Line
+ 4200 5800 4200 5050
+Connection ~ 3350 5800
+Wire Wire Line
+ 4850 3500 4850 3950
+Connection ~ 4200 3500
+Wire Wire Line
+ 3900 4450 4350 4450
+Wire Wire Line
+ 4550 4900 4550 5050
+Wire Wire Line
+ 4550 4600 4700 4600
+Wire Wire Line
+ 4700 4600 4700 4450
+Wire Wire Line
+ 4650 4450 5000 4450
+Connection ~ 4850 4450
+Connection ~ 4700 4450
+Wire Wire Line
+ 4850 5800 4850 5250
+Connection ~ 4200 5800
+Wire Wire Line
+ 4850 4250 4850 4850
+Wire Wire Line
+ 5050 4250 4300 4250
+Wire Wire Line
+ 4300 4250 4300 4350
+Wire Wire Line
+ 4300 4350 4200 4350
+Connection ~ 4200 4350
+Wire Wire Line
+ 5300 4450 5400 4450
+Wire Wire Line
+ 5400 4250 5400 4650
+Wire Wire Line
+ 5400 4250 5350 4250
+$Comp
+L resistor R?
+U 1 1 683EB199
+P 5500 3950
+F 0 "R?" H 5550 4080 50 0000 C CNN
+F 1 "12k" H 5550 3900 50 0000 C CNN
+F 2 "" H 5550 3930 30 0000 C CNN
+F 3 "" V 5550 4000 30 0000 C CNN
+ 1 5500 3950
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 5550 3500 5550 3850
+Connection ~ 4850 3500
+$Comp
+L eSim_NPN Q?
+U 1 1 683EB23D
+P 5450 5050
+F 0 "Q?" H 5350 5100 50 0000 R CNN
+F 1 "eSim_NPN" H 5400 5200 50 0000 R CNN
+F 2 "" H 5650 5150 29 0000 C CNN
+F 3 "" H 5450 5050 60 0000 C CNN
+ 1 5450 5050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5250 5050 5250 4650
+Wire Wire Line
+ 5250 4650 5400 4650
+Connection ~ 5400 4450
+Wire Wire Line
+ 5550 4150 5550 4850
+Wire Wire Line
+ 5550 5800 5550 5250
+Connection ~ 4850 5800
+$Comp
+L resistor R?
+U 1 1 683EC33E
+P 6100 3950
+F 0 "R?" H 6150 4080 50 0000 C CNN
+F 1 "12k" H 6150 3900 50 0000 C CNN
+F 2 "" H 6150 3930 30 0000 C CNN
+F 3 "" V 6150 4000 30 0000 C CNN
+ 1 6100 3950
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 6150 3500 6150 3850
+Connection ~ 5550 3500
+$Comp
+L eSim_NPN Q?
+U 1 1 683EC87C
+P 6050 5000
+F 0 "Q?" H 5950 5050 50 0000 R CNN
+F 1 "eSim_NPN" H 6000 5150 50 0000 R CNN
+F 2 "" H 6250 5100 29 0000 C CNN
+F 3 "" H 6050 5000 60 0000 C CNN
+ 1 6050 5000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6150 4150 6150 4800
+Wire Wire Line
+ 6150 5800 6150 5200
+Connection ~ 5550 5800
+$Comp
+L resistor R?
+U 1 1 683ED134
+P 5800 4550
+F 0 "R?" H 5850 4680 50 0000 C CNN
+F 1 "12k" H 5850 4500 50 0000 C CNN
+F 2 "" H 5850 4530 30 0000 C CNN
+F 3 "" V 5850 4600 30 0000 C CNN
+ 1 5800 4550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 5850 4750 5850 5000
+Wire Wire Line
+ 5850 4450 5850 4400
+Wire Wire Line
+ 5850 4400 6300 4400
+Connection ~ 6150 4400
+$Comp
+L capacitor C?
+U 1 1 683EDB50
+P 6450 4200
+F 0 "C?" H 6475 4300 50 0000 L CNN
+F 1 "23p" H 6050 4100 50 0000 L CNN
+F 2 "" H 6488 4050 30 0000 C CNN
+F 3 "" H 6450 4200 60 0000 C CNN
+ 1 6450 4200
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 6300 4200 5550 4200
+Connection ~ 5550 4200
+$Comp
+L resistor R?
+U 1 1 683EDC19
+P 6400 4450
+F 0 "R?" H 6450 4580 50 0000 C CNN
+F 1 "74k" H 6450 4400 50 0000 C CNN
+F 2 "" H 6450 4430 30 0000 C CNN
+F 3 "" V 6450 4500 30 0000 C CNN
+ 1 6400 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R?
+U 1 1 683EDD49
+P 6750 3950
+F 0 "R?" H 6800 4080 50 0000 C CNN
+F 1 "12k" H 6800 3900 50 0000 C CNN
+F 2 "" H 6800 3930 30 0000 C CNN
+F 3 "" V 6800 4000 30 0000 C CNN
+ 1 6750 3950
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q?
+U 1 1 683EE23F
+P 6700 5000
+F 0 "Q?" H 6600 5050 50 0000 R CNN
+F 1 "eSim_NPN" H 6650 5150 50 0000 R CNN
+F 2 "" H 6900 5100 29 0000 C CNN
+F 3 "" H 6700 5000 60 0000 C CNN
+ 1 6700 5000
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6800 4150 6800 4800
+Wire Wire Line
+ 6600 4200 6600 4600
+Wire Wire Line
+ 6500 5000 6500 4600
+Wire Wire Line
+ 6500 4600 6600 4600
+Connection ~ 6600 4400
+Wire Wire Line
+ 6800 5800 6800 5200
+Connection ~ 6150 5800
+Wire Wire Line
+ 6800 3500 6800 3850
+Connection ~ 6150 3500
+$Comp
+L eSim_NPN Q?
+U 1 1 683EF5C6
+P 7200 4400
+F 0 "Q?" H 7100 4450 50 0000 R CNN
+F 1 "eSim_NPN" H 7150 4550 50 0000 R CNN
+F 2 "" H 7400 4500 29 0000 C CNN
+F 3 "" H 7200 4400 60 0000 C CNN
+ 1 7200 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7000 4400 6800 4400
+Connection ~ 6800 4400
+Wire Wire Line
+ 7300 3500 7300 4200
+Connection ~ 6800 3500
+Wire Wire Line
+ 7300 5800 7300 4600
+Connection ~ 6800 5800
+$Comp
+L PORT U?
+U 1 1 683F01D4
+P 8000 4850
+F 0 "U?" H 8050 4950 30 0000 C CNN
+F 1 "PORT" H 8000 4850 30 0000 C CNN
+F 2 "" H 8000 4850 60 0000 C CNN
+F 3 "" H 8000 4850 60 0000 C CNN
+ 1 8000 4850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 2 1 683F022F
+P 8000 5150
+F 0 "U?" H 8050 5250 30 0000 C CNN
+F 1 "PORT" H 8000 5150 30 0000 C CNN
+F 2 "" H 8000 5150 60 0000 C CNN
+F 3 "" H 8000 5150 60 0000 C CNN
+ 2 8000 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U?
+U 3 1 683F0296
+P 7950 5400
+F 0 "U?" H 8000 5500 30 0000 C CNN
+F 1 "PORT" H 7950 5400 30 0000 C CNN
+F 2 "" H 7950 5400 60 0000 C CNN
+F 3 "" H 7950 5400 60 0000 C CNN
+ 3 7950 5400
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TA7642/TA7642.sub b/library/SubcircuitLibrary/TA7642/TA7642.sub
new file mode 100644
index 000000000..263c96295
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642.sub
@@ -0,0 +1,36 @@
+* Subcircuit TA7642
+.subckt TA7642 net-_q10-pad3_ net-_q1-pad2_ net-_q1-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\ta7642\ta7642.cir
+.include NPN.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_c1-pad2_ Q2N2222
+q2 net-_c1-pad2_ net-_q2-pad2_ net-_q10-pad3_ Q2N2222
+c1 net-_c1-pad1_ net-_c1-pad2_ 12p
+r2 net-_c1-pad1_ net-_q4-pad2_ 3.3k
+r3 net-_q1-pad1_ net-_q3-pad1_ 12k
+r4 net-_q3-pad1_ net-_q4-pad2_ 12k
+q3 net-_q3-pad1_ net-_q2-pad2_ net-_q10-pad3_ Q2N2222
+r1 net-_q3-pad1_ net-_q2-pad2_ 5.6k
+r5 net-_q1-pad1_ net-_c2-pad2_ 12k
+q4 net-_c2-pad2_ net-_q4-pad2_ net-_q10-pad3_ Q2N2222
+c2 net-_c2-pad1_ net-_c2-pad2_ 12p
+r6 net-_q1-pad1_ net-_c3-pad2_ 12k
+q5 net-_c3-pad2_ net-_c2-pad1_ net-_q10-pad3_ Q2N2222
+r9 net-_q1-pad1_ net-_q6-pad1_ 12k
+r7 net-_c2-pad1_ net-_q6-pad1_ 12k
+q6 net-_q6-pad1_ net-_q6-pad2_ net-_q10-pad3_ Q2N2222
+r8 net-_q6-pad1_ net-_q6-pad2_ 12k
+r10 net-_q6-pad1_ net-_c3-pad1_ 12k
+c3 net-_c3-pad1_ net-_c3-pad2_ 12p
+r11 net-_q1-pad1_ net-_c4-pad2_ 12k
+q7 net-_c4-pad2_ net-_c3-pad1_ net-_q10-pad3_ Q2N2222
+r13 net-_q1-pad1_ net-_q8-pad1_ 12k
+q8 net-_q8-pad1_ net-_q8-pad2_ net-_q10-pad3_ Q2N2222
+r12 net-_q8-pad1_ net-_q8-pad2_ 12k
+c4 net-_c4-pad1_ net-_c4-pad2_ 23p
+r14 net-_q8-pad1_ net-_c4-pad1_ 74k
+r15 net-_q1-pad1_ net-_q10-pad2_ 12k
+q9 net-_q10-pad2_ net-_c4-pad1_ net-_q10-pad3_ Q2N2222
+q10 net-_q1-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+* Control Statements
+
+.ends TA7642
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_Previous_Values.xml b/library/SubcircuitLibrary/TA7642/TA7642_Previous_Values.xml
new file mode 100644
index 000000000..b3cf203cf
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test-cache.lib b/library/SubcircuitLibrary/TA7642/TA7642_test-cache.lib
new file mode 100644
index 000000000..5cf84601c
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test-cache.lib
@@ -0,0 +1,116 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# TA7642
+#
+DEF TA7642 X 0 40 Y Y 1 F N
+F0 "X" 0 -400 60 H V C CNN
+F1 "TA7642" 0 300 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -200 150 200 -100 0 1 0 N
+X A 1 0 -300 200 U 50 50 1 1 I
+X B 2 -400 0 200 R 50 50 1 1 I
+X C 3 400 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_VCC
+#
+DEF eSim_VCC #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -150 50 H I C CNN
+F1 "eSim_VCC" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 0 75 25 0 1 0 N
+P 2 0 1 0 0 0 0 50 N
+X VCC 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.cir b/library/SubcircuitLibrary/TA7642/TA7642_test.cir
new file mode 100644
index 000000000..33a84c143
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.cir
@@ -0,0 +1,20 @@
+* C:\Users\pavithra\eSim-Workspace\TA7642_test\TA7642_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/03/25 13:07:35
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+C1 Net-_C1-Pad1_ in 0.01u
+R1 in GND 75
+C2 GND Vout 1u
+R2 Net-_C1-Pad1_ Vout 100k
+R3 Vout VCC 1.5k
+U1 Vout plot_v1
+v1 in GND sine
+U2 in plot_v1
+X1 GND Net-_C1-Pad1_ Vout TA7642
+R4 Vout GND 100k
+
+.end
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.cir.out b/library/SubcircuitLibrary/TA7642/TA7642_test.cir.out
new file mode 100644
index 000000000..be0de6951
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.cir.out
@@ -0,0 +1,38 @@
+* c:\users\pavithra\esim-workspace\ta7642_test\ta7642_test.cir
+
+.include TA7642.sub
+
+* Input AM Signal (reduced amplitude)
+v1 in 0 AM(0.05 0.04 1k 1Meg 0 0)
+r1 in gnd 75
+c1 net-_c1-pad1_ in 0.01u
+
+* Power Supply (Safe for TA7642)
+v2 vcc gnd DC 1.4
+
+* TA7642 Instance
+x1 gnd net-_c1-pad1_ vout TA7642
+
+* Output stage
+r2 net-_c1-pad1_ vout 100k
+r3 vout vcc 1.5k
+r4 vout gnd 100k
+c2 gnd vout 1u
+
+* Probes
+* u1 vout plot_v1
+* u2 in plot_v1
+
+* Transient Analysis
+.tran 0.1u 10m 0
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(vout)
+plot v(in)
+.endc
+
+.end
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.pro b/library/SubcircuitLibrary/TA7642/TA7642_test.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.proj b/library/SubcircuitLibrary/TA7642/TA7642_test.proj
new file mode 100644
index 000000000..15b792653
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.proj
@@ -0,0 +1 @@
+schematicFile TA7642_test.sch
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test.sch b/library/SubcircuitLibrary/TA7642/TA7642_test.sch
new file mode 100644
index 000000000..767bad85a
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test.sch
@@ -0,0 +1,253 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:TA7642_test-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L capacitor C1
+U 1 1 683D76B8
+P 4400 3900
+F 0 "C1" H 4425 4000 50 0000 L CNN
+F 1 "0.01u" H 4425 3800 50 0000 L CNN
+F 2 "" H 4438 3750 30 0000 C CNN
+F 3 "" H 4400 3900 60 0000 C CNN
+ 1 4400 3900
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R1
+U 1 1 683D76F0
+P 4100 4400
+F 0 "R1" H 4150 4530 50 0000 C CNN
+F 1 "75" H 4150 4350 50 0000 C CNN
+F 2 "" H 4150 4380 30 0000 C CNN
+F 3 "" V 4150 4450 30 0000 C CNN
+ 1 4100 4400
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor C2
+U 1 1 683D775A
+P 5800 4200
+F 0 "C2" H 5825 4300 50 0000 L CNN
+F 1 "1u" H 5825 4100 50 0000 L CNN
+F 2 "" H 5838 4050 30 0000 C CNN
+F 3 "" H 5800 4200 60 0000 C CNN
+ 1 5800 4200
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 683D77BE
+P 5350 3400
+F 0 "R2" H 5400 3530 50 0000 C CNN
+F 1 "100k" H 5400 3350 50 0000 C CNN
+F 2 "" H 5400 3380 30 0000 C CNN
+F 3 "" V 5400 3450 30 0000 C CNN
+ 1 5350 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 683D7822
+P 6100 3400
+F 0 "R3" H 6150 3530 50 0000 C CNN
+F 1 "1.5k" H 6150 3350 50 0000 C CNN
+F 2 "" H 6150 3380 30 0000 C CNN
+F 3 "" V 6150 3450 30 0000 C CNN
+ 1 6100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 683D78A0
+P 6000 4800
+F 0 "#PWR01" H 6000 4550 50 0001 C CNN
+F 1 "eSim_GND" H 6000 4650 50 0000 C CNN
+F 2 "" H 6000 4800 50 0001 C CNN
+F 3 "" H 6000 4800 50 0001 C CNN
+ 1 6000 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 683D78F9
+P 6100 4100
+F 0 "U1" H 6100 4600 60 0000 C CNN
+F 1 "plot_v1" H 6300 4450 60 0000 C CNN
+F 2 "" H 6100 4100 60 0000 C CNN
+F 3 "" H 6100 4100 60 0000 C CNN
+ 1 6100 4100
+ 1 0 0 -1
+$EndComp
+Text GLabel 6500 4050 2 60 Input ~ 0
+Vout
+$Comp
+L sine v1
+U 1 1 683D79C7
+P 3750 4350
+F 0 "v1" H 3550 4450 60 0000 C CNN
+F 1 "sine" H 3550 4300 60 0000 C CNN
+F 2 "R1" H 3450 4350 60 0000 C CNN
+F 3 "" H 3750 4350 60 0000 C CNN
+ 1 3750 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4550 3900 4800 3900
+Wire Wire Line
+ 4150 3900 4150 4300
+Wire Wire Line
+ 3750 3900 4250 3900
+Wire Wire Line
+ 5600 3900 6100 3900
+Wire Wire Line
+ 5800 3350 5800 4050
+Wire Wire Line
+ 4700 3900 4700 3350
+Wire Wire Line
+ 4700 3350 5250 3350
+Connection ~ 4700 3900
+Wire Wire Line
+ 5550 3350 6000 3350
+Connection ~ 5800 3900
+Connection ~ 5800 3350
+Wire Wire Line
+ 5950 3900 5950 4050
+Wire Wire Line
+ 5950 4050 6500 4050
+Connection ~ 5950 3900
+Connection ~ 4150 3900
+Wire Wire Line
+ 3750 4800 6000 4800
+Wire Wire Line
+ 4150 4800 4150 4600
+Wire Wire Line
+ 5200 4800 5200 4200
+Connection ~ 4150 4800
+Wire Wire Line
+ 5800 4800 5800 4350
+Connection ~ 5200 4800
+Connection ~ 5800 4800
+Text GLabel 3800 3800 0 60 Input ~ 0
+in
+$Comp
+L plot_v1 U2
+U 1 1 683DD3EC
+P 3950 3900
+F 0 "U2" H 3950 4400 60 0000 C CNN
+F 1 "plot_v1" H 4150 4250 60 0000 C CNN
+F 2 "" H 3950 3900 60 0000 C CNN
+F 3 "" H 3950 3900 60 0000 C CNN
+ 1 3950 3900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3950 3700 3950 3900
+Connection ~ 3950 3900
+Wire Wire Line
+ 3800 3800 3950 3800
+Connection ~ 3950 3800
+$Comp
+L eSim_VCC #PWR02
+U 1 1 683E8921
+P 6350 3250
+F 0 "#PWR02" H 6350 3100 50 0001 C CNN
+F 1 "eSim_VCC" H 6350 3400 50 0000 C CNN
+F 2 "" H 6350 3250 50 0001 C CNN
+F 3 "" H 6350 3250 50 0001 C CNN
+ 1 6350 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6350 3250 6350 3350
+Wire Wire Line
+ 6350 3350 6300 3350
+$Comp
+L TA7642 X1
+U 1 1 683E9609
+P 5200 3900
+F 0 "X1" H 5200 3500 60 0000 C CNN
+F 1 "TA7642" H 5200 4200 60 0000 C CNN
+F 2 "" H 5200 3900 60 0001 C CNN
+F 3 "" H 5200 3900 60 0001 C CNN
+ 1 5200 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R4
+U 1 1 683EA678
+P 6000 4350
+F 0 "R4" V 6050 4480 50 0000 C CNN
+F 1 "100k" H 6050 4300 50 0000 C CNN
+F 2 "" H 6050 4330 30 0000 C CNN
+F 3 "" V 6050 4400 30 0000 C CNN
+ 1 6000 4350
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 6050 4550 6050 4650
+Wire Wire Line
+ 6050 4650 5900 4650
+Wire Wire Line
+ 5900 4650 5900 4800
+Connection ~ 5900 4800
+Wire Wire Line
+ 6050 4250 6050 4100
+Wire Wire Line
+ 6050 4100 5900 4100
+Wire Wire Line
+ 5900 4100 5900 3900
+Connection ~ 5900 3900
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TA7642/TA7642_test_Previous_Values.xml b/library/SubcircuitLibrary/TA7642/TA7642_test_Previous_Values.xml
new file mode 100644
index 000000000..72957726d
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/TA7642_test_Previous_Values.xml
@@ -0,0 +1 @@
+sine0300u1m0dc1.4C:\FOSSEE\eSim\library\SubcircuitLibrary\TA7642truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.110msusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TA7642/analysis b/library/SubcircuitLibrary/TA7642/analysis
new file mode 100644
index 000000000..6dcba7452
--- /dev/null
+++ b/library/SubcircuitLibrary/TA7642/analysis
@@ -0,0 +1 @@
+.tran 0.1e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP-cache.lib
new file mode 100644
index 000000000..14a754158
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP-cache.lib
@@ -0,0 +1,246 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# Y1
+#
+DEF Y1 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y1" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 150 350 -150 0 1 0 N
+X Vdd 1 -500 100 200 R 50 50 1 1 I
+X A 2 -500 0 200 R 50 50 1 1 I
+X B_bar 3 -500 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X C_bar 5 550 100 200 L 50 50 1 1 I
+X D_bar 6 550 0 200 L 50 50 1 1 I
+X Y1 7 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Y2
+#
+DEF Y2 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y2" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 150 350 -150 0 1 0 N
+X Vdd 1 -500 100 200 R 50 50 1 1 I
+X A_bar 2 -500 0 200 R 50 50 1 1 I
+X B 3 -500 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X C_bar 5 550 100 200 L 50 50 1 1 I
+X D_bar 6 550 0 200 L 50 50 1 1 I
+X Y2 7 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Y3
+#
+DEF Y3 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y3" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 150 350 -150 0 1 0 N
+X Vdd 1 -500 100 200 R 50 50 1 1 I
+X A 2 -500 0 200 R 50 50 1 1 I
+X B 3 -500 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X C_bar 5 550 100 200 L 50 50 1 1 I
+X D_bar 6 550 0 200 L 50 50 1 1 I
+X Y3 7 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Y4
+#
+DEF Y4 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y4" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X Vdd 1 -550 100 200 R 50 50 1 1 I
+X A_bar 2 -550 0 200 R 50 50 1 1 I
+X B_bar 3 -550 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X C 5 550 100 200 L 50 50 1 1 I
+X D_bar 6 550 0 200 L 50 50 1 1 I
+X Y4 7 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Y5
+#
+DEF Y5 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y5" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X Vdd 1 -550 100 200 R 50 50 1 1 I
+X A 2 -550 0 200 R 50 50 1 1 I
+X B_bar 3 -550 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X C 5 550 100 200 L 50 50 1 1 I
+X D_bar 6 550 0 200 L 50 50 1 1 I
+X Y5 7 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Y6
+#
+DEF Y6 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y6" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X Vdd 1 -550 100 200 R 50 50 1 1 I
+X A_bar 2 -550 0 200 R 50 50 1 1 I
+X B 3 -550 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X C 5 550 100 200 L 50 50 1 1 I
+X D_bar 6 550 0 200 L 50 50 1 1 I
+X Y6 7 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Y7
+#
+DEF Y7 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y7" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X Vdd 1 -550 100 200 R 50 50 1 1 I
+X A 2 -550 0 200 R 50 50 1 1 I
+X B 3 -550 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X C 5 550 100 200 L 50 50 1 1 I
+X D_bar 6 550 0 200 L 50 50 1 1 I
+X Y7 7 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Y8
+#
+DEF Y8 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y8" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 400 -150 0 1 0 N
+X Vdd 1 -550 100 200 R 50 50 1 1 I
+X A_bar 2 -550 0 200 R 50 50 1 1 I
+X B_bar 3 -550 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X C_bar 5 600 100 200 L 50 50 1 1 I
+X D 6 600 0 200 L 50 50 1 1 I
+X Y8 7 600 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Y9
+#
+DEF Y9 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y9" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X Vdd 1 -550 100 200 R 50 50 1 1 I
+X A 2 -550 0 200 R 50 50 1 1 I
+X B_bar 3 -550 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -350 200 U 50 50 1 1 I
+X C_bar 5 550 100 200 L 50 50 1 1 I
+X D 6 550 0 200 L 50 50 1 1 I
+X Y9 7 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.bak b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.bak
new file mode 100644
index 000000000..a1d188a96
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.bak
@@ -0,0 +1,669 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:TC74HC4028AP-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 6869436A
+P 2650 1250
+F 0 "X1" H 2650 1350 60 0000 C CNN
+F 1 "Y0" H 2600 1050 60 0000 C CNN
+F 2 "" H 2650 1250 60 0001 C CNN
+F 3 "" H 2650 1250 60 0001 C CNN
+ 1 2650 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y1 X4
+U 1 1 68694446
+P 4100 1250
+F 0 "X4" H 4100 1350 60 0000 C CNN
+F 1 "Y1" H 4050 1050 60 0000 C CNN
+F 2 "" H 4100 1250 60 0001 C CNN
+F 3 "" H 4100 1250 60 0001 C CNN
+ 1 4100 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y2 X6
+U 1 1 68694477
+P 5550 1250
+F 0 "X6" H 5550 1350 60 0000 C CNN
+F 1 "Y2" H 5500 1050 60 0000 C CNN
+F 2 "" H 5550 1250 60 0001 C CNN
+F 3 "" H 5550 1250 60 0001 C CNN
+ 1 5550 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y3 X9
+U 1 1 686944AA
+P 7000 1250
+F 0 "X9" H 7000 1350 60 0000 C CNN
+F 1 "Y3" H 6950 1050 60 0000 C CNN
+F 2 "" H 7000 1250 60 0001 C CNN
+F 3 "" H 7000 1250 60 0001 C CNN
+ 1 7000 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y4 X2
+U 1 1 686944E9
+P 2650 2100
+F 0 "X2" H 2650 2200 60 0000 C CNN
+F 1 "Y4" H 2600 1900 60 0000 C CNN
+F 2 "" H 2650 2100 60 0001 C CNN
+F 3 "" H 2650 2100 60 0001 C CNN
+ 1 2650 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y5 X5
+U 1 1 6869451A
+P 4150 2100
+F 0 "X5" H 4150 2200 60 0000 C CNN
+F 1 "Y5" H 4100 1900 60 0000 C CNN
+F 2 "" H 4150 2100 60 0001 C CNN
+F 3 "" H 4150 2100 60 0001 C CNN
+ 1 4150 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y6 X7
+U 1 1 6869454D
+P 5600 2100
+F 0 "X7" H 5600 2200 60 0000 C CNN
+F 1 "Y6" H 5550 1900 60 0000 C CNN
+F 2 "" H 5600 2100 60 0001 C CNN
+F 3 "" H 5600 2100 60 0001 C CNN
+ 1 5600 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y7 X10
+U 1 1 6869457C
+P 7050 2100
+F 0 "X10" H 7050 2200 60 0000 C CNN
+F 1 "Y7" H 7000 1900 60 0000 C CNN
+F 2 "" H 7050 2100 60 0001 C CNN
+F 3 "" H 7050 2100 60 0001 C CNN
+ 1 7050 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y9 X8
+U 1 1 686945F2
+P 6250 3000
+F 0 "X8" H 6250 3100 60 0000 C CNN
+F 1 "Y9" H 6200 2800 60 0000 C CNN
+F 2 "" H 6250 3000 60 0001 C CNN
+F 3 "" H 6250 3000 60 0001 C CNN
+ 1 6250 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 6869470D
+P 10350 1750
+F 0 "scmode1" H 10350 1900 98 0000 C CNB
+F 1 "SKY130mode" H 10350 1650 118 0000 C CNB
+F 2 "" H 10350 1900 60 0001 C CNN
+F 3 "" H 10350 1900 60 0001 C CNN
+ 1 10350 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68697E56
+P 1550 1150
+F 0 "U1" H 1600 1250 30 0000 C CNN
+F 1 "PORT" H 1550 1150 30 0000 C CNN
+F 2 "" H 1550 1150 60 0000 C CNN
+F 3 "" H 1550 1150 60 0000 C CNN
+ 1 1550 1150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68697EC9
+P 3500 3700
+F 0 "U1" H 3550 3800 30 0000 C CNN
+F 1 "PORT" H 3500 3700 30 0000 C CNN
+F 2 "" H 3500 3700 60 0000 C CNN
+F 3 "" H 3500 3700 60 0000 C CNN
+ 8 3500 3700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6869826A
+P 1600 2100
+F 0 "U1" H 1650 2200 30 0000 C CNN
+F 1 "PORT" H 1600 2100 30 0000 C CNN
+F 2 "" H 1600 2100 60 0000 C CNN
+F 3 "" H 1600 2100 60 0000 C CNN
+ 2 1600 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68698527
+P 1700 1800
+F 0 "U1" H 1750 1900 30 0000 C CNN
+F 1 "PORT" H 1700 1800 30 0000 C CNN
+F 2 "" H 1700 1800 60 0000 C CNN
+F 3 "" H 1700 1800 60 0000 C CNN
+ 3 1700 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68698765
+P 3200 1500
+F 0 "U1" H 3250 1600 30 0000 C CNN
+F 1 "PORT" H 3200 1500 30 0000 C CNN
+F 2 "" H 3200 1500 60 0000 C CNN
+F 3 "" H 3200 1500 60 0000 C CNN
+ 6 3200 1500
+ 1 0 0 -1
+$EndComp
+Text Label 3450 1500 0 60 ~ 0
+A
+Text Label 1950 1800 0 60 ~ 0
+B_bar
+Text Label 1850 2100 0 60 ~ 0
+A_bar
+Text Label 1800 1150 0 60 ~ 0
+Vd
+Text Label 3500 3450 0 60 ~ 0
+Gnd
+$Comp
+L PORT U1
+U 14 1 68698C0E
+P 5250 1600
+F 0 "U1" H 5300 1700 30 0000 C CNN
+F 1 "PORT" H 5250 1600 30 0000 C CNN
+F 2 "" H 5250 1600 60 0000 C CNN
+F 3 "" H 5250 1600 60 0000 C CNN
+ 14 5250 1600
+ -1 0 0 1
+$EndComp
+Text Label 5000 1600 0 60 ~ 0
+B
+$Comp
+L PORT U1
+U 12 1 68699104
+P 4550 950
+F 0 "U1" H 4600 1050 30 0000 C CNN
+F 1 "PORT" H 4550 950 30 0000 C CNN
+F 2 "" H 4550 950 60 0000 C CNN
+F 3 "" H 4550 950 60 0000 C CNN
+ 12 4550 950
+ 1 0 0 -1
+$EndComp
+Text Label 4800 1050 0 60 ~ 0
+C_bar
+$Comp
+L PORT U1
+U 11 1 686995D3
+P 4450 1800
+F 0 "U1" H 4500 1900 30 0000 C CNN
+F 1 "PORT" H 4450 1800 30 0000 C CNN
+F 2 "" H 4450 1800 60 0000 C CNN
+F 3 "" H 4450 1800 60 0000 C CNN
+ 11 4450 1800
+ 1 0 0 -1
+$EndComp
+Text Label 4700 1900 0 60 ~ 0
+C
+$Comp
+L PORT U1
+U 4 1 6869A09B
+P 3000 1600
+F 0 "U1" H 3050 1700 30 0000 C CNN
+F 1 "PORT" H 3000 1600 30 0000 C CNN
+F 2 "" H 3000 1600 60 0000 C CNN
+F 3 "" H 3000 1600 60 0000 C CNN
+ 4 3000 1600
+ 1 0 0 -1
+$EndComp
+Text Label 3250 1600 0 60 ~ 0
+D_bar
+$Comp
+L PORT U1
+U 18 1 6869A296
+P 7250 3000
+F 0 "U1" H 7300 3100 30 0000 C CNN
+F 1 "PORT" H 7250 3000 30 0000 C CNN
+F 2 "" H 7250 3000 60 0000 C CNN
+F 3 "" H 7250 3000 60 0000 C CNN
+ 18 7250 3000
+ -1 0 0 1
+$EndComp
+Text Label 6900 3000 0 60 ~ 0
+D
+$Comp
+L PORT U1
+U 5 1 6869A547
+P 3100 950
+F 0 "U1" H 3150 1050 30 0000 C CNN
+F 1 "PORT" H 3100 950 30 0000 C CNN
+F 2 "" H 3100 950 60 0000 C CNN
+F 3 "" H 3100 950 60 0000 C CNN
+ 5 3100 950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6869A7EA
+P 4150 950
+F 0 "U1" H 4200 1050 30 0000 C CNN
+F 1 "PORT" H 4150 950 30 0000 C CNN
+F 2 "" H 4150 950 60 0000 C CNN
+F 3 "" H 4150 950 60 0000 C CNN
+ 10 4150 950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2100 1150 1800 1150
+Wire Wire Line
+ 1800 800 1800 2000
+Wire Wire Line
+ 1800 800 6500 800
+Wire Wire Line
+ 6500 800 6500 1150
+Wire Wire Line
+ 1800 2000 2100 2000
+Connection ~ 1800 1150
+Wire Wire Line
+ 3600 1150 3500 1150
+Wire Wire Line
+ 3500 800 3500 2700
+Connection ~ 3500 800
+Wire Wire Line
+ 3500 2000 3600 2000
+Connection ~ 3500 1150
+Wire Wire Line
+ 5050 1150 4950 1150
+Wire Wire Line
+ 4950 800 4950 2000
+Connection ~ 4950 800
+Wire Wire Line
+ 4950 2000 5050 2000
+Connection ~ 4950 1150
+Wire Wire Line
+ 6500 2000 6400 2000
+Wire Wire Line
+ 6400 2000 6400 800
+Connection ~ 6400 800
+Wire Wire Line
+ 2950 2900 2950 2700
+Wire Wire Line
+ 2950 2700 5700 2700
+Connection ~ 3500 2000
+Wire Wire Line
+ 2650 1600 2650 1700
+Wire Wire Line
+ 2650 1700 7100 1700
+Wire Wire Line
+ 7100 1700 7100 2550
+Wire Wire Line
+ 7100 2550 2550 2550
+Wire Wire Line
+ 2550 2550 2550 3450
+Wire Wire Line
+ 2550 3450 6250 3450
+Wire Wire Line
+ 6250 3450 6250 3350
+Wire Wire Line
+ 3500 3350 3500 3450
+Connection ~ 3500 3450
+Wire Wire Line
+ 2650 2450 2650 2550
+Connection ~ 2650 2550
+Wire Wire Line
+ 4150 2450 4150 2550
+Connection ~ 4150 2550
+Wire Wire Line
+ 5600 2450 5600 2550
+Connection ~ 5600 2550
+Wire Wire Line
+ 7050 2450 7050 2550
+Connection ~ 7050 2550
+Wire Wire Line
+ 7000 1600 7000 1700
+Connection ~ 7000 1700
+Wire Wire Line
+ 5550 1600 5550 1700
+Connection ~ 5550 1700
+Wire Wire Line
+ 4100 1600 4100 1700
+Connection ~ 4100 1700
+Wire Wire Line
+ 5700 2700 5700 2900
+Connection ~ 3500 2700
+Wire Wire Line
+ 2100 1250 1850 1250
+Wire Wire Line
+ 1850 1250 1850 3000
+Wire Wire Line
+ 1850 2100 2100 2100
+Wire Wire Line
+ 5050 1250 4900 1250
+Wire Wire Line
+ 4900 1250 4900 2100
+Wire Wire Line
+ 4900 2100 5050 2100
+Wire Wire Line
+ 4900 1750 1850 1750
+Connection ~ 1850 1750
+Connection ~ 4900 1750
+Wire Wire Line
+ 1850 3000 2950 3000
+Connection ~ 1850 2100
+Wire Wire Line
+ 2100 1350 1950 1350
+Wire Wire Line
+ 1950 1350 1950 3200
+Wire Wire Line
+ 1950 2200 2100 2200
+Wire Wire Line
+ 3600 1350 3550 1350
+Wire Wire Line
+ 3550 1350 3550 2200
+Wire Wire Line
+ 3550 2200 3600 2200
+Wire Wire Line
+ 1950 1800 3550 1800
+Connection ~ 3550 1800
+Connection ~ 1950 1800
+Wire Wire Line
+ 5700 3100 5700 3200
+Wire Wire Line
+ 5700 3200 1950 3200
+Connection ~ 1950 2200
+Wire Wire Line
+ 2950 3100 2950 3200
+Connection ~ 2950 3200
+Wire Wire Line
+ 3600 1250 3450 1250
+Wire Wire Line
+ 3450 1250 3450 2100
+Wire Wire Line
+ 3450 2100 3600 2100
+Wire Wire Line
+ 6500 1250 6450 1250
+Wire Wire Line
+ 6450 1250 6450 2100
+Wire Wire Line
+ 6450 2100 6500 2100
+Wire Wire Line
+ 3450 1500 6450 1500
+Connection ~ 6450 1500
+Connection ~ 3450 1500
+Wire Wire Line
+ 5700 3000 4850 3000
+Wire Wire Line
+ 4850 3000 4850 1500
+Connection ~ 4850 1500
+Wire Wire Line
+ 5050 1350 5000 1350
+Wire Wire Line
+ 5000 1350 5000 2200
+Wire Wire Line
+ 5000 2200 5050 2200
+Wire Wire Line
+ 6500 1350 6350 1350
+Wire Wire Line
+ 6350 1350 6350 2200
+Wire Wire Line
+ 6350 2200 6500 2200
+Wire Wire Line
+ 6350 1600 5000 1600
+Connection ~ 5000 1600
+Connection ~ 6350 1600
+Wire Wire Line
+ 3200 1150 3200 1050
+Wire Wire Line
+ 3200 1050 7550 1050
+Wire Wire Line
+ 7550 1050 7550 1150
+Wire Wire Line
+ 4100 2900 4100 2800
+Wire Wire Line
+ 4100 2800 6800 2800
+Wire Wire Line
+ 6800 2800 6800 2900
+Wire Wire Line
+ 4800 950 4800 2800
+Connection ~ 4800 2800
+Connection ~ 4800 1050
+Wire Wire Line
+ 4650 1150 4650 1050
+Connection ~ 4650 1050
+Wire Wire Line
+ 6100 1150 6100 1050
+Connection ~ 6100 1050
+Wire Wire Line
+ 3200 2000 3200 1900
+Wire Wire Line
+ 3200 1900 7600 1900
+Wire Wire Line
+ 7600 1900 7600 2000
+Wire Wire Line
+ 6150 2000 6150 1900
+Connection ~ 6150 1900
+Wire Wire Line
+ 4700 1800 4700 2000
+Connection ~ 4700 1900
+Wire Wire Line
+ 3200 1250 3250 1250
+Wire Wire Line
+ 3250 1250 3250 2100
+Wire Wire Line
+ 3250 2100 3200 2100
+Wire Wire Line
+ 4650 1250 4750 1250
+Wire Wire Line
+ 4750 1250 4750 2100
+Wire Wire Line
+ 4750 2100 4700 2100
+Wire Wire Line
+ 6100 1250 6250 1250
+Wire Wire Line
+ 6250 1250 6250 2100
+Wire Wire Line
+ 6250 2100 6150 2100
+Wire Wire Line
+ 7550 1250 7650 1250
+Wire Wire Line
+ 7650 1250 7650 2100
+Wire Wire Line
+ 7650 2100 7600 2100
+Wire Wire Line
+ 3250 1600 4600 1600
+Wire Wire Line
+ 4600 1600 4600 1450
+Wire Wire Line
+ 4600 1450 7650 1450
+Connection ~ 7650 1450
+Connection ~ 3250 1600
+Connection ~ 6250 1450
+Connection ~ 4750 1450
+Wire Wire Line
+ 4100 3000 4200 3000
+Wire Wire Line
+ 4200 3000 4200 2650
+Wire Wire Line
+ 4200 2650 6900 2650
+Wire Wire Line
+ 6900 2650 6900 3000
+Wire Wire Line
+ 6800 3000 7000 3000
+Connection ~ 6900 3000
+Wire Wire Line
+ 3350 950 3350 1350
+Wire Wire Line
+ 3350 1350 3200 1350
+Wire Wire Line
+ 4400 950 4700 950
+Wire Wire Line
+ 4700 950 4700 1350
+Wire Wire Line
+ 4700 1350 4650 1350
+$Comp
+L PORT U1
+U 15 1 6869A9FB
+P 5950 950
+F 0 "U1" H 6000 1050 30 0000 C CNN
+F 1 "PORT" H 5950 950 30 0000 C CNN
+F 2 "" H 5950 950 60 0000 C CNN
+F 3 "" H 5950 950 60 0000 C CNN
+ 15 5950 950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6200 950 6200 1350
+Wire Wire Line
+ 6200 1350 6100 1350
+$Comp
+L PORT U1
+U 19 1 6869AC25
+P 7800 1350
+F 0 "U1" H 7850 1450 30 0000 C CNN
+F 1 "PORT" H 7800 1350 30 0000 C CNN
+F 2 "" H 7800 1350 60 0000 C CNN
+F 3 "" H 7800 1350 60 0000 C CNN
+ 19 7800 1350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 20 1 6869ACEC
+P 7850 2200
+F 0 "U1" H 7900 2300 30 0000 C CNN
+F 1 "PORT" H 7850 2200 30 0000 C CNN
+F 2 "" H 7850 2200 60 0000 C CNN
+F 3 "" H 7850 2200 60 0000 C CNN
+ 20 7850 2200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 6869ADC5
+P 6150 2450
+F 0 "U1" H 6200 2550 30 0000 C CNN
+F 1 "PORT" H 6150 2450 30 0000 C CNN
+F 2 "" H 6150 2450 60 0000 C CNN
+F 3 "" H 6150 2450 60 0000 C CNN
+ 16 6150 2450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6869AF77
+P 4700 2450
+F 0 "U1" H 4750 2550 30 0000 C CNN
+F 1 "PORT" H 4700 2450 30 0000 C CNN
+F 2 "" H 4700 2450 60 0000 C CNN
+F 3 "" H 4700 2450 60 0000 C CNN
+ 13 4700 2450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6869B03E
+P 3200 2450
+F 0 "U1" H 3250 2550 30 0000 C CNN
+F 1 "PORT" H 3200 2450 30 0000 C CNN
+F 2 "" H 3200 2450 60 0000 C CNN
+F 3 "" H 3200 2450 60 0000 C CNN
+ 7 3200 2450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6869B11E
+P 4100 3350
+F 0 "U1" H 4150 3450 30 0000 C CNN
+F 1 "PORT" H 4100 3350 30 0000 C CNN
+F 2 "" H 4100 3350 60 0000 C CNN
+F 3 "" H 4100 3350 60 0000 C CNN
+ 9 4100 3350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 17 1 6869B205
+P 6800 3350
+F 0 "U1" H 6850 3450 30 0000 C CNN
+F 1 "PORT" H 6800 3350 30 0000 C CNN
+F 2 "" H 6800 3350 60 0000 C CNN
+F 3 "" H 6800 3350 60 0000 C CNN
+ 17 6800 3350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L Y8 X3
+U 1 1 68695022
+P 3500 3000
+F 0 "X3" H 3500 3100 60 0000 C CNN
+F 1 "Y8" H 3450 2800 60 0000 C CNN
+F 2 "" H 3500 3000 60 0001 C CNN
+F 3 "" H 3500 3000 60 0001 C CNN
+ 1 3500 3000
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.cir b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.cir
new file mode 100644
index 000000000..b2dd5c478
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.cir
@@ -0,0 +1,22 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 21:40:54 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 /A_bar /B_bar /Gnd /Vd Net-_U1-Pad5_ /C_bar /D_bar Y0
+X4 /Vd /A /B_bar /Gnd /C_bar /D_bar Net-_U1-Pad10_ Y1
+X6 /Vd /A_bar /B /Gnd /C_bar /D_bar Net-_U1-Pad15_ Y2
+X9 /Vd /A /B /Gnd /C_bar /D_bar Net-_U1-Pad19_ Y3
+X2 /Vd /A_bar /B_bar /Gnd /C /D_bar Net-_U1-Pad7_ Y4
+X5 /Vd /A /B_bar /Gnd /C /D_bar Net-_U1-Pad13_ Y5
+X7 /Vd /A_bar /B /Gnd /C /D_bar Net-_U1-Pad16_ Y6
+X10 /Vd /A /B /Gnd /C /D_bar Net-_U1-Pad20_ Y7
+X8 /Vd /A /B_bar /Gnd /C_bar /D Net-_U1-Pad17_ Y9
+scmode1 SKY130mode
+U1 /Vd /A_bar /B_bar /D_bar Net-_U1-Pad5_ /A Net-_U1-Pad7_ /Gnd Net-_U1-Pad9_ Net-_U1-Pad10_ /C /C_bar Net-_U1-Pad13_ /B Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ /D Net-_U1-Pad19_ Net-_U1-Pad20_ PORT
+X3 /Vd /A_bar /B_bar /Gnd /C_bar /D Net-_U1-Pad9_ Y8
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.cir.out
new file mode 100644
index 000000000..0fcc3f4a9
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.cir.out
@@ -0,0 +1,35 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tc74hc4028ap/tc74hc4028ap.cir
+
+.include Y5.sub
+.include Y1.sub
+.include Y2.sub
+.include Y8.sub
+.include Y4.sub
+.include Y9.sub
+.include Y7.sub
+.include Y3.sub
+.include Y6.sub
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 /a_bar /b_bar /gnd /vd net-_u1-pad5_ /c_bar /d_bar Y0
+x4 /vd /a /b_bar /gnd /c_bar /d_bar net-_u1-pad10_ Y1
+x6 /vd /a_bar /b /gnd /c_bar /d_bar net-_u1-pad15_ Y2
+x9 /vd /a /b /gnd /c_bar /d_bar net-_u1-pad19_ Y3
+x2 /vd /a_bar /b_bar /gnd /c /d_bar net-_u1-pad7_ Y4
+x5 /vd /a /b_bar /gnd /c /d_bar net-_u1-pad13_ Y5
+x7 /vd /a_bar /b /gnd /c /d_bar net-_u1-pad16_ Y6
+x10 /vd /a /b /gnd /c /d_bar net-_u1-pad20_ Y7
+x8 /vd /a /b_bar /gnd /c_bar /d net-_u1-pad17_ Y9
+* s c m o d e
+* u1 /vd /a_bar /b_bar /d_bar net-_u1-pad5_ /a net-_u1-pad7_ /gnd net-_u1-pad9_ net-_u1-pad10_ /c /c_bar net-_u1-pad13_ /b net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ /d net-_u1-pad19_ net-_u1-pad20_ port
+x3 /vd /a_bar /b_bar /gnd /c_bar /d net-_u1-pad9_ Y8
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.pro b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.sch b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.sch
new file mode 100644
index 000000000..7fbc2d5c9
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.sch
@@ -0,0 +1,669 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:TC74HC4028AP-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 6869436A
+P 2650 1250
+F 0 "X1" H 2650 1350 60 0000 C CNN
+F 1 "Y0" H 2600 1050 60 0000 C CNN
+F 2 "" H 2650 1250 60 0001 C CNN
+F 3 "" H 2650 1250 60 0001 C CNN
+ 1 2650 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y1 X4
+U 1 1 68694446
+P 4100 1250
+F 0 "X4" H 4100 1350 60 0000 C CNN
+F 1 "Y1" H 4050 1050 60 0000 C CNN
+F 2 "" H 4100 1250 60 0001 C CNN
+F 3 "" H 4100 1250 60 0001 C CNN
+ 1 4100 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y2 X6
+U 1 1 68694477
+P 5550 1250
+F 0 "X6" H 5550 1350 60 0000 C CNN
+F 1 "Y2" H 5500 1050 60 0000 C CNN
+F 2 "" H 5550 1250 60 0001 C CNN
+F 3 "" H 5550 1250 60 0001 C CNN
+ 1 5550 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y3 X9
+U 1 1 686944AA
+P 7000 1250
+F 0 "X9" H 7000 1350 60 0000 C CNN
+F 1 "Y3" H 6950 1050 60 0000 C CNN
+F 2 "" H 7000 1250 60 0001 C CNN
+F 3 "" H 7000 1250 60 0001 C CNN
+ 1 7000 1250
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y4 X2
+U 1 1 686944E9
+P 2650 2100
+F 0 "X2" H 2650 2200 60 0000 C CNN
+F 1 "Y4" H 2600 1900 60 0000 C CNN
+F 2 "" H 2650 2100 60 0001 C CNN
+F 3 "" H 2650 2100 60 0001 C CNN
+ 1 2650 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y5 X5
+U 1 1 6869451A
+P 4150 2100
+F 0 "X5" H 4150 2200 60 0000 C CNN
+F 1 "Y5" H 4100 1900 60 0000 C CNN
+F 2 "" H 4150 2100 60 0001 C CNN
+F 3 "" H 4150 2100 60 0001 C CNN
+ 1 4150 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y6 X7
+U 1 1 6869454D
+P 5600 2100
+F 0 "X7" H 5600 2200 60 0000 C CNN
+F 1 "Y6" H 5550 1900 60 0000 C CNN
+F 2 "" H 5600 2100 60 0001 C CNN
+F 3 "" H 5600 2100 60 0001 C CNN
+ 1 5600 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y7 X10
+U 1 1 6869457C
+P 7050 2100
+F 0 "X10" H 7050 2200 60 0000 C CNN
+F 1 "Y7" H 7000 1900 60 0000 C CNN
+F 2 "" H 7050 2100 60 0001 C CNN
+F 3 "" H 7050 2100 60 0001 C CNN
+ 1 7050 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Y9 X8
+U 1 1 686945F2
+P 6250 3000
+F 0 "X8" H 6250 3100 60 0000 C CNN
+F 1 "Y9" H 6200 2800 60 0000 C CNN
+F 2 "" H 6250 3000 60 0001 C CNN
+F 3 "" H 6250 3000 60 0001 C CNN
+ 1 6250 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 6869470D
+P 8050 2750
+F 0 "scmode1" H 8050 2900 98 0000 C CNB
+F 1 "SKY130mode" H 8050 2650 118 0000 C CNB
+F 2 "" H 8050 2900 60 0001 C CNN
+F 3 "" H 8050 2900 60 0001 C CNN
+ 1 8050 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68697E56
+P 1550 1150
+F 0 "U1" H 1600 1250 30 0000 C CNN
+F 1 "PORT" H 1550 1150 30 0000 C CNN
+F 2 "" H 1550 1150 60 0000 C CNN
+F 3 "" H 1550 1150 60 0000 C CNN
+ 1 1550 1150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68697EC9
+P 3500 3700
+F 0 "U1" H 3550 3800 30 0000 C CNN
+F 1 "PORT" H 3500 3700 30 0000 C CNN
+F 2 "" H 3500 3700 60 0000 C CNN
+F 3 "" H 3500 3700 60 0000 C CNN
+ 8 3500 3700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6869826A
+P 1600 2100
+F 0 "U1" H 1650 2200 30 0000 C CNN
+F 1 "PORT" H 1600 2100 30 0000 C CNN
+F 2 "" H 1600 2100 60 0000 C CNN
+F 3 "" H 1600 2100 60 0000 C CNN
+ 2 1600 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68698527
+P 1700 1800
+F 0 "U1" H 1750 1900 30 0000 C CNN
+F 1 "PORT" H 1700 1800 30 0000 C CNN
+F 2 "" H 1700 1800 60 0000 C CNN
+F 3 "" H 1700 1800 60 0000 C CNN
+ 3 1700 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68698765
+P 3200 1500
+F 0 "U1" H 3250 1600 30 0000 C CNN
+F 1 "PORT" H 3200 1500 30 0000 C CNN
+F 2 "" H 3200 1500 60 0000 C CNN
+F 3 "" H 3200 1500 60 0000 C CNN
+ 6 3200 1500
+ 1 0 0 -1
+$EndComp
+Text Label 3450 1500 0 60 ~ 0
+A
+Text Label 1950 1800 0 60 ~ 0
+B_bar
+Text Label 1850 2100 0 60 ~ 0
+A_bar
+Text Label 1800 1150 0 60 ~ 0
+Vd
+Text Label 3500 3450 0 60 ~ 0
+Gnd
+$Comp
+L PORT U1
+U 14 1 68698C0E
+P 5250 1600
+F 0 "U1" H 5300 1700 30 0000 C CNN
+F 1 "PORT" H 5250 1600 30 0000 C CNN
+F 2 "" H 5250 1600 60 0000 C CNN
+F 3 "" H 5250 1600 60 0000 C CNN
+ 14 5250 1600
+ -1 0 0 1
+$EndComp
+Text Label 5000 1600 0 60 ~ 0
+B
+$Comp
+L PORT U1
+U 12 1 68699104
+P 4550 950
+F 0 "U1" H 4600 1050 30 0000 C CNN
+F 1 "PORT" H 4550 950 30 0000 C CNN
+F 2 "" H 4550 950 60 0000 C CNN
+F 3 "" H 4550 950 60 0000 C CNN
+ 12 4550 950
+ 1 0 0 -1
+$EndComp
+Text Label 4800 1050 0 60 ~ 0
+C_bar
+$Comp
+L PORT U1
+U 11 1 686995D3
+P 4450 1800
+F 0 "U1" H 4500 1900 30 0000 C CNN
+F 1 "PORT" H 4450 1800 30 0000 C CNN
+F 2 "" H 4450 1800 60 0000 C CNN
+F 3 "" H 4450 1800 60 0000 C CNN
+ 11 4450 1800
+ 1 0 0 -1
+$EndComp
+Text Label 4700 1900 0 60 ~ 0
+C
+$Comp
+L PORT U1
+U 4 1 6869A09B
+P 3000 1600
+F 0 "U1" H 3050 1700 30 0000 C CNN
+F 1 "PORT" H 3000 1600 30 0000 C CNN
+F 2 "" H 3000 1600 60 0000 C CNN
+F 3 "" H 3000 1600 60 0000 C CNN
+ 4 3000 1600
+ 1 0 0 -1
+$EndComp
+Text Label 3250 1600 0 60 ~ 0
+D_bar
+$Comp
+L PORT U1
+U 18 1 6869A296
+P 7250 3000
+F 0 "U1" H 7300 3100 30 0000 C CNN
+F 1 "PORT" H 7250 3000 30 0000 C CNN
+F 2 "" H 7250 3000 60 0000 C CNN
+F 3 "" H 7250 3000 60 0000 C CNN
+ 18 7250 3000
+ -1 0 0 1
+$EndComp
+Text Label 6900 3000 0 60 ~ 0
+D
+$Comp
+L PORT U1
+U 5 1 6869A547
+P 3100 950
+F 0 "U1" H 3150 1050 30 0000 C CNN
+F 1 "PORT" H 3100 950 30 0000 C CNN
+F 2 "" H 3100 950 60 0000 C CNN
+F 3 "" H 3100 950 60 0000 C CNN
+ 5 3100 950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6869A7EA
+P 4150 950
+F 0 "U1" H 4200 1050 30 0000 C CNN
+F 1 "PORT" H 4150 950 30 0000 C CNN
+F 2 "" H 4150 950 60 0000 C CNN
+F 3 "" H 4150 950 60 0000 C CNN
+ 10 4150 950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2100 1150 1800 1150
+Wire Wire Line
+ 1800 800 1800 2000
+Wire Wire Line
+ 1800 800 6500 800
+Wire Wire Line
+ 6500 800 6500 1150
+Wire Wire Line
+ 1800 2000 2100 2000
+Connection ~ 1800 1150
+Wire Wire Line
+ 3600 1150 3500 1150
+Wire Wire Line
+ 3500 800 3500 2700
+Connection ~ 3500 800
+Wire Wire Line
+ 3500 2000 3600 2000
+Connection ~ 3500 1150
+Wire Wire Line
+ 5050 1150 4950 1150
+Wire Wire Line
+ 4950 800 4950 2000
+Connection ~ 4950 800
+Wire Wire Line
+ 4950 2000 5050 2000
+Connection ~ 4950 1150
+Wire Wire Line
+ 6500 2000 6400 2000
+Wire Wire Line
+ 6400 2000 6400 800
+Connection ~ 6400 800
+Wire Wire Line
+ 2950 2900 2950 2700
+Wire Wire Line
+ 2950 2700 5700 2700
+Connection ~ 3500 2000
+Wire Wire Line
+ 2650 1600 2650 1700
+Wire Wire Line
+ 2650 1700 7100 1700
+Wire Wire Line
+ 7100 1700 7100 2550
+Wire Wire Line
+ 7100 2550 2550 2550
+Wire Wire Line
+ 2550 2550 2550 3450
+Wire Wire Line
+ 2550 3450 6250 3450
+Wire Wire Line
+ 6250 3450 6250 3350
+Wire Wire Line
+ 3500 3350 3500 3450
+Connection ~ 3500 3450
+Wire Wire Line
+ 2650 2450 2650 2550
+Connection ~ 2650 2550
+Wire Wire Line
+ 4150 2450 4150 2550
+Connection ~ 4150 2550
+Wire Wire Line
+ 5600 2450 5600 2550
+Connection ~ 5600 2550
+Wire Wire Line
+ 7050 2450 7050 2550
+Connection ~ 7050 2550
+Wire Wire Line
+ 7000 1600 7000 1700
+Connection ~ 7000 1700
+Wire Wire Line
+ 5550 1600 5550 1700
+Connection ~ 5550 1700
+Wire Wire Line
+ 4100 1600 4100 1700
+Connection ~ 4100 1700
+Wire Wire Line
+ 5700 2700 5700 2900
+Connection ~ 3500 2700
+Wire Wire Line
+ 2100 1250 1850 1250
+Wire Wire Line
+ 1850 1250 1850 3000
+Wire Wire Line
+ 1850 2100 2100 2100
+Wire Wire Line
+ 5050 1250 4900 1250
+Wire Wire Line
+ 4900 1250 4900 2100
+Wire Wire Line
+ 4900 2100 5050 2100
+Wire Wire Line
+ 4900 1750 1850 1750
+Connection ~ 1850 1750
+Connection ~ 4900 1750
+Wire Wire Line
+ 1850 3000 2950 3000
+Connection ~ 1850 2100
+Wire Wire Line
+ 2100 1350 1950 1350
+Wire Wire Line
+ 1950 1350 1950 3200
+Wire Wire Line
+ 1950 2200 2100 2200
+Wire Wire Line
+ 3600 1350 3550 1350
+Wire Wire Line
+ 3550 1350 3550 2200
+Wire Wire Line
+ 3550 2200 3600 2200
+Wire Wire Line
+ 1950 1800 3550 1800
+Connection ~ 3550 1800
+Connection ~ 1950 1800
+Wire Wire Line
+ 5700 3100 5700 3200
+Wire Wire Line
+ 5700 3200 1950 3200
+Connection ~ 1950 2200
+Wire Wire Line
+ 2950 3100 2950 3200
+Connection ~ 2950 3200
+Wire Wire Line
+ 3600 1250 3450 1250
+Wire Wire Line
+ 3450 1250 3450 2100
+Wire Wire Line
+ 3450 2100 3600 2100
+Wire Wire Line
+ 6500 1250 6450 1250
+Wire Wire Line
+ 6450 1250 6450 2100
+Wire Wire Line
+ 6450 2100 6500 2100
+Wire Wire Line
+ 3450 1500 6450 1500
+Connection ~ 6450 1500
+Connection ~ 3450 1500
+Wire Wire Line
+ 5700 3000 4850 3000
+Wire Wire Line
+ 4850 3000 4850 1500
+Connection ~ 4850 1500
+Wire Wire Line
+ 5050 1350 5000 1350
+Wire Wire Line
+ 5000 1350 5000 2200
+Wire Wire Line
+ 5000 2200 5050 2200
+Wire Wire Line
+ 6500 1350 6350 1350
+Wire Wire Line
+ 6350 1350 6350 2200
+Wire Wire Line
+ 6350 2200 6500 2200
+Wire Wire Line
+ 6350 1600 5000 1600
+Connection ~ 5000 1600
+Connection ~ 6350 1600
+Wire Wire Line
+ 3200 1150 3200 1050
+Wire Wire Line
+ 3200 1050 7550 1050
+Wire Wire Line
+ 7550 1050 7550 1150
+Wire Wire Line
+ 4100 2900 4100 2800
+Wire Wire Line
+ 4100 2800 6800 2800
+Wire Wire Line
+ 6800 2800 6800 2900
+Wire Wire Line
+ 4800 950 4800 2800
+Connection ~ 4800 2800
+Connection ~ 4800 1050
+Wire Wire Line
+ 4650 1150 4650 1050
+Connection ~ 4650 1050
+Wire Wire Line
+ 6100 1150 6100 1050
+Connection ~ 6100 1050
+Wire Wire Line
+ 3200 2000 3200 1900
+Wire Wire Line
+ 3200 1900 7600 1900
+Wire Wire Line
+ 7600 1900 7600 2000
+Wire Wire Line
+ 6150 2000 6150 1900
+Connection ~ 6150 1900
+Wire Wire Line
+ 4700 1800 4700 2000
+Connection ~ 4700 1900
+Wire Wire Line
+ 3200 1250 3250 1250
+Wire Wire Line
+ 3250 1250 3250 2100
+Wire Wire Line
+ 3250 2100 3200 2100
+Wire Wire Line
+ 4650 1250 4750 1250
+Wire Wire Line
+ 4750 1250 4750 2100
+Wire Wire Line
+ 4750 2100 4700 2100
+Wire Wire Line
+ 6100 1250 6250 1250
+Wire Wire Line
+ 6250 1250 6250 2100
+Wire Wire Line
+ 6250 2100 6150 2100
+Wire Wire Line
+ 7550 1250 7650 1250
+Wire Wire Line
+ 7650 1250 7650 2100
+Wire Wire Line
+ 7650 2100 7600 2100
+Wire Wire Line
+ 3250 1600 4600 1600
+Wire Wire Line
+ 4600 1600 4600 1450
+Wire Wire Line
+ 4600 1450 7650 1450
+Connection ~ 7650 1450
+Connection ~ 3250 1600
+Connection ~ 6250 1450
+Connection ~ 4750 1450
+Wire Wire Line
+ 4100 3000 4200 3000
+Wire Wire Line
+ 4200 3000 4200 2650
+Wire Wire Line
+ 4200 2650 6900 2650
+Wire Wire Line
+ 6900 2650 6900 3000
+Wire Wire Line
+ 6800 3000 7000 3000
+Connection ~ 6900 3000
+Wire Wire Line
+ 3350 950 3350 1350
+Wire Wire Line
+ 3350 1350 3200 1350
+Wire Wire Line
+ 4400 950 4700 950
+Wire Wire Line
+ 4700 950 4700 1350
+Wire Wire Line
+ 4700 1350 4650 1350
+$Comp
+L PORT U1
+U 15 1 6869A9FB
+P 5950 950
+F 0 "U1" H 6000 1050 30 0000 C CNN
+F 1 "PORT" H 5950 950 30 0000 C CNN
+F 2 "" H 5950 950 60 0000 C CNN
+F 3 "" H 5950 950 60 0000 C CNN
+ 15 5950 950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6200 950 6200 1350
+Wire Wire Line
+ 6200 1350 6100 1350
+$Comp
+L PORT U1
+U 19 1 6869AC25
+P 7800 1350
+F 0 "U1" H 7850 1450 30 0000 C CNN
+F 1 "PORT" H 7800 1350 30 0000 C CNN
+F 2 "" H 7800 1350 60 0000 C CNN
+F 3 "" H 7800 1350 60 0000 C CNN
+ 19 7800 1350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 20 1 6869ACEC
+P 7850 2200
+F 0 "U1" H 7900 2300 30 0000 C CNN
+F 1 "PORT" H 7850 2200 30 0000 C CNN
+F 2 "" H 7850 2200 60 0000 C CNN
+F 3 "" H 7850 2200 60 0000 C CNN
+ 20 7850 2200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 6869ADC5
+P 6150 2450
+F 0 "U1" H 6200 2550 30 0000 C CNN
+F 1 "PORT" H 6150 2450 30 0000 C CNN
+F 2 "" H 6150 2450 60 0000 C CNN
+F 3 "" H 6150 2450 60 0000 C CNN
+ 16 6150 2450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6869AF77
+P 4700 2450
+F 0 "U1" H 4750 2550 30 0000 C CNN
+F 1 "PORT" H 4700 2450 30 0000 C CNN
+F 2 "" H 4700 2450 60 0000 C CNN
+F 3 "" H 4700 2450 60 0000 C CNN
+ 13 4700 2450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6869B03E
+P 3200 2450
+F 0 "U1" H 3250 2550 30 0000 C CNN
+F 1 "PORT" H 3200 2450 30 0000 C CNN
+F 2 "" H 3200 2450 60 0000 C CNN
+F 3 "" H 3200 2450 60 0000 C CNN
+ 7 3200 2450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6869B11E
+P 4100 3350
+F 0 "U1" H 4150 3450 30 0000 C CNN
+F 1 "PORT" H 4100 3350 30 0000 C CNN
+F 2 "" H 4100 3350 60 0000 C CNN
+F 3 "" H 4100 3350 60 0000 C CNN
+ 9 4100 3350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 17 1 6869B205
+P 6800 3350
+F 0 "U1" H 6850 3450 30 0000 C CNN
+F 1 "PORT" H 6800 3350 30 0000 C CNN
+F 2 "" H 6800 3350 60 0000 C CNN
+F 3 "" H 6800 3350 60 0000 C CNN
+ 17 6800 3350
+ 0 -1 -1 0
+$EndComp
+$Comp
+L Y8 X3
+U 1 1 68695022
+P 3500 3000
+F 0 "X3" H 3500 3100 60 0000 C CNN
+F 1 "Y8" H 3450 2800 60 0000 C CNN
+F 2 "" H 3500 3000 60 0001 C CNN
+F 3 "" H 3500 3000 60 0001 C CNN
+ 1 3500 3000
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.sub b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.sub
new file mode 100644
index 000000000..5a8530dc2
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP.sub
@@ -0,0 +1,29 @@
+* Subcircuit TC74HC4028AP
+.subckt TC74HC4028AP /vd /a_bar /b_bar /d_bar net-_u1-pad5_ /a net-_u1-pad7_ /gnd net-_u1-pad9_ net-_u1-pad10_ /c /c_bar net-_u1-pad13_ /b net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ /d net-_u1-pad19_ net-_u1-pad20_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/tc74hc4028ap/tc74hc4028ap.cir
+.include Y5.sub
+.include Y1.sub
+.include Y2.sub
+.include Y8.sub
+.include Y4.sub
+.include Y9.sub
+.include Y7.sub
+.include Y3.sub
+.include Y6.sub
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 /a_bar /b_bar /gnd /vd net-_u1-pad5_ /c_bar /d_bar Y0
+x4 /vd /a /b_bar /gnd /c_bar /d_bar net-_u1-pad10_ Y1
+x6 /vd /a_bar /b /gnd /c_bar /d_bar net-_u1-pad15_ Y2
+x9 /vd /a /b /gnd /c_bar /d_bar net-_u1-pad19_ Y3
+x2 /vd /a_bar /b_bar /gnd /c /d_bar net-_u1-pad7_ Y4
+x5 /vd /a /b_bar /gnd /c /d_bar net-_u1-pad13_ Y5
+x7 /vd /a_bar /b /gnd /c /d_bar net-_u1-pad16_ Y6
+x10 /vd /a /b /gnd /c /d_bar net-_u1-pad20_ Y7
+x8 /vd /a /b_bar /gnd /c_bar /d net-_u1-pad17_ Y9
+* s c m o d e
+x3 /vd /a_bar /b_bar /gnd /c_bar /d net-_u1-pad9_ Y8
+* Control Statements
+
+.ends TC74HC4028AP
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP_Previous_Values.xml
new file mode 100644
index 000000000..c9c66b6e4
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/TC74HC4028AP_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y1/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y2/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y3/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y4/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y5/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y6/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y7/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y9/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y8truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y0-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y0-cache.lib
new file mode 100644
index 000000000..b57744f64
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y0-cache.lib
@@ -0,0 +1,110 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__nfet_01v8
+#
+DEF sky130_fd_pr__nfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__nfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 2 0 0 2 -200 0 25 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 150 -175 N
+P 2 0 0 2 75 175 200 175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 150 -150 200 -175 150 -200 150 -150 F
+P 4 0 0 1 200 25 150 0 200 -25 200 25 F
+X D 1 200 300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 -300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sky130_fd_pr__pfet_01v8
+#
+DEF sky130_fd_pr__pfet_01v8 SC 0 20 Y N 1 F N
+F0 "SC" 50 300 50 H V C CNN
+F1 "sky130_fd_pr__pfet_01v8" 300 87 50 H V R CNN
+F2 "" 0 -1500 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+A -25 0 50 0 600 0 0 1 N 25 0 0 43
+A -25 0 50 600 1200 0 0 1 N 0 43 -50 43
+A -25 0 50 1200 1800 0 0 1 N -50 43 -75 0
+A -25 0 50 1800 -1200 0 0 1 N -75 0 -50 -43
+A -25 0 50 -1200 -600 0 0 1 N -50 -43 0 -43
+A -25 0 50 -600 0 0 0 1 N 0 -43 25 0
+P 2 0 0 2 -200 0 -75 0 N
+P 2 0 0 2 25 150 25 -150 N
+P 2 0 0 2 75 -175 200 -175 N
+P 2 0 0 2 75 225 75 -225 N
+P 2 0 0 2 125 175 200 175 N
+P 2 0 0 2 200 -175 200 -300 N
+P 2 0 0 2 200 300 200 175 N
+P 4 0 0 1 125 200 75 175 125 150 125 200 F
+P 4 0 0 1 150 25 200 0 150 -25 150 25 F
+X D 1 200 -300 5 R 50 43 1 1 B
+X G 2 -300 0 100 R 50 43 1 1 I
+X S 3 200 300 5 R 50 43 1 1 B
+X B 4 100 0 100 R 50 43 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y0.bak b/library/SubcircuitLibrary/TC74HC4028AP/Y0.bak
new file mode 100644
index 000000000..39c2c4129
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y0.bak
@@ -0,0 +1,330 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 68676C8E
+P 3950 1650
+F 0 "SC1" H 4000 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4250 1737 50 0000 R CNN
+F 2 "" H 3950 150 50 0001 C CNN
+F 3 "" H 3950 1650 50 0001 C CNN
+ 1 3950 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 68676CCD
+P 4900 1650
+F 0 "SC2" H 4950 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5200 1737 50 0000 R CNN
+F 2 "" H 4900 150 50 0001 C CNN
+F 3 "" H 4900 1650 50 0001 C CNN
+ 1 4900 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC7
+U 1 1 68676D7A
+P 5500 1650
+F 0 "SC7" H 5550 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5800 1737 50 0000 R CNN
+F 2 "" H 5500 150 50 0001 C CNN
+F 3 "" H 5500 1650 50 0001 C CNN
+ 1 5500 1650
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC8
+U 1 1 68676DC9
+P 6450 1650
+F 0 "SC8" H 6500 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6750 1737 50 0000 R CNN
+F 2 "" H 6450 150 50 0001 C CNN
+F 3 "" H 6450 1650 50 0001 C CNN
+ 1 6450 1650
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 68676F1A
+P 5000 2500
+F 0 "SC3" H 5050 2800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5300 2587 50 0000 R CNN
+F 2 "" H 5000 1000 50 0001 C CNN
+F 3 "" H 5000 2500 50 0001 C CNN
+ 1 5000 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 68676F92
+P 5000 3150
+F 0 "SC4" H 5050 3450 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5300 3237 50 0000 R CNN
+F 2 "" H 5000 1650 50 0001 C CNN
+F 3 "" H 5000 3150 50 0001 C CNN
+ 1 5000 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 68676FE3
+P 5400 3800
+F 0 "SC5" H 5450 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5700 3887 50 0000 R CNN
+F 2 "" H 5400 2300 50 0001 C CNN
+F 3 "" H 5400 3800 50 0001 C CNN
+ 1 5400 3800
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 68677050
+P 5400 4450
+F 0 "SC6" H 5450 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5700 4537 50 0000 R CNN
+F 2 "" H 5400 2950 50 0001 C CNN
+F 3 "" H 5400 4450 50 0001 C CNN
+ 1 5400 4450
+ -1 0 0 -1
+$EndComp
+Connection ~ 6200 1300
+Wire Wire Line
+ 6200 1650 6200 1300
+Wire Wire Line
+ 6350 1650 6200 1650
+Connection ~ 4200 1300
+Wire Wire Line
+ 4200 1650 4200 1300
+Wire Wire Line
+ 4050 1650 4200 1650
+Connection ~ 5250 1300
+Wire Wire Line
+ 5250 1650 5250 1300
+Wire Wire Line
+ 5400 1650 5250 1650
+Connection ~ 5150 1300
+Wire Wire Line
+ 5150 1650 5150 1300
+Wire Wire Line
+ 5000 1650 5150 1650
+Connection ~ 5300 1300
+Wire Wire Line
+ 5300 1350 5300 1300
+Connection ~ 5100 1300
+Wire Wire Line
+ 5100 1350 5100 1300
+Wire Wire Line
+ 6250 1300 6250 1350
+Wire Wire Line
+ 4150 1300 6250 1300
+Wire Wire Line
+ 4150 1350 4150 1300
+Wire Wire Line
+ 5200 4100 5200 4150
+Wire Wire Line
+ 5200 3450 5200 3500
+Wire Wire Line
+ 5200 2800 5200 2850
+Connection ~ 5200 2000
+Wire Wire Line
+ 5200 2200 5200 2000
+Connection ~ 5300 2000
+Wire Wire Line
+ 5300 1950 5300 2000
+Connection ~ 5100 2000
+Wire Wire Line
+ 5100 1950 5100 2000
+Wire Wire Line
+ 6250 2000 6250 1950
+Wire Wire Line
+ 4150 2000 6250 2000
+Wire Wire Line
+ 4150 1950 4150 2000
+Wire Wire Line
+ 5100 2500 5250 2500
+Wire Wire Line
+ 5250 2500 5250 3550
+Wire Wire Line
+ 5250 3550 5100 3550
+Wire Wire Line
+ 5100 3550 5100 4750
+Wire Wire Line
+ 5050 4750 5200 4750
+Wire Wire Line
+ 5300 4450 5100 4450
+Connection ~ 5100 4450
+Wire Wire Line
+ 5300 3800 5100 3800
+Connection ~ 5100 3800
+Wire Wire Line
+ 5100 3150 5250 3150
+Connection ~ 5250 3150
+Wire Wire Line
+ 3650 1650 3650 2500
+Wire Wire Line
+ 3650 2500 4700 2500
+Wire Wire Line
+ 4700 3150 4500 3150
+Wire Wire Line
+ 4500 3150 4500 1650
+Wire Wire Line
+ 4500 1650 4600 1650
+Wire Wire Line
+ 5800 1650 5800 3800
+Wire Wire Line
+ 5800 3800 5700 3800
+Wire Wire Line
+ 5700 4450 6750 4450
+Wire Wire Line
+ 6750 4450 6750 1650
+$Comp
+L PORT U1
+U 1 1 68677A45
+P 3350 1850
+F 0 "U1" H 3400 1950 30 0000 C CNN
+F 1 "PORT" H 3350 1850 30 0000 C CNN
+F 2 "" H 3350 1850 60 0000 C CNN
+F 3 "" H 3350 1850 60 0000 C CNN
+ 1 3350 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68677B5F
+P 4200 2150
+F 0 "U1" H 4250 2250 30 0000 C CNN
+F 1 "PORT" H 4200 2150 30 0000 C CNN
+F 2 "" H 4200 2150 60 0000 C CNN
+F 3 "" H 4200 2150 60 0000 C CNN
+ 2 4200 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68677BC8
+P 5650 2100
+F 0 "U1" H 5700 2200 30 0000 C CNN
+F 1 "PORT" H 5650 2100 30 0000 C CNN
+F 2 "" H 5650 2100 60 0000 C CNN
+F 3 "" H 5650 2100 60 0000 C CNN
+ 5 5650 2100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68677C7B
+P 6100 2850
+F 0 "U1" H 6150 2950 30 0000 C CNN
+F 1 "PORT" H 6100 2850 30 0000 C CNN
+F 2 "" H 6100 2850 60 0000 C CNN
+F 3 "" H 6100 2850 60 0000 C CNN
+ 6 6100 2850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68677D10
+P 6450 2850
+F 0 "U1" H 6500 2950 30 0000 C CNN
+F 1 "PORT" H 6450 2850 30 0000 C CNN
+F 2 "" H 6450 2850 60 0000 C CNN
+F 3 "" H 6450 2850 60 0000 C CNN
+ 7 6450 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68677DD2
+P 4800 4750
+F 0 "U1" H 4850 4850 30 0000 C CNN
+F 1 "PORT" H 4800 4750 30 0000 C CNN
+F 2 "" H 4800 4750 60 0000 C CNN
+F 3 "" H 4800 4750 60 0000 C CNN
+ 3 4800 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68677EED
+P 4950 1200
+F 0 "U1" H 5000 1300 30 0000 C CNN
+F 1 "PORT" H 4950 1200 30 0000 C CNN
+F 2 "" H 4950 1200 60 0000 C CNN
+F 3 "" H 4950 1200 60 0000 C CNN
+ 4 4950 1200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5200 1200 5200 1300
+Connection ~ 5200 1300
+Wire Wire Line
+ 3600 1850 3650 1850
+Connection ~ 3650 1850
+Wire Wire Line
+ 4450 2150 4500 2150
+Connection ~ 4500 2150
+Wire Wire Line
+ 5400 2100 5200 2100
+Connection ~ 5200 2100
+Wire Wire Line
+ 5850 2850 5800 2850
+Connection ~ 5800 2850
+Wire Wire Line
+ 6700 2850 6750 2850
+Connection ~ 6750 2850
+Connection ~ 5100 4750
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y0.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y0.cir
new file mode 100644
index 000000000..622527f5c
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y0.cir
@@ -0,0 +1,20 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0/Y0.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 11:46:28 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+SC1 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC2 Net-_SC1-Pad1_ Net-_SC2-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC7 Net-_SC1-Pad1_ Net-_SC5-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC8 Net-_SC1-Pad1_ Net-_SC6-Pad2_ Net-_SC1-Pad3_ Net-_SC1-Pad3_ sky130_fd_pr__pfet_01v8
+SC3 Net-_SC1-Pad1_ Net-_SC1-Pad2_ Net-_SC3-Pad3_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+SC4 Net-_SC3-Pad3_ Net-_SC2-Pad2_ Net-_SC4-Pad3_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+SC5 Net-_SC4-Pad3_ Net-_SC5-Pad2_ Net-_SC5-Pad3_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+SC6 Net-_SC5-Pad3_ Net-_SC6-Pad2_ Net-_SC3-Pad4_ Net-_SC3-Pad4_ sky130_fd_pr__nfet_01v8
+U1 Net-_SC1-Pad2_ Net-_SC2-Pad2_ Net-_SC3-Pad4_ Net-_SC1-Pad3_ Net-_SC1-Pad1_ Net-_SC5-Pad2_ Net-_SC6-Pad2_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y0.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y0.cir.out
new file mode 100644
index 000000000..7eb8fc0d0
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y0.cir.out
@@ -0,0 +1,23 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y0/y0.cir
+
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc7 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc1-pad1_ net-_sc6-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc2-pad2_ net-_sc4-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc5-pad2_ net-_sc5-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc5-pad3_ net-_sc6-pad2_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* u1 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc3-pad4_ net-_sc1-pad3_ net-_sc1-pad1_ net-_sc5-pad2_ net-_sc6-pad2_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y0.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y0.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y0.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y0.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y0.sch
new file mode 100644
index 000000000..ed74e0c7b
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y0.sch
@@ -0,0 +1,341 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sky130_fd_pr__pfet_01v8 SC1
+U 1 1 68676C8E
+P 3950 1650
+F 0 "SC1" H 4000 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 4250 1737 50 0000 R CNN
+F 2 "" H 3950 150 50 0001 C CNN
+F 3 "" H 3950 1650 50 0001 C CNN
+ 1 3950 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC2
+U 1 1 68676CCD
+P 4900 1650
+F 0 "SC2" H 4950 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5200 1737 50 0000 R CNN
+F 2 "" H 4900 150 50 0001 C CNN
+F 3 "" H 4900 1650 50 0001 C CNN
+ 1 4900 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC7
+U 1 1 68676D7A
+P 5500 1650
+F 0 "SC7" H 5550 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 5800 1737 50 0000 R CNN
+F 2 "" H 5500 150 50 0001 C CNN
+F 3 "" H 5500 1650 50 0001 C CNN
+ 1 5500 1650
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__pfet_01v8 SC8
+U 1 1 68676DC9
+P 6450 1650
+F 0 "SC8" H 6500 1950 50 0000 C CNN
+F 1 "sky130_fd_pr__pfet_01v8" H 6750 1737 50 0000 R CNN
+F 2 "" H 6450 150 50 0001 C CNN
+F 3 "" H 6450 1650 50 0001 C CNN
+ 1 6450 1650
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC3
+U 1 1 68676F1A
+P 5000 2500
+F 0 "SC3" H 5050 2800 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5300 2587 50 0000 R CNN
+F 2 "" H 5000 1000 50 0001 C CNN
+F 3 "" H 5000 2500 50 0001 C CNN
+ 1 5000 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC4
+U 1 1 68676F92
+P 5000 3150
+F 0 "SC4" H 5050 3450 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5300 3237 50 0000 R CNN
+F 2 "" H 5000 1650 50 0001 C CNN
+F 3 "" H 5000 3150 50 0001 C CNN
+ 1 5000 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC5
+U 1 1 68676FE3
+P 5400 3800
+F 0 "SC5" H 5450 4100 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5700 3887 50 0000 R CNN
+F 2 "" H 5400 2300 50 0001 C CNN
+F 3 "" H 5400 3800 50 0001 C CNN
+ 1 5400 3800
+ -1 0 0 -1
+$EndComp
+$Comp
+L sky130_fd_pr__nfet_01v8 SC6
+U 1 1 68677050
+P 5400 4450
+F 0 "SC6" H 5450 4750 50 0000 C CNN
+F 1 "sky130_fd_pr__nfet_01v8" H 5700 4537 50 0000 R CNN
+F 2 "" H 5400 2950 50 0001 C CNN
+F 3 "" H 5400 4450 50 0001 C CNN
+ 1 5400 4450
+ -1 0 0 -1
+$EndComp
+Connection ~ 6200 1300
+Wire Wire Line
+ 6200 1650 6200 1300
+Wire Wire Line
+ 6350 1650 6200 1650
+Connection ~ 4200 1300
+Wire Wire Line
+ 4200 1650 4200 1300
+Wire Wire Line
+ 4050 1650 4200 1650
+Connection ~ 5250 1300
+Wire Wire Line
+ 5250 1650 5250 1300
+Wire Wire Line
+ 5400 1650 5250 1650
+Connection ~ 5150 1300
+Wire Wire Line
+ 5150 1650 5150 1300
+Wire Wire Line
+ 5000 1650 5150 1650
+Connection ~ 5300 1300
+Wire Wire Line
+ 5300 1350 5300 1300
+Connection ~ 5100 1300
+Wire Wire Line
+ 5100 1350 5100 1300
+Wire Wire Line
+ 6250 1300 6250 1350
+Wire Wire Line
+ 4150 1300 6250 1300
+Wire Wire Line
+ 4150 1350 4150 1300
+Wire Wire Line
+ 5200 4100 5200 4150
+Wire Wire Line
+ 5200 3450 5200 3500
+Wire Wire Line
+ 5200 2800 5200 2850
+Connection ~ 5200 2000
+Wire Wire Line
+ 5200 2200 5200 2000
+Connection ~ 5300 2000
+Wire Wire Line
+ 5300 1950 5300 2000
+Connection ~ 5100 2000
+Wire Wire Line
+ 5100 1950 5100 2000
+Wire Wire Line
+ 6250 2000 6250 1950
+Wire Wire Line
+ 4150 2000 6250 2000
+Wire Wire Line
+ 4150 1950 4150 2000
+Wire Wire Line
+ 5100 2500 5250 2500
+Wire Wire Line
+ 5250 2500 5250 3550
+Wire Wire Line
+ 5250 3550 5100 3550
+Wire Wire Line
+ 5100 3550 5100 4750
+Wire Wire Line
+ 5050 4750 5200 4750
+Wire Wire Line
+ 5300 4450 5100 4450
+Connection ~ 5100 4450
+Wire Wire Line
+ 5300 3800 5100 3800
+Connection ~ 5100 3800
+Wire Wire Line
+ 5100 3150 5250 3150
+Connection ~ 5250 3150
+Wire Wire Line
+ 3650 1650 3650 2500
+Wire Wire Line
+ 3650 2500 4700 2500
+Wire Wire Line
+ 4700 3150 4500 3150
+Wire Wire Line
+ 4500 3150 4500 1650
+Wire Wire Line
+ 4500 1650 4600 1650
+Wire Wire Line
+ 5800 1650 5800 3800
+Wire Wire Line
+ 5800 3800 5700 3800
+Wire Wire Line
+ 5700 4450 6750 4450
+Wire Wire Line
+ 6750 4450 6750 1650
+$Comp
+L PORT U1
+U 1 1 68677A45
+P 3350 1850
+F 0 "U1" H 3400 1950 30 0000 C CNN
+F 1 "PORT" H 3350 1850 30 0000 C CNN
+F 2 "" H 3350 1850 60 0000 C CNN
+F 3 "" H 3350 1850 60 0000 C CNN
+ 1 3350 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68677B5F
+P 4200 2150
+F 0 "U1" H 4250 2250 30 0000 C CNN
+F 1 "PORT" H 4200 2150 30 0000 C CNN
+F 2 "" H 4200 2150 60 0000 C CNN
+F 3 "" H 4200 2150 60 0000 C CNN
+ 2 4200 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68677BC8
+P 5650 2100
+F 0 "U1" H 5700 2200 30 0000 C CNN
+F 1 "PORT" H 5650 2100 30 0000 C CNN
+F 2 "" H 5650 2100 60 0000 C CNN
+F 3 "" H 5650 2100 60 0000 C CNN
+ 5 5650 2100
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68677C7B
+P 6100 2850
+F 0 "U1" H 6150 2950 30 0000 C CNN
+F 1 "PORT" H 6100 2850 30 0000 C CNN
+F 2 "" H 6100 2850 60 0000 C CNN
+F 3 "" H 6100 2850 60 0000 C CNN
+ 6 6100 2850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68677D10
+P 6450 2850
+F 0 "U1" H 6500 2950 30 0000 C CNN
+F 1 "PORT" H 6450 2850 30 0000 C CNN
+F 2 "" H 6450 2850 60 0000 C CNN
+F 3 "" H 6450 2850 60 0000 C CNN
+ 7 6450 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68677DD2
+P 4800 4750
+F 0 "U1" H 4850 4850 30 0000 C CNN
+F 1 "PORT" H 4800 4750 30 0000 C CNN
+F 2 "" H 4800 4750 60 0000 C CNN
+F 3 "" H 4800 4750 60 0000 C CNN
+ 3 4800 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68677EED
+P 4950 1200
+F 0 "U1" H 5000 1300 30 0000 C CNN
+F 1 "PORT" H 4950 1200 30 0000 C CNN
+F 2 "" H 4950 1200 60 0000 C CNN
+F 3 "" H 4950 1200 60 0000 C CNN
+ 4 4950 1200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5200 1200 5200 1300
+Connection ~ 5200 1300
+Wire Wire Line
+ 3600 1850 3650 1850
+Connection ~ 3650 1850
+Wire Wire Line
+ 4450 2150 4500 2150
+Connection ~ 4500 2150
+Wire Wire Line
+ 5400 2100 5200 2100
+Connection ~ 5200 2100
+Wire Wire Line
+ 5850 2850 5800 2850
+Connection ~ 5800 2850
+Wire Wire Line
+ 6700 2850 6750 2850
+Connection ~ 6750 2850
+Connection ~ 5100 4750
+$Comp
+L SKY130mode scmode1
+U 1 1 686789A5
+P 8950 2600
+F 0 "scmode1" H 8950 2750 98 0000 C CNB
+F 1 "SKY130mode" H 8950 2500 118 0000 C CNB
+F 2 "" H 8950 2750 60 0001 C CNN
+F 3 "" H 8950 2750 60 0001 C CNN
+ 1 8950 2600
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y0.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y0.sub
new file mode 100644
index 000000000..8fa0310cb
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y0.sub
@@ -0,0 +1,17 @@
+* Subcircuit Y0
+.subckt Y0 net-_sc1-pad2_ net-_sc2-pad2_ net-_sc3-pad4_ net-_sc1-pad3_ net-_sc1-pad1_ net-_sc5-pad2_ net-_sc6-pad2_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y0/y0.cir
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+xsc1 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc2 net-_sc1-pad1_ net-_sc2-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc7 net-_sc1-pad1_ net-_sc5-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc8 net-_sc1-pad1_ net-_sc6-pad2_ net-_sc1-pad3_ net-_sc1-pad3_ sky130_fd_pr__pfet_01v8 w=3 l=0.15
+xsc3 net-_sc1-pad1_ net-_sc1-pad2_ net-_sc3-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc4 net-_sc3-pad3_ net-_sc2-pad2_ net-_sc4-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc5 net-_sc4-pad3_ net-_sc5-pad2_ net-_sc5-pad3_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+xsc6 net-_sc5-pad3_ net-_sc6-pad2_ net-_sc3-pad4_ net-_sc3-pad4_ sky130_fd_pr__nfet_01v8 w=1 l=0.15
+* s c m o d e
+* Control Statements
+
+.ends Y0
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y0_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y0_Previous_Values.xml
new file mode 100644
index 000000000..0520033b7
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y0_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicettw=3 l=0.15w=3 l=0.15w=3 l=0.15w=3 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15w=1 l=0.15truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y1-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y1-cache.lib
new file mode 100644
index 000000000..25c3aaccc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y1-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y1.bak b/library/SubcircuitLibrary/TC74HC4028AP/Y1.bak
new file mode 100644
index 000000000..d72313891
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y1.bak
@@ -0,0 +1,155 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 6868C462
+P 5500 2950
+F 0 "X1" H 5500 3050 60 0000 C CNN
+F 1 "Y0" H 5450 2750 60 0000 C CNN
+F 2 "" H 5500 2950 60 0001 C CNN
+F 3 "" H 5500 2950 60 0001 C CNN
+ 1 5500 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6868C694
+P 4700 2850
+F 0 "U1" H 4750 2950 30 0000 C CNN
+F 1 "PORT" H 4700 2850 30 0000 C CNN
+F 2 "" H 4700 2850 60 0000 C CNN
+F 3 "" H 4700 2850 60 0000 C CNN
+ 1 4700 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6868C6F5
+P 4700 2950
+F 0 "U1" H 4750 3050 30 0000 C CNN
+F 1 "PORT" H 4700 2950 30 0000 C CNN
+F 2 "" H 4700 2950 60 0000 C CNN
+F 3 "" H 4700 2950 60 0000 C CNN
+ 2 4700 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6868C7FF
+P 4700 3050
+F 0 "U1" H 4750 3150 30 0000 C CNN
+F 1 "PORT" H 4700 3050 30 0000 C CNN
+F 2 "" H 4700 3050 60 0000 C CNN
+F 3 "" H 4700 3050 60 0000 C CNN
+ 3 4700 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6868C83E
+P 6300 2850
+F 0 "U1" H 6350 2950 30 0000 C CNN
+F 1 "PORT" H 6300 2850 30 0000 C CNN
+F 2 "" H 6300 2850 60 0000 C CNN
+F 3 "" H 6300 2850 60 0000 C CNN
+ 5 6300 2850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6868C889
+P 6300 2950
+F 0 "U1" H 6350 3050 30 0000 C CNN
+F 1 "PORT" H 6300 2950 30 0000 C CNN
+F 2 "" H 6300 2950 60 0000 C CNN
+F 3 "" H 6300 2950 60 0000 C CNN
+ 6 6300 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6868C8CC
+P 6300 3050
+F 0 "U1" H 6350 3150 30 0000 C CNN
+F 1 "PORT" H 6300 3050 30 0000 C CNN
+F 2 "" H 6300 3050 60 0000 C CNN
+F 3 "" H 6300 3050 60 0000 C CNN
+ 7 6300 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6868C920
+P 5250 3300
+F 0 "U1" H 5300 3400 30 0000 C CNN
+F 1 "PORT" H 5250 3300 30 0000 C CNN
+F 2 "" H 5250 3300 60 0000 C CNN
+F 3 "" H 5250 3300 60 0000 C CNN
+ 4 5250 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode?
+U 1 1 6868C9C1
+P 7500 3100
+F 0 "scmode?" H 7500 3250 98 0000 C CNB
+F 1 "SKY130mode" H 7500 3000 118 0000 C CNB
+F 2 "" H 7500 3250 60 0001 C CNN
+F 3 "" H 7500 3250 60 0001 C CNN
+ 1 7500 3100
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y1.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y1.cir
new file mode 100644
index 000000000..e63cff5a1
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y1.cir
@@ -0,0 +1,13 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y1/Y1.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 12:02:16 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_U1-Pad6_ Y0
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y1.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y1.cir.out
new file mode 100644
index 000000000..1e95076e7
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y1.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y1/y1.cir
+
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y1.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y1.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y1.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y1.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y1.sch
new file mode 100644
index 000000000..8a315c74f
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y1.sch
@@ -0,0 +1,155 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 6868C462
+P 5500 2950
+F 0 "X1" H 5500 3050 60 0000 C CNN
+F 1 "Y0" H 5450 2750 60 0000 C CNN
+F 2 "" H 5500 2950 60 0001 C CNN
+F 3 "" H 5500 2950 60 0001 C CNN
+ 1 5500 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6868C694
+P 4700 2850
+F 0 "U1" H 4750 2950 30 0000 C CNN
+F 1 "PORT" H 4700 2850 30 0000 C CNN
+F 2 "" H 4700 2850 60 0000 C CNN
+F 3 "" H 4700 2850 60 0000 C CNN
+ 1 4700 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6868C6F5
+P 4700 2950
+F 0 "U1" H 4750 3050 30 0000 C CNN
+F 1 "PORT" H 4700 2950 30 0000 C CNN
+F 2 "" H 4700 2950 60 0000 C CNN
+F 3 "" H 4700 2950 60 0000 C CNN
+ 2 4700 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6868C7FF
+P 4700 3050
+F 0 "U1" H 4750 3150 30 0000 C CNN
+F 1 "PORT" H 4700 3050 30 0000 C CNN
+F 2 "" H 4700 3050 60 0000 C CNN
+F 3 "" H 4700 3050 60 0000 C CNN
+ 3 4700 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6868C83E
+P 6300 2850
+F 0 "U1" H 6350 2950 30 0000 C CNN
+F 1 "PORT" H 6300 2850 30 0000 C CNN
+F 2 "" H 6300 2850 60 0000 C CNN
+F 3 "" H 6300 2850 60 0000 C CNN
+ 5 6300 2850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6868C889
+P 6300 2950
+F 0 "U1" H 6350 3050 30 0000 C CNN
+F 1 "PORT" H 6300 2950 30 0000 C CNN
+F 2 "" H 6300 2950 60 0000 C CNN
+F 3 "" H 6300 2950 60 0000 C CNN
+ 6 6300 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6868C8CC
+P 6300 3050
+F 0 "U1" H 6350 3150 30 0000 C CNN
+F 1 "PORT" H 6300 3050 30 0000 C CNN
+F 2 "" H 6300 3050 60 0000 C CNN
+F 3 "" H 6300 3050 60 0000 C CNN
+ 7 6300 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6868C920
+P 5250 3300
+F 0 "U1" H 5300 3400 30 0000 C CNN
+F 1 "PORT" H 5250 3300 30 0000 C CNN
+F 2 "" H 5250 3300 60 0000 C CNN
+F 3 "" H 5250 3300 60 0000 C CNN
+ 4 5250 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 6868C9C1
+P 7500 3100
+F 0 "scmode1" H 7500 3250 98 0000 C CNB
+F 1 "SKY130mode" H 7500 3000 118 0000 C CNB
+F 2 "" H 7500 3250 60 0001 C CNN
+F 3 "" H 7500 3250 60 0001 C CNN
+ 1 7500 3100
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y1.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y1.sub
new file mode 100644
index 000000000..f79c5f57c
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y1.sub
@@ -0,0 +1,11 @@
+* Subcircuit Y1
+.subckt Y1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y1/y1.cir
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* Control Statements
+
+.ends Y1
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y1_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y1_Previous_Values.xml
new file mode 100644
index 000000000..73bfc204a
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y1_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y2-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y2-cache.lib
new file mode 100644
index 000000000..25c3aaccc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y2-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y2.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y2.cir
new file mode 100644
index 000000000..3d88cac72
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y2.cir
@@ -0,0 +1,13 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y2/Y2.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 12:27:26 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_U1-Pad6_ Y0
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y2.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y2.cir.out
new file mode 100644
index 000000000..f93fb21fc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y2.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y2/y2.cir
+
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y2.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y2.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y2.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y2.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y2.sch
new file mode 100644
index 000000000..d3e74d8f7
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y2.sch
@@ -0,0 +1,155 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 6868CC9E
+P 5150 3000
+F 0 "X1" H 5150 3100 60 0000 C CNN
+F 1 "Y0" H 5100 2800 60 0000 C CNN
+F 2 "" H 5150 3000 60 0001 C CNN
+F 3 "" H 5150 3000 60 0001 C CNN
+ 1 5150 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 6868CD17
+P 6750 5150
+F 0 "scmode1" H 6750 5300 98 0000 C CNB
+F 1 "SKY130mode" H 6750 5050 118 0000 C CNB
+F 2 "" H 6750 5300 60 0001 C CNN
+F 3 "" H 6750 5300 60 0001 C CNN
+ 1 6750 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6868CD44
+P 4350 2900
+F 0 "U1" H 4400 3000 30 0000 C CNN
+F 1 "PORT" H 4350 2900 30 0000 C CNN
+F 2 "" H 4350 2900 60 0000 C CNN
+F 3 "" H 4350 2900 60 0000 C CNN
+ 1 4350 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6868CD67
+P 4350 3000
+F 0 "U1" H 4400 3100 30 0000 C CNN
+F 1 "PORT" H 4350 3000 30 0000 C CNN
+F 2 "" H 4350 3000 60 0000 C CNN
+F 3 "" H 4350 3000 60 0000 C CNN
+ 2 4350 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6868CD8C
+P 4350 3100
+F 0 "U1" H 4400 3200 30 0000 C CNN
+F 1 "PORT" H 4350 3100 30 0000 C CNN
+F 2 "" H 4350 3100 60 0000 C CNN
+F 3 "" H 4350 3100 60 0000 C CNN
+ 3 4350 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6868CDB5
+P 4900 3350
+F 0 "U1" H 4950 3450 30 0000 C CNN
+F 1 "PORT" H 4900 3350 30 0000 C CNN
+F 2 "" H 4900 3350 60 0000 C CNN
+F 3 "" H 4900 3350 60 0000 C CNN
+ 4 4900 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6868CDE4
+P 5950 2900
+F 0 "U1" H 6000 3000 30 0000 C CNN
+F 1 "PORT" H 5950 2900 30 0000 C CNN
+F 2 "" H 5950 2900 60 0000 C CNN
+F 3 "" H 5950 2900 60 0000 C CNN
+ 5 5950 2900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6868CE31
+P 5950 3000
+F 0 "U1" H 6000 3100 30 0000 C CNN
+F 1 "PORT" H 5950 3000 30 0000 C CNN
+F 2 "" H 5950 3000 60 0000 C CNN
+F 3 "" H 5950 3000 60 0000 C CNN
+ 6 5950 3000
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6868CE5C
+P 5950 3100
+F 0 "U1" H 6000 3200 30 0000 C CNN
+F 1 "PORT" H 5950 3100 30 0000 C CNN
+F 2 "" H 5950 3100 60 0000 C CNN
+F 3 "" H 5950 3100 60 0000 C CNN
+ 7 5950 3100
+ -1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y2.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y2.sub
new file mode 100644
index 000000000..5980e933d
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y2.sub
@@ -0,0 +1,11 @@
+* Subcircuit Y2
+.subckt Y2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y2/y2.cir
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* Control Statements
+
+.ends Y2
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y2_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y2_Previous_Values.xml
new file mode 100644
index 000000000..73bfc204a
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y2_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y3-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y3-cache.lib
new file mode 100644
index 000000000..25c3aaccc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y3-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y3.bak b/library/SubcircuitLibrary/TC74HC4028AP/Y3.bak
new file mode 100644
index 000000000..e69de29bb
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y3.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y3.cir
new file mode 100644
index 000000000..703e998d7
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y3.cir
@@ -0,0 +1,13 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y3/Y3.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 20:08:43 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_U1-Pad6_ Y0
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+scmode1 SKY130mode
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y3.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y3.cir.out
new file mode 100644
index 000000000..b4067166c
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y3.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y3/y3.cir
+
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+* s c m o d e
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y3.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y3.pro
new file mode 100644
index 000000000..354f24bb0
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y3.pro
@@ -0,0 +1,83 @@
+update=Sat Jul 5 20:07:25 2025
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y3.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y3.sch
new file mode 100644
index 000000000..3269c1180
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y3.sch
@@ -0,0 +1,156 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:Y3-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 686938B4
+P 5750 2900
+F 0 "X1" H 5750 3000 60 0000 C CNN
+F 1 "Y0" H 5700 2700 60 0000 C CNN
+F 2 "" H 5750 2900 60 0001 C CNN
+F 3 "" H 5750 2900 60 0001 C CNN
+ 1 5750 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6869391A
+P 4950 2800
+F 0 "U1" H 5000 2900 30 0000 C CNN
+F 1 "PORT" H 4950 2800 30 0000 C CNN
+F 2 "" H 4950 2800 60 0000 C CNN
+F 3 "" H 4950 2800 60 0000 C CNN
+ 1 4950 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68693963
+P 4950 2900
+F 0 "U1" H 5000 3000 30 0000 C CNN
+F 1 "PORT" H 4950 2900 30 0000 C CNN
+F 2 "" H 4950 2900 60 0000 C CNN
+F 3 "" H 4950 2900 60 0000 C CNN
+ 2 4950 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68693984
+P 4950 3000
+F 0 "U1" H 5000 3100 30 0000 C CNN
+F 1 "PORT" H 4950 3000 30 0000 C CNN
+F 2 "" H 4950 3000 60 0000 C CNN
+F 3 "" H 4950 3000 60 0000 C CNN
+ 3 4950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686939AB
+P 5500 3250
+F 0 "U1" H 5550 3350 30 0000 C CNN
+F 1 "PORT" H 5500 3250 30 0000 C CNN
+F 2 "" H 5500 3250 60 0000 C CNN
+F 3 "" H 5500 3250 60 0000 C CNN
+ 4 5500 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686939D6
+P 6550 2800
+F 0 "U1" H 6600 2900 30 0000 C CNN
+F 1 "PORT" H 6550 2800 30 0000 C CNN
+F 2 "" H 6550 2800 60 0000 C CNN
+F 3 "" H 6550 2800 60 0000 C CNN
+ 5 6550 2800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68693A27
+P 6550 2900
+F 0 "U1" H 6600 3000 30 0000 C CNN
+F 1 "PORT" H 6550 2900 30 0000 C CNN
+F 2 "" H 6550 2900 60 0000 C CNN
+F 3 "" H 6550 2900 60 0000 C CNN
+ 6 6550 2900
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68693A62
+P 6550 3000
+F 0 "U1" H 6600 3100 30 0000 C CNN
+F 1 "PORT" H 6550 3000 30 0000 C CNN
+F 2 "" H 6550 3000 60 0000 C CNN
+F 3 "" H 6550 3000 60 0000 C CNN
+ 7 6550 3000
+ -1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68693A89
+P 9150 2850
+F 0 "scmode1" H 9150 3000 98 0000 C CNB
+F 1 "SKY130mode" H 9150 2750 118 0000 C CNB
+F 2 "" H 9150 3000 60 0001 C CNN
+F 3 "" H 9150 3000 60 0001 C CNN
+ 1 9150 2850
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y3.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y3.sub
new file mode 100644
index 000000000..d0faae98f
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y3.sub
@@ -0,0 +1,11 @@
+* Subcircuit Y3
+.subckt Y3 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y3/y3.cir
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* Control Statements
+
+.ends Y3
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y3_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y3_Previous_Values.xml
new file mode 100644
index 000000000..73bfc204a
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y3_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y4-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y4-cache.lib
new file mode 100644
index 000000000..25c3aaccc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y4-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y4.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y4.cir
new file mode 100644
index 000000000..6531f8179
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y4.cir
@@ -0,0 +1,13 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y4/Y4.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 20:15:29 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_U1-Pad6_ Y0
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y4.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y4.cir.out
new file mode 100644
index 000000000..396911611
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y4.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y4/y4.cir
+
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y4.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y4.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y4.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y4.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y4.sch
new file mode 100644
index 000000000..5e954bb68
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y4.sch
@@ -0,0 +1,155 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 68693A51
+P 5250 2700
+F 0 "X1" H 5250 2800 60 0000 C CNN
+F 1 "Y0" H 5200 2500 60 0000 C CNN
+F 2 "" H 5250 2700 60 0001 C CNN
+F 3 "" H 5250 2700 60 0001 C CNN
+ 1 5250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68693A90
+P 7800 4350
+F 0 "scmode1" H 7800 4500 98 0000 C CNB
+F 1 "SKY130mode" H 7800 4250 118 0000 C CNB
+F 2 "" H 7800 4500 60 0001 C CNN
+F 3 "" H 7800 4500 60 0001 C CNN
+ 1 7800 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68693ADF
+P 4450 2600
+F 0 "U1" H 4500 2700 30 0000 C CNN
+F 1 "PORT" H 4450 2600 30 0000 C CNN
+F 2 "" H 4450 2600 60 0000 C CNN
+F 3 "" H 4450 2600 60 0000 C CNN
+ 1 4450 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68693B14
+P 4450 2700
+F 0 "U1" H 4500 2800 30 0000 C CNN
+F 1 "PORT" H 4450 2700 30 0000 C CNN
+F 2 "" H 4450 2700 60 0000 C CNN
+F 3 "" H 4450 2700 60 0000 C CNN
+ 2 4450 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68693B41
+P 4450 2800
+F 0 "U1" H 4500 2900 30 0000 C CNN
+F 1 "PORT" H 4450 2800 30 0000 C CNN
+F 2 "" H 4450 2800 60 0000 C CNN
+F 3 "" H 4450 2800 60 0000 C CNN
+ 3 4450 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68693B62
+P 5000 3050
+F 0 "U1" H 5050 3150 30 0000 C CNN
+F 1 "PORT" H 5000 3050 30 0000 C CNN
+F 2 "" H 5000 3050 60 0000 C CNN
+F 3 "" H 5000 3050 60 0000 C CNN
+ 4 5000 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68693BF5
+P 6050 2600
+F 0 "U1" H 6100 2700 30 0000 C CNN
+F 1 "PORT" H 6050 2600 30 0000 C CNN
+F 2 "" H 6050 2600 60 0000 C CNN
+F 3 "" H 6050 2600 60 0000 C CNN
+ 5 6050 2600
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68693C68
+P 6050 2700
+F 0 "U1" H 6100 2800 30 0000 C CNN
+F 1 "PORT" H 6050 2700 30 0000 C CNN
+F 2 "" H 6050 2700 60 0000 C CNN
+F 3 "" H 6050 2700 60 0000 C CNN
+ 6 6050 2700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68693C95
+P 6050 2800
+F 0 "U1" H 6100 2900 30 0000 C CNN
+F 1 "PORT" H 6050 2800 30 0000 C CNN
+F 2 "" H 6050 2800 60 0000 C CNN
+F 3 "" H 6050 2800 60 0000 C CNN
+ 7 6050 2800
+ -1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y4.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y4.sub
new file mode 100644
index 000000000..efafa72ed
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y4.sub
@@ -0,0 +1,11 @@
+* Subcircuit Y4
+.subckt Y4 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y4/y4.cir
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* Control Statements
+
+.ends Y4
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y4_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y4_Previous_Values.xml
new file mode 100644
index 000000000..73bfc204a
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y4_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y5-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y5-cache.lib
new file mode 100644
index 000000000..25c3aaccc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y5-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y5.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y5.cir
new file mode 100644
index 000000000..48276daf8
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y5.cir
@@ -0,0 +1,13 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y5/Y5.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 20:21:17 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_U1-Pad6_ Y0
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y5.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y5.cir.out
new file mode 100644
index 000000000..be0c2ec7e
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y5.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y5/y5.cir
+
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y5.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y5.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y5.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y5.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y5.sch
new file mode 100644
index 000000000..1bda8a005
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y5.sch
@@ -0,0 +1,155 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 68693B83
+P 5200 2800
+F 0 "X1" H 5200 2900 60 0000 C CNN
+F 1 "Y0" H 5150 2600 60 0000 C CNN
+F 2 "" H 5200 2800 60 0001 C CNN
+F 3 "" H 5200 2800 60 0001 C CNN
+ 1 5200 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68693C06
+P 6700 4100
+F 0 "scmode1" H 6700 4250 98 0000 C CNB
+F 1 "SKY130mode" H 6700 4000 118 0000 C CNB
+F 2 "" H 6700 4250 60 0001 C CNN
+F 3 "" H 6700 4250 60 0001 C CNN
+ 1 6700 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68693C2D
+P 4400 2700
+F 0 "U1" H 4450 2800 30 0000 C CNN
+F 1 "PORT" H 4400 2700 30 0000 C CNN
+F 2 "" H 4400 2700 60 0000 C CNN
+F 3 "" H 4400 2700 60 0000 C CNN
+ 1 4400 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68693CBD
+P 4400 2800
+F 0 "U1" H 4450 2900 30 0000 C CNN
+F 1 "PORT" H 4400 2800 30 0000 C CNN
+F 2 "" H 4400 2800 60 0000 C CNN
+F 3 "" H 4400 2800 60 0000 C CNN
+ 2 4400 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68693CF0
+P 4400 2900
+F 0 "U1" H 4450 3000 30 0000 C CNN
+F 1 "PORT" H 4400 2900 30 0000 C CNN
+F 2 "" H 4400 2900 60 0000 C CNN
+F 3 "" H 4400 2900 60 0000 C CNN
+ 3 4400 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68693D1D
+P 4950 3150
+F 0 "U1" H 5000 3250 30 0000 C CNN
+F 1 "PORT" H 4950 3150 30 0000 C CNN
+F 2 "" H 4950 3150 60 0000 C CNN
+F 3 "" H 4950 3150 60 0000 C CNN
+ 4 4950 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68693D50
+P 6000 2700
+F 0 "U1" H 6050 2800 30 0000 C CNN
+F 1 "PORT" H 6000 2700 30 0000 C CNN
+F 2 "" H 6000 2700 60 0000 C CNN
+F 3 "" H 6000 2700 60 0000 C CNN
+ 5 6000 2700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68693D9F
+P 6000 2800
+F 0 "U1" H 6050 2900 30 0000 C CNN
+F 1 "PORT" H 6000 2800 30 0000 C CNN
+F 2 "" H 6000 2800 60 0000 C CNN
+F 3 "" H 6000 2800 60 0000 C CNN
+ 6 6000 2800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68693DDE
+P 6000 2900
+F 0 "U1" H 6050 3000 30 0000 C CNN
+F 1 "PORT" H 6000 2900 30 0000 C CNN
+F 2 "" H 6000 2900 60 0000 C CNN
+F 3 "" H 6000 2900 60 0000 C CNN
+ 7 6000 2900
+ -1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y5.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y5.sub
new file mode 100644
index 000000000..0cddbd9e0
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y5.sub
@@ -0,0 +1,11 @@
+* Subcircuit Y5
+.subckt Y5 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y5/y5.cir
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* Control Statements
+
+.ends Y5
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y5_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y5_Previous_Values.xml
new file mode 100644
index 000000000..73bfc204a
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y5_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y6-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y6-cache.lib
new file mode 100644
index 000000000..25c3aaccc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y6-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y6.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y6.cir
new file mode 100644
index 000000000..4306bb477
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y6.cir
@@ -0,0 +1,13 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y6/Y6.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 20:24:47 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_U1-Pad6_ Y0
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y6.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y6.cir.out
new file mode 100644
index 000000000..cfd954565
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y6.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y6/y6.cir
+
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y6.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y6.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y6.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y6.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y6.sch
new file mode 100644
index 000000000..ebd6439df
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y6.sch
@@ -0,0 +1,155 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 68693C8D
+P 5400 2950
+F 0 "X1" H 5400 3050 60 0000 C CNN
+F 1 "Y0" H 5350 2750 60 0000 C CNN
+F 2 "" H 5400 2950 60 0001 C CNN
+F 3 "" H 5400 2950 60 0001 C CNN
+ 1 5400 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68693CCE
+P 7500 4750
+F 0 "scmode1" H 7500 4900 98 0000 C CNB
+F 1 "SKY130mode" H 7500 4650 118 0000 C CNB
+F 2 "" H 7500 4900 60 0001 C CNN
+F 3 "" H 7500 4900 60 0001 C CNN
+ 1 7500 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68693CF3
+P 4600 2850
+F 0 "U1" H 4650 2950 30 0000 C CNN
+F 1 "PORT" H 4600 2850 30 0000 C CNN
+F 2 "" H 4600 2850 60 0000 C CNN
+F 3 "" H 4600 2850 60 0000 C CNN
+ 1 4600 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68693D2E
+P 4600 2950
+F 0 "U1" H 4650 3050 30 0000 C CNN
+F 1 "PORT" H 4600 2950 30 0000 C CNN
+F 2 "" H 4600 2950 60 0000 C CNN
+F 3 "" H 4600 2950 60 0000 C CNN
+ 2 4600 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68693D85
+P 4600 3050
+F 0 "U1" H 4650 3150 30 0000 C CNN
+F 1 "PORT" H 4600 3050 30 0000 C CNN
+F 2 "" H 4600 3050 60 0000 C CNN
+F 3 "" H 4600 3050 60 0000 C CNN
+ 3 4600 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68693DB6
+P 5150 3300
+F 0 "U1" H 5200 3400 30 0000 C CNN
+F 1 "PORT" H 5150 3300 30 0000 C CNN
+F 2 "" H 5150 3300 60 0000 C CNN
+F 3 "" H 5150 3300 60 0000 C CNN
+ 4 5150 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68693DE1
+P 6200 2850
+F 0 "U1" H 6250 2950 30 0000 C CNN
+F 1 "PORT" H 6200 2850 30 0000 C CNN
+F 2 "" H 6200 2850 60 0000 C CNN
+F 3 "" H 6200 2850 60 0000 C CNN
+ 5 6200 2850
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68693E34
+P 6200 2950
+F 0 "U1" H 6250 3050 30 0000 C CNN
+F 1 "PORT" H 6200 2950 30 0000 C CNN
+F 2 "" H 6200 2950 60 0000 C CNN
+F 3 "" H 6200 2950 60 0000 C CNN
+ 6 6200 2950
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68693E67
+P 6200 3050
+F 0 "U1" H 6250 3150 30 0000 C CNN
+F 1 "PORT" H 6200 3050 30 0000 C CNN
+F 2 "" H 6200 3050 60 0000 C CNN
+F 3 "" H 6200 3050 60 0000 C CNN
+ 7 6200 3050
+ -1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y6.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y6.sub
new file mode 100644
index 000000000..e6bd24004
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y6.sub
@@ -0,0 +1,11 @@
+* Subcircuit Y6
+.subckt Y6 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y6/y6.cir
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* Control Statements
+
+.ends Y6
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y6_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y6_Previous_Values.xml
new file mode 100644
index 000000000..d866ca8a0
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y6_Previous_Values.xml
@@ -0,0 +1 @@
+/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y7-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y7-cache.lib
new file mode 100644
index 000000000..25c3aaccc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y7-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y7.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y7.cir
new file mode 100644
index 000000000..aefcdacd5
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y7.cir
@@ -0,0 +1,13 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y7/Y7.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 20:29:26 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_U1-Pad6_ Y0
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y7.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y7.cir.out
new file mode 100644
index 000000000..572724c1d
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y7.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y7/y7.cir
+
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y7.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y7.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y7.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y7.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y7.sch
new file mode 100644
index 000000000..f3a0ae254
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y7.sch
@@ -0,0 +1,155 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 68693DA4
+P 5150 2800
+F 0 "X1" H 5150 2900 60 0000 C CNN
+F 1 "Y0" H 5100 2600 60 0000 C CNN
+F 2 "" H 5150 2800 60 0001 C CNN
+F 3 "" H 5150 2800 60 0001 C CNN
+ 1 5150 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68693DE1
+P 7650 4100
+F 0 "scmode1" H 7650 4250 98 0000 C CNB
+F 1 "SKY130mode" H 7650 4000 118 0000 C CNB
+F 2 "" H 7650 4250 60 0001 C CNN
+F 3 "" H 7650 4250 60 0001 C CNN
+ 1 7650 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68693E14
+P 4350 2700
+F 0 "U1" H 4400 2800 30 0000 C CNN
+F 1 "PORT" H 4350 2700 30 0000 C CNN
+F 2 "" H 4350 2700 60 0000 C CNN
+F 3 "" H 4350 2700 60 0000 C CNN
+ 1 4350 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68693EFE
+P 4350 2800
+F 0 "U1" H 4400 2900 30 0000 C CNN
+F 1 "PORT" H 4350 2800 30 0000 C CNN
+F 2 "" H 4350 2800 60 0000 C CNN
+F 3 "" H 4350 2800 60 0000 C CNN
+ 2 4350 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68693F27
+P 4350 2900
+F 0 "U1" H 4400 3000 30 0000 C CNN
+F 1 "PORT" H 4350 2900 30 0000 C CNN
+F 2 "" H 4350 2900 60 0000 C CNN
+F 3 "" H 4350 2900 60 0000 C CNN
+ 3 4350 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68693F4A
+P 4900 3150
+F 0 "U1" H 4950 3250 30 0000 C CNN
+F 1 "PORT" H 4900 3150 30 0000 C CNN
+F 2 "" H 4900 3150 60 0000 C CNN
+F 3 "" H 4900 3150 60 0000 C CNN
+ 4 4900 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68693F8D
+P 5950 2700
+F 0 "U1" H 6000 2800 30 0000 C CNN
+F 1 "PORT" H 5950 2700 30 0000 C CNN
+F 2 "" H 5950 2700 60 0000 C CNN
+F 3 "" H 5950 2700 60 0000 C CNN
+ 5 5950 2700
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68693FB6
+P 5950 2800
+F 0 "U1" H 6000 2900 30 0000 C CNN
+F 1 "PORT" H 5950 2800 30 0000 C CNN
+F 2 "" H 5950 2800 60 0000 C CNN
+F 3 "" H 5950 2800 60 0000 C CNN
+ 6 5950 2800
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68693FDF
+P 5950 2900
+F 0 "U1" H 6000 3000 30 0000 C CNN
+F 1 "PORT" H 5950 2900 30 0000 C CNN
+F 2 "" H 5950 2900 60 0000 C CNN
+F 3 "" H 5950 2900 60 0000 C CNN
+ 7 5950 2900
+ -1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y7.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y7.sub
new file mode 100644
index 000000000..19b5cc503
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y7.sub
@@ -0,0 +1,11 @@
+* Subcircuit Y7
+.subckt Y7 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y7/y7.cir
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* Control Statements
+
+.ends Y7
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y7_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y7_Previous_Values.xml
new file mode 100644
index 000000000..73bfc204a
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y7_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y8-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y8-cache.lib
new file mode 100644
index 000000000..25c3aaccc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y8-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y8.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y8.cir
new file mode 100644
index 000000000..388978510
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y8.cir
@@ -0,0 +1,13 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y8/Y8.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 20:33:21 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_U1-Pad6_ Y0
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y8.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y8.cir.out
new file mode 100644
index 000000000..b5965c648
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y8.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y8/y8.cir
+
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y8.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y8.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y8.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y8.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y8.sch
new file mode 100644
index 000000000..cee28fe81
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y8.sch
@@ -0,0 +1,155 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 68693E7E
+P 4900 2650
+F 0 "X1" H 4900 2750 60 0000 C CNN
+F 1 "Y0" H 4850 2450 60 0000 C CNN
+F 2 "" H 4900 2650 60 0001 C CNN
+F 3 "" H 4900 2650 60 0001 C CNN
+ 1 4900 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68693ED9
+P 8650 4350
+F 0 "scmode1" H 8650 4500 98 0000 C CNB
+F 1 "SKY130mode" H 8650 4250 118 0000 C CNB
+F 2 "" H 8650 4500 60 0001 C CNN
+F 3 "" H 8650 4500 60 0001 C CNN
+ 1 8650 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68693F20
+P 4100 2550
+F 0 "U1" H 4150 2650 30 0000 C CNN
+F 1 "PORT" H 4100 2550 30 0000 C CNN
+F 2 "" H 4100 2550 60 0000 C CNN
+F 3 "" H 4100 2550 60 0000 C CNN
+ 1 4100 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68693F57
+P 4100 2650
+F 0 "U1" H 4150 2750 30 0000 C CNN
+F 1 "PORT" H 4100 2650 30 0000 C CNN
+F 2 "" H 4100 2650 60 0000 C CNN
+F 3 "" H 4100 2650 60 0000 C CNN
+ 2 4100 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68693F80
+P 4100 2750
+F 0 "U1" H 4150 2850 30 0000 C CNN
+F 1 "PORT" H 4100 2750 30 0000 C CNN
+F 2 "" H 4100 2750 60 0000 C CNN
+F 3 "" H 4100 2750 60 0000 C CNN
+ 3 4100 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68693FAF
+P 4650 3000
+F 0 "U1" H 4700 3100 30 0000 C CNN
+F 1 "PORT" H 4650 3000 30 0000 C CNN
+F 2 "" H 4650 3000 60 0000 C CNN
+F 3 "" H 4650 3000 60 0000 C CNN
+ 4 4650 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68693FE8
+P 5700 2550
+F 0 "U1" H 5750 2650 30 0000 C CNN
+F 1 "PORT" H 5700 2550 30 0000 C CNN
+F 2 "" H 5700 2550 60 0000 C CNN
+F 3 "" H 5700 2550 60 0000 C CNN
+ 5 5700 2550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68694305
+P 5700 2650
+F 0 "U1" H 5750 2750 30 0000 C CNN
+F 1 "PORT" H 5700 2650 30 0000 C CNN
+F 2 "" H 5700 2650 60 0000 C CNN
+F 3 "" H 5700 2650 60 0000 C CNN
+ 6 5700 2650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68694342
+P 5700 2750
+F 0 "U1" H 5750 2850 30 0000 C CNN
+F 1 "PORT" H 5700 2750 30 0000 C CNN
+F 2 "" H 5700 2750 60 0000 C CNN
+F 3 "" H 5700 2750 60 0000 C CNN
+ 7 5700 2750
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y8.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y8.sub
new file mode 100644
index 000000000..b85b7c552
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y8.sub
@@ -0,0 +1,11 @@
+* Subcircuit Y8
+.subckt Y8 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y8/y8.cir
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* Control Statements
+
+.ends Y8
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y8_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y8_Previous_Values.xml
new file mode 100644
index 000000000..73bfc204a
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y8_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y9-cache.lib b/library/SubcircuitLibrary/TC74HC4028AP/Y9-cache.lib
new file mode 100644
index 000000000..25c3aaccc
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y9-cache.lib
@@ -0,0 +1,75 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# SKY130mode
+#
+DEF SKY130mode scmode 0 40 Y Y 1 F N
+F0 "scmode" 0 150 98 H V C CNB
+F1 "SKY130mode" 0 -100 118 H V C CNB
+F2 "" 0 150 60 H I C CNN
+F3 "" 0 150 60 H I C CNN
+DRAW
+S -600 350 600 -350 0 1 79 N
+ENDDRAW
+ENDDEF
+#
+# Y0
+#
+DEF Y0 X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "Y0" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -350 150 350 -150 0 1 0 N
+X A_bar 1 -550 0 200 R 50 50 1 1 I
+X B_bar 2 -550 -100 200 R 50 50 1 1 I
+X Gnd 3 0 -350 200 U 50 50 1 1 I
+X Vdd 4 -550 100 200 R 50 50 1 1 I
+X Y0 5 550 -100 200 L 50 50 1 1 O
+X C_bar 6 550 100 200 L 50 50 1 1 I
+X D_bar 7 550 0 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y9.cir b/library/SubcircuitLibrary/TC74HC4028AP/Y9.cir
new file mode 100644
index 000000000..a2b2c1bac
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y9.cir
@@ -0,0 +1,13 @@
+* /home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y9/Y9.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Sat Jul 5 20:37:19 2025
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad1_ Net-_U1-Pad7_ Net-_U1-Pad5_ Net-_U1-Pad6_ Y0
+scmode1 SKY130mode
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y9.cir.out b/library/SubcircuitLibrary/TC74HC4028AP/Y9.cir.out
new file mode 100644
index 000000000..2ab60d530
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y9.cir.out
@@ -0,0 +1,17 @@
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y9/y9.cir
+
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y9.pro b/library/SubcircuitLibrary/TC74HC4028AP/Y9.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y9.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y9.sch b/library/SubcircuitLibrary/TC74HC4028AP/Y9.sch
new file mode 100644
index 000000000..9102285ea
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y9.sch
@@ -0,0 +1,155 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L Y0 X1
+U 1 1 68693F7B
+P 4700 2550
+F 0 "X1" H 4700 2650 60 0000 C CNN
+F 1 "Y0" H 4650 2350 60 0000 C CNN
+F 2 "" H 4700 2550 60 0001 C CNN
+F 3 "" H 4700 2550 60 0001 C CNN
+ 1 4700 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L SKY130mode scmode1
+U 1 1 68693FB8
+P 8250 3950
+F 0 "scmode1" H 8250 4100 98 0000 C CNB
+F 1 "SKY130mode" H 8250 3850 118 0000 C CNB
+F 2 "" H 8250 4100 60 0001 C CNN
+F 3 "" H 8250 4100 60 0001 C CNN
+ 1 8250 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68693FFF
+P 3900 2450
+F 0 "U1" H 3950 2550 30 0000 C CNN
+F 1 "PORT" H 3900 2450 30 0000 C CNN
+F 2 "" H 3900 2450 60 0000 C CNN
+F 3 "" H 3900 2450 60 0000 C CNN
+ 1 3900 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68694048
+P 3900 2550
+F 0 "U1" H 3950 2650 30 0000 C CNN
+F 1 "PORT" H 3900 2550 30 0000 C CNN
+F 2 "" H 3900 2550 60 0000 C CNN
+F 3 "" H 3900 2550 60 0000 C CNN
+ 2 3900 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6869406D
+P 3900 2650
+F 0 "U1" H 3950 2750 30 0000 C CNN
+F 1 "PORT" H 3900 2650 30 0000 C CNN
+F 2 "" H 3900 2650 60 0000 C CNN
+F 3 "" H 3900 2650 60 0000 C CNN
+ 3 3900 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6869409C
+P 4450 2900
+F 0 "U1" H 4500 3000 30 0000 C CNN
+F 1 "PORT" H 4450 2900 30 0000 C CNN
+F 2 "" H 4450 2900 60 0000 C CNN
+F 3 "" H 4450 2900 60 0000 C CNN
+ 4 4450 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686940CF
+P 5500 2450
+F 0 "U1" H 5550 2550 30 0000 C CNN
+F 1 "PORT" H 5500 2450 30 0000 C CNN
+F 2 "" H 5500 2450 60 0000 C CNN
+F 3 "" H 5500 2450 60 0000 C CNN
+ 5 5500 2450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 68694132
+P 5500 2550
+F 0 "U1" H 5550 2650 30 0000 C CNN
+F 1 "PORT" H 5500 2550 30 0000 C CNN
+F 2 "" H 5500 2550 60 0000 C CNN
+F 3 "" H 5500 2550 60 0000 C CNN
+ 6 5500 2550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 68694173
+P 5500 2650
+F 0 "U1" H 5550 2750 30 0000 C CNN
+F 1 "PORT" H 5500 2650 30 0000 C CNN
+F 2 "" H 5500 2650 60 0000 C CNN
+F 3 "" H 5500 2650 60 0000 C CNN
+ 7 5500 2650
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y9.sub b/library/SubcircuitLibrary/TC74HC4028AP/Y9.sub
new file mode 100644
index 000000000..5449a8396
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y9.sub
@@ -0,0 +1,11 @@
+* Subcircuit Y9
+.subckt Y9 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_
+* /home/vsduser/downloads/esim-2.3/library/subcircuitlibrary/y9/y9.cir
+.include Y0.sub
+*.lib "/usr/share/local/sky130_fd_pr/models/sky130.lib.spice" tt
+
+x1 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad7_ net-_u1-pad5_ net-_u1-pad6_ Y0
+* s c m o d e
+* Control Statements
+
+.ends Y9
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/Y9_Previous_Values.xml b/library/SubcircuitLibrary/TC74HC4028AP/Y9_Previous_Values.xml
new file mode 100644
index 000000000..73bfc204a
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/Y9_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec/usr/share/local/sky130_fd_pr/models/sky130.lib.spicett/home/vsduser/Downloads/eSim-2.3/library/SubcircuitLibrary/Y0
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/TC74HC4028AP/analysis b/library/SubcircuitLibrary/TC74HC4028AP/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/TC74HC4028AP/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/cd4070b_ic/NMOS-180nm.lib b/library/SubcircuitLibrary/cd4070b_ic/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697
++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0
++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3
++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286
++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078
++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/cd4070b_ic/PMOS-180nm.lib b/library/SubcircuitLibrary/cd4070b_ic/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9
++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3
++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/cd4070b_ic/analysis b/library/SubcircuitLibrary/cd4070b_ic/analysis
new file mode 100644
index 000000000..0a6c83b5a
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/analysis
@@ -0,0 +1 @@
+.tran 250e-03 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic-cache.lib b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic-cache.lib
new file mode 100644
index 000000000..6c512720e
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir
new file mode 100644
index 000000000..e9054ad73
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir
@@ -0,0 +1,22 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\cd4070b_ic\cd4070b_ic.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/23/25 22:05:51
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M3 Net-_M11-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M11-Pad1_ eSim_MOS_P
+M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M4 Net-_M11-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad1_ Net-_M11-Pad1_ eSim_MOS_P
+M6 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M10-Pad2_ Net-_M11-Pad1_ eSim_MOS_P
+M5 Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ eSim_MOS_N
+M8 Net-_M11-Pad1_ Net-_M2-Pad1_ Net-_M8-Pad3_ Net-_M11-Pad1_ eSim_MOS_P
+M9 Net-_M8-Pad3_ Net-_M1-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad1_ eSim_MOS_P
+M7 Net-_M10-Pad2_ Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M1-Pad3_ eSim_MOS_N
+M11 Net-_M11-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad1_ Net-_M11-Pad1_ eSim_MOS_P
+M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+U1 Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad2_ Net-_M11-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir.out b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir.out
new file mode 100644
index 000000000..d2d1ea10b
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.cir.out
@@ -0,0 +1,25 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4070b_ic\cd4070b_ic.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m3 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m11-pad1_ net-_m2-pad2_ net-_m2-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m8 net-_m11-pad1_ net-_m2-pad1_ net-_m8-pad3_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m9 net-_m8-pad3_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m7 net-_m10-pad2_ net-_m1-pad1_ net-_m2-pad1_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+* u1 net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m11-pad1_ port
+.tran 250e-03 10e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.pro b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sch b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sch
new file mode 100644
index 000000000..73a3e929e
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sch
@@ -0,0 +1,576 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_N M1
+U 1 1 68597EF6
+P 3200 2650
+F 0 "M1" H 3200 2500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 3300 2600 50 0000 R CNN
+F 2 "" H 3500 2350 29 0000 C CNN
+F 3 "" H 3300 2450 60 0000 C CNN
+ 1 3200 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M3
+U 1 1 68597EF7
+P 3250 2250
+F 0 "M3" H 3200 2300 50 0000 R CNN
+F 1 "eSim_MOS_P" H 3300 2400 50 0000 R CNN
+F 2 "" H 3500 2350 29 0000 C CNN
+F 3 "" H 3300 2250 60 0000 C CNN
+ 1 3250 2250
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 68597EF8
+P 3200 4200
+F 0 "M2" H 3200 4050 50 0000 R CNN
+F 1 "eSim_MOS_N" H 3300 4150 50 0000 R CNN
+F 2 "" H 3500 3900 29 0000 C CNN
+F 3 "" H 3300 4000 60 0000 C CNN
+ 1 3200 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 68597EF9
+P 3250 3800
+F 0 "M4" H 3200 3850 50 0000 R CNN
+F 1 "eSim_MOS_P" H 3300 3950 50 0000 R CNN
+F 2 "" H 3500 3900 29 0000 C CNN
+F 3 "" H 3300 3800 60 0000 C CNN
+ 1 3250 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M6
+U 1 1 68597EFA
+P 5600 3050
+F 0 "M6" H 5550 3100 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5650 3200 50 0000 R CNN
+F 2 "" H 5850 3150 29 0000 C CNN
+F 3 "" H 5650 3050 60 0000 C CNN
+ 1 5600 3050
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 68597EFB
+P 4650 2850
+F 0 "M5" H 4650 2700 50 0000 R CNN
+F 1 "eSim_MOS_N" H 4750 2800 50 0000 R CNN
+F 2 "" H 4950 2550 29 0000 C CNN
+F 3 "" H 4750 2650 60 0000 C CNN
+ 1 4650 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M8
+U 1 1 68597EFC
+P 6700 2350
+F 0 "M8" H 6650 2400 50 0000 R CNN
+F 1 "eSim_MOS_P" H 6750 2500 50 0000 R CNN
+F 2 "" H 6950 2450 29 0000 C CNN
+F 3 "" H 6750 2350 60 0000 C CNN
+ 1 6700 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M9
+U 1 1 68597EFD
+P 6700 3500
+F 0 "M9" H 6650 3550 50 0000 R CNN
+F 1 "eSim_MOS_P" H 6750 3650 50 0000 R CNN
+F 2 "" H 6950 3600 29 0000 C CNN
+F 3 "" H 6750 3500 60 0000 C CNN
+ 1 6700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M7
+U 1 1 68597EFE
+P 6650 3900
+F 0 "M7" H 6650 3750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6750 3850 50 0000 R CNN
+F 2 "" H 6950 3600 29 0000 C CNN
+F 3 "" H 6750 3700 60 0000 C CNN
+ 1 6650 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M11
+U 1 1 68597EFF
+P 8150 2850
+F 0 "M11" H 8100 2900 50 0000 R CNN
+F 1 "eSim_MOS_P" H 8200 3000 50 0000 R CNN
+F 2 "" H 8400 2950 29 0000 C CNN
+F 3 "" H 8200 2850 60 0000 C CNN
+ 1 8150 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 68597F00
+P 8050 3350
+F 0 "M10" H 8050 3200 50 0000 R CNN
+F 1 "eSim_MOS_N" H 8150 3300 50 0000 R CNN
+F 2 "" H 8350 3050 29 0000 C CNN
+F 3 "" H 8150 3150 60 0000 C CNN
+ 1 8050 3350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3400 1550 3400 2050
+Wire Wire Line
+ 3400 1850 3650 1850
+Wire Wire Line
+ 3650 1850 3650 2450
+Wire Wire Line
+ 3650 2450 3500 2450
+Wire Wire Line
+ 3500 2450 3500 2400
+Wire Wire Line
+ 3400 2450 3400 2650
+Wire Wire Line
+ 3400 3050 3400 3200
+Wire Wire Line
+ 2450 3200 3500 3200
+Wire Wire Line
+ 3500 3200 3500 3000
+Wire Wire Line
+ 3100 2250 2750 2250
+Wire Wire Line
+ 2750 2250 2750 2850
+Wire Wire Line
+ 2750 2850 3100 2850
+Wire Wire Line
+ 3500 3950 3500 4000
+Wire Wire Line
+ 3500 4000 3600 4000
+Wire Wire Line
+ 3600 4000 3600 3500
+Wire Wire Line
+ 3600 3500 2350 3500
+Wire Wire Line
+ 3400 3500 3400 3600
+Wire Wire Line
+ 3400 4000 3400 4200
+Wire Wire Line
+ 3400 4600 3400 4700
+Wire Wire Line
+ 3500 4700 3500 4550
+Wire Wire Line
+ 3100 3800 2800 3800
+Wire Wire Line
+ 2800 3800 2800 4400
+Wire Wire Line
+ 2800 4400 3100 4400
+Wire Wire Line
+ 2350 3500 2350 1550
+Connection ~ 3400 3500
+Connection ~ 3400 1850
+Wire Wire Line
+ 4850 3250 4850 3400
+Wire Wire Line
+ 4850 3400 5450 3400
+Wire Wire Line
+ 5450 3400 5450 3250
+Wire Wire Line
+ 2450 4700 2450 3200
+Connection ~ 3400 4700
+Connection ~ 3400 3200
+Wire Wire Line
+ 4550 3050 4550 4100
+Wire Wire Line
+ 3400 4100 5450 4100
+Connection ~ 3400 4100
+Wire Wire Line
+ 4950 4700 4950 3200
+Connection ~ 3500 4700
+Wire Wire Line
+ 4850 2850 4850 2600
+Wire Wire Line
+ 4850 2600 5450 2600
+Wire Wire Line
+ 5450 2600 5450 2850
+Wire Wire Line
+ 3400 2550 6000 2550
+Wire Wire Line
+ 5200 2550 5200 2600
+Connection ~ 5200 2600
+Connection ~ 3400 2550
+Wire Wire Line
+ 5250 3200 5350 3200
+Wire Wire Line
+ 5250 1550 5250 3200
+Connection ~ 3400 1550
+Wire Wire Line
+ 2050 4100 2800 4100
+Wire Wire Line
+ 2600 4100 2600 3450
+Wire Wire Line
+ 2600 3450 5900 3450
+Wire Wire Line
+ 5900 3450 5900 3050
+Wire Wire Line
+ 5900 3050 5750 3050
+Connection ~ 2800 4100
+Wire Wire Line
+ 6550 3500 6200 3500
+Wire Wire Line
+ 6200 3500 6200 4100
+Wire Wire Line
+ 6200 4100 6550 4100
+Wire Wire Line
+ 6000 2550 6000 3750
+Wire Wire Line
+ 6000 3750 6200 3750
+Connection ~ 6200 3750
+Connection ~ 5200 2550
+Wire Wire Line
+ 6550 2350 6050 2350
+Wire Wire Line
+ 6050 2350 6050 4450
+Wire Wire Line
+ 5450 4450 6850 4450
+Wire Wire Line
+ 6850 4450 6850 4300
+Wire Wire Line
+ 5450 4100 5450 4450
+Connection ~ 4550 4100
+Connection ~ 6050 4450
+Wire Wire Line
+ 6950 4700 6950 4250
+Connection ~ 4950 4700
+Wire Wire Line
+ 6850 3700 6850 3900
+Wire Wire Line
+ 6850 2550 6850 3300
+Wire Wire Line
+ 6850 2150 6850 1950
+Wire Wire Line
+ 6850 1950 7250 1950
+Wire Wire Line
+ 7250 1550 7250 3650
+Wire Wire Line
+ 7250 2550 6950 2550
+Wire Wire Line
+ 6950 2550 6950 2500
+Wire Wire Line
+ 7250 3650 6950 3650
+Connection ~ 7250 2550
+Connection ~ 7250 1950
+Connection ~ 5250 1550
+Wire Wire Line
+ 8300 1550 8300 2650
+Connection ~ 7250 1550
+Wire Wire Line
+ 7700 2850 8000 2850
+Wire Wire Line
+ 7700 2850 7700 3550
+Wire Wire Line
+ 7700 3550 7950 3550
+Wire Wire Line
+ 8300 3050 8300 3250
+Wire Wire Line
+ 8250 3250 9700 3250
+Wire Wire Line
+ 8250 3250 8250 3350
+Wire Wire Line
+ 8250 3750 8250 4700
+Wire Wire Line
+ 8250 3900 8350 3900
+Wire Wire Line
+ 8350 3900 8350 3700
+Connection ~ 6950 4700
+Connection ~ 8250 3900
+Wire Wire Line
+ 6850 3800 7550 3800
+Wire Wire Line
+ 7550 3100 7550 4500
+Wire Wire Line
+ 7550 3100 7700 3100
+Connection ~ 7700 3100
+Connection ~ 6850 3800
+Wire Wire Line
+ 8300 2400 8550 2400
+Wire Wire Line
+ 8550 2400 8550 3000
+Wire Wire Line
+ 8550 3000 8400 3000
+Connection ~ 8300 2400
+Wire Wire Line
+ 7550 4500 5100 4500
+Wire Wire Line
+ 5100 4500 5100 3400
+Connection ~ 5100 3400
+Connection ~ 7550 3800
+Connection ~ 2750 2350
+Wire Wire Line
+ 2050 2650 2050 4100
+Connection ~ 2600 4100
+Connection ~ 8300 3250
+Connection ~ 8300 1550
+Wire Wire Line
+ 2350 1550 8300 1550
+Wire Wire Line
+ 2450 4700 10200 4700
+Connection ~ 8250 4700
+$Comp
+L PORT U1
+U 1 1 68598A23
+P 850 3200
+F 0 "U1" H 900 3300 30 0000 C CNN
+F 1 "PORT" H 850 3200 30 0000 C CNN
+F 2 "" H 850 3200 60 0000 C CNN
+F 3 "" H 850 3200 60 0000 C CNN
+ 1 850 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68598ACE
+P 750 1600
+F 0 "U1" H 800 1700 30 0000 C CNN
+F 1 "PORT" H 750 1600 30 0000 C CNN
+F 2 "" H 750 1600 60 0000 C CNN
+F 3 "" H 750 1600 60 0000 C CNN
+ 2 750 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68598B80
+P 9950 3250
+F 0 "U1" H 10000 3350 30 0000 C CNN
+F 1 "PORT" H 9950 3250 30 0000 C CNN
+F 2 "" H 9950 3250 60 0000 C CNN
+F 3 "" H 9950 3250 60 0000 C CNN
+ 3 9950 3250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68598E3D
+P 9950 2950
+F 0 "U1" H 10000 3050 30 0000 C CNN
+F 1 "PORT" H 9950 2950 30 0000 C CNN
+F 2 "" H 9950 2950 60 0000 C CNN
+F 3 "" H 9950 2950 60 0000 C CNN
+ 4 9950 2950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68598EF2
+P 750 1950
+F 0 "U1" H 800 2050 30 0000 C CNN
+F 1 "PORT" H 750 1950 30 0000 C CNN
+F 2 "" H 750 1950 60 0000 C CNN
+F 3 "" H 750 1950 60 0000 C CNN
+ 5 750 1950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685990E3
+P 850 2950
+F 0 "U1" H 900 3050 30 0000 C CNN
+F 1 "PORT" H 850 2950 30 0000 C CNN
+F 2 "" H 850 2950 60 0000 C CNN
+F 3 "" H 850 2950 60 0000 C CNN
+ 6 850 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 68599207
+P 850 3550
+F 0 "U1" H 900 3650 30 0000 C CNN
+F 1 "PORT" H 850 3550 30 0000 C CNN
+F 2 "" H 850 3550 60 0000 C CNN
+F 3 "" H 850 3550 60 0000 C CNN
+ 8 850 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685992D0
+P 750 1300
+F 0 "U1" H 800 1400 30 0000 C CNN
+F 1 "PORT" H 750 1300 30 0000 C CNN
+F 2 "" H 750 1300 60 0000 C CNN
+F 3 "" H 750 1300 60 0000 C CNN
+ 9 750 1300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6859946D
+P 9950 3550
+F 0 "U1" H 10000 3650 30 0000 C CNN
+F 1 "PORT" H 9950 3550 30 0000 C CNN
+F 2 "" H 9950 3550 60 0000 C CNN
+F 3 "" H 9950 3550 60 0000 C CNN
+ 10 9950 3550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6859964A
+P 9950 3800
+F 0 "U1" H 10000 3900 30 0000 C CNN
+F 1 "PORT" H 9950 3800 30 0000 C CNN
+F 2 "" H 9950 3800 60 0000 C CNN
+F 3 "" H 9950 3800 60 0000 C CNN
+ 11 9950 3800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685997A5
+P 750 2200
+F 0 "U1" H 800 2300 30 0000 C CNN
+F 1 "PORT" H 750 2200 30 0000 C CNN
+F 2 "" H 750 2200 60 0000 C CNN
+F 3 "" H 750 2200 60 0000 C CNN
+ 12 750 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6859980E
+P 850 2650
+F 0 "U1" H 900 2750 30 0000 C CNN
+F 1 "PORT" H 850 2650 30 0000 C CNN
+F 2 "" H 850 2650 60 0000 C CNN
+F 3 "" H 850 2650 60 0000 C CNN
+ 13 850 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 68599873
+P 5000 1150
+F 0 "U1" H 5050 1250 30 0000 C CNN
+F 1 "PORT" H 5000 1150 30 0000 C CNN
+F 2 "" H 5000 1150 60 0000 C CNN
+F 3 "" H 5000 1150 60 0000 C CNN
+ 14 5000 1150
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 5000 1400 5000 1550
+Connection ~ 5000 1550
+Wire Wire Line
+ 2750 2350 1000 2350
+Wire Wire Line
+ 1000 2350 1000 2200
+Wire Wire Line
+ 1000 1300 1650 1300
+Wire Wire Line
+ 1650 1300 1650 2350
+Connection ~ 1650 2350
+Wire Wire Line
+ 1000 1600 1550 1600
+Wire Wire Line
+ 1550 1600 1550 2350
+Connection ~ 1550 2350
+Wire Wire Line
+ 1000 1950 1350 1950
+Wire Wire Line
+ 1350 1950 1350 2350
+Connection ~ 1350 2350
+Wire Wire Line
+ 1100 3550 2050 3550
+Connection ~ 2050 3550
+Wire Wire Line
+ 1100 3200 2050 3200
+Wire Wire Line
+ 1100 2950 2050 2950
+Connection ~ 2050 3200
+Wire Wire Line
+ 1100 2650 2050 2650
+Connection ~ 2050 2950
+Wire Wire Line
+ 9700 2950 9600 2950
+Wire Wire Line
+ 9600 2950 9600 3250
+Connection ~ 9600 3250
+Wire Wire Line
+ 9700 3550 9450 3550
+Wire Wire Line
+ 9450 3550 9450 3250
+Connection ~ 9450 3250
+Wire Wire Line
+ 9700 3800 9300 3800
+Wire Wire Line
+ 9300 3800 9300 3250
+Connection ~ 9300 3250
+$Comp
+L PORT U1
+U 7 1 6859A8A9
+P 10450 4700
+F 0 "U1" H 10500 4800 30 0000 C CNN
+F 1 "PORT" H 10450 4700 30 0000 C CNN
+F 2 "" H 10450 4700 60 0000 C CNN
+F 3 "" H 10450 4700 60 0000 C CNN
+ 7 10450 4700
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sub b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sub
new file mode 100644
index 000000000..cbfbe6eae
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic.sub
@@ -0,0 +1,19 @@
+* Subcircuit cd4070b_ic
+.subckt cd4070b_ic net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m11-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\cd4070b_ic\cd4070b_ic.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m3 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m11-pad1_ net-_m2-pad2_ net-_m2-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m8 net-_m11-pad1_ net-_m2-pad1_ net-_m8-pad3_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m9 net-_m8-pad3_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m7 net-_m10-pad2_ net-_m1-pad1_ net-_m2-pad1_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+* Control Statements
+
+.ends cd4070b_ic
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic_Previous_Values.xml b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic_Previous_Values.xml
new file mode 100644
index 000000000..025477594
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4070b_ic/cd4070b_ic_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/cd4077b/NMOS-180nm.lib b/library/SubcircuitLibrary/cd4077b/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697
++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0
++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3
++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286
++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078
++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/cd4077b/PMOS-180nm.lib b/library/SubcircuitLibrary/cd4077b/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9
++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3
++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/SubcircuitLibrary/cd4077b/analysis b/library/SubcircuitLibrary/cd4077b/analysis
new file mode 100644
index 000000000..0a6c83b5a
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/analysis
@@ -0,0 +1 @@
+.tran 250e-03 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b-cache.lib b/library/SubcircuitLibrary/cd4077b/cd4077b-cache.lib
new file mode 100644
index 000000000..6c512720e
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/cd4077b-cache.lib
@@ -0,0 +1,100 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_P
+#
+DEF eSim_MOS_P M 0 0 Y N 1 F N
+F0 "M" -50 50 50 H V R CNN
+F1 "eSim_MOS_P" 50 150 50 H V R CNN
+F2 "" 250 100 29 H V C CNN
+F3 "" 50 0 60 H V C CNN
+ALIAS mosfet_p
+DRAW
+C 100 0 111 0 1 10 N
+P 2 0 1 0 80 -70 150 -70 N
+P 2 0 1 10 80 -50 80 -90 N
+P 2 0 1 0 80 0 150 0 N
+P 2 0 1 10 80 20 80 -20 N
+P 2 0 1 0 80 70 150 70 N
+P 2 0 1 10 80 90 80 50 N
+P 2 0 1 0 150 -70 150 -100 N
+P 2 0 1 0 150 100 150 70 N
+P 3 0 1 10 60 75 60 -75 60 -75 N
+P 3 0 1 0 150 0 250 0 250 -50 N
+P 4 0 1 0 140 0 100 -15 100 15 140 0 F
+X D 1 150 200 100 D 50 50 1 1 P
+X G 2 -150 0 210 R 50 50 1 1 P
+X S 3 150 -200 100 U 50 50 1 1 P
+X B 4 250 -150 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.cir b/library/SubcircuitLibrary/cd4077b/cd4077b.cir
new file mode 100644
index 000000000..7be5bf486
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/cd4077b.cir
@@ -0,0 +1,22 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\cd4077b\cd4077b.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/24/25 14:56:23
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M3 Net-_M11-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad1_ Net-_M11-Pad1_ eSim_MOS_P
+M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M4 Net-_M11-Pad1_ Net-_M2-Pad2_ Net-_M2-Pad1_ Net-_M11-Pad1_ eSim_MOS_P
+M6 Net-_M1-Pad1_ Net-_M2-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad1_ eSim_MOS_P
+M5 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M10-Pad2_ Net-_M1-Pad3_ eSim_MOS_N
+M7 Net-_M10-Pad2_ Net-_M1-Pad1_ Net-_M7-Pad3_ Net-_M7-Pad3_ eSim_MOS_N
+M9 Net-_M2-Pad1_ Net-_M1-Pad1_ Net-_M10-Pad2_ Net-_M11-Pad1_ eSim_MOS_P
+M8 Net-_M7-Pad3_ Net-_M2-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M10 Net-_M10-Pad1_ Net-_M10-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N
+M11 Net-_M11-Pad1_ Net-_M10-Pad2_ Net-_M10-Pad1_ Net-_M11-Pad1_ eSim_MOS_P
+U1 Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M10-Pad1_ Net-_M10-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad2_ Net-_M11-Pad1_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.cir.out b/library/SubcircuitLibrary/cd4077b/cd4077b.cir.out
new file mode 100644
index 000000000..fc6467d62
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/cd4077b.cir.out
@@ -0,0 +1,25 @@
+* c:\fossee\esim\library\subcircuitlibrary\cd4077b\cd4077b.cir
+
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m3 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m11-pad1_ net-_m2-pad2_ net-_m2-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m7 net-_m10-pad2_ net-_m1-pad1_ net-_m7-pad3_ net-_m7-pad3_ CMOSN W=100u L=100u M=1
+m9 net-_m2-pad1_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m8 net-_m7-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+* u1 net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m11-pad1_ port
+.tran 250e-03 10e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.pro b/library/SubcircuitLibrary/cd4077b/cd4077b.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/cd4077b.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.sch b/library/SubcircuitLibrary/cd4077b/cd4077b.sch
new file mode 100644
index 000000000..6cbc04bf3
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/cd4077b.sch
@@ -0,0 +1,555 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_MOS_N M1
+U 1 1 685A6E8E
+P 3050 2900
+F 0 "M1" H 3050 2750 50 0000 R CNN
+F 1 "eSim_MOS_N" H 3150 2850 50 0000 R CNN
+F 2 "" H 3350 2600 29 0000 C CNN
+F 3 "" H 3150 2700 60 0000 C CNN
+ 1 3050 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M3
+U 1 1 685A6E8F
+P 3100 2400
+F 0 "M3" H 3050 2450 50 0000 R CNN
+F 1 "eSim_MOS_P" H 3150 2550 50 0000 R CNN
+F 2 "" H 3350 2500 29 0000 C CNN
+F 3 "" H 3150 2400 60 0000 C CNN
+ 1 3100 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M2
+U 1 1 685A6E90
+P 3050 4350
+F 0 "M2" H 3050 4200 50 0000 R CNN
+F 1 "eSim_MOS_N" H 3150 4300 50 0000 R CNN
+F 2 "" H 3350 4050 29 0000 C CNN
+F 3 "" H 3150 4150 60 0000 C CNN
+ 1 3050 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M4
+U 1 1 685A6E91
+P 3100 3850
+F 0 "M4" H 3050 3900 50 0000 R CNN
+F 1 "eSim_MOS_P" H 3150 4000 50 0000 R CNN
+F 2 "" H 3350 3950 29 0000 C CNN
+F 3 "" H 3150 3850 60 0000 C CNN
+ 1 3100 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M6
+U 1 1 685A6E92
+P 5500 3250
+F 0 "M6" H 5450 3300 50 0000 R CNN
+F 1 "eSim_MOS_P" H 5550 3400 50 0000 R CNN
+F 2 "" H 5750 3350 29 0000 C CNN
+F 3 "" H 5550 3250 60 0000 C CNN
+ 1 5500 3250
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 685A6E93
+P 4650 3050
+F 0 "M5" H 4650 2900 50 0000 R CNN
+F 1 "eSim_MOS_N" H 4750 3000 50 0000 R CNN
+F 2 "" H 4950 2750 29 0000 C CNN
+F 3 "" H 4750 2850 60 0000 C CNN
+ 1 4650 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M7
+U 1 1 685A6E94
+P 6750 2750
+F 0 "M7" H 6750 2600 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6850 2700 50 0000 R CNN
+F 2 "" H 7050 2450 29 0000 C CNN
+F 3 "" H 6850 2550 60 0000 C CNN
+ 1 6750 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M9
+U 1 1 685A6E95
+P 6800 2350
+F 0 "M9" H 6750 2400 50 0000 R CNN
+F 1 "eSim_MOS_P" H 6850 2500 50 0000 R CNN
+F 2 "" H 7050 2450 29 0000 C CNN
+F 3 "" H 6850 2350 60 0000 C CNN
+ 1 6800 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M8
+U 1 1 685A6E96
+P 6750 3700
+F 0 "M8" H 6750 3550 50 0000 R CNN
+F 1 "eSim_MOS_N" H 6850 3650 50 0000 R CNN
+F 2 "" H 7050 3400 29 0000 C CNN
+F 3 "" H 6850 3500 60 0000 C CNN
+ 1 6750 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M10
+U 1 1 685A6E97
+P 8150 3150
+F 0 "M10" H 8150 3000 50 0000 R CNN
+F 1 "eSim_MOS_N" H 8250 3100 50 0000 R CNN
+F 2 "" H 8450 2850 29 0000 C CNN
+F 3 "" H 8250 2950 60 0000 C CNN
+ 1 8150 3150
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_P M11
+U 1 1 685A6E98
+P 8200 2600
+F 0 "M11" H 8150 2650 50 0000 R CNN
+F 1 "eSim_MOS_P" H 8250 2750 50 0000 R CNN
+F 2 "" H 8450 2700 29 0000 C CNN
+F 3 "" H 8250 2600 60 0000 C CNN
+ 1 8200 2600
+ 1 0 0 -1
+$EndComp
+Connection ~ 5050 2750
+Connection ~ 6350 2750
+Wire Wire Line
+ 6350 2950 6650 2950
+Wire Wire Line
+ 6350 2350 6350 2950
+Wire Wire Line
+ 6650 2350 6350 2350
+Connection ~ 6200 4200
+Wire Wire Line
+ 6650 4200 6650 3900
+Connection ~ 5850 4200
+Connection ~ 3250 4200
+Wire Wire Line
+ 5850 3250 5650 3250
+Wire Wire Line
+ 5850 4200 5850 3250
+Wire Wire Line
+ 3250 4200 6650 4200
+Connection ~ 2600 4200
+Wire Wire Line
+ 4550 3450 4550 3250
+Wire Wire Line
+ 2350 3450 4550 3450
+Wire Wire Line
+ 2350 4200 2350 3450
+Wire Wire Line
+ 1650 4200 2600 4200
+Connection ~ 3450 2100
+Wire Wire Line
+ 5150 3450 5150 2100
+Wire Wire Line
+ 5250 3450 5150 3450
+Wire Wire Line
+ 5250 3400 5250 3450
+Connection ~ 3350 4850
+Wire Wire Line
+ 4950 4850 4950 3400
+Connection ~ 3250 2750
+Connection ~ 5050 2850
+Wire Wire Line
+ 5050 2750 5050 2850
+Wire Wire Line
+ 3250 2750 6350 2750
+Wire Wire Line
+ 5350 3650 5350 3450
+Wire Wire Line
+ 4850 3650 5350 3650
+Wire Wire Line
+ 4850 3450 4850 3650
+Wire Wire Line
+ 5350 2850 5350 3050
+Wire Wire Line
+ 4850 2850 5350 2850
+Wire Wire Line
+ 4850 3050 4850 2850
+Connection ~ 3250 3400
+Connection ~ 3250 4850
+Wire Wire Line
+ 2400 3400 2400 4850
+Connection ~ 3250 3550
+Connection ~ 3250 2100
+Wire Wire Line
+ 2300 3550 2300 2100
+Wire Wire Line
+ 2600 4550 2950 4550
+Wire Wire Line
+ 2600 3850 2600 4550
+Wire Wire Line
+ 2950 3850 2600 3850
+Wire Wire Line
+ 3350 4850 3350 4700
+Wire Wire Line
+ 2400 4850 8350 4850
+Wire Wire Line
+ 3250 4750 3250 4850
+Wire Wire Line
+ 3250 3550 3250 3650
+Wire Wire Line
+ 3450 3550 2300 3550
+Wire Wire Line
+ 3450 4100 3450 3550
+Wire Wire Line
+ 3350 4100 3450 4100
+Wire Wire Line
+ 3350 4000 3350 4100
+Wire Wire Line
+ 3250 4050 3250 4350
+Wire Wire Line
+ 2600 3100 2950 3100
+Wire Wire Line
+ 2600 2400 2600 3100
+Wire Wire Line
+ 2950 2400 2600 2400
+Wire Wire Line
+ 3350 3400 3350 3250
+Wire Wire Line
+ 2400 3400 3350 3400
+Wire Wire Line
+ 3250 3300 3250 3400
+Wire Wire Line
+ 3250 2100 3250 2200
+Wire Wire Line
+ 3450 2650 3450 2100
+Wire Wire Line
+ 3350 2650 3450 2650
+Wire Wire Line
+ 3350 2550 3350 2650
+Wire Wire Line
+ 3250 2600 3250 2900
+Wire Wire Line
+ 6950 2150 6950 1950
+Wire Wire Line
+ 6950 1950 6200 1950
+Wire Wire Line
+ 6200 1950 6200 4200
+Wire Wire Line
+ 6950 2550 6950 2750
+Wire Wire Line
+ 6950 3150 6950 3700
+Wire Wire Line
+ 8350 2800 8350 3150
+Wire Wire Line
+ 8450 2750 8600 2750
+Wire Wire Line
+ 8350 2100 8350 2400
+Wire Wire Line
+ 8350 4850 8350 3550
+Wire Wire Line
+ 8350 3700 8450 3700
+Wire Wire Line
+ 8450 3700 8450 3500
+Wire Wire Line
+ 8050 2600 7700 2600
+Wire Wire Line
+ 7700 2600 7700 3350
+Wire Wire Line
+ 7700 3350 8050 3350
+Connection ~ 5150 2100
+Wire Wire Line
+ 8600 2750 8600 2100
+Connection ~ 8350 2100
+Connection ~ 4950 4850
+Connection ~ 8350 3700
+Wire Wire Line
+ 6950 4100 6950 4850
+Wire Wire Line
+ 6950 4250 7050 4250
+Wire Wire Line
+ 7050 4250 7050 4050
+Connection ~ 6950 4850
+Connection ~ 6950 4250
+Wire Wire Line
+ 7050 3100 7050 3300
+Wire Wire Line
+ 7050 3300 6950 3300
+Connection ~ 6950 3300
+Wire Wire Line
+ 7050 2500 7250 2500
+Wire Wire Line
+ 7250 2500 7250 2100
+Connection ~ 7250 2100
+Wire Wire Line
+ 5100 3650 5100 4500
+Wire Wire Line
+ 5100 4500 7400 4500
+Wire Wire Line
+ 7400 4500 7400 2650
+Wire Wire Line
+ 7400 2650 6950 2650
+Connection ~ 6950 2650
+Connection ~ 5100 3650
+Wire Wire Line
+ 7400 3000 7700 3000
+Connection ~ 7700 3000
+Connection ~ 7400 3000
+Connection ~ 2600 2750
+Connection ~ 2350 4200
+Connection ~ 8600 2100
+Wire Wire Line
+ 5650 5150 5650 4850
+Connection ~ 5650 4850
+Wire Wire Line
+ 1300 2750 2600 2750
+Wire Wire Line
+ 8350 2950 9450 2950
+Connection ~ 8350 2950
+Wire Wire Line
+ 2300 2100 10200 2100
+$Comp
+L PORT U1
+U 1 1 685A74DB
+P 1400 4200
+F 0 "U1" H 1450 4300 30 0000 C CNN
+F 1 "PORT" H 1400 4200 30 0000 C CNN
+F 2 "" H 1400 4200 60 0000 C CNN
+F 3 "" H 1400 4200 60 0000 C CNN
+ 1 1400 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 685A754E
+P 1050 2750
+F 0 "U1" H 1100 2850 30 0000 C CNN
+F 1 "PORT" H 1050 2750 30 0000 C CNN
+F 2 "" H 1050 2750 60 0000 C CNN
+F 3 "" H 1050 2750 60 0000 C CNN
+ 2 1050 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 685A767B
+P 9700 2950
+F 0 "U1" H 9750 3050 30 0000 C CNN
+F 1 "PORT" H 9700 2950 30 0000 C CNN
+F 2 "" H 9700 2950 60 0000 C CNN
+F 3 "" H 9700 2950 60 0000 C CNN
+ 3 9700 2950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 685A7834
+P 9700 3200
+F 0 "U1" H 9750 3300 30 0000 C CNN
+F 1 "PORT" H 9700 3200 30 0000 C CNN
+F 2 "" H 9700 3200 60 0000 C CNN
+F 3 "" H 9700 3200 60 0000 C CNN
+ 4 9700 3200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 685A7930
+P 1050 2400
+F 0 "U1" H 1100 2500 30 0000 C CNN
+F 1 "PORT" H 1050 2400 30 0000 C CNN
+F 2 "" H 1050 2400 60 0000 C CNN
+F 3 "" H 1050 2400 60 0000 C CNN
+ 5 1050 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 685A796D
+P 1400 3900
+F 0 "U1" H 1450 4000 30 0000 C CNN
+F 1 "PORT" H 1400 3900 30 0000 C CNN
+F 2 "" H 1400 3900 60 0000 C CNN
+F 3 "" H 1400 3900 60 0000 C CNN
+ 6 1400 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 685A7A53
+P 5650 5400
+F 0 "U1" H 5700 5500 30 0000 C CNN
+F 1 "PORT" H 5650 5400 30 0000 C CNN
+F 2 "" H 5650 5400 60 0000 C CNN
+F 3 "" H 5650 5400 60 0000 C CNN
+ 7 5650 5400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 8 1 685A7C28
+P 1400 4500
+F 0 "U1" H 1450 4600 30 0000 C CNN
+F 1 "PORT" H 1400 4500 30 0000 C CNN
+F 2 "" H 1400 4500 60 0000 C CNN
+F 3 "" H 1400 4500 60 0000 C CNN
+ 8 1400 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 685A7DF4
+P 1050 2950
+F 0 "U1" H 1100 3050 30 0000 C CNN
+F 1 "PORT" H 1050 2950 30 0000 C CNN
+F 2 "" H 1050 2950 60 0000 C CNN
+F 3 "" H 1050 2950 60 0000 C CNN
+ 9 1050 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 685A7E75
+P 9700 3450
+F 0 "U1" H 9750 3550 30 0000 C CNN
+F 1 "PORT" H 9700 3450 30 0000 C CNN
+F 2 "" H 9700 3450 60 0000 C CNN
+F 3 "" H 9700 3450 60 0000 C CNN
+ 10 9700 3450
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 685A80FC
+P 9700 3650
+F 0 "U1" H 9750 3750 30 0000 C CNN
+F 1 "PORT" H 9700 3650 30 0000 C CNN
+F 2 "" H 9700 3650 60 0000 C CNN
+F 3 "" H 9700 3650 60 0000 C CNN
+ 11 9700 3650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 685A814D
+P 1050 2150
+F 0 "U1" H 1100 2250 30 0000 C CNN
+F 1 "PORT" H 1050 2150 30 0000 C CNN
+F 2 "" H 1050 2150 60 0000 C CNN
+F 3 "" H 1050 2150 60 0000 C CNN
+ 12 1050 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 685A83A6
+P 1400 3650
+F 0 "U1" H 1450 3750 30 0000 C CNN
+F 1 "PORT" H 1400 3650 30 0000 C CNN
+F 2 "" H 1400 3650 60 0000 C CNN
+F 3 "" H 1400 3650 60 0000 C CNN
+ 13 1400 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 685A84E7
+P 10450 2100
+F 0 "U1" H 10500 2200 30 0000 C CNN
+F 1 "PORT" H 10450 2100 30 0000 C CNN
+F 2 "" H 10450 2100 60 0000 C CNN
+F 3 "" H 10450 2100 60 0000 C CNN
+ 14 10450 2100
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 9450 3200 9350 3200
+Wire Wire Line
+ 9350 3200 9350 2950
+Connection ~ 9350 2950
+Wire Wire Line
+ 9450 3450 9200 3450
+Wire Wire Line
+ 9200 3450 9200 2950
+Connection ~ 9200 2950
+Wire Wire Line
+ 9450 3650 9050 3650
+Wire Wire Line
+ 9050 3650 9050 2950
+Connection ~ 9050 2950
+Wire Wire Line
+ 1300 2150 1500 2150
+Wire Wire Line
+ 1500 2150 1500 2950
+Wire Wire Line
+ 1300 2400 1500 2400
+Connection ~ 1500 2400
+Connection ~ 1500 2750
+Wire Wire Line
+ 1500 2950 1300 2950
+Wire Wire Line
+ 1650 3650 1900 3650
+Wire Wire Line
+ 1900 3650 1900 4500
+Wire Wire Line
+ 1650 3900 1900 3900
+Connection ~ 1900 3900
+Connection ~ 1900 4200
+Wire Wire Line
+ 1900 4500 1650 4500
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b.sub b/library/SubcircuitLibrary/cd4077b/cd4077b.sub
new file mode 100644
index 000000000..183a479ea
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/cd4077b.sub
@@ -0,0 +1,19 @@
+* Subcircuit cd4077b
+.subckt cd4077b net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad2_ net-_m10-pad1_ net-_m10-pad1_ net-_m1-pad2_ net-_m2-pad2_ net-_m11-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\cd4077b\cd4077b.cir
+.include NMOS-180nm.lib
+.include PMOS-180nm.lib
+m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m3 net-_m11-pad1_ net-_m1-pad2_ net-_m1-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m4 net-_m11-pad1_ net-_m2-pad2_ net-_m2-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m6 net-_m1-pad1_ net-_m2-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m5 net-_m1-pad1_ net-_m2-pad2_ net-_m10-pad2_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m7 net-_m10-pad2_ net-_m1-pad1_ net-_m7-pad3_ net-_m7-pad3_ CMOSN W=100u L=100u M=1
+m9 net-_m2-pad1_ net-_m1-pad1_ net-_m10-pad2_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+m8 net-_m7-pad3_ net-_m2-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m10 net-_m10-pad1_ net-_m10-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad1_ net-_m11-pad1_ CMOSP W=100u L=100u M=1
+* Control Statements
+
+.ends cd4077b
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/cd4077b/cd4077b_Previous_Values.xml b/library/SubcircuitLibrary/cd4077b/cd4077b_Previous_Values.xml
new file mode 100644
index 000000000..e8d19e0d7
--- /dev/null
+++ b/library/SubcircuitLibrary/cd4077b/cd4077b_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dff/analysis b/library/SubcircuitLibrary/dff/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/dff/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dff/dff-cache.lib b/library/SubcircuitLibrary/dff/dff-cache.lib
new file mode 100644
index 000000000..440552005
--- /dev/null
+++ b/library/SubcircuitLibrary/dff/dff-cache.lib
@@ -0,0 +1,92 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/dff/dff.cir b/library/SubcircuitLibrary/dff/dff.cir
new file mode 100644
index 000000000..883325a5e
--- /dev/null
+++ b/library/SubcircuitLibrary/dff/dff.cir
@@ -0,0 +1,18 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\dff\dff.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 11:41:14
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_nand
+U4 Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_U4-Pad3_ d_nand
+U5 Net-_U2-Pad6_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_and
+U6 Net-_U4-Pad3_ Net-_U2-Pad3_ Net-_U6-Pad3_ d_and
+U7 Net-_U2-Pad4_ Net-_U5-Pad3_ Net-_U2-Pad5_ d_nand
+U8 Net-_U2-Pad5_ Net-_U6-Pad3_ Net-_U2-Pad4_ d_nand
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/dff/dff.cir.out b/library/SubcircuitLibrary/dff/dff.cir.out
new file mode 100644
index 000000000..849212938
--- /dev/null
+++ b/library/SubcircuitLibrary/dff/dff.cir.out
@@ -0,0 +1,40 @@
+* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir
+
+* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand
+* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and
+* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand
+* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port
+a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6
+a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7
+a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8
+a7 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/dff/dff.pro b/library/SubcircuitLibrary/dff/dff.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/dff/dff.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/dff/dff.sch b/library/SubcircuitLibrary/dff/dff.sch
new file mode 100644
index 000000000..675737646
--- /dev/null
+++ b/library/SubcircuitLibrary/dff/dff.sch
@@ -0,0 +1,273 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nand U3
+U 1 1 6851060F
+P 3700 2300
+F 0 "U3" H 3700 2300 60 0000 C CNN
+F 1 "d_nand" H 3750 2400 60 0000 C CNN
+F 2 "" H 3700 2300 60 0000 C CNN
+F 3 "" H 3700 2300 60 0000 C CNN
+ 1 3700 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 68510656
+P 3700 3300
+F 0 "U4" H 3700 3300 60 0000 C CNN
+F 1 "d_nand" H 3750 3400 60 0000 C CNN
+F 2 "" H 3700 3300 60 0000 C CNN
+F 3 "" H 3700 3300 60 0000 C CNN
+ 1 3700 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 68510666
+P 5400 2300
+F 0 "U5" H 5400 2300 60 0000 C CNN
+F 1 "d_and" H 5450 2400 60 0000 C CNN
+F 2 "" H 5400 2300 60 0000 C CNN
+F 3 "" H 5400 2300 60 0000 C CNN
+ 1 5400 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U6
+U 1 1 685106C5
+P 5400 3300
+F 0 "U6" H 5400 3300 60 0000 C CNN
+F 1 "d_and" H 5450 3400 60 0000 C CNN
+F 2 "" H 5400 3300 60 0000 C CNN
+F 3 "" H 5400 3300 60 0000 C CNN
+ 1 5400 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U7
+U 1 1 685106D1
+P 7100 2300
+F 0 "U7" H 7100 2300 60 0000 C CNN
+F 1 "d_nand" H 7150 2400 60 0000 C CNN
+F 2 "" H 7100 2300 60 0000 C CNN
+F 3 "" H 7100 2300 60 0000 C CNN
+ 1 7100 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U8
+U 1 1 68510816
+P 7150 3300
+F 0 "U8" H 7150 3300 60 0000 C CNN
+F 1 "d_nand" H 7200 3400 60 0000 C CNN
+F 2 "" H 7150 3300 60 0000 C CNN
+F 3 "" H 7150 3300 60 0000 C CNN
+ 1 7150 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5850 3250 6150 3250
+Wire Wire Line
+ 6150 3250 6150 3300
+Wire Wire Line
+ 6150 3300 6700 3300
+Wire Wire Line
+ 5850 2250 6050 2250
+Wire Wire Line
+ 6050 2250 6050 2300
+Wire Wire Line
+ 6050 2300 6650 2300
+Wire Wire Line
+ 7550 2250 8000 2250
+Wire Wire Line
+ 7600 3250 8150 3250
+Wire Wire Line
+ 4950 2200 4750 2200
+Wire Wire Line
+ 4750 2200 4750 1750
+Wire Wire Line
+ 4950 3300 4750 3300
+Wire Wire Line
+ 4750 3300 4750 3800
+Wire Wire Line
+ 4150 3250 4500 3250
+Wire Wire Line
+ 4500 3250 4500 3200
+Wire Wire Line
+ 4500 3200 4950 3200
+Wire Wire Line
+ 4150 2250 4400 2250
+Wire Wire Line
+ 4400 2250 4400 2300
+Wire Wire Line
+ 4400 2300 4950 2300
+Wire Wire Line
+ 7850 2250 7850 2600
+Wire Wire Line
+ 7850 2600 6450 2600
+Wire Wire Line
+ 6450 2600 6450 3200
+Wire Wire Line
+ 6450 3200 6700 3200
+Connection ~ 7850 2250
+Wire Wire Line
+ 7750 3250 7750 2750
+Wire Wire Line
+ 7750 2750 6250 2750
+Wire Wire Line
+ 6250 2750 6250 2200
+Wire Wire Line
+ 6250 2200 6650 2200
+Connection ~ 7750 3250
+Wire Wire Line
+ 3250 2200 2100 2200
+Wire Wire Line
+ 3250 2300 3000 2300
+Wire Wire Line
+ 3000 2300 3000 3200
+Wire Wire Line
+ 3000 3200 3250 3200
+Wire Wire Line
+ 2300 2200 2300 3300
+Connection ~ 2300 2200
+$Comp
+L d_inverter U1
+U 1 1 68510965
+P 2700 3300
+F 0 "U1" H 2700 3200 60 0000 C CNN
+F 1 "d_inverter" H 2700 3450 60 0000 C CNN
+F 2 "" H 2750 3250 60 0000 C CNN
+F 3 "" H 2750 3250 60 0000 C CNN
+ 1 2700 3300
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3000 3300 3250 3300
+Wire Wire Line
+ 2300 3300 2400 3300
+Wire Wire Line
+ 3000 2750 1950 2750
+Wire Wire Line
+ 1950 2750 1950 3750
+Connection ~ 3000 2750
+$Comp
+L PORT U2
+U 1 1 68510A2C
+P 1850 2200
+F 0 "U2" H 1900 2300 30 0000 C CNN
+F 1 "PORT" H 1850 2200 30 0000 C CNN
+F 2 "" H 1850 2200 60 0000 C CNN
+F 3 "" H 1850 2200 60 0000 C CNN
+ 1 1850 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 2 1 68510A87
+P 1700 3750
+F 0 "U2" H 1750 3850 30 0000 C CNN
+F 1 "PORT" H 1700 3750 30 0000 C CNN
+F 2 "" H 1700 3750 60 0000 C CNN
+F 3 "" H 1700 3750 60 0000 C CNN
+ 2 1700 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 3 1 68510ACA
+P 4500 3800
+F 0 "U2" H 4550 3900 30 0000 C CNN
+F 1 "PORT" H 4500 3800 30 0000 C CNN
+F 2 "" H 4500 3800 60 0000 C CNN
+F 3 "" H 4500 3800 60 0000 C CNN
+ 3 4500 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 5 1 68510AFD
+P 8000 2500
+F 0 "U2" H 8050 2600 30 0000 C CNN
+F 1 "PORT" H 8000 2500 30 0000 C CNN
+F 2 "" H 8000 2500 60 0000 C CNN
+F 3 "" H 8000 2500 60 0000 C CNN
+ 5 8000 2500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 4 1 68510B2C
+P 8150 3500
+F 0 "U2" H 8200 3600 30 0000 C CNN
+F 1 "PORT" H 8150 3500 30 0000 C CNN
+F 2 "" H 8150 3500 60 0000 C CNN
+F 3 "" H 8150 3500 60 0000 C CNN
+ 4 8150 3500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 6 1 68510B5D
+P 4500 1750
+F 0 "U2" H 4550 1850 30 0000 C CNN
+F 1 "PORT" H 4500 1750 30 0000 C CNN
+F 2 "" H 4500 1750 60 0000 C CNN
+F 3 "" H 4500 1750 60 0000 C CNN
+ 6 4500 1750
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/dff/dff.sub b/library/SubcircuitLibrary/dff/dff.sub
new file mode 100644
index 000000000..885e878fc
--- /dev/null
+++ b/library/SubcircuitLibrary/dff/dff.sub
@@ -0,0 +1,34 @@
+* Subcircuit dff
+.subckt dff net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_
+* d:\fossee\esim\library\subcircuitlibrary\dff\dff.cir
+* u3 net-_u1-pad1_ net-_u2-pad2_ net-_u3-pad3_ d_nand
+* u4 net-_u2-pad2_ net-_u1-pad2_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad6_ net-_u3-pad3_ net-_u5-pad3_ d_and
+* u6 net-_u4-pad3_ net-_u2-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u2-pad4_ net-_u5-pad3_ net-_u2-pad5_ d_nand
+* u8 net-_u2-pad5_ net-_u6-pad3_ net-_u2-pad4_ d_nand
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+a1 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u2-pad6_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a4 [net-_u4-pad3_ net-_u2-pad3_ ] net-_u6-pad3_ u6
+a5 [net-_u2-pad4_ net-_u5-pad3_ ] net-_u2-pad5_ u7
+a6 [net-_u2-pad5_ net-_u6-pad3_ ] net-_u2-pad4_ u8
+a7 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u7 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends dff
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dff/dff_Previous_Values.xml b/library/SubcircuitLibrary/dff/dff_Previous_Values.xml
new file mode 100644
index 000000000..2a57486b8
--- /dev/null
+++ b/library/SubcircuitLibrary/dff/dff_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_nandd_nandd_andd_andd_nandd_nandd_inverter
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dlatch_own/analysis b/library/SubcircuitLibrary/dlatch_own/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/dlatch_own/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own-cache.lib b/library/SubcircuitLibrary/dlatch_own/dlatch_own-cache.lib
new file mode 100644
index 000000000..c743d042c
--- /dev/null
+++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own-cache.lib
@@ -0,0 +1,94 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir b/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir
new file mode 100644
index 000000000..f79b758d8
--- /dev/null
+++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir
@@ -0,0 +1,16 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\dlatch_own\dlatch_own.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/21/25 19:09:28
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U3 Net-_U1-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad3_ d_and
+U4 Net-_U2-Pad2_ Net-_U1-Pad1_ Net-_U4-Pad3_ d_and
+U5 Net-_U3-Pad3_ Net-_U2-Pad3_ Net-_U2-Pad4_ d_nor
+U6 Net-_U2-Pad4_ Net-_U4-Pad3_ Net-_U2-Pad3_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir.out b/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir.out
new file mode 100644
index 000000000..5bcd05907
--- /dev/null
+++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.cir.out
@@ -0,0 +1,32 @@
+* d:\fossee\esim\library\subcircuitlibrary\dlatch_own\dlatch_own.cir
+
+* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
+* u4 net-_u2-pad2_ net-_u1-pad1_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u2-pad3_ net-_u2-pad4_ d_nor
+* u6 net-_u2-pad4_ net-_u4-pad3_ net-_u2-pad3_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_ port
+a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad1_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u2-pad3_ ] net-_u2-pad4_ u5
+a4 [net-_u2-pad4_ net-_u4-pad3_ ] net-_u2-pad3_ u6
+a5 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.pro b/library/SubcircuitLibrary/dlatch_own/dlatch_own.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.sch b/library/SubcircuitLibrary/dlatch_own/dlatch_own.sch
new file mode 100644
index 000000000..9ed392a0c
--- /dev/null
+++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.sch
@@ -0,0 +1,209 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U3
+U 1 1 6856B545
+P 4350 3350
+F 0 "U3" H 4350 3350 60 0000 C CNN
+F 1 "d_and" H 4400 3450 60 0000 C CNN
+F 2 "" H 4350 3350 60 0000 C CNN
+F 3 "" H 4350 3350 60 0000 C CNN
+ 1 4350 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U4
+U 1 1 6856B5D2
+P 4400 4750
+F 0 "U4" H 4400 4750 60 0000 C CNN
+F 1 "d_and" H 4450 4850 60 0000 C CNN
+F 2 "" H 4400 4750 60 0000 C CNN
+F 3 "" H 4400 4750 60 0000 C CNN
+ 1 4400 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U5
+U 1 1 6856B5DC
+P 7300 3350
+F 0 "U5" H 7300 3350 60 0000 C CNN
+F 1 "d_nor" H 7350 3450 60 0000 C CNN
+F 2 "" H 7300 3350 60 0000 C CNN
+F 3 "" H 7300 3350 60 0000 C CNN
+ 1 7300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 6856B689
+P 7300 4750
+F 0 "U6" H 7300 4750 60 0000 C CNN
+F 1 "d_nor" H 7350 4850 60 0000 C CNN
+F 2 "" H 7300 4750 60 0000 C CNN
+F 3 "" H 7300 4750 60 0000 C CNN
+ 1 7300 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U1
+U 1 1 6856B986
+P 2800 3250
+F 0 "U1" H 2800 3150 60 0000 C CNN
+F 1 "d_inverter" H 2800 3400 60 0000 C CNN
+F 2 "" H 2850 3200 60 0000 C CNN
+F 3 "" H 2850 3200 60 0000 C CNN
+ 1 2800 3250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7750 3300 8750 3300
+Wire Wire Line
+ 7750 4700 9050 4700
+Wire Wire Line
+ 6850 4650 6500 4650
+Wire Wire Line
+ 6500 4650 6500 4300
+Wire Wire Line
+ 6500 4300 8400 4300
+Wire Wire Line
+ 8400 4300 8400 3300
+Connection ~ 8400 3300
+Wire Wire Line
+ 8250 4700 8250 3800
+Wire Wire Line
+ 8250 3800 6600 3800
+Wire Wire Line
+ 6600 3800 6600 3350
+Wire Wire Line
+ 6600 3350 6850 3350
+Connection ~ 8250 4700
+Wire Wire Line
+ 5150 4700 5150 4750
+Wire Wire Line
+ 5150 4750 6850 4750
+Wire Wire Line
+ 4850 4700 5150 4700
+Wire Wire Line
+ 4800 3300 6400 3300
+Wire Wire Line
+ 6400 3300 6400 3250
+Wire Wire Line
+ 6400 3250 6850 3250
+Wire Wire Line
+ 3900 3350 3450 3350
+Wire Wire Line
+ 3450 3350 3450 4650
+Wire Wire Line
+ 3450 4650 3950 4650
+Wire Wire Line
+ 3950 4750 2500 4750
+Wire Wire Line
+ 3100 3250 3900 3250
+Wire Wire Line
+ 2500 3250 2500 4150
+Wire Wire Line
+ 2500 4150 2800 4150
+Wire Wire Line
+ 2800 4150 2800 4750
+Connection ~ 2800 4750
+Wire Wire Line
+ 3450 3950 3200 3950
+Connection ~ 3450 3950
+$Comp
+L PORT U2
+U 1 1 6856BAF3
+P 2250 4750
+F 0 "U2" H 2300 4850 30 0000 C CNN
+F 1 "PORT" H 2250 4750 30 0000 C CNN
+F 2 "" H 2250 4750 60 0000 C CNN
+F 3 "" H 2250 4750 60 0000 C CNN
+ 1 2250 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 3 1 6856BB14
+P 9300 4700
+F 0 "U2" H 9350 4800 30 0000 C CNN
+F 1 "PORT" H 9300 4700 30 0000 C CNN
+F 2 "" H 9300 4700 60 0000 C CNN
+F 3 "" H 9300 4700 60 0000 C CNN
+ 3 9300 4700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U2
+U 2 1 6856BB59
+P 2950 3950
+F 0 "U2" H 3000 4050 30 0000 C CNN
+F 1 "PORT" H 2950 3950 30 0000 C CNN
+F 2 "" H 2950 3950 60 0000 C CNN
+F 3 "" H 2950 3950 60 0000 C CNN
+ 2 2950 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 4 1 6856BB9A
+P 9000 3300
+F 0 "U2" H 9050 3400 30 0000 C CNN
+F 1 "PORT" H 9000 3300 30 0000 C CNN
+F 2 "" H 9000 3300 60 0000 C CNN
+F 3 "" H 9000 3300 60 0000 C CNN
+ 4 9000 3300
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own.sub b/library/SubcircuitLibrary/dlatch_own/dlatch_own.sub
new file mode 100644
index 000000000..38e1779a5
--- /dev/null
+++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own.sub
@@ -0,0 +1,26 @@
+* Subcircuit dlatch_own
+.subckt dlatch_own net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ net-_u2-pad4_
+* d:\fossee\esim\library\subcircuitlibrary\dlatch_own\dlatch_own.cir
+* u3 net-_u1-pad2_ net-_u2-pad2_ net-_u3-pad3_ d_and
+* u4 net-_u2-pad2_ net-_u1-pad1_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u2-pad3_ net-_u2-pad4_ d_nor
+* u6 net-_u2-pad4_ net-_u4-pad3_ net-_u2-pad3_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+a1 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u1-pad1_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u2-pad3_ ] net-_u2-pad4_ u5
+a4 [net-_u2-pad4_ net-_u4-pad3_ ] net-_u2-pad3_ u6
+a5 net-_u1-pad1_ net-_u1-pad2_ u1
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends dlatch_own
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dlatch_own/dlatch_own_Previous_Values.xml b/library/SubcircuitLibrary/dlatch_own/dlatch_own_Previous_Values.xml
new file mode 100644
index 000000000..0a9ca5d55
--- /dev/null
+++ b/library/SubcircuitLibrary/dlatch_own/dlatch_own_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_nord_nord_inverter
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dm74ls51/3_and-cache.lib b/library/SubcircuitLibrary/dm74ls51/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.cir b/library/SubcircuitLibrary/dm74ls51/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.cir.out b/library/SubcircuitLibrary/dm74ls51/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.pro b/library/SubcircuitLibrary/dm74ls51/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.sch b/library/SubcircuitLibrary/dm74ls51/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/dm74ls51/3_and.sub b/library/SubcircuitLibrary/dm74ls51/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dm74ls51/3_and_Previous_Values.xml b/library/SubcircuitLibrary/dm74ls51/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dm74ls51/analysis b/library/SubcircuitLibrary/dm74ls51/analysis
new file mode 100644
index 000000000..0a6c83b5a
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/analysis
@@ -0,0 +1 @@
+.tran 250e-03 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51-cache.lib b/library/SubcircuitLibrary/dm74ls51/dm74ls51-cache.lib
new file mode 100644
index 000000000..cf18b4a95
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51-cache.lib
@@ -0,0 +1,98 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir b/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir
new file mode 100644
index 000000000..e148710b4
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir
@@ -0,0 +1,17 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\dm74ls51\dm74ls51.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/03/25 20:46:55
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad1_ Net-_U3-Pad1_ 3_and
+X2 Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U3-Pad2_ 3_and
+U5 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad1_ d_and
+U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and
+U3 Net-_U3-Pad1_ Net-_U3-Pad2_ Net-_U1-Pad8_ d_nor
+U4 Net-_U4-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_nor
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir.out b/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir.out
new file mode 100644
index 000000000..8494a0915
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.cir.out
@@ -0,0 +1,31 @@
+* c:\fossee\esim\library\subcircuitlibrary\dm74ls51\dm74ls51.cir
+
+.include 3_and.sub
+x1 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad1_ net-_u3-pad1_ 3_and
+x2 net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u3-pad2_ 3_and
+* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad1_ d_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad8_ d_nor
+* u4 net-_u4-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad1_ u5
+a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a3 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u1-pad8_ u3
+a4 [net-_u4-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u4
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 250e-03 10e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.pro b/library/SubcircuitLibrary/dm74ls51/dm74ls51.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.sch b/library/SubcircuitLibrary/dm74ls51/dm74ls51.sch
new file mode 100644
index 000000000..7f0d40034
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.sch
@@ -0,0 +1,312 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and X1
+U 1 1 68669C7A
+P 5350 2450
+F 0 "X1" H 5450 2400 60 0000 C CNN
+F 1 "3_and" H 5500 2600 60 0000 C CNN
+F 2 "" H 5350 2450 60 0000 C CNN
+F 3 "" H 5350 2450 60 0000 C CNN
+ 1 5350 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 68669CC5
+P 5350 2950
+F 0 "X2" H 5450 2900 60 0000 C CNN
+F 1 "3_and" H 5500 3100 60 0000 C CNN
+F 2 "" H 5350 2950 60 0000 C CNN
+F 3 "" H 5350 2950 60 0000 C CNN
+ 1 5350 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U5
+U 1 1 68669D04
+P 5400 3900
+F 0 "U5" H 5400 3900 60 0000 C CNN
+F 1 "d_and" H 5450 4000 60 0000 C CNN
+F 2 "" H 5400 3900 60 0000 C CNN
+F 3 "" H 5400 3900 60 0000 C CNN
+ 1 5400 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 68669D39
+P 5400 4300
+F 0 "U2" H 5400 4300 60 0000 C CNN
+F 1 "d_and" H 5450 4400 60 0000 C CNN
+F 2 "" H 5400 4300 60 0000 C CNN
+F 3 "" H 5400 4300 60 0000 C CNN
+ 1 5400 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U3
+U 1 1 68669D6A
+P 6650 2700
+F 0 "U3" H 6650 2700 60 0000 C CNN
+F 1 "d_nor" H 6700 2800 60 0000 C CNN
+F 2 "" H 6650 2700 60 0000 C CNN
+F 3 "" H 6650 2700 60 0000 C CNN
+ 1 6650 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U4
+U 1 1 68669DBD
+P 6750 4100
+F 0 "U4" H 6750 4100 60 0000 C CNN
+F 1 "d_nor" H 6800 4200 60 0000 C CNN
+F 2 "" H 6750 4100 60 0000 C CNN
+F 3 "" H 6750 4100 60 0000 C CNN
+ 1 6750 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 68669E78
+P 3650 1950
+F 0 "U1" H 3700 2050 30 0000 C CNN
+F 1 "PORT" H 3650 1950 30 0000 C CNN
+F 2 "" H 3650 1950 60 0000 C CNN
+F 3 "" H 3650 1950 60 0000 C CNN
+ 1 3650 1950
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68669F10
+P 4250 3450
+F 0 "U1" H 4300 3550 30 0000 C CNN
+F 1 "PORT" H 4250 3450 30 0000 C CNN
+F 2 "" H 4250 3450 60 0000 C CNN
+F 3 "" H 4250 3450 60 0000 C CNN
+ 2 4250 3450
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68669FB7
+P 4000 3450
+F 0 "U1" H 4050 3550 30 0000 C CNN
+F 1 "PORT" H 4000 3450 30 0000 C CNN
+F 2 "" H 4000 3450 60 0000 C CNN
+F 3 "" H 4000 3450 60 0000 C CNN
+ 3 4000 3450
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68669FF6
+P 4000 4700
+F 0 "U1" H 4050 4800 30 0000 C CNN
+F 1 "PORT" H 4000 4700 30 0000 C CNN
+F 2 "" H 4000 4700 60 0000 C CNN
+F 3 "" H 4000 4700 60 0000 C CNN
+ 4 4000 4700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6866A06F
+P 4250 4700
+F 0 "U1" H 4300 4800 30 0000 C CNN
+F 1 "PORT" H 4250 4700 30 0000 C CNN
+F 2 "" H 4250 4700 60 0000 C CNN
+F 3 "" H 4250 4700 60 0000 C CNN
+ 5 4250 4700
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 5850 2400 6200 2400
+Wire Wire Line
+ 6200 2400 6200 2600
+Wire Wire Line
+ 6200 2700 6200 2900
+Wire Wire Line
+ 6200 2900 5850 2900
+Wire Wire Line
+ 5850 3850 6300 3850
+Wire Wire Line
+ 6300 3850 6300 4000
+Wire Wire Line
+ 6300 4100 6300 4250
+Wire Wire Line
+ 6300 4250 5850 4250
+Wire Wire Line
+ 4250 3700 4250 3800
+Wire Wire Line
+ 4250 3800 4950 3800
+Wire Wire Line
+ 4950 3900 4000 3900
+Wire Wire Line
+ 4000 3900 4000 3700
+Wire Wire Line
+ 4250 4450 4250 4300
+Wire Wire Line
+ 4250 4300 4950 4300
+Wire Wire Line
+ 4950 4200 4000 4200
+Wire Wire Line
+ 4000 4200 4000 4450
+$Comp
+L PORT U1
+U 6 1 6866A23A
+P 7800 4050
+F 0 "U1" H 7850 4150 30 0000 C CNN
+F 1 "PORT" H 7800 4050 30 0000 C CNN
+F 2 "" H 7800 4050 60 0000 C CNN
+F 3 "" H 7800 4050 60 0000 C CNN
+ 6 7800 4050
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6866A31C
+P 7700 2650
+F 0 "U1" H 7750 2750 30 0000 C CNN
+F 1 "PORT" H 7700 2650 30 0000 C CNN
+F 2 "" H 7700 2650 60 0000 C CNN
+F 3 "" H 7700 2650 60 0000 C CNN
+ 8 7700 2650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6866A3A3
+P 3450 3100
+F 0 "U1" H 3500 3200 30 0000 C CNN
+F 1 "PORT" H 3450 3100 30 0000 C CNN
+F 2 "" H 3450 3100 60 0000 C CNN
+F 3 "" H 3450 3100 60 0000 C CNN
+ 9 3450 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6866A498
+P 3450 2900
+F 0 "U1" H 3500 3000 30 0000 C CNN
+F 1 "PORT" H 3450 2900 30 0000 C CNN
+F 2 "" H 3450 2900 60 0000 C CNN
+F 3 "" H 3450 2900 60 0000 C CNN
+ 10 3450 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6866A522
+P 3450 2700
+F 0 "U1" H 3500 2800 30 0000 C CNN
+F 1 "PORT" H 3450 2700 30 0000 C CNN
+F 2 "" H 3450 2700 60 0000 C CNN
+F 3 "" H 3450 2700 60 0000 C CNN
+ 11 3450 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6866A569
+P 4250 1950
+F 0 "U1" H 4300 2050 30 0000 C CNN
+F 1 "PORT" H 4250 1950 30 0000 C CNN
+F 2 "" H 4250 1950 60 0000 C CNN
+F 3 "" H 4250 1950 60 0000 C CNN
+ 12 4250 1950
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6866A5B8
+P 3950 1950
+F 0 "U1" H 4000 2050 30 0000 C CNN
+F 1 "PORT" H 3950 1950 30 0000 C CNN
+F 2 "" H 3950 1950 60 0000 C CNN
+F 3 "" H 3950 1950 60 0000 C CNN
+ 13 3950 1950
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 4250 2200 5000 2200
+Wire Wire Line
+ 5000 2200 5000 2300
+Wire Wire Line
+ 3950 2200 3950 2400
+Wire Wire Line
+ 3950 2400 5000 2400
+Wire Wire Line
+ 3650 2200 3650 2500
+Wire Wire Line
+ 3650 2500 5000 2500
+Wire Wire Line
+ 3700 2700 5000 2700
+Wire Wire Line
+ 5000 2700 5000 2800
+Wire Wire Line
+ 5000 2900 3700 2900
+Wire Wire Line
+ 3700 3100 5000 3100
+Wire Wire Line
+ 5000 3100 5000 3000
+Wire Wire Line
+ 7200 4050 7550 4050
+Wire Wire Line
+ 7100 2650 7450 2650
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51.sub b/library/SubcircuitLibrary/dm74ls51/dm74ls51.sub
new file mode 100644
index 000000000..35c5445f8
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51.sub
@@ -0,0 +1,25 @@
+* Subcircuit dm74ls51
+.subckt dm74ls51 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_
+* c:\fossee\esim\library\subcircuitlibrary\dm74ls51\dm74ls51.cir
+.include 3_and.sub
+x1 net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad1_ net-_u3-pad1_ 3_and
+x2 net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u3-pad2_ 3_and
+* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u4-pad1_ d_and
+* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and
+* u3 net-_u3-pad1_ net-_u3-pad2_ net-_u1-pad8_ d_nor
+* u4 net-_u4-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u4-pad1_ u5
+a2 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2
+a3 [net-_u3-pad1_ net-_u3-pad2_ ] net-_u1-pad8_ u3
+a4 [net-_u4-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u4
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends dm74ls51
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/dm74ls51/dm74ls51_Previous_Values.xml b/library/SubcircuitLibrary/dm74ls51/dm74ls51_Previous_Values.xml
new file mode 100644
index 000000000..1f9d5b233
--- /dev/null
+++ b/library/SubcircuitLibrary/dm74ls51/dm74ls51_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_andd_andd_nord_norC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/eSim_Subckt.lib b/library/SubcircuitLibrary/eSim_Subckt.lib
index 1a8a32397..35fa624df 100644
--- a/library/SubcircuitLibrary/eSim_Subckt.lib
+++ b/library/SubcircuitLibrary/eSim_Subckt.lib
@@ -1,5 +1,2809 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 10bitDAC
+#
+DEF 10bitDAC X 0 40 Y Y 1 F N
+F0 "X" 0 50 60 H V C CNN
+F1 "10bitDAC" -50 -50 60 H V C CNN
+F2 "" 0 50 60 H I C CNN
+F3 "" 0 50 60 H I C CNN
+DRAW
+S -500 500 400 -600 0 1 0 N
+X D0 1 -700 -500 200 R 50 50 1 1 I
+X D1 2 -700 -400 200 R 50 50 1 1 I
+X D2 3 -700 -300 200 R 50 50 1 1 I
+X D3 4 -700 -200 200 R 50 50 1 1 I
+X D4 5 -700 -100 200 R 50 50 1 1 I
+X D5 6 -700 0 200 R 50 50 1 1 I
+X D6 7 -700 100 200 R 50 50 1 1 I
+X D7 8 -700 200 200 R 50 50 1 1 I
+X D8 9 -700 300 200 R 50 50 1 1 I
+X D9 10 -700 400 200 R 50 50 1 1 I
+X AnalogOut 11 600 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 2BITMUL
+#
+DEF 2BITMUL X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "2BITMUL" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 400 300 -400 0 1 0 N
+X A0 1 -500 300 200 R 50 50 1 1 I
+X A1 2 -500 150 200 R 50 50 1 1 I
+X B0 3 -500 -50 200 R 50 50 1 1 I
+X B1 4 -500 -250 200 R 50 50 1 1 I
+X M0 5 500 250 200 L 50 50 1 1 O
+X M1 6 500 100 200 L 50 50 1 1 O
+X M2 7 500 -50 200 L 50 50 1 1 O
+X M3 8 500 -250 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 2_in_and
+#
+DEF 2_in_and X 0 40 Y Y 1 F N
+F0 "X" -50 0 60 H V C CNN
+F1 "2_in_and" -100 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A -50 0 206 760 -760 0 1 0 N 0 200 0 -200
+P 2 0 1 0 -250 200 -250 -200 N
+P 2 0 1 0 -250 200 0 200 N
+P 2 0 1 0 0 -200 0 -200 N
+P 3 0 1 0 -250 -200 -50 -200 0 -200 N
+X vdd 1 -450 150 200 R 50 50 1 1 I
+X Gnd 2 -450 -150 200 R 50 50 1 1 I
+X in1 3 -450 50 200 R 50 50 1 1 I
+X in2 4 -450 -50 200 R 50 50 1 1 I
+X out 5 350 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 3_in_and
+#
+DEF 3_in_and X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "3_in_and" 0 -300 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 0 0 255 787 -787 0 1 0 N 50 250 50 -250
+P 2 0 1 0 -250 250 50 250 N
+P 3 0 1 0 -250 250 -250 -250 50 -250 N
+X in1 1 -450 100 200 R 50 50 1 1 I
+X in2 2 -450 0 200 R 50 50 1 1 I
+X VDD 3 -450 200 200 R 50 50 1 1 I
+X GND 4 -450 -200 200 R 50 50 1 1 I
+X in3 5 -450 -100 200 R 50 50 1 1 I
+X OUT 6 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_in_and
+#
+DEF 4_in_and X 0 40 Y Y 1 F N
+F0 "X" -50 0 60 H V C CNN
+F1 "4_in_and" -100 -350 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A -100 0 304 805 -805 0 1 0 N -50 300 -50 -300
+P 2 0 1 0 -350 -300 -50 -300 N
+P 2 0 1 0 -350 300 -350 -300 N
+P 2 0 1 0 -350 300 -100 300 N
+P 2 0 1 0 -100 300 -50 300 N
+X vdd 1 -550 250 200 R 50 50 1 1 I
+X in1 2 -550 150 200 R 50 50 1 1 I
+X in2 3 -550 50 200 R 50 50 1 1 I
+X in3 4 -550 -50 200 R 50 50 1 1 I
+X Gnd 5 -550 -250 200 R 50 50 1 1 I
+X in4 6 -550 -150 200 R 50 50 1 1 I
+X out 7 400 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 556
+#
+DEF 556 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "556" 0 0 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 250 -550 0 1 0 N
+X dis1 1 -500 150 200 R 50 50 1 1 I
+X thr1 2 -500 -150 200 R 50 50 1 1 I
+X cv1 3 -150 -750 200 U 50 50 1 1 I
+X rst1 4 -200 600 200 D 50 50 1 1 I
+X out1 5 -500 0 200 R 50 50 1 1 O
+X trig1 6 -500 -300 200 R 50 50 1 1 I
+X gnd 7 0 -750 200 U 50 50 1 1 I
+X trig2 8 450 -300 200 L 50 50 1 1 I
+X out2 9 450 0 200 L 50 50 1 1 O
+X rst2 10 100 600 200 D 50 50 1 1 I
+X cv2 11 150 -750 200 U 50 50 1 1 I
+X thr2 12 450 -150 200 L 50 50 1 1 I
+X dis2 13 450 150 200 L 50 50 1 1 I
+X vcc 14 -50 600 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# 5_and
+#
+DEF 5_and X 0 40 Y Y 1 F N
+F0 "X" 50 -100 60 H V C CNN
+F1 "5_and" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
+P 2 0 1 0 -250 250 150 250 N
+P 3 0 1 0 -250 250 -250 -250 150 -250 N
+X in1 1 -450 200 200 R 50 50 1 1 I
+X in2 2 -450 100 200 R 50 50 1 1 I
+X in3 3 -450 0 200 R 50 50 1 1 I
+X in4 4 -450 -100 200 R 50 50 1 1 I
+X in5 5 -450 -200 200 R 50 50 1 1 I
+X out 6 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CD4042B
+#
+DEF CD4042B X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CD4042B" 0 -450 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -450 400 450 -400 0 1 0 N
+X CLOCK 1 -650 -150 200 R 50 50 1 1 I
+X POLARITY 2 -650 -250 200 R 50 50 1 1 I
+X D1 3 -650 250 200 R 50 50 1 1 I
+X D2 4 -650 150 200 R 50 50 1 1 I
+X D3 5 -650 50 200 R 50 50 1 1 I
+X D4 6 -650 -50 200 R 50 50 1 1 I
+X VDD 7 -650 350 200 R 50 50 1 1 I
+X GND 8 -650 -350 200 R 50 50 1 1 I
+X Q1 9 650 350 200 L 50 50 1 1 O
+X Q2 10 650 250 200 L 50 50 1 1 O
+X Q3 11 650 150 200 L 50 50 1 1 O
+X Q4 12 650 50 200 L 50 50 1 1 O
+X Q1_Bar 13 650 -50 200 L 50 50 1 1 O
+X Q2_Bar 14 650 -150 200 L 50 50 1 1 O
+X Q3_Bar 15 650 -250 200 L 50 50 1 1 O
+X Q4_Bar 16 650 -350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CD4044BMS
+#
+DEF CD4044BMS X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CD4044BMS" 0 -450 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 350 350 -350 0 1 0 N
+X S1 1 -500 200 200 R 50 50 1 1 I
+X E 2 0 550 200 D 50 50 1 1 I
+X R1 3 -500 -200 200 R 50 50 1 1 I
+X S2 4 -500 100 200 R 50 50 1 1 I
+X R2 5 -500 -300 200 R 50 50 1 1 I
+X S3 6 -500 0 200 R 50 50 1 1 I
+X R3 7 550 300 200 L 50 50 1 1 I
+X S4 8 -500 -100 200 R 50 50 1 1 I
+X R4 9 550 200 200 L 50 50 1 1 I
+X GND 10 550 -300 200 L 50 50 1 1 I
+X VDD 11 -500 300 200 R 50 50 1 1 I
+X O1 12 550 100 200 L 50 50 1 1 O
+X O3 13 550 -100 200 L 50 50 1 1 O
+X O2 14 550 0 200 L 50 50 1 1 O
+X O4 15 550 -200 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CD4068B
+#
+DEF CD4068B X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CD4068B" 0 -350 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 300 350 -300 0 1 0 N
+X in1 1 -500 150 200 R 50 50 1 1 I
+X in2 2 -500 50 200 R 50 50 1 1 I
+X in3 3 -500 -50 200 R 50 50 1 1 I
+X in4 4 -500 -150 200 R 50 50 1 1 I
+X in5 5 -500 -250 200 R 50 50 1 1 I
+X in6 6 550 250 200 L 50 50 1 1 I
+X in7 7 550 150 200 L 50 50 1 1 I
+X in8 8 550 50 200 L 50 50 1 1 I
+X VDD 9 -500 250 200 R 50 50 1 1 I
+X GND 10 550 -250 200 L 50 50 1 1 I
+X OUT 11 550 -50 200 L 50 50 1 1 O
+X OUT_Bar 12 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_BUF
+#
+DEF CMOS_BUF X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_BUF" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+P 4 0 1 0 -250 150 -250 -150 250 0 -250 150 N
+X VDD 1 -450 100 200 R 50 50 1 1 I
+X GND 2 -450 -100 200 R 50 50 1 1 I
+X IN 3 -450 0 200 R 50 50 1 1 I
+X OUT 4 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_INVTR
+#
+DEF CMOS_INVTR X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "CMOS_INVTR" -50 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+C 250 0 50 0 1 0 N
+P 2 0 1 0 -250 150 200 0 N
+P 3 0 1 0 -250 150 -250 -150 200 0 N
+X IN 1 -450 0 200 R 50 50 1 1 I
+X VDD 2 -450 100 200 R 50 50 1 1 I
+X GND 3 -450 -100 200 R 50 50 1 1 I
+X OUT 4 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CMOS_NAND
+#
+DEF CMOS_NAND X 0 40 Y Y 1 F N
+F0 "X" -100 -150 60 H V C CNN
+F1 "CMOS_NAND" 0 -50 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -350 300 300 300 N
+P 3 0 1 0 -350 300 -350 -400 300 -400 N
+X in1 1 -550 250 200 R 50 50 1 1 I
+X in2 2 -550 -300 200 R 50 50 1 1 I
+X out 3 800 0 279 L 79 79 1 1 I
+ENDDRAW
+ENDDEF
+#
+# Clock_pulse_generator
+#
+DEF Clock_pulse_generator X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "Clock_pulse_generator" 0 -100 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -550 200 600 -300 0 1 0 N
+X Vdd 1 -750 100 200 R 50 50 1 1 I
+X R 2 -750 -50 200 R 50 50 1 1 I
+X C 3 -750 -200 200 R 50 50 1 1 I
+X Clkout 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# DFF_CE
+#
+DEF DFF_CE X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "DFF_CE" 0 -200 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -400 150 300 -150 0 1 0 N
+X CLK 1 -600 -100 200 R 50 50 1 1 I
+X CLK_EN 2 -600 0 200 R 50 50 1 1 I
+X D 3 -600 100 200 R 50 50 1 1 I
+X VDD 4 500 100 200 L 50 50 1 1 I
+X GND 5 500 -100 200 L 50 50 1 1 I
+X OUT 6 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# DS_blk
+#
+DEF DS_blk X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "DS_blk" 50 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -250 200 250 -200 0 1 0 N
+X in1 1 -450 150 200 R 50 50 1 1 I
+X ws1 2 -450 50 200 R 50 50 1 1 I
+X ws2 3 -450 -50 200 R 50 50 1 1 I
+X in2 4 -450 -150 200 R 50 50 1 1 I
+X clk 5 450 50 200 L 50 50 1 1 I C
+X vdd 6 450 150 200 L 50 50 1 1 I
+X gnd 7 450 -150 200 L 50 50 1 1 I
+X out 8 450 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# D_FF
+#
+DEF D_FF X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "D_FF" 50 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -250 200 300 -200 0 1 0 N
+X D 1 -450 50 200 R 50 50 1 1 I
+X CLK 2 -450 -50 200 R 50 50 1 1 I
+X VDD 3 -450 150 200 R 50 50 1 1 I
+X GND 4 -450 -150 200 R 50 50 1 1 I
+X OUT 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# D_Latch
+#
+DEF D_Latch X 0 40 Y Y 1 F N
+F0 "X" -50 0 60 H V C CNN
+F1 "D_Latch" 0 -250 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -250 200 300 -200 0 1 0 N
+X LE 1 -450 100 200 R 50 50 1 1 I
+X D 2 -450 0 200 R 50 50 1 1 I
+X RE 3 -450 -100 200 R 50 50 1 1 I
+X Gnd 4 0 -400 200 U 50 50 1 1 I
+X Vdd 5 0 400 200 D 50 50 1 1 I
+X Q 6 500 50 200 L 50 50 1 1 O
+X Q_Bar 7 500 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Decoder_38
+#
+DEF Decoder_38 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "Decoder_38" 0 -500 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -300 450 250 -450 0 1 0 N
+X S0_B 1 -500 300 200 R 50 50 1 1 I I
+X S1_B 2 -500 200 200 R 50 50 1 1 I I
+X S2_B 3 -500 100 200 R 50 50 1 1 I I
+X S0 4 -500 -100 200 R 50 50 1 1 I
+X S1 5 -500 -200 200 R 50 50 1 1 I
+X S2 6 -500 -300 200 R 50 50 1 1 I
+X G 7 -500 0 200 R 50 50 1 1 I I
+X Vdd 8 -500 400 200 R 50 50 1 1 I
+X Gnd 9 -500 -400 200 R 50 50 1 1 I
+X D6 10 450 -300 200 L 50 50 1 1 O
+X D4 11 450 -100 200 L 50 50 1 1 O
+X D0 12 450 400 200 L 50 50 1 1 O
+X D7 13 450 -400 200 L 50 50 1 1 O
+X D5 14 450 -200 200 L 50 50 1 1 O
+X D2 15 450 200 200 L 50 50 1 1 O
+X D1 16 450 300 200 L 50 50 1 1 O
+X D3 17 450 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# Decoder_38_Address_Latch_storage
+#
+DEF Decoder_38_Address_Latch_storage X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "Decoder_38_Address_Latch_storage" 0 -600 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -250 550 200 -550 0 1 0 N
+X Q1 1 400 350 200 L 50 50 1 1 O
+X Q3 2 400 150 200 L 50 50 1 1 O
+X Q2 3 400 250 200 L 50 50 1 1 O
+X Q4 4 400 50 200 L 50 50 1 1 O
+X Vdd 5 -450 500 200 R 50 50 1 1 I
+X Gnd 6 -450 -500 200 R 50 50 1 1 I
+X Q5 7 400 -50 200 L 50 50 1 1 O
+X Q6 8 400 -150 200 L 50 50 1 1 O
+X Q7 9 400 -250 200 L 50 50 1 1 O
+X Q8 10 400 -350 200 L 50 50 1 1 O
+X RE 11 -450 -300 200 R 50 50 1 1 I
+X D 12 -450 -400 200 R 50 50 1 1 I
+X S0_B 13 -450 400 200 R 50 50 1 1 I I
+X S1_B 14 -450 300 200 R 50 50 1 1 I I
+X S2_B 15 -450 200 200 R 50 50 1 1 I I
+X G 16 -450 -200 200 R 50 50 1 1 I I
+X S0 17 -450 100 200 R 50 50 1 1 I
+X S1 18 -450 0 200 R 50 50 1 1 I
+X S2 19 -450 -100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4002
+#
+DEF IC_4002 X 0 40 Y Y 1 F N
+F0 "X" 0 150 60 H V C CNN
+F1 "IC_4002" 0 0 60 H V C CNN
+F2 "" 50 -150 60 H V C CNN
+F3 "" 50 -150 60 H V C CNN
+DRAW
+S -250 350 250 -400 0 1 0 N
+X 1Y 1 -450 250 200 R 50 50 1 1 O
+X 1A 2 -450 150 200 R 50 50 1 1 I
+X 1B 3 -450 50 200 R 50 50 1 1 I
+X 1C 4 -450 -50 200 R 50 50 1 1 I
+X 1D 5 -450 -150 200 R 50 50 1 1 I
+X NC 6 -450 -250 200 R 50 50 1 1 I
+X GND 7 -450 -350 200 R 50 50 1 1 I
+X NC 8 450 -350 200 L 50 50 1 1 I
+X 2A 9 450 -250 200 L 50 50 1 1 I
+X 2B 10 450 -150 200 L 50 50 1 1 I
+X 2C 11 450 -50 200 L 50 50 1 1 I
+X 2D 12 450 50 200 L 50 50 1 1 I
+X 2Y 13 450 150 200 L 50 50 1 1 O
+X VCC 14 450 250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4012
+#
+DEF IC_4012 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "IC_4012" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 350 -400 0 1 0 N
+X Q1 1 -500 300 200 R 50 50 1 1 O
+X A1 2 -500 200 200 R 50 50 1 1 I
+X B1 3 -500 100 200 R 50 50 1 1 I
+X C1 4 -500 0 200 R 50 50 1 1 I
+X D1 5 -500 -100 200 R 50 50 1 1 I
+X NC 6 -500 -200 200 R 50 50 1 1 N
+X VSS 7 -500 -300 200 R 50 50 1 1 I
+X NC 8 550 -300 200 L 50 50 1 1 N
+X A2 9 550 -200 200 L 50 50 1 1 I
+X B2 10 550 -100 200 L 50 50 1 1 I
+X C2 11 550 0 200 L 50 50 1 1 I
+X D2 12 550 100 200 L 50 50 1 1 I
+X Q2 13 550 200 200 L 50 50 1 1 O
+X VDD 14 550 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4017
+#
+DEF IC_4017 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "IC_4017" 0 0 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 850 400 -850 0 1 0 N
+X 1 1 600 650 200 L 50 50 1 1 O
+X 2 2 600 500 200 L 50 50 1 1 O
+X 3 3 600 350 200 L 50 50 1 1 O
+X 4 4 600 200 200 L 50 50 1 1 O
+X 5 5 600 50 200 L 50 50 1 1 O
+X 6 6 600 -100 200 L 50 50 1 1 O
+X 7 7 600 -250 200 L 50 50 1 1 O
+X 8 8 600 -400 200 L 50 50 1 1 O
+X 9 9 600 -600 200 L 50 50 1 1 O
+X 10 10 600 -750 200 L 50 50 1 1 O
+X RST 11 -550 -400 200 R 50 50 1 1 I
+X CLK 12 -550 350 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4023
+#
+DEF IC_4023 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4023" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X C3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X A3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4028
+#
+DEF IC_4028 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4028" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X Q4 1 -500 350 200 R 50 50 1 1 O
+X Q2 2 -500 250 200 R 50 50 1 1 O
+X Q0 3 -500 150 200 R 50 50 1 1 O
+X Q7 4 -500 50 200 R 50 50 1 1 O
+X Q9 5 -500 -50 200 R 50 50 1 1 O
+X Q5 6 -500 -150 200 R 50 50 1 1 O
+X Q6 7 -500 -250 200 R 50 50 1 1 O
+X Vss 8 -500 -350 200 R 50 50 1 1 I
+X Q8 9 500 -350 200 L 50 50 1 1 O
+X A0 10 500 -250 200 L 50 50 1 1 I
+X A3 11 500 -150 200 L 50 50 1 1 I
+X A2 12 500 -50 200 L 50 50 1 1 I
+X A1 13 500 50 200 L 50 50 1 1 I
+X Q1 14 500 150 200 L 50 50 1 1 O
+X Q3 15 500 250 200 L 50 50 1 1 O
+X Vdd 16 500 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_4073
+#
+DEF IC_4073 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4073" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 300 -400 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X A3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X C3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_74153
+#
+DEF IC_74153 X 0 40 Y Y 1 F N
+F0 "X" 100 50 60 H V C CNN
+F1 "IC_74153" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 100 -200 60 0 0 0 4:1 Normal 0 C C
+T 0 100 -100 60 0 0 0 DUAL Normal 0 C C
+T 0 100 -300 60 0 0 0 MUX Normal 0 C C
+S -200 500 350 -550 0 1 0 N
+X a0 1 -400 350 200 R 50 50 1 1 I
+X a1 2 -400 250 200 R 50 50 1 1 I
+X a2 3 -400 150 200 R 50 50 1 1 I
+X a3 4 -400 50 200 R 50 50 1 1 I
+X EA 5 0 700 200 D 50 50 1 1 I I
+X b0 6 -400 -150 200 R 50 50 1 1 I
+X b1 7 -400 -250 200 R 50 50 1 1 I
+X b2 8 -400 -350 200 R 50 50 1 1 I
+X b3 9 -400 -450 200 R 50 50 1 1 I
+X EB 10 200 700 200 D 50 50 1 1 I I
+X s1 11 50 -750 200 U 50 50 1 1 I
+X s0 12 150 -750 200 U 50 50 1 1 I
+X ya 13 550 250 200 L 50 50 1 1 O
+X yb 14 550 -300 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_74154
+#
+DEF IC_74154 X 0 40 Y Y 1 F N
+F0 "X" 0 -200 60 H V C CNN
+F1 "IC_74154" 50 -50 60 H V C CNN
+F2 "" 0 50 60 H V C CNN
+F3 "" 0 50 60 H V C CNN
+DRAW
+T 0 0 400 60 0 0 0 4:16~ Normal 0 C C
+T 0 0 250 60 0 0 0 decoder Normal 0 C C
+S -350 700 400 -700 0 0 0 N
+X ~Y0 1 -550 550 200 R 50 50 1 1 O I
+X ~Y1 2 -550 450 200 R 50 50 1 1 O I
+X ~Y2 3 -550 350 200 R 50 50 1 1 O I
+X ~Y3 4 -550 250 200 R 50 50 1 1 O I
+X ~Y4 5 -550 150 200 R 50 50 1 1 O I
+X ~Y5 6 -550 50 200 R 50 50 1 1 O I
+X ~Y6 7 -550 -50 200 R 50 50 1 1 O I
+X ~Y7 8 -550 -150 200 R 50 50 1 1 O I
+X ~Y8 9 -550 -250 200 R 50 50 1 1 O I
+X ~Y9 10 -550 -350 200 R 50 50 1 1 O I
+X A3 20 600 150 200 L 50 50 1 1 I
+X ~Y10 11 -550 -450 200 R 50 50 1 1 O I
+X A2 21 600 250 200 L 50 50 1 1 I
+X GND 12 -550 -550 200 R 50 50 1 1 I
+X A1 22 600 350 200 L 50 50 1 1 I
+X ~Y11 13 600 -550 200 L 50 50 1 1 O I
+X A0 23 600 450 200 L 50 50 1 1 I
+X ~Y12 14 600 -450 200 L 50 50 1 1 O I
+X Vcc 24 600 550 200 L 50 50 1 1 I
+X ~Y13 15 600 -350 200 L 50 50 1 1 O I
+X ~Y14 16 600 -250 200 L 50 50 1 1 O I
+X ~Y15 17 600 -150 200 L 50 50 1 1 O I
+X ~E0 18 600 -50 200 L 50 50 1 1 I I
+X ~E1 19 600 50 200 L 50 50 1 1 I I
+ENDDRAW
+ENDDEF
+#
+# IC_74157
+#
+DEF IC_74157 X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "IC_74157" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 50 -300 60 0 0 0 2:1 Normal 0 C C
+T 0 50 -400 60 0 0 0 MUX Normal 0 C C
+T 0 50 -200 60 0 0 0 QUAD Normal 0 C C
+S -350 550 400 -650 0 1 0 N
+X a0 1 -550 450 200 R 50 50 1 1 I
+X a1 2 -550 300 200 R 50 50 1 1 I
+X b0 3 -550 200 200 R 50 50 1 1 I
+X b1 4 -550 100 200 R 50 50 1 1 I
+X c0 5 -550 0 200 R 50 50 1 1 I
+X c1 6 -550 -100 200 R 50 50 1 1 I
+X d0 7 -550 -200 200 R 50 50 1 1 I
+X d1 8 -550 -300 200 R 50 50 1 1 I
+X EN 9 -550 -550 200 R 50 50 1 1 I I
+X S 10 -550 -450 200 R 50 50 1 1 I
+X Yd 11 600 0 200 L 50 50 1 1 O
+X Ya 12 600 300 200 L 50 50 1 1 O
+X Yb 13 600 200 200 L 50 50 1 1 O
+X Yc 14 600 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_7485
+#
+DEF IC_7485 X 0 40 Y Y 1 F N
+F0 "X" -50 -100 60 H V C CNN
+F1 "IC_7485" -50 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C
+S -350 450 400 -400 0 1 0 N
+X AB(in) 3 600 -300 200 L 50 50 1 1 I
+X A3 4 -550 100 200 R 50 50 1 1 I
+X B3 5 -550 -350 200 R 50 50 1 1 I
+X A2 6 -550 200 200 R 50 50 1 1 I
+X B2 7 -550 -250 200 R 50 50 1 1 I
+X A1 8 -550 300 200 R 50 50 1 1 I
+X B1 9 -550 -150 200 R 50 50 1 1 I
+X A0 10 -550 400 200 R 50 50 1 1 I
+X B0 11 -550 -50 200 R 50 50 1 1 I
+X A>B(out) 12 600 350 200 L 50 50 1 1 O
+X A=B(out) 13 600 250 200 L 50 50 1 1 O
+X AB(in) 3 600 -300 200 L 50 50 1 1 I
+X A3 4 -550 100 200 R 50 50 1 1 I
+X B3 5 -550 -350 200 R 50 50 1 1 I
+X A2 6 -550 200 200 R 50 50 1 1 I
+X B2 7 -550 -250 200 R 50 50 1 1 I
+X A1 8 -550 300 200 R 50 50 1 1 I
+X B1 9 -550 -150 200 R 50 50 1 1 I
+X A0 10 -550 400 200 R 50 50 1 1 I
+X B0 11 -550 -50 200 R 50 50 1 1 I
+X A>B(out) 12 600 350 200 L 50 50 1 1 O
+X A=B(out) 13 600 250 200 L 50 50 1 1 O
+X A plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/f100102/f100102.pro b/library/SubcircuitLibrary/f100102/f100102.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/f100102/f100102.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/f100102/f100102.sch b/library/SubcircuitLibrary/f100102/f100102.sch
new file mode 100644
index 000000000..cce2457fe
--- /dev/null
+++ b/library/SubcircuitLibrary/f100102/f100102.sch
@@ -0,0 +1,586 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 68680518
+P 4100 1800
+F 0 "U2" H 4100 1800 60 0000 C CNN
+F 1 "d_or" H 4100 1900 60 0000 C CNN
+F 2 "" H 4100 1800 60 0000 C CNN
+F 3 "" H 4100 1800 60 0000 C CNN
+ 1 4100 1800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U6
+U 1 1 68680541
+P 5150 2050
+F 0 "U6" H 5150 2050 60 0000 C CNN
+F 1 "d_or" H 5150 2150 60 0000 C CNN
+F 2 "" H 5150 2050 60 0000 C CNN
+F 3 "" H 5150 2050 60 0000 C CNN
+ 1 5150 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 686805B7
+P 4100 2400
+F 0 "U3" H 4100 2400 60 0000 C CNN
+F 1 "d_or" H 4100 2500 60 0000 C CNN
+F 2 "" H 4100 2400 60 0000 C CNN
+F 3 "" H 4100 2400 60 0000 C CNN
+ 1 4100 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U7
+U 1 1 686805BD
+P 5150 2650
+F 0 "U7" H 5150 2650 60 0000 C CNN
+F 1 "d_or" H 5150 2750 60 0000 C CNN
+F 2 "" H 5150 2650 60 0000 C CNN
+F 3 "" H 5150 2650 60 0000 C CNN
+ 1 5150 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 6868075B
+P 4100 3050
+F 0 "U4" H 4100 3050 60 0000 C CNN
+F 1 "d_or" H 4100 3150 60 0000 C CNN
+F 2 "" H 4100 3050 60 0000 C CNN
+F 3 "" H 4100 3050 60 0000 C CNN
+ 1 4100 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U8
+U 1 1 68680761
+P 5150 3300
+F 0 "U8" H 5150 3300 60 0000 C CNN
+F 1 "d_or" H 5150 3400 60 0000 C CNN
+F 2 "" H 5150 3300 60 0000 C CNN
+F 3 "" H 5150 3300 60 0000 C CNN
+ 1 5150 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U5
+U 1 1 68680769
+P 4100 3650
+F 0 "U5" H 4100 3650 60 0000 C CNN
+F 1 "d_or" H 4100 3750 60 0000 C CNN
+F 2 "" H 4100 3650 60 0000 C CNN
+F 3 "" H 4100 3650 60 0000 C CNN
+ 1 4100 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U9
+U 1 1 6868076F
+P 5150 3900
+F 0 "U9" H 5150 3900 60 0000 C CNN
+F 1 "d_or" H 5150 4000 60 0000 C CNN
+F 2 "" H 5150 3900 60 0000 C CNN
+F 3 "" H 5150 3900 60 0000 C CNN
+ 1 5150 3900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 686808D4
+P 6200 1650
+F 0 "U10" H 6200 1550 60 0000 C CNN
+F 1 "d_inverter" H 6200 1800 60 0000 C CNN
+F 2 "" H 6250 1600 60 0000 C CNN
+F 3 "" H 6250 1600 60 0000 C CNN
+ 1 6200 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U11
+U 1 1 68680929
+P 6200 2350
+F 0 "U11" H 6200 2250 60 0000 C CNN
+F 1 "d_inverter" H 6200 2500 60 0000 C CNN
+F 2 "" H 6250 2300 60 0000 C CNN
+F 3 "" H 6250 2300 60 0000 C CNN
+ 1 6200 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 6868096E
+P 6200 2950
+F 0 "U12" H 6200 2850 60 0000 C CNN
+F 1 "d_inverter" H 6200 3100 60 0000 C CNN
+F 2 "" H 6250 2900 60 0000 C CNN
+F 3 "" H 6250 2900 60 0000 C CNN
+ 1 6200 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U13
+U 1 1 686809B9
+P 6200 3600
+F 0 "U13" H 6200 3500 60 0000 C CNN
+F 1 "d_inverter" H 6200 3750 60 0000 C CNN
+F 2 "" H 6250 3550 60 0000 C CNN
+F 3 "" H 6250 3550 60 0000 C CNN
+ 1 6200 3600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5600 3600 5900 3600
+Wire Wire Line
+ 5600 3850 5600 3600
+Wire Wire Line
+ 5600 2950 5900 2950
+Wire Wire Line
+ 5600 3250 5600 2950
+Wire Wire Line
+ 5600 2350 5900 2350
+Wire Wire Line
+ 5600 2600 5600 2350
+Wire Wire Line
+ 5600 1650 5900 1650
+Wire Wire Line
+ 5600 2000 5600 1650
+Wire Wire Line
+ 2850 3900 4700 3900
+Wire Wire Line
+ 2850 3300 4700 3300
+Wire Wire Line
+ 2850 2650 4700 2650
+Wire Wire Line
+ 2850 2050 4700 2050
+Wire Wire Line
+ 4550 3800 4700 3800
+Wire Wire Line
+ 4550 3600 4550 3800
+Wire Wire Line
+ 4550 3200 4700 3200
+Wire Wire Line
+ 4550 3000 4550 3200
+Wire Wire Line
+ 4550 2550 4700 2550
+Wire Wire Line
+ 4550 2350 4550 2550
+Wire Wire Line
+ 4550 1950 4700 1950
+Wire Wire Line
+ 4550 1750 4550 1950
+$Comp
+L d_or U14
+U 1 1 68680CEF
+P 4100 4350
+F 0 "U14" H 4100 4350 60 0000 C CNN
+F 1 "d_or" H 4100 4450 60 0000 C CNN
+F 2 "" H 4100 4350 60 0000 C CNN
+F 3 "" H 4100 4350 60 0000 C CNN
+ 1 4100 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U15
+U 1 1 68680CF5
+P 5150 4600
+F 0 "U15" H 5150 4600 60 0000 C CNN
+F 1 "d_or" H 5150 4700 60 0000 C CNN
+F 2 "" H 5150 4600 60 0000 C CNN
+F 3 "" H 5150 4600 60 0000 C CNN
+ 1 5150 4600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2850 4600 4700 4600
+Wire Wire Line
+ 4550 4500 4700 4500
+Wire Wire Line
+ 4550 4300 4550 4500
+$Comp
+L d_inverter U16
+U 1 1 68680D10
+P 6200 4250
+F 0 "U16" H 6200 4150 60 0000 C CNN
+F 1 "d_inverter" H 6200 4400 60 0000 C CNN
+F 2 "" H 6250 4200 60 0000 C CNN
+F 3 "" H 6250 4200 60 0000 C CNN
+ 1 6200 4250
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5600 4550 5600 4250
+Wire Wire Line
+ 5600 4250 5900 4250
+$Comp
+L d_buffer U17
+U 1 1 68680DA0
+P 2200 5350
+F 0 "U17" H 2200 5300 60 0000 C CNN
+F 1 "d_buffer" H 2200 5400 60 0000 C CNN
+F 2 "" H 2200 5350 60 0000 C CNN
+F 3 "" H 2200 5350 60 0000 C CNN
+ 1 2200 5350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2850 5350 2850 2050
+Connection ~ 2850 2650
+Connection ~ 2850 3300
+Connection ~ 2850 3900
+Connection ~ 2850 4600
+$Comp
+L PORT U1
+U 1 1 686810B2
+P 2250 4400
+F 0 "U1" H 2300 4500 30 0000 C CNN
+F 1 "PORT" H 2250 4400 30 0000 C CNN
+F 2 "" H 2250 4400 60 0000 C CNN
+F 3 "" H 2250 4400 60 0000 C CNN
+ 1 2250 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2500 4400 3650 4400
+Wire Wire Line
+ 3650 4400 3650 4350
+$Comp
+L PORT U1
+U 2 1 6868124C
+P 7150 4500
+F 0 "U1" H 7200 4600 30 0000 C CNN
+F 1 "PORT" H 7150 4500 30 0000 C CNN
+F 2 "" H 7150 4500 60 0000 C CNN
+F 3 "" H 7150 4500 60 0000 C CNN
+ 2 7150 4500
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6868133D
+P 7150 4250
+F 0 "U1" H 7200 4350 30 0000 C CNN
+F 1 "PORT" H 7150 4250 30 0000 C CNN
+F 2 "" H 7150 4250 60 0000 C CNN
+F 3 "" H 7150 4250 60 0000 C CNN
+ 3 7150 4250
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 6500 4250 6900 4250
+Wire Wire Line
+ 6900 4500 5600 4500
+Connection ~ 5600 4500
+$Comp
+L PORT U1
+U 4 1 686814AF
+P 7200 3600
+F 0 "U1" H 7250 3700 30 0000 C CNN
+F 1 "PORT" H 7200 3600 30 0000 C CNN
+F 2 "" H 7200 3600 60 0000 C CNN
+F 3 "" H 7200 3600 60 0000 C CNN
+ 4 7200 3600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 68681516
+P 7200 3800
+F 0 "U1" H 7250 3900 30 0000 C CNN
+F 1 "PORT" H 7200 3800 30 0000 C CNN
+F 2 "" H 7200 3800 60 0000 C CNN
+F 3 "" H 7200 3800 60 0000 C CNN
+ 5 7200 3800
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 6500 3600 6950 3600
+Wire Wire Line
+ 6950 3800 5600 3800
+Connection ~ 5600 3800
+$Comp
+L PORT U1
+U 8 1 686816C8
+P 7250 2950
+F 0 "U1" H 7300 3050 30 0000 C CNN
+F 1 "PORT" H 7250 2950 30 0000 C CNN
+F 2 "" H 7250 2950 60 0000 C CNN
+F 3 "" H 7250 2950 60 0000 C CNN
+ 8 7250 2950
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6868172D
+P 7250 3150
+F 0 "U1" H 7300 3250 30 0000 C CNN
+F 1 "PORT" H 7250 3150 30 0000 C CNN
+F 2 "" H 7250 3150 60 0000 C CNN
+F 3 "" H 7250 3150 60 0000 C CNN
+ 9 7250 3150
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 6500 2950 7000 2950
+Wire Wire Line
+ 7000 3150 5600 3150
+Connection ~ 5600 3150
+$Comp
+L PORT U1
+U 10 1 68681826
+P 7050 2550
+F 0 "U1" H 7100 2650 30 0000 C CNN
+F 1 "PORT" H 7050 2550 30 0000 C CNN
+F 2 "" H 7050 2550 60 0000 C CNN
+F 3 "" H 7050 2550 60 0000 C CNN
+ 10 7050 2550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 68681885
+P 7050 2350
+F 0 "U1" H 7100 2450 30 0000 C CNN
+F 1 "PORT" H 7050 2350 30 0000 C CNN
+F 2 "" H 7050 2350 60 0000 C CNN
+F 3 "" H 7050 2350 60 0000 C CNN
+ 11 7050 2350
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 6500 2350 6800 2350
+Wire Wire Line
+ 6800 2550 5600 2550
+Connection ~ 5600 2550
+$Comp
+L PORT U1
+U 12 1 686819AB
+P 7100 1650
+F 0 "U1" H 7150 1750 30 0000 C CNN
+F 1 "PORT" H 7100 1650 30 0000 C CNN
+F 2 "" H 7100 1650 60 0000 C CNN
+F 3 "" H 7100 1650 60 0000 C CNN
+ 12 7100 1650
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 68681A0A
+P 7100 1900
+F 0 "U1" H 7150 2000 30 0000 C CNN
+F 1 "PORT" H 7100 1900 30 0000 C CNN
+F 2 "" H 7100 1900 60 0000 C CNN
+F 3 "" H 7100 1900 60 0000 C CNN
+ 13 7100 1900
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 6500 1650 6850 1650
+Wire Wire Line
+ 6850 1900 5600 1900
+Connection ~ 5600 1900
+$Comp
+L PORT U1
+U 14 1 68681BBA
+P 2300 1600
+F 0 "U1" H 2350 1700 30 0000 C CNN
+F 1 "PORT" H 2300 1600 30 0000 C CNN
+F 2 "" H 2300 1600 60 0000 C CNN
+F 3 "" H 2300 1600 60 0000 C CNN
+ 14 2300 1600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 68681C37
+P 2300 1850
+F 0 "U1" H 2350 1950 30 0000 C CNN
+F 1 "PORT" H 2300 1850 30 0000 C CNN
+F 2 "" H 2300 1850 60 0000 C CNN
+F 3 "" H 2300 1850 60 0000 C CNN
+ 15 2300 1850
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2550 1600 3650 1600
+Wire Wire Line
+ 3650 1600 3650 1700
+Wire Wire Line
+ 3650 1800 3650 1850
+Wire Wire Line
+ 3650 1850 2550 1850
+$Comp
+L PORT U1
+U 16 1 68681E20
+P 2250 2200
+F 0 "U1" H 2300 2300 30 0000 C CNN
+F 1 "PORT" H 2250 2200 30 0000 C CNN
+F 2 "" H 2250 2200 60 0000 C CNN
+F 3 "" H 2250 2200 60 0000 C CNN
+ 16 2250 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 68681E81
+P 2250 2450
+F 0 "U1" H 2300 2550 30 0000 C CNN
+F 1 "PORT" H 2250 2450 30 0000 C CNN
+F 2 "" H 2250 2450 60 0000 C CNN
+F 3 "" H 2250 2450 60 0000 C CNN
+ 17 2250 2450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2500 2200 3650 2200
+Wire Wire Line
+ 3650 2200 3650 2300
+Wire Wire Line
+ 3650 2400 3650 2450
+Wire Wire Line
+ 3650 2450 2500 2450
+$Comp
+L PORT U1
+U 20 1 68682086
+P 2250 2900
+F 0 "U1" H 2300 3000 30 0000 C CNN
+F 1 "PORT" H 2250 2900 30 0000 C CNN
+F 2 "" H 2250 2900 60 0000 C CNN
+F 3 "" H 2250 2900 60 0000 C CNN
+ 20 2250 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 21 1 686820F1
+P 2250 3100
+F 0 "U1" H 2300 3200 30 0000 C CNN
+F 1 "PORT" H 2250 3100 30 0000 C CNN
+F 2 "" H 2250 3100 60 0000 C CNN
+F 3 "" H 2250 3100 60 0000 C CNN
+ 21 2250 3100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2500 2900 3650 2900
+Wire Wire Line
+ 3650 2900 3650 2950
+Wire Wire Line
+ 3650 3050 3650 3100
+Wire Wire Line
+ 3650 3100 2500 3100
+$Comp
+L PORT U1
+U 22 1 68682267
+P 2300 3500
+F 0 "U1" H 2350 3600 30 0000 C CNN
+F 1 "PORT" H 2300 3500 30 0000 C CNN
+F 2 "" H 2300 3500 60 0000 C CNN
+F 3 "" H 2300 3500 60 0000 C CNN
+ 22 2300 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 23 1 68682310
+P 2300 3700
+F 0 "U1" H 2350 3800 30 0000 C CNN
+F 1 "PORT" H 2300 3700 30 0000 C CNN
+F 2 "" H 2300 3700 60 0000 C CNN
+F 3 "" H 2300 3700 60 0000 C CNN
+ 23 2300 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 24 1 68682390
+P 2250 4150
+F 0 "U1" H 2300 4250 30 0000 C CNN
+F 1 "PORT" H 2250 4150 30 0000 C CNN
+F 2 "" H 2250 4150 60 0000 C CNN
+F 3 "" H 2250 4150 60 0000 C CNN
+ 24 2250 4150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2550 3500 3650 3500
+Wire Wire Line
+ 3650 3500 3650 3550
+Wire Wire Line
+ 3650 3650 3650 3700
+Wire Wire Line
+ 3650 3700 2550 3700
+Wire Wire Line
+ 2500 4150 3650 4150
+Wire Wire Line
+ 3650 4150 3650 4250
+$Comp
+L PORT U1
+U 19 1 68682BB8
+P 1350 5350
+F 0 "U1" H 1400 5450 30 0000 C CNN
+F 1 "PORT" H 1350 5350 30 0000 C CNN
+F 2 "" H 1350 5350 60 0000 C CNN
+F 3 "" H 1350 5350 60 0000 C CNN
+ 19 1350 5350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1600 5350 1700 5350
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/f100102/f100102.sub b/library/SubcircuitLibrary/f100102/f100102.sub
new file mode 100644
index 000000000..e1f542189
--- /dev/null
+++ b/library/SubcircuitLibrary/f100102/f100102.sub
@@ -0,0 +1,70 @@
+* Subcircuit f100102
+.subckt f100102 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_
+* c:\fossee\esim\library\subcircuitlibrary\f100102\f100102.cir
+* u2 net-_u1-pad14_ net-_u1-pad15_ net-_u2-pad3_ d_or
+* u6 net-_u2-pad3_ net-_u15-pad2_ net-_u1-pad13_ d_or
+* u3 net-_u1-pad16_ net-_u1-pad17_ net-_u3-pad3_ d_or
+* u7 net-_u3-pad3_ net-_u15-pad2_ net-_u1-pad10_ d_or
+* u4 net-_u1-pad20_ net-_u1-pad21_ net-_u4-pad3_ d_or
+* u8 net-_u4-pad3_ net-_u15-pad2_ net-_u1-pad9_ d_or
+* u5 net-_u1-pad22_ net-_u1-pad23_ net-_u5-pad3_ d_or
+* u9 net-_u5-pad3_ net-_u15-pad2_ net-_u1-pad5_ d_or
+* u10 net-_u1-pad13_ net-_u1-pad12_ d_inverter
+* u11 net-_u1-pad10_ net-_u1-pad11_ d_inverter
+* u12 net-_u1-pad9_ net-_u1-pad8_ d_inverter
+* u13 net-_u1-pad5_ net-_u1-pad4_ d_inverter
+* u14 net-_u1-pad24_ net-_u1-pad1_ net-_u14-pad3_ d_or
+* u15 net-_u14-pad3_ net-_u15-pad2_ net-_u1-pad2_ d_or
+* u16 net-_u1-pad2_ net-_u1-pad3_ d_inverter
+* u17 net-_u1-pad19_ net-_u15-pad2_ d_buffer
+a1 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u15-pad2_ ] net-_u1-pad13_ u6
+a3 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u3-pad3_ u3
+a4 [net-_u3-pad3_ net-_u15-pad2_ ] net-_u1-pad10_ u7
+a5 [net-_u1-pad20_ net-_u1-pad21_ ] net-_u4-pad3_ u4
+a6 [net-_u4-pad3_ net-_u15-pad2_ ] net-_u1-pad9_ u8
+a7 [net-_u1-pad22_ net-_u1-pad23_ ] net-_u5-pad3_ u5
+a8 [net-_u5-pad3_ net-_u15-pad2_ ] net-_u1-pad5_ u9
+a9 net-_u1-pad13_ net-_u1-pad12_ u10
+a10 net-_u1-pad10_ net-_u1-pad11_ u11
+a11 net-_u1-pad9_ net-_u1-pad8_ u12
+a12 net-_u1-pad5_ net-_u1-pad4_ u13
+a13 [net-_u1-pad24_ net-_u1-pad1_ ] net-_u14-pad3_ u14
+a14 [net-_u14-pad3_ net-_u15-pad2_ ] net-_u1-pad2_ u15
+a15 net-_u1-pad2_ net-_u1-pad3_ u16
+a16 net-_u1-pad19_ net-_u15-pad2_ u17
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u17 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends f100102
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/f100102/f100102_Previous_Values.xml b/library/SubcircuitLibrary/f100102/f100102_Previous_Values.xml
new file mode 100644
index 000000000..178b9dab8
--- /dev/null
+++ b/library/SubcircuitLibrary/f100102/f100102_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025010secmssecd_ord_ord_ord_ord_ord_ord_ord_ord_inverterd_inverterd_inverterd_inverterd_ord_ord_inverterd_buffer
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ic100117/3_and-cache.lib b/library/SubcircuitLibrary/ic100117/3_and-cache.lib
new file mode 100644
index 000000000..af0586415
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/ic100117/3_and.cir b/library/SubcircuitLibrary/ic100117/3_and.cir
new file mode 100644
index 000000000..ba296cf01
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/ic100117/3_and.cir.out b/library/SubcircuitLibrary/ic100117/3_and.cir.out
new file mode 100644
index 000000000..d7cf79a07
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/ic100117/3_and.pro b/library/SubcircuitLibrary/ic100117/3_and.pro
new file mode 100644
index 000000000..00597a5ad
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/ic100117/3_and.sch b/library/SubcircuitLibrary/ic100117/3_and.sch
new file mode 100644
index 000000000..d6ac89f95
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/ic100117/3_and.sub b/library/SubcircuitLibrary/ic100117/3_and.sub
new file mode 100644
index 000000000..3d9120bb6
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ic100117/3_and_Previous_Values.xml b/library/SubcircuitLibrary/ic100117/3_and_Previous_Values.xml
new file mode 100644
index 000000000..abc5faaae
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ic100117/analysis b/library/SubcircuitLibrary/ic100117/analysis
new file mode 100644
index 000000000..eed5e2985
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/analysis
@@ -0,0 +1 @@
+.tran 250e-03 20e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ic100117/ic100117-cache.lib b/library/SubcircuitLibrary/ic100117/ic100117-cache.lib
new file mode 100644
index 000000000..ee93e1956
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/ic100117-cache.lib
@@ -0,0 +1,95 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/ic100117/ic100117.cir b/library/SubcircuitLibrary/ic100117/ic100117.cir
new file mode 100644
index 000000000..e11bd03ad
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/ic100117.cir
@@ -0,0 +1,23 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\ic100117\ic100117.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/10/25 22:41:29
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U5-Pad3_ d_or
+U6 Net-_U1-Pad24_ Net-_U1-Pad1_ Net-_U6-Pad3_ d_or
+X3 Net-_U5-Pad3_ Net-_U6-Pad3_ Net-_U1-Pad19_ Net-_U1-Pad4_ 3_and
+U9 Net-_U1-Pad4_ Net-_U1-Pad5_ d_inverter
+U10 Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U10-Pad3_ d_or
+U2 Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U2-Pad3_ d_or
+X1 Net-_U10-Pad3_ Net-_U2-Pad3_ Net-_U1-Pad17_ Net-_U1-Pad8_ 3_and
+U7 Net-_U1-Pad8_ Net-_U1-Pad9_ d_inverter
+U3 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U3-Pad3_ d_or
+U4 Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U4-Pad3_ d_or
+X2 Net-_U3-Pad3_ Net-_U4-Pad3_ Net-_U1-Pad16_ Net-_U1-Pad11_ 3_and
+U8 Net-_U1-Pad11_ Net-_U1-Pad10_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U1-Pad24_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/ic100117/ic100117.cir.out b/library/SubcircuitLibrary/ic100117/ic100117.cir.out
new file mode 100644
index 000000000..b989016d0
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/ic100117.cir.out
@@ -0,0 +1,52 @@
+* c:\fossee\esim\library\subcircuitlibrary\ic100117\ic100117.cir
+
+.include 3_and.sub
+* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_or
+* u6 net-_u1-pad24_ net-_u1-pad1_ net-_u6-pad3_ d_or
+x3 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad19_ net-_u1-pad4_ 3_and
+* u9 net-_u1-pad4_ net-_u1-pad5_ d_inverter
+* u10 net-_u1-pad22_ net-_u1-pad23_ net-_u10-pad3_ d_or
+* u2 net-_u1-pad20_ net-_u1-pad21_ net-_u2-pad3_ d_or
+x1 net-_u10-pad3_ net-_u2-pad3_ net-_u1-pad17_ net-_u1-pad8_ 3_and
+* u7 net-_u1-pad8_ net-_u1-pad9_ d_inverter
+* u3 net-_u1-pad12_ net-_u1-pad13_ net-_u3-pad3_ d_or
+* u4 net-_u1-pad14_ net-_u1-pad15_ net-_u4-pad3_ d_or
+x2 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad16_ net-_u1-pad11_ 3_and
+* u8 net-_u1-pad11_ net-_u1-pad10_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_ port
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5
+a2 [net-_u1-pad24_ net-_u1-pad1_ ] net-_u6-pad3_ u6
+a3 net-_u1-pad4_ net-_u1-pad5_ u9
+a4 [net-_u1-pad22_ net-_u1-pad23_ ] net-_u10-pad3_ u10
+a5 [net-_u1-pad20_ net-_u1-pad21_ ] net-_u2-pad3_ u2
+a6 net-_u1-pad8_ net-_u1-pad9_ u7
+a7 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u4-pad3_ u4
+a9 net-_u1-pad11_ net-_u1-pad10_ u8
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 250e-03 20e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/ic100117/ic100117.pro b/library/SubcircuitLibrary/ic100117/ic100117.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/ic100117.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/ic100117/ic100117.sch b/library/SubcircuitLibrary/ic100117/ic100117.sch
new file mode 100644
index 000000000..eab919cf8
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/ic100117.sch
@@ -0,0 +1,506 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U5
+U 1 1 686FF152
+P 4250 2550
+F 0 "U5" H 4250 2550 60 0000 C CNN
+F 1 "d_or" H 4250 2650 60 0000 C CNN
+F 2 "" H 4250 2550 60 0000 C CNN
+F 3 "" H 4250 2550 60 0000 C CNN
+ 1 4250 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U6
+U 1 1 686FF177
+P 4250 3000
+F 0 "U6" H 4250 3000 60 0000 C CNN
+F 1 "d_or" H 4250 3100 60 0000 C CNN
+F 2 "" H 4250 3000 60 0000 C CNN
+F 3 "" H 4250 3000 60 0000 C CNN
+ 1 4250 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X3
+U 1 1 686FF19E
+P 5550 2750
+F 0 "X3" H 5650 2700 60 0000 C CNN
+F 1 "3_and" H 5700 2900 60 0000 C CNN
+F 2 "" H 5550 2750 60 0000 C CNN
+F 3 "" H 5550 2750 60 0000 C CNN
+ 1 5550 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 686FF1F7
+P 6900 2700
+F 0 "U9" H 6900 2600 60 0000 C CNN
+F 1 "d_inverter" H 6900 2850 60 0000 C CNN
+F 2 "" H 6950 2650 60 0000 C CNN
+F 3 "" H 6950 2650 60 0000 C CNN
+ 1 6900 2700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4700 2500 5200 2500
+Wire Wire Line
+ 5200 2500 5200 2600
+Wire Wire Line
+ 4700 2950 4700 2700
+Wire Wire Line
+ 4700 2700 5200 2700
+Wire Wire Line
+ 5200 3250 5200 2800
+Wire Wire Line
+ 3350 3250 5200 3250
+Wire Wire Line
+ 6050 2700 6600 2700
+Wire Wire Line
+ 6300 2700 6300 3150
+Wire Wire Line
+ 6300 3150 7450 3150
+Connection ~ 6300 2700
+$Comp
+L d_or U10
+U 1 1 686FF420
+P 4150 3750
+F 0 "U10" H 4150 3750 60 0000 C CNN
+F 1 "d_or" H 4150 3850 60 0000 C CNN
+F 2 "" H 4150 3750 60 0000 C CNN
+F 3 "" H 4150 3750 60 0000 C CNN
+ 1 4150 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U2
+U 1 1 686FF426
+P 4150 4200
+F 0 "U2" H 4150 4200 60 0000 C CNN
+F 1 "d_or" H 4150 4300 60 0000 C CNN
+F 2 "" H 4150 4200 60 0000 C CNN
+F 3 "" H 4150 4200 60 0000 C CNN
+ 1 4150 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X1
+U 1 1 686FF42C
+P 5450 3950
+F 0 "X1" H 5550 3900 60 0000 C CNN
+F 1 "3_and" H 5600 4100 60 0000 C CNN
+F 2 "" H 5450 3950 60 0000 C CNN
+F 3 "" H 5450 3950 60 0000 C CNN
+ 1 5450 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U7
+U 1 1 686FF432
+P 6800 3900
+F 0 "U7" H 6800 3800 60 0000 C CNN
+F 1 "d_inverter" H 6800 4050 60 0000 C CNN
+F 2 "" H 6850 3850 60 0000 C CNN
+F 3 "" H 6850 3850 60 0000 C CNN
+ 1 6800 3900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4600 3700 5100 3700
+Wire Wire Line
+ 5100 3700 5100 3800
+Wire Wire Line
+ 4600 4150 4600 3900
+Wire Wire Line
+ 4600 3900 5100 3900
+Wire Wire Line
+ 5100 4450 5100 4000
+Wire Wire Line
+ 3400 4450 5100 4450
+Wire Wire Line
+ 5950 3900 6500 3900
+Wire Wire Line
+ 6200 3900 6200 4350
+Wire Wire Line
+ 6200 4350 7400 4350
+Connection ~ 6200 3900
+$Comp
+L d_or U3
+U 1 1 686FF4EE
+P 4150 4900
+F 0 "U3" H 4150 4900 60 0000 C CNN
+F 1 "d_or" H 4150 5000 60 0000 C CNN
+F 2 "" H 4150 4900 60 0000 C CNN
+F 3 "" H 4150 4900 60 0000 C CNN
+ 1 4150 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 686FF4F4
+P 4150 5350
+F 0 "U4" H 4150 5350 60 0000 C CNN
+F 1 "d_or" H 4150 5450 60 0000 C CNN
+F 2 "" H 4150 5350 60 0000 C CNN
+F 3 "" H 4150 5350 60 0000 C CNN
+ 1 4150 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X2
+U 1 1 686FF4FA
+P 5450 5100
+F 0 "X2" H 5550 5050 60 0000 C CNN
+F 1 "3_and" H 5600 5250 60 0000 C CNN
+F 2 "" H 5450 5100 60 0000 C CNN
+F 3 "" H 5450 5100 60 0000 C CNN
+ 1 5450 5100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U8
+U 1 1 686FF500
+P 6800 5050
+F 0 "U8" H 6800 4950 60 0000 C CNN
+F 1 "d_inverter" H 6800 5200 60 0000 C CNN
+F 2 "" H 6850 5000 60 0000 C CNN
+F 3 "" H 6850 5000 60 0000 C CNN
+ 1 6800 5050
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4600 4850 5100 4850
+Wire Wire Line
+ 5100 4850 5100 4950
+Wire Wire Line
+ 4600 5300 4600 5050
+Wire Wire Line
+ 4600 5050 5100 5050
+Wire Wire Line
+ 5100 5600 5100 5150
+Wire Wire Line
+ 3350 5600 5100 5600
+Wire Wire Line
+ 5950 5050 6500 5050
+Wire Wire Line
+ 6200 5050 6200 5500
+Wire Wire Line
+ 6200 5500 7450 5500
+Connection ~ 6200 5050
+$Comp
+L PORT U1
+U 1 1 686FF57E
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 1 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686FF5CF
+P 3100 2450
+F 0 "U1" H 3150 2550 30 0000 C CNN
+F 1 "PORT" H 3100 2450 30 0000 C CNN
+F 2 "" H 3100 2450 60 0000 C CNN
+F 3 "" H 3100 2450 60 0000 C CNN
+ 2 3100 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686FF67C
+P 2750 2550
+F 0 "U1" H 2800 2650 30 0000 C CNN
+F 1 "PORT" H 2750 2550 30 0000 C CNN
+F 2 "" H 2750 2550 60 0000 C CNN
+F 3 "" H 2750 2550 60 0000 C CNN
+ 3 2750 2550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686FF6C9
+P 7700 3150
+F 0 "U1" H 7750 3250 30 0000 C CNN
+F 1 "PORT" H 7700 3150 30 0000 C CNN
+F 2 "" H 7700 3150 60 0000 C CNN
+F 3 "" H 7700 3150 60 0000 C CNN
+ 4 7700 3150
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686FF7B4
+P 7700 2700
+F 0 "U1" H 7750 2800 30 0000 C CNN
+F 1 "PORT" H 7700 2700 30 0000 C CNN
+F 2 "" H 7700 2700 60 0000 C CNN
+F 3 "" H 7700 2700 60 0000 C CNN
+ 5 7700 2700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 686FF8EF
+P 7650 4350
+F 0 "U1" H 7700 4450 30 0000 C CNN
+F 1 "PORT" H 7650 4350 30 0000 C CNN
+F 2 "" H 7650 4350 60 0000 C CNN
+F 3 "" H 7650 4350 60 0000 C CNN
+ 8 7650 4350
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686FFA28
+P 7650 3900
+F 0 "U1" H 7700 4000 30 0000 C CNN
+F 1 "PORT" H 7650 3900 30 0000 C CNN
+F 2 "" H 7650 3900 60 0000 C CNN
+F 3 "" H 7650 3900 60 0000 C CNN
+ 9 7650 3900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686FFA7D
+P 7700 5050
+F 0 "U1" H 7750 5150 30 0000 C CNN
+F 1 "PORT" H 7700 5050 30 0000 C CNN
+F 2 "" H 7700 5050 60 0000 C CNN
+F 3 "" H 7700 5050 60 0000 C CNN
+ 10 7700 5050
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686FFB76
+P 7700 5500
+F 0 "U1" H 7750 5600 30 0000 C CNN
+F 1 "PORT" H 7700 5500 30 0000 C CNN
+F 2 "" H 7700 5500 60 0000 C CNN
+F 3 "" H 7700 5500 60 0000 C CNN
+ 11 7700 5500
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686FFBC3
+P 3150 4800
+F 0 "U1" H 3200 4900 30 0000 C CNN
+F 1 "PORT" H 3150 4800 30 0000 C CNN
+F 2 "" H 3150 4800 60 0000 C CNN
+F 3 "" H 3150 4800 60 0000 C CNN
+ 12 3150 4800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686FFD46
+P 2850 4900
+F 0 "U1" H 2900 5000 30 0000 C CNN
+F 1 "PORT" H 2850 4900 30 0000 C CNN
+F 2 "" H 2850 4900 60 0000 C CNN
+F 3 "" H 2850 4900 60 0000 C CNN
+ 13 2850 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 686FFDC4
+P 3150 5250
+F 0 "U1" H 3200 5350 30 0000 C CNN
+F 1 "PORT" H 3150 5250 30 0000 C CNN
+F 2 "" H 3150 5250 60 0000 C CNN
+F 3 "" H 3150 5250 60 0000 C CNN
+ 14 3150 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 686FFE4F
+P 2800 5350
+F 0 "U1" H 2850 5450 30 0000 C CNN
+F 1 "PORT" H 2800 5350 30 0000 C CNN
+F 2 "" H 2800 5350 60 0000 C CNN
+F 3 "" H 2800 5350 60 0000 C CNN
+ 15 2800 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 686FFEA4
+P 3100 5600
+F 0 "U1" H 3150 5700 30 0000 C CNN
+F 1 "PORT" H 3100 5600 30 0000 C CNN
+F 2 "" H 3100 5600 60 0000 C CNN
+F 3 "" H 3100 5600 60 0000 C CNN
+ 16 3100 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 686FFF0B
+P 3150 4450
+F 0 "U1" H 3200 4550 30 0000 C CNN
+F 1 "PORT" H 3150 4450 30 0000 C CNN
+F 2 "" H 3150 4450 60 0000 C CNN
+F 3 "" H 3150 4450 60 0000 C CNN
+ 17 3150 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 19 1 6870003B
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 19 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 20 1 68700186
+P 3000 4100
+F 0 "U1" H 3050 4200 30 0000 C CNN
+F 1 "PORT" H 3000 4100 30 0000 C CNN
+F 2 "" H 3000 4100 60 0000 C CNN
+F 3 "" H 3000 4100 60 0000 C CNN
+ 20 3000 4100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 21 1 6870025E
+P 2800 4200
+F 0 "U1" H 2850 4300 30 0000 C CNN
+F 1 "PORT" H 2800 4200 30 0000 C CNN
+F 2 "" H 2800 4200 60 0000 C CNN
+F 3 "" H 2800 4200 60 0000 C CNN
+ 21 2800 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 22 1 687002CF
+P 3100 3650
+F 0 "U1" H 3150 3750 30 0000 C CNN
+F 1 "PORT" H 3100 3650 30 0000 C CNN
+F 2 "" H 3100 3650 60 0000 C CNN
+F 3 "" H 3100 3650 60 0000 C CNN
+ 22 3100 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 23 1 68700328
+P 2850 3750
+F 0 "U1" H 2900 3850 30 0000 C CNN
+F 1 "PORT" H 2850 3750 30 0000 C CNN
+F 2 "" H 2850 3750 60 0000 C CNN
+F 3 "" H 2850 3750 60 0000 C CNN
+ 23 2850 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 24 1 6870038D
+P 2700 2900
+F 0 "U1" H 2750 3000 30 0000 C CNN
+F 1 "PORT" H 2700 2900 30 0000 C CNN
+F 2 "" H 2700 2900 60 0000 C CNN
+F 3 "" H 2700 2900 60 0000 C CNN
+ 24 2700 2900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3350 2450 3800 2450
+Wire Wire Line
+ 3800 2550 3000 2550
+Wire Wire Line
+ 3800 2900 2950 2900
+Wire Wire Line
+ 3350 3000 3800 3000
+Wire Wire Line
+ 3350 3650 3700 3650
+Wire Wire Line
+ 3700 3750 3100 3750
+Wire Wire Line
+ 3250 4100 3700 4100
+Wire Wire Line
+ 3700 4200 3050 4200
+Wire Wire Line
+ 3700 4800 3400 4800
+Wire Wire Line
+ 3700 4900 3100 4900
+Wire Wire Line
+ 3700 5250 3400 5250
+Wire Wire Line
+ 3700 5350 3050 5350
+Wire Wire Line
+ 7200 2700 7450 2700
+Wire Wire Line
+ 7400 3900 7100 3900
+Wire Wire Line
+ 7450 5050 7100 5050
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/ic100117/ic100117.sub b/library/SubcircuitLibrary/ic100117/ic100117.sub
new file mode 100644
index 000000000..5ceb0b370
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/ic100117.sub
@@ -0,0 +1,46 @@
+* Subcircuit ic100117
+.subckt ic100117 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ net-_u1-pad24_
+* c:\fossee\esim\library\subcircuitlibrary\ic100117\ic100117.cir
+.include 3_and.sub
+* u5 net-_u1-pad2_ net-_u1-pad3_ net-_u5-pad3_ d_or
+* u6 net-_u1-pad24_ net-_u1-pad1_ net-_u6-pad3_ d_or
+x3 net-_u5-pad3_ net-_u6-pad3_ net-_u1-pad19_ net-_u1-pad4_ 3_and
+* u9 net-_u1-pad4_ net-_u1-pad5_ d_inverter
+* u10 net-_u1-pad22_ net-_u1-pad23_ net-_u10-pad3_ d_or
+* u2 net-_u1-pad20_ net-_u1-pad21_ net-_u2-pad3_ d_or
+x1 net-_u10-pad3_ net-_u2-pad3_ net-_u1-pad17_ net-_u1-pad8_ 3_and
+* u7 net-_u1-pad8_ net-_u1-pad9_ d_inverter
+* u3 net-_u1-pad12_ net-_u1-pad13_ net-_u3-pad3_ d_or
+* u4 net-_u1-pad14_ net-_u1-pad15_ net-_u4-pad3_ d_or
+x2 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad16_ net-_u1-pad11_ 3_and
+* u8 net-_u1-pad11_ net-_u1-pad10_ d_inverter
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u5-pad3_ u5
+a2 [net-_u1-pad24_ net-_u1-pad1_ ] net-_u6-pad3_ u6
+a3 net-_u1-pad4_ net-_u1-pad5_ u9
+a4 [net-_u1-pad22_ net-_u1-pad23_ ] net-_u10-pad3_ u10
+a5 [net-_u1-pad20_ net-_u1-pad21_ ] net-_u2-pad3_ u2
+a6 net-_u1-pad8_ net-_u1-pad9_ u7
+a7 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u3-pad3_ u3
+a8 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u4-pad3_ u4
+a9 net-_u1-pad11_ net-_u1-pad10_ u8
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u6 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends ic100117
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/ic100117/ic100117_Previous_Values.xml b/library/SubcircuitLibrary/ic100117/ic100117_Previous_Values.xml
new file mode 100644
index 000000000..3e80f3732
--- /dev/null
+++ b/library/SubcircuitLibrary/ic100117/ic100117_Previous_Values.xml
@@ -0,0 +1 @@
+d_ord_ord_inverterd_ord_ord_inverterd_ord_ord_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes025020secmssec
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/mc1496/NPN.lib b/library/SubcircuitLibrary/mc1496/NPN.lib
new file mode 100644
index 000000000..be5f3073a
--- /dev/null
+++ b/library/SubcircuitLibrary/mc1496/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/mc1496/analysis b/library/SubcircuitLibrary/mc1496/analysis
new file mode 100644
index 000000000..6dcba7452
--- /dev/null
+++ b/library/SubcircuitLibrary/mc1496/analysis
@@ -0,0 +1 @@
+.tran 0.1e-06 10e-03 0e-03
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/mc1496/mc1496-cache.lib b/library/SubcircuitLibrary/mc1496/mc1496-cache.lib
new file mode 100644
index 000000000..e95e63c62
--- /dev/null
+++ b/library/SubcircuitLibrary/mc1496/mc1496-cache.lib
@@ -0,0 +1,83 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/mc1496/mc1496.cir b/library/SubcircuitLibrary/mc1496/mc1496.cir
new file mode 100644
index 000000000..b9067a27b
--- /dev/null
+++ b/library/SubcircuitLibrary/mc1496/mc1496.cir
@@ -0,0 +1,23 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1496\mc1496.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/12/25 22:39:35
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+Q5 Net-_Q5-Pad1_ Net-_Q5-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+Q6 Net-_Q2-Pad1_ Net-_Q5-Pad2_ Net-_Q6-Pad3_ eSim_NPN
+Q9 Net-_Q5-Pad1_ Net-_Q2-Pad2_ Net-_Q6-Pad3_ eSim_NPN
+Q3 Net-_Q2-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
+Q4 Net-_Q3-Pad3_ Net-_Q1-Pad1_ Net-_Q4-Pad3_ eSim_NPN
+Q7 Net-_Q6-Pad3_ Net-_Q7-Pad2_ Net-_Q7-Pad3_ eSim_NPN
+Q8 Net-_Q7-Pad3_ Net-_Q1-Pad1_ Net-_Q8-Pad3_ eSim_NPN
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q1-Pad3_ eSim_NPN
+R2 Net-_Q4-Pad3_ Net-_R1-Pad2_ 500
+R1 Net-_Q1-Pad3_ Net-_R1-Pad2_ 500
+R3 Net-_Q8-Pad3_ Net-_R1-Pad2_ 500
+U1 Net-_Q7-Pad2_ Net-_Q7-Pad3_ Net-_Q3-Pad3_ Net-_Q3-Pad2_ Net-_Q1-Pad1_ Net-_Q2-Pad1_ ? Net-_Q2-Pad2_ ? Net-_Q5-Pad2_ ? Net-_Q5-Pad1_ ? Net-_R1-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/mc1496/mc1496.cir.out b/library/SubcircuitLibrary/mc1496/mc1496.cir.out
new file mode 100644
index 000000000..c0008ca7c
--- /dev/null
+++ b/library/SubcircuitLibrary/mc1496/mc1496.cir.out
@@ -0,0 +1,25 @@
+* c:\fossee\esim\library\subcircuitlibrary\mc1496\mc1496.cir
+
+.include NPN.lib
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q5 net-_q5-pad1_ net-_q5-pad2_ net-_q2-pad3_ Q2N2222
+q6 net-_q2-pad1_ net-_q5-pad2_ net-_q6-pad3_ Q2N2222
+q9 net-_q5-pad1_ net-_q2-pad2_ net-_q6-pad3_ Q2N2222
+q3 net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+q4 net-_q3-pad3_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222
+q7 net-_q6-pad3_ net-_q7-pad2_ net-_q7-pad3_ Q2N2222
+q8 net-_q7-pad3_ net-_q1-pad1_ net-_q8-pad3_ Q2N2222
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222
+r2 net-_q4-pad3_ net-_r1-pad2_ 500
+r1 net-_q1-pad3_ net-_r1-pad2_ 500
+r3 net-_q8-pad3_ net-_r1-pad2_ 500
+* u1 net-_q7-pad2_ net-_q7-pad3_ net-_q3-pad3_ net-_q3-pad2_ net-_q1-pad1_ net-_q2-pad1_ ? net-_q2-pad2_ ? net-_q5-pad2_ ? net-_q5-pad1_ ? net-_r1-pad2_ port
+.tran 0.1e-06 10e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/mc1496/mc1496.pro b/library/SubcircuitLibrary/mc1496/mc1496.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/mc1496/mc1496.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/mc1496/mc1496.sch b/library/SubcircuitLibrary/mc1496/mc1496.sch
new file mode 100644
index 000000000..f020d21a7
--- /dev/null
+++ b/library/SubcircuitLibrary/mc1496/mc1496.sch
@@ -0,0 +1,442 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:mc1496-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q2
+U 1 1 684ADEF2
+P 5350 2400
+F 0 "Q2" H 5250 2450 50 0000 R CNN
+F 1 "eSim_NPN" H 5300 2550 50 0000 R CNN
+F 2 "" H 5550 2500 29 0000 C CNN
+F 3 "" H 5350 2400 60 0000 C CNN
+ 1 5350 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 684ADF85
+P 6050 2400
+F 0 "Q5" H 5950 2450 50 0000 R CNN
+F 1 "eSim_NPN" H 6000 2550 50 0000 R CNN
+F 2 "" H 6250 2500 29 0000 C CNN
+F 3 "" H 6050 2400 60 0000 C CNN
+ 1 6050 2400
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 684AE05C
+P 7100 2400
+F 0 "Q6" H 7000 2450 50 0000 R CNN
+F 1 "eSim_NPN" H 7050 2550 50 0000 R CNN
+F 2 "" H 7300 2500 29 0000 C CNN
+F 3 "" H 7100 2400 60 0000 C CNN
+ 1 7100 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 684AE062
+P 7800 2400
+F 0 "Q9" H 7700 2450 50 0000 R CNN
+F 1 "eSim_NPN" H 7750 2550 50 0000 R CNN
+F 2 "" H 8000 2500 29 0000 C CNN
+F 3 "" H 7800 2400 60 0000 C CNN
+ 1 7800 2400
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 684AE0CE
+P 5600 3050
+F 0 "Q3" H 5500 3100 50 0000 R CNN
+F 1 "eSim_NPN" H 5550 3200 50 0000 R CNN
+F 2 "" H 5800 3150 29 0000 C CNN
+F 3 "" H 5600 3050 60 0000 C CNN
+ 1 5600 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 684AE0F9
+P 5600 3850
+F 0 "Q4" H 5500 3900 50 0000 R CNN
+F 1 "eSim_NPN" H 5550 4000 50 0000 R CNN
+F 2 "" H 5800 3950 29 0000 C CNN
+F 3 "" H 5600 3850 60 0000 C CNN
+ 1 5600 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 684AE124
+P 7400 3050
+F 0 "Q7" H 7300 3100 50 0000 R CNN
+F 1 "eSim_NPN" H 7350 3200 50 0000 R CNN
+F 2 "" H 7600 3150 29 0000 C CNN
+F 3 "" H 7400 3050 60 0000 C CNN
+ 1 7400 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 684AE15D
+P 7400 3850
+F 0 "Q8" H 7300 3900 50 0000 R CNN
+F 1 "eSim_NPN" H 7350 4000 50 0000 R CNN
+F 2 "" H 7600 3950 29 0000 C CNN
+F 3 "" H 7400 3850 60 0000 C CNN
+ 1 7400 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 684AE198
+P 4850 4050
+F 0 "Q1" H 4750 4100 50 0000 R CNN
+F 1 "eSim_NPN" H 4800 4200 50 0000 R CNN
+F 2 "" H 5050 4150 29 0000 C CNN
+F 3 "" H 4850 4050 60 0000 C CNN
+ 1 4850 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 684AE385
+P 5650 4400
+F 0 "R2" H 5700 4530 50 0000 C CNN
+F 1 "500" H 5700 4350 50 0000 C CNN
+F 2 "" H 5700 4380 30 0000 C CNN
+F 3 "" V 5700 4450 30 0000 C CNN
+ 1 5650 4400
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R1
+U 1 1 684AE3CA
+P 4900 4400
+F 0 "R1" H 4950 4530 50 0000 C CNN
+F 1 "500" H 4950 4350 50 0000 C CNN
+F 2 "" H 4950 4380 30 0000 C CNN
+F 3 "" V 4950 4450 30 0000 C CNN
+ 1 4900 4400
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R3
+U 1 1 684AE411
+P 7450 4400
+F 0 "R3" H 7500 4530 50 0000 C CNN
+F 1 "500" H 7500 4350 50 0000 C CNN
+F 2 "" H 7500 4380 30 0000 C CNN
+F 3 "" V 7500 4450 30 0000 C CNN
+ 1 7450 4400
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 1 1 684AE863
+P 4250 3400
+F 0 "U1" H 4300 3500 30 0000 C CNN
+F 1 "PORT" H 4250 3400 30 0000 C CNN
+F 2 "" H 4250 3400 60 0000 C CNN
+F 3 "" H 4250 3400 60 0000 C CNN
+ 1 4250 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 684AEA59
+P 8400 3300
+F 0 "U1" H 8450 3400 30 0000 C CNN
+F 1 "PORT" H 8400 3300 30 0000 C CNN
+F 2 "" H 8400 3300 60 0000 C CNN
+F 3 "" H 8400 3300 60 0000 C CNN
+ 2 8400 3300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 684AEA98
+P 8400 3550
+F 0 "U1" H 8450 3650 30 0000 C CNN
+F 1 "PORT" H 8400 3550 30 0000 C CNN
+F 2 "" H 8400 3550 60 0000 C CNN
+F 3 "" H 8400 3550 60 0000 C CNN
+ 3 8400 3550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 684AEB4A
+P 4250 3050
+F 0 "U1" H 4300 3150 30 0000 C CNN
+F 1 "PORT" H 4250 3050 30 0000 C CNN
+F 2 "" H 4250 3050 60 0000 C CNN
+F 3 "" H 4250 3050 60 0000 C CNN
+ 4 4250 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 684AEC45
+P 3950 3850
+F 0 "U1" H 4000 3950 30 0000 C CNN
+F 1 "PORT" H 3950 3850 30 0000 C CNN
+F 2 "" H 3950 3850 60 0000 C CNN
+F 3 "" H 3950 3850 60 0000 C CNN
+ 5 3950 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 684AECBB
+P 5450 1350
+F 0 "U1" H 5500 1450 30 0000 C CNN
+F 1 "PORT" H 5450 1350 30 0000 C CNN
+F 2 "" H 5450 1350 60 0000 C CNN
+F 3 "" H 5450 1350 60 0000 C CNN
+ 6 5450 1350
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 7 1 684AED24
+P 3000 1050
+F 0 "U1" H 3050 1150 30 0000 C CNN
+F 1 "PORT" H 3000 1050 30 0000 C CNN
+F 2 "" H 3000 1050 60 0000 C CNN
+F 3 "" H 3000 1050 60 0000 C CNN
+ 7 3000 1050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 684AEDED
+P 4250 2650
+F 0 "U1" H 4300 2750 30 0000 C CNN
+F 1 "PORT" H 4250 2650 30 0000 C CNN
+F 2 "" H 4250 2650 60 0000 C CNN
+F 3 "" H 4250 2650 60 0000 C CNN
+ 8 4250 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 684AEE7E
+P 3000 1350
+F 0 "U1" H 3050 1450 30 0000 C CNN
+F 1 "PORT" H 3000 1350 30 0000 C CNN
+F 2 "" H 3000 1350 60 0000 C CNN
+F 3 "" H 3000 1350 60 0000 C CNN
+ 9 3000 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 684AEEC3
+P 4250 2450
+F 0 "U1" H 4300 2550 30 0000 C CNN
+F 1 "PORT" H 4250 2450 30 0000 C CNN
+F 2 "" H 4250 2450 60 0000 C CNN
+F 3 "" H 4250 2450 60 0000 C CNN
+ 10 4250 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 684AEF8E
+P 3000 1650
+F 0 "U1" H 3050 1750 30 0000 C CNN
+F 1 "PORT" H 3000 1650 30 0000 C CNN
+F 2 "" H 3000 1650 60 0000 C CNN
+F 3 "" H 3000 1650 60 0000 C CNN
+ 11 3000 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 684AEFFD
+P 7700 1100
+F 0 "U1" H 7750 1200 30 0000 C CNN
+F 1 "PORT" H 7700 1100 30 0000 C CNN
+F 2 "" H 7700 1100 60 0000 C CNN
+F 3 "" H 7700 1100 60 0000 C CNN
+ 12 7700 1100
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 13 1 684AF0F2
+P 3000 1900
+F 0 "U1" H 3050 2000 30 0000 C CNN
+F 1 "PORT" H 3000 1900 30 0000 C CNN
+F 2 "" H 3000 1900 60 0000 C CNN
+F 3 "" H 3000 1900 60 0000 C CNN
+ 13 3000 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 684AF1C4
+P 4350 4750
+F 0 "U1" H 4400 4850 30 0000 C CNN
+F 1 "PORT" H 4350 4750 30 0000 C CNN
+F 2 "" H 4350 4750 60 0000 C CNN
+F 3 "" H 4350 4750 60 0000 C CNN
+ 14 4350 4750
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5450 2600 5450 2750
+Wire Wire Line
+ 5450 2750 5950 2750
+Wire Wire Line
+ 5950 2750 5950 2600
+Wire Wire Line
+ 5700 2850 5700 2750
+Connection ~ 5700 2750
+Wire Wire Line
+ 7200 2600 7200 2750
+Wire Wire Line
+ 7200 2750 7700 2750
+Wire Wire Line
+ 7700 2750 7700 2600
+Wire Wire Line
+ 7500 2850 7500 2750
+Connection ~ 7500 2750
+Wire Wire Line
+ 5700 3250 5700 3650
+Wire Wire Line
+ 7500 3250 7500 3650
+Wire Wire Line
+ 6250 2400 6900 2400
+Wire Wire Line
+ 5450 1600 5450 2200
+Wire Wire Line
+ 5450 1900 7200 1900
+Wire Wire Line
+ 7700 1350 7700 2200
+Wire Wire Line
+ 5950 2200 5950 2000
+Wire Wire Line
+ 5950 2000 7700 2000
+Wire Wire Line
+ 5150 2400 5150 2650
+Wire Wire Line
+ 4500 2650 8000 2650
+Wire Wire Line
+ 8000 2650 8000 2400
+Wire Wire Line
+ 4200 3850 5400 3850
+Wire Wire Line
+ 4950 4300 4950 4250
+Wire Wire Line
+ 5700 4050 5700 4300
+Wire Wire Line
+ 7500 4050 7500 4300
+Wire Wire Line
+ 4950 4600 4950 4750
+Wire Wire Line
+ 4600 4750 7500 4750
+Wire Wire Line
+ 5700 4750 5700 4600
+Wire Wire Line
+ 7500 4750 7500 4600
+Connection ~ 5700 4750
+Wire Wire Line
+ 4650 4050 4300 4050
+Wire Wire Line
+ 4300 4050 4300 3850
+Connection ~ 4950 3850
+Connection ~ 4950 4750
+Connection ~ 4300 3850
+Wire Wire Line
+ 4500 3400 7200 3400
+Wire Wire Line
+ 7200 3400 7200 3050
+Wire Wire Line
+ 4500 3050 5400 3050
+Connection ~ 5150 2650
+Wire Wire Line
+ 4500 2450 4500 2200
+Wire Wire Line
+ 4500 2200 6600 2200
+Wire Wire Line
+ 6600 2200 6600 2400
+Connection ~ 6600 2400
+Connection ~ 5450 1900
+Wire Wire Line
+ 7500 3300 8150 3300
+Connection ~ 7500 3300
+Wire Wire Line
+ 8150 3550 5700 3550
+Connection ~ 5700 3550
+NoConn ~ 3250 1050
+NoConn ~ 3250 1350
+NoConn ~ 3250 1650
+NoConn ~ 3250 1900
+Wire Wire Line
+ 7200 3850 7200 4100
+Wire Wire Line
+ 7200 4100 5300 4100
+Wire Wire Line
+ 5300 4100 5300 3850
+Connection ~ 5300 3850
+Wire Wire Line
+ 7200 1900 7200 2200
+Connection ~ 7700 2000
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/mc1496/mc1496.sub b/library/SubcircuitLibrary/mc1496/mc1496.sub
new file mode 100644
index 000000000..67de09f28
--- /dev/null
+++ b/library/SubcircuitLibrary/mc1496/mc1496.sub
@@ -0,0 +1,19 @@
+* Subcircuit mc1496
+.subckt mc1496 net-_q7-pad2_ net-_q7-pad3_ net-_q3-pad3_ net-_q3-pad2_ net-_q1-pad1_ net-_q2-pad1_ ? net-_q2-pad2_ ? net-_q5-pad2_ ? net-_q5-pad1_ ? net-_r1-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\mc1496\mc1496.cir
+.include NPN.lib
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_q2-pad3_ Q2N2222
+q5 net-_q5-pad1_ net-_q5-pad2_ net-_q2-pad3_ Q2N2222
+q6 net-_q2-pad1_ net-_q5-pad2_ net-_q6-pad3_ Q2N2222
+q9 net-_q5-pad1_ net-_q2-pad2_ net-_q6-pad3_ Q2N2222
+q3 net-_q2-pad3_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222
+q4 net-_q3-pad3_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222
+q7 net-_q6-pad3_ net-_q7-pad2_ net-_q7-pad3_ Q2N2222
+q8 net-_q7-pad3_ net-_q1-pad1_ net-_q8-pad3_ Q2N2222
+q1 net-_q1-pad1_ net-_q1-pad1_ net-_q1-pad3_ Q2N2222
+r2 net-_q4-pad3_ net-_r1-pad2_ 500
+r1 net-_q1-pad3_ net-_r1-pad2_ 500
+r3 net-_q8-pad3_ net-_r1-pad2_ 500
+* Control Statements
+
+.ends mc1496
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/mc1496/mc1496_Previous_Values.xml b/library/SubcircuitLibrary/mc1496/mc1496_Previous_Values.xml
new file mode 100644
index 000000000..c5e4dddb9
--- /dev/null
+++ b/library/SubcircuitLibrary/mc1496/mc1496_Previous_Values.xml
@@ -0,0 +1 @@
+C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.110msusms
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/tc4008bp_ic/analysis b/library/SubcircuitLibrary/tc4008bp_ic/analysis
new file mode 100644
index 000000000..edc4bc4f9
--- /dev/null
+++ b/library/SubcircuitLibrary/tc4008bp_ic/analysis
@@ -0,0 +1 @@
+.tran 200e-03 10e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic-cache.lib b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic-cache.lib
new file mode 100644
index 000000000..e0605f3e5
--- /dev/null
+++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic-cache.lib
@@ -0,0 +1,150 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir
new file mode 100644
index 000000000..400c40b0e
--- /dev/null
+++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir
@@ -0,0 +1,55 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\tc4008bp_ic\tc4008bp_ic.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 07/09/25 23:55:17
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U7 Net-_U1-Pad1_ Net-_U1-Pad15_ Net-_U16-Pad1_ d_nor
+U8 Net-_U1-Pad1_ Net-_U1-Pad15_ Net-_U11-Pad1_ d_nand
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U11-Pad2_ Net-_U16-Pad3_ d_nor
+U20 Net-_U16-Pad3_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_xor
+U30 Net-_U20-Pad3_ Net-_U1-Pad13_ d_inverter
+U50 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U12-Pad1_ d_nor
+U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U14-Pad2_ d_nand
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+U14 Net-_U12-Pad2_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_nand
+U23 Net-_U12-Pad2_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_and
+U33 Net-_U21-Pad2_ Net-_U23-Pad3_ Net-_U20-Pad2_ d_nor
+U21 Net-_U14-Pad2_ Net-_U21-Pad2_ d_inverter
+U24 Net-_U14-Pad3_ Net-_U23-Pad2_ Net-_U24-Pad3_ d_xor
+U34 Net-_U24-Pad3_ Net-_U1-Pad12_ d_inverter
+U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U15-Pad1_ d_nor
+U4 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U22-Pad1_ d_nand
+U9 Net-_U22-Pad1_ Net-_U15-Pad2_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nor
+U26 Net-_U15-Pad1_ Net-_U26-Pad2_ Net-_U26-Pad3_ d_or
+U27 Net-_U15-Pad3_ Net-_U26-Pad2_ Net-_U27-Pad3_ d_xor
+U35 Net-_U22-Pad1_ Net-_U26-Pad3_ Net-_U23-Pad2_ d_nand
+U36 Net-_U27-Pad3_ Net-_U1-Pad11_ d_inverter
+U5 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U10-Pad1_ d_nor
+U6 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U13-Pad2_ d_nand
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U13 Net-_U10-Pad2_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nand
+U25 Net-_U10-Pad2_ Net-_U1-Pad9_ Net-_U25-Pad3_ d_and
+U37 Net-_U29-Pad2_ Net-_U25-Pad3_ Net-_U26-Pad2_ d_nor
+U29 Net-_U13-Pad2_ Net-_U29-Pad2_ d_inverter
+U28 Net-_U13-Pad3_ Net-_U1-Pad9_ Net-_U28-Pad3_ d_xor
+U38 Net-_U28-Pad3_ Net-_U1-Pad10_ d_inverter
+U17 Net-_U15-Pad1_ Net-_U13-Pad2_ Net-_U17-Pad3_ d_or
+U22 Net-_U22-Pad1_ Net-_U17-Pad3_ Net-_U22-Pad3_ d_and
+U32 Net-_U12-Pad1_ Net-_U22-Pad3_ Net-_U32-Pad3_ d_or
+U39 Net-_U14-Pad2_ Net-_U32-Pad3_ Net-_U39-Pad3_ d_and
+U41 Net-_U16-Pad1_ Net-_U39-Pad3_ Net-_U41-Pad3_ d_or
+U42 Net-_U11-Pad1_ Net-_U41-Pad3_ Net-_U42-Pad3_ d_nand
+U43 Net-_U40-Pad3_ Net-_U42-Pad3_ Net-_U43-Pad3_ d_nor
+U44 Net-_U43-Pad3_ Net-_U1-Pad14_ d_inverter
+U19 Net-_U15-Pad1_ Net-_U10-Pad1_ Net-_U19-Pad3_ d_nor
+U18 Net-_U16-Pad1_ Net-_U12-Pad1_ Net-_U18-Pad3_ d_nor
+U31 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U31-Pad3_ d_nor
+U40 Net-_U1-Pad9_ Net-_U31-Pad3_ Net-_U40-Pad3_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir.out b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir.out
new file mode 100644
index 000000000..9c3de971b
--- /dev/null
+++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.cir.out
@@ -0,0 +1,188 @@
+* c:\fossee\esim\library\subcircuitlibrary\tc4008bp_ic\tc4008bp_ic.cir
+
+* u7 net-_u1-pad1_ net-_u1-pad15_ net-_u16-pad1_ d_nor
+* u8 net-_u1-pad1_ net-_u1-pad15_ net-_u11-pad1_ d_nand
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u11-pad2_ net-_u16-pad3_ d_nor
+* u20 net-_u16-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_xor
+* u30 net-_u20-pad3_ net-_u1-pad13_ d_inverter
+* u50 net-_u1-pad2_ net-_u1-pad3_ net-_u12-pad1_ d_nor
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u14-pad2_ d_nand
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u14 net-_u12-pad2_ net-_u14-pad2_ net-_u14-pad3_ d_nand
+* u23 net-_u12-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and
+* u33 net-_u21-pad2_ net-_u23-pad3_ net-_u20-pad2_ d_nor
+* u21 net-_u14-pad2_ net-_u21-pad2_ d_inverter
+* u24 net-_u14-pad3_ net-_u23-pad2_ net-_u24-pad3_ d_xor
+* u34 net-_u24-pad3_ net-_u1-pad12_ d_inverter
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u15-pad1_ d_nor
+* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u22-pad1_ d_nand
+* u9 net-_u22-pad1_ net-_u15-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor
+* u26 net-_u15-pad1_ net-_u26-pad2_ net-_u26-pad3_ d_or
+* u27 net-_u15-pad3_ net-_u26-pad2_ net-_u27-pad3_ d_xor
+* u35 net-_u22-pad1_ net-_u26-pad3_ net-_u23-pad2_ d_nand
+* u36 net-_u27-pad3_ net-_u1-pad11_ d_inverter
+* u5 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad1_ d_nor
+* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u13-pad2_ d_nand
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u13 net-_u10-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_nand
+* u25 net-_u10-pad2_ net-_u1-pad9_ net-_u25-pad3_ d_and
+* u37 net-_u29-pad2_ net-_u25-pad3_ net-_u26-pad2_ d_nor
+* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter
+* u28 net-_u13-pad3_ net-_u1-pad9_ net-_u28-pad3_ d_xor
+* u38 net-_u28-pad3_ net-_u1-pad10_ d_inverter
+* u17 net-_u15-pad1_ net-_u13-pad2_ net-_u17-pad3_ d_or
+* u22 net-_u22-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and
+* u32 net-_u12-pad1_ net-_u22-pad3_ net-_u32-pad3_ d_or
+* u39 net-_u14-pad2_ net-_u32-pad3_ net-_u39-pad3_ d_and
+* u41 net-_u16-pad1_ net-_u39-pad3_ net-_u41-pad3_ d_or
+* u42 net-_u11-pad1_ net-_u41-pad3_ net-_u42-pad3_ d_nand
+* u43 net-_u40-pad3_ net-_u42-pad3_ net-_u43-pad3_ d_nor
+* u44 net-_u43-pad3_ net-_u1-pad14_ d_inverter
+* u19 net-_u15-pad1_ net-_u10-pad1_ net-_u19-pad3_ d_nor
+* u18 net-_u16-pad1_ net-_u12-pad1_ net-_u18-pad3_ d_nor
+* u31 net-_u18-pad3_ net-_u19-pad3_ net-_u31-pad3_ d_nor
+* u40 net-_u1-pad9_ net-_u31-pad3_ net-_u40-pad3_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port
+a1 [net-_u1-pad1_ net-_u1-pad15_ ] net-_u16-pad1_ u7
+a2 [net-_u1-pad1_ net-_u1-pad15_ ] net-_u11-pad1_ u8
+a3 net-_u11-pad1_ net-_u11-pad2_ u11
+a4 [net-_u16-pad1_ net-_u11-pad2_ ] net-_u16-pad3_ u16
+a5 [net-_u16-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a6 net-_u20-pad3_ net-_u1-pad13_ u30
+a7 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u12-pad1_ u50
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u14-pad2_ u2
+a9 net-_u12-pad1_ net-_u12-pad2_ u12
+a10 [net-_u12-pad2_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a11 [net-_u12-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a12 [net-_u21-pad2_ net-_u23-pad3_ ] net-_u20-pad2_ u33
+a13 net-_u14-pad2_ net-_u21-pad2_ u21
+a14 [net-_u14-pad3_ net-_u23-pad2_ ] net-_u24-pad3_ u24
+a15 net-_u24-pad3_ net-_u1-pad12_ u34
+a16 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u15-pad1_ u3
+a17 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u22-pad1_ u4
+a18 net-_u22-pad1_ net-_u15-pad2_ u9
+a19 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a20 [net-_u15-pad1_ net-_u26-pad2_ ] net-_u26-pad3_ u26
+a21 [net-_u15-pad3_ net-_u26-pad2_ ] net-_u27-pad3_ u27
+a22 [net-_u22-pad1_ net-_u26-pad3_ ] net-_u23-pad2_ u35
+a23 net-_u27-pad3_ net-_u1-pad11_ u36
+a24 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad1_ u5
+a25 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u13-pad2_ u6
+a26 net-_u10-pad1_ net-_u10-pad2_ u10
+a27 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a28 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u25-pad3_ u25
+a29 [net-_u29-pad2_ net-_u25-pad3_ ] net-_u26-pad2_ u37
+a30 net-_u13-pad2_ net-_u29-pad2_ u29
+a31 [net-_u13-pad3_ net-_u1-pad9_ ] net-_u28-pad3_ u28
+a32 net-_u28-pad3_ net-_u1-pad10_ u38
+a33 [net-_u15-pad1_ net-_u13-pad2_ ] net-_u17-pad3_ u17
+a34 [net-_u22-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22
+a35 [net-_u12-pad1_ net-_u22-pad3_ ] net-_u32-pad3_ u32
+a36 [net-_u14-pad2_ net-_u32-pad3_ ] net-_u39-pad3_ u39
+a37 [net-_u16-pad1_ net-_u39-pad3_ ] net-_u41-pad3_ u41
+a38 [net-_u11-pad1_ net-_u41-pad3_ ] net-_u42-pad3_ u42
+a39 [net-_u40-pad3_ net-_u42-pad3_ ] net-_u43-pad3_ u43
+a40 net-_u43-pad3_ net-_u1-pad14_ u44
+a41 [net-_u15-pad1_ net-_u10-pad1_ ] net-_u19-pad3_ u19
+a42 [net-_u16-pad1_ net-_u12-pad1_ ] net-_u18-pad3_ u18
+a43 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u31-pad3_ u31
+a44 [net-_u1-pad9_ net-_u31-pad3_ ] net-_u40-pad3_ u40
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u24 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u27 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u28 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 200e-03 10e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.pro b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sch b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sch
new file mode 100644
index 000000000..d784c7685
--- /dev/null
+++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sch
@@ -0,0 +1,1019 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A2 23386 16535
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nor U7
+U 1 1 686EAFDD
+P 10550 6050
+F 0 "U7" H 10550 6050 60 0000 C CNN
+F 1 "d_nor" H 10600 6150 60 0000 C CNN
+F 2 "" H 10550 6050 60 0000 C CNN
+F 3 "" H 10550 6050 60 0000 C CNN
+ 1 10550 6050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U8
+U 1 1 686EAFDE
+P 10550 6550
+F 0 "U8" H 10550 6550 60 0000 C CNN
+F 1 "d_nand" H 10600 6650 60 0000 C CNN
+F 2 "" H 10550 6550 60 0000 C CNN
+F 3 "" H 10550 6550 60 0000 C CNN
+ 1 10550 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U11
+U 1 1 686EAFDF
+P 11750 6500
+F 0 "U11" H 11750 6400 60 0000 C CNN
+F 1 "d_inverter" H 11750 6650 60 0000 C CNN
+F 2 "" H 11800 6450 60 0000 C CNN
+F 3 "" H 11800 6450 60 0000 C CNN
+ 1 11750 6500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U16
+U 1 1 686EAFE0
+P 12950 6250
+F 0 "U16" H 12950 6250 60 0000 C CNN
+F 1 "d_nor" H 13000 6350 60 0000 C CNN
+F 2 "" H 12950 6250 60 0000 C CNN
+F 3 "" H 12950 6250 60 0000 C CNN
+ 1 12950 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U20
+U 1 1 686EAFE1
+P 14250 6300
+F 0 "U20" H 14250 6300 60 0000 C CNN
+F 1 "d_xor" H 14300 6400 47 0000 C CNN
+F 2 "" H 14250 6300 60 0000 C CNN
+F 3 "" H 14250 6300 60 0000 C CNN
+ 1 14250 6300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U30
+U 1 1 686EAFE2
+P 15400 6250
+F 0 "U30" H 15400 6150 60 0000 C CNN
+F 1 "d_inverter" H 15400 6400 60 0000 C CNN
+F 2 "" H 15450 6200 60 0000 C CNN
+F 3 "" H 15450 6200 60 0000 C CNN
+ 1 15400 6250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U50
+U 1 1 686EAFE3
+P 10450 7250
+F 0 "U50" H 10450 7250 60 0000 C CNN
+F 1 "d_nor" H 10500 7350 60 0000 C CNN
+F 2 "" H 10450 7250 60 0000 C CNN
+F 3 "" H 10450 7250 60 0000 C CNN
+ 1 10450 7250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U2
+U 1 1 686EAFE4
+P 10450 7750
+F 0 "U2" H 10450 7750 60 0000 C CNN
+F 1 "d_nand" H 10500 7850 60 0000 C CNN
+F 2 "" H 10450 7750 60 0000 C CNN
+F 3 "" H 10450 7750 60 0000 C CNN
+ 1 10450 7750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U12
+U 1 1 686EAFE5
+P 11750 7200
+F 0 "U12" H 11750 7100 60 0000 C CNN
+F 1 "d_inverter" H 11750 7350 60 0000 C CNN
+F 2 "" H 11800 7150 60 0000 C CNN
+F 3 "" H 11800 7150 60 0000 C CNN
+ 1 11750 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U14
+U 1 1 686EAFE6
+P 12900 7700
+F 0 "U14" H 12900 7700 60 0000 C CNN
+F 1 "d_nand" H 12950 7800 60 0000 C CNN
+F 2 "" H 12900 7700 60 0000 C CNN
+F 3 "" H 12900 7700 60 0000 C CNN
+ 1 12900 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U23
+U 1 1 686EAFE7
+P 14350 7300
+F 0 "U23" H 14350 7300 60 0000 C CNN
+F 1 "d_and" H 14400 7400 60 0000 C CNN
+F 2 "" H 14350 7300 60 0000 C CNN
+F 3 "" H 14350 7300 60 0000 C CNN
+ 1 14350 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U33
+U 1 1 686EAFE8
+P 15600 6950
+F 0 "U33" H 15600 6950 60 0000 C CNN
+F 1 "d_nor" H 15650 7050 60 0000 C CNN
+F 2 "" H 15600 6950 60 0000 C CNN
+F 3 "" H 15600 6950 60 0000 C CNN
+ 1 15600 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 686EAFE9
+P 14300 6850
+F 0 "U21" H 14300 6750 60 0000 C CNN
+F 1 "d_inverter" H 14300 7000 60 0000 C CNN
+F 2 "" H 14350 6800 60 0000 C CNN
+F 3 "" H 14350 6800 60 0000 C CNN
+ 1 14300 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U24
+U 1 1 686EAFEA
+P 14350 7750
+F 0 "U24" H 14350 7750 60 0000 C CNN
+F 1 "d_xor" H 14400 7850 47 0000 C CNN
+F 2 "" H 14350 7750 60 0000 C CNN
+F 3 "" H 14350 7750 60 0000 C CNN
+ 1 14350 7750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U34
+U 1 1 686EAFEB
+P 15600 7700
+F 0 "U34" H 15600 7600 60 0000 C CNN
+F 1 "d_inverter" H 15600 7850 60 0000 C CNN
+F 2 "" H 15650 7650 60 0000 C CNN
+F 3 "" H 15650 7650 60 0000 C CNN
+ 1 15600 7700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U3
+U 1 1 686EAFEC
+P 10450 8650
+F 0 "U3" H 10450 8650 60 0000 C CNN
+F 1 "d_nor" H 10500 8750 60 0000 C CNN
+F 2 "" H 10450 8650 60 0000 C CNN
+F 3 "" H 10450 8650 60 0000 C CNN
+ 1 10450 8650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 686EAFED
+P 10450 9150
+F 0 "U4" H 10450 9150 60 0000 C CNN
+F 1 "d_nand" H 10500 9250 60 0000 C CNN
+F 2 "" H 10450 9150 60 0000 C CNN
+F 3 "" H 10450 9150 60 0000 C CNN
+ 1 10450 9150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U9
+U 1 1 686EAFEE
+P 11650 9100
+F 0 "U9" H 11650 9000 60 0000 C CNN
+F 1 "d_inverter" H 11650 9250 60 0000 C CNN
+F 2 "" H 11700 9050 60 0000 C CNN
+F 3 "" H 11700 9050 60 0000 C CNN
+ 1 11650 9100
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U15
+U 1 1 686EAFEF
+P 12900 8800
+F 0 "U15" H 12900 8800 60 0000 C CNN
+F 1 "d_nor" H 12950 8900 60 0000 C CNN
+F 2 "" H 12900 8800 60 0000 C CNN
+F 3 "" H 12900 8800 60 0000 C CNN
+ 1 12900 8800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U26
+U 1 1 686EAFF0
+P 14450 8600
+F 0 "U26" H 14450 8600 60 0000 C CNN
+F 1 "d_or" H 14450 8700 60 0000 C CNN
+F 2 "" H 14450 8600 60 0000 C CNN
+F 3 "" H 14450 8600 60 0000 C CNN
+ 1 14450 8600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U27
+U 1 1 686EAFF1
+P 14450 9200
+F 0 "U27" H 14450 9200 60 0000 C CNN
+F 1 "d_xor" H 14500 9300 47 0000 C CNN
+F 2 "" H 14450 9200 60 0000 C CNN
+F 3 "" H 14450 9200 60 0000 C CNN
+ 1 14450 9200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U35
+U 1 1 686EAFF2
+P 15700 8350
+F 0 "U35" H 15700 8350 60 0000 C CNN
+F 1 "d_nand" H 15750 8450 60 0000 C CNN
+F 2 "" H 15700 8350 60 0000 C CNN
+F 3 "" H 15700 8350 60 0000 C CNN
+ 1 15700 8350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U36
+U 1 1 686EAFF3
+P 15700 9150
+F 0 "U36" H 15700 9050 60 0000 C CNN
+F 1 "d_inverter" H 15700 9300 60 0000 C CNN
+F 2 "" H 15750 9100 60 0000 C CNN
+F 3 "" H 15750 9100 60 0000 C CNN
+ 1 15700 9150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U5
+U 1 1 686EAFF4
+P 10450 10000
+F 0 "U5" H 10450 10000 60 0000 C CNN
+F 1 "d_nor" H 10500 10100 60 0000 C CNN
+F 2 "" H 10450 10000 60 0000 C CNN
+F 3 "" H 10450 10000 60 0000 C CNN
+ 1 10450 10000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U6
+U 1 1 686EAFF5
+P 10450 10600
+F 0 "U6" H 10450 10600 60 0000 C CNN
+F 1 "d_nand" H 10500 10700 60 0000 C CNN
+F 2 "" H 10450 10600 60 0000 C CNN
+F 3 "" H 10450 10600 60 0000 C CNN
+ 1 10450 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U10
+U 1 1 686EAFF6
+P 11650 9950
+F 0 "U10" H 11650 9850 60 0000 C CNN
+F 1 "d_inverter" H 11650 10100 60 0000 C CNN
+F 2 "" H 11700 9900 60 0000 C CNN
+F 3 "" H 11700 9900 60 0000 C CNN
+ 1 11650 9950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U13
+U 1 1 686EAFF7
+P 12800 10550
+F 0 "U13" H 12800 10550 60 0000 C CNN
+F 1 "d_nand" H 12850 10650 60 0000 C CNN
+F 2 "" H 12800 10550 60 0000 C CNN
+F 3 "" H 12800 10550 60 0000 C CNN
+ 1 12800 10550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U25
+U 1 1 686EAFF8
+P 14350 10050
+F 0 "U25" H 14350 10050 60 0000 C CNN
+F 1 "d_and" H 14400 10150 60 0000 C CNN
+F 2 "" H 14350 10050 60 0000 C CNN
+F 3 "" H 14350 10050 60 0000 C CNN
+ 1 14350 10050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U37
+U 1 1 686EAFF9
+P 15750 9700
+F 0 "U37" H 15750 9700 60 0000 C CNN
+F 1 "d_nor" H 15800 9800 60 0000 C CNN
+F 2 "" H 15750 9700 60 0000 C CNN
+F 3 "" H 15750 9700 60 0000 C CNN
+ 1 15750 9700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U29
+U 1 1 686EAFFA
+P 14700 9600
+F 0 "U29" H 14700 9500 60 0000 C CNN
+F 1 "d_inverter" H 14700 9750 60 0000 C CNN
+F 2 "" H 14750 9550 60 0000 C CNN
+F 3 "" H 14750 9550 60 0000 C CNN
+ 1 14700 9600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xor U28
+U 1 1 686EAFFB
+P 14600 10600
+F 0 "U28" H 14600 10600 60 0000 C CNN
+F 1 "d_xor" H 14650 10700 47 0000 C CNN
+F 2 "" H 14600 10600 60 0000 C CNN
+F 3 "" H 14600 10600 60 0000 C CNN
+ 1 14600 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U38
+U 1 1 686EAFFC
+P 15800 10550
+F 0 "U38" H 15800 10450 60 0000 C CNN
+F 1 "d_inverter" H 15800 10700 60 0000 C CNN
+F 2 "" H 15850 10500 60 0000 C CNN
+F 3 "" H 15850 10500 60 0000 C CNN
+ 1 15800 10550
+ 1 0 0 -1
+$EndComp
+Text Notes 9850 5900 0 60 ~ 0
+b4
+Text Notes 9950 6650 0 60 ~ 0
+a4
+Text Notes 9800 7100 0 60 ~ 0
+b3
+Text Notes 9900 7850 0 60 ~ 0
+a3
+Text Notes 9850 8500 0 60 ~ 0
+b2
+Text Notes 9900 9300 0 60 ~ 0
+a2
+Text Notes 9850 9800 0 60 ~ 0
+b1
+Text Notes 9950 10800 0 60 ~ 0
+a1
+Text Notes 9950 11200 0 60 ~ 0
+cin\n
+$Comp
+L d_or U17
+U 1 1 686EAFFD
+P 13300 5250
+F 0 "U17" H 13300 5250 60 0000 C CNN
+F 1 "d_or" H 13300 5350 60 0000 C CNN
+F 2 "" H 13300 5250 60 0000 C CNN
+F 3 "" H 13300 5250 60 0000 C CNN
+ 1 13300 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U22
+U 1 1 686EAFFE
+P 14350 4950
+F 0 "U22" H 14350 4950 60 0000 C CNN
+F 1 "d_and" H 14400 5050 60 0000 C CNN
+F 2 "" H 14350 4950 60 0000 C CNN
+F 3 "" H 14350 4950 60 0000 C CNN
+ 1 14350 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U32
+U 1 1 686EAFFF
+P 15500 4550
+F 0 "U32" H 15500 4550 60 0000 C CNN
+F 1 "d_or" H 15500 4650 60 0000 C CNN
+F 2 "" H 15500 4550 60 0000 C CNN
+F 3 "" H 15500 4550 60 0000 C CNN
+ 1 15500 4550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U39
+U 1 1 686EB000
+P 16550 4050
+F 0 "U39" H 16550 4050 60 0000 C CNN
+F 1 "d_and" H 16600 4150 60 0000 C CNN
+F 2 "" H 16550 4050 60 0000 C CNN
+F 3 "" H 16550 4050 60 0000 C CNN
+ 1 16550 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U41
+U 1 1 686EB001
+P 17700 3700
+F 0 "U41" H 17700 3700 60 0000 C CNN
+F 1 "d_or" H 17700 3800 60 0000 C CNN
+F 2 "" H 17700 3700 60 0000 C CNN
+F 3 "" H 17700 3700 60 0000 C CNN
+ 1 17700 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U42
+U 1 1 686EB002
+P 18800 3250
+F 0 "U42" H 18800 3250 60 0000 C CNN
+F 1 "d_nand" H 18850 3350 60 0000 C CNN
+F 2 "" H 18800 3250 60 0000 C CNN
+F 3 "" H 18800 3250 60 0000 C CNN
+ 1 18800 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U43
+U 1 1 686EB003
+P 19950 2800
+F 0 "U43" H 19950 2800 60 0000 C CNN
+F 1 "d_nor" H 20000 2900 60 0000 C CNN
+F 2 "" H 19950 2800 60 0000 C CNN
+F 3 "" H 19950 2800 60 0000 C CNN
+ 1 19950 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U44
+U 1 1 686EB004
+P 21000 2750
+F 0 "U44" H 21000 2650 60 0000 C CNN
+F 1 "d_inverter" H 21000 2900 60 0000 C CNN
+F 2 "" H 21050 2700 60 0000 C CNN
+F 3 "" H 21050 2700 60 0000 C CNN
+ 1 21000 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U19
+U 1 1 686EB005
+P 14150 3600
+F 0 "U19" H 14150 3600 60 0000 C CNN
+F 1 "d_nor" H 14200 3700 60 0000 C CNN
+F 2 "" H 14150 3600 60 0000 C CNN
+F 3 "" H 14150 3600 60 0000 C CNN
+ 1 14150 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U18
+U 1 1 686EB006
+P 14150 3000
+F 0 "U18" H 14150 3000 60 0000 C CNN
+F 1 "d_nor" H 14200 3100 60 0000 C CNN
+F 2 "" H 14150 3000 60 0000 C CNN
+F 3 "" H 14150 3000 60 0000 C CNN
+ 1 14150 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U31
+U 1 1 686EB007
+P 15500 3250
+F 0 "U31" H 15500 3250 60 0000 C CNN
+F 1 "d_nor" H 15550 3350 60 0000 C CNN
+F 2 "" H 15500 3250 60 0000 C CNN
+F 3 "" H 15500 3250 60 0000 C CNN
+ 1 15500 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U40
+U 1 1 686EB008
+P 16950 2650
+F 0 "U40" H 16950 2650 60 0000 C CNN
+F 1 "d_and" H 17000 2750 60 0000 C CNN
+F 2 "" H 16950 2650 60 0000 C CNN
+F 3 "" H 16950 2650 60 0000 C CNN
+ 1 16950 2650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7850 5950 10100 5950
+Wire Wire Line
+ 9850 5950 9850 6450
+Wire Wire Line
+ 9850 6450 10100 6450
+Wire Wire Line
+ 10100 6050 9950 6050
+Wire Wire Line
+ 9950 6050 9950 6550
+Wire Wire Line
+ 8000 6550 10100 6550
+Wire Wire Line
+ 11000 6500 11450 6500
+Wire Wire Line
+ 12050 6500 12050 6250
+Wire Wire Line
+ 12050 6250 12500 6250
+Wire Wire Line
+ 12500 6150 12500 6000
+Wire Wire Line
+ 12500 6000 11000 6000
+Wire Wire Line
+ 13400 6200 13800 6200
+Wire Wire Line
+ 14700 6250 15100 6250
+Wire Wire Line
+ 8150 7150 10000 7150
+Wire Wire Line
+ 9700 7150 9700 7650
+Wire Wire Line
+ 9700 7650 10000 7650
+Wire Wire Line
+ 10000 7250 9850 7250
+Wire Wire Line
+ 9850 7250 9850 7750
+Wire Wire Line
+ 8300 7750 10000 7750
+Wire Wire Line
+ 10900 7200 11450 7200
+Wire Wire Line
+ 12050 7200 13900 7200
+Wire Wire Line
+ 12450 7200 12450 7600
+Wire Wire Line
+ 10900 7700 12450 7700
+Connection ~ 12450 7200
+Wire Wire Line
+ 14600 6850 15150 6850
+Wire Wire Line
+ 15150 6950 15150 7250
+Wire Wire Line
+ 15150 7250 14800 7250
+Wire Wire Line
+ 13350 7650 13900 7650
+Wire Wire Line
+ 13900 7300 13600 7300
+Wire Wire Line
+ 13600 7300 13600 8000
+Wire Wire Line
+ 13600 7750 13900 7750
+Wire Wire Line
+ 14800 7700 15300 7700
+Wire Wire Line
+ 13800 6300 13600 6300
+Wire Wire Line
+ 13600 6300 13600 6500
+Wire Wire Line
+ 13600 6500 16200 6500
+Wire Wire Line
+ 16200 6500 16200 6900
+Wire Wire Line
+ 16200 6900 16050 6900
+Wire Wire Line
+ 10000 8550 9700 8550
+Wire Wire Line
+ 9700 8200 9700 9050
+Wire Wire Line
+ 9700 9050 10000 9050
+Wire Wire Line
+ 10000 8650 9850 8650
+Wire Wire Line
+ 9850 8650 9850 9150
+Wire Wire Line
+ 8350 9150 10000 9150
+Wire Wire Line
+ 10900 9100 11350 9100
+Wire Wire Line
+ 11950 9100 12400 9100
+Wire Wire Line
+ 12400 9100 12400 8800
+Wire Wire Line
+ 12400 8800 12450 8800
+Wire Wire Line
+ 12450 8500 12450 8700
+Wire Wire Line
+ 12450 8600 10900 8600
+Wire Wire Line
+ 12450 8500 14000 8500
+Connection ~ 12450 8600
+Wire Wire Line
+ 13350 8750 13350 9100
+Wire Wire Line
+ 13350 9100 14000 9100
+Wire Wire Line
+ 14000 8600 13650 8600
+Wire Wire Line
+ 13650 8600 13650 9300
+Wire Wire Line
+ 13650 9200 14000 9200
+Wire Wire Line
+ 14900 9150 15400 9150
+Wire Wire Line
+ 14900 8550 15250 8550
+Wire Wire Line
+ 15250 8550 15250 8350
+Wire Wire Line
+ 8200 9900 10000 9900
+Wire Wire Line
+ 9700 9900 9700 10500
+Wire Wire Line
+ 9700 10500 10000 10500
+Wire Wire Line
+ 10000 10000 9850 10000
+Wire Wire Line
+ 9850 10000 9850 10600
+Wire Wire Line
+ 8100 10600 10000 10600
+Wire Wire Line
+ 10900 9950 11350 9950
+Wire Wire Line
+ 11950 9950 13900 9950
+Wire Wire Line
+ 12350 9950 12350 10450
+Wire Wire Line
+ 10900 10550 12350 10550
+Connection ~ 12350 9950
+Wire Wire Line
+ 14800 10000 15300 10000
+Wire Wire Line
+ 15300 10000 15300 9700
+Wire Wire Line
+ 15000 9600 15300 9600
+Wire Wire Line
+ 15050 10550 15500 10550
+Wire Wire Line
+ 13250 10500 14150 10500
+Wire Wire Line
+ 13900 10050 13650 10050
+Wire Wire Line
+ 13650 10050 13650 10800
+Wire Wire Line
+ 13650 10600 14150 10600
+Wire Wire Line
+ 13600 8000 16350 8000
+Wire Wire Line
+ 16350 8000 16350 8300
+Wire Wire Line
+ 16350 8300 16150 8300
+Connection ~ 13600 7750
+Wire Wire Line
+ 13650 9300 16400 9300
+Wire Wire Line
+ 16400 9300 16400 9650
+Wire Wire Line
+ 16400 9650 16200 9650
+Connection ~ 13650 9200
+Wire Wire Line
+ 13750 5200 13750 4950
+Wire Wire Line
+ 13750 4950 13900 4950
+Wire Wire Line
+ 14800 4900 14800 4550
+Wire Wire Line
+ 14800 4550 15050 4550
+Wire Wire Line
+ 15950 4500 15950 4050
+Wire Wire Line
+ 15950 4050 16100 4050
+Wire Wire Line
+ 17000 4000 17000 3700
+Wire Wire Line
+ 17000 3700 17250 3700
+Wire Wire Line
+ 18150 3650 18150 3250
+Wire Wire Line
+ 18150 3250 18350 3250
+Wire Wire Line
+ 19250 3200 19250 2800
+Wire Wire Line
+ 19250 2800 19500 2800
+Wire Wire Line
+ 20400 2750 20700 2750
+Wire Wire Line
+ 14600 2950 15050 2950
+Wire Wire Line
+ 15050 2950 15050 3150
+Wire Wire Line
+ 15050 3250 15050 3550
+Wire Wire Line
+ 15050 3550 14600 3550
+Wire Wire Line
+ 15950 3200 15950 2650
+Wire Wire Line
+ 15950 2650 16500 2650
+Wire Wire Line
+ 16500 2550 11400 2550
+Wire Wire Line
+ 11400 2550 11400 11200
+Wire Wire Line
+ 11400 11200 7950 11200
+Wire Wire Line
+ 17400 2600 19500 2600
+Wire Wire Line
+ 19500 2600 19500 2700
+Wire Wire Line
+ 12850 5250 11350 5250
+Wire Wire Line
+ 11350 5250 11350 10550
+Connection ~ 11350 10550
+Wire Wire Line
+ 12850 5150 11300 5150
+Wire Wire Line
+ 11300 3500 11300 8600
+Connection ~ 11300 8600
+Wire Wire Line
+ 13900 4850 11250 4850
+Wire Wire Line
+ 11250 4850 11250 9100
+Connection ~ 11250 9100
+Wire Wire Line
+ 15050 4450 11200 4450
+Wire Wire Line
+ 11200 3000 11200 7200
+Connection ~ 11200 7200
+Wire Wire Line
+ 16100 3950 11150 3950
+Wire Wire Line
+ 11150 3950 11150 7700
+Connection ~ 11150 7700
+Wire Wire Line
+ 17250 3600 14400 3600
+Wire Wire Line
+ 14400 3600 14400 3800
+Wire Wire Line
+ 14400 3800 11100 3800
+Wire Wire Line
+ 11100 2900 11100 6000
+Connection ~ 11100 6000
+Wire Wire Line
+ 18350 3150 16800 3150
+Wire Wire Line
+ 16800 3150 16800 3750
+Wire Wire Line
+ 16800 3750 11050 3750
+Wire Wire Line
+ 11050 3750 11050 6500
+Connection ~ 11050 6500
+Wire Wire Line
+ 13700 3600 11000 3600
+Wire Wire Line
+ 11000 3600 11000 9950
+Connection ~ 11000 9950
+Wire Wire Line
+ 11300 3500 13700 3500
+Connection ~ 11300 5150
+Wire Wire Line
+ 11200 3000 13700 3000
+Connection ~ 11200 4450
+Wire Wire Line
+ 11100 2900 13700 2900
+Connection ~ 11100 3800
+Wire Wire Line
+ 14000 6850 11150 6850
+Connection ~ 11150 6850
+Wire Wire Line
+ 14400 9600 11350 9600
+Connection ~ 11350 9600
+Wire Wire Line
+ 15250 8250 11250 8250
+Connection ~ 11250 8250
+Wire Wire Line
+ 13650 10800 11400 10800
+Connection ~ 11400 10800
+Connection ~ 13650 10600
+Connection ~ 9850 5950
+Connection ~ 9950 6550
+Connection ~ 9700 7150
+Connection ~ 9850 7750
+Connection ~ 9700 8550
+Connection ~ 9850 9150
+Connection ~ 9700 9900
+Connection ~ 9850 10600
+Wire Wire Line
+ 21300 2750 21500 2750
+Wire Wire Line
+ 15700 6250 18950 6250
+Wire Wire Line
+ 19800 7150 15900 7150
+Wire Wire Line
+ 15900 7150 15900 7700
+Wire Wire Line
+ 16000 9150 16750 9150
+Wire Wire Line
+ 17150 10550 16100 10550
+Wire Wire Line
+ 7850 8200 9700 8200
+$Comp
+L PORT U1
+U 1 1 686EEBA3
+P 7600 5950
+F 0 "U1" H 7650 6050 30 0000 C CNN
+F 1 "PORT" H 7600 5950 30 0000 C CNN
+F 2 "" H 7600 5950 60 0000 C CNN
+F 3 "" H 7600 5950 60 0000 C CNN
+ 1 7600 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 686EED82
+P 7900 7150
+F 0 "U1" H 7950 7250 30 0000 C CNN
+F 1 "PORT" H 7900 7150 30 0000 C CNN
+F 2 "" H 7900 7150 60 0000 C CNN
+F 3 "" H 7900 7150 60 0000 C CNN
+ 2 7900 7150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 686EEE7B
+P 8050 7750
+F 0 "U1" H 8100 7850 30 0000 C CNN
+F 1 "PORT" H 8050 7750 30 0000 C CNN
+F 2 "" H 8050 7750 60 0000 C CNN
+F 3 "" H 8050 7750 60 0000 C CNN
+ 3 8050 7750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 686EEF60
+P 7600 8200
+F 0 "U1" H 7650 8300 30 0000 C CNN
+F 1 "PORT" H 7600 8200 30 0000 C CNN
+F 2 "" H 7600 8200 60 0000 C CNN
+F 3 "" H 7600 8200 60 0000 C CNN
+ 4 7600 8200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 686EF117
+P 8100 9150
+F 0 "U1" H 8150 9250 30 0000 C CNN
+F 1 "PORT" H 8100 9150 30 0000 C CNN
+F 2 "" H 8100 9150 60 0000 C CNN
+F 3 "" H 8100 9150 60 0000 C CNN
+ 5 8100 9150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 686EF32C
+P 7950 9900
+F 0 "U1" H 8000 10000 30 0000 C CNN
+F 1 "PORT" H 7950 9900 30 0000 C CNN
+F 2 "" H 7950 9900 60 0000 C CNN
+F 3 "" H 7950 9900 60 0000 C CNN
+ 6 7950 9900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 686EF63B
+P 7850 10600
+F 0 "U1" H 7900 10700 30 0000 C CNN
+F 1 "PORT" H 7850 10600 30 0000 C CNN
+F 2 "" H 7850 10600 60 0000 C CNN
+F 3 "" H 7850 10600 60 0000 C CNN
+ 7 7850 10600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 686EF78C
+P 7700 11200
+F 0 "U1" H 7750 11300 30 0000 C CNN
+F 1 "PORT" H 7700 11200 30 0000 C CNN
+F 2 "" H 7700 11200 60 0000 C CNN
+F 3 "" H 7700 11200 60 0000 C CNN
+ 9 7700 11200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 686EFC2D
+P 17400 10550
+F 0 "U1" H 17450 10650 30 0000 C CNN
+F 1 "PORT" H 17400 10550 30 0000 C CNN
+F 2 "" H 17400 10550 60 0000 C CNN
+F 3 "" H 17400 10550 60 0000 C CNN
+ 10 17400 10550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 686EFE88
+P 17000 9150
+F 0 "U1" H 17050 9250 30 0000 C CNN
+F 1 "PORT" H 17000 9150 30 0000 C CNN
+F 2 "" H 17000 9150 60 0000 C CNN
+F 3 "" H 17000 9150 60 0000 C CNN
+ 11 17000 9150
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 686EFF3D
+P 20050 7150
+F 0 "U1" H 20100 7250 30 0000 C CNN
+F 1 "PORT" H 20050 7150 30 0000 C CNN
+F 2 "" H 20050 7150 60 0000 C CNN
+F 3 "" H 20050 7150 60 0000 C CNN
+ 12 20050 7150
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 686F0059
+P 19200 6250
+F 0 "U1" H 19250 6350 30 0000 C CNN
+F 1 "PORT" H 19200 6250 30 0000 C CNN
+F 2 "" H 19200 6250 60 0000 C CNN
+F 3 "" H 19200 6250 60 0000 C CNN
+ 13 19200 6250
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 686F03B2
+P 21750 2750
+F 0 "U1" H 21800 2850 30 0000 C CNN
+F 1 "PORT" H 21750 2750 30 0000 C CNN
+F 2 "" H 21750 2750 60 0000 C CNN
+F 3 "" H 21750 2750 60 0000 C CNN
+ 14 21750 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 686F071A
+P 7750 6550
+F 0 "U1" H 7800 6650 30 0000 C CNN
+F 1 "PORT" H 7750 6550 30 0000 C CNN
+F 2 "" H 7750 6550 60 0000 C CNN
+F 3 "" H 7750 6550 60 0000 C CNN
+ 15 7750 6550
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sub b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sub
new file mode 100644
index 000000000..7f584f9c3
--- /dev/null
+++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic.sub
@@ -0,0 +1,182 @@
+* Subcircuit tc4008bp_ic
+.subckt tc4008bp_ic net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_
+* c:\fossee\esim\library\subcircuitlibrary\tc4008bp_ic\tc4008bp_ic.cir
+* u7 net-_u1-pad1_ net-_u1-pad15_ net-_u16-pad1_ d_nor
+* u8 net-_u1-pad1_ net-_u1-pad15_ net-_u11-pad1_ d_nand
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u11-pad2_ net-_u16-pad3_ d_nor
+* u20 net-_u16-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_xor
+* u30 net-_u20-pad3_ net-_u1-pad13_ d_inverter
+* u50 net-_u1-pad2_ net-_u1-pad3_ net-_u12-pad1_ d_nor
+* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u14-pad2_ d_nand
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u14 net-_u12-pad2_ net-_u14-pad2_ net-_u14-pad3_ d_nand
+* u23 net-_u12-pad2_ net-_u23-pad2_ net-_u23-pad3_ d_and
+* u33 net-_u21-pad2_ net-_u23-pad3_ net-_u20-pad2_ d_nor
+* u21 net-_u14-pad2_ net-_u21-pad2_ d_inverter
+* u24 net-_u14-pad3_ net-_u23-pad2_ net-_u24-pad3_ d_xor
+* u34 net-_u24-pad3_ net-_u1-pad12_ d_inverter
+* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u15-pad1_ d_nor
+* u4 net-_u1-pad4_ net-_u1-pad5_ net-_u22-pad1_ d_nand
+* u9 net-_u22-pad1_ net-_u15-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor
+* u26 net-_u15-pad1_ net-_u26-pad2_ net-_u26-pad3_ d_or
+* u27 net-_u15-pad3_ net-_u26-pad2_ net-_u27-pad3_ d_xor
+* u35 net-_u22-pad1_ net-_u26-pad3_ net-_u23-pad2_ d_nand
+* u36 net-_u27-pad3_ net-_u1-pad11_ d_inverter
+* u5 net-_u1-pad6_ net-_u1-pad7_ net-_u10-pad1_ d_nor
+* u6 net-_u1-pad6_ net-_u1-pad7_ net-_u13-pad2_ d_nand
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u13 net-_u10-pad2_ net-_u13-pad2_ net-_u13-pad3_ d_nand
+* u25 net-_u10-pad2_ net-_u1-pad9_ net-_u25-pad3_ d_and
+* u37 net-_u29-pad2_ net-_u25-pad3_ net-_u26-pad2_ d_nor
+* u29 net-_u13-pad2_ net-_u29-pad2_ d_inverter
+* u28 net-_u13-pad3_ net-_u1-pad9_ net-_u28-pad3_ d_xor
+* u38 net-_u28-pad3_ net-_u1-pad10_ d_inverter
+* u17 net-_u15-pad1_ net-_u13-pad2_ net-_u17-pad3_ d_or
+* u22 net-_u22-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and
+* u32 net-_u12-pad1_ net-_u22-pad3_ net-_u32-pad3_ d_or
+* u39 net-_u14-pad2_ net-_u32-pad3_ net-_u39-pad3_ d_and
+* u41 net-_u16-pad1_ net-_u39-pad3_ net-_u41-pad3_ d_or
+* u42 net-_u11-pad1_ net-_u41-pad3_ net-_u42-pad3_ d_nand
+* u43 net-_u40-pad3_ net-_u42-pad3_ net-_u43-pad3_ d_nor
+* u44 net-_u43-pad3_ net-_u1-pad14_ d_inverter
+* u19 net-_u15-pad1_ net-_u10-pad1_ net-_u19-pad3_ d_nor
+* u18 net-_u16-pad1_ net-_u12-pad1_ net-_u18-pad3_ d_nor
+* u31 net-_u18-pad3_ net-_u19-pad3_ net-_u31-pad3_ d_nor
+* u40 net-_u1-pad9_ net-_u31-pad3_ net-_u40-pad3_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad15_ ] net-_u16-pad1_ u7
+a2 [net-_u1-pad1_ net-_u1-pad15_ ] net-_u11-pad1_ u8
+a3 net-_u11-pad1_ net-_u11-pad2_ u11
+a4 [net-_u16-pad1_ net-_u11-pad2_ ] net-_u16-pad3_ u16
+a5 [net-_u16-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a6 net-_u20-pad3_ net-_u1-pad13_ u30
+a7 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u12-pad1_ u50
+a8 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u14-pad2_ u2
+a9 net-_u12-pad1_ net-_u12-pad2_ u12
+a10 [net-_u12-pad2_ net-_u14-pad2_ ] net-_u14-pad3_ u14
+a11 [net-_u12-pad2_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a12 [net-_u21-pad2_ net-_u23-pad3_ ] net-_u20-pad2_ u33
+a13 net-_u14-pad2_ net-_u21-pad2_ u21
+a14 [net-_u14-pad3_ net-_u23-pad2_ ] net-_u24-pad3_ u24
+a15 net-_u24-pad3_ net-_u1-pad12_ u34
+a16 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u15-pad1_ u3
+a17 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u22-pad1_ u4
+a18 net-_u22-pad1_ net-_u15-pad2_ u9
+a19 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a20 [net-_u15-pad1_ net-_u26-pad2_ ] net-_u26-pad3_ u26
+a21 [net-_u15-pad3_ net-_u26-pad2_ ] net-_u27-pad3_ u27
+a22 [net-_u22-pad1_ net-_u26-pad3_ ] net-_u23-pad2_ u35
+a23 net-_u27-pad3_ net-_u1-pad11_ u36
+a24 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u10-pad1_ u5
+a25 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u13-pad2_ u6
+a26 net-_u10-pad1_ net-_u10-pad2_ u10
+a27 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a28 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u25-pad3_ u25
+a29 [net-_u29-pad2_ net-_u25-pad3_ ] net-_u26-pad2_ u37
+a30 net-_u13-pad2_ net-_u29-pad2_ u29
+a31 [net-_u13-pad3_ net-_u1-pad9_ ] net-_u28-pad3_ u28
+a32 net-_u28-pad3_ net-_u1-pad10_ u38
+a33 [net-_u15-pad1_ net-_u13-pad2_ ] net-_u17-pad3_ u17
+a34 [net-_u22-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22
+a35 [net-_u12-pad1_ net-_u22-pad3_ ] net-_u32-pad3_ u32
+a36 [net-_u14-pad2_ net-_u32-pad3_ ] net-_u39-pad3_ u39
+a37 [net-_u16-pad1_ net-_u39-pad3_ ] net-_u41-pad3_ u41
+a38 [net-_u11-pad1_ net-_u41-pad3_ ] net-_u42-pad3_ u42
+a39 [net-_u40-pad3_ net-_u42-pad3_ ] net-_u43-pad3_ u43
+a40 net-_u43-pad3_ net-_u1-pad14_ u44
+a41 [net-_u15-pad1_ net-_u10-pad1_ ] net-_u19-pad3_ u19
+a42 [net-_u16-pad1_ net-_u12-pad1_ ] net-_u18-pad3_ u18
+a43 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u31-pad3_ u31
+a44 [net-_u1-pad9_ net-_u31-pad3_ ] net-_u40-pad3_ u40
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u20 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u24 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u26 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u27 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u28 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u39 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u41 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u31 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u40 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends tc4008bp_ic
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic_Previous_Values.xml b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic_Previous_Values.xml
new file mode 100644
index 000000000..f7d1db7a0
--- /dev/null
+++ b/library/SubcircuitLibrary/tc4008bp_ic/tc4008bp_ic_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes020010secmssecd_nord_nandd_inverterd_nord_xord_inverterd_nord_nandd_inverterd_nandd_andd_nord_inverterd_xord_inverterd_nord_nandd_inverterd_nord_ord_xord_nandd_inverterd_nord_nandd_inverterd_nandd_andd_nord_inverterd_xord_inverterd_ord_andd_ord_andd_ord_nandd_nord_inverterd_nord_nord_nord_and
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/tff_1/analysis b/library/SubcircuitLibrary/tff_1/analysis
new file mode 100644
index 000000000..ebd5c0a94
--- /dev/null
+++ b/library/SubcircuitLibrary/tff_1/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/tff_1/tff_1-cache.lib b/library/SubcircuitLibrary/tff_1/tff_1-cache.lib
new file mode 100644
index 000000000..c07ae5124
--- /dev/null
+++ b/library/SubcircuitLibrary/tff_1/tff_1-cache.lib
@@ -0,0 +1,78 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/tff_1/tff_1.cir b/library/SubcircuitLibrary/tff_1/tff_1.cir
new file mode 100644
index 000000000..5a146818a
--- /dev/null
+++ b/library/SubcircuitLibrary/tff_1/tff_1.cir
@@ -0,0 +1,19 @@
+* D:\FOSSEE\eSim\library\SubcircuitLibrary\tff_1\tff_1.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/17/25 12:05:50
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and
+U3 Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U3-Pad3_ d_and
+U4 Net-_U1-Pad3_ Net-_U2-Pad4_ Net-_U4-Pad3_ d_nand
+U5 Net-_U2-Pad5_ Net-_U3-Pad3_ Net-_U5-Pad3_ d_nand
+U6 Net-_U2-Pad6_ Net-_U4-Pad3_ Net-_U6-Pad3_ d_and
+U7 Net-_U5-Pad3_ Net-_U2-Pad3_ Net-_U7-Pad3_ d_and
+U8 Net-_U6-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ d_nand
+U9 Net-_U2-Pad5_ Net-_U7-Pad3_ Net-_U2-Pad4_ d_nand
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/tff_1/tff_1.cir.out b/library/SubcircuitLibrary/tff_1/tff_1.cir.out
new file mode 100644
index 000000000..eb1d38f67
--- /dev/null
+++ b/library/SubcircuitLibrary/tff_1/tff_1.cir.out
@@ -0,0 +1,44 @@
+* d:\fossee\esim\library\subcircuitlibrary\tff_1\tff_1.cir
+
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and
+* u3 net-_u1-pad2_ net-_u1-pad1_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad3_ net-_u2-pad4_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad5_ net-_u3-pad3_ net-_u5-pad3_ d_nand
+* u6 net-_u2-pad6_ net-_u4-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u5-pad3_ net-_u2-pad3_ net-_u7-pad3_ d_and
+* u8 net-_u6-pad3_ net-_u2-pad4_ net-_u2-pad5_ d_nand
+* u9 net-_u2-pad5_ net-_u7-pad3_ net-_u2-pad4_ d_nand
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad3_ net-_u2-pad4_ ] net-_u4-pad3_ u4
+a4 [net-_u2-pad5_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a5 [net-_u2-pad6_ net-_u4-pad3_ ] net-_u6-pad3_ u6
+a6 [net-_u5-pad3_ net-_u2-pad3_ ] net-_u7-pad3_ u7
+a7 [net-_u6-pad3_ net-_u2-pad4_ ] net-_u2-pad5_ u8
+a8 [net-_u2-pad5_ net-_u7-pad3_ ] net-_u2-pad4_ u9
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/tff_1/tff_1.pro b/library/SubcircuitLibrary/tff_1/tff_1.pro
new file mode 100644
index 000000000..e27a398be
--- /dev/null
+++ b/library/SubcircuitLibrary/tff_1/tff_1.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/tff_1/tff_1.sch b/library/SubcircuitLibrary/tff_1/tff_1.sch
new file mode 100644
index 000000000..467a8221e
--- /dev/null
+++ b/library/SubcircuitLibrary/tff_1/tff_1.sch
@@ -0,0 +1,299 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:tff_1-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U1
+U 1 1 68510BDF
+P 3350 2450
+F 0 "U1" H 3350 2450 60 0000 C CNN
+F 1 "d_and" H 3400 2550 60 0000 C CNN
+F 2 "" H 3350 2450 60 0000 C CNN
+F 3 "" H 3350 2450 60 0000 C CNN
+ 1 3350 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 68510C68
+P 3400 3750
+F 0 "U3" H 3400 3750 60 0000 C CNN
+F 1 "d_and" H 3450 3850 60 0000 C CNN
+F 2 "" H 3400 3750 60 0000 C CNN
+F 3 "" H 3400 3750 60 0000 C CNN
+ 1 3400 3750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U4
+U 1 1 68510CCF
+P 5300 2450
+F 0 "U4" H 5300 2450 60 0000 C CNN
+F 1 "d_nand" H 5350 2550 60 0000 C CNN
+F 2 "" H 5300 2450 60 0000 C CNN
+F 3 "" H 5300 2450 60 0000 C CNN
+ 1 5300 2450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U5
+U 1 1 68510D24
+P 5350 3700
+F 0 "U5" H 5350 3700 60 0000 C CNN
+F 1 "d_nand" H 5400 3800 60 0000 C CNN
+F 2 "" H 5350 3700 60 0000 C CNN
+F 3 "" H 5350 3700 60 0000 C CNN
+ 1 5350 3700
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 3800 2400 4600 2400
+Wire Wire Line
+ 4600 2400 4600 2350
+Wire Wire Line
+ 4600 2350 4850 2350
+Wire Wire Line
+ 3850 3700 4900 3700
+$Comp
+L d_and U6
+U 1 1 685111F3
+P 6600 2400
+F 0 "U6" H 6600 2400 60 0000 C CNN
+F 1 "d_and" H 6650 2500 60 0000 C CNN
+F 2 "" H 6600 2400 60 0000 C CNN
+F 3 "" H 6600 2400 60 0000 C CNN
+ 1 6600 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U7
+U 1 1 685111F9
+P 6650 3700
+F 0 "U7" H 6650 3700 60 0000 C CNN
+F 1 "d_and" H 6700 3800 60 0000 C CNN
+F 2 "" H 6650 3700 60 0000 C CNN
+F 3 "" H 6650 3700 60 0000 C CNN
+ 1 6650 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U8
+U 1 1 685111FF
+P 8550 2400
+F 0 "U8" H 8550 2400 60 0000 C CNN
+F 1 "d_nand" H 8600 2500 60 0000 C CNN
+F 2 "" H 8550 2400 60 0000 C CNN
+F 3 "" H 8550 2400 60 0000 C CNN
+ 1 8550 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nand U9
+U 1 1 68511205
+P 8600 3650
+F 0 "U9" H 8600 3650 60 0000 C CNN
+F 1 "d_nand" H 8650 3750 60 0000 C CNN
+F 2 "" H 8600 3650 60 0000 C CNN
+F 3 "" H 8600 3650 60 0000 C CNN
+ 1 8600 3650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 7050 2350 7850 2350
+Wire Wire Line
+ 7850 2350 7850 2300
+Wire Wire Line
+ 7850 2300 8100 2300
+Wire Wire Line
+ 7100 3650 8150 3650
+Wire Wire Line
+ 5800 3650 5900 3650
+Wire Wire Line
+ 5900 3650 5900 3600
+Wire Wire Line
+ 5900 3600 6200 3600
+Wire Wire Line
+ 5750 2400 6150 2400
+Wire Wire Line
+ 6150 2300 5850 2300
+Wire Wire Line
+ 5850 2300 5850 1900
+Wire Wire Line
+ 6200 3700 6050 3700
+Wire Wire Line
+ 6050 3700 6050 4250
+Wire Wire Line
+ 9000 2350 9700 2350
+Wire Wire Line
+ 9050 3600 9900 3600
+Wire Wire Line
+ 9450 2350 9450 3050
+Wire Wire Line
+ 9450 3050 7750 3050
+Wire Wire Line
+ 7750 3050 7750 3550
+Wire Wire Line
+ 7750 3550 8150 3550
+Connection ~ 9450 2350
+Wire Wire Line
+ 9350 3600 9350 2700
+Wire Wire Line
+ 9350 2700 8000 2700
+Wire Wire Line
+ 8000 2700 8000 2400
+Wire Wire Line
+ 8000 2400 8100 2400
+Connection ~ 9350 3600
+Wire Wire Line
+ 7750 3200 4550 3200
+Wire Wire Line
+ 4550 3200 4550 3600
+Wire Wire Line
+ 4550 3600 4900 3600
+Connection ~ 7750 3200
+Wire Wire Line
+ 8000 2600 4700 2600
+Wire Wire Line
+ 4700 2600 4700 2450
+Wire Wire Line
+ 4700 2450 4850 2450
+Connection ~ 8000 2600
+Wire Wire Line
+ 2900 2450 2550 2450
+Wire Wire Line
+ 2550 2450 2550 3650
+Wire Wire Line
+ 2550 3650 2950 3650
+Wire Wire Line
+ 2550 3050 2050 3050
+Wire Wire Line
+ 2050 3050 2050 4200
+Connection ~ 2550 3050
+Wire Wire Line
+ 2900 2350 1800 2350
+Wire Wire Line
+ 1800 2350 1800 2300
+Wire Wire Line
+ 2150 2350 2150 3750
+Wire Wire Line
+ 2150 3750 2950 3750
+Connection ~ 2150 2350
+$Comp
+L PORT U2
+U 1 1 68512107
+P 1550 2300
+F 0 "U2" H 1600 2400 30 0000 C CNN
+F 1 "PORT" H 1550 2300 30 0000 C CNN
+F 2 "" H 1550 2300 60 0000 C CNN
+F 3 "" H 1550 2300 60 0000 C CNN
+ 1 1550 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 4 1 6851219B
+P 9900 3850
+F 0 "U2" H 9950 3950 30 0000 C CNN
+F 1 "PORT" H 9900 3850 30 0000 C CNN
+F 2 "" H 9900 3850 60 0000 C CNN
+F 3 "" H 9900 3850 60 0000 C CNN
+ 4 9900 3850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 5 1 685121CC
+P 9700 2600
+F 0 "U2" H 9750 2700 30 0000 C CNN
+F 1 "PORT" H 9700 2600 30 0000 C CNN
+F 2 "" H 9700 2600 60 0000 C CNN
+F 3 "" H 9700 2600 60 0000 C CNN
+ 5 9700 2600
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U2
+U 6 1 68512212
+P 5600 1900
+F 0 "U2" H 5650 2000 30 0000 C CNN
+F 1 "PORT" H 5600 1900 30 0000 C CNN
+F 2 "" H 5600 1900 60 0000 C CNN
+F 3 "" H 5600 1900 60 0000 C CNN
+ 6 5600 1900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 2 1 68512275
+P 1800 4200
+F 0 "U2" H 1850 4300 30 0000 C CNN
+F 1 "PORT" H 1800 4200 30 0000 C CNN
+F 2 "" H 1800 4200 60 0000 C CNN
+F 3 "" H 1800 4200 60 0000 C CNN
+ 2 1800 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U2
+U 3 1 685122C6
+P 5800 4250
+F 0 "U2" H 5850 4350 30 0000 C CNN
+F 1 "PORT" H 5800 4250 30 0000 C CNN
+F 2 "" H 5800 4250 60 0000 C CNN
+F 3 "" H 5800 4250 60 0000 C CNN
+ 3 5800 4250
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/tff_1/tff_1.sub b/library/SubcircuitLibrary/tff_1/tff_1.sub
new file mode 100644
index 000000000..c7f567e0c
--- /dev/null
+++ b/library/SubcircuitLibrary/tff_1/tff_1.sub
@@ -0,0 +1,38 @@
+* Subcircuit tff_1
+.subckt tff_1 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_
+* d:\fossee\esim\library\subcircuitlibrary\tff_1\tff_1.cir
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and
+* u3 net-_u1-pad2_ net-_u1-pad1_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad3_ net-_u2-pad4_ net-_u4-pad3_ d_nand
+* u5 net-_u2-pad5_ net-_u3-pad3_ net-_u5-pad3_ d_nand
+* u6 net-_u2-pad6_ net-_u4-pad3_ net-_u6-pad3_ d_and
+* u7 net-_u5-pad3_ net-_u2-pad3_ net-_u7-pad3_ d_and
+* u8 net-_u6-pad3_ net-_u2-pad4_ net-_u2-pad5_ d_nand
+* u9 net-_u2-pad5_ net-_u7-pad3_ net-_u2-pad4_ d_nand
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1
+a2 [net-_u1-pad2_ net-_u1-pad1_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad3_ net-_u2-pad4_ ] net-_u4-pad3_ u4
+a4 [net-_u2-pad5_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a5 [net-_u2-pad6_ net-_u4-pad3_ ] net-_u6-pad3_ u6
+a6 [net-_u5-pad3_ net-_u2-pad3_ ] net-_u7-pad3_ u7
+a7 [net-_u6-pad3_ net-_u2-pad4_ ] net-_u2-pad5_ u8
+a8 [net-_u2-pad5_ net-_u7-pad3_ ] net-_u2-pad4_ u9
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends tff_1
\ No newline at end of file
diff --git a/library/SubcircuitLibrary/tff_1/tff_1_Previous_Values.xml b/library/SubcircuitLibrary/tff_1/tff_1_Previous_Values.xml
new file mode 100644
index 000000000..ab6605eb4
--- /dev/null
+++ b/library/SubcircuitLibrary/tff_1/tff_1_Previous_Values.xml
@@ -0,0 +1 @@
+truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_andd_andd_nandd_nandd_andd_andd_nandd_nand
\ No newline at end of file
diff --git a/library/deviceModelLibrary/Diode/1N34A/1N34A.lib b/library/deviceModelLibrary/Diode/1N34A/1N34A.lib
index 6e3cabf39..adbb503ba 100644
--- a/library/deviceModelLibrary/Diode/1N34A/1N34A.lib
+++ b/library/deviceModelLibrary/Diode/1N34A/1N34A.lib
@@ -1 +1,2 @@
-.MODEL 1N34A D( Is=0.2u N=1.30 Rs=7 bv=75 Ibv=0.018 Cjo=0.5p Vj=0.10 M=0.27 tt=144n )
\ No newline at end of file
+.model 1N34A D(IS=2.6u RS=6.5 N=1.6 CJO=0.8p EG=0.67 BV=75 IBV=1m)
+.MODEL 1N34A_1 D( Is=0.2u N=1.30 Rs=7 bv=75 Ibv=0.018 Cjo=0.5p Vj=0.10 M=0.27 tt=144n )
diff --git a/library/deviceModelLibrary/Diode/1N34A/1N34A.xml b/library/deviceModelLibrary/Diode/1N34A/1N34A.xml
index e8a194428..4855289a7 100644
--- a/library/deviceModelLibrary/Diode/1N34A/1N34A.xml
+++ b/library/deviceModelLibrary/Diode/1N34A/1N34A.xml
@@ -1,3 +1,4 @@
+D1N34A2.6u6.51.60.8p0.67751m
D
1N34A
diff --git a/library/deviceModelLibrary/JFET/2N4393/2N4393.lib b/library/deviceModelLibrary/JFET/2N4393/2N4393.lib
new file mode 100644
index 000000000..1d2d426f8
--- /dev/null
+++ b/library/deviceModelLibrary/JFET/2N4393/2N4393.lib
@@ -0,0 +1 @@
+.MODEL 2N4393 NJF (VTO=-1.4 BETA=0.0091 LAMBDA=0.006 RD=1 RS=1 CGS=4.1p CGD=4.6p PB=1 IS=205f AF=1 FC=0.5 BETATCE=-0.5 N=1 NR=2 XTI=3 VTOTC=-2.5m ALPHA=21u VK=1 ISR=10f KF=0.001f M=0.5)
diff --git a/library/deviceModelLibrary/JFET/2N4393/2N4393.xml b/library/deviceModelLibrary/JFET/2N4393/2N4393.xml
new file mode 100644
index 000000000..94a59a2da
--- /dev/null
+++ b/library/deviceModelLibrary/JFET/2N4393/2N4393.xml
@@ -0,0 +1 @@
+NJF2N4393-1.40.00910.006114.1p4.6p1205f10.5-0.5123-2.5m21u110f0.001f0.5
\ No newline at end of file
diff --git a/library/deviceModelLibrary/Transistor/2N3903/2N3903.lib b/library/deviceModelLibrary/Transistor/2N3903/2N3903.lib
new file mode 100644
index 000000000..8d0f57a3a
--- /dev/null
+++ b/library/deviceModelLibrary/Transistor/2N3903/2N3903.lib
@@ -0,0 +1,4 @@
+ .model 2N3903 NPN( Is=6.734f Xti=3 Eg=1.11 Vaf=74 Bf=200 Ne=1.5
++ Ise=6.734f Ikf=0.284 Xtb=1.5 Br=3 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=3p
++ Mjc=0.33 Vjc=0.75 Fc=0.5 Cje=4p Mje=0.33 Vje=0.75 Tr=100n Tf=350p
++ Itf=0.1 Vtf=10 Xtf=1 Rb=0.56)
diff --git a/library/deviceModelLibrary/Transistor/2N3903/2N3903.xml b/library/deviceModelLibrary/Transistor/2N3903/2N3903.xml
new file mode 100644
index 000000000..7b48a6d2b
--- /dev/null
+++ b/library/deviceModelLibrary/Transistor/2N3903/2N3903.xml
@@ -0,0 +1 @@
+NPN2N39036.734f31.11742001.56.734f0.2841.5
320013p0.330.750.54p0.330.75100n
350p0.11010.56
\ No newline at end of file
diff --git a/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.lib b/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.lib
new file mode 100644
index 000000000..9660ac880
--- /dev/null
+++ b/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.lib
@@ -0,0 +1,9 @@
+
+.model TIP41C NPN (
++ IS=1.0E-10 BF=100 NF=1.0 VAF=50 IKF=1.0
++ ISE=1.0E-11 NE=2.0 BR=1.0 NR=1.0 VAR=10 IKR=0.5
++ RE=0.5 RC=1.0 RB=1.0
++ CJE=30p VJE=0.75 MJE=0.33
++ CJC=10p VJC=0.5 MJC=0.33
++ TF=0.5n TR=1n
+)
diff --git a/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.xml b/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.xml
new file mode 100644
index 000000000..6cc915943
--- /dev/null
+++ b/library/deviceModelLibrary/Transistor/TIP41C/TIP41C.xml
@@ -0,0 +1 @@
+NPNTIP41C1.0E-101001.0501.01.0E-112.0
1.01.0100.50.51.01.030p0.750.3310p0.50.330.5n1n
\ No newline at end of file
diff --git a/library/ihp integration/cmosInverter/NMOS-180nm.lib b/library/ihp integration/cmosInverter/NMOS-180nm.lib
new file mode 100644
index 000000000..51e9b1196
--- /dev/null
+++ b/library/ihp integration/cmosInverter/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697
++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0
++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3
++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286
++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078
++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/ihp integration/cmosInverter/PMOS-180nm.lib b/library/ihp integration/cmosInverter/PMOS-180nm.lib
new file mode 100644
index 000000000..032b5b95e
--- /dev/null
+++ b/library/ihp integration/cmosInverter/PMOS-180nm.lib
@@ -0,0 +1,11 @@
+.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015
++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363
++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478
++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677
++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9
++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148
++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10
++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9
++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5
++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3
++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3)
diff --git a/library/ihp integration/cmosInverter/analysis b/library/ihp integration/cmosInverter/analysis
new file mode 100644
index 000000000..6331256ea
--- /dev/null
+++ b/library/ihp integration/cmosInverter/analysis
@@ -0,0 +1 @@
+.tran 0.1e-00 20e-00 0e-00
\ No newline at end of file
diff --git a/library/ihp integration/cmosInverter/cmosInverter.cir b/library/ihp integration/cmosInverter/cmosInverter.cir
new file mode 100644
index 000000000..2cbd3c1b8
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmosInverter.cir
@@ -0,0 +1,27 @@
+
+* CMOS inverter - Windows-safe version (no Verilog-A needed)
+.title CMOS inverter (fallback models)
+
+.global GND
+
+* Power
+VDD vdd GND DC 1.2
+
+* Input
+VIN input GND PWL(0ns 0 2ns 0 4ns 1.2 9ns 1.2 11ns 0 20ns 0)
+
+* Simple built-in MOS models
+.model NMOS NMOS (VTO=0.6 KP=100u)
+.model PMOS PMOS (VTO=-0.6 KP=40u)
+
+* Devices: D G S B
+M1 output input GND GND NMOS W=1u L=0.13u
+M2 output input vdd vdd PMOS W=2u L=0.13u
+
+.control
+tran 0.1n 40n
+run
+plot v(input) v(output)
+.endc
+
+.end
diff --git a/library/ihp integration/cmosInverter/cmosInverter.cir.out b/library/ihp integration/cmosInverter/cmosInverter.cir.out
new file mode 100644
index 000000000..890cac3de
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmosInverter.cir.out
@@ -0,0 +1,21 @@
+.title kicad schematic
+
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+m1 net-_m1-pad1_ input output net-_m1-pad1_ CMOSN W=100u L=100u M=1
+m2 output input gnd gnd CMOSP W=100u L=100u M=1
+* u2 output plot_v1
+v2 net-_m1-pad1_ gnd dc 5
+* u1 input plot_v1
+v1 input gnd pwl(0 0 10 0 11 5 20 5)
+.tran 0.1e-00 20e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(output)
+plot v(input)
+.endc
+.end
diff --git a/library/ihp integration/cmosInverter/cmosInverter.kicad_sch b/library/ihp integration/cmosInverter/cmosInverter.kicad_sch
new file mode 100644
index 000000000..8847132bd
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmosInverter.kicad_sch
@@ -0,0 +1,744 @@
+(kicad_sch (version 20211123) (generator eeschema)
+
+ (uuid 1e3c9461-7029-410b-b626-f8fc60beaa63)
+
+ (paper "A4")
+
+ (lib_symbols
+ (symbol "eSim_Devices:eSim_MOS_N" (pin_names (offset 0) hide) (in_bom yes) (on_board yes)
+ (property "Reference" "M" (id 0) (at 0 -3.81 0)
+ (effects (font (size 1.27 1.27)) (justify right))
+ )
+ (property "Value" "eSim_MOS_N" (id 1) (at 2.54 -1.27 0)
+ (effects (font (size 1.27 1.27)) (justify right))
+ )
+ (property "Footprint" "" (id 2) (at 7.62 -7.62 0)
+ (effects (font (size 0.7366 0.7366)))
+ )
+ (property "Datasheet" "" (id 3) (at 2.54 -5.08 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (symbol "eSim_MOS_N_0_1"
+ (polyline
+ (pts
+ (xy 3.302 -7.366)
+ (xy 3.302 -6.35)
+ )
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.302 -6.858)
+ (xy 5.08 -6.858)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.302 -5.588)
+ (xy 3.302 -4.572)
+ )
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.302 -5.08)
+ (xy 5.08 -5.08)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.302 -3.81)
+ (xy 3.302 -2.794)
+ )
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.302 -3.302)
+ (xy 5.08 -3.302)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 5.08 -7.62)
+ (xy 5.08 -6.858)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 5.08 -3.302)
+ (xy 5.08 -2.54)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 2.794 -6.985)
+ (xy 2.794 -3.175)
+ (xy 2.794 -3.175)
+ )
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 5.08 -5.08)
+ (xy 7.62 -5.08)
+ (xy 7.62 -6.35)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.556 -5.08)
+ (xy 4.572 -5.461)
+ (xy 4.572 -4.699)
+ (xy 3.556 -5.08)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type outline))
+ )
+ (circle (center 3.81 -5.08) (radius 2.8194)
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "eSim_MOS_N_1_1"
+ (pin passive line (at 5.08 0 270) (length 2.54)
+ (name "D" (effects (font (size 1.27 1.27))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ (pin passive line (at -2.54 -5.08 0) (length 5.334)
+ (name "G" (effects (font (size 1.27 1.27))))
+ (number "2" (effects (font (size 1.27 1.27))))
+ )
+ (pin passive line (at 5.08 -10.16 90) (length 2.54)
+ (name "S" (effects (font (size 1.27 1.27))))
+ (number "3" (effects (font (size 1.27 1.27))))
+ )
+ (pin passive line (at 7.62 -8.89 90) (length 2.4892)
+ (name "B" (effects (font (size 1.1938 1.1938))))
+ (number "4" (effects (font (size 1.1938 1.1938))))
+ )
+ )
+ )
+ (symbol "eSim_Devices:eSim_MOS_P" (pin_names (offset 0) hide) (in_bom yes) (on_board yes)
+ (property "Reference" "M" (id 0) (at -1.27 1.27 0)
+ (effects (font (size 1.27 1.27)) (justify right))
+ )
+ (property "Value" "eSim_MOS_P" (id 1) (at 1.27 3.81 0)
+ (effects (font (size 1.27 1.27)) (justify right))
+ )
+ (property "Footprint" "" (id 2) (at 6.35 2.54 0)
+ (effects (font (size 0.7366 0.7366)))
+ )
+ (property "Datasheet" "" (id 3) (at 1.27 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (symbol "eSim_MOS_P_0_1"
+ (polyline
+ (pts
+ (xy 2.032 -1.778)
+ (xy 3.81 -1.778)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 2.032 -1.27)
+ (xy 2.032 -2.286)
+ )
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 2.032 0)
+ (xy 3.81 0)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 2.032 0.508)
+ (xy 2.032 -0.508)
+ )
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 2.032 1.778)
+ (xy 3.81 1.778)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 2.032 2.286)
+ (xy 2.032 1.27)
+ )
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.81 -1.778)
+ (xy 3.81 -2.54)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.81 2.54)
+ (xy 3.81 1.778)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 1.524 1.905)
+ (xy 1.524 -1.905)
+ (xy 1.524 -1.905)
+ )
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.81 0)
+ (xy 6.35 0)
+ (xy 6.35 -1.27)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (polyline
+ (pts
+ (xy 3.556 0)
+ (xy 2.54 -0.381)
+ (xy 2.54 0.381)
+ (xy 3.556 0)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type outline))
+ )
+ (circle (center 2.54 0) (radius 2.8194)
+ (stroke (width 0.254) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "eSim_MOS_P_1_1"
+ (pin passive line (at 3.81 5.08 270) (length 2.54)
+ (name "D" (effects (font (size 1.27 1.27))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ (pin passive line (at -3.81 0 0) (length 5.334)
+ (name "G" (effects (font (size 1.27 1.27))))
+ (number "2" (effects (font (size 1.27 1.27))))
+ )
+ (pin passive line (at 3.81 -5.08 90) (length 2.54)
+ (name "S" (effects (font (size 1.27 1.27))))
+ (number "3" (effects (font (size 1.27 1.27))))
+ )
+ (pin passive line (at 6.35 -3.81 90) (length 2.54)
+ (name "B" (effects (font (size 1.27 1.27))))
+ (number "4" (effects (font (size 1.27 1.27))))
+ )
+ )
+ )
+ (symbol "eSim_Plot:plot_v1" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+ (property "Reference" "U" (id 0) (at 0 12.7 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Value" "plot_v1" (id 1) (at 5.08 8.89 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Footprint" "" (id 2) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (symbol "plot_v1_0_1"
+ (circle (center 0 12.7) (radius 2.54)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "plot_v1_1_1"
+ (pin input line (at 0 5.08 90) (length 5.08)
+ (name "~" (effects (font (size 1.27 1.27))))
+ (number "~" (effects (font (size 1.27 1.27))))
+ )
+ )
+ )
+ (symbol "eSim_Power:eSim_GND" (power) (pin_names (offset 0)) (in_bom yes) (on_board yes)
+ (property "Reference" "#PWR" (id 0) (at 0 -6.35 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (property "Value" "eSim_GND" (id 1) (at 0 -3.81 0)
+ (effects (font (size 1.27 1.27)))
+ )
+ (property "Footprint" "" (id 2) (at 0 0 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (property "Datasheet" "" (id 3) (at 0 0 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (symbol "eSim_GND_0_1"
+ (polyline
+ (pts
+ (xy 0 0)
+ (xy 0 -1.27)
+ (xy 1.27 -1.27)
+ (xy 0 -2.54)
+ (xy -1.27 -1.27)
+ (xy 0 -1.27)
+ )
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "eSim_GND_1_1"
+ (pin power_in line (at 0 0 270) (length 0) hide
+ (name "GND" (effects (font (size 1.27 1.27))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ )
+ )
+ (symbol "eSim_Sources:DC" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+ (property "Reference" "v" (id 0) (at -5.08 2.54 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Value" "DC" (id 1) (at -5.08 -1.27 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Footprint" "R1" (id 2) (at -7.62 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "ki_fp_filters" "1_pin" (id 4) (at 0 0 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (symbol "DC_0_1"
+ (circle (center 0 0) (radius 3.81)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "DC_1_1"
+ (pin power_out line (at 0 11.43 270) (length 7.62)
+ (name "+" (effects (font (size 1.27 1.27))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ (pin power_out line (at 0 -11.43 90) (length 7.62)
+ (name "-" (effects (font (size 1.27 1.27))))
+ (number "2" (effects (font (size 1.27 1.27))))
+ )
+ )
+ )
+ (symbol "eSim_Sources:pwl" (pin_names (offset 1.016)) (in_bom yes) (on_board yes)
+ (property "Reference" "v" (id 0) (at -5.08 2.54 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Value" "pwl" (id 1) (at -6.35 -1.27 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Footprint" "R1" (id 2) (at -7.62 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 0 0 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "ki_fp_filters" "1_pin" (id 4) (at 0 0 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (symbol "pwl_0_1"
+ (arc (start -2.54 1.27) (mid -3.1997 0.0124) (end -3.81 -1.27)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start -1.27 1.27) (mid -1.905 1.2806) (end -2.54 1.27)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start 0 -1.27) (mid -0.608 0.0135) (end -1.27 1.27)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start 0 -1.27) (mid 0.635 -1.2859) (end 1.27 -1.27)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (circle (center 0 0) (radius 3.81)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ (arc (start 1.27 -1.27) (mid 1.944 -0.0194) (end 2.54 1.27)
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (fill (type none))
+ )
+ )
+ (symbol "pwl_1_1"
+ (pin input line (at 0 11.43 270) (length 7.62)
+ (name "+" (effects (font (size 0 0))))
+ (number "1" (effects (font (size 1.27 1.27))))
+ )
+ (pin input line (at 0 -11.43 90) (length 7.62)
+ (name "-" (effects (font (size 0 0))))
+ (number "2" (effects (font (size 1.27 1.27))))
+ )
+ )
+ )
+ )
+
+ (junction (at 138.43 97.79) (diameter 0) (color 0 0 0 0)
+ (uuid 3e6a8ec2-69dd-467c-9fba-56f0bc8c2980)
+ )
+ (junction (at 115.57 81.28) (diameter 0) (color 0 0 0 0)
+ (uuid 4d3861d6-5d19-4087-bf7c-f38e59e7f2bd)
+ )
+ (junction (at 153.67 97.79) (diameter 0) (color 0 0 0 0)
+ (uuid 5b1204dd-b3a8-428d-80c2-c0c8e483a70a)
+ )
+ (junction (at 138.43 120.65) (diameter 0) (color 0 0 0 0)
+ (uuid 9e1d64b5-4537-42a3-a443-86562435f6f4)
+ )
+ (junction (at 139.7 73.66) (diameter 0) (color 0 0 0 0)
+ (uuid a8607d9e-9381-4c1f-a2e5-8691a3ae2e20)
+ )
+ (junction (at 138.43 123.19) (diameter 0) (color 0 0 0 0)
+ (uuid ab30530c-4761-422b-9347-8c411bc67bda)
+ )
+ (junction (at 104.14 81.28) (diameter 0) (color 0 0 0 0)
+ (uuid cda25fb5-fd53-4130-b5ae-2859fccee556)
+ )
+ (junction (at 99.06 81.28) (diameter 0) (color 0 0 0 0)
+ (uuid f4790b0a-2a43-44a2-ba7d-280f9c88eec2)
+ )
+
+ (wire (pts (xy 139.7 69.85) (xy 180.34 69.85))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 0fc5acb2-d64c-4191-9633-806a7fd148e5)
+ )
+ (wire (pts (xy 180.34 123.19) (xy 138.43 123.19))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 23bea5b5-db70-4951-be4d-50e77e0308a6)
+ )
+ (wire (pts (xy 158.75 73.66) (xy 139.7 73.66))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 257c2bea-b732-4b4f-82c0-07c46ff9f4d6)
+ )
+ (wire (pts (xy 138.43 86.36) (xy 139.7 86.36))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 2e99c811-273d-4755-8a13-9c75a8aafdea)
+ )
+ (wire (pts (xy 138.43 104.14) (xy 138.43 97.79))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 346c0c7d-8ab3-4103-b1ed-6fb589a66fc3)
+ )
+ (wire (pts (xy 180.34 69.85) (xy 180.34 83.82))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 3e2113e5-0a8b-4ca0-9cc1-a60d95ca9887)
+ )
+ (wire (pts (xy 90.17 123.19) (xy 138.43 123.19))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 40cc61fc-bb6b-40b9-af3a-b27c8f294520)
+ )
+ (wire (pts (xy 115.57 81.28) (xy 104.14 81.28))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 4106e162-7ba1-42b6-bb0e-ee0f08196c88)
+ )
+ (wire (pts (xy 90.17 81.28) (xy 90.17 85.09))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 5a4de4ea-cfd4-4525-a0fe-5dfe369c3d35)
+ )
+ (wire (pts (xy 90.17 107.95) (xy 90.17 123.19))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 7ec12566-78fb-42ac-b4f3-9160b3f70b45)
+ )
+ (wire (pts (xy 138.43 120.65) (xy 140.97 120.65))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 975d2d1b-a349-410f-9d1b-c257124168c5)
+ )
+ (wire (pts (xy 138.43 120.65) (xy 138.43 123.19))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid 9ce8fed9-0797-46ee-a96a-eb24ce4c3bb8)
+ )
+ (wire (pts (xy 153.67 97.79) (xy 156.21 97.79))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid a538b08d-458a-45a8-ae23-67946f2808f4)
+ )
+ (wire (pts (xy 138.43 97.79) (xy 138.43 86.36))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid a7b3d352-7265-48c3-b84e-daa34c544499)
+ )
+ (wire (pts (xy 104.14 81.28) (xy 99.06 81.28))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid ababd2d9-23ff-4c2c-938d-55e86e10cad0)
+ )
+ (wire (pts (xy 139.7 73.66) (xy 139.7 69.85))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid add4817b-fab3-404c-8ffc-061b9353d6a3)
+ )
+ (wire (pts (xy 104.14 71.12) (xy 104.14 81.28))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid af054dd7-967e-47f8-b22f-91d7a3ae2f01)
+ )
+ (wire (pts (xy 99.06 73.66) (xy 99.06 81.28))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid b3451f5b-43c1-4bd7-bd3b-fa9b890b890d)
+ )
+ (wire (pts (xy 138.43 123.19) (xy 138.43 127))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid b6e3d749-abb3-4c3c-877a-4126ac332219)
+ )
+ (wire (pts (xy 115.57 109.22) (xy 115.57 81.28))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid c1354afc-e3e0-4694-9fbb-2e806bff9f26)
+ )
+ (wire (pts (xy 153.67 97.79) (xy 153.67 101.6))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid c1aab5d3-d06e-4758-b3d0-31a758898176)
+ )
+ (wire (pts (xy 139.7 73.66) (xy 139.7 76.2))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid cbdf201c-10d2-42c9-b208-610ccec1def4)
+ )
+ (wire (pts (xy 158.75 85.09) (xy 158.75 73.66))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid cf042937-8308-4cb0-928a-6ac37a9c34c9)
+ )
+ (wire (pts (xy 138.43 114.3) (xy 138.43 120.65))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid dbafda34-f8cc-4cbb-af9e-6baf684e3657)
+ )
+ (wire (pts (xy 180.34 106.68) (xy 180.34 123.19))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid dc8d414c-3419-4699-9996-33b11816e2c6)
+ )
+ (wire (pts (xy 140.97 113.03) (xy 140.97 120.65))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid dd12b240-675a-42c9-a925-a973882a5507)
+ )
+ (wire (pts (xy 132.08 81.28) (xy 115.57 81.28))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid e97a6413-41f2-4328-83a3-1a30326e0d0a)
+ )
+ (wire (pts (xy 142.24 85.09) (xy 158.75 85.09))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid eb988b37-2cbe-447a-8032-7262692bf862)
+ )
+ (wire (pts (xy 130.81 109.22) (xy 115.57 109.22))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid ed7c08d8-a59b-4e77-9bb9-5f4b41ad2ec0)
+ )
+ (wire (pts (xy 99.06 81.28) (xy 90.17 81.28))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid edc9a8ff-3cc7-4fba-96c3-13ede0b6abfb)
+ )
+ (wire (pts (xy 138.43 97.79) (xy 153.67 97.79))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid efc34b4a-ab3c-4a13-a694-b03998b18352)
+ )
+ (wire (pts (xy 91.44 73.66) (xy 99.06 73.66))
+ (stroke (width 0) (type default) (color 0 0 0 0))
+ (uuid f1e58e95-5b6b-4fc4-9e96-aa74caa04255)
+ )
+
+ (global_label "output" (shape input) (at 153.67 101.6 0) (fields_autoplaced)
+ (effects (font (size 1.27 1.27)) (justify left))
+ (uuid 513c1fc4-dccc-443e-bdd8-39d5ec287ff6)
+ (property "Intersheet References" "${INTERSHEET_REFS}" (id 0) (at 162.1307 101.5206 0)
+ (effects (font (size 1.27 1.27)) (justify left) hide)
+ )
+ )
+ (global_label "input" (shape input) (at 91.44 73.66 180) (fields_autoplaced)
+ (effects (font (size 1.27 1.27)) (justify right))
+ (uuid f8e1b8c5-6525-4ef8-abf8-17cd2ad5bfd2)
+ (property "Intersheet References" "${INTERSHEET_REFS}" (id 0) (at 84.2493 73.7394 0)
+ (effects (font (size 1.27 1.27)) (justify right) hide)
+ )
+ )
+
+ (symbol (lib_id "eSim_Plot:plot_v1") (at 156.21 102.87 0) (unit 1)
+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid 165e3c02-4aa0-4ee4-a03b-afbff72c156d)
+ (property "Reference" "U2" (id 0) (at 160.02 88.9 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Value" "plot_v1" (id 1) (at 160.02 92.71 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Footprint" "" (id 2) (at 156.21 102.87 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 156.21 102.87 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (pin "~" (uuid ad9861ad-883f-4817-94c8-d760267644f8))
+ )
+
+ (symbol (lib_id "eSim_Power:eSim_GND") (at 138.43 127 0) (unit 1)
+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid 345c679b-e7a7-43f6-abc1-704616530570)
+ (property "Reference" "#PWR0101" (id 0) (at 138.43 133.35 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (property "Value" "eSim_GND" (id 1) (at 138.43 132.08 0))
+ (property "Footprint" "" (id 2) (at 138.43 127 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (property "Datasheet" "" (id 3) (at 138.43 127 0)
+ (effects (font (size 1.27 1.27)) hide)
+ )
+ (pin "1" (uuid d0de1379-c82b-4498-9aab-e8423a7c4a95))
+ )
+
+ (symbol (lib_id "eSim_Sources:pwl") (at 90.17 96.52 0) (unit 1)
+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid 432658f5-5185-4bac-9c6b-d6a9d9fc2fda)
+ (property "Reference" "v1" (id 0) (at 95.25 93.345 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Value" "pwl" (id 1) (at 95.25 97.155 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Footprint" "R1" (id 2) (at 95.25 100.965 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Datasheet" "" (id 3) (at 90.17 96.52 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (pin "1" (uuid 8167f4b8-a273-44f5-ac9e-939415d50daf))
+ (pin "2" (uuid bd8692d3-a333-4cd3-8815-54e9d8a7a49c))
+ )
+
+ (symbol (lib_id "eSim_Plot:plot_v1") (at 104.14 76.2 0) (unit 1)
+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid 471c24e3-cbd2-4ecb-aa78-7735d5d39b92)
+ (property "Reference" "U1" (id 0) (at 107.95 62.23 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Value" "plot_v1" (id 1) (at 107.95 66.04 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Footprint" "" (id 2) (at 104.14 76.2 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (property "Datasheet" "" (id 3) (at 104.14 76.2 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (pin "~" (uuid 6d79e20c-1711-48ca-9ecf-fcc2edee830b))
+ )
+
+ (symbol (lib_id "eSim_Devices:eSim_MOS_N") (at 134.62 76.2 0) (unit 1)
+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid 6d052b53-826f-458a-9219-a86e2e66519b)
+ (property "Reference" "XM1" (id 0) (at 143.51 80.0099 0)
+ (effects (font (size 1.27 1.27)) (justify left))
+ )
+ (property "Value" "eSim_MOS_N" (id 1) (at 143.51 82.5499 0)
+ (effects (font (size 1.27 1.27)) (justify left))
+ )
+ (property "Footprint" "" (id 2) (at 142.24 83.82 0)
+ (effects (font (size 0.7366 0.7366)))
+ )
+ (property "Datasheet" "" (id 3) (at 137.16 81.28 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (pin "1" (uuid b863ca0a-0384-4481-b1d9-014924a18c6c))
+ (pin "2" (uuid 77db360b-38d2-4d78-90e7-99fda37930d6))
+ (pin "3" (uuid 9c839e98-9bc5-4344-aa1c-6746916a3a80))
+ (pin "4" (uuid fc1d010c-966b-4d96-ac7e-29aeb9979486))
+ )
+
+ (symbol (lib_id "eSim_Sources:DC") (at 180.34 95.25 0) (unit 1)
+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid adf48e01-4638-4d9b-a8be-f1106864d5da)
+ (property "Reference" "v2" (id 0) (at 185.42 92.075 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Value" "DC" (id 1) (at 185.42 95.885 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Footprint" "R1" (id 2) (at 185.42 99.695 0)
+ (effects (font (size 1.524 1.524)) (justify left))
+ )
+ (property "Datasheet" "" (id 3) (at 180.34 95.25 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (pin "1" (uuid 0179bda0-692b-4569-a148-222a11a689ec))
+ (pin "2" (uuid 3da3bb66-aaab-436d-aab7-1a3522015c55))
+ )
+
+ (symbol (lib_id "eSim_Devices:eSim_MOS_P") (at 134.62 109.22 0) (unit 1)
+ (in_bom yes) (on_board yes) (fields_autoplaced)
+ (uuid fdec8009-ce12-45bf-ae19-21b4eaa52a84)
+ (property "Reference" "XM2" (id 0) (at 142.24 107.9499 0)
+ (effects (font (size 1.27 1.27)) (justify left))
+ )
+ (property "Value" "eSim_MOS_P" (id 1) (at 142.24 110.4899 0)
+ (effects (font (size 1.27 1.27)) (justify left))
+ )
+ (property "Footprint" "" (id 2) (at 140.97 106.68 0)
+ (effects (font (size 0.7366 0.7366)))
+ )
+ (property "Datasheet" "" (id 3) (at 135.89 109.22 0)
+ (effects (font (size 1.524 1.524)))
+ )
+ (pin "1" (uuid e180c4a6-7a36-45ba-b28a-9748bd079263))
+ (pin "2" (uuid 94da1cbf-fe96-4598-ab25-c420ea2559c1))
+ (pin "3" (uuid bbc8c206-c7ff-46b9-beeb-4062b486fd6c))
+ (pin "4" (uuid 2de10ee2-ef5f-431d-81df-3eaf0964473a))
+ )
+
+ (sheet_instances
+ (path "/" (page "1"))
+ )
+
+ (symbol_instances
+ (path "/345c679b-e7a7-43f6-abc1-704616530570"
+ (reference "#PWR0101") (unit 1) (value "eSim_GND") (footprint "")
+ )
+ (path "/471c24e3-cbd2-4ecb-aa78-7735d5d39b92"
+ (reference "U1") (unit 1) (value "plot_v1") (footprint "")
+ )
+ (path "/165e3c02-4aa0-4ee4-a03b-afbff72c156d"
+ (reference "U2") (unit 1) (value "plot_v1") (footprint "")
+ )
+ (path "/6d052b53-826f-458a-9219-a86e2e66519b"
+ (reference "XM1") (unit 1) (value "eSim_MOS_N") (footprint "")
+ )
+ (path "/fdec8009-ce12-45bf-ae19-21b4eaa52a84"
+ (reference "XM2") (unit 1) (value "eSim_MOS_P") (footprint "")
+ )
+ (path "/432658f5-5185-4bac-9c6b-d6a9d9fc2fda"
+ (reference "v1") (unit 1) (value "pwl") (footprint "R1")
+ )
+ (path "/adf48e01-4638-4d9b-a8be-f1106864d5da"
+ (reference "v2") (unit 1) (value "DC") (footprint "R1")
+ )
+ )
+)
diff --git a/library/ihp integration/cmosInverter/cmosInverter.proj b/library/ihp integration/cmosInverter/cmosInverter.proj
new file mode 100644
index 000000000..3ec07abf5
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmosInverter.proj
@@ -0,0 +1 @@
+schematicFile cmosInverter.kicad_sch
diff --git a/library/ihp integration/cmosInverter/cmosInverter.raw b/library/ihp integration/cmosInverter/cmosInverter.raw
new file mode 100644
index 000000000..af800f795
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmosInverter.raw
@@ -0,0 +1,1298 @@
+Title: kicad schematic
+Date: Sun Nov 16 14:08:39 2025
+Plotname: Transient Analysis
+Flags: real
+No. Variables: 6
+No. Points: 214
+Variables:
+ 0 time time
+ 1 v(net-_m1-pad1_) voltage
+ 2 v(input) voltage
+ 3 v(output) voltage
+ 4 i(v1) current
+ 5 i(v2) current
+Values:
+0 0.000000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 0.000000000000000e+00
+ -2.332854625461174e-01
+1 1.000000000000000e-03
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 3.308722450212111e-23
+ -2.332854625461138e-01
+2 2.000000000000000e-03
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 3.308722450212111e-23
+ -2.332854625461138e-01
+3 4.000000000000000e-03
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -1.257314531080602e-22
+ -2.332854625461138e-01
+4 8.000000000000000e-03
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645507e+00
+ -5.624828165360588e-23
+ -2.332854625461138e-01
+5 1.600000000000000e-02
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645507e+00
+ -1.654361225106055e-24
+ -2.332854625461174e-01
+6 3.200000000000000e-02
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645507e+00
+ -1.406207041340147e-23
+ -2.332854625461103e-01
+7 6.400000000000000e-02
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 3.308722450212111e-24
+ -2.332854625461174e-01
+8 1.280000000000000e-01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -2.274746684520826e-24
+ -2.332854625461209e-01
+9 2.280000000000000e-01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 4.549493369041652e-24
+ -2.332854625461138e-01
+10 3.280000000000000e-01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -8.065010972392020e-24
+ -2.332854625461138e-01
+11 4.280000000000000e-01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+12 5.280000000000000e-01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+13 6.280000000000000e-01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+14 7.280000000000000e-01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+15 8.280000000000000e-01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+16 9.279999999999999e-01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+17 1.028000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+18 1.128000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+19 1.228000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+20 1.328000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+21 1.428000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+22 1.528000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+23 1.628000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+24 1.728000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+25 1.828000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+26 1.928000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+27 2.028000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+28 2.128000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+29 2.228000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+30 2.328000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+31 2.428000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+32 2.528000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+33 2.628000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+34 2.728000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+35 2.828000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+36 2.928000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+37 3.028000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+38 3.128000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+39 3.228000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+40 3.328000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+41 3.428000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+42 3.528000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+43 3.628000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+44 3.728000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+45 3.828000000000003e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+46 3.928000000000003e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+47 4.028000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+48 4.128000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+49 4.228000000000002e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+50 4.328000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+51 4.428000000000001e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+52 4.528000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+53 4.628000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+54 4.728000000000000e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+55 4.827999999999999e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+56 4.927999999999999e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+57 5.027999999999999e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+58 5.127999999999998e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+59 5.227999999999998e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+60 5.327999999999998e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+61 5.427999999999997e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+62 5.527999999999997e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+63 5.627999999999997e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+64 5.727999999999996e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+65 5.827999999999996e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+66 5.927999999999995e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+67 6.027999999999995e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+68 6.127999999999995e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+69 6.227999999999994e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+70 6.327999999999994e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+71 6.427999999999994e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+72 6.527999999999993e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+73 6.627999999999993e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+74 6.727999999999993e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+75 6.827999999999992e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+76 6.927999999999992e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+77 7.027999999999992e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+78 7.127999999999991e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+79 7.227999999999991e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+80 7.327999999999991e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+81 7.427999999999990e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+82 7.527999999999990e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+83 7.627999999999989e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+84 7.727999999999989e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+85 7.827999999999989e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+86 7.927999999999988e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+87 8.027999999999988e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+88 8.127999999999988e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+89 8.227999999999987e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+90 8.327999999999987e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+91 8.427999999999987e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+92 8.527999999999986e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+93 8.627999999999986e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+94 8.727999999999986e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+95 8.827999999999985e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+96 8.927999999999985e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+97 9.027999999999984e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+98 9.127999999999984e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+99 9.227999999999984e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+100 9.327999999999983e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+101 9.427999999999983e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+102 9.527999999999983e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+103 9.627999999999982e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+104 9.727999999999982e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+105 9.827999999999982e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 5.169878828456423e-24
+ -2.332854625461138e-01
+106 9.927999999999981e+00
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ -6.410649747285964e-24
+ -2.332854625461138e-01
+107 1.000000000000000e+01
+ 5.000000000000000e+00
+ 0.000000000000000e+00
+ 2.628305822645506e+00
+ 3.308722450212111e-24
+ -2.332854625461209e-01
+108 1.001000000000000e+01
+ 5.000000000000000e+00
+ 4.999999999999893e-02
+ 2.628305992975592e+00
+ -7.665348826357122e-10
+ -2.332854376469982e-01
+109 1.003000000000000e+01
+ 5.000000000000000e+00
+ 1.499999999999968e-01
+ 2.628306279035034e+00
+ -7.670511497948279e-10
+ -2.332853965384878e-01
+110 1.007000000000000e+01
+ 5.000000000000000e+00
+ 3.499999999999925e-01
+ 2.628306714061739e+00
+ -7.678658728391872e-10
+ -2.332853340224439e-01
+111 1.015000000000000e+01
+ 5.000000000000000e+00
+ 7.499999999999929e-01
+ 2.628306917573378e+00
+ -6.177974825956485e-10
+ -2.332853047765617e-01
+112 1.025000000000000e+01
+ 5.000000000000000e+00
+ 1.249999999999991e+00
+ 2.628306917833742e+00
+ -6.078676114868122e-10
+ -2.332853047391446e-01
+113 1.035000000000000e+01
+ 5.000000000000000e+00
+ 1.749999999999989e+00
+ 2.628306917842596e+00
+ -9.548763791999386e-10
+ -2.332853047378727e-01
+114 1.045000000000000e+01
+ 5.000000000000000e+00
+ 2.249999999999988e+00
+ 2.628306917833745e+00
+ -7.265240367590002e-10
+ -2.332853047391446e-01
+115 1.055000000000000e+01
+ 5.000000000000000e+00
+ 2.749999999999986e+00
+ 2.628306917842596e+00
+ -9.595108823468656e-10
+ -2.332853047379437e-01
+116 1.065000000000000e+01
+ 5.000000000000000e+00
+ 3.249999999999984e+00
+ 2.628306917833745e+00
+ -7.219652510596598e-10
+ -2.332853047437773e-01
+117 1.075000000000000e+01
+ 5.000000000000000e+00
+ 3.749999999999982e+00
+ 2.628306917842601e+00
+ -8.412373593130030e-10
+ -2.332853048562242e-01
+118 1.085000000000000e+01
+ 5.000000000000000e+00
+ 4.249999999999980e+00
+ 2.628306918437656e+00
+ -3.938526632097084e-10
+ -2.332853051468220e-01
+119 1.095000000000000e+01
+ 5.000000000000000e+00
+ 4.749999999999979e+00
+ 2.628308437459640e+00
+ -1.027592554450317e-09
+ -2.332854932397446e-01
+120 1.100000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625494486e+00
+ -5.135022931343027e-10
+ -2.332858891276857e-01
+121 1.101000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311589266800e+00
+ -4.511207935519557e-14
+ -2.332858848395141e-01
+122 1.103000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925317827556663e-16
+ -2.332858893341374e-01
+123 1.107000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925311371411982e-16
+ -2.332858893341339e-01
+124 1.115000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314535377825e-16
+ -2.332858893341445e-01
+125 1.125000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314527106019e-16
+ -2.332858893341374e-01
+126 1.135000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314518834213e-16
+ -2.332858893341374e-01
+127 1.145000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314518834213e-16
+ -2.332858893341374e-01
+128 1.155000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314527106019e-16
+ -2.332858893341374e-01
+129 1.165000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314518834213e-16
+ -2.332858893341374e-01
+130 1.175000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314527106019e-16
+ -2.332858893341374e-01
+131 1.185000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314535377825e-16
+ -2.332858893341374e-01
+132 1.195000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314543649631e-16
+ -2.332858893341374e-01
+133 1.205000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314535377825e-16
+ -2.332858893341374e-01
+134 1.215000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314543649631e-16
+ -2.332858893341374e-01
+135 1.224999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314535377825e-16
+ -2.332858893341374e-01
+136 1.234999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314543649631e-16
+ -2.332858893341374e-01
+137 1.244999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314535377825e-16
+ -2.332858893341374e-01
+138 1.254999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314560193243e-16
+ -2.332858893341374e-01
+139 1.264999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314551921437e-16
+ -2.332858893341374e-01
+140 1.274999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314560193243e-16
+ -2.332858893341374e-01
+141 1.284999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314551921437e-16
+ -2.332858893341374e-01
+142 1.294999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314560193243e-16
+ -2.332858893341374e-01
+143 1.304999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314568465049e-16
+ -2.332858893341374e-01
+144 1.314999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314576736855e-16
+ -2.332858893341374e-01
+145 1.324999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314568465049e-16
+ -2.332858893341374e-01
+146 1.334999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314576736855e-16
+ -2.332858893341374e-01
+147 1.344999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314568465049e-16
+ -2.332858893341374e-01
+148 1.354999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314576736855e-16
+ -2.332858893341374e-01
+149 1.364999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314568465049e-16
+ -2.332858893341374e-01
+150 1.374999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314593280468e-16
+ -2.332858893341374e-01
+151 1.384999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314585008662e-16
+ -2.332858893341374e-01
+152 1.394999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314593280468e-16
+ -2.332858893341374e-01
+153 1.404999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314585008662e-16
+ -2.332858893341374e-01
+154 1.414999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314593280468e-16
+ -2.332858893341374e-01
+155 1.424999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314585008662e-16
+ -2.332858893341374e-01
+156 1.434999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314593280468e-16
+ -2.332858893341374e-01
+157 1.444999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314601552274e-16
+ -2.332858893341374e-01
+158 1.454999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314609824080e-16
+ -2.332858893341374e-01
+159 1.464999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314601552274e-16
+ -2.332858893341374e-01
+160 1.474999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314609824080e-16
+ -2.332858893341374e-01
+161 1.484999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314601552274e-16
+ -2.332858893341374e-01
+162 1.494999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314609824080e-16
+ -2.332858893341374e-01
+163 1.504999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314618095886e-16
+ -2.332858893341374e-01
+164 1.514999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314626367692e-16
+ -2.332858893341374e-01
+165 1.524999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314618095886e-16
+ -2.332858893341374e-01
+166 1.534999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314626367692e-16
+ -2.332858893341374e-01
+167 1.544999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314618095886e-16
+ -2.332858893341374e-01
+168 1.554999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314626367692e-16
+ -2.332858893341374e-01
+169 1.564999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314634639498e-16
+ -2.332858893341374e-01
+170 1.574999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314642911304e-16
+ -2.332858893341374e-01
+171 1.584999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314634639498e-16
+ -2.332858893341374e-01
+172 1.594999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314642911304e-16
+ -2.332858893341374e-01
+173 1.604999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314634639498e-16
+ -2.332858893341374e-01
+174 1.614999999999998e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314642911304e-16
+ -2.332858893341374e-01
+175 1.624999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314634639498e-16
+ -2.332858893341374e-01
+176 1.634999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314659454917e-16
+ -2.332858893341374e-01
+177 1.644999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314651183111e-16
+ -2.332858893341374e-01
+178 1.654999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314659454917e-16
+ -2.332858893341374e-01
+179 1.664999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314651183111e-16
+ -2.332858893341374e-01
+180 1.674999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314659454917e-16
+ -2.332858893341374e-01
+181 1.684999999999999e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314651183111e-16
+ -2.332858893341374e-01
+182 1.695000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314659454917e-16
+ -2.332858893341374e-01
+183 1.705000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314667726723e-16
+ -2.332858893341374e-01
+184 1.715000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314675998529e-16
+ -2.332858893341374e-01
+185 1.725000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314667726723e-16
+ -2.332858893341374e-01
+186 1.735000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314675998529e-16
+ -2.332858893341374e-01
+187 1.745000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314667726723e-16
+ -2.332858893341374e-01
+188 1.755000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314692542141e-16
+ -2.332858893341374e-01
+189 1.765000000000001e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314684270335e-16
+ -2.332858893341374e-01
+190 1.775000000000001e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314692542141e-16
+ -2.332858893341374e-01
+191 1.785000000000001e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314684270335e-16
+ -2.332858893341374e-01
+192 1.795000000000001e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314692542141e-16
+ -2.332858893341374e-01
+193 1.805000000000001e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314684270335e-16
+ -2.332858893341374e-01
+194 1.815000000000001e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314692542141e-16
+ -2.332858893341374e-01
+195 1.825000000000001e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314700813947e-16
+ -2.332858893341374e-01
+196 1.835000000000002e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314709085753e-16
+ -2.332858893341374e-01
+197 1.845000000000002e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314700813947e-16
+ -2.332858893341374e-01
+198 1.855000000000002e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314709085753e-16
+ -2.332858893341374e-01
+199 1.865000000000002e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314700813947e-16
+ -2.332858893341374e-01
+200 1.875000000000002e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314709085753e-16
+ -2.332858893341374e-01
+201 1.885000000000002e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314700813947e-16
+ -2.332858893341374e-01
+202 1.895000000000002e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314725629366e-16
+ -2.332858893341374e-01
+203 1.905000000000003e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314717357560e-16
+ -2.332858893341374e-01
+204 1.915000000000003e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314725629366e-16
+ -2.332858893341374e-01
+205 1.925000000000003e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314717357560e-16
+ -2.332858893341374e-01
+206 1.935000000000003e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314725629366e-16
+ -2.332858893341374e-01
+207 1.945000000000003e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314733901172e-16
+ -2.332858893341374e-01
+208 1.955000000000003e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314742172978e-16
+ -2.332858893341374e-01
+209 1.965000000000003e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314733901172e-16
+ -2.332858893341374e-01
+210 1.975000000000004e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314742172978e-16
+ -2.332858893341374e-01
+211 1.985000000000004e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314733901172e-16
+ -2.332858893341374e-01
+212 1.995000000000004e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ 8.925314742172978e-16
+ -2.332858893341374e-01
+213 2.000000000000000e+01
+ 5.000000000000000e+00
+ 5.000000000000000e+00
+ 2.628311625487040e+00
+ -8.925314696678044e-16
+ -2.332858893341339e-01
diff --git a/library/ihp integration/cmosInverter/cmosInverterRun.cir b/library/ihp integration/cmosInverter/cmosInverterRun.cir
new file mode 100644
index 000000000..5f9f37c8d
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmosInverterRun.cir
@@ -0,0 +1,41 @@
+* cmos_ihp.cir -- CMOS inverter using IHP SG13G2 PDK (try this first)
+.title CMOS inverter using IHP SG13G2 PDK
+
+* Load the corner section from the IHP PDK (defines params, includes subckt file)
+.lib "C:/Users/KEERTHANA/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib" mos_tt
+
+.global GND
+
+* Power rail (taken from KiCad node Net-_XM1-Pad1_)
+VDD Net-_XM1-Pad1_ GND DC 1.2
+
+* Input: simple PWL (toggle)
+VIN input GND PWL(0ns 0 2ns 0 4ns 1.2 9ns 1.2 11ns 0 20ns 0)
+
+* Transistor instances (Drain Gate Source Bulk Model)
+* PMOS: source & bulk -> VDD
+XM2 output input Net-_XM1-Pad1_ Net-_XM1-Pad1_ sg13_lv_pmos w=2.0u l=0.13u
+
+* NMOS: source & bulk -> GND
+XM1 output input GND GND sg13_lv_nmos w=1.0u l=0.13u
+
+* optional: probe nodes (not required by netlist)
+* U2 output plot_v1
+* U1 input plot_v1
+
+.control
+* transient sim: time step 0.1ns, total 40ns
+tran 0.1n 40n
+run
+
+* plot waveforms
+plot v(input) v(output)
+
+* print DC operating point of NMOS (optional)
+op
+let Id = @m.xm1[id]
+print Id
+
+.endc
+
+.end
diff --git a/library/ihp integration/cmosInverter/cmosInverter_Previous_Values.xml b/library/ihp integration/cmosInverter/cmosInverter_Previous_Values.xml
new file mode 100644
index 000000000..9f1bcd799
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmosInverter_Previous_Values.xml
@@ -0,0 +1 @@
+dc5pwl0 0 10 0 11 5 20 5truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.120secsecsec
\ No newline at end of file
diff --git a/library/ihp integration/cmosInverter/cmos_fallback_fixed.cir.txt b/library/ihp integration/cmosInverter/cmos_fallback_fixed.cir.txt
new file mode 100644
index 000000000..3607709ad
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmos_fallback_fixed.cir.txt
@@ -0,0 +1,26 @@
+* CMOS inverter - Windows-safe version (no Verilog-A needed)
+.title CMOS inverter (fallback models)
+
+.global GND
+
+* Power
+VDD vdd GND DC 1.2
+
+* Input
+VIN input GND PWL(0ns 0 2ns 0 4ns 1.2 9ns 1.2 11ns 0 20ns 0)
+
+* Simple built-in MOS models
+.model NMOS NMOS (VTO=0.6 KP=100u)
+.model PMOS PMOS (VTO=-0.6 KP=40u)
+
+* Devices: D G S B
+M1 output input GND GND NMOS W=1u L=0.13u
+M2 output input vdd vdd PMOS W=2u L=0.13u
+
+.control
+tran 0.1n 40n
+run
+plot v(input) v(output)
+.endc
+
+.end
diff --git a/library/ihp integration/cmosInverter/cmos_fixed.cir b/library/ihp integration/cmosInverter/cmos_fixed.cir
new file mode 100644
index 000000000..d5e0b99c7
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmos_fixed.cir
@@ -0,0 +1,28 @@
+* cir_run.cir -- NMOS DC Test using IHP SG13G2 TT Corner
+.title NMOS DC Test using IHP SG13G2 TT Corner
+
+* Load the PDK corner (this defines the parameters and pulls in the model file)
+.lib "C:/Users/KEERTHANA/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib" mos_tt
+
+* Global reference
+.GLOBAL GND
+
+* Bias sources
+Vgs net1 GND 0.4
+Vds net3 GND 1.0
+Vd net3 net2 0
+
+.param temp=27
+
+* Device under test
+* Drain = net2, Gate = net1, Source = GND, Bulk = GND
+XM1 net2 net1 GND GND sg13_lv_nmos w=1.0u l=0.13u ng=1 m=1
+
+.control
+* save all ; optional - you can keep or remove
+op
+let Id = @m.xm1[id]
+print Id
+.endc
+
+.end
diff --git a/library/ihp integration/cmosInverter/cmos_run.cir b/library/ihp integration/cmosInverter/cmos_run.cir
new file mode 100644
index 000000000..d5e0b99c7
--- /dev/null
+++ b/library/ihp integration/cmosInverter/cmos_run.cir
@@ -0,0 +1,28 @@
+* cir_run.cir -- NMOS DC Test using IHP SG13G2 TT Corner
+.title NMOS DC Test using IHP SG13G2 TT Corner
+
+* Load the PDK corner (this defines the parameters and pulls in the model file)
+.lib "C:/Users/KEERTHANA/IHP-Open-PDK/ihp-sg13g2/libs.tech/ngspice/models/cornerMOSlv.lib" mos_tt
+
+* Global reference
+.GLOBAL GND
+
+* Bias sources
+Vgs net1 GND 0.4
+Vds net3 GND 1.0
+Vd net3 net2 0
+
+.param temp=27
+
+* Device under test
+* Drain = net2, Gate = net1, Source = GND, Bulk = GND
+XM1 net2 net1 GND GND sg13_lv_nmos w=1.0u l=0.13u ng=1 m=1
+
+.control
+* save all ; optional - you can keep or remove
+op
+let Id = @m.xm1[id]
+print Id
+.endc
+
+.end
diff --git a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib
index 79b70d61a..718d5fb48 100644
--- a/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib
+++ b/library/kicadLibrary/kicad_eSim-Library/eSim_Subckt.lib
@@ -1,1350 +1,2026 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# 10bitDAC
-#
-DEF 10bitDAC X 0 40 Y Y 1 F N
-F0 "X" 0 50 60 H V C CNN
-F1 "10bitDAC" -50 -50 60 H V C CNN
-F2 "" 0 50 60 H I C CNN
-F3 "" 0 50 60 H I C CNN
-DRAW
-S -500 500 400 -600 0 1 0 N
-X D0 1 -700 -500 200 R 50 50 1 1 I
-X D1 2 -700 -400 200 R 50 50 1 1 I
-X D2 3 -700 -300 200 R 50 50 1 1 I
-X D3 4 -700 -200 200 R 50 50 1 1 I
-X D4 5 -700 -100 200 R 50 50 1 1 I
-X D5 6 -700 0 200 R 50 50 1 1 I
-X D6 7 -700 100 200 R 50 50 1 1 I
-X D7 8 -700 200 200 R 50 50 1 1 I
-X D8 9 -700 300 200 R 50 50 1 1 I
-X D9 10 -700 400 200 R 50 50 1 1 I
-X AnalogOut 11 600 350 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 2BITMUL
-#
-DEF 2BITMUL X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "2BITMUL" 0 0 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -300 400 300 -400 0 1 0 N
-X A0 1 -500 300 200 R 50 50 1 1 I
-X A1 2 -500 150 200 R 50 50 1 1 I
-X B0 3 -500 -50 200 R 50 50 1 1 I
-X B1 4 -500 -250 200 R 50 50 1 1 I
-X M0 5 500 250 200 L 50 50 1 1 O
-X M1 6 500 100 200 L 50 50 1 1 O
-X M2 7 500 -50 200 L 50 50 1 1 O
-X M3 8 500 -250 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 3_and
-#
-DEF 3_and X 0 40 Y Y 1 F N
-F0 "X" 100 -50 60 H V C CNN
-F1 "3_and" 150 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
-P 2 0 1 0 -150 200 200 200 N
-P 3 0 1 0 -150 200 -150 -100 200 -100 N
-X in1 1 -350 150 200 R 50 50 1 1 I
-X in2 2 -350 50 200 R 50 50 1 1 I
-X in3 3 -350 -50 200 R 50 50 1 1 I
-X out 4 500 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_OR
-#
-DEF 4_OR X 0 40 Y Y 1 F N
-F0 "X" 150 -100 60 H V C CNN
-F1 "4_OR" 150 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
-A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
-A -30 -99 393 627 146 0 1 0 N 150 250 350 0
-P 2 0 1 0 -200 -250 150 -250 N
-P 2 0 1 0 -200 250 150 250 N
-X in1 1 -350 150 200 R 50 50 1 1 I
-X in2 2 -350 50 200 R 50 50 1 1 I
-X in3 3 -350 -50 200 R 50 50 1 1 I
-X in4 4 -350 -150 200 R 50 50 1 1 I
-X out 5 550 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_and
-#
-DEF 4_and X 0 40 Y Y 1 F N
-F0 "X" 50 -50 60 H V C CNN
-F1 "4_and" 100 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
-P 2 0 1 0 -200 200 150 200 N
-P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
-X in1 1 -400 150 200 R 50 50 1 1 I
-X in2 2 -400 50 200 R 50 50 1 1 I
-X in3 3 -400 -50 200 R 50 50 1 1 I
-X in4 4 -400 -150 200 R 50 50 1 1 I
-X out 5 500 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 4_input_nor
-#
-DEF 4_input_nor X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "4_input_nor" 0 -150 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -700 450 800 -350 0 1 0 N
-X B 1 -900 150 200 R 50 50 1 1 I
-X C 2 -900 50 200 R 50 50 1 1 I
-X D 3 -900 -50 200 R 50 50 1 1 I
-X A 4 -900 250 200 R 50 50 1 1 I
-X G 5 -900 -150 200 R 50 50 1 1 I
-X Y 6 1000 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# 556
-#
-DEF 556 X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "556" 0 0 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -300 400 250 -550 0 1 0 N
-X dis1 1 -500 150 200 R 50 50 1 1 I
-X thr1 2 -500 -150 200 R 50 50 1 1 I
-X cv1 3 -150 -750 200 U 50 50 1 1 I
-X rst1 4 -200 600 200 D 50 50 1 1 I
-X out1 5 -500 0 200 R 50 50 1 1 O
-X trig1 6 -500 -300 200 R 50 50 1 1 I
-X gnd 7 0 -750 200 U 50 50 1 1 I
-X trig2 8 450 -300 200 L 50 50 1 1 I
-X out2 9 450 0 200 L 50 50 1 1 O
-X rst2 10 100 600 200 D 50 50 1 1 I
-X cv2 11 150 -750 200 U 50 50 1 1 I
-X thr2 12 450 -150 200 L 50 50 1 1 I
-X dis2 13 450 150 200 L 50 50 1 1 I
-X vcc 14 -50 600 200 D 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# 5_and
-#
-DEF 5_and X 0 40 Y Y 1 F N
-F0 "X" 50 -100 60 H V C CNN
-F1 "5_and" 100 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 100 0 255 787 -787 0 1 0 N 150 250 150 -250
-P 2 0 1 0 -250 250 150 250 N
-P 3 0 1 0 -250 250 -250 -250 150 -250 N
-X in1 1 -450 200 200 R 50 50 1 1 I
-X in2 2 -450 100 200 R 50 50 1 1 I
-X in3 3 -450 0 200 R 50 50 1 1 I
-X in4 4 -450 -100 200 R 50 50 1 1 I
-X in5 5 -450 -200 200 R 50 50 1 1 I
-X out 6 550 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# AP331
-#
-DEF AP331 X 0 40 Y Y 1 F N
-F0 "X" 0 250 60 H V C CNN
-F1 "AP331" 0 -350 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -200 200 200 -300 0 1 0 N
-X IN- 1 -400 100 200 R 50 50 1 1 I
-X GND 2 -400 -50 200 R 50 50 1 1 I
-X IN+ 3 -400 -250 200 R 50 50 1 1 I
-X OUT 4 400 -250 200 L 50 50 1 1 O
-X VCC 5 400 50 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# And_or_gate
-#
-DEF And_or_gate X 0 40 Y Y 1 F N
-F0 "X" 50 50 60 H V C CNN
-F1 "And_or_gate" 50 -100 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -400 250 500 -250 0 1 0 N
-X A 1 -600 150 200 R 50 50 1 1 I
-X B 2 -600 0 200 R 50 50 1 1 I
-X C 3 -600 -150 200 R 50 50 1 1 I
-X Out 4 700 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# CD4007
-#
-DEF CD4007 X 0 40 Y Y 1 F N
-F0 "X" 100 0 60 H V C CNN
-F1 "CD4007" 200 -300 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -800 650 1150 -800 0 1 0 N
-X Q2(P)_Drain 1 -1000 450 200 R 50 50 1 1 O
-X Q2(P)_Source 2 -1000 250 200 R 50 50 1 1 I
-X Q3_Gate 3 -1000 100 200 R 50 50 1 1 I
-X Q2(N)_Source 4 -1000 -100 200 R 50 50 1 1 I
-X Q2(N)_Drain 5 -1000 -250 200 R 50 50 1 1 O
-X Q1_Gate 6 -1000 -450 200 R 50 50 1 1 I
-X VSS 7 -1000 -600 200 R 50 50 1 1 I
-X Q1(N)_Drain 8 1350 -600 200 L 50 50 1 1 O
-X Q3(N)_Source 9 1350 -450 200 L 50 50 1 1 I
-X Q3_Gate 10 1350 -250 200 L 50 50 1 1 I
-X Q3(P)_Drain 11 1350 -100 200 L 50 50 1 1 I
-X Q3_Drain_Source 12 1350 100 200 L 50 50 1 1 O
-X Q1(P)_Source 13 1350 300 200 L 50 50 1 1 O
-X VDD 14 1350 500 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# CD4063
-#
-DEF CD4063 X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "CD4063" 150 -700 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -600 700 650 -900 0 1 0 N
-X A0 1 -800 500 200 R 50 50 1 1 I
-X A1 2 -800 400 200 R 50 50 1 1 I
-X A2 3 -800 300 200 R 50 50 1 1 I
-X A3 4 -800 200 200 R 50 50 1 1 I
-X B0 5 -800 100 200 R 50 50 1 1 I
-X B1 6 -800 0 200 R 50 50 1 1 I
-X B2 7 -800 -150 200 R 50 50 1 1 I
-X B3 8 -800 -250 200 R 50 50 1 1 I
-X (AB)IN 10 -800 -550 200 R 50 50 1 1 I
-X (A=B)IN 11 -800 -700 200 R 50 50 1 1 I
-X (AB)OUT 13 850 -150 200 L 50 50 1 1 O
-X (A=B)OUT 14 850 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# CD4066
-#
-DEF CD4066 X 0 40 Y Y 1 F N
-F0 "X" -150 450 60 H V C CNN
-F1 "CD4066" -150 -100 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -900 550 700 -150 0 1 0 N
-X SIG_A_IN/OUT 1 -1100 500 200 R 50 50 1 1 B
-X SIG_A_OUT/IN 2 -1100 400 200 R 50 50 1 1 B
-X SIG_B_OUT/IN 3 -1100 300 200 R 50 50 1 1 B
-X SIG_B_IN/OUT 4 -1100 200 200 R 50 50 1 1 B
-X CONTROL_B 5 -1100 100 200 R 50 50 1 1 I
-X CONTROL_C 6 -1100 0 200 R 50 50 1 1 I
-X VSS 7 -1100 -100 200 R 50 50 1 1 I
-X SIG_C_IN/OUT 8 900 -100 200 L 50 50 1 1 B
-X SIG_C_OUT/IN 9 900 0 200 L 50 50 1 1 B
-X SIG_D_OUT/IN 10 900 100 200 L 50 50 1 1 B
-X SIG_D_IN/OUT 11 900 200 200 L 50 50 1 1 B
-X CONTROL_D 12 900 300 200 L 50 50 1 1 I
-X CONTROL_A 13 900 400 200 L 50 50 1 1 I
-X VDD 14 900 500 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# CD4585
-#
-DEF CD4585 X 0 40 Y Y 1 F N
-F0 "X" -50 50 60 H V C CNN
-F1 "CD4585" 0 -450 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -650 650 550 -1000 0 1 0 N
-X A3 1 -850 500 200 R 50 50 1 1 I
-X B3 2 -850 100 200 R 50 50 1 1 I
-X A2 3 -850 400 200 R 50 50 1 1 I
-X B2 4 -850 -50 200 R 50 50 1 1 I
-X A1 5 -850 300 200 R 50 50 1 1 I
-X (AB)IN 8 -850 -800 200 R 50 50 1 1 I
-X B1 9 -850 -200 200 R 50 50 1 1 I
-X A0 10 -850 200 200 R 50 50 1 1 I
-X B0 11 -850 -350 200 R 50 50 1 1 I
-X (AB)OUT 14 750 -200 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# CD_4007
-#
-DEF CD_4007 X 0 40 Y Y 1 F N
-F0 "X" 50 500 60 H V C CNN
-F1 "CD_4007" 0 -700 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -650 700 700 -800 0 1 0 N
-X Q2(P)_Drain 1 -850 350 200 R 50 50 1 1 I
-X Q2(P)_Source 2 -850 200 200 R 50 50 1 1 I
-X Q3_Gate 3 -850 50 200 R 50 50 1 1 I
-X Q2(N)_Source 4 -850 -150 200 R 50 50 1 1 I
-X Q2(N)_Drain 5 -850 -300 200 R 50 50 1 1 I
-X Q1_Gate 6 -850 -450 200 R 50 50 1 1 I
-X VSS 7 -850 -600 200 R 50 50 1 1 I
-X Q1(N)_Drain 8 900 -500 200 L 50 50 1 1 I
-X Q3(N)_Source 9 900 -350 200 L 50 50 1 1 I
-X Q3_Gate 10 900 -200 200 L 50 50 1 1 I
-X Q3(P)_Drain 11 900 -50 200 L 50 50 1 1 I
-X Q3_Drain_Source 12 900 150 200 L 50 50 1 1 I
-X Q1(P)_Source 13 900 300 200 L 50 50 1 1 I
-X VDD 14 900 450 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# CMOS_NAND
-#
-DEF CMOS_NAND X 0 40 Y Y 1 F N
-F0 "X" -100 -150 60 H V C CNN
-F1 "CMOS_NAND" 0 -50 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400
-C 550 0 50 0 1 0 N
-P 2 0 1 0 -350 300 300 300 N
-P 3 0 1 0 -350 300 -350 -400 300 -400 N
-X in1 1 -550 250 200 R 50 50 1 1 I
-X in2 2 -550 -300 200 R 50 50 1 1 I
-X out 3 800 0 279 L 79 79 1 1 I
-ENDDRAW
-ENDDEF
-#
-# COMPARATOR
-#
-DEF COMPARATOR X 0 40 Y Y 1 F N
-F0 "X" 200 200 60 H V C CNN
-F1 "COMPARATOR" 250 -150 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -500 300 600 -200 0 1 0 N
-X NON_INV_INP 1 -700 200 200 R 50 50 1 1 I
-X INV_INP 2 -700 100 200 R 50 50 1 1 I
-X GND 3 -700 0 200 R 50 50 1 1 I
-X OUT 4 800 50 200 L 50 50 1 1 O
-X VCC 5 -700 -100 200 R 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# Clock_pulse_generator
-#
-DEF Clock_pulse_generator X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "Clock_pulse_generator" 0 -100 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -550 200 600 -300 0 1 0 N
-X Vdd 1 -750 100 200 R 50 50 1 1 I
-X R 2 -750 -50 200 R 50 50 1 1 I
-X C 3 -750 -200 200 R 50 50 1 1 I
-X Clkout 4 800 0 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# HCF4066
-#
-DEF HCF4066 X 0 40 Y Y 1 F N
-F0 "X" -150 450 60 H V C CNN
-F1 "HCF4066" -150 -100 60 H V C CNN
-F2 "" 0 0 60 H I C CNN
-F3 "" 0 0 60 H I C CNN
-DRAW
-S -900 550 700 -150 0 1 0 N
-X SIG_A_IN/OUT 1 -1100 500 200 R 50 50 1 1 B
-X SIG_A_OUT/IN 2 -1100 400 200 R 50 50 1 1 B
-X SIG_B_OUT/IN 3 -1100 300 200 R 50 50 1 1 B
-X SIG_B_IN/OUT 4 -1100 200 200 R 50 50 1 1 B
-X CONTROL_B 5 -1100 100 200 R 50 50 1 1 I
-X CONTROL_C 6 -1100 0 200 R 50 50 1 1 I
-X VSS 7 -1100 -100 200 R 50 50 1 1 I
-X SIG_C_IN/OUT 8 900 -100 200 L 50 50 1 1 B
-X SIG_C_OUT/IN 9 900 0 200 L 50 50 1 1 B
-X SIG_D_OUT/IN 10 900 100 200 L 50 50 1 1 B
-X SIG_D_IN/OUT 11 900 200 200 L 50 50 1 1 B
-X CONTROL_D 12 900 300 200 L 50 50 1 1 I
-X CONTROL_A 13 900 400 200 L 50 50 1 1 I
-X VDD 14 900 500 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# IC_4002
-#
-DEF IC_4002 X 0 40 Y Y 1 F N
-F0 "X" 0 150 60 H V C CNN
-F1 "IC_4002" 0 0 60 H V C CNN
-F2 "" 50 -150 60 H V C CNN
-F3 "" 50 -150 60 H V C CNN
-DRAW
-S -250 350 250 -400 0 1 0 N
-X 1Y 1 -450 250 200 R 50 50 1 1 O
-X 1A 2 -450 150 200 R 50 50 1 1 I
-X 1B 3 -450 50 200 R 50 50 1 1 I
-X 1C 4 -450 -50 200 R 50 50 1 1 I
-X 1D 5 -450 -150 200 R 50 50 1 1 I
-X NC 6 -450 -250 200 R 50 50 1 1 I
-X GND 7 -450 -350 200 R 50 50 1 1 I
-X NC 8 450 -350 200 L 50 50 1 1 I
-X 2A 9 450 -250 200 L 50 50 1 1 I
-X 2B 10 450 -150 200 L 50 50 1 1 I
-X 2C 11 450 -50 200 L 50 50 1 1 I
-X 2D 12 450 50 200 L 50 50 1 1 I
-X 2Y 13 450 150 200 L 50 50 1 1 O
-X VCC 14 450 250 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# IC_4012
-#
-DEF IC_4012 X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "IC_4012" 0 200 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -300 400 350 -400 0 1 0 N
-X Q1 1 -500 300 200 R 50 50 1 1 O
-X A1 2 -500 200 200 R 50 50 1 1 I
-X B1 3 -500 100 200 R 50 50 1 1 I
-X C1 4 -500 0 200 R 50 50 1 1 I
-X D1 5 -500 -100 200 R 50 50 1 1 I
-X NC 6 -500 -200 200 R 50 50 1 1 N
-X VSS 7 -500 -300 200 R 50 50 1 1 I
-X NC 8 550 -300 200 L 50 50 1 1 N
-X A2 9 550 -200 200 L 50 50 1 1 I
-X B2 10 550 -100 200 L 50 50 1 1 I
-X C2 11 550 0 200 L 50 50 1 1 I
-X D2 12 550 100 200 L 50 50 1 1 I
-X Q2 13 550 200 200 L 50 50 1 1 O
-X VDD 14 550 300 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# IC_4017
-#
-DEF IC_4017 X 0 40 Y Y 1 F N
-F0 "X" 0 0 60 H V C CNN
-F1 "IC_4017" 0 0 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -350 850 400 -850 0 1 0 N
-X 1 1 600 650 200 L 50 50 1 1 O
-X 2 2 600 500 200 L 50 50 1 1 O
-X 3 3 600 350 200 L 50 50 1 1 O
-X 4 4 600 200 200 L 50 50 1 1 O
-X 5 5 600 50 200 L 50 50 1 1 O
-X 6 6 600 -100 200 L 50 50 1 1 O
-X 7 7 600 -250 200 L 50 50 1 1 O
-X 8 8 600 -400 200 L 50 50 1 1 O
-X 9 9 600 -600 200 L 50 50 1 1 O
-X 10 10 600 -750 200 L 50 50 1 1 O
-X RST 11 -550 -400 200 R 50 50 1 1 I
-X CLK 12 -550 350 200 R 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# IC_4023
-#
-DEF IC_4023 X 0 40 Y Y 1 F N
-F0 "X" 0 -100 60 H V C CNN
-F1 "IC_4023" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -300 450 300 -450 0 1 0 N
-X A1 1 -500 300 200 R 50 50 1 1 I
-X B1 2 -500 200 200 R 50 50 1 1 I
-X A2 3 -500 100 200 R 50 50 1 1 I
-X B2 4 -500 0 200 R 50 50 1 1 I
-X C2 5 -500 -100 200 R 50 50 1 1 I
-X Q2 6 -500 -200 200 R 50 50 1 1 O
-X Vss 7 -500 -300 200 R 50 50 1 1 I
-X C1 8 500 -300 200 L 50 50 1 1 I
-X Q1 9 500 -200 200 L 50 50 1 1 O
-X Q3 10 500 -100 200 L 50 50 1 1 O
-X C3 11 500 0 200 L 50 50 1 1 I
-X B3 12 500 100 200 L 50 50 1 1 I
-X A3 13 500 200 200 L 50 50 1 1 I
-X Vdd 14 500 300 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# IC_4028
-#
-DEF IC_4028 X 0 40 Y Y 1 F N
-F0 "X" 0 -100 60 H V C CNN
-F1 "IC_4028" 0 50 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -300 450 300 -450 0 1 0 N
-X Q4 1 -500 350 200 R 50 50 1 1 O
-X Q2 2 -500 250 200 R 50 50 1 1 O
-X Q0 3 -500 150 200 R 50 50 1 1 O
-X Q7 4 -500 50 200 R 50 50 1 1 O
-X Q9 5 -500 -50 200 R 50 50 1 1 O
-X Q5 6 -500 -150 200 R 50 50 1 1 O
-X Q6 7 -500 -250 200 R 50 50 1 1 O
-X Vss 8 -500 -350 200 R 50 50 1 1 I
-X Q8 9 500 -350 200 L 50 50 1 1 O
-X A0 10 500 -250 200 L 50 50 1 1 I
-X A3 11 500 -150 200 L 50 50 1 1 I
-X A2 12 500 -50 200 L 50 50 1 1 I
-X A1 13 500 50 200 L 50 50 1 1 I
-X Q1 14 500 150 200 L 50 50 1 1 O
-X Q3 15 500 250 200 L 50 50 1 1 O
-X Vdd 16 500 350 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# IC_4073
-#
-DEF IC_4073 X 0 40 Y Y 1 F N
-F0 "X" 0 -100 60 H V C CNN
-F1 "IC_4073" 0 50 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-S -300 400 300 -400 0 1 0 N
-X A1 1 -500 300 200 R 50 50 1 1 I
-X B1 2 -500 200 200 R 50 50 1 1 I
-X A2 3 -500 100 200 R 50 50 1 1 I
-X B2 4 -500 0 200 R 50 50 1 1 I
-X C2 5 -500 -100 200 R 50 50 1 1 I
-X Q2 6 -500 -200 200 R 50 50 1 1 O
-X Vss 7 -500 -300 200 R 50 50 1 1 I
-X C1 8 500 -300 200 L 50 50 1 1 I
-X Q1 9 500 -200 200 L 50 50 1 1 O
-X Q3 10 500 -100 200 L 50 50 1 1 O
-X A3 11 500 0 200 L 50 50 1 1 I
-X B3 12 500 100 200 L 50 50 1 1 I
-X C3 13 500 200 200 L 50 50 1 1 I
-X Vdd 14 500 300 200 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# IC_74153
-#
-DEF IC_74153 X 0 40 Y Y 1 F N
-F0 "X" 100 50 60 H V C CNN
-F1 "IC_74153" 100 150 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-T 0 100 -200 60 0 0 0 4:1 Normal 0 C C
-T 0 100 -100 60 0 0 0 DUAL Normal 0 C C
-T 0 100 -300 60 0 0 0 MUX Normal 0 C C
-S -200 500 350 -550 0 1 0 N
-X a0 1 -400 350 200 R 50 50 1 1 I
-X a1 2 -400 250 200 R 50 50 1 1 I
-X a2 3 -400 150 200 R 50 50 1 1 I
-X a3 4 -400 50 200 R 50 50 1 1 I
-X EA 5 0 700 200 D 50 50 1 1 I I
-X b0 6 -400 -150 200 R 50 50 1 1 I
-X b1 7 -400 -250 200 R 50 50 1 1 I
-X b2 8 -400 -350 200 R 50 50 1 1 I
-X b3 9 -400 -450 200 R 50 50 1 1 I
-X EB 10 200 700 200 D 50 50 1 1 I I
-X s1 11 50 -750 200 U 50 50 1 1 I
-X s0 12 150 -750 200 U 50 50 1 1 I
-X ya 13 550 250 200 L 50 50 1 1 O
-X yb 14 550 -300 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# IC_74154
-#
-DEF IC_74154 X 0 40 Y Y 1 F N
-F0 "X" 0 -200 60 H V C CNN
-F1 "IC_74154" 50 -50 60 H V C CNN
-F2 "" 0 50 60 H V C CNN
-F3 "" 0 50 60 H V C CNN
-DRAW
-T 0 0 400 60 0 0 0 4:16~ Normal 0 C C
-T 0 0 250 60 0 0 0 decoder Normal 0 C C
-S -350 700 400 -700 0 0 0 N
-X ~Y0 1 -550 550 200 R 50 50 1 1 O I
-X ~Y1 2 -550 450 200 R 50 50 1 1 O I
-X ~Y2 3 -550 350 200 R 50 50 1 1 O I
-X ~Y3 4 -550 250 200 R 50 50 1 1 O I
-X ~Y4 5 -550 150 200 R 50 50 1 1 O I
-X ~Y5 6 -550 50 200 R 50 50 1 1 O I
-X ~Y6 7 -550 -50 200 R 50 50 1 1 O I
-X ~Y7 8 -550 -150 200 R 50 50 1 1 O I
-X ~Y8 9 -550 -250 200 R 50 50 1 1 O I
-X ~Y9 10 -550 -350 200 R 50 50 1 1 O I
-X A3 20 600 150 200 L 50 50 1 1 I
-X ~Y10 11 -550 -450 200 R 50 50 1 1 O I
-X A2 21 600 250 200 L 50 50 1 1 I
-X GND 12 -550 -550 200 R 50 50 1 1 I
-X A1 22 600 350 200 L 50 50 1 1 I
-X ~Y11 13 600 -550 200 L 50 50 1 1 O I
-X A0 23 600 450 200 L 50 50 1 1 I
-X ~Y12 14 600 -450 200 L 50 50 1 1 O I
-X Vcc 24 600 550 200 L 50 50 1 1 I
-X ~Y13 15 600 -350 200 L 50 50 1 1 O I
-X ~Y14 16 600 -250 200 L 50 50 1 1 O I
-X ~Y15 17 600 -150 200 L 50 50 1 1 O I
-X ~E0 18 600 -50 200 L 50 50 1 1 I I
-X ~E1 19 600 50 200 L 50 50 1 1 I I
-ENDDRAW
-ENDDEF
-#
-# IC_74157
-#
-DEF IC_74157 X 0 40 Y Y 1 F N
-F0 "X" 50 -50 60 H V C CNN
-F1 "IC_74157" 50 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-T 0 50 -300 60 0 0 0 2:1 Normal 0 C C
-T 0 50 -400 60 0 0 0 MUX Normal 0 C C
-T 0 50 -200 60 0 0 0 QUAD Normal 0 C C
-S -350 550 400 -650 0 1 0 N
-X a0 1 -550 450 200 R 50 50 1 1 I
-X a1 2 -550 300 200 R 50 50 1 1 I
-X b0 3 -550 200 200 R 50 50 1 1 I
-X b1 4 -550 100 200 R 50 50 1 1 I
-X c0 5 -550 0 200 R 50 50 1 1 I
-X c1 6 -550 -100 200 R 50 50 1 1 I
-X d0 7 -550 -200 200 R 50 50 1 1 I
-X d1 8 -550 -300 200 R 50 50 1 1 I
-X EN 9 -550 -550 200 R 50 50 1 1 I I
-X S 10 -550 -450 200 R 50 50 1 1 I
-X Yd 11 600 0 200 L 50 50 1 1 O
-X Ya 12 600 300 200 L 50 50 1 1 O
-X Yb 13 600 200 200 L 50 50 1 1 O
-X Yc 14 600 100 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-# IC_7485
-#
-DEF IC_7485 X 0 40 Y Y 1 F N
-F0 "X" -50 -100 60 H V C CNN
-F1 "IC_7485" -50 50 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C
-S -350 450 400 -400 0 1 0 N
-X AB(in) 3 600 -300 200 L 50 50 1 1 I
-X A3 4 -550 100 200 R 50 50 1 1 I
-X B3 5 -550 -350 200 R 50 50 1 1 I
-X A2 6 -550 200 200 R 50 50 1 1 I
-X B2 7 -550 -250 200 R 50 50 1 1 I
-X A1 8 -550 300 200 R 50 50 1 1 I
-X B1 9 -550 -150 200 R 50 50 1 1 I
-X A0 10 -550 400 200 R 50 50 1 1 I
-X B0 11 -550 -50 200 R 50 50 1 1 I
-X A>B(out) 12 600 350 200 L 50 50 1 1 O
-X A=B(out) 13 600 250 200 L 50 50 1 1 O
-X AB)IN 10 -800 -550 200 R 50 50 1 1 I
+X (A=B)IN 11 -800 -700 200 R 50 50 1 1 I
+X (AB)OUT 13 850 -150 200 L 50 50 1 1 O
+X (A=B)OUT 14 850 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CD4066
+#
+DEF CD4066 X 0 40 Y Y 1 F N
+F0 "X" -150 450 60 H V C CNN
+F1 "CD4066" -150 -100 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -900 550 700 -150 0 1 0 N
+X SIG_A_IN/OUT 1 -1100 500 200 R 50 50 1 1 B
+X SIG_A_OUT/IN 2 -1100 400 200 R 50 50 1 1 B
+X SIG_B_OUT/IN 3 -1100 300 200 R 50 50 1 1 B
+X SIG_B_IN/OUT 4 -1100 200 200 R 50 50 1 1 B
+X CONTROL_B 5 -1100 100 200 R 50 50 1 1 I
+X CONTROL_C 6 -1100 0 200 R 50 50 1 1 I
+X VSS 7 -1100 -100 200 R 50 50 1 1 I
+X SIG_C_IN/OUT 8 900 -100 200 L 50 50 1 1 B
+X SIG_C_OUT/IN 9 900 0 200 L 50 50 1 1 B
+X SIG_D_OUT/IN 10 900 100 200 L 50 50 1 1 B
+X SIG_D_IN/OUT 11 900 200 200 L 50 50 1 1 B
+X CONTROL_D 12 900 300 200 L 50 50 1 1 I
+X CONTROL_A 13 900 400 200 L 50 50 1 1 I
+X VDD 14 900 500 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# CD4585
+#
+DEF CD4585 X 0 40 Y Y 1 F N
+F0 "X" -50 50 60 H V C CNN
+F1 "CD4585" 0 -450 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -650 650 550 -1000 0 1 0 N
+X A3 1 -850 500 200 R 50 50 1 1 I
+X B3 2 -850 100 200 R 50 50 1 1 I
+X A2 3 -850 400 200 R 50 50 1 1 I
+X B2 4 -850 -50 200 R 50 50 1 1 I
+X A1 5 -850 300 200 R 50 50 1 1 I
+X (AB)IN 8 -850 -800 200 R 50 50 1 1 I
+X B1 9 -850 -200 200 R 50 50 1 1 I
+X A0 10 -850 200 200 R 50 50 1 1 I
+X B0 11 -850 -350 200 R 50 50 1 1 I
+X (AB)OUT 14 750 -200 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# CD_4007
+#
+DEF CD_4007 X 0 40 Y Y 1 F N
+F0 "X" 50 500 60 H V C CNN
+F1 "CD_4007" 0 -700 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -650 700 700 -800 0 1 0 N
+X Q2(P)_Drain 1 -850 350 200 R 50 50 1 1 I
+X Q2(P)_Source 2 -850 200 200 R 50 50 1 1 I
+X Q3_Gate 3 -850 50 200 R 50 50 1 1 I
+X Q2(N)_Source 4 -850 -150 200 R 50 50 1 1 I
+X Q2(N)_Drain 5 -850 -300 200 R 50 50 1 1 I
+X Q1_Gate 6 -850 -450 200 R 50 50 1 1 I
+X VSS 7 -850 -600 200 R 50 50 1 1 I
+X Q1(N)_Drain 8 900 -500 200 L 50 50 1 1 I
+X Q3(N)_Source 9 900 -350 200 L 50 50 1 1 I
+X Q3_Gate 10 900 -200 200 L 50 50 1 1 I
+X Q3(P)_Drain 11 900 -50 200 L 50 50 1 1 I
+X Q3_Drain_Source 12 900 150 200 L 50 50 1 1 I
+X Q1(P)_Source 13 900 300 200 L 50 50 1 1 I
+X VDD 14 900 450 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# CMOS_NAND
+#
+DEF CMOS_NAND X 0 40 Y Y 1 F N
+F0 "X" -100 -150 60 H V C CNN
+F1 "CMOS_NAND" 0 -50 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400
+C 550 0 50 0 1 0 N
+P 2 0 1 0 -350 300 300 300 N
+P 3 0 1 0 -350 300 -350 -400 300 -400 N
+X in1 1 -550 250 200 R 50 50 1 1 I
+X in2 2 -550 -300 200 R 50 50 1 1 I
+X out 3 800 0 279 L 79 79 1 1 I
+ENDDRAW
+ENDDEF
+#
+# COMPARATOR
+#
+DEF COMPARATOR X 0 40 Y Y 1 F N
+F0 "X" 200 200 60 H V C CNN
+F1 "COMPARATOR" 250 -150 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -500 300 600 -200 0 1 0 N
+X NON_INV_INP 1 -700 200 200 R 50 50 1 1 I
+X INV_INP 2 -700 100 200 R 50 50 1 1 I
+X GND 3 -700 0 200 R 50 50 1 1 I
+X OUT 4 800 50 200 L 50 50 1 1 O
+X VCC 5 -700 -100 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# Clock_pulse_generator
+#
+DEF Clock_pulse_generator X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "Clock_pulse_generator" 0 -100 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -550 200 600 -300 0 1 0 N
+X Vdd 1 -750 100 200 R 50 50 1 1 I
+X R 2 -750 -50 200 R 50 50 1 1 I
+X C 3 -750 -200 200 R 50 50 1 1 I
+X Clkout 4 800 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# DSR_Latch
+#
+DEF DSR_Latch X 0 40 Y Y 1 F N
+F0 "X" -50 -350 60 H V C CNN
+F1 "DSR_Latch" -50 200 60 H V C CNN
+F2 "" -50 200 60 H I C CNN
+F3 "" -50 200 60 H I C CNN
+DRAW
+S -300 150 200 -300 0 1 0 N
+S 200 -300 200 -250 0 1 0 N
+X E_Bar 1 -500 100 200 R 50 50 1 1 I
+X S0_bar 2 -500 -150 200 R 50 50 1 1 I
+X D0 3 -500 -250 200 R 50 50 1 1 I
+X MR_Bar 9 -500 0 200 R 50 50 1 1 I
+X Q0 15 400 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# EXOR_S
+#
+DEF EXOR_S X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "EXOR_S" 0 0 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -550 450 500 -350 0 1 0 N
+X A 1 -750 300 200 R 50 50 1 1 I
+X B 2 -750 -100 200 R 50 50 1 1 I
+X O 3 700 50 200 L 50 50 1 1 O
+X VSS 7 0 -550 200 U 50 50 1 1 I
+X VCC 14 0 650 200 D 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# HEX
+#
+DEF HEX X 0 40 Y Y 1 F N
+F0 "X" 0 100 60 H V C CNN
+F1 "HEX" 0 -50 60 H V C CNN
+F2 "" 0 -50 60 H I C CNN
+F3 "" 0 -50 60 H I C CNN
+DRAW
+S -250 150 250 -200 0 1 0 N
+S 250 -200 250 -200 0 1 0 N
+X A 1 -450 0 200 R 50 50 1 1 I
+X Y 2 450 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC733
+#
+DEF IC733 X 0 40 Y Y 1 F N
+F0 "X" -150 -800 60 H V C CNN
+F1 "IC733" -150 400 60 H V C CNN
+F2 "" 0 450 60 H I C CNN
+F3 "" 0 450 60 H I C CNN
+DRAW
+S -450 350 150 -750 0 1 0 N
+X IN2 1 -650 250 200 R 50 50 1 1 I
+X NC 2 -650 100 200 R 50 50 1 1 I
+X G2B 3 -650 -50 200 R 50 50 1 1 I
+X G1B 4 -650 -200 200 R 50 50 1 1 I
+X V- 5 -650 -350 200 R 50 50 1 1 I
+X NC 6 -650 -500 200 R 50 50 1 1 I
+X OUT2 7 -650 -650 200 R 50 50 1 1 O
+X OUT1 8 350 -650 200 L 50 50 1 1 O
+X NC 9 350 -500 200 L 50 50 1 1 I
+X V+ 10 350 -350 200 L 50 50 1 1 I
+X G1A 11 350 -200 200 L 50 50 1 1 I
+X G2A 12 350 -50 200 L 50 50 1 1 I
+X NC 13 350 100 200 L 50 50 1 1 I
+X IN1 14 350 250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# ICL7611
+#
+DEF ICL7611 X 0 40 Y Y 1 F N
+F0 "X" 0 -50 60 H V C CNN
+F1 "ICL7611" 0 -350 60 H V C CNN
+F2 "" 0 -50 60 H I C CNN
+F3 "" 0 -50 60 H I C CNN
+DRAW
+S -300 100 -300 100 0 1 0 N
+S -250 250 250 -300 0 1 0 N
+S 250 -250 250 -250 0 1 0 N
+X BAL 1 -450 200 200 R 50 50 1 1 I
+X -IN 2 -450 50 200 R 50 50 1 1 I
+X +IN 3 -450 -100 200 R 50 50 1 1 I
+X V- 4 -450 -250 200 R 50 50 1 1 I
+X BAL 5 450 -250 200 L 50 50 1 1 I
+X OUT 6 450 -100 200 L 50 50 1 1 O
+X V+ 7 450 50 200 L 50 50 1 1 I
+X Iq_SET 8 450 200 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# ICL8212
+#
+DEF ICL8212 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "ICL8212" 0 -350 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -450 450 500 -500 0 1 0 N
+X HYST 2 -650 250 200 R 50 50 1 1 O
+X THRES 3 -650 0 200 R 50 50 1 1 I
+X OUT 4 -650 -200 200 R 50 50 1 1 O
+X GND 5 700 -100 200 L 50 50 1 1 I
+X V+ 8 700 150 200 L 50 50 1 1 I
+# HCF4066
+#
+DEF HCF4066 X 0 40 Y Y 1 F N
+F0 "X" -150 450 60 H V C CNN
+F1 "HCF4066" -150 -100 60 H V C CNN
+F2 "" 0 0 60 H I C CNN
+F3 "" 0 0 60 H I C CNN
+DRAW
+S -900 550 700 -150 0 1 0 N
+X SIG_A_IN/OUT 1 -1100 500 200 R 50 50 1 1 B
+X SIG_A_OUT/IN 2 -1100 400 200 R 50 50 1 1 B
+X SIG_B_OUT/IN 3 -1100 300 200 R 50 50 1 1 B
+X SIG_B_IN/OUT 4 -1100 200 200 R 50 50 1 1 B
+X CONTROL_B 5 -1100 100 200 R 50 50 1 1 I
+X CONTROL_C 6 -1100 0 200 R 50 50 1 1 I
+X VSS 7 -1100 -100 200 R 50 50 1 1 I
+X SIG_C_IN/OUT 8 900 -100 200 L 50 50 1 1 B
+X SIG_C_OUT/IN 9 900 0 200 L 50 50 1 1 B
+X SIG_D_OUT/IN 10 900 100 200 L 50 50 1 1 B
+X SIG_D_IN/OUT 11 900 200 200 L 50 50 1 1 B
+X CONTROL_D 12 900 300 200 L 50 50 1 1 I
+X CONTROL_A 13 900 400 200 L 50 50 1 1 I
+X VDD 14 900 500 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4002
+#
+DEF IC_4002 X 0 40 Y Y 1 F N
+F0 "X" 0 150 60 H V C CNN
+F1 "IC_4002" 0 0 60 H V C CNN
+F2 "" 50 -150 60 H V C CNN
+F3 "" 50 -150 60 H V C CNN
+DRAW
+S -250 350 250 -400 0 1 0 N
+X 1Y 1 -450 250 200 R 50 50 1 1 O
+X 1A 2 -450 150 200 R 50 50 1 1 I
+X 1B 3 -450 50 200 R 50 50 1 1 I
+X 1C 4 -450 -50 200 R 50 50 1 1 I
+X 1D 5 -450 -150 200 R 50 50 1 1 I
+X NC 6 -450 -250 200 R 50 50 1 1 I
+X GND 7 -450 -350 200 R 50 50 1 1 I
+X NC 8 450 -350 200 L 50 50 1 1 I
+X 2A 9 450 -250 200 L 50 50 1 1 I
+X 2B 10 450 -150 200 L 50 50 1 1 I
+X 2C 11 450 -50 200 L 50 50 1 1 I
+X 2D 12 450 50 200 L 50 50 1 1 I
+X 2Y 13 450 150 200 L 50 50 1 1 O
+X VCC 14 450 250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4012
+#
+DEF IC_4012 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "IC_4012" 0 200 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 350 -400 0 1 0 N
+X Q1 1 -500 300 200 R 50 50 1 1 O
+X A1 2 -500 200 200 R 50 50 1 1 I
+X B1 3 -500 100 200 R 50 50 1 1 I
+X C1 4 -500 0 200 R 50 50 1 1 I
+X D1 5 -500 -100 200 R 50 50 1 1 I
+X NC 6 -500 -200 200 R 50 50 1 1 N
+X VSS 7 -500 -300 200 R 50 50 1 1 I
+X NC 8 550 -300 200 L 50 50 1 1 N
+X A2 9 550 -200 200 L 50 50 1 1 I
+X B2 10 550 -100 200 L 50 50 1 1 I
+X C2 11 550 0 200 L 50 50 1 1 I
+X D2 12 550 100 200 L 50 50 1 1 I
+X Q2 13 550 200 200 L 50 50 1 1 O
+X VDD 14 550 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4017
+#
+DEF IC_4017 X 0 40 Y Y 1 F N
+F0 "X" 0 0 60 H V C CNN
+F1 "IC_4017" 0 0 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 850 400 -850 0 1 0 N
+X 1 1 600 650 200 L 50 50 1 1 O
+X 2 2 600 500 200 L 50 50 1 1 O
+X 3 3 600 350 200 L 50 50 1 1 O
+X 4 4 600 200 200 L 50 50 1 1 O
+X 5 5 600 50 200 L 50 50 1 1 O
+X 6 6 600 -100 200 L 50 50 1 1 O
+X 7 7 600 -250 200 L 50 50 1 1 O
+X 8 8 600 -400 200 L 50 50 1 1 O
+X 9 9 600 -600 200 L 50 50 1 1 O
+X 10 10 600 -750 200 L 50 50 1 1 O
+X RST 11 -550 -400 200 R 50 50 1 1 I
+X CLK 12 -550 350 200 R 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4023
+#
+DEF IC_4023 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4023" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X C3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X A3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_4028
+#
+DEF IC_4028 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4028" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X Q4 1 -500 350 200 R 50 50 1 1 O
+X Q2 2 -500 250 200 R 50 50 1 1 O
+X Q0 3 -500 150 200 R 50 50 1 1 O
+X Q7 4 -500 50 200 R 50 50 1 1 O
+X Q9 5 -500 -50 200 R 50 50 1 1 O
+X Q5 6 -500 -150 200 R 50 50 1 1 O
+X Q6 7 -500 -250 200 R 50 50 1 1 O
+X Vss 8 -500 -350 200 R 50 50 1 1 I
+X Q8 9 500 -350 200 L 50 50 1 1 O
+X A0 10 500 -250 200 L 50 50 1 1 I
+X A3 11 500 -150 200 L 50 50 1 1 I
+X A2 12 500 -50 200 L 50 50 1 1 I
+X A1 13 500 50 200 L 50 50 1 1 I
+X Q1 14 500 150 200 L 50 50 1 1 O
+X Q3 15 500 250 200 L 50 50 1 1 O
+X Vdd 16 500 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_4073
+#
+DEF IC_4073 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "IC_4073" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 400 300 -400 0 1 0 N
+X A1 1 -500 300 200 R 50 50 1 1 I
+X B1 2 -500 200 200 R 50 50 1 1 I
+X A2 3 -500 100 200 R 50 50 1 1 I
+X B2 4 -500 0 200 R 50 50 1 1 I
+X C2 5 -500 -100 200 R 50 50 1 1 I
+X Q2 6 -500 -200 200 R 50 50 1 1 O
+X Vss 7 -500 -300 200 R 50 50 1 1 I
+X C1 8 500 -300 200 L 50 50 1 1 I
+X Q1 9 500 -200 200 L 50 50 1 1 O
+X Q3 10 500 -100 200 L 50 50 1 1 O
+X A3 11 500 0 200 L 50 50 1 1 I
+X B3 12 500 100 200 L 50 50 1 1 I
+X C3 13 500 200 200 L 50 50 1 1 I
+X Vdd 14 500 300 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# IC_74153
+#
+DEF IC_74153 X 0 40 Y Y 1 F N
+F0 "X" 100 50 60 H V C CNN
+F1 "IC_74153" 100 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 100 -200 60 0 0 0 4:1 Normal 0 C C
+T 0 100 -100 60 0 0 0 DUAL Normal 0 C C
+T 0 100 -300 60 0 0 0 MUX Normal 0 C C
+S -200 500 350 -550 0 1 0 N
+X a0 1 -400 350 200 R 50 50 1 1 I
+X a1 2 -400 250 200 R 50 50 1 1 I
+X a2 3 -400 150 200 R 50 50 1 1 I
+X a3 4 -400 50 200 R 50 50 1 1 I
+X EA 5 0 700 200 D 50 50 1 1 I I
+X b0 6 -400 -150 200 R 50 50 1 1 I
+X b1 7 -400 -250 200 R 50 50 1 1 I
+X b2 8 -400 -350 200 R 50 50 1 1 I
+X b3 9 -400 -450 200 R 50 50 1 1 I
+X EB 10 200 700 200 D 50 50 1 1 I I
+X s1 11 50 -750 200 U 50 50 1 1 I
+X s0 12 150 -750 200 U 50 50 1 1 I
+X ya 13 550 250 200 L 50 50 1 1 O
+X yb 14 550 -300 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_74154
+#
+DEF IC_74154 X 0 40 Y Y 1 F N
+F0 "X" 0 -200 60 H V C CNN
+F1 "IC_74154" 50 -50 60 H V C CNN
+F2 "" 0 50 60 H V C CNN
+F3 "" 0 50 60 H V C CNN
+DRAW
+T 0 0 400 60 0 0 0 4:16~ Normal 0 C C
+T 0 0 250 60 0 0 0 decoder Normal 0 C C
+S -350 700 400 -700 0 0 0 N
+X ~Y0 1 -550 550 200 R 50 50 1 1 O I
+X ~Y1 2 -550 450 200 R 50 50 1 1 O I
+X ~Y2 3 -550 350 200 R 50 50 1 1 O I
+X ~Y3 4 -550 250 200 R 50 50 1 1 O I
+X ~Y4 5 -550 150 200 R 50 50 1 1 O I
+X ~Y5 6 -550 50 200 R 50 50 1 1 O I
+X ~Y6 7 -550 -50 200 R 50 50 1 1 O I
+X ~Y7 8 -550 -150 200 R 50 50 1 1 O I
+X ~Y8 9 -550 -250 200 R 50 50 1 1 O I
+X ~Y9 10 -550 -350 200 R 50 50 1 1 O I
+X A3 20 600 150 200 L 50 50 1 1 I
+X ~Y10 11 -550 -450 200 R 50 50 1 1 O I
+X A2 21 600 250 200 L 50 50 1 1 I
+X GND 12 -550 -550 200 R 50 50 1 1 I
+X A1 22 600 350 200 L 50 50 1 1 I
+X ~Y11 13 600 -550 200 L 50 50 1 1 O I
+X A0 23 600 450 200 L 50 50 1 1 I
+X ~Y12 14 600 -450 200 L 50 50 1 1 O I
+X Vcc 24 600 550 200 L 50 50 1 1 I
+X ~Y13 15 600 -350 200 L 50 50 1 1 O I
+X ~Y14 16 600 -250 200 L 50 50 1 1 O I
+X ~Y15 17 600 -150 200 L 50 50 1 1 O I
+X ~E0 18 600 -50 200 L 50 50 1 1 I I
+X ~E1 19 600 50 200 L 50 50 1 1 I I
+ENDDRAW
+ENDDEF
+#
+# IC_74157
+#
+DEF IC_74157 X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "IC_74157" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 50 -300 60 0 0 0 2:1 Normal 0 C C
+T 0 50 -400 60 0 0 0 MUX Normal 0 C C
+T 0 50 -200 60 0 0 0 QUAD Normal 0 C C
+S -350 550 400 -650 0 1 0 N
+X a0 1 -550 450 200 R 50 50 1 1 I
+X a1 2 -550 300 200 R 50 50 1 1 I
+X b0 3 -550 200 200 R 50 50 1 1 I
+X b1 4 -550 100 200 R 50 50 1 1 I
+X c0 5 -550 0 200 R 50 50 1 1 I
+X c1 6 -550 -100 200 R 50 50 1 1 I
+X d0 7 -550 -200 200 R 50 50 1 1 I
+X d1 8 -550 -300 200 R 50 50 1 1 I
+X EN 9 -550 -550 200 R 50 50 1 1 I I
+X S 10 -550 -450 200 R 50 50 1 1 I
+X Yd 11 600 0 200 L 50 50 1 1 O
+X Ya 12 600 300 200 L 50 50 1 1 O
+X Yb 13 600 200 200 L 50 50 1 1 O
+X Yc 14 600 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# IC_7485
+#
+DEF IC_7485 X 0 40 Y Y 1 F N
+F0 "X" -50 -100 60 H V C CNN
+F1 "IC_7485" -50 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C
+S -350 450 400 -400 0 1 0 N
+X AB(in) 3 600 -300 200 L 50 50 1 1 I
+X A3 4 -550 100 200 R 50 50 1 1 I
+X B3 5 -550 -350 200 R 50 50 1 1 I
+X A2 6 -550 200 200 R 50 50 1 1 I
+X B2 7 -550 -250 200 R 50 50 1 1 I
+X A1 8 -550 300 200 R 50 50 1 1 I
+X B1 9 -550 -150 200 R 50 50 1 1 I
+X A0 10 -550 400 200 R 50 50 1 1 I
+X B0 11 -550 -50 200 R 50 50 1 1 I
+X A>B(out) 12 600 350 200 L 50 50 1 1 O
+X A=B(out) 13 600 250 200 L 50 50 1 1 O
+X A