When running top.v in the passthrough test on the Cmod-S7-25 and Pmod-I2S2 module, the left channel from the ADC is output on the right channel of the DAC and vice versa. This appears to be an issue in axis_i2s2.v and not the other files. At the signal level everything looks good in the source file with regards to the LRCK signal for both the tx and rx.
When running
top.vin the passthrough test on the Cmod-S7-25 and Pmod-I2S2 module, the left channel from the ADC is output on the right channel of the DAC and vice versa. This appears to be an issue inaxis_i2s2.vand not the other files. At the signal level everything looks good in the source file with regards to theLRCKsignal for both the tx and rx.